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  • FPGA Design With Verilog

    Transféré par

    machnik1486624
    143 vues2 pages
    This document discusses FPGA design using Verilog. It covers FPGA architecture and design flow, including concepts like lookup tables and CLBs. It also discusses designing with Verilog HDL, including modules, data types, gates, and behavioral/structural modeling. Additionally, it addresses RTL design using Verilog, including finite state machines and asynchronous state machines. Finally, it describes a lab session that involves simulating and synthesizing a serial transmitter design and pedestrian crossing control project using Verilog.

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    FPGA DESIGN WITH VERILOG

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    This document discusses FPGA design using Verilog. It covers FPGA architecture and design flow, including concepts like lookup tables and CLBs. It also discusses designing with Verilog HDL, including modules, data types, gates, and behavioral/structural modeling. Additionally, it addresses RTL design using Verilog, including finite state machines and asynchronous state machines. Finally, it describes a lab session that involves simulating and synthesizing a serial transmitter design and pedestrian crossing control project using Verilog.

    Droits d'auteur :

    © All Rights Reserved
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    143 vues2 pages

    FPGA Design With Verilog

    Transféré par

    machnik1486624
    This document discusses FPGA design using Verilog. It covers FPGA architecture and design flow, including concepts like lookup tables and CLBs. It also discusses designing with Verilog HDL, including modules, data types, gates, and behavioral/structural modeling. Additionally, it addresses RTL design using Verilog, including finite state machines and asynchronous state machines. Finally, it describes a lab session that involves simulating and synthesizing a serial transmitter design and pedestrian crossing control project using Verilog.

    Droits d'auteur :

    © All Rights Reserved
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 2

    FPGA Design with Verilog

    a) FPGA Architecture and Design flow

    Concept of programmable hardware


    Difference between FPGA and CPLD
    Architecture of FPGA
    Look up table concept
    Programmable routing
    CLBs
    Input/output blocks
    Xilinx XC4000/Spartan architecture
    Application of FPGA
    FPGA design flow Xilinx(ISE)
    Design capture
    Synthesis/STA
    Timing constraints/ Pin constraints
    How to fix timing issues
    Care about for clocks
    Drive strengths/IO
    Report analysis
    Place and route
    Bit map generation
    Bitmap download methods

    b) Designing using Verilog-HDL

    The module
    Nets and Networks of modules
    Basic Data Types
    Primitive Gates Specifying Time Delays
    The Continuous Assignment Statement
    Operators and Expressions
    Data flow modelling
    Structural modelling
    Behavioural Descriptions -The Sequential Block
    Describing Combinational Logic
    Describing Sequential Logic
    Design Verification using Test-fixtures

    c) RTL level design using verilog

    FSM
    ASM
    RTL Level Design for Serial Transmitter Using verilog-HDL

    d) Lab Session

    Simulation
    Simulation of serial transmitter and analysing wave forms

    Project
    Concepts of Pedestrian crossing control
    Designing of Pedestrian crossing control using verilog HDL
    Simulation of Pedestrian crossing control
    Synthesis of Pedestrian crossing control

    Pre-Requisites:

    Digital Design concepts


    Basic Concepts of C programming

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