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Compte rendu TP n 1

VHDL

Elabor par :

HOSNI Anis
&
LAHMER Ibrahim

Classe :
2 GEC 3
2014/2015

Application 1
1) Lentit et larchitecture de type flot de donne de la porte AND_2 (porte AND 2
entres).
library ieee ;
use ieee.std_logic_1164.all
entity AND_2 is
port (a, b : in std_logic ;
s : out std_logic ) ;
end ;
architecture flot of AND_2 is
begin
s<=a and b ;
end ;

Table de vrit de la porte AND deux entres


a

2) Lentit et larchitecture de type flot de donne de la porte NXOR_3 (porte NXOR 3


entres).
library ieee ;
use ieee.std_logic_1164.all
entity NXOR_3 is
port (a, b, c : in std_logic ;
s : out std_logic ) ;
end ;

architecture flot of NXOR_3 is


begin
s<= not(a xor b xor c);
end ;

Table de vrit de la porte NXOR trois entres


a

0
1

1
0

1
0

1
0

1
1

1
1

0
1

1
0

3) Lentit et larchitecture de type flot de donne de la porte NAND_2 (porte NAND 2


entres).
library ieee ;
use ieee.std_logic_1164.all
entity NAND_2 is
port (a, b : in std_logic ;
s : out std_logic ) ;
end ;
architecture flot of NAND_2 is
begin
s<= not(a and b) ;
end ;

Table de vrit de la porte NAND deux entres


a

4) Lentit et larchitecture de type flot de donne de la porte NOR_3 (porte NOR 3


entres).
library ieee ;
use ieee.std_logic_1164.all
entity NOR_3 is
port (a, b, c : in std_logic ;
s : out std_logic ) ;
end ;
architecture flot of NOR_3 is
begin
s<= not(a or b or b) ;
end ;

Table de vrit de la porte NOR trois entres


a

0
1

1
0

1
0

1
1

1
1

1
1

0
1

1
0

5) Description structurelle de ladditionneur complet


library ieee ;
use ieee.std_logic_1164.all
entity Adder is
port (x, y, cin : in std_logic ;
sum, cout : out std_logic ) ;
end ;
architecture structurelle of NOR_3 is
component AND_2
port (a, b : in std_logic ;
s : out std_logic) ;
end component ;
component NAND_2
port (a, b : in std_logic ;
s : out std_logic) ;
end component ;
component NOR_3
port (a, b, c : in std_logic ;
s : out std_logic) ;
end component ;
component NXOR_3
port (a, b, c : in std_logic ;
s : out std_logic) ;
end component ;
signal n1, n2, n3, n4, n5 : std_logic ;

begin
U1 : NXOR_3 port map (x, y, cin, n1) ;
U2 : AND_2 port map (x, y, n2) ;
U3 : AND_2 port map (x, cin, n3) ;
U4 : AND_2 port map (y, cin, n4) ;
U5 : NAND_2 port map (n1, n1, sum) ;
U6 : NOR_3 port map (n2, n3, n4, n5) ;
U7 : NAND_2 port map (n5, n5, cout) ;
end ;

Table de vrit de ladditionneur complet.


x
0
0
0
0
1
1
1
1

y cin sum cout


0 0
0
0
0 1
1
0
1 0
1
0
1 1
0
1
0 0
1
0
0 1
0
1
1 0
0
1
1 1
1
1

Application 2
1) Lentit (adder4bits) et larchitecture (arch_adder4b) dun additionneur 4 bits en
rutilisant le composant additionneur dcrit en exercice 1.
library ieee;
use ieee.std_logic_1164.all;
entity adder4bits is
port(cin:in std_logic;
a,b: in std_logic_vector(3 downto 0);
s: out std_logic_vector (3 downto 0);
cout:out std_logic);
end;

architecture arch_adder4b of adder4bits is


component Adder
port(x,y,cin:in std_logic;
sum,cout:out std_logic);
end component;
signal ci1,ci2,ci3:std_logic;
begin
u1:Adder port map(a(0),b(0),cin,s(0),ci1);
u2:Adder port map(a(1),b(1),ci1,s(1),ci2);
u3: Adder port map (a(2),b(2),ci2,s(2),ci3);
u4:Adder port map(a(3),b(3),ci3,s(3),cout);
end;
2) Lentit (ouexclusif) et larchitecture (arch_ouex).
library ieee;
use ieee.std_logic_1164.all;
entity ouexclusif is
port(a: in std_logic_vector(3 downto 0);
c:in std_logic;
s:out std_logic_vector(3 downto 0));
end;
architecture arch_ouex of ouexclusif is
begin
s(0)<=a(0) xor c;
s(1)<=a(1) xor c;
s(2)<=a(2) xor c;
s(3)<=a(3) xor c;
end;

3) La description VHDL structurelle de ladditionneur/soustracteur.


library ieee;
use ieee.std_logic_1164.all;
entity add_sous is
port(a,b: in std_logic_vector(3 downto 0);
as:in std_logic;
s:out std_logic_vector(3 downto 0);
carry : out std_logic);
end;
architecture structurelle of add_sous is
component adder4bits
port( a,b: in std_logic_vector(3 downto 0);
cin:in std_logic;
s: out std_logic_vector (3 downto 0);
cout:out std_logic);
end component;
component ouexclusif
port(a: in std_logic_vector(3 downto 0);
c:in std_logic;
s:out std_logic_vector(3 downto 0));
end component;

signal n:std_logic_vector(3 downto 0);


begin
u1:xor4 port map(a(3 downto 0),as,n(3 downto 0));
u2:add4 port map(n(3 downto 0),b(3 downto 0),as,s(3 downto 0),carry);
end;
4) Le test bench de ladditionneur/soustractur.
library ieee;
use ieee.std_logic_1164.all;
entity circuittest is
end;
architecture test of circuittest is
component add_sous
port(a,b: in std_logic_vector(3 downto 0);
as:in std_logic;
s:out std_logic_vector(3 downto 0);
carry : out std_logic);
end component;
signal e1,e2:std_logic_vector(3 downto 0):="0000";
signal e3: std_logic:='0';
signal s1:std_logic_vector(3 downto 0);
signal s2:std_logic;
begin
u1: add_sous port map(e1,e2,e3,s1,s2);
e1(0)<= not e1(0) after 10 ns;
e1(1)<= not e1(1) after 20 ns;
e1(2)<= not e1(2) after 40 ns;
e1(3)<= not e1(3) after 80 ns;
e2(0)<= not e2(0) after 160 ns;
e2(1)<= not e2(1) after 320 ns;
e2(2)<= not e2(2) after 640 ns;
e2(3)<= not e2(3) after 1280 ns;

process
begin
wait for 1280 ns;
end process;
end;

Simulation du test.