Lab 7: Introduction to Behavioral

Verilog and Logic Sythesis

Kevin Bradshaw
ECEN 248: Introduction to Digital Design, Section 302
TA: Daniel Mcbride
Due date: July 22, 2014

Objectives:
The purpose of this lab is to learn behavioral Verilog coding in order to test larger circuits in an
efficient manner. In the last lab, basic Verilog coding was done with gate-level modules and
dataflow. Using behavioral Verilog, a higher level of abstraction, codes for more complicated
circuits can be done much easier than describing every single gate-level module. This helps
students learn how to use the building blocks of circuit design in larger, more intricate designs.

Design
Using the information given in the Pre-Lab and background section of the manual, the circuits
were written in Verilog in ISE Design Suite. The source code for experiments one, two, and
three are attached to this document.
The first source code implements behavioral modeling of a 1-bit wide, 2:1 MUX. This
design introduces the students on higher level abstractions with one of the two types of
procedure statements.
The second source code implements behavioral modeling of a 4-bit wide, MUX. This
design also uses the same type of procedure statement as before.
The third source code implements behavioral modeling of a 4-bit wide, 4:1 MUX. The
previous two designs used if and else statements where in this design, cases are used to
simulate the different bits for the output ports.
The fourth source code implements behavioral modeling of a 2:4 decoder, using the same
variable (in this case, bits) switching as the third design with case statements.
The fifth source code implements behavioral modeling of a 4:2 encoder that triggers
whenever the input changes. It also uses a statement to cover the default cases that
weren't listed.
The sixth source code implements behavioral modeling of a priority encoder, using some
of the same coding concepts as in the fifth source code for the 4:2 encoder, but instead
this time also includes don't cares for the left side of the truth table.

Results
Experiment 1
All Verilog codes compiled and
ran successfully. Figure 1 shows
the waveform of the first source
code.
Figure 1:
1-bit wide,
2:1 MUX

Figure 2 shows the waveform for part 2, higher level techniques learned in this lab, used to build
a complex MUX with less code than before.
Figure 2:
4-bit MUX

The third part of experiment one shows the first introduction to case switching between a
variable. In this design, variable S is switched when any one of the inputs is changed. Figure 3
shows the waveform for this design.
Figure 3:
4-bit wide,
4:1 MUX

Experiment 2
The results of experiment 2 shows how using higher level abstraction, the same variable
switching methods can be used with circuits that incorporate more bits in the inputs and outputs.
shows a decoder can be built by using a selection based on a variable, W, that uses 4-bit binary
values. Using if statement, all outputs can also be disabled. Figure 4 shows the waveform for this
decoder. Figure 4 shows the waveform of the decoder.
Figure 4:
2:4 Decoder

The second part of experiment 2 shows how a 4:2 encoder can be simulated using the selection
as a single variable, W, which has 4-bit binary values and covers the cases that aren't listed in the
corresponding truth table. Figure 5 shows the waveform for this encoder.
Figure 5:
2:4 Decoder

The third part of experiment 2 implements a priority encoder, which outputs the currently active
highest input. The selection is again based on a variable, W, that also includes both the don't
cares on the left side and the right side of its corresponding truth table. Figure 6 shows the
waveform for the priority encoder.
Figure 6:
Priority Encoder

Experiment 3
The first circuit to be synthesized on the FPGA was the 2:4 decoder. To test the circuit, there was
three switches and four LEDs that represented binary values. Table 1 shows the truth table for
the circuit. Every 'one' under a column for the LEDs represents that it was switched on. A 'zero'
represents that the LED was switched off.
Table 1: 2:4 Decoder Truth Table

SW2

SW1

SW0

LED3

LED2

LED1

LED0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
1

0
0
0
0
0
0
1
0

0
0
0
0
0
1
0
0

0
0
0
0
1
0
0
0

The second circuit synthesized on the FPGA was the 4:2 encoder. To test the circuit, there were
four push-buttons in a circle labeled North, East, South, and West. There was also four LEDs as
before. Table 2 shows the truth table for the binary representation of the values tested. When two
buttons were pressed simultaneously, none of the lights switched on.
Table 2: 4:2 Encoder Truth Table
North
0
1
0
0
0

West
0
0
1
0
0

South
0
0
0
1
0

East
0
0
0
0
1

LED2
1
0
0
0
0

LED1
0
0
1
1
0

LED0
0
0
1
0
1

The third circuit synthesized on the FPGA was the priority encoder. It was tested the same way
as the 4:2 encoder and the results are were the same. The only difference was that when two
buttons were pushed simultaneously, instead of no lights switching on, the highest priority would
switch on. Whichever button was connected to the higher priority input, the corresponding LED
would switch on.

Post-Lab Questions
1. Provide a comparison between behavioral Verilog used in this weeks lab and the structural
and dataflow Verilog used in last weeks lab. What might be the advantages and disadvantages
of each.
Using a higher level abstraction of Verilog this week was much easier and convenient than it was
using dataflow or structural. The advantage of using behavioral Verilog is that it uses case
statements that can be triggered to change when a particular input changes. This can be done for
a variety of number of bits used. The disadvantage is that with higher level abstraction comes
less interaction with the smaller parts of the circuit that can be manipulated to do a variety of
many things. By using both methods, complex circuits can be designed and synthesized in a
matter of minutes.
2. Compare the process of bread-boarding digital circuit to implementing a digital circuit on an
FPGA. State some advantages and disadvantages of each. Which process do you prefer?
The two main processes of implementing a specific digital circuit are vastly different. When
bread-boarding a circuit, it's mainly first drawing a schematic, building the design, testing and
debugging. This process can take a good amount of time, especially when it comes to larger
designs. The process for implementing an FPGA is designing a circuit first, then coding the
design, testing and debugging, synthesizing, then testing the circuit if it works properly to its

specified operation. The disadvantage to the FPGA that it's a limited board. Using a bread-board,
there is no limit to what is designed, only the space on which it is designed. I prefer the breadboarding technique because the exact design of a circuit on a board is always more reliable and
faster than the software implementation of an FPGA.

Conclusion
In this lab, all the source codes worked properly to show how using higher level abstraction
when possible is efficient for writing in Verilog. By testing the code into a FPGA, I was able to
demonstrate how to completely move through the engineering design process. By understanding
behavioral Verilog, I can now use these concepts on circuits that use variable triggered switches.
The results I obtained helped me better understand how multiplexors, decoders, and encoders
function.

Student Feedback
1. What did you like most about the lab assignment and why? What did you like least about it
and why?
I liked this lab because we were able to use higher level abstraction in order to complete six
different circuits! I didn't like that we didn't get to test every circuit on the FPGA.
2. Were there any sections of the lab manual that were unclear?
The lab manual could have been more in depth in the comments for students to better understand
what statements were exactly doing in the code.
3. What suggestions do you have to improve the overall lab assignment?
To improve the lab assignment, there should be more instruction on how to debug the Verilog
code.