Lab 11: A Simple Digital

Combinational Lock
Kevin Bradshaw
ECEN 248: Introduction to Digital Design, Section 302
TA: Daniel Mcbride
Due date: August 11th, 2014

Objectives:
The purpose of this lab is to learn more about sequential logic circuits using Verilog. The binary
counter is introduced using some of the combinational components as previous labs and some
new behavioral logic techniques. Since these designs are used easily in practice, they were tested
on the FPGA boards to ensure that the students understood the validity of the circuits.

Design
Using the information given in the Pre-Lab and background section of the manual, the circuits
were written in Verilog in ISE Design Suite. The source code for experiments one and two are
attached to this document.
The first source code implements a Clock Divider using behavioral Verilog to introduce
the concept of clock frequency division.
The second source code implements a Half Adder, again using structural Verilog and
built-in gate level primitives. This adder is used in the Up Counter source code.
The third source code implements a 4-bit binary Up Counter that uses a D Flip-Flop for
every Half Adder instantiated.
The fourth source code implements a Top Level code, this time, wiring up all
synchronous components together. The Count signal from the Clock Divider circuit was
changed to 26 bits wide.
The fifth source code implements a User Constraint File (UCF) for the Top Level code.
It's used to connect the ports of the design to the pins of the FPGA. It contains
information on the switches, push-buttons LEDs, and the clock period.
The sixth and seventh source codes are for a Switch Bounce and its corresponding UCF.
It was written in order to compare electrical chatter on the oscilloscope on a synchronous
circuit. It's compared with a code named noDebounce and withDebounce to observe the
differences between electrical chatter on a clock driven circuit.

Results
Experiment 1
All Verilog codes compiled and ran
successfully. Figure 1 shows the waveforms
seen on the Logic Analyzer for the Clock
Divider circuit. Count can be seen counting
upwards. Table 1 shows the measured
periods of the clock signals and the
frequency the clock is running on.
Figure 1:
Logic
Analyzer,
Waveforms

Table 1: Logic Analyzer, Clock Periods

Frequency of Clock
Count 1
Count 2
Count 3
Count 4

12.5 MHz
80 ns
160 ns
320 ns
640 ns

Experiment 2
This experiment used a 4-bit binary Up Counter and Half Adders illustrated in Figure 2. The
frequency the Clk signal produces in the test bench code is 200 MHz, because it has a period of 5
nanoseconds. The reset holds an interval of 20 nanoseconds and the enable stays at LOW for 20
nanoseconds also. The maximum count value is the same as the frequency and it rolls over
whenever Carry3 is enabled.
Figure 2: 4-bit Binary Up-Counter

In the top level source code, the rate that the most significant bit of the divider will oscillate at 50
MHz divided by 2^26, which is about 0.75 Hz. Once the code is loaded onto the FPGA, the
LEDs switch at a rate corresponding to which switches are turned on. They follow the rates in
Tabled 2 and are listed corresponding for 0 being the slowest and 3 being the fastest. The lights
count in the order shown in Table 3. The LEDs in Table 3 are ON if they have a 1 and OFF if
they have a 0.
Table 2: Count Speed
SW1
SW0
Rate
1
1
0
0
1
1
1
0
2
0
0
3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

LED4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0

Table 3: LED Count

LED3
LED2
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0

LED1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

LED0
1
1
1
1
1
1
1
1
0

Experiment 3
The third experiment compares electrical chatter between different codes for a synchronous
circuit. Figures 3 and 4 show different observations of the electrical chatter waveforms captured
from the oscilloscope.
Figure 3: Electrical Chatter Image
Figure 4: Electrical Chatter Image

The designs work as intended because the first shows chatter and then the following code
doesn't. Comments are added to the withDebounce Verilog code used. When it was tested, it was
shown to count all the way up and rolling over with no chatter.

Post-Lab Questions
All source codes are included with this lab report, including UCFs modified or written. All
questions throughout the lab manual are answered throughout the results section.

Conclusion
In this lab, all the source codes worked properly showing how higher level abstraction to
manipulate modules designed by the student can be instantiated together to build memory
storage units. By testing the code with the Logic Analyzer, I was able to learn how clock
frequencies are used in different kinds of synchronous circuits. Also, by using the Oscilloscope
and the FPGA, I learned about how electrical chatter, even if very minimal, can affect the count
of a circuit if it's fully synchronous or not. By following the lab procedure, I was able fully
implement and test all the designs that I created and was given.

Student Feedback
1. What did you like most about the lab assignment and why? What did you like least about it
and why?
I liked this lab because I learned how to use clock division techniques to drive a circuit. I liked
least about this lab that the Logic Analyzer wasn't used more throughout the rest of the
experiments.
2. Were there any sections of the lab manual that were unclear?
The section on electrical chatter could have been more in depth.
3. What suggestions do you have to improve the overall lab assignment?
To improve the lab assignment, there should be more descriptions on what each test does.