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Chapter 1 Introduction (5/02/04)

Page 1.0-1

CHAPTER 1 INTRODUCTION AND BACKGROUND


Chapter Outline
1.1 Analog Integrated Circuit Design
1.2 Technology Impact on Analog IC Design
1.3 Analog Signal Processing
1.4 Notation, Symbology and Terminology
1.5 Summary
Objectives
The objective of this course is to teach analog integrated circuit design using todays
technologies and in particular, CMOS technology.
Approach
1. Develop a firm background on technology and modeling
2. Present analog integrated circuits in a hierarchical, bottom-up manner
3. Emphasize understanding and concept over analytical methods (simple models)
4. Illustrate the correct usage of the simulator in design
5. Develop design procedures that permit the novice to design complex analog circuits
(these procedures will be modified with experience)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Introduction (5/02/04)

Page 1.0-2

Organization (Second Edition of CMOS Analog IC Design)


Chapter 9
Switched Capacitor Circuits

Chapter 10
D/A and A/D
Converters

Systems

Chapter 6
Simple CMOS &
BiCMOS OTA's

Chapter 7
High Performance
OTA's

Chapter 8
CMOS/BiCMOS
Comparators

Complex

Simple

Chapter 4
CMOS
Subcircuits

Chapter 5
CMOS
Amplifiers

Chapter
Chapter10
2
CMOS/BiCMOS
D/A and A/D
Technology
Converters

Chapter
Chapter11
3
CMOS/BiCMOS
Analog
Modeling
Systems

Circuits

Devices
Introduction
CMOS Analog Circuit Design

Fig. 1.0-01

P.E. Allen - 2004

Chapter 1 Section 1 (5/2/04)

Page 1.1-1

SECTION 1.1 - ANALOG INTEGRATED CIRCUIT DESIGN


What is Analog IC Design?
Integrated
Analog IC design is the successful
Circuit
implementation of analog circuits and
Technology
systems using integrated circuit
technology.
Successful
Solution
Function or
Application

Fig. 1-1

Unique Features of Analog IC Design


Geometry is an important part of the design
Electrical Design Physical Design Test Design
Usually implemented in a mixed analog-digital circuit
Analog is 20% and digital 80% of the chip area
Analog requires 80% of the design time
Analog is designed at the circuit level
Passes for success: 2-3 for analog, 1 for digital
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 1 (5/2/04)

Page 1.1-2

The Analog IC Design Flow


Conception of the idea

Definition of the design

Electrical
Design

Comparison
with design
specifications

Implementation

Comparison
with design
specifications

Simulation

Physical Definition

Physical
Design

Physical Verification

Parasitic Extraction

Fabrication

Fabrication

Testing and
Product
Development

Testing and Verification

Product
Fig. 1.1-2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 1 (5/2/04)

Page 1.1-3

Analog IC Design - Continued


Electrical Aspects

;;
L

W/L ratios

Circuit or
systems
specifications

Analog
Integrated
Circuit Design

M3

vin
+

VDD
M6

M4

M1

Cc
vout

CL

M2

+
VBias
-

M7

M5
VSS

Topology
DC Currents

Fig. 1.1-3

Physical Aspects
Implementation of the physical design including:
- Transistors and passive components
- Connections between the above
- Busses for power and clock distribution
- External connections
Testing Aspects
Design and implementation for the experimental verification of the circuit after
fabrication
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 1 (5/2/04)

Page 1.1-4

Comparison of Analog and Digital Circuits


Analog Circuits
Signals are continuous in
amplitude and can be continuous
or discrete in time
Designed at the circuit level
Components must have a
continuum of values
Customized
CAD tools are difficult to apply
Requires precision modeling
Performance optimized
Irregular block
Difficult to route automatically
Dynamic range limited by power
supplies and noise (and linearity)
CMOS Analog Circuit Design

Digital Circuits
Signal are discontinuous in
amplitude and time - binary
signals have two amplitude states
Designed at the systems level
Component have fixed values
Standard
CAD tools have been extremely
successful
Timing models only
Programmable by software
Regular blocks
Easy to route automatically
Dynamic range unlimited

P.E. Allen - 2004

Chapter 1 Section 1 (5/2/04)

Page 1.1-5

Skills Required for Analog IC Design


In general, analog circuits are more complex than digital
Requires an ability to grasp multiple concepts simultaneously
Must be able to make appropriate simplifications and assumptions
Requires a good grasp of both modeling and technology
Have a wide range of skills - breadth (analog only is rare)
Be able to learn from failure
Be able to use simulation correctly
Simulation truths:
(Usage of a simulator) x (Common sense) Constant
Simulators are only as good as the models and the knowledge of those models
by the designer
Simulators are only good if you already know the answers

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 2 (5/2/04)

Page 1.2-1

SECTION 1.2 - TECHNOLOGY IMPACT ON ANALOG IC DESIGN


Trends in CMOS Technology
Moores law: The minimum feature size tends to decrease by a factor of 1/ 2 every
three years.
Semiconductor Industry Association roadmap for CMOS
Feature Size
0.35m 0.25m 0.18m 0.13m 0.10m 0.07m

Power Supply Voltage

3.0V
2.5V
2.0V
Desktop Systems
1.5V
1.0V
Portable Systems
1995

1998

2001

2004
Year

CMOS Analog Circuit Design

2007

2010
Fig. 1.2-1
P.E. Allen - 2004

Chapter 1 Section 2 (5/2/04)

Page 1.2-2

Trends in CMOS Technology - Continued


Threshold voltages and power supply:
Power Supply and Threshold Voltage (Volts)

2005-2006
10
5
2

Analog
Headroom

1
0.5

VDD
VT (scenario 2)

0.2

VT (scenario 1)

0.1
0.01

0.02

0.05
0.2
0.1
0.5
MOSFET Channel Length, m

1
Fig. 1.2-2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 2 (5/2/04)

Page 1.2-3

Trends in IC Technology
Technology Speed Figure of Merit vs. Time:
ft

HEMTs, HBTs

300GHz

SiGe

100GHz
30GHz
10GHz
3GHz

GaAs
Bipolar

1GHz

1m

0.25m
0.35m
0.5m
0.8m 0.6m

1.5m

2m

3m

Carrier Frequency of RF
Cellular Telephony
77 79 81 83 85 87 89 91 93 95 97 99

CMOS

0.09m
0.13m
0.18m

01 03

05

Year

Fig. 1.2-3B

Estimated Frequency Performance based on Scaling:


Technology

ft

0.35 micron
0.25 micron
0.18 micron

25GHz
40GHz
60GHz

CMOS Analog Circuit Design

fmax
40GHz
60-70GHz
90-100GHz
P.E. Allen - 2004

Chapter 1 Section 2 (5/2/04)

Page 1.2-4

Innovation in Analog IC Design


In the past, circuit innovation was driven by new technologies.
Rate of
Circuit
Innovation
Ideal

Actual
?

1950

1960

Discrete
Transistors

1970

Bipolar
Analog IC

1980

1990

MOS
Analog IC

2000
Fig. 1.2-4

Candidates for the future


Packaging?
Opto-electronics?
Vertically integrated transistors?
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 2 (5/2/04)

Page 1.2-5

Technology-Driven versus Application-Driven Innovation


Technology driven circuit innovation:
NewTechnology

Innovative
Solution
Generic
Function
Application driven circuit innovation:
Standard
Technology
Innovative
Solution
New
Application
CMOS Analog Circuit Design

Fig. 1.2-5
P.E. Allen - 2004

Chapter 1 Section 2 (5/2/04)

Page 1.2-6

Implications of Technology on IC Design


The good:
Smaller geometries
Smaller parasitics
Higher transconductance
Higher bandwidths
The bad:
Reduced voltages
Smaller channel resistances (lower gain)
More nonlinearity
Deviation from square-law behavior
The ugly:
Increased substrate noise in mixed signal applications
Threshold voltages are not scaling with power supply
Reduced dynamic range
Suitable models for analog design

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 3 (5/2/04)

Page 1.3-1

SECTION 1.3 - ANALOG SIGNAL PROCESSING


Signal Bandwidths versus Application

Video

RF

Acoustic
Imaging

Seismic
Sonar

Microwave
Radar

Audio

Optical

AM-FM radio, TV

Telecommunications

10

100

CMOS Analog Circuit Design

1k

10k

100k
1M
10M
Signal Frequency (Hz)

100M

1G

10G

100G
Fig. 1.3-1

P.E. Allen - 2004

Chapter 1 Section 3 (5/2/04)

Page 1.3-2

Signal Bandwidths versus Technology

Mostly digital implementation


BiCMOS
Bipolar analog
Bipolar digital logic

;
;
;
;
;
;
;
;
;
;

Mostly analog
implementation

Fuzzy boundary,
keeps moving to
the right

Surface acoustic
waves
MOS digital logic
MOS analog

10

100

1k

10k

100k
1M
10M
Signal Frequency (Hz)

CMOS Analog Circuit Design


Chapter 1 Section 3 (5/2/04)

100M

Optical
GaAs

1G

10G

100G
Fig. 1.3-2
P.E. Allen - 2004
Page 1.3-3

Analog IC Design has Reached Maturity


There are established fields of application:
Digital-analog and analog-digital conversion
Disk drive controllers
Modems - filters
Bandgap reference
Analog phase lock loops
DC-DC conversion
Buffers
Codecs

Existing philosophy regarding analog circuits:


If it can be done economically by digital, dont use analog.
Consequently:
Analog finds applications where speed, area, or power have advantages over a digital
approach.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 3 (5/2/04)

Page 1.3-4

Eggshell Analogy of Analog IC Design (Paul Gray)


Power
Source

Physical
Sensors
Actuators

Transmission
Media

VLSI
DIGITAL
SYSTEM

Imagers &
Displays

Audio
I/O

Storage
Media
Analog/Digital
Interface
Electronics

Fig. 1.3-3

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 3 (5/2/04)

Page 1.3-5

Analog Signal Processing versus Digital Signal Processing in VLSI


Key issues:
Analog/Digital mix is application dependent
Not scaling driven
Driven by system requirements for
programmability/adaptability/testability/designability
Now:
ASP

A/D

DSP

System

Trend:
ASP

A/D

DSP

System
Fig. 1.3-4

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 3 (5/2/04)

Page 1.3-6

Application Areas of Analog IC Design


There are two major areas of analog IC design:
Restituitive - performance oriented (speed, accuracy, power, area)
Classical analog circuit and systems design
Cognitive - function oriented (adaptable, massively parallel)
A newly growing area inspired by biological systems
Analog VLSI (An oxymoron):
Combination of analog circuits and VLSI philosophies
Many similarities between analog circuits and biological systems
Scalability
Nonlinearity
Adaptability
Neuromorphic analog VLSI
Use of biological systems to inspire circuit design such as smart sensors and imagers
Smart autonomous systems
Self-guided vehicles (Mars lander)
Industrial cleanup in a hazardous environment
Sensorimotor feedback
Self contained systems with sensor input, motor output
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 3 (5/2/04)

Page 1.3-7

What is the Future of Analog IC Design?


Technology will require more creative circuit solutions in order to achieve desired
performance
Analog circuits will continue to be a part of large VLSI digital systems
Interference and noise will become even more serious as the chip complexity increases
Packaging will be an important issue and offers some interesting solutions
Analog circuits will always be at the cutting edge of performance
Analog designer must also be both a circuit and systems designer and must know:
Technology and modeling
Analog circuit design
VLSI digital design
System application concepts
There will be no significantly new and different technologies - innovation will combine
new applications with existing or improved technologies
Semicustom methodology will eventually evolve with CAD tools that will allow:
- Design capture and reuse
- Quick extraction of model parameters from new technology
- Test design
- Automated design and layout of simple analog circuits
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 4 (5/2/04)

Page 1.4-1

SECTION 1.4 - NOTATION, SYMBOLOGY, AND TERMINOLOGY


Definition of Symbols for Various Signals

Drain Current

Signal Definition
Quantity
Subscript Example
Total instantaneous value of the signal Lowercase Uppercase
qA
DC value of the signal
Uppercase Uppercase
QA
AC value of the signal
Lowercase Lowercase
qa
Complex variable, phasor, or rms value Uppercase Lowercase
Qa
of the signal
Example:
Idm
id
ID

iD
t
Fig. 1.4-1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 4 (5/2/04)

Page 1.4-2

MOS Transistor Symbols


D
Enhancement
NMOS with
VBS = 0V.

Enhancement
PMOS with
VBS = 0V.

S
Enhancement
B NMOS with
VBS 0V.

Enhancement
B PMOS with
VBS 0V.

S
Simple
NMOS
symbol

S
CMOS Analog Circuit Design

Simple
PMOS
symbol

D
P.E. Allen - 2004

Chapter 1 Section 4 (5/2/04)

Page 1.4-3

Other Schematic Symbols


+
V

Differential amplifier,
op amp, or comparator

+
A vV1 -

V1
I1

V
-

Independent
current source
I2

Independent
voltage sources
+

V2

V1

Voltage-controlled,
voltage source

GmV1

I1

Voltage-controlled,
current source

I2

+
RmI1 +-

Ai I1

V2
-

Current-controlled,
voltage source

Current-controlled,
current source

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 4 (5/2/04)

Page 1.4-4

Three-Terminal Notation (Data books)

QABC
A = Terminal with the larger magnitude of potential
B = Terminal with the smaller magnitude of potential
C = Condition of the remaining terminal with respect to terminal B
C = 0 There is an infinite resistance between terminal B and the 3rd terminal
C = S There is a zero resistance between terminal B and the 3rd terminal
C = R There is a finite resistance between terminal B and the 3rd terminal
C = X There is a voltage source in series with a resistor between terminal B
and the 3rd terminal in such a manner as to reverse bias a PN junction.
Examples
I DSS
S

VGS

CDGS

+
G

(a.)

IDS
S

(b.)

BVDGO
G

(c.)

(a.) Capacitance from drain to gate with the source shorted to the gate.
(b.) Drain-source current when gate is shorted to source (depletion device)
(c.) Breakdown voltage from drain to gate with the source is open- circuited to the gate.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 1 Section 5 (5/2/04)

Page 1.5-1

1.5 - SUMMARY
Analog IC design combines a function or application with IC technology for a successful
solution.
Analog IC design consists of three major steps:
1.) Electrical design Topology, W/L values, and dc currents
2.) Physical design (Layout)
3.) Test design (Testing)
Analog designers must be flexible and have a skill set that allows one to simplify and
understand a complex problem
Analog IC design is driven by improving technologies rather than new technologies.
Analog IC design has reached maturity and is here to stay.
The appropriate philosophy is If it can be done economically by digital, dont use
analog.
As a result of the above, analog finds applications where speed, area, or power have
advantages over a digital approach.
Deep-submicron technologies will offer severe challenges to the creativity of the analog
designer.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Introduction (5/02/04)

Page 2.0-1

CHAPTER 2 CMOS TECHNOLOGY


Chapter Outline
2.1 Basic MOS Semiconductor Fabrication Processes
2.2 CMOS Technology
2.3 PN Junction
2.4 MOS Transistor
2.5 Passive Components
2.6 Other Considerations of CMOS Technology
2.7 Bipolar Transistor (optional)
2.8 BiCMOS Technology (optional)
Perspective
Analog
Integrated
Circuit
Design

CMOS
Technology
and
Fabrication

CMOS
Transistor and Passive
Component
Modeling
Fig. 2.0-1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Introduction (5/02/04)

Page 2.0-2

Classification of Silicon Technology


Silicon IC Technologies

Bipolar

Junction
Isolated

Dielectric
Isolated

SiliconGermanium
Fig. 150-01

CMOS Analog Circuit Design

Bipolar/CMOS

Oxide
isolated

Silicon

CMOS

Aluminum
gate

MOS

PMOS
(Aluminum
Gate)

Silicon
gate

NMOS

Aluminum
gate

Silicon
gate

P.E. Allen - 2004

Chapter 2 Introduction (5/02/04)

Page 2.0-3

Why CMOS Technology?


Comparison of BJT and MOSFET technology from an analog viewpoint:
Feature
Cutoff Frequency(fT)
Noise (thermal about the same)
DC Range of Operation

BJT

MOSFET
100 GHz
50 GHz (0.25m)
Less 1/f
More 1/f
9 decades of exponential 2-3 decades of square law
current versus vBE
behavior
Slightly larger
Smaller for short channel
Poor
Good
Voltage dependent
Reasonably good

Small Signal Output Resistance


Switch Implementation
Capacitor Implementation
Therefore,
Almost every comparison favors the BJT, however a similar comparison made from a
digital viewpoint would come up on the side of CMOS.
Therefore, since large-volume technology will be driven by digital demands, CMOS is
an obvious result as the technology of availability.
Other factors:
The potential for technology improvement for CMOS is greater than for BJT
Performance generally increases with decreasing channel length
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Introduction (5/02/04)

Page 2.0-4

Components of a Modern CMOS Technology


Illustration of a modern CMOS process:
Metal Layers
0.8m
M8
NMOS
PMOS
M7
Transistor
Transistor
M6
M5 7m
Polycide 0.3m
Polycide
Sidewall Spacers
M4
Salicide
Salicide
M3
Salicide
M2
M1
STI

n+
n+
Source/drain
extensions
Deep p-well

STI

p+
p+
Source/drain
STI
extensions
Deep n-well

p-substrate
031211-02

In addition to NMOS and PMOS transistors, the technology provides:


1.) A deep n-well that can be utilized to reduce substrate noise coupling.
2.) A MOS varactor that can serve in VCOs
3.) At least 6 levels of metal that can form many useful structures such as inductors,
capacitors, and transmission lines.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Introduction (5/02/04)

Page 2.0-5

CMOS Components Transistors


fT as a function of gate-source overdrive, VGS-VT (0.13m):
Typical, 25C

70
60

NMOS

Slow, 70C

fT (GHz)

50
Typical, 25C

40
30

Slow, 70C

PMOS

20
10
0

100

200
300
|VGS-VT| (mV)

400

500
030901-07

The upper frequency limit is probably around 40 GHz for NMOS with an fT in the vicinity
of 60GHz with an overdrive of 0.5V and at the slow-high temperature corner.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-1

SECTION 2.1 - BASIC CMOS TECHNOLOGY


FUNDAMENTAL PROCESSING STEPS
Basic steps
Oxide growth
Thermal diffusion
Ion implantation
Deposition
Etching
Epitaxy
Photolithography
Photolithography is the means by which the above steps are applied to selected areas of
the silicon wafer.
Silicon wafer
125-200 mm
(5"-8")

n-type: 3-5 -cm


p-type: 14-16 -cm
CMOS Analog Circuit Design

0.5-0.8mm

Fig. 2.1-1r
P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-2

Oxidation
Description:
Oxidation is the process by which a layer of silicon dioxide is grown on the surface of a
silicon wafer.
Original silicon surface

tox

Silicon dioxide
0.44 tox

Silicon substrate
Fig. 2.1-2

Uses:
Protect the underlying material from contamination
Provide isolation between two layers.
Very thin oxides (100 to 1000) are grown using dry oxidation techniques. Thicker
oxides (>1000) are grown using wet oxidation techniques.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-3

Diffusion
Diffusion is the movement of impurity atoms at the surface of the silicon into the bulk of
the silicon.
Always in the direction from higher concentration to lower concentration.
Low
Concentration

High
Concentration

Fig. 150-04

Diffusion is typically done at high temperatures: 800 to 1400C


N0

Gaussian

ERFC

N(x)

N0
t1 < t2 < t3

N(x)

t1 < t2 < t3

NB

NB
t1

t2

t3

Depth (x)
Infinite source of impurities at the surface.

t1

t2

t3

Depth (x)
Finite source of impurities at the surface.
Fig. 150-05

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-4

Ion Implantation
Ion implantation is the process by which
impurity ions are accelerated to a high
velocity and physically lodged into the
target material.

Path of
impurity
atom
Fixed Atom
Fixed Atom

Annealing is required to activate the


impurity atoms and repair the physical
Impurity Atom
damage to the crystal lattice. This step
final resting place
is done at 500 to 800C.
Ion implantation is a lower temperature
process compared to diffusion.
N(x)
Can implant through surface layers, thus it is
useful for field-threshold adjustment.
Can achieve unique doping profile such as
buried concentration peak.
N

Fixed Atom
Fig. 150-06

Concentration peak

CMOS Analog Circuit Design


Chapter 2 Section 1 (5/02/04)

Depth (x)

Fig. 150-07

P.E. Allen - 2004


Page 2.1-5

Deposition
Deposition is the means by which various materials are deposited on the silicon wafer.
Examples:
Silicon nitride (Si3N4)
Silicon dioxide (SiO2)
Aluminum
Polysilicon
There are various ways to deposit a material on a substrate:
Chemical-vapor deposition (CVD)
Low-pressure chemical-vapor deposition (LPCVD)
Plasma-assisted chemical-vapor deposition (PECVD)
Sputter deposition
Material that is being deposited using these techniques covers the entire wafer.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-6

Etching

Mask
Film

Etching is the process of selectively


removing a layer of material.
When etching is performed, the etchant
may remove portions or all of:
The desired material
The underlying layer
The masking layer

Underlying layer
(a) Portion of the top layer ready for etching.
a Selectivity
Mask
Film

c
b

Selectivity

Anisotropy
Underlying layer

Important considerations:
(b) Horizontal etching and etching of underlying layer.
Fig. 150-08
Anisotropy of the etch is defined as,
A = 1-(lateral etch rate/vertical etch rate)
Selectivity of the etch (film to mask and film to substrate) is defined as,
film etch rate
Sfilm-mask = mask etch rate
A = 1 and Sfilm-mask = are desired.
There are basically two types of etches:
Wet etch which uses chemicals
Dry etch which uses chemically active ionized gases.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-7

Epitaxy
Epitaxial growth consists of the formation of a layer of single-crystal silicon on the
surface of the silicon material so that the crystal structure of the silicon is continuous
across the interfaces.
It is done externally to the material as opposed to diffusion which is internal
The epitaxial layer (epi) can be doped differently, even oppositely, of the material on
which it grown
It accomplished at high temperatures using a chemical reaction at the surface
The epi layer can be any thickness, typically 1-20 microns
Gaseous cloud containing SiCL4 or SiH4
Si +

Si

Si
Si

Si
Si

Si
Si

Si

Si
Si

Si
Si

Si
Si

- Si
Si

Si
Si

Si

Si

Si

Si

Si
Si
Si
Si

Si
Si

Si

Si

Si

Si

Si

Si
Si

Si
Si

Si

Si

Si
Si

Si
Si

Si

Si
Si

Si
Si

Si
Si

Si

Si

Si

Si

Si

Si

Si
Si

Si
Si

Si

Si

Si

Si

Si
Si

Si

Si

Si
Si

Si

Si
Si

Si
Si

Fig. 150-09

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-8

Photolithography
Components
Photoresist material
Mask
Material to be patterned (e.g., oxide)
Positive photoresist
Areas exposed to UV light are soluble in the developer
Negative photoresist
Areas not exposed to UV light are soluble in the developer
Steps
1. Apply photoresist
2. Soft bake (drives off solvents in the photoresist)
3. Expose the photoresist to UV light through a mask
4. Develop (remove unwanted photoresist using solvents)
5. Hard bake ( 100C)
6. Remove photoresist (solvents)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-9

Illustration of Photolithography - Exposure


The process of exposing
Photomask
selective areas to light
through a photo-mask is
called printing.
Types of printing include:
Contact printing
Proximity printing
Projection printing
UV Light
Photomask

Photoresist
Polysilicon
Fig. 150-10

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-10

Illustration of Photolithography - Positive Photoresist

Develop
Polysilicon
Photoresist

Etch

Photoresist
Polysilicon

Remove
photoresist

Polysilicon

Fig. 150-11

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-11

Illustration of Photolithography - Negative Photoresist


(Not used much any more)
Photoresist

Underlying Layer
Photoresist

SiO2

Underlying Layer
SiO2

SiO2

Underlying Layer
CMOS Analog Circuit Design

Fig. 150-12

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-12

TYPICAL DSM CMOS FABRICATION PROCESS


Major Fabrication Steps for a DSM CMOS Process
1.) p and n wells
2.) Shallow trench isolation
3.) Threshold shift
4.) Thin oxide and gate polysilicon
5.) Lightly doped drains and sources
6.) Sidewall spacer
7.) Heavily doped drains and sources
8.) Siliciding (Salicide and Polycide)
9.) Bottom metal, tungsten plugs, and oxide
10.) Higher level metals, tungsten plugs/vias, and oxide
11.) Top level metal, vias and protective oxide

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-13

Step 1 Starting Material


The substrate should be highly doped to act like a good conductor.

yy
;;
Gate Ox

Oxide

Substrate
p+

CMOS Analog Circuit Design

p-

n-

n+

Poly

Salicide Polycide

Metal

031231-13

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-14

Step 2 - n and p wells


These are the areas where the transistors will be fabricated - NMOS in the p-well and
PMOS in the n-well.
Done by implantation followed by a deep diffusion.

n well implant and diffusion

yy
;;
Gate Ox

Oxide

p well implant and diffusion

n-well

p-well
Substrate

p+

p-

n-

n+

Poly

Salicide Polycide

CMOS Analog Circuit Design

Metal

031231-12

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-15

Step 3 Shallow Trench Isolation


The shallow trench isolation (STI) electrically isolates one region/transistor from another.

Shallow
Trench
Isolation

yy
;;
Gate Ox

Oxide

Shallow
Trench
Isolation
n-well

Shallow
Trench
Isolation
p-well
Substrate

p+

CMOS Analog Circuit Design

p-

n-

n+

Poly

Salicide Polycide

Metal

031231-11

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-16

Step 4 Threshold Shift and Anti-Punch Through Implants


The natural thresholds of the NMOS is about 0V and of the PMOS is about 1.2V. An nimplant is used to make the NMOS harder to invert and the PMOS easier resulting in
threshold voltages balanced around zero volts.
Also an implant can be applied to create a higher-doped region beneath the channels to
prevent punch-through from the drain depletion region extending to source depletion
region.
n+ anti-punch through implant

p+ anti-punch through implant

p threshold implant

p threshold implant

Shallow
Trench
Isolation

yy
;;
Gate Ox

Oxide

Shallow
Trench
Isolation
n-well

Shallow
Trench
Isolation
p-well
Substrate

p+

p-

n-

n+

Poly

Salicide Polycide

CMOS Analog Circuit Design

Metal

031231-10

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-17

; ;

Step 5 Thin Oxide and Polysilicon Gates


A thin oxide is deposited followed by polysilicon. These layers are removed where they
are not wanted.

Thin Oxide

Shallow
Trench
Isolation

yy
;;
Gate Ox

Oxide

Shallow
Trench
Isolation

n-well

Shallow
Trench
Isolation

p-well
Substrate

p+

CMOS Analog Circuit Design

p-

n-

n+

Poly

Salicide Polycide

Metal

031231-09

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-18

; ;

Step 6 Lightly Doped Drains and Sources


A lightly-doped implant is used to create a lightly-doped source and drain next to the
channel of the MOSFETs.

Shallow pImplant

Shallow
Trench
Isolation

yy
;;
Gate Ox

Oxide

Shallow pImplant

Shallow nImplant

Shallow nImplant

Shallow
Trench
Isolation

n-well

Shallow
Trench
Isolation

p-well
Substrate

p+

p-

n-

n+

Poly

Salicide Polycide

CMOS Analog Circuit Design

Metal

031231-08

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-19

Step 7 Sidewall Spacers


A layer of dielectric is deposited on the surface and removed in such a way as to leave
sidewall spacers next to the thin-oxide-polysilicon-polycide sandwich. These sidewall
spacers will prevent the part of the source and drain next to the channel from becoming
heavily doped.

; ;
Sidewall
Spacers

Shallow
Trench
Isolation

yy
;;
Gate Ox

Oxide

Sidewall
Spacers

Shallow
Trench
Isolation

n-well

Shallow
Trench
Isolation

p-well
Substrate

p+

CMOS Analog Circuit Design

p-

n-

n+

Poly

Salicide Polycide

Metal

031231-07

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-20

; ;

Step 8 Implantation of the Heavily Doped Sources and Drains


Note that not only does this step provide the completed sources and drains but allows for
ohmic contact into the wells and substrate.

p+
implant

n+
implant

p+

n+

Sidewall
p+ Spacers
p+
implant
implant

yy
;;
Gate Ox

Oxide

n+
implant

p+
implant

n+

n+

p+

p+

p+

Shallow
Trench
Isolation

n+
implant

Shallow
Trench
Isolation

n-well

Shallow
Trench
Isolation

p-well
Substrate

p+

p-

n-

n+

Poly

Salicide Polycide

CMOS Analog Circuit Design

Metal

031231-06

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-21

Step 9 Siliciding
Siliciding and polyciding is used to reduce interconnect resistivity by placing a lowresistance silicide such as TiSi2, WSi2, TaSi2, etc. on top of the diffusions.

; ;
Sidewall
Spacers

Salicide

Salicide
p+

n+

yy
;;
Gate Ox

Oxide

Salicide

p+

p+

Shallow
Trench
Isolation

Polycide

Salicide

n+

n+

p+

Shallow
Trench
Isolation

n-well

Shallow
Trench
Isolation

p-well
Substrate

p+

CMOS Analog Circuit Design

p-

n-

n+

Poly

Salicide Polycide

Metal

031231-05

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-22

Step 10 Intermediate Oxide Layer


An oxide layer is used to cover the transistors and to planarize the surface.

Intermediate
Oxide
Layer

Salicide

Salicide
p+

n+

yy
;;

Oxide

Polycide

Salicide

p+

p+

Shallow
Trench
Isolation

Gate Ox

; ;
Sidewall
Spacers

Salicide

n+

n+

p+

Shallow
Trench
Isolation

n-well

Shallow
Trench
Isolation

p-well
Substrate

p+

p-

n-

n+

Salicide Polycide

Poly

CMOS Analog Circuit Design

Metal

031231-04

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-23

Step 11- First-Level Metal


Tungsten plugs are built through the lower intermediate oxide layer to provide contact
between the devices, wells and substrate to the first-level metal.
Intermediate
Oxide
Layers

Tungsten
Plugs

Salicide
p+

Salicide
n+

yy
;;

Oxide

Polycide

Salicide

p+

p+

Shallow
Trench
Isolation

Gate Ox

; ;
Sidewall
Spacers

Tungsten
Plug

Salicide

n+

n+

p+

Shallow
Trench
Isolation

n-well

First
Level
Metal

Shallow
Trench
Isolation

p-well
Substrate

p+

CMOS Analog Circuit Design

p-

n-

n+

Poly

Salicide Polycide

Metal

031231-03

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-24

Step 12 Second-Level Metal


The previous step is repeated to from the second-level metal.

Intermediate
Oxide
Layers

Tungsten
Plugs
Tungsten
Plugs

Salicide
p+

Salicide
n+

yy
;;

Oxide

Salicide

Tungsten
Plug

Salicide

p+

p+

Shallow
Trench
Isolation

Gate Ox

; ;
Tungsten Plugs
Polycide

Sidewall
Spacers

n+

n+

p+

Shallow
Trench
Isolation

n-well

Second
Level
Metal
First
Level
Metal

Shallow
Trench
Isolation

p-well
Substrate

p+

p-

n-

n+

Poly

Salicide Polycide

Metal

CMOS Analog Circuit Design

031231-02

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-25

Completed Fabrication
After multiple levels of metal are applied, the fabrication is completed with a thicker toplevel metal and a protective layer to hermetically seal the circuit from the environment.
Note that metal is used for the upper level metal vias. The chip is electrically connected
by removing the protective layer over large bonding pads.

; ;

Protective Insulator Layer

Metal Vias

Intermediate
Oxide
Layers

Tungsten
Plugs

Salicide
p+

Metal Via

Tungsten Plugs
Polycide

Sidewall
Spacers

Tungsten
Plugs
Salicide
n+

Salicide

p+

p+

Shallow
Trench
Isolation

Top
Metal

Tungsten
Plug

Salicide

n+

n+

p+

Shallow
Trench
Isolation

n-well

Second
Level
Metal
First
Level
Metal

Shallow
Trench
Isolation

p-well
Substrate

Gate Ox

Oxide

p+

CMOS Analog Circuit Design

p-

n-

n+

Poly

Salicide Polycide

Metal

031231-01

P.E. Allen - 2004

Chapter 2 Section 1 (5/02/04)

Page 2.1-26

Scanning Electron Microscope of a MOSFET Cross-section

Tungsten Plug
TEOS
SOG

Polycide
Sidewall
Spacer

TEOS/BPSG

Poly
Gate

Fig. 2.8-20
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 2 (5/02/04)

Page 2.2-1

Scanning Electron Microscope Showing Metal Levels and Interconnect

Metal 3
Aluminum
Vias
Metal 2

Tungsten
Plugs

Metal 1

Transistors
CMOS Analog Circuit Design

Fig.180-11

P.E. Allen - 2004

Chapter 2 Section 2 (5/02/04)

Page 2.2-2

SUMMARY
Fabrication is the means by which the circuit components, both active and passive, are
built as an integrated circuit.
Basic process steps include:
1.) Oxide growth
2.) Thermal diffusion
3.) Ion implantation
4.) Deposition
5.) Etching
6.) Epitaxy
The complexity of a process can be measured in the terms of the number of masking
steps or masks required to implement the process.
Major CMOS Processing Steps:
1.) p and n wells
2.) Shallow trench isolation
3.) Threshold shift
4.) Thin oxide and gate polysilicon
5.) Lightly doped drains and sources
6.) Sidewall spacer
7.) Heavily doped drains and sources
8.) Siliciding (Salicide and Polycide)
9.) Bottom metal, tungsten plugs, and oxide
10.) Higher level metals, tungsten plugs/vias, and oxide
11.) Top level metal, vias and protective oxide

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 2 (5/02/04)

Page 2.2-3

SECTION 2.2 - THE PN JUNCTION


Abrupt Junction
Metallurgical Junction
n-type semiconductor

p-type semiconductor

iD

+vD Depletion
region
n-type
semiconductor

p-type
semiconductor

iD

+ v -D W
-W1

W2

Fig. 06-01

1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.
2. As these fixed atoms lose their free carriers, they build up an electric field, which
opposes the diffusion mechanism.
3. Equilibrium conditions are reached when:
Current due to diffusion = Current due to electric field
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 2 (5/02/04)

Page 2.2-4

Mathematical Characterization of the Abrupt PN Junction


Impurity concentration (cm-3)
Assume the pn junction is open-circuited.
ND

Cross-section of an ideal pn junction:

0
xd
xp

Depletion charge concentration (cm-3)

n-type
semiconductor

p-type
semiconductor

iD

-NA

xn

+ v-D -

qND
-W1
0

Fig. 06-02

W2

-qNA

Symbol for the pn junction:

Electric Field (V/cm)

iD

+v Built-in potential, o:
D
iD
NAND
o = Vt ln n 2 ,
i
+v D
kT
where Vt = q and ni2
is the intrinsic concentration of silicon.
CMOS Analog Circuit Design
Chapter 2 Section 2 (5/02/04)

E0
Potential (V)
Fig. 06-03

x
xd

Fig. 06-04A

P.E. Allen - 2004


Page 2.2-5

Physics of Abrupt PN Junctions


Apply a forward bias voltage, vD, to the pn junction:
1.) The voltage across the junction is o - vD.
2.) Charge equality requires that W1NA = W2ND where
W1 (W2) = depletion region width on the p-side(n-side)
3.) Poissons equation in one dimension is
Depletion charge concentration (cm-3)
qNA
d2v
qND
for -W1<x<0
dx2 = - =
-W1
x
0
where
W2
= charge density
-qNA
-19
q = charge of an electron (1.6x10 coulomb)
= KSo
KS = dielectric constant of silicon
o = permittivity of free space (8.86x10-14F/cm)
Electric Field (V/cm)
W2
-W
0
qN
1
dv
A
4.) Integrating Poissons equation gives, dx = x + C1

dv qNA

E0
5.) The electric field, = - dx = - x + C1
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 2 (5/02/04)

Page 2.2-6

Physics of Abrupt PN Junctions - Continued


6.) Since there is zero electric field outside the depletion region, a boundary condition is
= 0 for x = -W1
Electric Field (V/cm)
W2
-W
0
1
This gives,
x
dv qNA
= - dx = - x + W1 for -W1 < x< 0
Emax
Note that the maximum electric field occurs at x = 0
which gives
qN W
Potential (V)
A 1
max = -
V2
0 vD
7.) Integration of the electric field gives,
x
V1

qNA x 2

-W1
W2
v = 2 + W1x + C2
xd0
8.) A second boundary condition is obtained by assuming that the potential of the neutral
p-type region is zero. This boundary condition is,
v = 0 for x = -W1
Substituting in the expression above gives,
W12
qNA x 2
v = 2 + W1x + 2
CMOS Analog Circuit Design
Chapter 2 Section 2 (5/02/04)

P.E. Allen - 2004


Page 2.2-7

Physics of Abrupt PN Junctions - Continued


Potential (V)
9.) At x =0, we define the potential v = V1 which gives
V2
qNA W 12
0 vD
V1 =
2
V1
If the potential difference from x = 0 to x = W2 is V2, then
-W1
W2
xd0
qND W 22
V2 =
2
10.) The total voltage across the pn junction is
q
o-vD = V1+V2 = 2 NAW12 + NDW22
11.) Substituting W1NA = W2ND into the above expression gives
qNAW12 ND W 2 2 qNAW12 NA
o-vD = 2
1+ N W =
1+ N
2
A 1
D

12.) The depletion region width on the p-side of the pn junction is given as
2(o -vD)
2(o -vD)
and
W
=
W1 =
2

NA
ND

qNA1 + ND
qND1 + NA

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 2 (5/02/04)

Page 2.2-8

Summary of the Abrupt PN Junction Characterization


Barrier potential NAND
kT NAND
o = q ln ni2 = Vt ln ni2

Depletion region widthsW1 =


W2 =

2si(o-vD)ND
qNA(NA+ND)
2si(o-vD)NA
qND(NA+ND)

1
N

Depletion capacitancesiA
siA
siA
Cj = d = W 1+W 2 =
2si(o-vD) ND
q(ND+NA) NA +
=A

siqNAND
2(NA+ND)

CMOS Analog Circuit Design


Chapter 2 Section 2 (5/02/04)

1
o-vD =

Cj

NA
ND

Cj0

Cj0
vD
1 - o

Fig. 06-05

0 vD

P.E. Allen - 2004


Page 2.2-9

Example 1
An abrupt silicon pn junction has the doping densities of NA = 1015 atoms/cm3 and ND =
1016 atoms/cm3. Calculate the junction built-in potential, the depletion-layer widths, the
maximum field and the depletion capacitance with 10V reverse bias if Cj0 = 3pF.
Solution
At room temperature, kT/q = 26mV and the intrinsic concentration is ni = 1.5x1010 cm-3.
10151016
Therefore, the junction built-in potential is o = 0.026 ln2.25x1026 = 0.637V

The depletion width on the p-side is,


21.04x10-1210.64
-4
W1 =
1.6x10-1910151.1 = 3.55x10 cm = 3.55m
The depletion width on the n-side is,
21.04x10-1210.64
-4
W2 =
1.6x10-19101611 = 0.35x10 cm = 0.35m
The maximum field occurs for x = 0 and is
-1.6x10-1910153.5x10-4
qNA

4
max = - W 1 =
= -5.38x10 V/cm
1.04x10-12

3pF
The depletion capacitance can be found as Cj =
= 0.734pF
1 + (10/0.637)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 2 (5/02/04)

Page 2.2-10

Reverse Breakdown and Leakage Current Characteristics of the PN Junction


Breakdown voltage
si(NA+ND)
2
1
VR = 2qNAND Emax N
2
where Emax is the maximum electric field before breakdown occurs (usually due to
avalanche breakdown).
Reverse leakage current
The reverse current, IR, increases by a multiplication factor M as the reverse voltage
increases and is
ID (mA)
IRA = MIR
3
where
2
1
M =
V
R n
1
BV
1 - BV
5
-25 -20 -15 -10
-5
VR

VD (V)

-1

Breakdown

-2
-3

CMOS Analog Circuit Design


Chapter 2 Section 2 (5/02/04)

Fig. 6-06
P.E. Allen - 2004
Page 2.2-11

Example 2
An abrupt pn junction has doping densities of NA = 3x1016 atoms/cm3 and ND = 4x1019
atoms/cm3. Calculate the breakdown voltage if crit = 3x105 V/cm.
Solution
2
si
si(NA+ND) 2
1.04x10-129x1010
VR = 2qNAND Emax 2qNA Emax = 21.6x10-193x1016 = 9.7V

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 2 (5/02/04)

Page 2.2-12

Summary of a Graded PN Junction Characterization


Graded junction:
ND
x

0
-NA

Fig. 6-07

The previous expressions become:


Depletion region widths 2si(o-vD)ND m
W 1 = qNA(NA+ND)

W 1 m
2si(o-vD)NA m
N
W 2 = qND(NA+ND)

Depletion capacitance siqNAND m


Cj0
1
=
Cj = A2(NA+ND)

m
vD m

o-vD
1 o

where 0.33 m 0.5.


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 2 (5/02/04)

Page 2.2-13

Forward Bias Current-Voltage Relationship of the PN Junction


-VGO
Dppno Dnnpo qAD ni2
3
where Is = qA Lp + Ln L N = KT exp Vt

vD
iD = I exp Vt - 1

25
20

iD 15
I s 10
5
0
-5

-4

-3

-2

-1

vD/Vt

16

10 x10

16

8x10

16
iD 6x10
Is
16
4x10

2x1016
0
-40
CMOS Analog Circuit Design

-30

-20

-10

0
vD/Vt

10

20

30

40
P.E. Allen - 2004

Chapter 2 Section 2 (5/02/04)

Page 2.2-14

Metal-Semiconductor Junctions
Ohmic Junctions: A pn junction formed by a highly doped semiconductor and metal.
Energy band diagram
IV Characteristics
I
1

Vacuum Level

;;;;
;;;;

Thermionic
or tunneling

qm

qB

n-type metal

qs

Contact
Resistance

EC
EF

EV
n-type semiconductor

Fig. 2.3-4

Schottky Junctions: A pn junction formed by a lightly doped semiconductor and metal.


Energy band diagram
IV Characteristics
I

;;;;
;;;;
;;;;
qB

n-type metal

Forward Bias

EC
EF
Reverse Bias
Forward Bias

Reverse Bias

EV

n-type semiconductor

Fig. 2.3-5

CMOS Analog Circuit Design

Chapter 2 Section 2 (5/02/04)

P.E. Allen - 2004


Page 2.2-15

SUMMARY
Characterized the reverse bias operation of the abrupt pn junction
pn junction has a barrier potential o
Depletion region widths are proportional to N-0.5
The pn junction depletion region acts like a voltage dependent capacitance
Applications of the reverse biased pn junction
Isolate transistors from the material they are built in
Variable capacitors - varactors

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 3 (5/02/04)

Page 2.3-1

SECTION 2.3 - THE MOS TRANSISTOR


Physical Structure of the n-channel and p-channel transistor in an n-well technology
p-channel transistor

n-channel transistor

SiO2

(n+

Substrate tie

dra
in

sou
rce

FOX

FOX

)
(n+

)
(p+

FOX

p+

FOX

n+

sou
rce

Well tie

dra
in

(p+

Polysilicon

FOX

n-well
p- substrate
Fig. 2.4-1

How does the transistor work?


Consider the enhancement n-channel MOSFET:
When the gate is positive with respect to the substrate a depletion region is formed
beneath the gate resulting in holes being pushed away from the Si-SiO2 interface.
When the gate voltage is sufficiently large (0.5-0.7V), the region beneath the gate
inverts and a n-channel is formed between the source and drain.
CMOS Analog Circuit Design
Chapter 2 Section 3 (5/02/04)

P.E. Allen - 2004


Page 2.3-2

The MOSFET Threshold Voltage


When the gate voltage reaches a value called the threshold voltage (VT), the substrate
beneath the gate becomes inverted (it changes from p-type to n-type).

Qb QSS
VT = MS + -2F - Cox + Cox

where
MS = F(substrate) - F(gate)
F = Equilibrium electrostatic potential (Femi potential)
kT
F(PMOS) = q ln(ND/ni) = Vt ln(ND/ni)
kT
F(NMOS) = q ln(ni/NA) = Vt ln(ni/NA)
Qb 2qNAsi(|-2F+vSB|)
QSS = undesired positive charge present between the oxide and the bulk silicon
Rewriting the threshold voltage expression gives,
Qb0 QSS Qb - Qb0
VT = MS -2F - C - C - C
= VT0 + |-2F + vSB| - |-2F|
ox
ox
ox
where
2qsiNA
Qb0 QSS
and
=
VT0 = MS - 2F - Cox - Cox
Cox
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 3 (5/02/04)

Page 2.3-3

Signs for the Quantities in the Threshold Voltage Expression


Parameter
Substrate
MS
Metal
n+ Si Gate
p+ Si Gate
F
Qb0,Qb
Qss
VSB

CMOS Analog Circuit Design

N-Channel
p-type

P-Channel
n-type

+
+
+

+
+
+
+

P.E. Allen - 2004

Chapter 2 Section 3 (5/02/04)

Page 2.3-4

Example 2.3-1 - Calculation of the Threshold Voltage


Find the threshold voltage and body factor for an n-channel transistor with an n+ silicon
gate if tox = 200, NA = 3 1016 cm-3, gate doping, ND = 4 1019 cm-3, and if the
positively-charged ions at the oxide-silicon interface per area is 1010 cm-2.
Solution
The intrinsic concentration is 1.45x1010 atoms/cm3. From above, F(substrate) is given
as
1.451010
F(substrate) = -0.0259 ln 31016 = -0.377 V

The equilibrium electrostatic potential for the n+ polysilicon gate is found from as
41019
F(gate) = 0.0259 ln 1.451010 = 0.563 V

Therefore, the potential MS is found to be


F(substrate) -F(gate) = -0.940 V.
The oxide capacitance is given as
3.9 8.854 10-14
= 1.72710-7 F/cm2
Cox = ox/tox =
200 10-8
The fixed charge in the depletion region, Qb0, is given as
Qb0 = [21.610-1911.78.85410-1420.37731016]1/2 = 8.6610-8 C/cm2.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 3 (5/02/04)

Page 2.3-5

Example 2.3-1 - Continued


Dividing Qb0 by Cox gives -0.501 V. Finally, Qss/Cox is given as
Qss 10101.6010-19
-3
Cox = 1.72710-7 = 9.310 V
Substituting these values for VT0 gives
VT0 = - 0.940 + 0.754 + 0.501 - 9.3 x 10-3 = 0.306 V
The body factor is found as
21.610-1911.78.85410-1431016
=
1.72710-7

1/2

= 0.577 V1/2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 3 (5/02/04)

Page 2.3-6

Depletion Mode MOSFET


The channel is diffused into the substrate so that a channel exists between the source and
drain with no external gate potential.
Source Gate

Drain

ne

lW

id

th

,W

Bulk

Ch

an

Polysilicon

p+

Fig.
4.3-4
n+

n+
n-channel
Channel
Length, L

p substrate (bulk)

The threshold voltage for a depletion mode NMOS transistor will be negative (a negative
gate potential is necessary to attract enough holes underneath the gate to cause this
region to invert to p-type material).

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 3 (5/02/04)

Weak Inversion Operation


Weak inversion operation occurs when
the applied gate voltage is below VT and
pertains to when the surface of the
substrate beneath the gate is weakly
inverted.

;;;
;;;
yyy

Page 2.3-7

VGS

n+

n-channel

n+

Diffusion Current
p-substrate/well

Regions of operation according to the surface potential, S.


S < F :
Substrate not inverted
F < S < 2F :
Channel is weakly inverted (diffusion current)
Strong inversion (drift current)
2F < S :
Drift current versus
diffusion current in a
MOSFET:

log iD
Diffusion Current
Drift Current

10-6

10-12

VT

VGS

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-1

SECTION 2.4 - PASSIVE COMPONENTS


CAPACITORS
Types of Capacitors Considered
pn junction capacitors
Standard MOS capacitors
Accumulation mode MOS capacitors
Poly-poly capacitors
Metal-metal capacitors
Characterization of Capacitors
Assume C is the desired capacitance:
1.) Dissipation (quality factor) of a capacitor is
Q = CRp
where Rp is the equivalent resistance in parallel with the capacitor, C.
2.) Cmax/Cmin ratio is the ratio of the largest value of capacitance to the smallest when
the capacitor is used as a variable capacitor called varactor.
3.) Variation of capacitance with the control voltage.
4.) Parasitic capacitors from both terminal of the desired capacitor to ac ground.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-2

Desirable Characteristics of Varactors


1.) A high quality factor
2.) A control voltage range compatible with supply voltage
3.) Good tunability over the available control voltage range
4.) Small silicon area (reduces cost)
5.) Reasonably uniform capacitance variation over the available control voltage range
6.) A high Cmax/Cmin ratio
Some References for Further Information
1.) P. Andreani and S. Mattisson, On the Use of MOS Varactors in RF VCOs, IEEE
J. of Solid-State Circuits, vol. 35, no. 6, June 2000, pp. 905-910.
2.) A-S Porret, T. Melly, C. Enz, and E. Vittoz, Design of High-Q Varactors for LowPower Wireless Applications Using a Standard CMOS Process, IEEE J. of Solid-State
Circuits, vol. 35, no. 3, March 2000, pp. 337-345.
3.) E. Pedersen, RF CMOS Varactors for 2GHz Applications, Analog Integrated
Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-3

PN Junction Capacitors
Generally made by diffusion into the well.
Anode

;;;
;;;
Cj

n+

Cathode

rD

Cj

p+

Rwj

n-well

Substrate

Cw

VA

p+

n+

Rwj
Rw
Depletion
Region

Anode

VB
Rwj

Cathode

Rs

p- substrate

Layout:
Minimize the distance between the p+ and n+ diffusions.
Two different versions have been tested.
1.) Large islands 9m on a side
2.) Small islands 1.2m on a side

Fig. 2.5-011

n+ diffusion
p+ diffusion
n-well

Fig. 2.5-1A

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-4

PN-Junction Capacitors Continued


The anode should be the floating node and the cathode must be connected to ac ground.
Experimental data (Q at 2GHz, 0.5m CMOS):
Cmax

Cmin

Qmin

120

Qmax

100

3
2.5

Small Islands

Large Islands

80

QAnode

CAnode (pF)

4
3.5

Small Islands

2
1.5

60
40

Large Islands

1
20

0.5
0

0
0

0.5

1
1.5
2
2.5
Cathode Voltage (V)

3.5

0.5

1.5
2
2.5
Cathode Voltage (V)

3.5
Fig2.5-1B

Summary:
Terminal Small Islands (598 1.2m x1.2m)
Large Islands (42 9m x 9m)
Under Test Cmax/Cmin
Qmin
Qmax
Cmax/Cmin
Qmin
Qmax
Anode
1.23
94.5
109
1.32
19
22.6
Cathode
1.21
8.4
9.2
1.29
8.6
9.5
Electrons as majority carriers lead to higher Q because of their higher mobility.
The resistance, Rwj, is reduced in small islands compared with large islands higher Q.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-5

Single-Ended and Differential PN Junction Capacitors


Differential configurations can reduce the bulk resistances and increase the effective Q.
VS

Vcontrol
n+

p+

n+

p+

p+

VS

n+

n-well
Vcontrol
VS+
VS-

Vcontrol
n+

p+

p+

p+

p+

n+

VS+

VS-

Vcontrol

n-well
Fig. 2.5-015

An examination of the electric field lines shows that because the symmetry inherent in the
differential configuration, the path to the small-signal ground can be shortened if devices
with opposite polarity alternate.

CMOS Analog Circuit Design

P.E. Allen - 2004

;;

Chapter 2 Section 4 (5/02/04)

Standard MOS Capacitor (D = S = B)


Conditions:
D=S=B
Operates from accumulation to
inversion
Nonmonotonic
p+
Nonlinear

Page 2.4-6

;;;;

D,S,B

p+

n+

p+

Charge
carrier path

n- well

p- substrate/bulk

Capacitance

Cox

Cox
Weak
Inv.

Accumulation

Chapter 2 Section 4 (5/02/04)

Inversion Mode MOS Capacitors


Conditions:
D = S, B = VDD
Accumulation region removed
by connecting bulk to VDD
Channel resistance:
L
Ron = 12KP'(VBG-|VT|)
LDD transistors will give
lower Q because of the
increased series resistance

VSG

Moderate
Inversion

Depletion

CMOS Analog Circuit Design

Strong
Inversion
Fig. 2.5-012

;;

P.E. Allen - 2004


Page 2.4-7

;;;;
G

p+

p-channel

p+

D,S

VDD

B
n+

p+

Charge carrier paths

n- well

p- substrate/bulk

Capacitance

Cox

B=D=S

Cox

Inversion
Mode MOS

VT shift due
to VBS
0

VSG
Fig. 2.5-013

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-8

Simulation Results for Standard and Inversion Mode 0.25m CMOS Varactors
n-well:

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-9

Inversion Mode MOS Capacitors Continued


Bulk tuning of the polysilicon-oxide-channel capacitor (0.35m CMOS)
0.8
VT

-0.65V
CG

0.4

vB

0.2
0.0
-1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5
vB (Volts)

Fig. 2.5-3

Cmax/Cmin 4
Interpretation:

Capacitance
Cmax

Cox
VBS = -1.50V
VBS = -1.05V
VBS = -0.65V

Inversion
Mode MOS
Cmin
0
CMOS Analog Circuit Design

0.6

Volts or pF

1.0

CG

0.65V

VSG
Fig. 2.5-34
P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

;;;

Page 2.4-10

Inversion Mode NMOS Varactor Continued


More Detail - Includes the LDD transistor

;;;
;;;;;;;;
;;;
;;;;;;;;

Bulk Rsj Cj
p+

Cov

n+

p- substrate/bulk

Rd

D,S

Shown in inversion mode

Cov

Cox

Csi Cd

Cd

Rsi

D,S

Rd

n+

n- LDD

Fig. 2.5-2

Best results are obtained when the drain-source are on ac ground.


Experimental Results (Q at 2GHz, 0.5m CMOS):
Cmin

Cmax

4.5

34

VG = 2.1V

3.5

VG = 2.1V

32

QGate

CGate (pF)

Qmin

Qmax

38
36

VG = 1.8V

2.5

VG = 1.5V

26

VG = 1.5V

VG = 1.8V

30
28
24
22

1.5
0

0.5

1
1.5
2
2.5
Drain/Source Voltage (V)

3.5

0.5

1
1.5
2
2.5
Drain/Source Voltage (V)

3.5

Fig. 2.5-1c

VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9)
CMOS Analog Circuit Design
Chapter 2 Section 4 (5/02/04)

Accumulation Mode MOS Capacitors


Conditions:
Remove p+ drain and source and put
n+ bulk contacts instead
Variable capacitor with a larger
transition region between the
maximum and minimum values.

P.E. Allen - 2004

;;

Page 2.4-11

;;;;
G

p+

n+

n+

Charge carrier paths

n- well

p- substrate/bulk

Capacitance

Cox

B=D=S

Cox
Accumulation
Mode MOS
0

VSG
Fig. 2.5-014

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-12

;;;

Accumulation-Mode Capacitor More Detail

Bulk
p+

Cov

Cw
Rs

n+

Rw

;;;
;;;;

Rd

D,S

Shown in depletion mode.

Cov

Cox

Rd

Cd

Cd

n- LDD

D,S
B

n+

n- well

p- substrate/bulk

Fig. 2.5-5

Best results are obtained when the drain-source are on ac ground.


Experimental Results (Q at 2GHz, 0.5m CMOS):
Cmax

Cmin

VG = 0.9V

3.2

VG = 0.6V

VG = 0.6V

35

2.8

VG = 0.9V

30

VG = 0.3V

2.4

VG = 0.3V

40
QGate

CGate (pF)

3.6

Qmin

Qmax

45

25
0

0.5

1
1.5
2
2.5
Drain/Source Voltage (V)

3.5

0.5

1
1.5
2
2.5
Drain/Source Voltage (V)

3.5
Fig. 2.5-6

VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-13

Differential Varactors
Vcontrol

Vcontrol
A

B
Diode Varactor

Vcontrol
B

VDD
Inversion-PMOS Varactor

Accumulation-PMOS Varactor
Fig. 040-01

Varactor
Diode
I-MOS
A-MOS

fL fH

fC

Tuning
Range

(GHz) (GHz)
1.731.83 10.9%
1.93
1.711.81 11.0%
1.91
1.701.80 10.6%
1.89

P. Andreani and S. Mattisson, On the Use of MOS Varactors in RF VCOs, IEEE J. of Solid-State Circuits, Vol. 35, No. 6, June 2000, pp. 905910.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-14

Compensated MOS-Capacitors in Depletion with Substrate Biasing


Substrate biasing keeps the MOS capacitors in a broad depletion region and extends the
usable voltage range and achieves a first-order cancellation of the nonlinearity effect.
Principle:
M1

VSB1

M2

VSB2
Fig. 040-02

T. Tille, J. Sauerbrey and D. Schmitt-Landsiedel, A 1.8V MOSFET-Only Modulator Using Substrate Biased Depletion-Mode MOS Capacitors
in Series Compensation, IEEE J. of Solid-State Circuits, Vol. 36, No. 7, July 2001, pp. 1041-1047.
CMOS Analog Circuit Design
P.E. Allen - 2004
Chapter 2 Section 4 (5/02/04)

Page 2.4-15

Compensated MOS-Capacitors in Depletion Continued


Measured CV plot of a series compensated MOS capacitor with different substrate biases
(0.25m CMOS, tox = 5nm, W1=W2=20m and L1=L2=20m):

Example of a realization of the series


compensation without using floating
batteries.

M1

VS/D

M2

B
Keep the S/D at the lowest
potential to avoid forward
biasing the bulk-source.
Fig. 040-03

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-16

MOS Capacitors - Continued


Polysilicon-Oxide-Polysilicon (Poly-Poly):
A

B
IOX
IOX

Polysilicon II

IOX

Polysilicon I

FOX

FOX

substrate

Best possible capacitor for analog circuits


Less parasitics
Voltage independent
Possible approach for increasing the voltage linearity:
Top Plate

Top Plate

Bottom Plate

Bottom Plate

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-17

Implementation of Capacitors using Available Interconnect Layers


M3
M2
B

M1

Poly
T

M3
T

M2
M1

M2
B

CMOS Analog Circuit Design

B
M1

Poly

M2
M1

Fig. 2.5-8

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-18

Horizontal Metal Capacitors


Capacitance between conductors on the same level and use lateral flux.
Top view:
Fringing field
Metal

Metal

Metal 3

Metal 2

Metal 1

Side view:

Fig2.5-9

These capacitors are sometimes called fractal capacitors because the fractal patterns are
structures that enclose a finite area with a near-infinite perimeter.
The capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-19

More Detail on Horizontal Metal Capacitors


Some of the possible metal capacitor structures include:
1.) Horizontal parallel plate (HPP).

030909-01

2.) Parallel wires (PW):

Lateral View

030909-02

Top View

R. Aparicio and A. Hajimiri, Capacity Limits and Matching Properties of Integrated Capacitors, IEEE J. of Solid-State Circuits, vol. 37, no. 3,
March 2002, pp. 384-393.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-20

Horizontal Metal Capacitors - Continued


3.) Vertical parallel plates (VPP):

Vias

030909-03

4.) Vertical bars (VB):

Vias

030909-04

Lateral View

Top View

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-21

Horizontal Metal Capacitors - Continued


Experimental results for a CMOS process with 3 layers of metal, Lmin =0.5m, tox =
0.95m and tmetal = 0.63m for the bottom 2 layers of metal.
Structure

Cap. Density
(aF/m2)

Caver. Std. Dev.


(fF)
Caver.
(pF)

fres.
Q @ Rs () Breakdown (V)
(GHz) 1 GHz

VPP
158.3
18.99
103
0.0054 3.65
14.5
0.57
355
PW
101.5
33.5
315
0.0094 1.1
8.6
0.55
380
HPP
35.8
6.94
427
0.0615 6.0
21
1.1
690
Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24m, tox
= 0.7m and tmetal = 0.53m for the bottom 5 layers of metal. All capacitors = 1pF.
Structure Cap. Density Caver. Area Cap.
(aF/m2)
(pF) (m2) Enhanc
(1 pF)
ement
VPP
1512.2
1.01 670
7.4
VB
1281.3
1.07 839.7
6.3
HPP
203.6
1.09 5378
1.0
MIM
1100
1.05 960.9
5.4
CMOS Analog Circuit Design

Std.
Dev.
(fF)
5.06
14.19
26.11
-

Q @ Breakfres.
Caver. (GHz) 1 GHz down
(V)
0.0050 >40
83.2
128
0.0132 37.1 48.7
124
0.0239 21
63.8
500
11
95
P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-22

Horizontal Metal Capacitors - Continued


Histogram of the capacitance distribution for the above case (1 pF):
Number of dice

12
HPP
VPP
PW

10
8
6
4
2
0

94

96

98

100

102

104

106
030909-05

Caver

Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24m, tox
= 0.7m and tmetal = 0.53m for the bottom 5 layers of metal. All capacitors = 10pF.
Structure Cap. Density Caver. Area Cap.
(aF/m2)
(pF) (m2) Enhanc
(10 pF)
ement
VPP
1480.0
11.46 7749
8.0
VB
1223.2
10.60 8666
6.6
HPP
183.6
10.21 55615
1.0
MIM
1100
10.13 9216
6.0
CMOS Analog Circuit Design
Chapter 2 Section 4 (5/02/04)

Std.
Dev.
(fF)
73.43
73.21
182.1
-

Q @ Breakfres.
Caver. (GHz) 1 GHz down
(V)
0.0064 11.3 26.6
125
0.0069 11.1 17.8
121
0.0178 6.17 23.5
495
4.05 25.6
P.E. Allen - 2004
Page 2.4-23

Capacitor Errors
1.) Oxide gradients
2.) Edge effects
3.) Parasitics
4.) Voltage dependence
5.) Temperature dependence

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-24

Capacitor Errors - Oxide Gradients


Error due to a variation in oxide thickness across the wafer.
A1

A2

A1

A2

x1

x2

x1

No common centroid
layout
Common centroid
layout

Only good for one-dimensional errors.


An alternate approach is to layout numerous repetitions and connect them randomly to
achieve a statistical error balanced over the entire area of interest.
A

0.2% matching of poly resistors was achieved using an array of 50 unit resistors.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-25

Capacitor Errors - Edge Effects


There will always be a randomness on the definition of the edge.
However, etching can be influenced by the presence of adjacent structures.
For example,
Matching of A and B are disturbed by the presence of C.

C
A

Improved matching achieve by matching the surroundings of A and B.

C
A

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-26

Capacitor Errors - Area/Periphery Ratio


The best match between two structures occurs when their area-to-periphery ratios are
identical.
Let C1 = C1 C1 and C2 = C2 C2
where
C = the actual capacitance
C = the desired capacitance (which is proportional to area)
C = edge uncertainty (which is proportional to the periphery)
Solve for the ratio of C2/C1,
C2
C2
C1 C2
C2 C1
C2 C2 C2 C2 1 C2 C2
- C
=
=

C1 C1 C1 C1
C1 C1
C2
C1 C1
C2 +
1
1 C1
If

C2 C1
C2 C2
=
,
then
C2
C1
C1 = C1

Therefore, the best matching results are obtained when the area/periphery ratio of C2 is
equal to the area/periphery ratio of C1.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-27

Capacitor Errors - Relative Accuracy


Capacitor relative accuracy is proportional to the area of the capacitors and inversely
proportional to the difference in values between the two capacitors.
For example,
0.04

Relative Accuracy

Unit Capacitance = 0.5pF


0.03
Unit Capacitance = 1pF
0.02

0.01
Unit Capacitance = 4pF
0.00

CMOS Analog Circuit Design

4
8
16
Ratio of Capacitors

32

64

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-28

Capacitor Errors - Parasitics


Parasitics are normally from the top and bottom plate to ac ground which is typically the
substrate.
Top Plate
Top
plate
parasitic

Desired
Capacitor
Bottom
plate
parasitic

Bottom Plate

Top plate parasitic is 0.01 to 0.001 of Cdesired


Bottom plate parasitic is 0.05 to 0.2 Cdesired

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-29

Other Considerations on Capacitor Accuracy


Decreasing Sensitivity to Edge Variation:
A

A'

B'

Sensitive to edge variation in


both upper andlower plates

A'
B'

B
Sensitive to edge varation in
upper plate only.

Fig. 2.6-13

A structure that minimizes the ratio of perimeter to area (circle is best).

Top Plate
of Capacitor

Bottom plate
of capacitor

Fig. 2.6-14
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-30

Definition of Temperature and Voltage Coefficients


In general a variable y which is a function of x, y = f(x), can be expressed as a Taylor
series,
y(x = x0) y(x0) + a1(x- x0) + a2(x- x0)2+ a3(x- x0)3 +
where the coefficients, ai, are defined as,
df(x) |
1 d2f(x) |
a1 = dx x=x0 , a2 = 2 dx2 x=x0 , .
The coefficients, ai, are called the first-order, second-order, . temperature or voltage
coefficients depending on whether x is temperature or voltage.
Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a term
called fractional temperature coefficient, TCF, which is defined as,
1
df(T) |
TCF(T=T0) = f(T=T ) dT T=T0 parts per million/C (ppm/C)
0
or more simply,
1 df(T)
TCF = f(T) dT parts per million/C (ppm/C)
A similar definition holds for fractional voltage coefficient.
CMOS Analog Circuit Design
Chapter 2 Section 4 (5/02/04)

P.E. Allen - 2004


Page 2.4-31

Capacitor Errors - Temperature and Voltage Dependence


Polysilicon-Oxide-Semiconductor Capacitors
Absolute accuracy 10%
Relative accuracy 0.2%
Temperature coefficient +25 ppm/C
Voltage coefficient -50ppm/V
Polysilicon-Oxide-Polysilicon Capacitors
Absolute accuracy 10%
Relative accuracy 0.2%
Temperature coefficient +25 ppm/C
Voltage coefficient -20ppm/V
Accuracies depend upon the size of the capacitors.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-32

RESISTORS
MOS Resistors - Source/Drain Resistor
Metal
p+

SiO2

FOX

FOX
n- well

p- substrate

Fig. 2.5-16

Diffusion:
Ion Implanted:
10-100 ohms/square
500-2000 ohms/square
Absolute accuracy = 35%
Absolute accuracy = 15%
Relative accuracy=2% (5m), 0.2% (50m) Relative accuracy=2% (5m), 0.15% (50m
Temperature coefficient = +1500 ppm/C
Temperature coefficient = +400 ppm/C
Voltage coefficient 200 ppm/V
Voltage coefficient 800 ppm/V
Comments:
Parasitic capacitance to substrate is voltage dependent.
Piezoresistance effects occur due to chip strain from mounting.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-33

Polysilicon Resistor
Metal

;;;;;
Polysilicon resistor

;;

FOX

p- substrate

Fig. 2.5-17

30-100 ohms/square (unshielded)


100-500 ohms/square (shielded)
Absolute accuracy = 30%
Relative accuracy = 2% (5 m)
Temperature coefficient = 500-1000 ppm/C
Voltage coefficient 100 ppm/V
Comments:
Used for fuzzes and laser trimming
Good general resistor with low parasitics
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-34

N-well Resistor
Metal
n+

FOX

FOX

FOX

n- well
p- substrate

Fig. 2.5-18

1000-5000 ohms/square
Absolute accuracy = 40%
Relative accuracy 5%
Temperature coefficient = 4000 ppm/C
Voltage coefficient is large 8000 ppm/V
Comments:
Good when large values of resistance are needed.
Parasitics are large and resistance is voltage dependent

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-35

MOS Passive RC Component Performance Summary


Component Type
Poly-oxide-semiconductor Capacitor
Poly-Poly Capacitor
Diffused Resistor
Ion Implanted
Resistor
Poly Resistor
n-well Resistor

CMOS Analog Circuit Design

Range of Absolute Relative Temperature Voltage


Values
Accuracy Accuracy Coefficient Coefficient
0.35-0.5
10%
0.1%
20ppm/C 20ppm/V
2
fF/m
0.3-0.4
20%
0.1%
25ppm/C 50ppm/V
fF/m2
10-100
35%
2%
1500ppm/C 200ppm/V
/sq.
0.5-2
15%
2%
400ppm/C 800ppm/V
k/sq.
30-200
30%
2%
1500ppm/C 100ppm/V
/sq.
1-10 k/sq.
40%
5%
8000ppm/C 10kppm/V

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-36

Future Technology Impact on Passive RC Components


What will be the impact of scaling down in CMOS technology?
Resistors probably little impact
Capacitors a different story
The capacitance can be divided into gate capacitance and overlap capacitance.
Gate capacitance varies with external voltage changes
Overlap capacitances are constant with respect to external voltage changes
As the channel length decreases, the gate capacitance becomes less of the total
capacitance and consequently the Cmax/Cmin will decrease. However, the Q of the
capacitor will increase because the physical dimensions are getting smaller.
Best capacitor for future scaled CMOS?
The standard mode CMOS depeletion capacitor because Cmax/Cmin is larger than
that for the accumulation mode and Q should be sufficient.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-37

INDUCTORS
Inductors
What is the range of values for on-chip inductors?

;;;;;;
12

Inductor area is too large

Inductance (nH)

10
8
6

L = 50

;;;;;;
4

Interconnect parasitics
are too large

0 0

10

20
30
40
Frequency (GHz)

50

Fig. 6-5

Consider an inductor used to resonate with 5pF at 1000MHz.


1
1
= 5nH
L= 2 2 =
4 fo C (2109)25x10-12
Note: Off-chip connections will result in inductance as well.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-38

Candidates for inductors in CMOS technology are:


1.) Bond wires
2.) Spiral inductors
3.) Multi-level spiral
4.) Solenoid
Bond wire Inductors:

Fig.6-6

Function of the pad distance d and the bond angle


Typical value is 1nH/mm which gives 2nH to 5nH in typical packages
Series loss is 0.2 /mm for 1 mil diameter aluminum wire
Q 60 at 2 GHz

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-39

Planar Spiral Inductors


Spiral Inductors on a Lossy Substrate:
L

C1

C2

R1

R2

Fig. 16-7

Design Parameters:
Inductance,L = (Lself + Lmutual)
L
Quality factor, Q = R
1
Self-resonant frequency: fself =
LC
Trade-off exists between the Q and self-resonant frequency
Typical values are L = 1-8nH and Q = 3-6 at 2GHz
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-40

Planar Spiral Inductors - Continued


Inductor Design
I

;;;;;

SiO2

ID

Silicon

I
Nturns = 2.5

Fig. 6-9

Typically: 3 < Nturns < 5 and S = Smin for the given current
Select the OD, Nturns, and W so that ID allows sufficient magnetic flux to flow
through the center.
Loss Mechanisms:

Skin effect

Capacitive substrate losses

Eddy currents in the silicon


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-41

Planar Spiral Inductors - Continued


Influence of a Lossy Substrate
L

C1

C2

R1

R2

CLoad

Fig. 12.2-13

where:
L is the desired inductance
R is the series resistance
C1 and C2 are the capacitance from the inductor to the ground plane
R1 and R2 are the eddy current losses in the silicon
Guidelines for using spiral inductors on chip:
Lossy substrate degrades Q at frequencies close to fself
To achieve an inductor, one must select frequencies less than fself
The Q of the capacitors associated with the inductor should be very high
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-42

Planar Spiral Inductors - Continued


Comments concerning implementation:
1.) Put a metal ground shield between the inductor and the silicon to reduce the
capacitance.
Should be patterned so flux goes through but electric field is grounded
Metal strips should be orthogonal to the spiral to avoid induced loop current
The resistance of the shield should be low to terminate the electric field
2.) Avoid contact resistance wherever possible to keep the series resistance low.
3.) Use the metal with the lowest resistance
and furtherest away from the substrate.
4.) Parallel metal strips if other metal levels
are available to reduce the resistance.
Example:

Fig. 2.5-12

CMOS Analog Circuit Design


Chapter 2 Section 4 (5/02/04)

P.E. Allen - 2004


Page 2.4-43

Multi-Level Spiral Inductors


Use of more than one level of metal to make the inductor.
Can get more inductance per area
Can increase the interwire capacitance so the different levels are often offset to get
minimum overlap.
Multi-level spiral inductors suffer from contact resistance (must have many parallel
contacts to reduce the contact resistance).
Metal especially designed for inductors is top level approximately 4m thick.

Q = 5-6, fSR = 30-40GHz. Q = 10-11, fSR = 15-30GHz1. Good for high L in small area.
1

The skin effect and substrate loss appear to be the limiting factor at higher frequencies of self-resonance.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-44

Inductors - Continued
Self-resonance as a function of inductance. Outer dimension of inductors.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-45

Solenoid Inductors
Example:
Upper Metal

ent

;;
;;;;;;;;
;;
Coil

Coil

Cur

Contact
Vias
rent

Curr

Magnetic Flux

Lower Metal

SiO2

Silicon

Fig. 6-11

Comments:
Magnetic flux is small due to planar structure
Capacitive coupling to substrate is still present
Potentially best with a ferromagnetic core

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Page 2.4-46

Transformers
Transformer structures are easily obtained using stacked inductors as shown below for a
1:2 transformer.
Method of reducing the
inter-winding capacitances.

Measured 1:2 transformer voltage gains:


4 turns

8 turns

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 4 (5/02/04)

Transformers Continued
A 1:4 transformer:
Structure-

3 turns

Page 2.4-47

Measured voltage gain-

Secondary

(CL = 0, 50fF, 100fF, 500fF and 1pF.


CL is the capacitive loading on the
secondary.)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-1

SECTION 2.5 - OTHER CONSIDERATIONS OF CMOS TECHNOLOGY


Lateral Bipolar Junction Transistor
P-Well Process, NPN Lateral:
VDD

n+

Base

Emitter

Collector

p+

n+

n+

p-well
n-substrate

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-2

Lateral Bipolar Junction Transistor - Continued


Field-aided LateralF 50 to 100 depending on the process
Keep channel
from forming
VDD

n+

Base

Emitter VGate Collector

n+

p+

n+

p-well
n-substrate

Good geometry matching


Low 1/f noise (if channel doesnt form)
Acts like a photodetector with good efficiency

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-3

Geometry of the Lateral PNP BJT


Minimum Size layout of a single
emitter dot lateral PNP BJT:

n-well

p-diffusion
contact

40 emitter dot LPNP transistor (total device area


is 0.006mm2 in a 1.2m CMOS process):

p-substrate
diffusion

Base
n-well
contact

Lateral
Collector
Emitter
31.2
m

71.4
m

Base

Gate
Lateral
Collector

V SS
Emitter

V SS

Gate
(poly)

84.0 m

33.0 m

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-4

Performance of the Lateral PNP BJT


Schematic:
Emitter
Gate

Base
Lateral
Collector

Vertical
Collector
( V SS )

L vs ICL for the 40 emitter


dot LPNP BJT:

Lateral efficiency versus IE for the 40


emitter dot LPNP BJT:

V CE =
4.0 V

150

1.0

Lateral Efficiency

130

Lateral

VCE =
4.0 V

0.8

110
V CE =
0.4 V

90

VCE =
0. 4V

0.6

0.4

0.2

70

50
1 nA

0
1 nA

10 nA

100 nA
1 A
10 A
Lateral Collector Current

CMOS Analog Circuit Design

100 A

1 mA

10 nA

100 nA
1 A
10 A
Emitter Current

100 A

1 mA

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-5

Performance of the Lateral PNP BJT - Continued


Typical Performance for the 40 emitter dot LPNP BJT:
Transistor area
Lateral
Lateral efficiency
Base resistance
En @ 5 Hz

0.006 mm2
90
0.70
150

En (midband)

1.92 nV / Hz
3.2 Hz

fc (En)
In @ 5 Hz

2.46 nV / Hz

3.53 pA / Hz

In (midband)

0.61 pA / Hz
162 Hz
85 MHz
16 V

fc (In)
fT
Early voltage

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-6

;;

High Voltage MOS Transistor


The well can be substituted for the drain giving a lower conductivity drain and therefore
higher breakdown voltage.
NMOS in n-well example:
Substrate
Source
Drain
Gate
Oxide

Polysilicon

n+
Source

Channel

n+

p+

n-well

p-substrate

Fig. 190-07

Drain-substrate/channel can be as large as 20V or more.


Need to make the channel longer to avoid breakdowns via the channel.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-7

Latch-up in CMOS Technology


Latch-up Mechanisms:
1. SCR regenerative switching action.
2. Secondary breakdown.
3. Sustaining voltage breakdown.
Parasitic lateral PNP and vertical NPN BJTs in a p-well CMOS technology:

;;
;;
;;
;;
;;
;;
;;;;;;;;;;
;;
;;
;;;;
;; ;;
;;;;
;;
;;;
y;; ;;;
y;;;;
VDD

n+

p+

p+

p-well

n+

VSS

p+

n+

RN-

RP-

n- substrate

Fig. 190-08

VDD

Equivalent circuit of the SCR


formed from the parasitic BJTs:

VDD

RNA
Vin VSS

Vout
B
RP-

VSS
VSS
CMOS Analog Circuit Design

Fig. 190-09

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-8

Preventing Latch-Up in a P-Well Technology


1.) Keep the source/drain of the MOS device not in the well as far away from the well as
possible. This will lower the value of the BJT betas.
2.) Reduce the values of RN- and RP-. This requires more current before latch-up can
occur.
3.) Make a p- diffusion around the p-well. This shorts the collector of Q1 to ground.
n+

p-channel transistor
guard bars

VDD

FOX

p+

n-channel transistor
guard bars

VSS

FOX

FOX

FOX

FOX

p-well

FOX

FOX

n- substrate
Figure 190-10

For more information see R. Troutman, CMOS Latchup, Kluwer Academic Publishers.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-9

Electrostatic Discharge Protection (ESD)


Objective: To prevent large external voltages from destroying the gate oxide.
Electrical equivalent circuit
VDD
p+ to n-well
diode
To internal gates
n+ to p-substrate
diode

p+ resistor

Bonding
Pad

VSS
Implementation in CMOS technology
Metal

FOX

n+

FOX

p+

FOX

n-well
p-substrate
Fig. 190-11
CMOS Analog Circuit Design
Chapter 2 Section 5 (5/02/04)

P.E. Allen - 2004


Page 2.5-10

Temperature Characteristics of Transistors


Fractional Temperature Coefficient
1 x
TCF =x T Typically in ppm/C
MOS Transistor
VT = V(T0) + (T-T0) + , where -2.3mV/C (200K to 400K)
= KT-1.5
BJT Transistor
Reverse Current, IS:
1 IS 3 1 VG0
IS T = T + T kT/q
Empirically, IS doubles approximately every 5C increase
Forward Voltage, vD:
vD
VG0 - vD 3kT/q
=
- T -2mV/C at vD = 0.6V

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-11

Noise in Transistors
Shot Noise
i2 = 2qIDf (amperes2)
where
q = charge of an electron
ID = dc value of iD
f = bandwidth in Hz
i2
Noise current spectral density = f (amperes2/Hz)
Thermal Noise
Resistor:
v2 = 4kTRf (volts2)
MOSFET:
8kTgmf
iD 2 =
(ignoring bottom gate)
3
where
k = Boltzmanns constant
R = resistor or equivalent resistor in which the thermal noise is occurring.
gm = transconductance of the MOSFET
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 5 (5/02/04)

Page 2.5-12

Noise in Transistors - Continued


Flicker (1/f) Noise
Ia

iD2 = Kffb f

where
Kf = constant (10-28 Faradamperes)
a = constant (0.5 to 2)
b = constant (1)

Noise power
spectral density
1/f

log(f)
CMOS Analog Circuit Design

Fig. 190-12
P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-1

SECTION 2.6 INTEGRATED CIRCUIT LAYOUT


Matching Concepts
1.) Unit matching principle Always implement two unequal components by an integer
number of unit components.
1.0

1.0

1.5

0.5

0.5

0.5

1.5

0.5

0.5

Fig. 2.6-01

2.) Common-centroid layout (illustrated above).


3.) Elimination of mismatch due to
surrounding material

Fig. 2.6-02

4.) Minimize the ratio of the perimeter to the area (a circle is optimum).
5.) For parallel plates make one larger than the other to eliminate alignment problems.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-2

Matching Concepts - Continued


6.) Maintain a constant area-to-perimeter ratio between matching elements.
Yiannoulos path A serpentine structure that maintains a constant area-to-perimeter
ratio and allows efficient use of area.
One unit

Total perimeter
is 25 units

Total perimeter
is 36 units

Etch compensation

Total area is
12.5 units

Fig. 2.6-03

Total area is
18 units.

Both structures have a periphery/area ratio of 2.


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-3

MOS Transistor Layout


Example of the layout of a single MOS transistor:
Metal
FOX
Active area
drain/source
Contact
Cut

FOX

;;
;;
;;
;;
;;
Polysilicon
gate
L

Active area
drain/source
Fig. 2.6-04

Metal 1

Comments:
Make sure to contact the source and drain with multiple contacts to evenly distribute
the current flow under the gate.
Minimize the area of the source and drain to reduce bulk-source/drain capacitance.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-4

MOS Transistor Layout - Continued


For best matching, the transistor stripes should be oriented in the same direction (not
orthogonal).
Photolithographic invariance (PLI) are transistors that exhibit identical orientation.
Examples of the layout of matched MOS transistors:
1.) Examples of mirror symmetry and photolithographic invariance.

;;
;
;;
;
;;
;
;;;
Mirror Symmetry

CMOS Analog Circuit Design

;;;;
;;
;;;;
;;

Photolithographic Invariance
Fig. 2.6-05

P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-5

MOS Transistor Layout - Continued


2.) Two transistors sharing a common source and laid out to achieve both
photolithographic invariance and common centroid.

;;;
;;;
;;
;
;;;

Metal 2

Via 1

;;;;;;;;;
;;;;;;;;;
;;;;
;
;;
;;
;
;;;;;;;;
Metal 1

Fig. 2.6-06

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-6

MOS Transistor Layout - Continued


3.) Compact layout of the previous example.
Metal 2

;;
;;;
;;
;;
;;;
;;
;;
;;;
;;
;;;;;;;

Via 1

Metal 2

CMOS Analog Circuit Design

Metal 1

Fig. 2.6-07

P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-7

Resistor Layout
Direction of current flow

W
T
Area, A
L

Fig. 2.6-15

Resistance of a conductive sheet is expressed in terms of


L L
R = A = W T ()
where
= resistivity in -m
Ohms/square:
L
L
R = T W = S W ()
where
S is a sheet resistivity and has the units of ohms/square
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-8

Example of Resistor Layouts


Metal

Metal
FOX

FOX

FOX

Substrate
Active area (diffusion)

FOX

Active area (diffusion) Well diffusion


Active area

Contact

FOX

Substrate

Active area or Polysilicon W

Well diffusion

Contact
Cut

Cut
L

Metal 1

Diffusion or polysilicon resistor

Metal 1

Well resistor

Fig. 2.6-16

Corner corrections:
0.5

1.45

1.25

Fig. 2.6-16B

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-9

Example 2.6-1 Resistance Calculation


Given a polysilicon resistor like that drawn above with W=0.8m and L=20m, calculate
s (in /), the number of squares of resistance, and the resistance value. Assume that
for polysilicon is 9 10-4 -cm and polysilicon is 3000 thick. Ignore any contact
resistance.
Solution
First calculate s.
9 10-4 -cm

s = T = 3000 10-8 cm = 30 /
The number of squares of resistance, N, is
20m
L
N = W = 0.8m = 25
giving the total resistance as
R = s = 30 25 = 750

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-10

Capacitor Layout
Double-polysilicon capacitor
Metal

Triple-level metal capacitor.

Polysilicon 2

Metal 3

FOX
Substrate

;;;;
;;;;
;;;;
;;;;
;;;;
;;;;

FOX
Substrate

Polysilicon gate

Polysilicon 2

Cut

CMOS Analog Circuit Design

Metal 2 Metal 1

Polysilicon gate

Metal 3

Metal 2 Metal 1 Metal 3


Via 2

Via 2
Cut

Metal 2
Via 1

Metal 1
Metal 1
Fig. 2.6-17

P.E. Allen - 2004

Chapter 2 Section 6 (5/02/04)

Page 2.6-11

Design Rules
Design rules are geometrical constraints that guarantee the proper operation of a circuit
implemented by a given CMOS process.
These rules are necessary to avoid problems such as device misalignment, metal
fracturing, lack of continuity, etc.
Design rules are expressed in terms of minimum dimensions such as minimum values of:
- Widths
- Separations
- Extensions
- Overlaps
Design rules typically use a minimum feature dimension called lambda. Lambda is
usually equal to the minimum channel length.
Minimum resolution of the design rules is typically half lambda.
In most processes, lambda can be scaled or reduced as the process matures.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-1

SECTION 2.7 - BIPOLAR TRANSISTOR (OPTIONAL)


Major Processing Steps for a Junction Isolated BJT Technology
Start with a p substrate.
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
6. p+ ohmic contact
7. Contact etching
8. Metal deposition and etching
9. Passivation and bond pad opening

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-2

Implantation of the Buried Layer (Mask Step 1)


Objective of the buried layer is to reduce the collector resistance.

TOP
VIEW

n++ implantation for buried layer


SIDE
VIEW

p substrate

p-

p+

ni

n-

n+

Metal

Fig.2.7-1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-3

Epitaxial Layer (No Mask Required)


The objective is to provide the proper n-type doping in which to build the npn BJT.
Assume the n+ buried layer can be seen underneath the epitaxial collector

TOP
VIEW

n collector

Epitaxial
Region

SIDE
VIEW
n+ buried layer
p substrate

p+

CMOS Analog Circuit Design

p-

ni

n-

n+

Metal

Fig.2.7-2

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-4

p+ isolation diffusion (Mask Step 2)


The objective of this step is to surround (isolate) the npn BJT by a p+ diffusion. These
regions also permit contact to the substrate from the surface.
Assume that the n+ buried region can be seen

TOP
VIEW

n collector

p+
isolation

p+
isolation

p+
isolation
n collector

SIDE
VIEW

n+ buried layer
p substrate

p+

p-

n-

ni

n+

Metal

Fig.2.7-3

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-5

Base p-type diffusion (Mask Step 3)


The step provides the p-type base for the npn BJT.

TOP
VIEW
n collector

p base

p+
isolation

pisolation

p base
n collector

SIDE
VIEW

n+ buried layer
p substrate

p+
CMOS Analog Circuit Design

p-

ni

n-

n+

Metal

Fig.2.7-4

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-6

Emitter n+ diffusion (Mask Step 4)


This step implements the n+ emitter of the npn BJT and the collector ohmic contact.

TOP
VIEW

p+
isolation

n+

p+
isolation

n+ emitter
p base

n collector

SIDE
VIEW

n+ buried layer
p substrate

p+

p-

n-

ni

n+

Metal

Fig.2.7-5

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-7

p+ ohmic contact (Mask Step 5)


This step permits ohmic contact to the base region if it is not doped sufficiently high.

TOP
VIEW

p+
isolation

n+

p+

p+
isolation

n+ emitter
p base

n collector

SIDE
VIEW

n+ buried layer
p substrate

p+
CMOS Analog Circuit Design

p-

ni

n-

n+

Metal

Fig.2.7-6

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-8

;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;; ;;;;;

Contact etching (Mask Step 6)


This step opens up the areas in the dielectric area which metal will contact.

TOP
VIEW

Dielectric Layer

p+
isolation

SIDE
VIEW

n+

p+

p+
isolation

n+ emitter

p base

n collector

n+ buried layer
p substrate

p+

p-

n-

ni

n+

Metal

Fig.2.7-7

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-9

Metal deposition and etching (Mask Step 7)


In this step, metal is deposited over the entire wafer and removed where it is not wanted.

TOP
VIEW

;;;;
;;
;;
;;;;
;;;;;;;; ;;;;
p+
isolation

SIDE
VIEW

n+

p+

n+ emitter

p base

p+
isolation

n collector

n+ buried layer
p substrate
Fig.2.7-8

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-10

Passivation (Mask Step 8)


Cover the entire wafer with glass and open the area over bond pads (requires another
mask).

TOP
VIEW

;;;;;;;;;;;;
;;;;;;;; ;;;;
;;;;;;;; ;;;;

Passivation

p+
isolation

SIDE
VIEW

p+

n+

p+
isolation

n+ emitter

p base

n collector

n+ buried layer
p substrate
Fig.2.7-9

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-11

Typical Impurity Concentration Profile for the npn BJT


Taken along the line from the surface indicated in the last slide.
p

n+

1020
Substrate Doping Level

1019
1018
Epitaxial
collector
doping level

1017
1016
1015
1014
1013
1012

Emitter

Impurity Concentration (cm-3)

1021 n+

CMOS Analog Circuit Design

Base Collector

Buried Layer

10

11

Substrate

12

x, Depth from the


surface (microns)
Fig. 2.7-10

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-12

Substrate pnp BJT


Collector is always connected to the substrate potential which is the most negative DC
potential.

TOP
VIEW

;;;;
;;;;
;;;;;;
p+
isolation/
collector

p+
isolation/
collector

p+

n+

p emitter

n base
SIDE
VIEW
p collector/substrate

p+

p-

n-

ni

n+

Metal

Fig.2.7-11

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-13

Lateral pnp BJT


Collector is not constrained to a fixed dc potential.

TOP
VIEW

;;;;;;;;;;;;;
p+
isolation

SIDE
VIEW

p+

p+

p collector

p emitter

n+

p+
isolation

n base

n+ buried layer
p substrate

p+

CMOS Analog Circuit Design

p-

ni

n-

n+

Metal

Fig.2.7-12

P.E. Allen - 2004

Chapter 2 Section 7 (5/02/04)

Page 2.7-14

Types of Modifications to the Standard npn Technology


1.) Dielectric isolation - Isolation of the transistor from the substrate using an oxide
layer.
2.) Double diffusion - A second, deeper n+ emitter diffusion is used to create JFETs.
3.) Ion implanted JFETs - Use of an ion implantation to create the upper gate of a pchannel JFET
4.) Superbeta transistors - Use of a very thin base width to achieve higher values of F.
5.) Double diffused pnp BJT - Double diffusion is used to build a vertical pnp transistor
whose performance more closely approaches that of the npn BJT.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-1

SECTION 2.8 - BiCMOS TECHNOLOGY (OPTIONAL)


Typical 0.5m BiCMOS Technology
Masking Sequence:
13. PMOS lightly doped drain
1. Buried n+ layer
2. Buried p+ layer
14. n+ source/drain
3. Collector tub
15. p+ source/drain
4. Active area
16. Silicide protection
5. Collector sinker
17. Contacts
6. n-well
18. Metal 1
7. p-well
19. Via 1
8. Emitter window
20. Metal 2
9. Base oxide/implant
21. Via 2
10. Emitter implant
22. Metal 3
11. Poly 1
23. Nitride passivation
12. NMOS lightly doped drain
Notation:
BSPG = Boron and Phosphorus doped Silicate Glass (oxide)
Kooi Nitride = A thin layer of silicon nitride on the silicon surface as a result of the
reaction of silicon with the HN3 generated, during the field oxidation.
TEOS = Tetro-Ethyl-Ortho-Silicate. A chemical compound used to deposit conformal
oxide films.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-2

n+ and p+ Buried Layers


Starting Substrate:

1m

p-substrate
BiCMOS-01

5m

n+ and p+ Buried Layers:


NPN Transistor
n+ buried layer

p+ buried
layer

PMOS Transistor

NMOS Transistor

n+ buried layer

p+ buried layer

1m

p-substrate
BiCMOS-02

5m

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-3

Epitaxial Growth
NPN Transistor

n-well

p-well

n+ buried layer

p+ buried
layer

PMOS Transistor

NMOS Transistor

n-well

p-well

n+ buried layer

p-type
Epitaxial
Silicon

p+ buried layer

1m

p-substrate
BiCMOS-03

5m

Comment:
As the epi layer grows vertically, it assumes the doping level of the substrate beneath it.
In addition, the high temperature of the epitaxial process causes the buried layers to
diffuse upward and downward.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-4

Collector Tub
NPN Transistor
Original Area of
CollectorTub Implant
Collector Tub

n+ buried layer

PMOS Transistor

p-well

p+ buried
layer

n-well

n+ buried layer

NMOS Transistor

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-04

5m

Comment:
The collector area is developed by an initial implant followed by a drive-in diffusion to
form the collector tub.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-5

Active Area Definition


NPN Transistor

PMOS Transistor

NMOS Transistor
Nitride
-Silicon

Collector Tub

n+ buried layer

p-well

p+ buried
layer

n-well

n+ buried layer

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-05

5m

Comment:
The silicon nitride is use to impede the growth of the thick oxide which allows contact
to the substrate
-silicon is used for stress relief and to minimize the birds beak encroachment
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-6

Field Oxide

FOX

NPN Transistor
FOX
Collector Tub

PMOS Transistor
Field Oxide
p-well

n+ buried layer

p+ buried
layer

NMOS Transistor
Field Oxide

n-well

Field Oxide
p-type
Epitaxial
Silicon

p-well

n+ buried layer

p+ buried layer
1m

p-substrate
BiCMOS-06

5m

Comments:
The field oxide is used to isolate surface structures (i.e. metal) from the substrate

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-7

Collector Sink and n-Well and p-Well Definitions

FOX

NPN Transistor
Collector Sink
FOX
Collector Tub

n+ buried layer

PMOS Transistor
Anti-Punch Through
Threshold Adjust
Field Oxide

Field Oxide

Field Oxide

n-well

p-well

p+ buried
layer

NMOS Transistor
Anti-Punch Through
Threshold Adjust

n+ buried layer

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-07

CMOS Analog Circuit Design

5m

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-8

Base Definition

FOX

NPN Transistor
FOX
Collector Tub

PMOS Transistor
Field Oxide

Field Oxide

p+ buried
layer

Field Oxide

n-well

p-well

n+ buried layer

NMOS Transistor

p-well

n+ buried layer

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-08

5m

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-9

Definition of the Emitter Window and Sub-Collector Implant


NPN Transistor

PMOS Transistor

NMOS Transistor

FOX

FOX

Sacrifical Oxide

Field Oxide

Field Oxide

Field Oxide

n-well

p-well

p-well

Sub-Collector

n+ buried layer

p+ buried
layer

n+ buried layer

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-09

CMOS Analog Circuit Design

5m

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-10

Emitter Implant

FOX

NPN Transistor
Emitter Implant
FOX
Collector Tub

PMOS Transistor
Field Oxide

NMOS Transistor
Field Oxide

Field Oxide

n-well

p-well

p-well

Sub-Collector

n+ buried layer

p+ buried
layer

n+ buried layer

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-10

5m

Comments:
The polysilicon above the base is implanted with n-type carriers

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-11

Emitter Diffusion

FOX

FOX

NPN Transistor

PMOS Transistor
Field Oxide

NMOS Transistor
Field Oxide

Field Oxide

n-well

p-well

p-well

Emitter

n+ buried layer

p+ buried
layer

n+ buried layer

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-11

5m

Comments:
The polysilicon not over the emitter window is removed and the n-type carriers diffuse
into the base forming the emitter

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-12

Formation of the MOS Gates and LD Drains/Sources

FOX

NPN Transistor
FOX

PMOS Transistor
Field Oxide

Field Oxide

p+ buried
layer

Field Oxide

n-well

p-well

n+ buried layer

NMOS Transistor

n+ buried layer

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-12

5m

Comments:
The surface of the region where the MOSFETs are to be built is cleared and a thin gate
oxide is deposited with a polysilicon layer on top of the thin oxide
The polysilicon is removed over the source and drain areas
A light source/drain diffusion is done for the NMOS and PMOS (separately)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-13

Heavily Doped Source/Drain

FOX

FOX

NPN Transistor

PMOS Transistor
Field Oxide

Field Oxide

p+ buried
layer

Field Oxide

n-well

p-well

n+ buried layer

NMOS Transistor

n+ buried layer

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-13

5m

Comments:
The sidewall spacers prevent the heavy source/drain doping from being near the
channel of the MOSFET

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-14

Siliciding

FOX

NPN Transistor
Silicide TiSi2
FOX

PMOS Transistor
Silicide TiSi2
Field Oxide

Field Oxide

p+ buried
layer

Field Oxide

n-well

p-well

n+ buried layer

NMOS Transistor
Silicide TiSi2

n+ buried layer

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-14

5m

Comments:
Siliciding is used to reduce the resistance of the polysilicon and to provide ohmic
contacts to the base, emitter, collector, sources and drains

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-15

Contacts
Tungsten Plugs

FOX

FOX

Tungsten Plugs

TEOS/BPSG/SOG

Field Oxide

Field Oxide

p+ buried
layer

n+ buried layer

TEOS/BPSG/SOG
Field
FieldOxide
Oxide

n-well

p-well

n+ buried layer

Tungsten Plugs

TEOS/BPSG/SOG

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-15

5m

Comments:
A dielectric is deposited over the entire wafer
One of the purposes of the dielectric is to smooth out the surface
Tungsten plugs are used to make electrical contact between the transistors and metal1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-16

Metal1

FOX

Metal1

FOX

Metal1

TEOS/BPSG/SOG

TEOS/BPSG/SOG

Field Oxide

Field Oxide

p+ buried
layer

n+ buried layer

TEOS/BPSG/SOG
Field
FieldOxide
Oxide

n-well

p-well

n+ buried layer

Metal1

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-16

5m

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-17

Metal1-Metal2 Vias

FOX

FOX

Tungsten Plugs

TEOS/BPSG/SOG

TEOS/BPSG/SOG

Field Oxide

Field Oxide

p+ buried
layer

n+ buried layer

TEOS/BPSG/SOG
Field
FieldOxide
Oxide

n-well

p-well

n+ buried layer

Oxide/
SOG/
Oxide

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-17

CMOS Analog Circuit Design

5m

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-18

Metal2
Metal 2

FOX

FOX

Oxide/
SOG/
Oxide
TEOS/BPSG/SOG

TEOS/BPSG/SOG

Field Oxide

Field Oxide

n+ buried layer

p+ buried
layer

Field
FieldOxide
Oxide

n-well

p-well

n+ buried layer

TEOS/BPSG/SOG

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-18

5m

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-19

Metal2-Metal3 Vias
TEOS/
BPSG/
SOG

FOX

FOX

Oxide/
SOG/
Oxide
TEOS/BPSG/SOG

TEOS/BPSG/SOG

Field Oxide

Field Oxide

n+ buried layer

p+ buried
layer

Field
FieldOxide
Oxide

n-well

p-well

n+ buried layer

TEOS/BPSG/SOG

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-19

5m

Comments:
The metal2-metal3 vias will be filled with metal3 as opposed to tungsten plugs
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 8 (5/02/04)

Page 2.8-20

Completed Wafer
Nitride (Hermetically seals the wafer)
Oxide/SOG/Oxide
Metal3

Metal3
Vias

TEOS/
BPSG/
SOG

FOX

FOX

Oxide/
SOG/
Oxide
TEOS/BPSG/SOG

TEOS/BPSG/SOG

Field Oxide

Field Oxide

n+ buried layer

p+ buried
layer

Field
FieldOxide
Oxide

n-well

p-well

n+ buried layer

TEOS/BPSG/SOG

p-well

p-type
Epitaxial
Silicon

p+ buried layer
1m

p-substrate
BiCMOS-20

CMOS Analog Circuit Design


Chapter 2 Section 8 (5/02/04)

5m
P.E. Allen - 2004
Page 2.8-21

SUMMARY
This section has illustrated the major process steps for a 0.5micron BiCMOS
technology.
The performance of the active devices are:
npn bipolar junction transistor:
F = 100-140
BVCEO = 7V
fT = 12GHz,
n-channel FET:
K = 127A/V2
VT = 0.64V
N 0.060
p-channel FET:
VT = -0.63V
P 0.072
K = 34A/V2
Although todays state of the art is 0.25m or 0.18m BiCMOS, the processing steps
illustrated above approximate that which is done in a smaller geometry.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 2 Section 9 (5/02/04)

Page 2.9-1

SECTION 2.9 - SUMMARY


Basic process steps include:
1.) Oxide growth
2.) Thermal diffusion
3.) Ion implantation
4.) Deposition
5.) Etching
6.) Epitaxy
PN junctions are used to electrically isolate regions in CMOS
A simple CMOS technology requires about 8 masks
Bipolar technology provides a good vertical NPN and lateral and substrate PNPs
BiCMOS combines the best of both BJT and CMOS technologies
Passive component compatible with CMOS technology include:
Capacitors - MOS, poly-poly, metal-metal, etc.
Resistors - Diffused, implanted, well, etc.
Inductors - Planar good only at very high frequencies
CMOS technology has a reasonably good lateral BJT
Other considerations in CMOS technology include:
Latch-up
ESD protection
Temperature influence
Noise influence
Design rules are used to preserve the integrity of the technology
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Introduction (5/02/04)

Page 3.0-1

CHAPTER 3 - CMOS MODELS


Chapter Outline
3.1 MOS Structure and Operation
3.2 Large signal MOS models suitable for hand calculations
3.3 Extensions of the large signal MOS model
3.4 Capacitances of the MOSFET
3.5 Small Signal MOS models
3.6 Temperature and noise models for MOS transistors
3.7 BJT models
3.8 SPICE level 2 model
3.9 Models for simulation of MOS circuits
3.10 Extraction of a large signal model for hand calculations from the BSIM3 model
3.11 Summary
Perspective
CMOS
Technology
and
Fabrication

Analog
Integrated
Circuit
Design

CMOS
Transistor and Passive
Component
Modeling
Fig.3.0-1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Introduction (5/02/04)

Page 3.0-2

Philosophy for Models Suitable for Analog Design


The model required for analog design with CMOS technology is one that leads to
understanding and insight as distinguished from accuracy.
Technology
Understanding
and Usage
Updating Model

Comparison of
simulation with
expectations

Thinking Model
Simple,
10% to 50% accuracy

Design Decisions"What can I change to


accomplish ....?"

Updating Technology

Extraction of Simple
Model Parameters
from Computer Models

Expectations
"Ballpark"
Computer Simulation

Refined and
optimized
design

Fig.3.0-02

This chapter is devoted to the simple model suitable for design not using simulation.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Introduction (5/02/04)

Page 3.0-3

Categorization of Electrical Models


Time Dependence
Time Independent
Linear
Linearity

Small-signal, midband
Rin, Av, Rout
(.TF)

Nonlinear DC operating point


iD = f(vD,vG,vS,vB)
(.OP)

Time Dependent
Small-signal frequency
response-poles and zeros
(.AC)
Large-signal transient
response - Slew rate
(.TRAN)

Based on the simulation capabilities of SPICE.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 1 (5/2/04)

Page 3.1-1

3.1 - MOS STRUCTURE AND OPERATION

;;;
;;;

Metal-Oxide-Semiconductor Structure
Bulk/Substrate

Source

Gate

Drain

Polysilicon

p+

n+

Thin Oxide
(10-100nm
100-1000)

n+

p- substrate

Heavily
Doped p

Lightly
Doped p

Intrinsic
Doping

Lightly
Doped n

Heavily Metal
Doped n
Fig.3.1-01

Terminals:
Bulk - Used to make an ohmic contact to the substrate
Gate - The gate voltage is applied in such a manner as to invert the doping of the
material directly beneath the gate to form a channel between the source and drain.
Source - Source of the carriers flowing in the channel
Drain - Collects the carriers flowing in the channel
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 1 (5/2/04)

Page 3.1-2

Formation of the Channel for an Enhancement MOS Transistor

;;;
;; ;;;
;; ;;;
;;;
;;;;
;;
;;;
;; ;;;
;;;
;;;
;;;;;;
;;;

Subthreshold (VG<VT)
VB = 0
VS = 0

VG < VT

VD = 0

Polysilicon

p+

n+

p- substrate
Threshold (VG=VT)
VB = 0

n+

Depletion Region
VG =VT

VS = 0

VD = 0

Polysilicon

p+

n+

n+

Inverted Region

p- substrate

Strong Threshold (VG>VT)


VB = 0
VS = 0

VG >VT

VD = 0

Polysilicon

p+

n+

n+

Inverted Region

p- substrate

Fig.3.1-02

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 1 (5/2/04)

Page 3.1-3

Transconductance Characteristics of an Enhancement NMOS FET when VDS = 0.1V


VGSVT:
VB = 0

;;;
;;
;;;
;; ;;;
;;;
;;;;;;;;;
;; ;;;
;;;
;;;
;;;;;;
;;;
VS = 0

VD = 0.1V
iD

vG =VT

Polysilicon

p+

n+

p- substrate
VGS=2VT:
VB = 0

n+

Depletion Region

VS = 0

VG = 2VT

Polysilicon

p+

VB = 0

0 VT 2VT 3VT

vGS

iD

n+

Inverted Region

VS = 0

VD = 0.1V
iD

n+

p- substrate
VGS=3VT:

iD

VG = 3VT

0
0 VT 2VT 3VT

VD = 0.1V

vGS

iD

Polysilicon

p+

p- substrate

CMOS Analog Circuit Design

n+

n+

Inverted Region

0
0 VT 2VT 3VT

vGS
Fig.3.1-03
P.E. Allen - 2004

Chapter 3 Section 1 (5/2/04)

Page 3.1-4

Output Characteristics of the Enhancement NMOS Transistor for VGS = 2VT


VDS=0:
VB = 0

;;;
;;
;;;
;;;;
;; ;;;
;;;
;;
;;;;
;;;
;;
;;;;
;;;
VS = 0

vG =2VT

Polysilicon

p+

n+

VS = 0

VG = 2VT

n+

VB = 0

VD = 0.5VT
iD

;;;
;;;
;;
;;;;
;;;
VS = 0

VG = 2VT

n+

p- substrate

0.5VT

vDS
VT

iD
VGS = 2VT

n+

Polysilicon

p+

Channel current

p- substrate
VDS=VT:

VGS = 2VT

n+

Polysilicon

p+

iD

Inverted Region

p- substrate
VDS=0.5VT:
VB = 0

VD = 0V
iD

0
0

VD =VT
iD

0.5VT

vDS
VT

iD
VGS = 2VT

n+

A depletion region
forms between the drain and channel

0
0

0.5VT

vDS
Fig.3.1-04

VT

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 1 (5/2/04)

Page 3.1-5

Output Characteristics of the Enhanced NMOS when vDS = 2VT


VGS=VT:
VB = 0

;;;
;;
;;;
;; ;;;
;;;
;;
;;;;
;;;
;;;;;;;;;
;;;
;;;
;;;;;;
;;;
VS = 0

vG =VT

Polysilicon

p+

n+

VD = 2VT
iD
n+

p- substrate
VGS=2VT:
VB = 0

VS = 0

VG = 2VT

Polysilicon

p+

n+

VB = 0

VS = 0

p- substrate

CMOS Analog Circuit Design

n+

0 VT

vDS

2VT 3VT

iD
VGS =2VT

n+

VG = 3VT
Polysilicon

p+

VGS =VT

VD = 2VT
iD

p- substrate
VGS=3VT:

iD

0
0 VT

VD = 2VT
iD

iD

vDS

2VT 3VT
VGS =3VT

n+

Further increase in
VG will cause the FET to become active

0
0 VT

2VT 3VT

vDS
Fig.3.1-05

P.E. Allen - 2004

Chapter 3 Section 1 (5/2/04)

Page 3.1-6

Output Characteristics of an Enhancement NMOS Transistor


2000
VGS = 3.0

iD(A)

1500
VGS = 2.5

1000
VGS = 2.0

500
VGS = 1.5
VGS = 1.0

vDS (Volts)

Fig. 3.1-6

SPICE Input File:


Output Characteristics for NMOS
M1 6 1 0 0 MOS1 w=5u l=1.0u
VGS1 1 0 1.0
M2 6 2 0 0 MOS1 w=5u l=1.0u
VGS2 2 0 1.5
M3 6 3 0 0 MOS1 w=5u l=1.0u
VGS3 3 0 2.0
M4 6 4 0 0 MOS1 w=5u l=1.0u
VGS4 4 0 2.5

M5 6 5 0 0 MOS1 w=5u l=1.0u


VGS5 5 0 3.0
VDS 6 0 5
.model mos1 nmos (vto=0.7 kp=110u
+gamma=0.4 +lambda=.04 phi=.7)
.dc vds 0 5 .2
.print dc ID(M1), ID(M2), ID(M3), ID(M4),
ID(M5)
.end

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 1 (5/2/04)

Page 3.1-7

Transconductance Characteristics of an Enhancement NMOS Transistor


6000

VDS = 5V

5000

VDS = 4V
VDS = 3V

iD(A)

4000
3000

VDS = 2V

2000
VDS = 1V

1000
0
0

2
3
vGS (Volts)

5
Fig. 3.1-7

SPICE Input File:


Transconductance Characteristics for NMOS
M1 1 6 0 0 MOS1 w=5u l=1.0u
VDS1 1 0 1.0
M2 2 6 0 0 MOS1 w=5u l=1.0u
VDS2 2 0 2.0
M3 3 6 0 0 MOS1 w=5u l=1.0u
VDS3 3 0 3.0
M4 4 6 0 0 MOS1 w=5u l=1.0u
VDS4 4 0 4.0
CMOS Analog Circuit Design

M5 5 6 0 0 MOS1 w=5u l=1.0u


VDS5 5 0 5.0
VGS 6 0 5
.model mos1 nmos (vto=0.7 kp=110u
+gamma=0.4 lambda=.04 phi=.7)
.dc vgs 0 5 .2
.print dc ID(M1), ID(M2), ID(M3), ID(M4),
ID(M5)
.probe
.end
P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-1

;;;

3.2 - LARGE SIGNAL FET MODEL FOR HAND CALCULATIONS

;;;

Large Signal Model Derivation


+
+
vGS
DerivationiD
- vDS
1.) Let the charge per unit area in the channel
inversion layer be
n+
n+
v(y)
Source
Drain
dy
2
QI(y) = -Cox[vGS-v(y)-VT] (coul./cm )
y
py y+dy
L
0
2.) Define sheet conductivity of the inversion
Fig.110-03
layer per square as
cm2 coulombs
amps
1
S = oQI(y) vs cm2 = volt = /sq.
3.) Ohm's Law for current in a sheet is
iD
-iD
-iDdy
dv
JS = W = -SEy = -S dy dv = SW dy = oQI(y)W iD dy = -WoQI(y)dv
4.) Integrating along the channel for 0 to L gives
L

vDS

iDdy = - WoQI(y)dv =

vDS

WoCox[vGS-v(y)-VT] dv

5.) Evaluating the limits gives


WoCox
v2(y)vDS
(vGS-VT)v(y) iD =
L
2 0

iD =

WoCox
vDS2
(v

-V
)v
GS
T
DS
L
2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-2

Saturation Voltage - VDS(sat)


Interpretation of the large
signal model:

iD
vDS = vGS-VT

Active Region

Saturation Region

Increasing
values of vGS
vDS
Fig. 110-04

The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of
the inverted parabolas.
vDS
diD oCoxW
[(vGS-VT) - vDS] = 0
L
dvDS =
Cutoff Saturation

CMOS Analog Circuit Design

vG
S=

0
0

vD

Useful definitions:
oCoxW KW
= L =
L

Active

SV
T

vDS(sat) = vGS - VT

VT

vGS

Fig. 3.2-4

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-3

The Simple Large Signal MOSFET Model


Regions of Operation of the MOS Transistor:
1.) Cutoff Region:
vGS - VT < 0
iD = 0
(Ignores subthreshold currents)
Output Characteristics of the MOSFET:
2.) Active Region
0 < vDS < vGS - VT
iD/ID0
vDS = vGS-VT
oCoxW
vGS-VT
iD = 2L 2(vGS - VT) - vDS vDS 1.0
Active
V
GS0-VT
Saturation Region
Region
3.) Saturation Region
0 < vGS - VT < vDS
oCoxW
iD =
2L vGS - VT 2

0.75
Channel modulation effects
0.5
0.25
Cutoff Region
0
0

0.5

1.0

1.5

2.0

= 1.0

vGS-VT
= 0.867
VGS0-VT
vGS-VT
= 0.707
VGS0-VT
vGS-VT
= 0.5
VGS0-VT
vGS-VT
=0
VGS0-VT
vDS
VGS0-VT
2.5
Fig. 110-05

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-4

Illustration of the Need to Account for the Influence of vD S on the Simple Sah Model
Compare the Simple Sah model to SPICE level 2:

25A
K' = 44.8A/V
k = 0, vDS(sat)
= 1.0V

20A

2
2

K' = 44.8A/V
k=0.5, vDS(sat)
= 1.0V

15A
iD
SPICE Level 2

10A

K' = 29.6A/V 2
k = 0, v (sat)
= 1.0V DS

5A
0A
0

0.2

0.4
0.6
vDS (volts)

0.8

VGS = 2.0V, W/L = 100m/100m, and no mobility effects.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-5

Modification of the Previous Model to Include the Effects of vDS on VT


From the previous derivation:
L

D
0

vD S

vD S

i dy = - WoQI(y)dv = WoCox[vGS - v(y) -VT]dv

Assume that the threshold voltage varies across the channel in the following way:
VT(y) = VT + kv(y)
where VT is the value of VT the at the source end of the channel and k is a constant.
Integrating the above gives,
WoCox
v2(y)vD S

(v -VT)v(y) - (1+k) 2
iD = L
GS
0
or
WoCox
v2DS
(vGS-VT)vDS - (1+k)
iD = L
2

To find vDS(sat), set the diD/dvDS equal to zero and solve for vDS = vDS(sat),
vGS - VT
vDS(sat) = 1 + k
Therefore, in the saturation region, the drain current is
WoCox
iD = 2(1+k)L (vGS - VT)2
For k = 0.5 and K = 44.8A/V2, excellent correlation is achieved with SPICE 2.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-6

Influence of VDS on the Output Characteristics


Channel modulation effect:
As the value of vDS increases, the
B
effective L decreases causing the
current to increase.

;;;
;;;;;;;
VG > VT

VD > VDS(sat)

Depletion
Region

Polysilicon

Illustration:

p+

;;;;;;;
n+

n+

eff
Note that Leff = L - Xd
Therefore the model in saturation
Xd
p- substrate
Fig110-06
becomes,
diD
dL
i dXd
KW
KW
2 eff = D
iD = 2L (vGS-VT)2 dv = (v
V
)
2Leff2 GS T dvDS Leff dvDS iD
eff
DS

Therefore, a good approximation to the influence of vDS on iD is


diD
KW
iD iD( = 0) + dvDS vDS = iD( = 0)(1 + vDS) = 2L (vGS-VT)2(1+vDS)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-7

Channel Length Modulation Parameter,


Assume the MOS is transistor is saturatedCoxW
iD = 2L (vGS - VT)2(1 + vDS)
Define iD(0) = iD when vDS = 0V.
CoxW
iD(0) = 2L (vGS- VT)2
Now,
iD = iD(0)[1 + vDS] = iD(0) + iD(0) vDS
Matching with y = mx + b gives the value of

iD
iD3(0)
iD2(0)
iD1(0)

VGS3
VGS2
VGS1
vDS

-1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-8

;;;
;;
;;;;
;;;
;;;;;;;;;
;;;
;;;;
;;
;;;
;;
;;;;
;;;
;;;
;;;;;;
;;;

Influence of the Bulk Voltage on the Large Signal MOSFET Model


VBS0 = 0V
Illustration of the influence of the bulk:
VS = 0
VG > VT
VSB0 = 0V:

VD > 0

iD

Polysilicon

p+

n+

n+

Channel current

p- substrate

Fig.110-07A

VSB1 > 0V

VSB1>0V:

VS = 0

VG > VT

VD > 0

iD

Polysilicon

p+

n+

n+

Channel current

p- substrate

Fig.110-07B

VSB2 > VSB1:

VSB2 >VSB1 V = 0
S

VG > VT

VD > 0

iD = 0

Polysilicon

p+

;;;;;;;;;
n+

n+

p- substrate

Fig.110-07C

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-9

Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristicsiD

Decreasing values
of bulk-source voltage

VBS = 0
ID
vDS vGS-VT

VT0

VT1

VT2

vGS
Fig. 110-08

VT2

In general, the simple model incorporates the bulk effect into VT by the previously
developed relationship:
VT(vBS) = VT0 + 2|f| + |vBS| - 2|f|

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-10

Summary of the Simple Large Signal MOSFET Model


N-channel reference convention:
G

iD

D
+
B

v
Non-saturation+
+ DS
vGS vBS
WoCox
vDS2
- (vGS - VT)vDS iD =
L
2 (1 + vDS)

S Fig. 110-10
SaturationWoCox
vDS(sat)2
WoCox
2
(vGS-VT)vDS(sat) (1+vDS) =
iD =
L
2
2L (vGS-VT) (1+vDS)

where:
o = zero field mobility (cm2/voltsec)
Cox = gate oxide capacitance per unit area (F/cm2)

= channel-length modulation parameter (volts-1)


VT = VT0 + 2|f| + |vBS| - 2|f|
VT0 = zero bias threshold voltage
= bulk threshold parameter (volts-0.5)
2|f| = strong inversion surface potential (volts)
For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert
current.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-11

Silicon Constants
Constant
Symbol
VG
k
ni

0
si
ox

Constant Description
Silicon bandgap (27C)
Boltzmanns constant
Intrinsic carrier
concentration (27C)
Permittivity of free space
Permittivity of silicon
Permittivity of SiO2

Value

Units

1.205
1.381x10-23
1.45x1010

V
J/K
cm-3

8.854x10-14
11.7 0
3.9 0

F/cm
F/cm
F/cm

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-12

MOSFET Parameters
Model Parameters for a Typical CMOS Bulk Process (0.8m CMOS n-well):
Parameter
Parameter
Symbol
Description
VT0 Threshold Voltage
(VBS = 0)
Transconductance ParaK'
meter (in saturation)
Bulk threshold

parameter
Channel length

modulation parameter
2|F| Surface potential at
strong inversion

CMOS Analog Circuit Design

Typical Parameter Value


N-Channel
P-Channel
0.7 0.15
-0.7 0.15

Units
V

110.0 10%

50.0 10%

A/V2

0.4

0.57

(V)1/2

0.04 (L=1 m)
0.01 (L=2 m)
0.7

0.05 (L=1 m)
0.01 (L=2 m)
0.8

(V)-1
V

P.E. Allen - 2004

Chapter 3 Section 2 (5/2/04)

Page 3.2-13

Large Signal Model of the MOS Transistor


Schematic:
D
All modeling so far
has been focused on
this dependent current
source.

where,
rG, rS, rB, and rD are ohmic and contact
resistances
and

vBD

iBD = Is exp Vt - 1

rG

CGD

rD
CBD

vBD
+ iBD
vBS
+ -

iD

rB

iBS
CBS

CGS

and

vBS

iBS = Is exp Vt - 1

CGB

rS
S

Fig. 3.2-10

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-1

3.3 - LARGE SIGNAL MODEL EXTENSIONS


TO SHORT-CHANNEL MOSFETS
Extensions
Velocity saturation
Weak inversion (subthreshold)
Substrate currents
Substrate Interference
Problems of mixed signal circuits on the same substrate
Modeling and potential solutions

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-2

An expression for the electron drift


velocity as a function of the electric
field is,
nE
vd 1 + E/Ec
where
vd = electron drift velocity (m/s)

Electron Drift Velocity (m/s)

VELOCITY SATURATION
What is Velocity Saturation?
The most important short-channel
effect in MOSFETs is the velocity
105
saturation of carriers in the channel.
A plot of electron drift velocity
5x104
versus electric field is shown below.
2x104
104
5x103

105

106
Electric Field (V/m)

107
Fig130-1

n = low-field mobility ( 0.07m2/Vs)


Ec = critical electrical field at which velocity saturation occurs
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-3

Short-Channel Model Derivation


As before,
iD
WQI(y)nE

E
JD = JS = W = QI(y)vd(y) iD = WQI(y)vd(y) = 1 + E/Ec iD 1+ Ec = WQI(y)nE

Replacing E by dv/dy gives,

1 dv
dv
iD 1 + Ec dy= WQI(y)n dy

Integrating along the channel gives,


L

vDS
1 dv
i 1 + Ec dydy = WQI(y)ndv

The result of this integration is,


nCox
W
K
W
2] =
[2(v
-V
)v
-v
iD =
GS
T
DS
DS

2[1+(vGS-VT)] L [2(vGS-VT)vDS-vDS2]
1 vDS L

21 + Ec L

where = 1/LEc with dimensions of V-1.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-4

Saturation Voltage
Differentiating iD with respect to vDS and setting equal to zero gives,

vDS2 + 2vDS 2(VGS-VT) = 0


Solving for vDS gives,

(VGS-VT)
1

+
VDS(sat) = 1 + 2(VGS-VT -1 (VGS-VT)1 2

or

(VGS-VT)

VDS(sat) VDS(sat) 1 +
2
Note that the transistor will enter the saturation region for vDS < vGS - VT in the
presence of velocity saturation.
Therefore the large signal model in the saturation region is,

(VGS-VT)
K
W

iD = 2[1 + (v -V )] L [ vGS - VT]2,


vDS (VGS-VT)1 +

2
GS T

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-5

The Influence of Velocity Saturation on the Transconductance Characteristics


The following plot was made for K = 110A/V2 and W/L = 1:
1000
=0
= 0.2

iD/W (A/m)

800

= 0.4
600
= 0.6
400
= 0.8
= 1.0

200
0
0.5

1.5

2
vGS (V)

2.5

3
Fig130-2

Note as the velocity saturation effect becomes stronger, that the drain current-gate
voltage relationship becomes linear.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-6

Circuit Model for Velocity Saturation


A simple circuit model to include the influence of velocity saturation
is the following:
We know that
KW
iD = 2L (vGS -VT)2 and
vGS = vGS + iD RSX
or
vGS = vGS - iDRXS
Substituting vGS into the current relationship gives,
KW
iD = 2L (vGS - iDRSX -VT)2
Solving for iD results in,
K
W
2
iD =
L (vGS - VT)
W
21 + K L RSX(vGS-VT)
Comparing with the previous result, we see that
1
L
W
= K L RSX
RSX = KW = EcKW

D
G

iD
+

+
vGS' RSX

vGS
Fig130-3

- S

Therefore for K = 110A/V2, W = 1m and Ec = 1.5x106V/m, we get RSX = 6.06k.


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-7

Output Characteristics of Short-Channel MOSFETs


IBM, 1998, tox = 3.5nm
800
Drain Current (A/m)

700
600

NFET VGS=1.8V
Leff =
0.08m

PFET
Leff =
0.11m

VGS=1.4V

500
400

VGS=-1.8V

300

VGS=-1.4V

200
100

VGS=1.0V
VGS=-1.0V
VGS=0.6V

VGS=-0.6V

0
-1.8

-1.2

-0.6

0.6
0.0
Drain Voltage (V)

1.2

1.8
Fig130-4

Su, L., et.al., A High Performance Sub-0.25m CMOS Technology with Multiple Thresholds and Copper Interconnects, 1998 Symposium on
VLSI Technology Digest of Technical Papers, pp. 18-19.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-8

Velocity Saturation Effects


Velocity Saturation Insignificant
W
gm = K2L (VGS-VT)
1 gm
fT = 2 Cgs L-2

Velocity Saturation Significant


1+ 2 (VGS-VT)-1
gm = WCoxuoEc 1+ 2 (V -V )
GS T
1 gm
fT = 2 Cgs L-1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-9

Important Short Channel Effects


1.) An approximate plot of the n as a function
of channel length is shown below where
iD (vGS VT)n

n
2
1
0

L
Lmin
Fig.130-5

Channel Length Modulation (V-1)

2.) Note that the value of varies with channel length, L. The data below is from a
0.25m CMOS technology.

CMOS Analog Circuit Design

0.6
0.5
0.4
PMOS

0.3
0.2
NMOS

0.1
0
0

0.5

1
1.5
Channel Length (microns)

2.5
Fig.130-6
P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-10

SUBTHRESHOLD MOSFET MODEL


What is Weak Inversion Operation?
Weak inversion operation occurs when the applied gate voltage is below VT and
pertains to when the surface of the substrate beneath the gate is weakly inverted.

;;;
;;;
yyy
VGS

n+

n-channel

n+

Diffusion Current
p-substrate/well

Fig. 140-01

Regions of operation according to the surface potential, S (or S)


S < F :
Substrate not inverted
F < S < 2F :
Channel is weakly inverted (diffusion current)
Strong inversion (drift current)
2F < S :

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-11

Drift versus Diffusion Current


1.) For strong inversion, the gate voltage controls the charge in the inverted region but
not in the depletion region. The concentration of charge across the channel is
approximately constant and the current is drift caused by electric field.
2.) For weak inversion, the charge in channel is much less that that in the depletion region
and drift current decreases. However, there is a concentration gradient in the channel,
that causes diffusion current.
The n-channel MOSFET acts like a NPN BJT: the emitter is the source, the base is
the substrate and the collector is the drain.
Illustration:

log iD
Diffusion Current
Drift Current

10-6

10-12

CMOS Analog Circuit Design

VT

V
Fig. 140-02 GS

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-12

Large-Signal Model for Weak Inversion


The electrons in the substrate at the source side can be expressed as,
s
np(0) = npoexpVt

The electrons in the substrate at the drain side can be expressed as,
s-vDS
np(L) = npoexp Vt

Therefore, the drain current due to diffusion is,


np(L)- np(0)
s
vDS
W

iD = qADn
=
qXD
n
exp
1
exp

- V
n
po
V
L
L
t

where X is the thickness of the region in which iD flows.


In weak inversion, the changes in the surface potential, s are controlled by changes in
the gate-source voltage, vGS, through a voltage divider consisting of Cox and Cjs, the
depletion region capacitance.
ds
Cox
vGS
vGS-VT
1
dvGS = Cox+ Cjs = n s = n + k1 = n
+ k2
where
VT
k2 = k1 + n
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-13

Large-Signal Model for Weak Inversion Continued


Substituting the above relationships back into the expression for iD gives,
k2
vGS-V T
vDS
W
iD = L qXDnnpo expVtexp nVt 1 - exp- Vt

Define It as
k2
It = qXDnnpo expVt

to get,
vGS-V T
vDS
W
iD = L It exp nVt 1 - exp- Vt

where n 1.5 3
iD
If vDS > 0, then
1A

v
vGS-VT
W
DS
iD = It L exp nVt 1 + V
A

VGS=VT

VGS<VT

CMOS Analog Circuit Design

1V

vDS
Fig. 140-03
P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-14

Small-Signal Model for Weak Inversion


Small-signal model:
diD |
gm = dvGS Q

vGS-V T
vDS ID qID ID Cox
W It

= It L nV exp nV 1 + V = nV = nkT = V C +C
t
t
t
t ox js
A

diD | ID
gds = dvDS Q VA
The boundary between nonsaturated and saturated is found as,
Vov = VDS(sat) = VON = VGS VT = 2nVt

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-15

Simulation of an n-channel MOSFET in both Weak and Strong Inversion


Uses the BSIM model.
100A
10A
iD

vGS

ID(M1)

1A
100nA
10nA
1nA
100pA
0V

0.4V

0.8V

VGS

1.2V

1.6V

2V

Fig. 140-05

Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 Users Guide, Kluwer Academic Publishers, Boston, 1999.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-16

Example 3-1 The NMOS in Weak Inversion


Calculate Vov and fT for an NMOS transistor with ID = 1A, It = 0.1A, and vDS>>VT.
Assume that W = 10m, L = 1m, n = 1.5, KN = 200A/V2, tox = 100, and the
temperature is 27C.
Solution
First we find the
Vov = VDS(sat) = VON = VGS VT = 2nVt = 2(1.5)(25.9mV) 78mV
Next, we need to find gm and Cgs.
ID
1A
gm = nVt = 1.525.9mV = 25.75S
Cjs
Previously, we found that n = 1 + Cox . Cjs = (n-1)Cox = 0.5 Cox
It can be shown that
CoxCjs
10m2 3.98.85410-14(F/cm)(100cm/106m)

Cgs = WL Cox + Cjs = 0.33WLCox = 3


100 (106m/1010)

1
1 25.75S

fT = |2 T = 2 11.5fF 360MHz
Cgs = 11.5fF
(Equivalent transistor operating in strong inversion has an fT = 3.4GHz)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-17

SUBSTRATE CURRENT FLOW IN MOSFETS


Impact Ionization
Impact Ionization:
Occurs because high electric fields cause an impact which generates a hole-electron
pair. The electrons flow out the drain and the holes flow into the substrate causing a
substrate current flow.
Illustration:

;;;
;;;;;;;;
VG > V T

VD > VDS(sat)

Polysilicon

p+

Depletion
Region

;;;;;;;;
;;;;;;;;
A

n+

Fixed
Atom

p- substrate

Free n+
electron

Free
hole

Fig130-7

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-18

Model of Substrate Current Flow


Substrate current:
iDB = K1(vDS - vDS(sat))iDe-[K2/(vDS-vDS(sat))]
where
K1 and K2 are process-dependent parameters (typical values: K1 = 5V-1 and K2 = 30V)
Schematic model:
D

iDB
G
B
S

Fig130-8

Small-signal model:
iDB
IDB
gdb = vDB = K2 VDS - VDS(sat)
This conductance will have a negative influence on high-output resistance current
sinks/sources.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-19

SUBSTRATE INTERFERENCE IN CMOS CIRCUITS


How Do Carriers Get Injected into the Substrate?
1.) Hot carriers (substrate current)
2.) Electrostatic coupling (across depletion regions and other dielectrics)
3.) Electromagnetic coupling (parallel conductors)
Why is this a Problem?
With decreasing channel lengths, more circuitry is being integrated on the same
substrate. The result is that noisy circuits (circuits with rapid transitions) are beginning
to adversely influence sensitive circuits (such as analog circuits).
Present Solution
Keep circuit separate by using multiple substrates and put the multiple substrates in the
same package.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-20

Hot Carrier Injection in CMOS Technology without an Epitaxial Region


Noisy Circuits
VDD

Quiet Circuits
VDD(Analog)

;;
vin

vout

VGS

p+

n+

vin vout

VDD(Digital)

p+

n+

p+

Substrate Noise

VDD(Analog)

vin

;;;
;;;;;
;;;
;;;
;;;;;
;;;

Digital Ground

RL
vout

vin

n+

;;;
;;;

RL
vout Analog Ground

VGS

n+ channel
stop (1 -cm)
p+ channel stop (1-cm)

n- well "AC ground"

Hot
Carrier
Put substrate connections
as close to the noise source
as possible

n+

n+

Back-gating due to a
momentary change in
reverse bias

iD

ID

"AC ground"

p+

iD
iD

vGS

VGS

p- substrate (10 -cm)

Heavily
Doped p

Lightly
Doped p

Intrinsic
Doping

Lightly
Doped n

Fig. SI-01

Heavily Metal
Doped n

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-21

Hot Carrier Injection in CMOS Technology with an Epitaxial Region


Noisy Circuits
VDD

Quiet Circuits
VDD(Analog)

;;
vin

vout

VGS

p+

n+

vin vout

n+

p+

VGS

n+

n- well "AC ground"

Put substrate Hot


connections Carrier
as close to the
noise source
as possible

Substrate Noise

VDD(Analog)

;;;
;;;

VDD(Digital)

p+

vin

;;;
;;;;;
;;;
;;;
;;;;;
;;;

Digital Ground

RL
vout

vin

RL
vout Analog Ground

n+

p-epitaxial
layer (15 -cm)

n+

p+

Reduced back
gating due to
smaller resistance

"AC ground"

p+ substrate (0.05 -cm)

Heavily
Doped p

CMOS Analog Circuit Design

Lightly
Doped p

Intrinsic
Doping

Lightly
Doped n

Heavily Metal
Doped n

Fig. SI-02

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-22

Computer Model for Substrate Interference Using SPICE Primitives


Noise Injection Model:
VDD

;;
vin

VDD

vout

Digital Ground

L1
Cs1
n- well

VDD(Digital)

;;;
;;;
;;;;;
;;;;;;;;
;;;
;;;;;
vin vout

p+

n+

p+

n+

Hot
Carrier

Hot
Carrier Coupling

p+

Lightly
Doped p

Intrinsic
Doping

Cs3

vout Rs1

Cs2

Substrate

Rs2

n+
n- well

Cs4

Coupling

Rs3
Cs5
L3

L2

Coupling

p- substrate

Heavily
Doped p

vin

Lightly
Doped n

Cs1 = Capacitance between n-well and substrate


Cs2,Cs3 and Cs4 = Capacitances between interconnect lines
(including bond pads) and substrate
Cs5 = All capacitance between the substrate and ac ground
Rs1,Rs2 and Rs3 = Bulk resistances in n-well and substrate
L1,L2 and L3 = Inductance of the bond wires and package leads

Heavily Metal
Doped n

Fig. SI-06

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-23

Computer Model for Substrate Interference Using SPICE Primitives


Noise Detection Model:
VDD(Analog)

VGS

;
RL
vout

vin

Substrate Noise

VDD

VDD(Analog)

vin

;;;
;;;

VGS

n+

n+

Analog Ground

Lightly
Doped p

L4

vout
CL

L6

p+

VGS
Substrate

Cs6 Rs4

Cs5

Cs7

L5

Cs5,Cs6 and Cs7 = Capacitances between interconnect lines


(including bond pads) and substrate
Rs4 = Bulk resistance in the substrate
L4,L5 and L6 = Inductance of the bond wires and package leads

p- substrate

Heavily
Doped p

RL

RL
vout

Intrinsic
Doping

CMOS Analog Circuit Design

Lightly
Doped n

Heavily Metal
Doped n

Fig. SI-07
P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-24

Other Sources of Substrate Injection


(We do it to ourselves and cant blame the digital circuits.)
Inductor
Substrate BJT
Collector Base
n+

p+

Emitter

;;;;;;;;

Collector
n+

n+

p- well

Fig. SI-04
Heavily
Doped p

Lightly
Doped p

Intrinsic
Doping

Lightly
Doped n

Heavily Metal
Doped n

Also, there is coupling from power supplies and clock lines to other adjacent signal lines.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 3 (5/2/04)

Page 3.3-25

What is a Good Ground?


On-chip, it is a region with very low bulk resistance.
It is best accomplished by connecting metal to the region at as many points as
possible.
Off-chip, it is all determined by the connections or
20
bond wires.
Settling Time to within 0.5mV (ns)
The inductance of the bond wires is large enough 16
to create significant ground potential changes for 12
Peak-to-Peak Noise (mV)
fast current transients.
8
di
4
v = L dt
0
Use multiple bonding wires to reduce the ground
0
1
2
3
4
5
6
7
8
Number of Substrate Contact Package Pins
noise caused by inductance.
Fig. SI-08
Fast changing signals have part of
their path (circuit through ground
and power supplies. Therefore
bypass the off-chip power supplies
to ground as close to the chip as
possible.
CMOS Analog Circuit Design

C2
t=0
-

Vin

C1

Vout

VDD
VSS
P.E. Allen - 2004

Fig. SI-05

Chapter 3 Section 3 (5/2/04)

Page 3.3-26

Summary of Substrate Interference


Methods to reduce substrate noise
1.) Physical separation
2.) Guard rings placed close to the sensitive circuits with dedicated package pins.
3.) Reduce the inductance in power supply and ground leads (best method)
4.) Connect regions of constant potential (wells and substrate) to metal with as
many contacts as possible.
Noise Insensitive Circuit Design Techniques
1.) Design for a high power supply rejection ratio (PSRR)
2.) Use multiple devices spatially distinct and average the signal and noise.
3.) Use quiet digital logic (power supply current remains constant)
4.) Use differential signal processing techniques.
Some references
1.) D.K. Su, M.J. Loinaz, S. Masui and B.A. Wooley, Experimental Results and Modeling Techniques for
Substrate Noise in Mixed-Signal ICs, J. of Solid-State Circuits, vol. 28, No. 4, April 1993, pp. 420-430.
2.) K.M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura and M. Hotta, Voltage-Comparator-Based
Measurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal ICs, J. of Solid-State
Circuits, vol. 31, No. 5, May 1996, pp. 726-731.
3.) X. Aragones, J. Gonzalez and A. Rubio, Analysis and Solutions for Switching Noise Coupling in MixedSignal ICs, Kluwer Acadmic Publishers, Boston, MA, 1999.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.4-1

3.4 - CAPACITANCES OF THE MOSFET


Types of Capacitance
Physical Picture:
SiO2

Gate
Source
C1

Drain
C2

C3

FOX

FOX
C4
CBS

CBD

Bulk

Fig120-06

MOSFET capacitors consist of:


Depletion capacitances
Charge storage or parallel plate capacitances
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.4-2

MOSFET Depletion Capacitors


Model:
1.) vBS FCPB
CJAS
CJSWPS
CBS =
,
MJ +

vBS
vBSMJSW
1
1
PB
PB

and
2.) vBS> FCPB
CJAS

CBS =

1+MJ

1- FC
CJSWPS

1 - FC

Polysilicon gate
H

1+MJSW

D
Source

Drain
F
E
A

SiO2

VBS
1 - (1+MJ)FC + MJ PB

B
Bulk
Fig. 120-07

Drain bottom = ABCD


Drain sidewall = ABFE + BCGF + DCGH + ADHE

VBS
1 - (1+MJSW)FC + MJSW PB

CBS

where
AS = area of the source
vBS FCPB
PS = perimeter of the source
CJSW = zero bias, bulk source sidewall capacitance
MJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.

vBS FCPB
PB
FCPB

vBS
Fig. 120-08

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.4-3

Charge Storage (Parallel Plate) MOSFET Capacitances - C1, C2, C3 and C4


Mask L

LD

Actual
L (Leff)

Oxide encroachment

Mask
W

Actual
W (Weff)

Gate
Drain-gate overlap
capacitance CGD (C3)

Source-gate overlap
capacitance CGS (C1)
Gate
FOX

Source
Gate-Channel
Capacitance (C2)

Bulk

FOX
Drain
Channel-Bulk
Capacitance (C4)

Overlap capacitances:
C1 = C3 = LDWeffCox = CGSO or CGDO
(LD 0.015 m for LDD structures)

Channel capacitances:
C2 = gate-to-channel = CoxWeff(L-2LD) =
CoxWeffLeff
C4 = voltage dependent channelbulk/substrate capacitance

Fig. 120-09

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.4-4

Charge Storage (Parallel Plate) MOSFET Capacitances - C5


View looking down the channel from source to drain
Overlap

Overlap

FOX C5

Gate
Source/Drain

C5 FOX

Bulk
Fig120-10

C5 = CGBO
Capacitance values based on an oxide thickness of 140 or Cox=24.7 10-4 F/m2:
Type
CGSO
CGDO
CGBO
CJ
CJSW
MJ
MJSW

P-Channel
220 10-12
220 10-12
700 10-12
560 10-6
350 10-12
0.5
0.35

N-Channel
220 10-12
220 10-12
700 10-12
770 10-6
380 10-12
0.5
0.38

Units
F/m
F/m
F/m
F/m2
F/m

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.4-5

Expressions for CGD, CGS and CGB


Cutoff Region:
CGB = C2+2C5 = Cox(Weff)(Leff)
+ 2CGBO(Leff)
CGS = C1 Cox(LD)Weff = CGSO(Weff)
CGD = C3 Cox(LD)Weff = CGDO(Weff)
Saturation Region:
CGB = 2C5 = CGBO(Leff)
CGS = C1+(2/3)C2 = Cox(LD+0.67Leff)(Weff)
= CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGD = C3 Cox(LD)Weff) = CGDO(Weff)
Nonsaturated Region:
CGB = 2 C 5 = 2CGBO(Leff)
CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGSO + 0.5CoxLeff)Weff
CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGDO + 0.5CoxLeff)Weff
CMOS Analog Circuit Design

Cutoff
VB = 0

;;;
;;;
;;;
;;;

VS = 0
CGS

VG < VT

Polysilicon

p+
p- substrate
Saturated
VB = 0

p+
p- substrate
Active
VB = 0

n+

VS = 0
CGS

n+

CGB

VG >VT

Polysilicon

n+

p- substrate

VD >VG -VT
CGD
n+

Inverted Region

VS = 0
CGS

VG >VT

Polysilicon

p+

VD > 0
CGD

n+

VD <VG -VT
CGD
n+

Inverted Region

Fig120-1

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.4-6

Illustration of CGD, CGS and CGB


Comments on the variation of CBG in the cutoff region:
1
CBG = 1
Capacitance
1 + 2C5
+
C4 Large
C2 C4
C2 + 2C5
1.) For vGS 0, CGB C2 + 2C5
(C4 is large because of the thin
inversion layer in weak inversion
where VGS is slightly less than VT))
2.) For 0 < vGS VT, CGB 2C5
(C4 is small because of the thicker
inversion layer in strong inversion)

CGS

C1+ 0.67C2
C1+ 0.5C2
C1, C3
2C5
0

CGS, CGD
vDS = constant
vBS = 0
C4 Small

CGS, CGD

CGD
CGB

Off

Saturation
VT

vGS
NonSaturation
vDS +VT
Fig120-12

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.5-1

3.5 SMALL SIGNAL MODELS FOR THE MOSFET


Small-Signal Model for the Saturation Region
The small-signal model is a linearization of the large signal model about a quiescent or
operating point.
Consider the large-signal MOSFET in the saturation region (vDS vGS VT) :
WoCox
2
iD =
2L (vGS - VT) (1 + vDS)
The small-signal model is the linear dependence of id on vgs, vbs, and vds. Written as,
id gmvgs + gmbsvbs + gds vds
where
diD |
gm dv Q = (VGS-VT) = 2ID
GS
ID
diD |
gds dv Q = 1 + V
ID
DS
DS
and
dD diD dvGS diD dVT
gm
gmbs dvBS Q = dvGS dvBS = - dVTdvBS =
= gm

Q 2 2|F| - VBS
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.5-2

Small-Signal Model Continued


Complete schematic
D
model:
G

where

id

+
vgs

+
vbs

gmvgs

rds

gmbsvbs

+D
vds
-

Fig. 120-01

diD |
gm dvGS Q =
diD |
iD
gds dvDS Q = 1 + vDS iD

(VGS-VT) = 2ID
and

D iD vGS iD vT
gm
gmbs = v Q = v v = - v v =
= gm
BS
GS BS Q
T BSQ 2 2|F| - VBS

Simplified schematic model:


id
D

An extremely important
assumption:
gm 10gmbs 100gds

+
vgs

gmvgs

+D
vds

rds

Fig. 120-02

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.5-3

Illustration of the Small-Signal Model Application


Assume that the gate is connected to the drain.
DC resistor:

i
AC Resistance

v
V
DC resistance = i = I = RDC
Q
Useful for biasing - creating current from
voltage and vice versa
Small-Signal Load (AC resistance):
D

G
S

G
B

VT

VDS

Fig. 120-03

id

DC Resistance

ID

+
vgs

+
vbs
-

gmvgs

gmbsvbs

rds

+D
vds
-

Fig. 120-01

Assume that vbs = 0,


vds vgs
1
1
AC resistance = id = id = gm + gds gm = Rac
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.5-4

Small-Signal Model for the Nonsaturated Region


KWVDS
iD |
KW

V DS
gm = vGS Q =
(1+

V
)

DS
L
L

iD |
KW VDS
gmbs = vBS Q = 2L 2 - V
F
BS
iD |
ID
KW
KW
gds = vDS Q = L ( VGS - VT - VDS)(1+VDS) + 1+VDS L (VGS - VT - VDS)
Note:
While the small-signal model analysis is independent of the region of operation, the
evaluation of the small-signal performance is not.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.5-5

Small Signal Model for the Subthreshold Region


If vDS > 0, then
W
iD = Kx L evGS/nVt (1 + vDS)
Small-signal model:
diD | qID
gm = dvGS Q = nkT
diD |
ID
gds = dvDS Q VA

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 4 (5/2/04)

Page 3.5-6

Small-Signal Frequency Dependent Model


The depletion capacitors
Cgd
are found by evaluating the
G
large signal capacitors at
+
Cgs
the DC operating point.
vgs
The charge storage
capacitors are constant for
a specific region of
operation.

Cgb

id

gmvgs

rds

gmbsvbs

vbs

Gain-bandwidth of the MOSFET:


Assume VSB = 0 and the MOSFET is in saturation,
gm
1
1 gm
fT = 2 Cgs + Cgd 2 Cgs
Recalling that
W
2
gm = oCox L (VGS-VT)
Cgs 3 CoxWL and

+
vds
S

Cbd

Cbs

+
B

Fig120-13

3 o
fT = 4 L2 (VGS-VT)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-1

3.6 - TEMPERATURE AND NOISE MODELS FOR THE MOSFET


Large Signal Temperature Model
Transconductance parameter:
K(T) = K(T0) (T/T0)-1.5
(Exponent becomes +1.5 below 77K)
Threshold Voltage:
VT(T) = VT(T0) + (T-T0) +
Typically NMOS = -2mV/C to 3mV/C from 200K to 400K (PMOS has a + sign)
Example
Find the value of ID for a NMOS transistor at 27C and 100C if VGS = 2V and W/L =
5m/1m if K(T0) = 110A/V2 and VT(T0) = 0.7V and T0 = 27C and NMOS = -2mV/C.
Solution
At room temperature, the value of drain current is,
110A/V25m
ID(27C) =
(2-0.7)2 = 465A
21m
-1.5
At T = 100C (373K), K(100C)=K(27C) (373/300) =110A/V20.72=79.3A/V2
and
VT(100C) = 0.7 (.002)(73C) = 0.554V
79.3A/V25m
ID(100C) =
(2-0.554)2 = 415A
(Repeat with VGS = 1.5V)
21m
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-2

Experimental Verification of the MOSFET Temperature Dependence


NMOS Threshold:
1.6
1.4
1.2
1
VT(V) 0.8
0.6
Theory
matched
at 25C

0.4
0.2
0

50

100

Symbol
O

Min. L
6m
5m
4m
2m

150
200
Temperature (C)

NA (cm-3)
2x1016
1x1016
2x1016
3.3x1016

250

300
Fig. 3.6-1

(mV/C)
-3.5
-2.5
-2.3
-1.8

)
tox (A
1000
650
500
275

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-3

Experimental Verification of the MOSFET Temperature Dependence


PMOS Threshold:
1.6
1.4
1.2
1
VT(V) 0.8
0.6
Theory
matched
at 25C

0.4
0.2
0

Symbol
O

CMOS Analog Circuit Design

50

Min. L
6m
5m
4m
2m

100
150
200
Temperature (C)

NA (cm-3)
2x1015
2x1015
2x1016
1.1x1016

)
Tox (A
1000
650
500
275

250

300
Fig. 3.6-2

(mV/C)
+3.5
+2.5
+2.3
+2.0
P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-4

Experimental Verification of the MOSFET Temperature Dependence


NMOS K:
1000
Data
Symbol Min. L
6 m
5 m
4 m
2 m

800

600
(T)
(cm2/Vs)
400

Theory
matched
at 25C

200

50

100
150
200
Temperature (C)

250

300
Fig. 3.6-3

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-5

Experimental Verification of the MOSFET Temperature Dependence


PMOS K:
1000

800

600
(T)
(cm2/Vs)
400 Theory
matched
at 25C
200

CMOS Analog Circuit Design

50

Data
Symbol Min. L
6 m
5 m
4 m
2 m

100
150
200
Temperature (C)

250

300
Fig. 3.6-4

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-6

Zero Temperature Coefficient (ZTC) Point for MOSFETs


For a given value of gate-source voltage, the drain current of the MOSFET will be
independent of temperature. Consider the following circuit:
Assume that the transistor is saturated and that:
ID
T
= oTo-1.5
and VT(T) = VT(To) + (T-To)
VGS

= -0.0023V/C and To = 27C


Fig. 4.5-12
oCoxW T -1.5
ID(T) = 2L To [VGS VT0 - (T-To)]2

T
dID -1.5oCox T -2.5

-1.5
2
=
[V
-V

(T-T
)]
+

C
[VGS-VT0-(T-To)] = 0
T
T
GS
T0
o
o
ox
dT
2To
o
o
where

-4T
VGS VT0 - (T-To) = 3

VGS(ZTC) = VT0 - To - 3

Let K = 10A/V2, W/L = 5 and VT0 = 0.71V.


At T=27C (300K), VGS(ZTC)=0.71-(-0.0023)(300K)-(0.333)(-0.0023)(300K) = 1.63V
At T = 27C (300K), ID = (10A/V2)(5/2)(1.63-0.71)2 = 21.2A
At T=200C (473K), VGS(ZTC)=0.71-(-0.0023)(300K)-(0.333)(-0.0023)(473K)=1.76V
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-7

Experimental Verification of the ZTC Point


The data below is for a 5m n-channel MOSFET with W/L=50m/10m, NA=1016 cm-3,
tox = 650, uoCox = 10A/V2, and VT0 = 0.71V.
25C
100C
150C
200C
250C

100
VDS = 6V
80

ID (A)

275C
60

300C

40
150C
275C 250C 200C

Zero TC Point

20

25C
100C

0
0

0.6

1.2

1.8
VGS (V)

CMOS Analog Circuit Design

2.4

3
Fig. 3.6-065

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-8

ZTC Point for PMOS


The data is for a 5m p-channel MOSFET with W/L=50m/10m, ND=2x10-15cm-3, and
tox = 650.
25C
100C

300C
40

ID (A)

VDS = -6V
30

150C

20
275C
VSG(ZTC) -1.95V
10
150C
100C
25C

250C
0
0

-0.6

-1.2

-1.8

-2.4

-3.0

VGS (V)

Fig. 3.6-066

Zero temperature coefficient will occur for every MOSFET up to about 200C.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-9

Bulk-Drain (Bulk-Source) Leakage Currents (VG S>VT )


Cross-section of a NMOS in a p-well:

;;;
;;;;;;;
VG > V T

VD > VDS(sat)

Depletion
Region

Polysilicon

p+

;;;;;;;
n+

n+

p-well

n- substrate
Fig.3.6-5

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-10

Bulk-Drain (Bulk-Source) Leakage Currents (VG S<VT )


Cross-section of a NMOS in a p-well:

;;;
;;; ;;
VG <VT

VD > VDS(sat)

Polysilicon

p+

;;; ;;
n+

Depletion
Region

n+

p-well

n- substrate
Fig.3.6-6

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-11

Temperature Modeling of the PN Junction


PN Junctions (Reverse-biased only):
2
Dppno
Dnnpo qAD ni
VGo

iD Is = qA Lp + Ln L N = KT 3exp V t
Differentiating with respect to temperature gives,
VGo
VGo
qKT 3VGo
3Is Is VGo
dIs 3KT 3

=
=
exp
exp
2
dT
T
KT
T + T Vt
Vt
Vt
dIs
3
1 VGo
TCF = I dT = T + T V t
s
Example
Assume that the temperature is 300 (room temperature) and calculate the reverse
diode current change and the TCF for a 5 increase.
Solution
The TCF can be calculated from the above expression as
TCF = 0.01 + 0.155 = 0.165
Since the TCF is change per degree, the reverse current will increase by a factor of 1.165
for every degree (or C) change in temperature. Multiplying by 1.165 five times gives
an increase of approximately 2. Thus, the reverse saturation current approximately
doubles for every 5C temperature increase. Experimentally, the reverse current doubles
for every 8 C increase in temperature because the reverse current is part leakage current.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-12

Experimental Verification of the PN Junction Temperature Dependence


10-5
200C

Leakage Current (A)

10-6
10-7
10-8
10-9

250C

50m
Lmin

10-10
10-11
10-12
1.8

IR

Data
Symbol Min. L
6 m
5 m
4 m
2 m
100C

1V

Theory
matched
at 150C GenerationDiffusion
Recombination
Leakage
Leakage
Dominant
Dominant
2
2.2
2.4
2.6
2.8
Fig.
3.6-7
1000/T (K-1)

Theory:
V (T)
G

Is(T) T 3 exp kT

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-13

Temperature Modeling of the PN Junction Continued


PN Junctions (Forward biased vD constant):
vD
iD Is exp V t
Differentiating this expression with respect to temperature and assuming that the diode
voltage is a constant (vD = VD) gives
diD iD dIs 1 VD
dT = Is dT - T Vt iD
The fractional temperature coefficient for iD is
1 diD 1 dIs V D 3 VGo - VD
iD dT = Is dT - TVt = T + TVt
If VD is assumed to be 0.6 volts, then the fractional temperature coefficient is equal to 0.01
+ (0.155 - 0.077) = 0.0879. The forward diode current will double for a 10C.
PN Junctions (Forward biased iD constant):
VD = Vt ln(ID/Is)
Differentiating with respect to temperature gives
1 dIs
V Go - vD 3Vt
vD 3Vt VGo
dvD vD

=
V
=
=

t
dT
T
T T
T
T - T

Is dT
Assuming that vD = VD = 0.6 V the temperature dependence of the forward diode voltage
at room temperature is approximately -2.3 mV/C.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-14

MOSFET NOISE
MOS Device Noise at Low Frequencies
D

eN2
B

G
S

in2

G
Noise
Free
MOSFET

B
S

*
Noise
Free
MOSFET S

where
8kTgm(1+) KF ID
+ fSCoxL2 f (amperes2)
3

f = bandwidth at a frequency, f
gmbs
= gm
k = Boltzmanns constant
KF = Flicker noise coefficient
S = Slope factor of the 1/f noise

in2 =

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-15

Reflecting the MOSFET Noise to the Gate


Dividing in2 by gm2 gives
8kT(1+)

in2
KF
+ 2fC WL K f (volts2)
en2 = gm2 = 3gm
ox

KF
It will be convenient to use B = 2CoxK for model simplification.
in2

1/f noise

CMOS Analog Circuit Design

Thermal noise

log10(f)

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-16

MOS Experimental Noise Data


W/L

ID(A)

25/25
25/25
25/25
1.2/1.2
1.2/1.2
1.2/1.2
0.8/0.8
0.8/0.8
0.8/0.8
25/2
25/2
25/2
25/1
25/1
25/1
25/0.6
25/0.6
25/0.6

90
50
20
90
50
20
90
50
20
90
50
20
90
50
20
90
50
20

Thermal Noise
Noise Voltage at
100Hz (nV/ Hz ) Voltage (nV/ Hz )
360
40
360
35
360
25
10,000
350
10,000
200
10,000
180
70,000
1800
60,000
1500
50,000
1200
900
30
850
28
1000
38
850
33
1000
30
950
50
750
42
700
35

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-17

MOSFET Noise Model at High Frequencies


At high frequencies, the source resistance can no longer be assumed to be small.
Therefore, a noise current generator at the input results.
MOSFET Noise Models:
Cgd

G
vin

vgs
gmvgs

Cgs

rds

io2

in2

S
S
Circuit 1: Frequency Dependent Noise Model
ei2
Cgd
G
D

vin

ii2

Cgs

vgs
gmvgs

rds

io2

S
S
Circuit 2: Input-referenced Noise Model

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 6 (5/2/04)

Page 3.6-18

MOSFET Noise Model at High Frequencies Continued


To find ei2 and ii2, we will perform the following calculations:
ei2:
Short-circuit the input and find io2 of both models and equate to get ei2 .
Ckt. 1: io2 = in2
Ckt. 2: io2 = gm2 ei2+ (Cgd)2ei2

in2
e = g 2 + (C )2
m
gd

2
i

ii2:
Open-circuit the input and find io2 of both models and equate to get ii2 .
Ckt. 1: io2 = in2

(1/Cgs)
gm2ii2
2
Ckt. 2: io2 = (1/Cds) + (1/Cgs) ii2 + 2(Cgs+Cds)2

2Cgs2
gm2
2
2
2Cgs2 in if Cgd < Cgs ii = gm2 in2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-1

SEC. 3.7 BJT MODELS


Bipolar Transistor Symbol and Sign Convention
The bipolar junction transistor (BJT) is a
three-terminal device whose symbol and sign
convention (according to the text) is given as
shown:
iB
B
Description of the three terminals:
Emitter - The emitter is the source of majority
carriers that result in the gain mechanism of
the BJT. These carriers which are emitted
into the base are electrons for the npn
transistor and holes for the pnp transistor.

iC
vBC+
+
vCE
+
vBE iE

iC
vBC+
+
vCE
+
vBE iE

E
npn

iB
B

E
pnp
Fig.07-02

Base - The base is a region which physically separates the emitter and collector and
has an opposite doping (holes for the npn and electrons for the pnp BJTs). The word
base comes from the way that the first transistors were constructed. The base was
the physical support for the whole transistor.
Collector - The collector serves to collect those carries injected from the emitter into
the base and which reach the collector without recombination.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-2

Physical Aspects of an npn BJT


A cross-section of an npn BJT is shown below:

;;;;;
;;;
;;;;;
;;;
E

Depletion
Region

n+

C Depletion
Region

;
;
;;
B

n+
A

Fig.070-03

n
A'

Depletion Depletion
Region Region

Comments:
The emitter-base depeletion region is generally smaller in width because the doping
level is higher and base-emitter junction is generally forward-biased.
The next slide will examine the carrier concentrations see looking into the above A-A
cross-section.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-3

Carrier Concentrations of the npn BJT


The carrier concentrations (not to scale) for the npn BJT are shown below.

;;
;;
;

Carrier
Concentration

nnE

pp(x)

Depletion
Region

pnE
A

pnE(0)
Emitter

;;;
;;;
;;;
;;;

Depletion
Region

np(0)

x=0

NA
np(x)

Base

np(WB)

x =WB

nnC

ND
pnC
Collector

x
A'

Fig.070-04

Comments:
The above carrier concentrations assume that the base-emitter junction is forward
biased and the base-collector junction is reverse biased.
The above carrier concentration will be used to derive the large signal model on the
next slide.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-4

Derivation of the BJT Large Signal Model in the Foward Active Region
1.) Carrier concentrations in the base on the emitter side. The concentration of electrons
in the base on the emitter side (x = 0) is
np(0) = npo exp(vBE/Vt)
The concentration of electrons in the base on the collector side (x = WB) is
np(WB) = npo exp(vBC/Vt) 0 because vBC is negative and large.
2.) If the recombination of electrons in the base is small, then the minority-carrier
concentrations, np(x), are straight lines and shown on the previous page. From
charge-neutrality requirements for the base,
NA + np(x) = pp(x) np(x) - pp(x) = NA
3.) The collector current is produced by minority-carrier electrons in the base diffusing in
the direction of the concentration gradient and being swept across the collector-base
depletion region by the field existing there. Therefore, the diffusion current density
due to electrons in the base is
dnp(x)
Jn = qDn dx

where Dn is the diffusion constant for electrons. The derivative is the slope of the
concentration profile in the base which gives,
np(0)
Jn = -qDn W
B

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-5

Derivation of the BJT Large Signal Model in the Foward Active Region - Continued
3.) Continued
If the collector current is defined as positive flowing into the collector terminal, then
np(0)
vBE
qADnnpo
iC = qADn W B = W B exp Vt

where A is the cross-sectional area of the emitter. The desired result is


vBE
iC = IS exp Vt

where the saturation current, IS, is defined as


qADnnpo
IS = W
B
Since, ni2 = npoNA, we can rewrite IS as
qADnni2 qADnni2
IS = W BNA = QB
where QB is the number of doping atoms in the base per unit area of the emitter.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-6

Derivation of the Forward Current Gain of the BJT, F


1.) The base current, iB, consists of two major components. These components are due
to the recombination of holes and electrons in the base, iB1, and the injection of holes
from the base into the emitter, iB2. It can be shown that,
vBE
1 npoWBqA
iB1 = 2
exp Vt
b

2.) Therefore the total base current is

and

vBE
qADp ni2
iB2 = Lp ND exp Vt

1 n W qA qAD n 2
vBE
po B
p i

+ Lp ND exp Vt
iB = iB1 + iB2 = 2
b

3.) Define the forward active current gain, F, as


qADnnpo
iC
WB
1
F = iB = n W qA qAD n 2 = W 2 D W N 50 to 150
1 po B
p i
B
p B A
+ Lp ND
b
2bDn + Dn Lp ND
2
Note that F is increased by decreasing WB and increasing ND/NA.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-7

Derivation of the Current Gain from Emitter to Collector in Forward Active Region
iC
1.) Emitter to collector current gain is designated as, F = iE .
2.) Since sum of all currents flowing into the transistor must be zero, we can write that

iC
iC

iE = -(iC+iB) = - iC + F =- iC 1+ F = - F

F
F = 1 + F =

1
=
1
W 2 D W N T
1 + F 1 + B + p B A
2bDn Dn Lp ND

where

T Base Transport factor

1
W B2
1 + 2bDn

and
Emitter injection efficiency

CMOS Analog Circuit Design

1
Dp W B NA 1
1 + Dn Lp ND
P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-8

Large Signal Model for the BJT in the Forward Active Region
Large-signal model for a npn transistor:
iB
B

vBE

FiB

E
v
iB = Is exp BE
F
Vt

Assumes vBE is a
constant and iB is
determined externally

+
VBE(on)
E

FiB
E
Fig.070-05

Large-signal model for a pnp transistor:


iB
B

iB
C

vBE
E

FiB

E
iB = - Is exp -vBE
F
Vt

Assumes vBE is a
constant and iB is
determined externally

VBE(on)
+
E

Fi B
E
Fig.070-06

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-9

COLLECTOR VOLTAGE INFLUENCE ON THE LARGE SIGNAL MODEL


Base Width Dependence on the Collector-Emitter Voltage
The large signal model so far has the collector current as a function of only the baseemitter voltage. However, there is a weak dependence of the collector current on the
collector-emitter voltage that is developed here.
Influence of the base-collector depletion region width:

;;
;;
;;
;;

Carrier
Concentration

Emitter

;;;
;;;
;;;
;;;

Collector depletion
region widens due to a
change in vCE, VCE

np(0) = npo exp vBE


Vt
iC
iC+iC
WB
Base

Initial
Depletion
Region

Collector

WB

Fig.070-07

Note that the change of the collector-emitter voltage causes the amount of charge in the
base to change slightly influencing the collector current.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-10

The Early Voltage of BJTs


Previously we saw that,
vBE
qADnni2
iC = Q
exp V
B
t

Differentiation of iC with respect to vCE gives,


qADnni2 VBE QB
IC QB
iC
vCE = - QB2 exp Vt vCE = - QB vCE
For a uniform-base transistor, QB = WBNA so that the derivative becomes
iC
vCE
IC W B
IC
=

V
=
-W
A
B W B
vCE W B vCE
VA
where VA is called the Early voltage.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-11

Illustration of the Early Voltage


The output characteristics of an npn BJT:
iC

VBE4
VBE3
VBE2
VBE1

VA

vCE
Fig.070-08

Modified large signal model now becomes,

vBE
vCE

iC = IS 1 + VA exp Vt

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-12

SATURATION AND INVERSE ACTIVE REGIONS


Regions of Operation of the BJT
If we consider the transistor as back-to-back diodes, we can clearly see the four regions
of operation.
vBE
Forward Active Region
BE forward biased
BC reverse biased

Saturation Region
BE forward biased
BC forward biased

vBC
Cutoff Region
BE reverse biased
BC reverse biased

Inverse Active Region


BE reverse biased
BC forward biased

E
Fig.080-01

Note: While the back-to-back diode model is appropriate here, it is not a suitable model
for the BJT in general because it does not model the current gain mechanism of the BJT.
Essentially, the back-to-back diode model has a very wide base region and all the injected
carriers from the emitter recombine in the base (F = 0).
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-13

Saturation Region
In the saturation region, both the base-emitter and base-collector pn junctions are
forward biased.
Consequently, there is injection of electrons into the base from both the emitter and
collector.
The carrier concentrations in saturation are:

;;
;;
;;
;;
;;

Carrier
Concentration

nnE

pp(x)

np(0)

Electrons

pnE

pnE(0)

Emitter

CMOS Analog Circuit Design

np1(x)

np(x) iC
np2(x)
WB
Base

;;
;;
;;
;;

np(WB)

nnC

pnC

Electrons

x
Collector

Fig.080-02

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-14

Typical Output Characteristics for an npn BJT


iC(mA)
IB=0.04mA
5
0.03mA

4
3

0.02mA

Saturation
2
Cutoff
-8

-6
IB=0.01mA

IB=0

Forward
active
region

0.01mA

1
-4

-2

10
-0.02
Saturation
-0.04

0.02mA
0.03mA
Inverse
active
region

20

30
Cutoff

IB=0
40

VCE(V)

BVCEO

-0.06

0.04mA

-0.08
-0.10

Fig.080-04

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-15

Large Signal Model in Saturation


In saturation, both junctions are forward biased and the impedance levels looking into the
emitter or collector is very low.
Simplified model:

B
VBE(on)
E

C
VCE(sat)
E

VCE(sat)

VBE(on)

npn
where VBE(on) 0.6 to 0.7V and VCE(sat) 0.2V

CMOS Analog Circuit Design

pnp

Fig.1.3-11

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

The Ebers-Moll Large Signal Model


Consider the saturation condition with both pn junctions forward biased.
1.) The emitter injected current in the base resulting
from np1(x) is,
np(0)

v
BE
np(x) iC
iEF = -IES exp V - 1
t

np1(x)
where IES is a constant called saturation current
iCR np2(x)
2.) The collector injected current in the base resulting
from np2(x) is,
WB

v
Base
BC
iCR = -ICS exp Vt - 1

where ICS is a constant called saturation current


3.) The total collector current, iC, given as

vBE
vBC
iC = iCR + FiEF = FIES exp V - 1 -ICS exp V - 1
t
t

Also, we can write,

vBE
vBC
iE = iEF + RiCR = IES exp Vt - 1 +RICS exp Vt - 1

where R is the collector efficiency (as an emitter) and R = R/(1-R).

Page 3.7-16

np(WB)
iEF
x
Fig.080-06

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-17

The Ebers-Moll Equations - Continued


The reciprocity condition allows us to write,
FIEF = RICR = IS
Substituting into the previous form of the Ebers-Moll equations gives,

vBE IS vBC
iC = IS exp V - 1 -R exp V - 1
t
t

and

IS vBE
vBC
iE =-F exp Vt - 1 +IS exp Vt - 1

These equations are valid for all four regions of operation of the BJT.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-18

TRANSISTOR BREAKDOWN VOLTAGES


Common-Base Transistor Breakdown Characteristics
iC(mA)
1.5

IE=1.5mA

1.0

IE=1.0mA

iC
IE

VCB

IE=0.5mA

0.5

IE=0
Fig.080-08

20

40

60

80

100

VCB(V)

BVCBO

As the collector-base voltage becomes large, the collector current can be written as,
i C = - F i E M
where
1
M=
vCB n

1 - BV
CBO

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-19

Common-Emitter Transistor Breakdown Characteristics


Assume that a constant base current, iB, is applied. Using the previous result gives
iC
i C = - F i E M i E = - M
F
FM

iC = -(iE + iB)
iC 1- M = -iB
iC = 1- M iB
F
F

where,
1
vCB n
1 - BVCBO

Breakdown occurs when FM = 1.


Assuming that vCE vCB gives,
F
BVCEO
BVCBO
1-F 1/n
=
1

=
BVCEO n
BVCBO
F1/n
1 - BVCBO

Note that BVCEO is less than BVCBO. For F = 100 and n = 4, BVCEO 0.5BVCBO.
M=

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-20

DEPENDENCE OF F ON OPERATING CONDITIONS


Transistor F Dependence on Collector Current and Temperature
Plot of F as a function of iC:
F
400

Region I

Region II

Region I: Low current region where F


decreases as iC decreases.

Region III

T=125C
300

Region II: Midcurrent region where F


is approximately constant.

T=25C
200
T=-55C

Region III: High current region where


F decreases as iC increases.

100

0
0.1A

1A

10A

100A

1mA

10mA

iC
Fig.080-09

The temperature coefficient of F is,

1 F
TCF = F +7000ppm/C (ppm = parts per million)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-21

Variation of Forward Beta with Collector Current


ln i
Region II:
vBE
vBE
IS
iC = IS exp Vt and iB FM exp Vt

where FM = the maximum value of F.


Region I:

ln FH
iC ln FM
ln FL

vBE
vBE

iC = IS exp Vt and iBX = ISX expmVt

due to recombination, m 2
vBE
iC
IS
1
FL = iBX = ISX exp Vt 1 - m

ln Is

Region I

iB

Region
II

Region III

Fig.080-10

vBE
(linear scale)

IS iC[1-(1/m)]
for m = 2, FL iC
SX Is

Region III:
vBE
iC = ISH exp 2Vt due to the high level injection and

vBE
IS
iB FM exp Vt

vBE
ISH
ISH2
1

FH IS F exp- 2Vt IS FM iC

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-22

BJT, Common-Emitter, Forward-Active Region


Effect of a small-signal input voltage applied to a BJT.
Emitter
Depletion
Region

iC = IC + ic
iB = IB + ib
vi

VCC

VBE

;;;;;;
;;;
;
;;;;;;
;;;
;
;
;;;;;;
;;;
;
;;;;;;
;;;

Carrier
Concentration

Qh

Collector
Depletion
Region

np(0) = npo exp VBE+vbe


Vt

Qe

IC+ic

np(0) = npo exp VBE


Vt

IC

WB
Base

Emitter

x
Collector
Fig.090-02

An increase in vBE (vi) causes more electrons to be injected in the base increasing the
base current iB by an amount ib. The increased base current causes the collector current
iC to increase by an amount ic.
vi i b i c

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-23

Transconductance of the Small Signal BJT Model


The small signal transconductance is defined as
iC
diC |
i c ic
gm dv Q = v
=
=

ic = gmvi
BE
BE vbe vi
The large signal model for iC is
vBE
iC = IS exp V
t

gm =

vBE
IS
VBE IC
d
I
exp
=
exp

dvBE S
V t Q V t
Vt = Vt

IC
gm = V t

Another way to develop the small signal transconductance


VBE+vi
VBE
vi
vi

vi 1 vi 2 1 vi 3
iC = IS exp Vt = IS exp Vt expVt = IC expVt IC1 + Vt + 2 Vt + 6 Vt +

But
iC = IC + ic
vi IC vi
IC vi
IC
ic IC Vt + 2 Vt2 + 6 Vt3 + Vt vi = gmvi

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-24

Input Resistance of the Small Signal BJT Model


In the forward-active region, we can write that
iC
iB = F
Small changes in iB and iC can be related as
d iC
iB = diC FiC
The small signal current gain, o, can be written as
iC
ic
1
o = iB = d i = ib
C
diC F
Therefore, we define the small signal input resistance as
vi ovi o
r i = i = g
b
c
m

o
r = gm

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-25

Output Resistance of the Small Signal BJT Model


In the forward-active region, we can write that the small signal output conductance, go
(ro = 1/go) as
iC
diC |
ic
go dv Q = v
=

ic = govce
CE
CE vce
The large signal model for iC , including the influence of vCE, is

vCE
vBE

iC = IS 1 + V exp V
A
t

diC |
VBE IC
1
go dvCE Q = IS VA exp Vt VA

VA
ro = I C

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-26

Simple Small Signal BJT Model


Implementing the above relationships, ic = gmvi, ic = govce, and vi = rib, into a schematic
model gives,
C

B
+
vi

ib

ic
gmvi

ro

C
+
vce

E
Fig. 090-03

Note that the small signal model is the same for either a npn or a pnp BJT.
Example:
Find the small signal input resistance, Rin, the output resistance, Rout, and the voltage
gain of the common emitter BJT if the BJT is unloaded (RL = ), vout/vin, the dc collector
current is 1mA, the Early voltage is 100V, and at room temperature.
o
IC 1mA
1
gm = V = 26mV = 26 mhos
R
=
r
=
in
gm = 10026 = 2.6k
t
VA 100V
vout
Rout = ro = IC = 1mA = 100k
vin = -gm ro = - 26mS100k = -2600V/V
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-27

EXTENSIONS OF THE SMALL SIGNAL BJT MODEL


Collector-Base Resistance of the Small Signal BJT Model
Recall the influence of V on the base width:

;;
;;
;;
;;

Carrier
Concentration

Emitter

;;;
;;;
;;;
;;;

Collector depletion
region widens due to a
change in vCE, VCE

np(0) = npo exp vBE


Vt
iC
iC+iC
WB
Base

Initial
Depletion
Region

Collector

WB

Fig.3.7-6

We noted that an increase in vCE causes and increase in the depletion width and a
decrease in the total minority-carrier charge stored in the base and therefore a decrease in
the base recombination current, iB1.
This influence is modeled by a collector-base resistor, r, defined as
vCE vCE iC
iC
r = i
=
=
r
iC i1 o i1 oro (if base current is primarily recomb.)
1
In general, r 10 oro for the npn BJT and about 2-5 oro for the lateral pnp BJT.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-28

Base-Charging Capacitance of the Small Signal BJT Model


Consider changes in base-carrier concentrations once again.
Emitter
Depletion
Region

iC = IC + ic
iB = IB + ib
vi

VCC

Qh

np(0) = npo exp VBE+vbe


Vt

VBE

np(0) = npo exp VBE


Vt
Emitter

;;;;;;
;;;
;
;;;;;;
;;;
;
;
;;;;;;
;;;
;
;;;;;;
;;;

Carrier
Concentration

Collector
Depletion
Region

Qe

IC+ic
IC

x
Collector

WB
Base

Fig.3.7-16

The vBE change causes a change in the minority carriers, Qe = qe, which must be equal
to the change in majority carriers, Qh = qh. This charge can be related to the voltage
across the base, vi, as
qh = Cbvi
where Cb is the base-charging capacitor and is given as
qh F ic
IC
Cb = vi = vi = F gm = F Vt
W B2
The base transit time F is defined as 2Dn
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-29

Parasitic Elements of the BJT Small Signal Model


Typical cross-section of the npn BJT:
Collector

Base

Emitter
n+ emitter

p+

n+
p- isolation

rex
Cje

rb
rc3 C p base

Ccs

n collector

Cje

p- isolation

Ccs

rc1

rc2
n+ buried layer

p- substrate

p+

p-

ni

n-

n+

Metal

Fig.3.7-18

Cje = base-emitter depletion capacitance (forward biased)


C0
C = vCB = collector-base depletion capacitance (reverse biased)

m
1 -
0

Resistances are all bulk ohmic resistances. rb, rc, and rex are important. Also, rb = f(IC).
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-30

Complete Small Signal BJT Model


r
B

rb
C

B'
r

+
v1
-

gmv1

rc
ro

Ccs

rex
E

E
Fig. 3.7-19

The capacitance, C, consists of the sum of Cje and Cb.


C = Cje +Cb

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-31

Example
Derive the complete small signal equivalent circuit for a BJT at IC = 1mA, VCB = 3V, and
VCS = 5V. The device parameters are Cje0 = 10fF, ne = 0.5, 0e = 0.9V, C0 = 10fF, nc =
0.3, 0c = 0.5V, Ccs0 = 20fF, ns = 0.3, 0s = 0.65V, o = 100, F = 10ps, VA = 20V, rb =
300, rc = 50, rex = 5, and r = 10oro.
Solution
Because Cje is difficult to determine and usually an insignificant part of C, let us
approximate it as 2Cje0.
Cje = 20fF
C0
Ccs0
10fF
20F
C = V =
=
5.6fF
and
C
=
=
cs

3 0.3
5 0.3 = 10.5fF
VCSn
CBne

s
1+

1+
1+
1+
0.5
0.65

0c
0s

IC 1mA
Cb = F gm = (10ps)(38mA/V) = 0.38pF
gm = Vt = 26mV = 38mA/V
C = Cb + Cje = 0.38pF+0.02pF = 0.4pF
o
VA 20V
r =g =10026=2.6k, ro= I =1mA =20k, and r=10ro=1010020k =20M
m
C
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-32

FREQUENCY RESPONSE OF THE BJT


Transition Frequency, fT
fT is the frequency where the magnitude of the short-circuit, common-emitter current
equal unity.
io
C
rc
rb
Circuit and model:
ii

ii

+
v1
-

gmv1

ro

Ccs

io

Fig.3.7-20

Assume that rc 0. As a result, ro and Ccs have no effect.


r
gm r
o
Io(j)
V11+ r(C+Cb)s Ii and IogmV1 Ii(j) =
(C+Cb)s =
(C+Cb)s
1+ gmr gm
1+ o gm
o
Io(j)
(j) = Ii(j) =
Now,
(C+Cb)j
1+ o
gm
At high frequencies,
gm
gm
1 gm
(j) j (C+Cb) When | (j)| =1 then T = C+Cb or fT = 2 C+Cb
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-33

Illustration of the BJT Transition Frequency


as a function of frequency:
|(j)|
1000
o
-6dB/octave

100
10
1

0.1T

(log scale)
Fig.3.7-21

Note that the product of the magnitude and frequency at any point on the 6dB/octave
curve is equal to T.
For example,
0.1 T x10 = T
In measuring T, the value of |(j)| is measured at some frequency less than T (say
x) and T is calculated by taking the product of |(jx)| and x to get T.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-34

Current Dependence of fT
C C Cb Cje C
Cje C
1
Note that T = = gm + gm = gm + gm + gm = F + gm + gm
At low currents, the Cje and C terms dominate causing T to rise and T to fall.
At high currents, T approaches F which is the maximum value of T.
For further increases in collector current, T decreases because of high-level injection
effects and the Kirk effect.
Typical frequency dependence of fT:
fT (GHz)
10
8
6
4
2
0
10A

1mA

100A

IC
10mA Fig.3.7-22

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-35

NOISE MODEL FOR THE BJT


Model Development
Consider the BJT in the following mode of operation:
io

+
v in
-

Add all internal noise sources to the BJT small signal model to get:
B

rb

B'

v2b = 4kTrb f

+
r

i2b
E

I
= 2qIBf + K1 B f
f

v gmv

ro

io
i2c = 2qICf

Noise-free BJT

where
vb2 = thermal noise of the base resistance
ib2 = base shot and flicker noise currents
and
ic2 = collector shot and flicker noise currents
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-36

Equivalent BJT Noise Model


Find an equivalent input noise current, ii2 , and input noise voltage, vi2 , given as:
eeq2 =vi2

B
vin

rb

B'
r

ieq2 = ii2

C
C

v
gmv

ro

Noise-free BJT

io2
E

Fig. 3.7-25

To find ii2 and vi2 , perform the following steps:


1.) Short circuit the input and find io2 of both models and equate to get vi2 .
2,) Open circuit the input and find io2 of both models and equate to get ii2 .
Calculations:
1,) Short circuit the input (assume rb << r)
Ckt 1: io2 = g m 2 vb2 + ic2
Ckt 2: io2 = g m 2 vi2

ic2
veq2 = vi2 = vb2 + gm2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-37

Equivalent BJT Noise Model Continued


2.) Open circuit the input (assume rb << r)
Circuit 1:
r 2
sC

1 2
i 2
2
2
2
2 = ic2 + gm2r2
io = ic + gm
i
b
b

1
srC+1
r + sC
1 2
ib2 = ic2 + |(j)|2 ib2
io2 = ic2 + o2 s

+ 1
Circuit 2:

io2 = |(j)|2 ii2


Equating the above results gives
ic2
K1IBf 2qICf
2
2
2
ieq = ii = ib + |(j)|2 = 2qIBf +
f + |(j)|2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-38

Frequency Dependence of the BJT Noise Model


Frequency response of ii1 or ieq2 ,
A
Hz

i2eq = i2i
10-23

1/f

10-24

Thermal

Influence of
a decreasing

10-25
f
100 1k 10k 100k 1M 10M 100M1G

log f

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-39

Thermal Noise due to Parasitic Resistances


vc2 = 4kTrc/Area
ve2 = 4kTrc/Area
and
vb2 = 4kTrb/Area (already included)
Modified BJT noise model:
r
B

rb

B'

v2b = 4kTrb f

*
C

v gmv

rc

+
r

I
i2b = 2qIBf + K1 B f
f

v2c = 4kTrcf

ro

CCS

v2e = 4kTref

i2c = 2qICf

*
re

E
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 7 (5/2/04)

Page 3.7-40

COMPARISON OF THE MOS AND BIPOLAR TRANSISTORS


Quantity

MOS Transistor
2KW
2LID

Intrinsic Gain

T
Input Noise Voltage
(V2/Hz)

1
F

VT +

4kTrb +

VGS-VT R (W/L)
- W/L
2
R
1
D

Rin

2qIC
gm2

IC
IB a

2qIB + K1 f +
|(j)|2

Rout

gm

1
ID

gm
2KID
3
=
Cgs 2Cox
WL3
8kT
K
+
3gm WLCoxf

Input Noise Current


(A2/Hz)
Input Offset Voltage

Bipolar Transistor
VA
Vt

kT R AE QB
q - R - AE - QB
VA
IC
r
IC
Vt

2KWID
L

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 8 (5/2/04)

Page 3.8-1

SEC. 3.8 SPICE LEVEL 2 MODEL


SECOND-ORDER EFFECTS IN THE LARGE SIGNAL MODEL
Derivation of the Second-Order Model
VG > VT VD < VDS(sat)
Consider the following illustration of a
VSB
MOSFET in the active region:
B
S

;;;
;;;;;;;

Depletion
Region

Polysilicon

p+

;;;;;;;
n+

n+

v(y)

dy

p- substrate

Fig.3.8-1

Assume, the charge in the depletion region between the channel and bulk is no longer
constant and is dependent on v(y). Therefore, we model the dependence of threshold
voltage, VT, on y as
VT(y) = VT0 + 2|F| + vCB - 2F
where vCB is the voltage across the depletion region at y and is expressed as
vCB = vS + v(y) vB = v(y) + vSB
VT(y) = VT0 + 2|F| + v(y) + vSB - 2F
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 8 (5/2/04)

Page 3.8-2

Derivation of the Second-Order Model Continued


Now we repeat the previous analysis using this expression for VT.
The charge in the inversion layer was written as,
QI(y) = Cox vGS -v(y) -VT (y) = Cox vGS -v(y) -VT0 - 2|F| +v(y) +vSB + 2F
Using Ohms law for an increment, dy, of channel, we can write
iDdy
dv(y) = iDdR = nQI(y)W

iDdy = nWQI(y)dv(y)
Integrating this result over the channel from source to drain gives,
vDS

iD = dy = nWCox
0

vGS -v(y) -VT0 - 2|F| +v(y) +vSB + 2F dv

Evaluating the limits gives,

vDS
2
2

1.5
1.5
iDL = nWC vGS-VT0+ 2|F|- 2 vDS-3 2|F| +vSB+vDS +3 2|F|+vSB

nWCox
vDS
2
2
1.5+ 2| |+v 1.5

v
-V
+

2|

|v

2|

|+v
+v
or iD =

T0
F 2 DS 3 F SB DS
3 F SB
L
GS
These results agree with the first edition of the text if the following definitions are made:
si
VBIN VT0 - 2|F| ,
1
and 4C W 1
ox

ox

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 8 (5/2/04)

Page 3.8-3

SECOND-ORDER EFFECTS DUE TO SMALL GEOMETRIES


Second-Order Effects
1.) Mobility degradation, s
2.) Corrected threshold voltage, VBIN
3.) Corrected bulk threshold parameter, s
4.) Effective channel length, Lmod
New model:

sWCox
vDS
2

1.5
1.5
iD = Lmod vGS -VBIN - 2 vDS - 3s 2|F| +vSB+vDS + 2|F| +vSB

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 8 (5/2/04)

Page 3.8-4

Mobility Degradation
The degradation of the surface mobility o can be written as

UCRITsi
UEXP

s = o C [v -V -UTRAv ]
ox
GS
T
DS

where
UCRIT = Critical field for mobility degradation (Volts/cm)
UTRA = Transverse field coefficient for mobility degradation
UEXP = Critical field exponent for mobility degradation
Normally, s o

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 8 (5/2/04)

Page 3.8-5

Corrected Threshold Voltage


The corrected built-in threshold voltage for short channel transistors can be expressed as
si
VBIN = VFB + 2F + 4CoxW (2F - |vBS|)
where
= an empirical channel width factor which adjusts the threshold voltage
si
= 1 + 4CoxW

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 8 (5/2/04)

;;

Page 3.8-6

;;;;
;;;;
;;;
;;;;;
;;;;
;;;
;;;;;

Corrected Bulk Threshold Parameter


Consider the following geometrical
situation for short channels:

Polysilicon Gate

SourceXJ

WS

WS W

XJ+WS

Gate oxide

XJ Drain

XJ+WD

WD

Define the corrected bulk threshold


Bulk charge depleted
parameter as
by the gate field
Bulk/Substrate
s = (1-S - D)
Fig.3.8-2
where

2WS
XJ
S = 2L 1+ XJ - 1

2WD
XJ
D = 2L 1+ XJ - 1
where
XJ = metallurgical junction depth (meters)
2si
WS = source depletion width =
qNSUB (2F + |vSB|) )
2si
WD = Drain depletion width =
qNSUB (2F + |vSB| + vDS) )
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 8 (5/2/04)

Page 3.8-7

Effective Channel Length


Effective channel length, Lmod can be expressed as,
Lmod = Leff(1-vDS)
where
Leff = L 2XJLD
LD = lateral diffusion
1
= LeffvDS

2si
qNSUB

vDS-vDS(sat)
+
4

v
-v (sat)2
DS DS

1 +
4

and
vGS-VBIN s2
+ 22 1vDS(sat) =

2 vGS-VBIN

1+ 2
+
2

+
|v
|
F
BS

Other short channel effects not considered here:


Saturation due to scattering-limited velocity
Hot electron effects

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-1

SEC. 3.9 MODELS FOR SIMULATION OF MOS CIRCUITS


FET Model Generations
First Generation Physically based analytical model including all geometry
dependence.
Second Generation Model equations became subject to mathematical conditioning for
circuit simulation. Use of empirical relationships and parameter extraction.
Third Generation A return to simpler model structure with reduced number of
parameters which are physically based rather than empirical. Uses better methods of
mathematical conditioning for simulation including more specialized smoothing
functions.
Performance Comparison of Models (from Cheng and Hu, MOSFET Modeling & BSIM3
Users Guide)
Model

Minimum Minimum
Model
iD Accuracy in iD Accuracy in
L (m) Tox (nm) Continuity Strong Inversion Subthreshold
MOS1
5
50
Poor
Poor
Not Modeled
MOS2
2
25
Poor
Poor
Poor
MOS3
1
20
Poor
Fair
Poor
BSIM1
0.8
15
Fair
Good
Fair
BSIM2
0.35
7.5
Fair
Good
Good
BSIM3v2
0.25
5
Fair
Good
Good
BSIM3v3
0.15
4
Good
Good
Good

Small signal Scalability


parameter
Poor
Poor
Poor
Poor
Fair
Good
Good

Poor
Fair
Poor
Fair
Fair
Good
Good

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-2

First Generation Models


Level 1 (MOS1)
Basic square law model based on the gradual channel approximation and the square law
for saturated drain current.
Good for hand analysis.
Needs improvement for deep-submicron technology (must incorporate the square law to
linear shift)
Level 2 (MOS2)
First attempt to include small geometry effects
Inclusion of the channel-bulk depletion charge results in the familiar 3/2 power terms
Introduced a simple subthreshold model which was not continuous with the strong
inversion model.
Model became quite complicated and probably is best known as a developing ground
for better modeling techniques.
Level 3 (MOS3)
Used to overcome the limitations of Level 2. Made use of a semi-empirical approach.
Added DIBL and the reduction of mobility by the lateral field.
Similar to Level 2 but considerably more efficient.
Used binning but was poorly implemented.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-3

Second Generation Models


BSIM (Berkeley Short-Channel IGFET Model)
Emphasis is on mathematical conditioning for circuit simulation
Short channel models are mostly empirical and shifts the modeling to the parameter
extraction capability
Introduced a more detailed subthreshold current model with good continuity
Poor modeling of channel conductance
HSPICE Level 28
Based on BSIM but has been extensively modified.
More suitable for analog circuit design
Uses model binning
Model parameter set is almost entirely empirical
User is locked into HSPICE
Model is proprietary
BSIM2
Closely based on BSIM
Employs several expressions developed from two dimensional analysis
Makes extensive modifications to the BSIM model for mobility and the drain current
Uses a new subthreshold model
Output conductance model makes the model very suitable for analog circuit design
The drain current model is more accurate and provides better convergence
Becomes more complex with a large number of parameters
No provisions for variations in the operating temperature
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-4

Third Generation Models


BSIM3
This model has achieved stability and is being widely used in industry for deep
submicron technology.
Initial focus of simplicity was not realized.
MOS Model 9
Developed at Philips Laboratory
Has extensive heritage of industrial use
Model equations are clean and simple should be efficient
Other Candidates
EKV (Enz-Krummenacher-Vittoz) fresh approach well suited to the needs of analog
circuit design

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-5

BSIM2 Model
Generic composite expression for the model parameters:
LX WX
X = Xo + Leff + W
eff
where
Xo = parameter for a given W and L
LX (WX) = first-order dependence of X on L (W)
Modeling features of BSIM2:
Mobility
Mobility reduction by the vertical field
Mobility reduction by the lateral field
Drain Current
Velocity saturation
Linear region drain current
Saturation region drain current
Subthreshold current
oCoxWeff kT evGS-Vt-Voff

iDS =
q
1 - eqVDS/kT
Leff
n
where
Voff = VOF + VOFB vBS + VOFD vDS and

n = NO +

NB
+ ND vDS
PHI - vBS

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-6

BSIM2 Output Conductance Model


Rout

Saturation
(DIBL)

Linear
Region
(Triode)

Channel
length
modulation
(CLM)
0

vDS(sat)

Drain
current

Substrate
current
induced
body
effect
(SCBE)

5V

vDS
(3.1-2)

Drain-Induced Barrier Lowering (DIBL) Lowering of the potential barrier at the


source-bulk junction allowing carriers to traverse the channel at a lower gate bias
than would otherwise be expected.
Substrate Current-Induced Body Effect (SCBE) The high field near the drain
accelerates carriers to high energies resulting in impact ionization which generates a
hole-electron pair (hot carrier generation). The opposite carriers are swept into the
substrate and have the effect of slightly forward-biasing the source-substrate junction.
This reduces the threshold voltage and increases the drain current.
Charge Model
Eliminates the partitioning choice (50%/50% is used)
BSIM charge model better documented with more options
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-7

BSIM2 Basic Parameter Extraction


A number of devices with different W/L are fabricated and measured
Weff
Weff,3

10

11

12

Weff,2
Weff,1
Leff,1

Leff,2

Leff,3

Leff,4

Leff

A long, wide device is used as the base to add geometry effects as corrections.
Procedure:
1.) Oxide thickness and the differences between the drawn and effective channel
dimensions are provided as process input.
2.) A long, wide device is used to determine some base parameters which are used as
the starting point for each individual device extraction in the second phase.
3.) In the second phase, a set of parameters is extracted independently for each device.
This phase represents the fitting of the data for each independent device to the intrinsic
equation structure of the model
1.) In the third phase, the compiled parameters from the second phase are used to
determine the geometry parameters. This represents the imposition of the extrinsic
structure onto the model.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-8

BSIM2 Model used in Subthreshold


BSIM Model Parameters used in Subthreshold
VDS 1 0 DC 3.0
M1 1 1 0 0 CMOSN W=5UM L=2UM
.MODEL CMOSN NMOS LEVEL=4
+VFB=-7.92628E-01
LVFB= 1.22972E-02
WVFB=-1.00233E-01
+PHI= 7.59099E-01
LPHI= 0.00000E+00
WPHI= 0.00000E+00
+K1= 1.06705E+00
LK1= 5.08430E-02
WK1= 4.72787E-01
+K2=-4.23365E-03
LK2= 6.76974E-02
WK2= 6.27415E-02
+ETA=-4.30579E-03
LETA= 9.05179E-03
WETA= 7.33154E-03
+MUZ= 5.58459E+02
DL=6.86137E-001
DW=-1.04701E-001
+U0= 5.52698E-02
LU0= 6.09430E-02
WU0=-6.91423E-02
+U1= 5.38133E-03
LU1= 5.43387E-01
WU1=-8.63357E-02
+X2MZ= 1.45214E+01
LX2MZ=-3.08694E+01
WX2MZ= 4.75033E+01
+X2E=-1.67104E-04
LX2E=-4.75323E-03
WX2E=-2.74841E-03
+X3E= 5.33407E-04
LX3E=-4.69455E-04
WX3E=-5.26199E-03
+X2U0= 2.45645E-03
LX2U0=-1.46188E-02
WX2U0= 2.63555E-02
+X2U1=-3.80979E-04
LX2U1=-1.71488E-03
WX2U1= 2.23520E-02
+MUS= 5.48735E+02
LMUS= 3.28720E+02
WMUS= 1.35360E+02
+X2MS= 6.72261E+00
LX2MS=-3.48094E+01
WX2MS= 9.84809E+01
+X3MS=-2.79427E+00
LX3MS= 6.31555E+01
WX3MS=-1.99720E-01
+X3U1= 1.18671E-03
LX3U1= 6.13936E-02
WX3U1=-3.49351E-03
+TOX=4.03000E-002
TEMP= 2.70000E+01
VDD= 5.00000E+00
+CGDO=4.40942E-010
CGSO=4.40942E-010
CGBO=6.34142E-010
+XPART=-1.00000E+000
+N0=1.00000E+000
LN0=0.00000E+000
WN0=0.00000E+000
+NB=0.00000E+000
LNB=0.00000E+000
WNB=0.00000E+000
+ND=0.00000E+000
LND=0.00000E+000
WND=0.00000E+000
+RSH=0 CJ=4.141500e-04 CJSW=4.617400e-10
JS=0 PB=0.8
+PBSW=0.8
MJ=0.4726
MJSW=0.3597 WDF=0 DELL=0
.DC VDS 5.0 0 0.01
.PRINT DC ID(M1)
.PROBE
.END
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-9

Results of the BSIM2 Model Simulation in Subthreshold


100A
10A

iD

+
vGS

ID(M1)

1A

100nA
10nA
1nA
100pA
0V

0.4V

0.8V

VGS

1.2V

1.6V

2V

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-10

BSIM3 Model
The background for the BSIM3 model and the equations are given in detail in the text
MOSFET Modeling & BSIM3 Users Guide, by Y. Cheng and C. Hu, Kluwer Academic
Publishers, 1999.
The short channel effects included in the BSIM3 model are:
Normal and reverse short-channel and narrow-width effects on the threshold.
Channel length modulation (CLM).
Drain induced barrier lowering (DIBL).
Velocity saturation.
Mobility degradation due to the vertical electric field.
Impact ionization.
Band-to-band tunnelling.
Velocity overshoot.
Self-heating.
1.) Channel quantiztion.
2.) Polysilicon depletion.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-11

BSIM3v3 Model Equations for Hand Calculations


In strong inversion, approximate hand equations are:

W eff
AbulkvDS
1

v
-V
vDS < VDS(sat)
iDS = effCox Leff

2 vDS ,
vDS GS th
1+ EsatLeff

vDS - VDS(sat)
iDS = WeffvsatCox[vGS Vth AbulkVDS(sat)]1+
vDS > VDS(sat)
,
VA

where
EsatLeff(vGS-Vth)
VDS(sat) = AbulkEsatLeff + (vGS-Vth)
Leff = Ldrawn 2dL
W eff = W drawn 2dW
Esat = Electric field where the drift velocity (v) saturates
vsat = saturation velocity of carriers in the channel
2vsat
eff
eff = Esat
= 1+(Ey/Esat)
Note: Assume Abulk 1 and extract Vth and VA.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-12

MOSIS Parametric Test Results


http://www.mosis.org/
RUN: T02D
TECHNOLOGY: SCN025

VENDOR: TSMC
FEATURE SIZE: 0.25 microns

INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIS
test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar measurements on a
selected wafer are also attached.
COMMENTS: TSMC 0251P5M.
TRANSISTOR PARAMETERS
MINIMUM
Vth
SHORT
Idss
Vth
Vpt
WIDE
Ids0
LARGE
Vth
Vjbkd
Ijlk
Gamma
K (Uo*Cox/2)
CMOS Analog Circuit Design

W/L

N-CHANNEL

P-CHANNEL

UNITS

0.36/0.24
0.54

-0.50

volts

557
0.56
7.6

-256
-0.56
-7.2

uA/um
volts
volts

6.6

-1.5

pA/um

0.47
5.8
-25.0
0.44
112.0

-0.60
-7.0
-1.1
0.61
-23.0

volts
volts
pA
V0.5
uA/V2

20.0/0.24

20.0/0.24
50.0/50.0

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-13

0.25m BSIM3v3.1 NMOS Parameters


.MODEL CMOSN NMOS (
LEVEL = 49
+VERSION = 3.1
TNOM = 27
TOX = 5.7E-9
+XJ
= 1E-7
NCH = 2.3549E17
VTH0 = 0.4273342
+K1
= 0.3922983
K2
= 0.0185825
K3
= 1E-3
+K3B = 2.0947677
W0
= 2.171779E-7 NLX = 1.919758E-7
+DVT0W = 0
DVT1W = 0
DVT2W = 0
+DVT0 = 7.137212E-3 DVT1 = 6.066487E-3 DVT2 = -0.3025397
+U0
= 403.1776038 UA
= -3.60743E-12 UB
= 1.323051E-18
+UC
= 2.575123E-11 VSAT = 1.616298E5 A0
= 1.4626549
+AGS = 0.3136349
B0
= 3.080869E-8 B1
= -1E-7
+KETA = 5.462411E-3 A1
= 4.653219E-4 A2
= 0.6191129
+RDSW = 345.624986 PRWG = 0.3183394
PRWB = -0.1441065
+WR
=1
WINT = 8.107812E-9 LINT = 3.375523E-9
+XL
= 3E-8
XW
=0
DWG = 6.420502E-10
+DWB = 1.042094E-8 VOFF = -0.1083577 NFACTOR = 1.1884386
+CIT = 0
CDSC = 2.4E-4
CDSCD = 0
+CDSCB = 0
ETA0 = 4.914545E-3 ETAB = 4.215338E-4
+DSUB = 0.0313287
PCLM = 1.2088426
PDIBLC1 = 0.7240447
+PDIBLC2 = 5.120303E-3 PDIBLCB = -0.0443076 DROUT = 0.7752992
+PSCBE1 = 4.451333E8 PSCBE2 = 5E-10
PVAG = 0.2068286
+DELTA = 0.01
MOBMOD = 1
PRT = 0
+UTE = -1.5
KT1 = -0.11
KT1L = 0
+KT2 = 0.022
UA1 = 4.31E-9
UB1 = -7.61E-18
+UC1 = -5.6E-11
AT
= 3.3E4
WL
=0
+WLN = 1
WW
= -1.22182E-16 WWN = 1.2127
+WWL = 0
LL
=0
LLN = 1
+LW
=0
LWN = 1
LWL = 0
+CAPMOD = 2
XPART = 0.4
CGDO = 6.33E-10
+CGSO = 6.33E-10
CGBO = 1E-11
CJ
= 1.766171E-3
+PB
= 0.9577677
MJ
= 0.4579102
CJSW = 3.931544E-10
+PBSW = 0.99
MJSW = 0.2722644
CF
=0
+PVTH0 = -2.126483E-3 PRDSW = -24.2435379 PK2 = -4.788094E-4
+WKETA = 1.430792E-3 LKETA = -6.548592E-3 )
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-14

0.25m BSIM3v3.1 PMOS Parameters


MODEL CMOSP PMOS (
LEVEL = 49
+VERSION = 3.1
TNOM = 27
TOX = 5.7E-9
+XJ
= 1E-7
NCH = 4.1589E17
VTH0 = -0.6193382
+K1
= 0.5275326
K2
= 0.0281819
K3
=0
+K3B = 11.249555
W0
= 1E-6
NLX = 1E-9
+DVT0W = 0
DVT1W = 0
DVT2W = 0
+DVT0 = 3.1920483
DVT1 = 0.4901788
DVT2 = -0.0295257
+U0
= 185.1288894 UA
= 3.40616E-9 UB
= 3.640498E-20
+UC
= -6.35238E-11 VSAT = 1.975064E5 A0
= 0.4156696
+AGS = 0.0702036
B0
= 3.111154E-6 B1
= 5E-6
+KETA = 0.0253118
A1
= 2.421043E-4 A2
= 0.6754231
+RDSW = 866.896668 PRWG = 0.0362726
PRWB = -0.293946
+WR
=1
WINT = 6.519911E-9 LINT = 2.210804E-8
+XL
= 3E-8
XW
=0
DWG = -2.423118E-8
+DWB = 3.052612E-8 VOFF = -0.1161062 NFACTOR = 1.2546896
+CIT = 0
CDSC = 2.4E-4
CDSCD = 0
+CDSCB = 0
ETA0 = 0.7241245
ETAB = -0.3675267
+DSUB = 1.1734643
PCLM = 1.0837457
PDIBLC1 = 9.608442E-4
+PDIBLC2 = 0.0176785
PDIBLCB = -9.605935E-4 DROUT = 0.0735541
+PSCBE1 = 1.579442E10 PSCBE2 = 6.707105E-9 PVAG = 0.0409261
+DELTA = 0.01
MOBMOD = 1
PRT = 0
+UTE = -1.5
KT1 = -0.11
KT1L = 0
+KT2 = 0.022
UA1 = 4.31E-9
UB1 = -7.61E-18
+UC1 = -5.6E-11
AT
= 3.3E4
WL
=0
+WLN = 1
WW
=0
WWN = 1
+WWL = 0
LL
=0
LLN = 1
+LW
=0
LWN = 1
LWL = 0
+CAPMOD = 2
XPART = 0.4
CGDO = 5.11E-10
+CGSO = 5.11E-10
CGBO = 1E-11
CJ
= 1.882953E-3
+PB
= 0.99
MJ
= 0.4690946
CJSW = 3.018356E-10
+PBSW = 0.8137064
MJSW = 0.3299497
CF
=0
+PVTH0 = 5.268963E-3 PRDSW = -2.2622317 PK2 = 3.952008E-3
+WKETA = -7.69819E-3 LKETA = -0.0119828
)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-15

Adjustable Precision Analog Models Table Lookup


y
High
Level
Simulators

x1
x2

Circuit
Level
Simulators

x3
Process
Simulators

"Extraction" Methodology
I-V characterisitcs
Capacitances
Transconductances

Measurement
Methods

Objective
Develop models having adjustable precision in ac and dc perfomrance using table
lookup models.
Advantages
Usable at any level device, circuit, or behavioral
Quickly developed from experiment or process simulators
Faster than analytical device models (BSIM)
Disadvantages
Requires approximately 10kbytes for a typical MOS model
Cant be parameterized easily
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 9 (5/2/04)

Page 3.9-16

Summary of MOSFET Models for Simulation


Models are much improved for efficient computer simulation
Output conductance model is greatly improved
Poor results for narrow channel transistors
Can have discontinuities at bin boundaries
Fairly complex model, difficult to understand in detail

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-1

SEC. 3.10 EXTRACTION OF A LARGE SIGNAL MODEL FOR HAND


CALCULATIONS
Objective
Extract a simple model that is useful for design from the computer models such as
BSIM3.
Extraction for Short Channel Models
Procedure for extracting short channel models:
1.) Extract the square-law model parameters for a transistor with length at least 10
times Lmin.
2.) Using the values of K, VT , , and extract the model parameters for the following
model:
K
W
iD = 2[1 + (v -V )] L [ vGS VT]2(1+vDS)
GS
T
Adjust the values of K, VT , and as needed.

CMOS Analog Circuit Design


Chapter 3 Section 10 (5/2/04)

P.E. Allen - 2004


Page 3.10-2

EXTRACTION OF THE SIMPLE, SQUARE-LAW MODEL


Characterization of the Simple Square-Law Model
Equations for the MOSFET in strong inversion:
Weff
(v - V ) 2(1 + vDS)
iD = K
2Leff GS T

(1)

2
Weff
vDS
(v - V )v (1 + vDS)
iD = K
Leff GS T DS 2

(2)

where
VT = VT0 + [ 2|F| + vSB 2|F| ]

CMOS Analog Circuit Design

(3)

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-3

Extraction of Model Parameters:


First assume that vDS is chosen such that the vDS term in Eq. (1) is much less than one
and vSB is zero, so that VT = VT0.
Therefore, Eq. (1) simplifies to
Weff
(4)
iD = K2Leff (vGS - VT0) 2

This equation can be manipulated algebraically to obtain the following


K' Weff
K' Weff
1/2
1/2
1/2
iD = 2Leff
vGS = 2Leff VT0
(5)

which has the form


y = mx + b
(6)
This equation is easily recognized as the equation for a straight line with m as the slope
and b as the y-intercept. Comparing Eq. (5) to Eq. (6) gives
1/2

(7)
(8)

y = iD
x = vGS
K' Weff
1/2
m = 2Leff

(9)

and
K' Weff
1/2
b = - 2Leff
VT0

(10)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-4

Illustration of K and VT Extraction


1/2
(iD)

Mobility degradation
region

vDS >VDSAT
Weak inversion
region

0
0

b =VT0

1/2

K Weff

m=
2L eff

vGS
AppB-01

Comments:
Stay away from the extreme regions of mobility degradation and weak inversion
Use channel lengths greater than Lmin

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-5

Example 3.10-1 Extraction of K and VT Using Linear Regression


Given the following transistor data shown in Table 3.10-1 and linear regression formulas
based on the form,
y = mx + b
(11)
and
m=

xi yi - ( xi yi)/n

(12)

xi - (xi)2/n
1/2

determine VT0 and K W/2L. The data in Table B-1 also give I D as a function of VGS.
Table 3.10-1 Data for Example 3.10-1
VGS (V)
1.000
1.200
1.500
1.700
1.900

ID (A)
0.700
2.00
8.00
13.95
22.1

ID (A)1/2
0.837
1.414
2.828
3.735
4.701

VSB (V)
0.000
0.000
0.000
0.000
0.000

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-6

Example 3.10-1 Continued


Solution
The data must be checked for linearity before linear regression is applied. Checking
slopes between data points is a simple numerical technique for determining linearity.
Using the formula that
Slope = m =

ID2 - ID1
y
=
x VGS2 - VGS1

Gives
m1 =

1.414 - 0.837
= 2.885
0.2

m2 =

2.828 - 1.414
= 4.713
0.3

m3 =

3.735 - 2.828
= 4.535
0.2

m4 =

4.701 - 3.735
= 4.830
0.2

These results indicate that the first (lowest value of VGS) data point is either bad, or at a
point where the transistor is in weak inversion. This data point will not be included in
subsequent analysis. Performing the linear regression yields the following results.
K'Weff
2
and
VT0 = 0.898 V
2Leff = 21.92 A/V

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-7

Extraction of the Bulk-Threshold Parameter


Using the same techniques as before, the following equation
VT = VT0 + [ 2|F| + vSB 2|F| ]
is written in the linear form where
y = VT
x = 2|F| + vSB 2|F|
(13)
m=
b = VT0
The term 2|F| is unknown but is normally in the range of 0.6 to 0.7 volts.
Procedure:
1.) Pick a value for 2|F|.
2.) Extract a value for .
2si q NSUB
3.) Calculate NSUB using the relationship, =
Cox
kT NSUB
4.) Calculate F using the relationship, F = q ln ni
5.) Iterative procedures can be used to achieve the desired accuracy of and 2|F|.
Generally, an approximate value for 2|F| gives adequate results.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-8

Illustration of the Procedure for Extracting


A plot of iD versus vGS for different values of vSB used to determine is shown below.
(iD)1/2

VT0

VT1

VT2

VT3

vGS
FigAppB-02

By plotting VT versus x of Eq. (13) one can measure the slope of the best fit line from
which the parameter can be extracted. In order to do this, VT must be determined at
various values of vSB using the technique previously described.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-9

Illustration of the Procedure for Extracting - Continued


Each VT determined above must be plotted against the vSB term. The result is shown
below. The slope m, measured from the best fit line, is the parameter .
VSB =3V
VT

VSB =2V
VSB =1V

m=

VSB =0V
0.5

(vSB +2 F ) (2 F )

CMOS Analog Circuit Design


Chapter 3 Section 10 (5/2/04)

0.5
FigAppB-03

P.E. Allen - 2004


Page 3.10-10

Example 3.10-2 Extraction of the Bulk Threshold Parameter


Using the results from Ex. 3.10-1 and the following transistor data, determine the value of
using linear regression techniques. Assume that 2|F| is 0.6 volts.
Table 3.10-2 Data for Example 3.10-2.
VSB (V) VGS (V) ID (A)
1.000
1.400
1.431
1.000
1.600
4.55
1.000
1.800
9.44
1.000
2.000
15.95
2.000
1.700
3.15
2.000
1.900
7.43
2.000
2.10
13.41
2.000
2.30
21.2
Solution
Table 3.10-2 shows data for V SB = 1 volt and V SB = 2 volts. A quick check of the data in
this table reveals that ID versus V GS is linear and thus may be used in the linear
regression analysis. Using the same procedure as in Ex. 3.10-1, the following thresholds
are determined: VT0 = 0.898 volts (from Ex. 3.10-1), VT = 1.143 volts (@VSB = 1 V), and V T
= 1.322 V (@VSB = 2 V). Table 3.10-3 gives the value of VT as a function of [(2|F| + VSB)1/2
(2|F|)1/2 ] for the three values of VSB.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-11

Example 3.10-2 - Continued


Table 3.10-3 Data for Example 3.10-2.
VSB (V) VT (V) [ 2|F| + VSB - 2|F| ] (V1/2)
0.000
0.898
0.000
1.000
1.143
0.490
2.000
1.322
0.838
With these data, linear regression must be performed on the data of VT versus [(2|F| +
VSB)0.5 (2|F |)0.5]. The regression parameters of Eq. (12) are
xiyi = 1.668
xiyi = 4.466
2

xi = 0.9423
(xi)2 = 1.764
These values give m = 0.506 = .

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-12

Extraction of the Channel Length Modulation Parameter,


The channel length modulation parameter should be determined for all device lengths
that might be used. For the sake of simplicity, Eq. (1) is rewritten as
iD = iD= vDS + iD
which is in the familiar linear form where
y = iD (Eq. (1))
x = vDS
m = i'D
b = i'D (Eq. (1) with = 0)
iD

By plotting iD versus vDS, measuring the slope


of the data in the saturation region, and
dividing that value by the y-intercept, can be
determined. The procedure is illustrated in the
figure shown.

Nonsaturation
region
i'D

m = i'D

AppB-03
CMOS Analog Circuit Design

Saturation region

vDS
P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-13

Example 3.10-3 Extraction of the Channel Length Modulation Parameter


Given the data of ID versus VDS in Table 3.10-4, determine the parameter .
Table 3.10-4 Data for Example 3.10-3.
ID (A)
39.2 68.2 86.8 94.2 95.7 97.2 98.8 100.3
VDS (V)
0.500 1.000 1.500 2.000 2.50 3.00 3.50 4.00
Solution
We note that the data of Table 3.10-4 covers both the saturation and nonsaturation
regions of operation. A quick check shows that saturation is reached near V DS = 2.0 V. To
calculate , we shall use the data for VDS greater than or equal to 2.5 V. The parameters of
the linear regression are
xiyi = 1277.85
xiyi = 5096.00
(xi)2 = 169
x2i = 43.5
These values result in m = I'D = 3.08 and b = I'D = 88, giving = 0.035 V-1.
The slope in the saturation region is typically very small, making it necessary to be careful
that two data points taken with low resolution are not subtracted (to obtain the slope)
resulting in a number that is of the same order of magnitude as the resolution of the data
point measured. If this occurs, then the value obtained will have significant and
unacceptable error.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-14

EXTRACTION OF THE SIMPLE MODEL FOR SHORT CHANNEL MOSFETS


Extraction for Short Channel MOSFETS
The model proposed is the following one which is the square-law model modified by
the velocity saturation influence.
K
W
iD = 2[1 + (v -V )] L [ vGS - VT]2(1+vDS)
GS
T
Using the values of K, VT , , and extracted previously, use an appropriate extraction
procedure to find the value of adjusting the values of K, VT , and as needed.
Comments:
We will assume that the bulk will be connected to the source or the standard
relationship between VT and VBS can be used.
The saturation voltage is still given by
VDS( sat) = VGS - VT

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-15

Example of a Genetic Algorithm


1.) To use this algorithm or any other, use the simulator and an appropriate shortchannel model (BSIM3) to generate a set of data for the transconductance (iD vs. vGS)
and output characteristics (iD vs. vDS) of the transistor with the desired W and L
values.
2.) The best fit to the data is found using a genetic algorithm. The constraints on the
parameters are obtained from experience with prior transistor parameters and are:
0 < VT < 1, and 0 < < 0.5
10E-6 < < 610E-6, 1 < < 5,
3,) The details of the genetic algorithm are:
Gene structure is A = [, , VT, fitness]. A mutation was done by varying all four
parameters. A weighted sum of the least square errors of the data curves was used as
the error function. The fitness of a gene was chosen as 1/error.
4.) The results for an extraction run of 8000 iterations for an NMOS transistor is shown
below.

(A/V2)
VT(V)
(V-1)
294.1x10-6
1.4564
0.4190
0.1437
5.) The results for a NMOS and PMOS transistor are shown on the following pages.

Anurag Kaplish, Parameter Optimization of Deep Submicron MOSFETS Using a Genetic Algorithm, May 4, 2000, Special Project Report, School
of ECE, Georgia Tech.
CMOS Analog Circuit Design
P.E. Allen - 2004
Chapter 3 Section 10 (5/2/04)

Page 3.10-16

Extraction Results for an NMOS Transistor with W = 0.32m and L = 0.18m


Transconductance:

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-17

Extraction Results for an NMOS Transistor with W = 0.32m and L = 0.18m


Output:

CMOS Analog Circuit Design


Chapter 3 Section 10 (5/2/04)

P.E. Allen - 2004


Page 3.10-18

Extraction Results for an PMOS Transistor with W = 0.32m and L = 0.18m


Transconductance:

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 10 (5/2/04)

Page 3.10-19

Extraction Results for an PMOS Transistor with W = 0.32m and L = 0.18m


Output:

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 3 Section 11 (5/2/04)

Page 3.11-1

SEC. 3.11 - SUMMARY


Model philosophy for analog IC design
Use simple models for design and sophisticated models for verification
Models have several parts
Large signal static (dc variables)
Small signal static (midband gains, resistances)
Small signal dynamic (frequency response, noise)
Large signal dynamic (slew rate)
In addition models may include:
Temperature
Noise
Process variations (Monte Carlo methods)
Computer models
Must be numerically efficient
Quickly derived from new technology
Analog Design Tricks
Stay away from minimum channel length if possible
- Larger rds larger gains
- Better agreement
Dont use the computer models for design, rather verification of design
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Introduction (5/2/04)

Page 4.0-1

CHAPTER 4 CMOS SUBCIRCUITS


Chapter Outline
4.1 MOS Switch
4.2 MOS Diode/Active Resistor
4.3 Current Sinks and Sources
4.4 Current Mirrors
4.5 Current and Voltage References
4.6 Bandgap Reference
Goal
To develop an understanding of the sub-blocks and subcircuits used in CMOS analog
circuit design.
Design Hierarchy

Functional blocks or circuits


(Perform a complex function)

Blocks or circuits
(Combination of primitives, independent)

Sub-blocks or subcircuits
(A primitive, not independent)

Chapter 4

Fig. 4.0-1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Introduction (5/2/04)

Page 4.0-2

Illustration of Hierarchy in Analog Circuits for an Op Amp


Operational Amplifier

Biasing
Circuits

Current Current Current


Source Mirrors
Sink

Input
Differential
Amplifier

Second
Gain
Stage

Inverter
Source
Current
Coupled Pair Mirror Load

Current
Sink Load

Output
Stage

Source
Follower

Current
Sink Load
Fig. 4.0-2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-1

SECTION 4.1 - MOS SWITCH


Model for a Switch
An ideal switch is a short-circuit
when ON and an open-circuit when
OFF.

IOFF

rOFF
VOS

rON
A

B
CAB
CAC

IA

CA

CBC

IB

CB

VC

Fig. 4.1-1
Actual switch:
VC = controlling terminal for the switch (VC high switch ON, VC low switch OFF)
roff = resistance of the switch when OFF
ron = resistance of the switch when ON
VOS = offset voltage when the switch is ON Ioff = offset current when the switch is OFF
IA and IB are leakage currents to ground
CA and CB are capacitances to ground
CAC and CBC = parasitic capacitors between the control terminal and switch terminals
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-2

MOS Transistor as a Switch


Bulk
A

(S/D)

(D/S)

C (G)

Fig4.1-2

On Characteristics of a MOS Switch


Assume operation in active region (vDS < vGS - VT) and vDS small.
CoxW
vDS
CoxW
iD = L (vGS - VT) - 2 vDS L (vGS - VT)vDS
Thus,

vDS
1
RON iD = CoxW
L (vGS - VT)

OFF Characteristics of a MOS Switch


If vGS < VT, then iD = IOFF = 0 when vDS 0V.
If vDS > 0, then
1
1
ROFF iD = IOFF
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-3

MOS Switch Voltage Ranges


If a MOS switch is used to connect two circuits that can have analog signal that vary
from 0 to 1V, what must be the value of the bulk and gate voltages for the switch to work
properly?
Bulk

Circuit
1

(0 to 1V)

(0 to 1V)

(S/D)

(D/S)

Circuit
2

Gate

Fig.4.1-3

To insure that the bulk-source and bulk-drain pn junctions are reverse biased, the bulk
voltage must be less than the minimum analog signal for a NMOS switch.
To insure that the switch is on, the gate voltage must be greater than the maximum
analog signal plus the threshold for a NMOS switch.
Therefore:
VBulk 0V
and
VGate(on) > 1V + VT
Also,
VGate(off) 0V
Unfortunately, the large value of reverse bias bulk voltage causes the threshold voltage to
increase.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-4

Current-Voltage Characteristics of a NMOS Switch


The following simulated output characteristics correspond to triode operation of the
MOSFET.
100A

50A

VGS=3.0V
VGS=3.5V
VGS=4.0V
VGS=4.5V
VGS=5.0V

VGS=2.5V

VGS=2.0V
VGS=1.5V

iD 0A

VGS=1.0V

-50A

-100A
-1V

-0.5V

SPICE Input File:


MOS Switch On Characteristics
M1 1 2 0 3 MNMOS W=1U L=1U
.MODEL MNMOS NMOS VTO=0.7, KP=110U,
+LAMBDA=0.04, GAMMA=0.4 PHI=0.7
VDS 1 0 DC 0.0
CMOS Analog Circuit Design

0V
vDS

0.5V

1V
Fig. 4.1-4

VGS 2 0 DC 0.0
VBS 3 0 DC -5.0
.DC VDS -1 1 0.1 VGS 1 5 0.5
.PRINT DC ID(M1)
.PROBE
.END
P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-5

MOS Switch ON Resistance as a Function of Gate-Source Voltage

MOSFEET On Resistance

100k

10k
W/L = 1m/1m
1 k

W/L = 5m/1m
W/L = 10m/1m

100
W/L = 50m/1m
10
1V 1.5V 2V 2.5V 3V 3.5V 4V 4.5V 5V
Fig. 4.1-5
VGS

+LAMBDA=0.04, GAMMA=0.4, PHI=0.7


VDS 1 0 DC 0.001V
MOS Switch On Resistance as a f(W/L)
VGS 2 0 DC 0.0
M1 1 2 0 0 MNMOS W=1U L=1U
.DC VGS 1 5 0.1
M2 1 2 0 0 MNMOS W=5U L=1U
.PRINT DC ID(M1) ID(M2) ID(M3)
M3 1 2 0 0 MNMOS W=10U L=1U
ID(M4)
M4 1 2 0 0 MNMOS W=50U L=1U
.PROBE
.MODEL MNMOS NMOS VTO=0.7, KP=110U, .END

SPICE Input File:

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-6

Influence of the ON Resistance on MOS Switches


Finite ON Resistance:
vC(0) = 0
+
-

vin=2.5V

VGate

v
+ C vin>0

RON
Fig. 4.1-6

Example
Initially assume the capacitor is uncharged. If VGate(ON) is 5V and is high for 0.1s,
find the W/L of the MOSFET switch that will charge a capacitance of 10pF in five time
constants.
Solution
The time constant must be 100ns/5 = 20ns. Therefore RON must be less than
20ns/10pF = 2k. The ON resistance of the MOSFET (for small vDS) is
1
W
1
1
=1.06
RON = KN(W/L)(VGS-VT) L = RONKN(VGS-VT) =
2k110A/V24.3
Comments:
It is relatively easy to charge on-chip capacitors with minimum size switches.
Switch resistance is really not constant during switching and the problem is more
complex than above.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-7

Including the Influence of the Varying On Resistance


Gate-source Constant
ID
KW

gON(t) = L (vGS(t)-VT) -0.5vDS(t)


gON(0) + gON()
1
gON(aver.) = rON(aver.)
2
gON()
KWVDS(0) KW
KW
+ 2L (VGS-VT) t=
= 2L (VGS-VT) 4L
vDS()
KWVDS(0)
KW
= L (VGS-VT) 4L
Gate-source Varying
ID

gON(0)

t=0

t=0

vDS(0)

VGS=5V

VDS
Fig. 4.1-7

VGate
+
vGS(t)
-

VGS=5V

vIN
VGS=5V-vIN

gON(0)

+
C

vC(0) = 0

gON()
t=
vDS()

vDS(0)

VDS

Fig. 4.1-8

KWVDS(0) KW
KW
gON = 2L [VGS(0)-VT] + 2L [VGS()-vIN-VT]
4L
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Example 4.1-1 - Switch ON Resistance


5V
Assume that at t = 0, the gate of the switch shown is
taken to 5V. Design the W/L value of the switch to 0V
discharge the C1 capacitor to within 1% of its initial
+ C1 =
charge in 10ns. Use the MOSFET parameters of Table
5V
3.1-2.
- 10pF

Page 4.1-8

C2 = 10pF
0V
vout(t)
+ +
Fig.4.1-9

Solution
Note that the source of the NMOS is on the right and is always at ground potential so
there is no bulk effect as long as the voltage across C1 is positive. The voltage across C1
can be expressed as

-t
vC1(t) = 5expR C
ON 1
At 10ns, vC1 is 5/100 or 0.05V. Therefore,

-103
ln(100)
-10-8

exp(G 103)=100 G
=
5exp
=
=0.0046S
0.05=5exp

ON
ON
RON
RON10-11
103

KWVDS(0)
KW
110x10-65W
W
-6
-6
110x10 4.3
0.0046 = L (VGS-VT) =
=
356x10
4L
4
L

L
W
0.0046
Thus, L =
= 13.71 14
356x10-6
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-9

Influence of the OFF State on MOS Switches


The OFF state influence is primarily in any current that flows from the terminals of the
switch to ground.
An example might be:
vin

RBulk

CH

+
vCH
-

vout

Fig. 4.1-10

Typically, no problems occur unless capacitance voltages are held for a long time. For
example,
vout(t) = vCH e-t/(RBulkCH)
If RBulk 109 and CH = 10pF, the time constant is 10910-11 = 0.01seconds

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-10

Influence of Parasitic Capacitances


The parasitic capacitors have two influences:
Parasitics to ground at the switch terminals (CBD and CBS) add to the value of the
desired capacitors.
This problem is solved by the use of stray-insensitive switched capacitor circuits
Parasitics from gate to source and drain cause charge injection onto or off the desired
capacitors.
This problem can be minimized but not eliminated.
Model for studying charge injection:
1
1

CL

+
vCL
-

A simple switch circuit useful


for studying charge injection.

CMOS Analog Circuit Design

Cchannel

CGS0

CGD0
Rchannel

CL

VS

A distributed model of
the transistor switch.

+
vCL
-

Cchannel
2

2
CGS0

VS

Cchannel

CGD0
Rchannel

CL

VS

A lumped model of
the transistor switch.

+
vCL
-

Fig. 4.1-11

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-11

Charge Injection (Clock feedthrough, Charge feedthrough)


Charge injection is a complex analysis which is better suited for computer analysis.
Here we will attempt to develop an understanding sufficient to show ways of reducing the
effect of charge injection.
What is Charge Injection?
1.) When the voltages change across the gate-drain
and gate-source capacitors, a current will flow
dv
because i = C dt .
2.) When the switch is off, charge injection will
appear on the external capacitors (CL) connected to
Fig. 4.1-12
the switch terminals causing their voltages to change.
There are two cases of charge injection depending upon the transition rate when the
switch turns off.
1.) Slow transition time.
2.) Fast transition time.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-12

Slow Transition Time


Consider the following switch circuit:
A
Switch ON
B
vin+VT
C

A
B
Switch OFF

vin+VT
C
Charge
injection

vin

CL

vin

CL
Fig. 4.1-13

1.) During the on-to-off transition time from A to B, the charge injection is absorbed by
the low impedance source, vin.
2.) The switch turns off when the gate voltage is vin+VT (point B).
3.) From B to C the switch is off but the gate voltage is changing. As a result charge
injection occurs to CL.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-13

Fast Transition Time


For the fast transition time, the rate of transition is faster than the channel time constant
so that some of the charge during the region from point A to point B is injected onto CL
even though the transistor switch has not yet turned off.
A
A
Switch ON
B
B
vin+VT
vin+VT
Switch OFF
C
C
Charge
injection

Charge
injection

vin

vin

CL

CL
Fig. 4.1-14

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-14

A Quantized Model of Charge Injection


Approximate the gate transition as a stair case and discretize in voltage as follows:
Voltage

Voltage
Discretized Gate Voltage

Discretized Gate Voltage


vGATE

vGATE
vin+VT
vin

vin+VT
vin
vCL
Slow Transition

vCL
Fast Transition

Charge
injection
due to fast
transition
t
Fig 4.1-15

The time constant of the channel, RchannelCchannel, determines whether or not the
capacitance, CL, fully charges during each voltage step.

B.J. Sheu and C. Hu, Switched-Induced Error Voltage on A Switched Capacitor, IEEE J. Solid-State Circuits, Vol. SC-19, No. 4, pp. 519-525,
August 1984.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-15

Analytical Expressions to Approximate Charge Injection


Assume the gate voltage is making a transition from high, VH, to low, VL.
vGate = vG(t) = VH - Ut
where U = magnitude of the slope of vG(t)
KW
Define VHT = VH - VS - VT and = L .
The error in voltage across CL, Verror, is given below in two terms. The first term
corrsponds to the feedthrough that occurs while the switch is still on and the second term
corresponds to feedthrough when the switch is off.
2

VHT
1.) Slow transition occurs when 2CL >> U.

C
WCGD0 + channel
UCL WCGD0
2

(VS+2VT -VL)
Verror = -
CL
2 CL

VHT
2.) Fast transition occurs when 2C << U.
L

Cchannel
3
WCGD0 +

V
2
HT WCGD0

(VS+2VT -VL)
Verror = -
CL
CL
VHT - 6UCL CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-16

Expression for Feedthrough when the Switch is OFF


The model for this case is given as:
A
B
Switch OFF
COL

vin VS VD

VS +VT
C

VT

VL

COL

Charge
injection

CL

COL
+

VS +V T

Circuit at the VL
instant gate
reaches VS +VT

CL

vCL

VS
Fig. 4.1-16

The switch decrease from B to C is modeled as a negative step of magnitude VS +VT - VL.
The output voltage on the capacitor after opening the switch is,

COL
COL
CL COL

vCL = COL+CLVS-COL+CLVT -(VS+VT -VL)COL+CL VS-(VS+2VT -VL) CL

if COL < CL.


Therefore, the error voltage is
COL
COL

Verror -(VS + 2VT - VL) CL = -(vin + 2VT - VL) CL

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-17

Example 4.1-2 - Calculation of Charge Feedthrough Error


vG
Calculate the effect of charge feedthrough
on the previous circuit where VS = 1V, CL 5V
= 200fF, W/L = 0.8m/0.8m, and VG is
Case 2
given below for the two cases. Use model
parameters from Tables 3.1-2 and 3.2-1.
Case 1
Neglect L and W effects.
0V
t
Solution
0.2ns
Fig. 4.1-17
10ns
Case 1:
The value of U is equal to 5V/0.2nS or 25x109. Next we must test to see if the slow
or fast transition time is appropriate. First calculate the value of VT as
VT = VT0 + 2|F| -VBS - 2|F| = 0.7 + 0.4 0.7+1 - 0.4 0.7 = 0.887V
Therefore,
2

VHT 110x10-63.1132
= 2.66x109 < 25x109
VHT =VH-VS-VT = 5-1-0.887=3.113V 2CL =
2200fF
which corresponds to the fast transition case. Using the previous expression gives,
Verror =
176x10-18+0.5(1.58x10-15)
3.32x10-3 176x10-18

-
3.113- 30x10-3 - 200x10-15(1+1.774-0) = -16.94mV
200x10-15
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-18

Example 4.1-2- Continued


Case 2:
In this case U is equal to 5V/10ns or 5x108 which means that the slow transition case
is valid (5x108 < 2.66x109).
Using the previous expression gives,
176x10-18+0.5(1.58x10-15)

Verror = -

200x10-15

314x10-6 176x10-18
(1+1.774-0) = -8.21mV
220x10-6 200x10-15

Comment:
These results are not expected to give precise answers regarding the amount of
charge feedthrough one should expect in an actual circuit. Rather, they are a guide to
understand the effects of various circuit elements and terminal conditions in order to
minimize unwanted behavior by design techniques.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-19

Solutions to Charge Injection


1.) Use minimum size switches to reduce the overlap capacitances and/or increaseCL.
2.) Use a dummy compensating transistor.
1

W1
L1

WD = W1
LD 2L1

M1

MD
Fig. 4.1-19

Requires complementary clocks


Complete cancellation is difficult and may in fact may make the feedthrough worse
3.) Use complementary switches (transmission gates)
4.) Use differential implementation of switched capacitor circuits (probably the best
solution)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-20

Input-Dependent Charge Injection


Examination of the error voltage reveals that,
Error voltage = Component independent of input + Component dependent on input
This only occurs for switches that are floating and is due to the fact that the input
influences the voltage at which the transistor switches (vin VS VD). Leads to
spurious responses and other undesired results.
Solution:
1
Use delayed clocks to
Ci
remove the input-depend2
Cs
2
Vin 1d
ence by breaking the
S1
S4
Vout
current path for injection
2 S2 S3 1
CL
from the floating switches.

1d

Assume that Cs is charged


t
to Vin (both 1 and 1d
Clock Delay
Fig. 4.1-20
are high):
1.) 1 opens, no input-dependent feedthrough because switch terminals (S3) are at
ground potential.
2.) 1d opens, no feedthrough occurs because there is no current path (except through
small parasitic capacitors).
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-21

CMOS Switches (Transmission Gate)


Clock
Clock
A

VDD

Clock
Clock

Fig. 4.1-21

Advantages:
Feedthrough somewhat diminished
Larger dynamic range
Lower ON resistance
Disadvantages:
Requires a complementary clock
Requires more area

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Example 4.1-3 - Charge Injection for a CMOS Switch


Calculate the effect of charge feedthrough on the
circuit shown below. Assume that U = 5V/50ns =
108V/s, vin = 2.5V and ignore the bulk effect. Use
the model parameters from Tables 3.1-2 and 3.2-1.
Solution
vin
First we must identify the transition behavior. For
the NMOS transistor we have
2
NVHTN 110x10-6(5-2.5-0.7)2
= 1.78x108
2CL =
210-12

Page 4.1-22

5V
vin-|VTP|
0.8m
0.8m

M2

0.8m
0.8m

0V

M1
5V

0V

CL =
1pF

+
vCL
vin+VTN
Fig. 4.1-18

For the PMOS transistor, noting that


VHTP = VS - |VTP| - VL = 2.5-0.7-0 = 1.8
2

PVHTP 50x10-6(1.8)2
= 8.10x107 . Thus, the NMOS transistor is in the
we have 2CL =
210-12
slow transition and the PMOS transistor is in the fast transition regimes.
Error due to NMOS:
176x10-18 + 0.5(1.58x10-15)
10810-12 176x10-18

(2.5+1.4-0)
Verror(NMOS) = -

10-12
2110x10-6
10-12
= -1.840mV
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-23

Example 4.1-3 - Continued


Error due to PMOS:
176x10-18+0.5(1.58x10-15)
50x10-6(1.8)3 176x10-18

Verror(PMOS) =
1.8- 610810-12 + 10-12 (5+1.4-2.5)
10-12

= 1.956mV
Net error voltage due to charge injection is 116V. This will vary with VS.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-24

VDD

M1
A

B
VDD

VA,B

10k

Switch On Resistance

Dynamic Range of the CMOS Switch


The dynamic range of a switch is the
range of voltages at the switch
terminals (VAVB=VA,B) over which
the ON resistance stays reasonably
small.

1A

VDD
=1V

VDD=1V

8k
VDD
=1.5V

VDD=1.5V

6k
VDD=2V
4k

VDD
=2V

2k

VDD=2.5V
VDD=3V

M2

0
Fig. 4.1-22

Spice File:
Simulation CMOS transmission switch resistance
M1 1 3 2 0 MNMOS L=1U W=10U
M2 1 0 2 3 MPMOS L=1U W=10U
.MODEL MNMOS NMOS VTO=0.7, KP=110U,
+LAMBDA=0.04, GAMMA=0.4, PHI=0.7
.MODEL MPMOS PMOS VTO=-0.7, KP=50U,
+ LAMBDA=0.05, GAMMA=0.5, PHI=0.8

0V

0.5V

1V
1.5V
2V
2.5V
3V
VA,B (Common mode voltage)
Fig. 4.1-22A

VDD 3 0
VAB 1 0
IA 2 0 DC 1U
.DC VAB 0 3 0.02 VDD 1 3 0.5
.PRINT DC V(1,2)
.END

Result:
Low ON resistance over a wide voltage range is difficult as the power supply decreases.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-25

CMOS Switch with Twin-Well Switching


V Control
M1

VDD
M3
Analog
Signal
Input

M4

Analog
Signal
Output

M5

V SS
M2

V Control

Circuit when VControl is in its high state.

Circuit when VControl is in its low state.


Low State

High State

M1

M1
Analog
Signal
Input

VSS

Analog
Signal
Input

Analog
Signal
Output

VDD

Analog
Signal
Output

M2

M2

High State

Low State

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-26

Charge Pumps for Switches with Low Power Supply Voltages


As power supply voltages decrease below 3V, it becomes difficult to keep the switch
on at a low value of on-resistance over the range of the power supply. Consequently,
charge pumps are used.
Charge pump circuit:
VDD = 3.3V

(Prevents latchup)
To a
single
NMOS
switch
Vhi 5V

Vsub_hi
M1

0V

C2

C1

CL
3.3V

0V

0V

C2
Vhi = 2VDDCgate,NMOS switch + C2 + CL
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-27

Charge Pump - Continued


High voltage generator for the well of M1:
VDD=3.3V
6.6V
Vsub_hi

3.3V

C1

C2

CBulk

CStorage

0V

Fig. 4.1-225

Prevents latch-up of M1 by providing a high bulk bias (6.6V).


Use a separate clock driver for each switch to avoid crosstalk through the gate clock
lines. Area for layout can be small.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-28

Simulation of the Charge Pump Circuit


Circuit:
CLK_out

M1

M2
M3

M5
C1

C1
M4

M6

CLK_in

VDD
CLK_out

VSS

Fig. 4.1-23

Simulation:
3.0
Output
2.0

Volts

Input
1.0

0.0

-1.0
0.0

1.0

2.0

3.0

4.0

5.0
6.0
Time (s)

7.0

8.0

9.0

10.0
Fig. 4.1-24

T.B. Cho and R.R. Gray, A 10b, 20 Msample/s, 35mW Pipeline A/D Converter, IEEE J. of Solid-State Circuits, Vol. 30, No. 3m March 1995, pp.
166-172.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-29

Bootstrapped Switches with High Reliability


In the previous charge pump switch driver, the amount of gate-source drive depends
upon the input signal and can easily cause
reliability problems because it becomes too large
VDD
for low values of input signal.
The solution to this problem is a
bootstrapped switch as shown.
OFF
ON Fig. 4.1-25
Actual bootstrap switch:
VDD
M2

M1

M3

vg

Boosted Clock

M4

VDD

M8
C1

M7

C2
C3

M5

M12

VDD
Input Signal

vg

M13

M10

M9
S

t
M11

Fig. 4.1-26

low: M7 and M10 make vg=0 and C3 charges to VDD, high: C3 connected to vGS11.
M7 reduces the vDS and vGS of M10 when = 0. M13 ensures that vGS8 VDD.
The parasitics at the source of M11 require this node to be driven from a low impedance.

A.M. Abo and P.R. Gray, A 1.5V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, IEEE J. of Solid-State Circuits, Vol. 34, No. 5,
May 1999, pp. 599-605.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 4 Section 1 (5/2/04)

Page 4.1-30

Summary of MOSFET Switches

Symmetrical switching characteristics


High OFF resistance
Moderate ON resistance (OK for most applications)
Clock feedthrough is proportional to size of switch (W) and inversely proportional to
switching capacitors.
Output offset due to clock feedthrough has 2 components:
Input dependent
Input independent
Complementary switches help increase dynamic range.
Fully differential operation should minimize the clock feedthrough.
As power supply reduces, switches become more difficult to fully turn on.
Switches contribute a kT/C noise which can get folded back into the baseband.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-1

SECTION 4.2 - MOS DIODE/ACTIVE RESISTOR


MOS Diode
When the MOSFET has the gate connected to the drain, it acts like a diode with
characteristics similar to a pn-junction diode.
i
+

i
vSG = v

vGS = v

i
-

VT

Fig. 4-2-1

Note that when the gate is connected to the drain of an enhancement MOSFET, the
MOSFET is always in the saturation region.
vDS vGS - VT

vD - vS vG - vS - VT vD - vG -VT

vDG -VT

Since VT is always greater than zero for an enhancement device, then vDG = 0 satisfies
the conditions for saturation.
Works for NMOS or PMOS
Note that the drain could be VT less than the gate and still be in saturation
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-2

Large-Signal and Small-Signal Characteristics of the MOS Diode


Large-Signal Characteristics:
Ignore channel modulation2iD

KW
i = iD = 2L (vGS - VT)2 = 2 (vGS - VT)2 and v = vGS = vDS = VT +

Small-Signal Characteristics:
The small signal model is a linearization of the large signal model at an operating point.

iD = 2 (vGS-VT)2(1+vDS) d + ID = 2 [vgs+(VGS-VT)]2[1+(vds+VDS)]

id+ID = 2 vgs2 + (VGS-VT)vgs + 2 (VGS-VT)2 + 2 vgs2vds + (VGS-VT)vgsvds

+ 2 (VGS-VT)2vds + 2 vgs2VDS + (VGS-VT)vgsVDS + 2 (VGS-VT)2VDS


Assume that vgs < VGS-VT, vds < VDS and <<1. Therefore we write:

id+ID (VGS-VT)vgs + 2 (VGS-VT)2vds + 2 (VGS-VT)2(1+VDS)

id = (VGS-VT)vgs+ 2 (VGS-VT)2vds = gmvgs+gdsvds and ID = 2 (VGS-VT)2(1+VDS)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-3

Application of the MOS Diode


DC resistor:

i
AC Resistance

v
V
DC resistance = i = I
Q

DC Resistance

ID

Useful for biasing - creating current from voltage


and vice versa

VDS

VT

Fig. 4-2-2B

Small-Signal Load (AC resistance):


D

id

+
vgs

+
vbs

gmvgs

gmbsvbs

rds

+D
vds
-

Fig. 4.2-4

vds
1
1
AC resistance = i = g + g g
d
m
ds
m
where
gm = (VGS-VT) = 2ID

and gds 2 (VGS-VT)2 = ID

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-4

Influence of the Back Gate (Bulk)


It can be shown that the small signal model for the MOSFET with the bulk not connected
to the source is,
D

id

B
S

G
B

+
vgs

+
vbs
-

gmvgs

gmbsvbs

rds

+D
vds
-

Fig. 4.2-4

where
iD vT
D iD vGS

gmbs is defined as vBS Q = vGS vBS = - vTvBS

gm
gmbs =
= gm
2 2|F| - VBS
It is very useful to simplify the small signal model when possible. The following are
reasonable guidelines for this simplification:
gm 10gmbs 100gds
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-5

Example 4.2-1 - Small-Signal Load Resistance


VDD = 5V
Find the small signal resistance of the MOS diode
shown using the parameters of Table 3.2-1.
Assume that the W/L ratio is 10m/1m.
Solution
rac
If we are going to include the bulk effect, we must first find
the dc value of the bulk-source voltage. Unfortunately, we do not
know the threshold voltage because the bulk-source voltage is
100A
unknown. The best approach is to ignore the bulk-source voltage,
find the gate-source voltage and then iterate if necessary.

Fig. 4.2-5

2I

2100
VGS =
+ VT0 =
11010 + 0.7 = 1.126V
Thus let us guess at a gate-source voltage of 1.3V (to account for the bulk effect) and
calculate the resulting gate-source voltage.

VT = VT0+ 2|F|-(-3.7)- 2|F| = 0.7+0.4 0.7+3.7-0.4 0.7 = 1.20V VGS = 1.63V


Now refine our guess at VGS as 1.6V and repeat the above to get VT = 1.175V which
gives VGS = 1.60V.
Therefore, VBS = -3.4V.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Example 4.2-1 - Continued


The small signal model for this example is shown.
The ac input resistance is found by,
iac = gdsvac - gmvgs - gmbsvbs
= gdsvac + gmvs + gmbsvs = vac(gm+gmbs+gds)
vac
1
rac = i = g +g
ac
m mbs+gds
Now we must find the parameters which are,

Page 4.2-6

id

G,D,B
gmvgs

rds

gmbsvbs

+
vds = vgs

rac
vac

iac Fig. 4.2-6

gm = 2ID = 211010100 S = 469S, gds = 0.04V-1100A = 4S,


469S0.4
= 0.0987469S = 46.33S
and gmbs =
2 0.7+3.4
Finally,

106
rac = 469 + 46.33 + 4 = 1926

If we had used the previous approximations of gm 10gmbs 100gds, then we could have
simply let
rac 1/gm = 1/469S = 2132
Probably the most important result of this approximation is that we would not have to
find VBS which took a lot of effort for little return.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-7

Applications of the MOS Diode for Biasing


1.) Deriving a bias voltage from power supply.

VDD

M2

ID1 = ID2 N(VBias-VTN)2 = P(VDD-VBias-|VTP|)2


Solving for VBias gives

ID

P
N (VDD-|VTP|)
VBias =
and ID = N(VBias-VTN)2
P
1 + N
Use the ratio of P/N to design VBias and the value of N to design

+
VBias

VTN +

M1

Fig. 4.2-7

the current ID.

VDD

2.) Deriving a bias voltage from a bias current.


VBias = VGS1+ VGS2
=

2IBias
1

+ VT1 +

2IBias
2

IBias

M2

+ VT2

Design 1 and 2 to yield the desired value of VBias. Try to keep


the values of W/L as close to unity as possible to minimize area.

M1

VBias

Fig. 4.2-8

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-8

Use of the MOSFET to Implement a Floating Resistor


In many applications, it is useful to implement a
resistance using a MOSFET. First, consider the
A
simple, single MOSFET implementation.
L
RAB = KW(VGS - VT)

VBias
B

RAB

Fig. 4.2-9

100A
VGS=10V
VGS=9V
60A

VGS=8V
VGS=7V

20A
VGS=2V
-20A
VGS=3V
VGS=4V
-60A
VGS=5V
VGS=6V
-100A
-1V
CMOS Analog Circuit Design

-0.6V

-0.2V

0.2V

0.6V

1V Fig. 4.2-95
P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-9

Cancellation of Second-Order Voltage Dependence Parallel MOSFETs


Circuit:
VDD

VDD

IBias

IBias
+

+
M1
VC
M2

iAB
A
+

VC
-

B
-

iAB
A
+

RAB
vAB

vAB

B
-

Fig. 4.2-10

Assume both devices are non-saturated

vAB2
iD1 = 1 (vAB + VC - VT)vAB - 2

vAB2
iD2 = 2 (VC - VT)vAB - 2

vAB2
vAB2
iAB = iD1 + iD2 = vAB2 + (VC - VT)vAB - 2 + (VC - VT)vAB - 2
iAB = 2(VC - VT)vAB
1
R AB = 2(VC - VT)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-10

Parallel MOSFET Performance


Voltage-Current Characteristic:
2mA

Vc=7V
6V
5V

I(VSENSE)

1mA

4V

W=15u
L=3u
VBS=-5.0V

3V

-1mA

-2mA

-2

-1

VDS

2 Fig. 4.1-11

SPICE Input File:


NMOS parallel transistor realization
M1 2 1 0 5 MNMOS W=15U L=3U
M2 2 4 0 5 MNMOS W=15U L=3U
.MODEL MNMOS NMOS VTO=0.75, KP=25U,
+LAMBDA=0.01, GAMMA=0.8 PHI=0.6
VC 1 2
E1 4 0 1 2 1.0
VSENSE 10 2 DC 0

VDS 10 0
VSS 5 0 DC -5
.DC VDS -2.0 2.0 .2 VC 3 7 1
.PRINT DC I(VSENSE)
.PROBE
.END

Still have the influence of the bulk on the threshold voltage.


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-11

Double MOSFET Differential Resistor


Cancels the bulk effect.
VC1
iD1
v1
v1
v2

R
R

i1
i2

iD2

VC2
iD3

v2

iD4

M1

i1

VSS
M2

M3

VSS

i2

M4
VC1

Fig. 4.2-12

iD1 = [(VC1-v-VT)(v1-v) - 0.5(v1-v)2]


iD2 = [(VC2-v-VT)(v1-v) - 0.5(v1-v)2]
iD4 = [(VC1-v-VT)(v2-v) - 0.5(v2-v)2]
iD3 = [(VC2-v-VT)(v2-v) - 0.5(v2-v)2]
i1 = iD1+iD3 = [(VC1-v-VT)V1-v) - 0.5(v1-v)2 + (VC2-v-VT)(v2-v) - 0.5(v2-v)2]
i2 = iD2+iD4 = [(VC2-v-VT)(v1-v) - 0.5(v1-v)2 + (VC1-v-VT)(v2-v) - 0.5(v2-v)2]
i1 - i2 = [(VC1-v-VT)(v1-v) + (VC2-v-VT)(v2-v) + (VC2-v-VT)(v1-v) + (VC1-v-VT)(v2-v)]
= [v1(VC1-VC2) + v2(VC2-VC1)] = (VC1-VC2)(v1-v2)
Differential input resistance is
v1-v2
v1-v2
1
v1,v2 min{(VC1-VT),(VC2-VT)}
Rin = i1-i2 = (VC1-VC2)(v1-v2) = (VC1-VC2) ,
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-12

Double-MOSFET, Differential Resistor Performance


SPICE Input File:

150uA

V C2 = 6V
5V

100uA

VBC =-5V
V3 =0V
VC1 =7V

I(VSENSE)

50uA

4V
3V
2V

- 50uA
-100uA
- 150uA

-3

-2

-1

V1-V2

Double MOSFET Differential Resistor Realization


M1 1 2 3 4 MNMOS1 W=3U L=3U
M2 1 5 8 4 MNMOS1 W=3U L=3U
M3 6 5 3 4 MNMOS1 W=3U L=3U
M4 6 2 8 4 MNMOS1 W=3U L=3U
VSENSE 3 8 DC 0
VC1 2 0 DC 7V
VC2 5 0
VSS 4 0 DC -5V
V12 1 6
.MODEL MNMOS1 NMOS VTO=0.75 KP=25U
+LAMBDA=0.01 GAMMA=0.8 PHI=0.6
.DC V12 -3 3 0.2 VC2 2 6 1
.PRINT DC I(VSENSE))
.PROBE
.END

Comments:
Good linearity and tunability.
Can be used as a multiplier.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 2 (5/2/04)

Page 4.2-13

Summary of Active Resistor Realizations


AC Resistance
Realization
Single MOSFET

Linearity

vBULK < Min (vS, vD)

Good

How
Controlled
VGS or
W/L
VC or W/L

Parallel MOSFET

Very
Good

VC1 - VC2
or
W/L

v1, v2 < min(VC1-VT,VC2-VT)


vBULK < min(v1,v2)
Transresistance only

Double-MOSFET,
differential resistor

Poor

Restrictions

v (VC - VT)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-1

SECTION 4.3 - CURRENT SINKS AND SOURCES


Characterization of MOS Sinks and Sources
A sink/source is characterized by two quantities:
rout - a measure of the flatness of the current sink/source (its independence of
voltage)
VMIN - the min. across the sink or source for which the current is no longer constant
CMOS Current Sink:
iOUT
VMIN

VDD

iOUT
VGG

and

1
rout = di /dv =
D DS

+
vOUT
-

1+VDS
D

;;
;;
;;
0

0 VGG-VT0

VGG

Slope = 1/rout

VDD

vOUT
Fig. 4.3-1

VMIN = VDS(sat) = VGS - VT0 = VGG - VT0


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-2

Simple MOS Current Source


iOUT
VDD
VGG

Slope = 1/rout
+
iOUT

vOUT
-

;;
;;
;;
VMIN

VDD-VGG

VGG

VGG+|VT0| VDD

vOUT

Fig. 280-02

This current source only works when vOUT VGG + |VT0|

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-3

Gate-Source Voltage Components


It is important to note that the gate-source voltage consists of two parts as illustrated
below:
iD

10W/L W/L

0.1W/L

ID
Enhance
Channel
0

Provide
Current

VT

VGS

vGS
Fig. 280-03

VGS = VT0 + VON = Part to enhance the channel + Part to cause current flow
where
VON = VDS(sat) = VGS - VT0

2ID
K(W/L) for the simple current sink.
Note that VMIN can be reduced by using large values of W/L.
VMIN = VON = VDS(sat) =

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-4

Simulation of a Simple MOS Current Sink

;
;
;
;
;
;

120

iOUT (A)

100

Slope = 1/Rout

80

+
vOUT
-

VGS1 =
1.126V

40
20

iOUT

10m
1m

60

Vmin

2
3
vOUT (Volts)

Comments:
VMIN is too large - desire VMIN to approach zero, at least approach VCE(sat)
Slope too high - desire the characteristic to be flat implying very large output resistance
(KN = 110A/V2, VT = 0.7Vand = 0.04V-1)

rds = 250k

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-5

Increasing the Output Resistance of a Current Sink/Source


Principle:
In order to increase the output resistance, use negative series feedback because,
rout (with feedback) = rout(without feedback) x [1 + Loop gain]
Circuit:
How does it work?
iOUT
+
1.) Assume iout increases.
M2
+v
2.) As a result, vS increases.
GS - +
vOUT
VGG
v
3.) Since the gate is held constant at VGG, then vGS decreases.
S
R
4.) The decrease in vGS causes iOUT to decrease opposing the
Fig. 280-08
original increase
Loop Gain?
iOUT = gmvS = gmRiOUT
iOUT'
iOUT
iOUT
+

Loop
gain
=
M2
iOUT = gmR
iOUT
rout(w.fb.) = rout(w/o fb.)x [1+gmR] = rds(1+gmR)
M2'
+ vOUT
VGG

vS
-

Fig. 280-09

CMOS Analog Circuit Design

If gmR >>1, then rout(w. fb.) gmrdsR

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-6

Increasing the Output Resistance of a Simple MOS Current Sink


Small signal model for calculating the
iOUT
output resistance for the cascode
M2
+
gmvgs2
current sink:
gmbsvbs2
vOUT

iout
+
rds2
vout

VGG
Loop equation:
vs2
R
R
vg2 = vb2 = 0
vout = (iout-gm2vgs2-gmbs2vbs2)rds2
Fig. 280-10
+ ioutR
= iout(rds2+R) - gm2rds2vgs2 - gmbs2rds2vbs2
But,
vgs2 = 0 - vs2 = -ioutR and
vbs2 = 0 - vs2 = -ioutR
Therefore,
vout = iout[rds2 + R + gm2rds2R + gmbs2rds2R]
or
vout
rout = i
= rds2 + R + gm2rds2R + gmbs2rds2R gm2rds2R = 2R
( = gmrds)
out
A general principle emerges:
The output resistance of a cascode circuit R x (Common source voltage gain of the
cascoding transistor)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-7

MOS Cascode Current Sink


iout

iOUT
M2
M1

+
gm2vgs2

gmbs2vbs2

vOUT

VGG2

gm1vgs1

VGG1
-

vgs1 =vg2 = vb2 = 0

rds1

rds2

+
vs2
-

vout
Fig. 280-11

Small signal output resistance:


Noting that vgs1 = vg2 = vb2 = 0 and writing a loop equation we get,
vout = (iout - gm2vgs2 - gmbs2vbs2)rds2 + rds1iout
However,
vgs2 = 0 - vs2 = -ioutrds1 and
vbs2 = 0 - vs2 = -ioutrds1
Therefore,
vout = iout[rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2]
or
vout
rout = iout = rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2 gm2rds1rds2 = 2rds1
Comments:
1.) Same as before if R = rds1
2.) Bulk effects have little influence.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-8

;;
;;
;;
;;
;;
;;

Simulation of the Cascode CMOS Current Sink


120

Example
Use the model parameters
KN=110A/V2, VT = 0.7 and N =
0.04V-1 to calculate (a) the smallsignal output resistance for the simple
current sink if IOUT = 100A and (b)
the small-signal output resistance for
the cascode current sink with IOUT =
100A. Assume that all W/L values
are 1.

Slope = 1/Rout

iOUT (A)

100

80
60

All W/Ls are iOUT


10m/1m +
VGG2 =
1.552V

vOUT

40
20

VGG1 =
1.126V

Vmin

2
3
vOUT (Volts)

5
Fig. 280-12

Solution
(a) Using = 0.04 V-1 and IOUT = 100A gives rds1 = 250k = rds2. (b) Ignoring the
bulk effect, we find that gm1 = gm2 = 469S which gives rout = (250k)(469S)(250k)
= 29.32M.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-9

Gate-Source Matching Principle


iD1
A. If the gate-source voltages of two or more transistors
are equal and the transistors are matched and operating W1 M1
in the saturation region, then the currents are related by L1
+
the W/L ratios of the individual transistors. The gatevGS1
source voltages may be directly connected or implied.
KW1
2KiD1
iD1 = 2L1 (vGS1-VT1)2 (vGS1-VT1)2 = (W 1/L1)
KW2
2KiD2
iD2 = 2L (vGS2-VT2)2 (vGS2-VT2)2 = (W /L )
2
2 2
W 2
W 1
W 1 /L 1
If vGS1 = vGS2, then L2 iD1 = L1 iD2 or
iD1 = W 2/L2 iD2

B. If the drain currents of two or more transistors are equal and the transistors are matched and operating in the saturation region, then the gatesource voltages are related by the W/L ratios (ignoring bulk effects).
If iD1 = iD2, then vGS1 = VT1 +

W 2/L2
W 1/L1 (vGS2 - VT2)

M2
+
vGS2

iD2
W2
L2

Fig. 290-02

iD1
+
vGS1

W1
L1
-

M2
+
vGS2

iD2
W2
L2

Fig. 290-03

or
if W2/L2 = W1/L1, then vGS1 = vGS2
CMOS Analog Circuit Design

(Note: VDS1must equal VDS2 for ideal results)


P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-10

Practical Cascode Current Sink Implementation


Does not require any batteries and uses the gate-source matching principle.
VDD
IREF

iOUT
2VT+2VON
M2

M4

iOUT
+
+
vDS2

+
+
VT+VON VT+VON vOUT
+
M3
VT+VON
+
VT+VON
M1
0

vOUT
Fig. 4.3-10

VT+2VON

However, VMIN is now equal to VT +VON + vDS2(min) = VT + VON + VON = VT + 2VON


Assuming that IOUT = 100A and W2/L2 = W1/L1 = 10 gives VON = 0.426V.
Thus VMIN = 0.7V + 20.426V = 1.55V (this is way too much)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-11

High-Swing Cascode Current Sink


VDD

Since
2ID
VON =
K(W/L) ,
then if L/W is
quadrupled, then
VON is doubled.
VMIN = 2VON.

IREF

VDD

IREF

iOUT

M2 +
1/1
VON
+
+
VT+VON VT+2VON M3
M1 +
1/1
VON
+
VT+VON 1/1 -

M4
1/4

iOUT
VMIN

+
vOUT
0

2VON

vOUT
Fig. 290-04

Example
Use the cascode current sink configuration above to design a current sink of 100A
and a VMIN = 1V. Assume the device parameters of Table 3.1-2.
Solution
With VMIN = 1V, choose VON = 0.5V. Assuming M1 and M2 are identical gives
2IOUT
2100x10-6
W
L = KVON2 = 110x10-6x0.25 = 7.27
CMOS Analog Circuit Design

W 1 W2 W3
W4
=
=
=
7.27
and
L1 L2 L3
L4 = 1.82
P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-12

Improved High-Swing Cascode Current Sink


Because the drain-source voltages of
VDD
the matching transistors, M1 and M3
are not equal, iOUT IREF.
IREF

VDD
IREF

iOUT

+
M5
VT
1/1
-

M2 +
1/1
VON
1/4
+
+
VT+VON + M3
M1 +
VT+2VON
VON
VON
+
V
+V
T
ON
1/1
1/1
M4

To circumvent this problem the cascode


current sink shown is utilized:
Note that the drain-source voltage of
M1 and M3 are identical causing iOUT
to be a replication of IREF.

+
vOUT

-Fig. 290-05

Design Procedure
1.) Since VMIN = 2VON = 2VDS(sat), let VON = 0.5VMIN.
W 1 W 2 W 3 W 5 2IREF
8IREF
2IREF

=
=
=
=
=
2.) VON =
K(W/L)
L1 L2 L3 L5 KV 2 KV
ON
MIN2
W4
2IREF
2IREF
IREF
3.) L4 =
=
=
K(VGS4-VT)2 K(2VON)2 2KVON2
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-13

Signal Flow in Transistors


The last example brings up an interesting and important point. This point is illustrated
by the following question, How does IREF flow into the M3-M5 combination of
transistors since there is no path to the gate of M5?
Consider how signals flow in transistors:
Output Only
C
+

Output Only
D
+
Input
G
Only

Input
Only B

+
+

+
S

+
+
+

Fig. 4.3-12B

Answer to the above question:


As VDD increases (i.e. the circuit begins to operate),
IREF cannot flow into the drain of M5, so it flows through
the path indicated by the arrow to the gate of M3. It
charges the stray capacitance and causes the gate-source
voltage of M3 to increase to the exact value necessary to
cause IREF to flow through the M3-M5 combination.
CMOS Analog Circuit Design

VDD

+
E
IREF

M5
M3

VT +2VON

+
VGS3
Fig. 4.3-12A
P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-14

Example 4.3-1 - Design of a Minimum VMIN Current Sink


Assume IREF = 100A and design a cascode current sink with a VMIN = 0.3V using the
following parameters: VTO=0.7, KP=110U, LAMBDA=0.04, GAMMA=0.4, PHI=0.7
Solution
From the previous equations, we get
W 1 W2 W3 W5
8IREF
8100
=
=
=
=
=
2
L1 L2 L3 L5 KVMIN
110(0.3V)2 = 80.8 and
IREF
W4
100
=
L4 2KVON 2 = 21100.152 = 20.2
120
Simulation Results:
100

iOUT(A)

Low Vmin Cascade Current Sink - Method No. 2


M1 5 1 0 0 MNMOS W=81U L=1U
M2 2 3 5 5 MNMOS W=81U L=1U
M3 4 1 0 0 MNMOS W=81U L=1U
M4 3 3 0 0 MNMOS W=20U L=1U
M5 1 3 4 4 MNMOS W=81U L=1U
.MODEL MNMOS NMOS VTO=0.7 KP=110U
+LAMBDA=0.04 GAMMA=0.4 PHI=0.7
VDD 6 0 DC 5V
IIN1 6 1 DC 100U
IIN2 6 3 DC 100U
VOUT 2 0 DC 5.0
.OP
.DC VOUT 5 0 0.05
.PRINT DC ID(M2)
.END

80
60
40
20
0

VMIN
0

3
vOUT(V)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-15

Self-Biased Cascode Current Sink


The VT + 2VON bias voltage is developed through a series
resistor.

VDD
IREF

Design procedure:
Same as the previous except
VON VMIN
R = IREF = 2IREF
For the previous example,
0.3V
R = 2100A = 1.5k

5
Fig. 290-06

VT+2VON

+
VON R
- VT+VON
iOU
+ M3
M4
VT
+ M1
VON
-

M2 +
VON
Fig. 290-0

Observation:
Note that the last several slides have been devoted to just getting the MOS cascode
current sink/source to have the same minimum voltage as the BJT!

T.L. Brooks and A.L. Westwick, A Low-Power Differential CMOS Bandgap Reference, Proc. of IEEE Inter. Solid-State Circuits Conf., Feb.
1994, pp. 248-249.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-16

MOS Regulated Cascode Sink


VDD

iD3
M5
M7 M6

IREF
IREF

VO1

M1

Increasing vGS3
VGS3(norm)

M3
vOUT

M4

IREF

VGS3(max)

iOUT

M2
VDS3(min)

VDS3(sat)

vDS3

Fig. 290-08

Comments:
Achieves very high output resistance by increasing the loop gain due to the M4-M5
inverting amplifier.

gm4 gm3rds2gm4rds4
rds3gm3rds2gm4rds4
Loop gain = gm3rds2gds4+gds5
if
r

ds4
ds5
out
2
2

M3 maintains constant current even though it is no longer in the saturation region.


Assume an iOUT increase vS3 increase vGS4 increase
vG3 decrease Large decrease in vGS3 Large decrease in iOUT

E. Sackinger and W. Guggenbuhl, A Versatile Building Block: The CMOS Differential Difference Amplifier, IEEE J. of Solid-State Circuits, vol.
SC-22, no. 2, pp. 287-294, April 1987.
CMOS Analog Circuit Design
P.E. Allen - 2004
Chapter 4 Section 3 (5/2/04)

Page 4.3-17

Regulated Cascode Current Sink - Continued


Small signal model:
D2=
iout
S3=
G3=D4=D5
+ vgs3 - G4 gm3vgs3
+
D3 +
rds4
rds2 v
vout
gs4 r
ds3
gm4vgs4
S2 = G2= S4
Fig. 290-09

Solving for the output resistance:


iout = gm3vgs3 + gds3(vout-vgs4)
rds5
But
vgs4 = ioutrds2
and
vgs3 = vg3 - vs3 = -gm4(rds4||rds5)vgs4 - vgs4 = -rds2[1 + gm4(rds4||rds5)]iout
iout = -gm3rds2[1 + gm4(rds4||rds5)]iout + gds3vout - gds3rds2iout
vout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]iout
vout
rout = iout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]
rds3gm3rds2gm4(rds4||rds5)
If IREF = 100A, all W/Ls are 10m/1m we get rds = 0.25M and gm = 469S which
gives
rout (0.25M)(469S)(0.25M)(469S)(0.125M) = 1.72G
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-18

Regulated Cascode Current Sink - Continued


VMIN:
Without the use of the VO1 battery shown, VMIN is pretty bad. It is,
VMIN = VGS4 + VDS3(sat) = VT + 2VON
Minimizing VMIN:
If VO1 = VT , then VMIN = 2VON. This is accomplished by the following circuit:
VDD

IREF
+IB

VDD

VDD

iOUT
ID4A

IB

M4A M4B
+ +
VGS4AVGS4B
M1

M3 +
+
VDS2
IB

vOUT

IREF+IB
M2 +
VDS2
-

If VGS4A - VGS4B = VDS2(sat) = VON,


then VMIN = 2VON

2ID4
KN(W4A/L4A) -

2IB
KN(W4B/L4B) =

2IB+2IRE
KN(W2/L

or

ID4
IB
IB+IREF
W 4A/L4A W 4B/L4B =
W 2/L2
A number of solutions exist. For example, let IB = IREF. This gives ID4A = 5.824IREF
assuming all W/L ratios are identical.
Fig. 290-10

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-19

Example 4.3-4 - Design of a Minimum VMIN Regulated Cascode Current Sink


Design a regulated cascode current sink for 100A and minimum voltage of VMIN = 0.3V.
Solution
Let the W/L ratios of M1 through M5 be equal and let IB = 10A. Therefore,
2100A
2110A
+
VMIN = 0.3V = VON3 + VON2 =
110A/V2(W/L)
110A/V2(W/L)
2100A

=
110A/V2(W/L) 1 + 1.1
+5V
+5V
+5V
Therefore,
2100A
110A 186A
10A iOUT
(2.049)
0.3V =
110A/V2(W/L)
+
M3
W 2100A2.0492
85/1
L = 110A/V20.32 = 84.8 85.
M4A M4B
85/1
85/1
With IB = 10A, then ID4A =

10A

10 + 110 = 186A
M1
85/1

vOUT

M2 110A
85/1
Fig. 290-11

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Page 4.3-20

Comparison of the MOS Cascode Current Sink and Regulated Cascode Current
Sink
Close examination in the knee area reveals interesting differences.
Simulation results:
110
105

MOS Cascode

iOUT (A)

100

BJT Cascode

Regulated
MOS
Cascode

95
90
85
80

0.1

0.2
0.3
vOUT (V)

0.4

0.5
Fig. 290-12

Comments:
The regulated cascode current is smaller than the cascode current because the drainsource voltages of M1 and M2 are not equal.
The regulated cascode current sink has a smaller VMIN due to the fact that M3 can
have a drain-source voltage smaller than VDS(sat).
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 3 (5/2/04)

Summary of Current Sinks and Sources


Current Sink/Source
Simple MOS Current Sink
Simple BJT Current Sink

Page 4.3-21

rOUT
1
rds = D
VA
ro = C
gm2rds2rds1
Fro
gm2rds2rds1

VMIN
VDS(sat) =
VON
VCE(sat)
0.2V
VT + 2VON
2VCE(sat)
2VON

Cascode MOS
Cascode BJT
Minimum VMIN Cascode Current
Sink
Regulated Cascode Current Sink* rds3gm3rds2gm4(rds4||rds5) VT +VON
Minimum VMIN Regulated
VON
rds3gm3rds2gm4(rds4||rds5)
Cascode Current Sink*
* Unfortunately, the regulated cascode current sink has a dominant pole in the feedback
loop which can cause a pole-zero doublet which leads to a combination of fast and slow
time constants. For this reason, the regulated cascode circuit should only be used in
biasing applications unless the impact of this dynamic is understood.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-1

SECTION 4.4 - CURRENT MIRRORS


Characterization of Current Mirrors
A current mirror is basically nothing more than a current amplifier. The ideal
characteristics of a current amplifier are:
Output current linearly related to the input current, iout = Aiiin
Input resistance is zero
Output resistance is infinity
Also, the characteristic VMIN applies not only to the output but also the input.
VMIN(in) is the range of vin over which the input resistance is not small
VMIN(out) is the range of vout over which the output resistance is not large
Graphically:
iout

iin
iin
+
vin
-

iout
Current
Mirror

iout
Slope = 1/Rout

Slope
= 1/Rin

vout
-

Ai
1

VMIN (in)

iin

vin

Input Characteristics Transfer Characteristics

VMIN (out)

vout

Output Characteristics
Fig. 300-01

Therefore, Rout, Rin, VMIN(out), VMIN(in), and Ai will characterize the current mirror.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-2

Simple MOS Current Mirror


iI

iO
+

vDS1
-

M2

M1
+
vGS
-

+
vDS2
Fig. 300-02

Assume that vDS2 > vGS - VT2, then


iO L1W 2VGS-VT221 + vDS2 K2
iI = W 1L2VGS-VT1 1 + vDS1 K1
If the transistors are matched, then K1 = K2 and VT1 = VT2 to give,
iO L1W 21 + vDS2
iI = W 1L21 + vDS1
If vDS1 = vDS2, then
iO L1W 2
iI = W 1L2
Therefore the sources of error are 1.) vDS1 vDS2 and 2.) M1 and M2 are not matched.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-3

Influence of the Channel Modulation Parameter,


If the transistors are matched and the W/L ratios are equal, then
iO 1 + vDS2
iI = 1 + vDS1
if the channel modulation parameter is the same for both transistors (L1 = L2).
Ratio error (%) versus drain voltage difference:

Measure VDS1,VDS2, iI and iO and


solve the above equation for the channel
modulation parameter, .

1 + vDS2
Ratio Error

1 + vDS1

Note that one could use this effect to


measure .

1 100 %

8.0
7.0

0.02

0.015

0.01

Ratio Error vDS2 - vDS1 (volts)

6.0
5.0
4.0
3.0
2.0
1.0

vDS1 = 2.0 volt

0.0
0.0

Fig. 300-03
CMOS Analog Circuit Design

1.0

2.0
3.0
vDS2 - vDS1 (volts)

4.0

5.0

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-4

Influence of Mismatched Transistors


Assume that vDS1 = vDS2 and that K1 K2 and VT1 VT2. Therefore we have
iO K2(vGS - VT2)2
iI = K (v - V )2
1

GS

T1

How do you analyze the mismatch? Use plus and minus worst case approach. Define
K = K2-K1 and K = 0.5(K2+K1)
K1= K-0.5K and K2= K+0.5K
VT = VT2-VT1 and VT = 0.5(VT1+VT2) VT1 =VT -0.5VT and VT2=VT+0.5VT
Substituting these terms into the above equation gives,
VT 2

K
1 +
1
2
2K 2(vGS-VT)

iO (K+0.5K)(vGS - VT - 0.5VT )
iI = (K-0.5K)(v - V + 0.5V )2 = K
VT 2
GS
T
T
1 1+
2(vGS-VT)
2K

Assuming that the terms added to or subtracted from 1 are smaller than unity gives
VT 2
VT 2
iO
2 VT
K
K
K
1 +
1 +
1
1

1
+
2K
2K 2(vGS-VT) 2(vGS-VT)
K (vGS-VT)
iI
Assume K/K = 5% and VT/(vGS-VT) = 10%.

iO/iI 1 0.05 (-0.20) = 1 (0.25) 15% error if tolerances are correlated.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-5

Illustration of the Offset Voltage Error Influence


Assume that VT1 = 0.7V and KW/L = 110A/V2.
iI = 1A

i
Ratio Error O 1 100 %

ii

16.0
14.0
12.0
10.0

iI = 3A

8.0

iI = 5A

6.0
iI = 10A
4.0
2.0

iI = 100A

0.0
0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

10

9.0

Fig. 300-4

VT (mV)

Key: Make the part of VGS causing the current to flow, VON, more significant than VT.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-6

Influence of Error in Aspect Ratio of the Transistors


Example 1 - Aspect Ratio Errors in Current Mirrors
Figure 4.4-4 shows the layout of a one-to-four current amplifier. Assume that the lengths
are identical (L1 = L2) and find the ratio error if W1 = 5 0.1 m. The actual widths of the
two transistors are
W1 = 5 0.1 m and W2 = 20 0.1 m
iI
iO

iI

;;;;;;;;;;
M2

GND

iO

M1

VDS1
-

M1

M2
+
VGS

+
VDS2
-

Fig. 300-5

Solution
We note that the tolerance is not multiplied by the nominal gain factor of 4. The ratio of
W2 to W1 and consequently the gain of the current amplifier is
iO W 2 20 0.1 1 (0.1/20)
0.1 0.1
0.1 0.4

4 1
1
4 1
=
=
=
4
iI W 1 5 0.1
20
5
20 - 20 = 4 - (0.03)
1 (0.1/5)

where we have assumed that the variations would both have the same sign (correlated). It
is seen that this ratio error is 0.75% of the desired current ratio or gain.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-7

Influence of Error in Aspect Ratio of the Transistors-Continued


Example 2 - Reduction of the Aspect Ratio Errors in Current Mirrors
Use the layout technique illustrated in Fig. 4.4-5 and calculate the ratio error of a current
amplifier having the specifications of the previous example.
Solutions
The actual widths of M1 and M2 are
W1 = 5 0.1 m and W2 = 4(5 0.1) m
The ratio of W2 to W1 and consequently the current gain is given below and is for all
practical purposes independent of layout error.
iO 4(5 0.1)
iI = 5 0.1 = 4

;;
;;

;;
;
;;
;;
;;
;
;;
;;
;;
;
;;
;;
;;;;;; ;
iI

M2a

M2b

M1

iO

M2c

iI

M2d

GND

CMOS Analog Circuit Design

iO

M1

M2

GND

Fig. 300-6

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-8

Summary of the Simple MOS Current Mirror/Amplifier


Minimum input voltage is VMIN(in) = VT+VON
Okay, but could be reduced to VON.
Principle:
M5 M6 M7
Ib
M3 M4

Ib

iI
iI

VT

+ M1
VON
-

iO

+
VT+VON
-

M2

VDD

Ib
iO

VT

M1
VON
+
- VT+VON
-

M2
Ib
Fig. 300-7

Will deal with later in low voltage op amps.


Minimum output voltage is VMIN(out) = VON
1
Output resistance is Rout = ID
1
Input resistance is Rin gm
Current gain accuracy is poor because vDS1 vDS2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-9

MOS Cascode Current Mirror


Improving the output resistance:
iI

+
gm3v3

iO

M3

M4

M1

S3=G2 -

vin

iin

gm1v1
-

M2

D3=G3=G4
+
rds3 v3

D4
+
rds4

gm4vgs4

D1=G1 +
rds1 v1
gm2vgs2
S1
-

S4

vout

iout

D2
rds2
-

S2

Fig. 310-018

Rout:
vout = rds4(iout-gm4vgs4) + rds2(iout-gm2vgs2)
vgs4 = -vs4 = -ioutrds2 and
But, iin = 0 so that v1 = v3 = 0
vout = iout[rds4 + rds2 + gm4rds2rds4] rds2gm4rds4
Rin:
1
1
1
1
2
Rin = g ||rds3 + g ||rds1 g + g g
m3
m1
m1
m3
m
VMIN(out) = VT + 2VON
VMIN(in) = 2(VT +VON)
Current gain match: Excellent since vDS1 = vDS2
CMOS Analog Circuit Design

vgs2 = 0

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-10

Large Output Swing Cascode Current Mirror


II
ii

IREF
M4
1/4

VDD

VDD

VDD

IO

1/1

M5

D5=G3

M2

+
1/1

M3
1/1

io
gm5vgs5
iin

M1
1/1

rds5

vin
gm3vgs3
= gm3vin
-

D3=S5 +
rds3 vs5
S3=G5 Fig. 310-02

Rout gm2rds2rds1
Rin = ?vin = rds5(iin-gm5vgs5)+vs5 = rds5(iin +gm5vs5)+vs5 = rds5iin+(1+gm5rds5)vs5
But, vs5 = rds3(iin - gm3vin)
vin = rds5iin + (1+gm5rds5)rds3iin - gm3rds3(1+gm5rds5)vin
vin rds5 + rds3 + rds3gm5rds5 1
Rin = iin = gm3rds3(1+gm5rds5) gm3
VMIN(out) = 2VON
VMIN(in) = VT + VON
Current gain is excellent because vDS1 = vDS3.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-11

Self-Biased Cascode Current Mirror


VDD

I1

iin

VDD

I2

iout
iin

+
R

gm3vgs3

Rin = ?
+
+
M4
M3
vin = iinR + rds3(iin-gm3vgs3)
rds3
vin
+
vin
v2
M2
M1
v1
gm1vgs1
rds1
+ rds1(iin-gm1vgs1)
But,
vgs1 = vin-iinR
Self-biased, cascode current mirror
Small-signal model to calculate Rin.
Fig. 310-03
and
vgs3 = vin-rds1(iin-gm1vgs1) = vin-rds1iin+gm1rds1(vin-iinR)
vin = iinR+rds3iin-gm3rds3[vin-rds1iin+gm1rds1(vin-iinR)]+rds1[iin-gm1(vin+iinR)]
vin[1+gm3rds3+gm1rds1gm3rds3+gm1rds1]
= iin[R+rds1+rds3+gm3rds3rds1+ gm1rds1gm3rds3R]
R + rds1 + rds3 + gm3rds3rds1 + gm1rds1gm3rds3R 1
Rin =
g
+R
1 + gm3rds3 + gm1rds1gm3rds3 + gm1rds1
m1
Rout gm4rds4rds2
VMIN(in) = VT + 2VON VMIN(out) = 2VON Current gain matching is excellent
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-12

Wilson MOS Current Mirror


iout
iI

iO
M3

+
gm3vgs3
iin

M1

M2

+ vgs3

+
vin gm1vgs1

rds1

gm2vgs2

rds3
vout

+
rds2

vgs2=vgs1
-

Fig. 310-09

Uses negative series feedback to achieve higher output resistance.


vout = rds2(iout - gm3vgs3) + vgs2
Rout = ? (iin=0)
rds2iout
iout
vgs2 = g +g = 1+g r
and vgs3 = -gm1rds1vgs2 - vgs2= -(1+gm1rds1)vgs2
m2 ds2
m2 ds2

1+gm3rds2+gm1rds1gm3rds3

vout = rds2iout + gm3rds2(1+gm1rds1)vgs2 = iout rds3+rds2


1 + gm2rds2

1+gm3rds2+gm1rds1gm3rds3
gm1rds1gm3rds3

Rout = rds3+rds2

1 + gm2rds2
gm2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-13

Wilson Current Mirror - Continued


Rin = ? (vout = 0)
gm1gm3vgs3
gm1gm3vgs3
iin gm1vgs1 = g +g +g

gm2
m2 ds2 ds3
gm1gm3vgs3
vgs3 = vin - vgs1= vin vgs3 =
gm2

vin
gm1gm3
1 + gm2

gm1gm3 vin
gm2 +gm3
iin gm2 +gm3
Rin = g g
m1 m3
VMIN(in) = 2(VT+VON)
VMIN(out) = VT + 2VON
Current gain matching - poor, vDS1 vDS2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-14

Evolution of the Regulated Cascode Current Mirror from the Wilson Current
Mirror
iI

iO
M3

iI

iO
M3

M1
M1
M2
M2

Wilson Current Mirror Redrawn

VBias2

Regulated Cascode Current Sink


Fig. 310-10

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-15

MOS Regulated Cascode Current Mirror

I
ii I

VDD
IBias

VDD

VDD
IO

io
M3

M1
M2

M4

FIG. 310-11

Rout gm2rds3
1
Rin
gm4
VMIN(out) = VT+2VON (Can be reduced to 2VON)
(Can be reduced to VON)
VMIN(in) = VT+VON
Current gain matching - good as long as vDS4 = vDS2
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 4 (5/2/04)

Page 4.4-16

SUMMARY
Summary of MOS Current Mirrors
Current
Mirror

Accuracy

Output
Resistance

Input
Resistance

Simple

Poor

rds

Cascode

Excellent

gmrds2

Wide Output
Swing
Cascode
Self-biased
Cascode
Wilson

Excellent

Regulated
Cascode
CMOS Analog Circuit Design

Minimum
Input
Voltage
VT+VON

VT+2VON

2(VT+VON)

gmrds2

1
gm
2
gm
1
gm

Minimum
Output
Voltage
VON

2VON

VT+VON

Excellent

gmrds2

1
R + gm

2VON

VT+2VON

Poor

gmrds2

2
gm

2(VT+VON) VT+2VON

GoodExcellent

gm2rds3

1
gm

VT+2VON
(min. is
2VON)

VT+VON
(min. is
VON)
P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-1

SECTION 4.5 - CURRENT AND VOLTAGE REFERENCES


Characteristics of a Voltage or Current Reference
What is a Voltage or Current Reference?
A voltage or current reference is an independent voltage or current source that has a
high degree of precision and stability.
Requirements of a Reference Circuit:
Should be independent of power supply
Should be independent of temperature
Should be independent of processing variations
Should be independent of noise and other interference
Reference
Nominal
Value

Noise

Temperature
Powe

r Sup

ply

Fig. 4.5-1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-2

REFERENCES WITH POWER SUPPLY INDEPENDENCE


Power Supply Independence
How do you characterize power supply independence?
Use the concept of:
IREF IREF/IREF VDD IREF
S VDD = VDD/VDD = IREF VDD
Application of sensitivity to determining power supply dependence:
IREF IREF VDD
IREF = S VDD VDD
Thus, the fractional change in the reference voltage is equal to the sensitivity times the
fractional change in the power supply voltage.
For example, if the sensitivity is 1, then a 10% change in VDD will cause a 10% change in
IREF.
IREF

Ideally, we want SV

DD

CMOS Analog Circuit Design

to be zero for power supply independence.

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-3

Simple Current Reference


VDD

VCC

IIN

IIN

IOUT

IC1

IOUT

ID1

IB1 IB2

Q1

Q2

M1

M2
Fig. 360-02

IOUT

VCC-VBE 1

R
1+ 2
F

IOUT

IREF

VDD-VGS
=
R

VDD -

2IIN
1 - V T
R

IREF

S VCC = 1

S VDD = 1

Temperature and process dependence?


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-4

MOS Widlar Current Reference


Operation:
VGS1 VGS2 IOUTR2 = 0
IOUTR2 + VON2 VON1 = 0
Assuming strong inversion and 0,
2IOUT
IOUTR2 + K'(W2/L2) VON1 = 0
Solving for IOUT gives,
2
- K'(W2/L2) +
IOUT =

2
K'(W2/L2) + 4R2VON1
2R2

2IIN
K'(W1/L1)
Differentiating IOUT with respect to VDD gives,
dIOUT
dVON1
1
1
=
2 IOUT dVDD
2/(K' W2/L2)+ 4R2VON1 dVDD ,

where

VDD

IIN

R1

ID1
M1

IOUT
M2
R2
Fig. 360-04

VON1 =

IREF

IOUT

S VDD =S VDD

CMOS Analog Circuit Design

dVON1 VON1 dIIN


dVDD = 2IIN dVDD

IIN
IIN
IIN
VON1
VON1
= V
S 4VON12 SVDD = 0.5SVDD
ON22+4 IOUTR2VON1 VDD
P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-5

Example 4.5-1
For the MOS Widlar current reference, find IOUT if IIN = 100A, R2 = 4k, K =
200A/V2, and W2/L2 = W1/L1 = 25. Assume the temperature is 27C and that n = 1.5.
Find the sensitivity of IOUT with respect to VDD.
Solution
2IIN
2100
VON1 =
=
20025 = 0.2V
K'(W1/L1)
2
20025 + 4(0.004)0.2
IOUT =
A = 5 A IOUT = 25A
20.004
Note that VON2 = VON1 - IOUTR2 = 0.2-(25)(0.004) = 0.1V > 2nVt = 78mV so both
transistors are in strong inversion.
For the sensitivity calculations, assume that VDD >> VGS1. Therefore IIN VDD/R1.
-

2
20025 +

IIN
VON1
VON1
S VDD = 4VON22 SVDD 4VON22 = 0.5
Therefore, a 10% variation in VDD causes a 5% variation in IOUT.
IREF

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-6

MOS Peaking Current Reference


Strong Inversion Operation:
VGS1 IINR VGS2 = 0
VON2 = VON1 IINR
K'(W2/L2)
VON22
IOUT =
2
K'(W2/L2)
=
(VON1 IINR)2
2
where

IIN

M2
Fig. 360-7

Transfer Characteristics:

2IIN
K'(W1/L1)
Weak Inversion Operation:

IIN
VGS2 VT nVt ln (W1/L1)IT IINR

If the transistors are identical and VDS2 > 3VT,


VGS2 VT
-IINR
W1

IOUT = L1 IT exp nVt IIN exp nVt

CMOS Analog Circuit Design

IOUT

M1

VON1 =

VDD

Circuit:

1.6
1.4

Weak Inversion

1.2
1.0
IOUT(A)
0.8
0.6
0.4
Strong Inversion

0.2
0

6
IIN(A)

10
Fig. 360-8

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-7

Threshold Referenced Current Reference


Circuit:

VDD

IIN

IOUT

R1

Operation:
2IIN
K'(W1/L1)
R2

VGS1 VT +
IOUT = R2 =
VT
R2 if VT > VON1
The sensitivity of IOUT with respect to VDD is
IOUT

S VDD

V ON1
= IOUTR2

IIN

VON1

M1
R2

IIN

Fig. 360-10

SVDD = 2VGS1 SVDD


IIN

For example, if VT = 1V, VON1 = 0.1V and SV

DD

IOUT

S VDD

M2

ID1

1, then

0.1
= 21.1 = 0.045

Therefore, if VDD changes by 10%, IREF or IOUT changes by 0.45%.


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-8

SIMPLE BIAS/REFERENCE CIRCUITS


Voltage References using Voltage Division
VDD

VDD

R1

M2
+

+
R2

M1 V

VREF

Resistor voltage divider.

R2
VREF = R +R VDD
1 2
VREF

S VDD =1

REF

Active device voltage divider.

VREF =

VTN + (P/N) (VDD-|VTP|)


1 + (P/N)

VREF VDD (P/N)


VDD (P/N)
S VDD =VREF 1+ ( / ) = V + ( / ) (V -|V |)
P N
TN
P N
DD TP

VDD (P/N)
VTN + (P/N) (VDD-|VTP|)

Assume N = P and VTN = |VTP|


CMOS Analog Circuit Design

Fig. 370-01

VREF

S VDD

=1

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-9

References with Sensitivity Less than One


In order to get sensitivities less than one, the upper and lower circuits must be different
with the lower circuit less dependent on VDD.
In otherwords, the upper circuit should act like a current source and the lower circuit like
a voltage source.
Principle:

VDD
IBias

VREF
Fig. 370-02

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-10

MOSFET-Resistance Voltage References


VDD

VDD

R
R

R1

vout

VREF

VREF
-

R2

Fig. 370-03

VREF = VGS = VT +

2(VDD-VREF)
R

1
or VREF = VT - R +

2(VDD-VT)
1
+
R
(R)2

VREF

S VDD

VDD
= 1 + (VREF-VT)R VREF

This circuit allows VREF to be larger.


If the current in R1 (and R2) is small
compared to the current flowing
through the transistor, then
R1 + R2
VREF R2 VGS

Assume that VDD = 5V, W/L = 2 and R =


100k,
Thus, VREF 1.281V and
CMOS Analog Circuit Design

VDD

SVREF = 0.283
P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-11

Bipolar-Resistance Voltage References


VCC

VCC

R
R
+

R1

VREF

VREF

vout

R2

Fig. 370-04

kT

VREF = VEB = q ln Is

VCC VEB VCC
R
R
kT VCC
VREF q ln RIs

VREF
1
1
SVCC = ln[VCC/(RIs)] = ln(I/Is)
If VCC=5V, R = 4.3k and Is = 1fA,
then VREF = 0.719V.
I=

VREF

Also, S V

CC

If the current in R1 (and R2) is small


compared to the current flowing
through the transistor, then
R1 + R2
VREF R2 VEB

= 0.0362

CMOS Analog Circuit Design


Chapter 4 Section 5 (5/2/04)

P.E. Allen - 2004


Page 4.5-12

Example 1 - Design of a Higher-Voltage Bipolar Voltage Reference


Use the circuit on the previous slide to design a voltage reference having VREF = 2.5V
when V CC = 5V. Assume Is = 1fA and F = 100. Evaluate the sensitivity of VREF with
respect to VCC.
Solution
Choose I (the current flowing through R) to be 100A.
VCC-VREF 2.5V
Therefore R = 100A = 100A = 25k.
Choose I1(the current flowing through R1) to be 50A. Therefore the current flowing in
50A
the emitter is 50A. The value of VEB = Vt ln 1fA = 0.638V.
0.638V
R1 = 50A = 12.76k
With 50A in the emitter, the base current is approximately 5A.
Therefore, the current through R2 is 55A.
2.5V-0.638V
= 33.85k.
Since VREF = IR2R2 + 0.638V = 2.5V, we get R2 = 55A

The sensitivity of VREF with respect to VCC is


VREF

S VCC

R1+ R2 VEB 12.76k+33.85k 1


= R1 SV =
ln(I /I ) = 3.652(0.0406) = 0.148
12.76k
Q s

CC

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-13

Breakdown Diode Voltage References


If the power supply voltage is high enough, i.e. VDD 10V, the breakdown diode can be
used as a voltage reference.
i

VDD
Temperature coefficient of VBV (mV/C)

R
i

VDD

IQ

VBV

5
4
3
2
1

-1

10

VBV

-2
-3

VDD

Variation of the temperature coefficient of the breakdown diode as a


function of the breakdown voltage, BV.

V-I characteristics of a breakdown diode.

Fig. 370-05

VREF = VBV
VREF

SVDD

VREF VDD
vref VDD
rZ VDD


= V V
=
DD
REF vdd VBV rZ + R VBV

where rz is the small-signal impedance of the breakdown diode at IQ (30 to 100).


Typical sensitivities are 0.02 to 0.05.
Note that the temperature dependence could be zero if VB was a variable.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-14

BOOTSTRAPPED BIAS/REFERENCE CIRCUITS


Bootstrapped Current Source
So far, none of the previous references except the base-emitter and threshold-referenced
sources have shown very good independence from power supply. Let us now examine a
technique which does achieve the desired independence.
Circuit:
VDD
RB
M7

M4
I2

I1

Startup

I5
I6
M6

M1

+
VGS1 R
-

0V

2
K'NW (V
GS1 - VT)
2L
Desired
operating
V
point
I2 = GS1
R

I1 =

M5

M3

M2
M8

IQ
Undesired
operating
point

VQ

v
Fig. 370-06

Principle:
If M3 = M4, then I1 I2. However, the M1-R loop gives VGS1 = VT1 +

2I1
KN(W1/L1)

2I1
VGS1 VT1 1

=
+
R
R
KN(W1/L1)
R
2VT1
VT1
1
1
1
The output current, Iout = I1 = I2 can be solved as Iout = R +
+
+
1R ( R)2
1R2 R
1

Solving these two equations gives I2 =

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-15

Simulation Results for the Bootstrapped Current Source


120A
ID1
100A
ID2
80A
60A
40A
20A
0

VDD

The current ID2 appears to be okay, why is


ID1 increasing?
Apparently, the channel modulation on the
current mirror M3-M4 is large.
At VDD = 5V, VSD3 = 2.83V and VSD4 =
1.09V which gives ID3 = 1.067ID4
107A
Need to cascode the upper current mirror.

Fig. 370-07

SPICE Input File:


Simple, Bootstrap Current Reference
VDD 1 0 DC 5.0
VSS 9 0 DC 0.0
M1 5 7 9 9 N W=20U L=1U
M2 3 5 7 9 N W=20U L=1U
M3 5 3 1 1 P W=25U L=1U
M4 3 3 1 1 P W=25U L=1U
M5 9 3 1 1 P W=25U L=1U
R 7 9 10KILOHM
M8 6 6 9 9 N W=1U L=1U
M7 6 6 5 9 N W=20U L=1U

RB 1 6 100KILOHM
.OP
.DC VDD 0 5 0.1
.MODEL N NMOS VTO=0.7 KP=110U
GAMMA=0.4 +PHI=0.7 LAMBDA=0.04
.MODEL P PMOS VTO=-0.7 KP=50U
GAMMA=0.57 +PHI=0.8 LAMBDA=0.05
.PRINT DC ID(M1) ID(M2) ID(M5)
.PROBE
.END

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-16

Cascoded Bootstrapped Current Source


VDD
M3

120A

M4
M5

M3C

MC4
MC5

RB
M7

80A
I1

RON

I2
M2

M8
Startup

ID2

100A

M1

+
VGS1 R
0V

I5

ID1

60A
40A
20A
0

SPICE Input File:


Cascode, Bootstrap Current Reference
VDD 1 0 DC 5.0
VSS 9 0 DC 0.0
M1 5 7 9 9 N W=20U L=1U
M2 4 5 7 9 N W=20U L=1U
M3 2 3 1 1 P W=25U L=1U
M4 8 3 1 1 P W=25U L=1U
M3C 5 4 2 1 P W=25U L=1U
MC4 3 4 8 1 P W=25U L=1U
RON 3 4 4KILOHM
M5 9 3 1 1 P W=25U L=1U
R 7 9 10KILOHM
M8 6 6 9 9 N W=1U L=1U
CMOS Analog Circuit Design

VDD

5
Fig. 370-

M7 6 6 5 9 N W=20U L=1U
RB 1 6 100KILOHM
.OP
.DC VDD 0 5 0.1
.MODEL N NMOS VTO=0.7
KP=110U GAMMA=0.4 PHI=0.7
LAMBDA=0.04
.MODEL P PMOS VTO=-0.7
KP=50U GAMMA=0.57 PHI=0.8
LAMBDA=0.05
.PRINT DC ID(M1) ID(M2) ID(M5)
.PROBE
.END
P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-17

Base-Emitter Referenced Circuit


VDD

M3

M4

M5

i2
M6 I
1
I2
M1

Desired
operating
point

I5

M2

+
VEB1
Q1

M7

i2=i1

Undesired
operating
point

Startup

i2=VTln(i1/Is)/R

VR

i1

Fig. 370-09

VEB1
Iout = I2 = R
BJT can be a MOSFET in weak inversion.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-18

Low Voltage Bootstrap MOS Circuit


The previous bootstrap circuits required at least 2 volts across the power supply before
operating.
A low-voltage bootstrap circuit:
VDD
M3
VON

I1

M4

VT
VT

VT+VON

I2
VON

M1

M2

VT+VON
R

VSS

VR
Fig. 4.5-8A

Without the batteries, VT, the minimum power supply is VT+2VON+VR.


With the batteries, VT, the minimum power supply is 2VON+VR 0.5V

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-19

Summary of Power-Supply Independent References


Reasonably good, simple references are possible
Best power supply sensitivity is approximately 0.01
(10% change in power supply causes a 0.1% change in reference)
Typical simple reference temperature dependence is 1000 ppm/C
Can obtain zero temperature coefficient over a limited range of operation
Type of Reference
Voltage division
MOSFET-R
BJT-R
Threshold
Referenced
Base-emitter
Referenced

VREF

SV
PP
1
<1
<<1
<<1
<<1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-20

REFERENCES WITH TEMPERATURE INDEPENDENCE


Characterization of Temperature Dependence
The objective is to minimize the fractional temperature coefficient defined as,
1 VREF
1 VREF
TCF = VREF T =
T S T parts per million per C or ppm/C
Temperature dependence of PN junctions:
v

i IsexpVt
(ln Is) 3
VGO
VGO
1 Is

=
=
+

-VGO

TVt
TVt
Is T
T
T
Is = KT3exp Vt

dvBE VBE - VGO


= -2mV/C at room temperature
dT
T
(VGO = 1.205 V at room temperature and is called the bandgap voltage)
Temperature dependence of MOSFET in strong inversion:
dvGS dVT
2L d iD
dT = dT + WCox dT o dv
GS - -2.3mV
-1.5
C
o = KT
dT
VT(T) = VT(To) - (T-To)

Resistors:
(1/R)(dR/dT) ppm/C
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-21

Bipolar-Resistance Voltage References


From previous work we know that,
kT VDD - VREF
VREF = q ln

RIs

VDD

R
+
VREF

However, not only is VREF a function of T, but R and Is are also


Fig. 380-1
functions of T.
dIs
dVREF k VDD-VREF kT RIs -1 dVREF VDD-VREF dR
dT = q ln RIs + q VDD-VREFRIs dT - RIs RdT + IsdT

dR
VREF
Vt
dVREF
dIs VREF-VGO
Vt
dVREF 3Vt Vt dR

= T - VDD-VREF dT - Vt RdT + IsdT =


T
VDD-VREF dT - T - R dT

VREF-VGO
dR 3Vt
V
t
dVREF
T
RdT - T VREF-VGO
dR 3Vt
dT =

V
t RdT - T
T
Vt
1 + V -V
DD
REF
3Vt
1 dVREF VREF-VGO Vt dR
TCF = V
=
VREFT VREF RdT VREFT
REF dT
If VREF = 0.6V, Vt = 0.026V, and the R is polysilicon, then at 27K the TCF is
0.6-1.205 0.0260.0015 30.026
- 0.6300 = 33110-6-65x10-6-433x10-6 =-3859ppm/C
TCF = 0.6300 0.6
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-22

MOSFET Resistor Voltage Reference


From previous results we know that
2(VDD-VREF)
VREF = VGS = VT +
R
or

1
VREF = VT - R +

2(VDD-VT)
1
+
R
(R)2

Note that VREF, VT, , and R are all functions of temperature.


It can be shown that the TCF of this reference is
dVREF
dT =

VDD VREF 1.5 1 dR

R dT
2R
T
1
1 + 2R (V V )
DD
REF

VDD

R
+
VREF
Fig. 380-02

VDD VREF 1.5 1 dR

R dT
2R
T
TCF =
1
VREF(1 + 2R (V V ))
DD
REF
+

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-23

Example 4.5-1 - Calculation of MOSFET-Resistor Voltage Reference TCF


Calculate the temperature coefficient of the MOSFET-Resistor voltage reference where
W/L=2, VDD=5V, R=100k using the parameters of Table 3.1-2. The resistor, R, is
polysilicon and has a temperature coefficient of 1500 ppm/C.
Solution
dR
First, calculate VREF . Note that R = 220 10-6 105 = 22 and RdT = 1500ppm/C
1
VREF = 0.7 22 +

2(5 0.7) 1 2
+ 22 = 1.281V
22

5 1.281 1.5

-6

1500

10
dVREF
222
300

=
= -1.189x10-3V/C
Now,
1
dT
1+
222 (5 - 1.281)
The fractional temperature coefficient is given by
1
TCF = 1.189 10-3 1.281 = 928 ppm/C
2.310-3 +

CMOS Analog Circuit Design


Chapter 4 Section 5 (5/2/04)

P.E. Allen - 2004


Page 4.5-24

Bootstrapped Current Source/Sink


Gate-source referenced source:
2VT1
VT1
1
1
1
The output current was given as, Iout = R +
+
+(
2

R
R
1R
1
1R)2
Although we could grind out the derivative of Iout with respect to T, the temperature
performance of this circuit is not that good to spend the time to do so. Therefore, let us
assume that VGS1 VT1 which gives
VT1
dIout 1 dVT1 1 dR
dT = R dT - R2 dT
Iout R
In the resistor is polysilicon, then
1 dIout
1 dVT1 1 dR - 1 dR -2.3x10-3
-1.5x10-3 = -4786ppm/C
TCF = Iout dT = VT1 dT - R dT = VT1 - R dT = 0.7
Base-emitter referenced source:
VBE1
The output current was given as, Iout = I2 = R
1 dVBE1 1 dR
The TCF = V
- R dT
BE1 dT
1
If VBE1 = 0.6V and R is poly, then the TCF = 0.6 (-2x10-3) - 1.5x10-3 = -4833ppm/C.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-25

VDD
Technique to Make gm Dependent on a Resistor
Consider the following circuit with all transistors having a
W/L = 10. This is a bootstrapped reference which creates a M3
M4
Vbias independent of VDD. The two key equations are:
I3 = I4 I1 = I2
M2D
and
M1
+
VGS1 = VGS2 + I2R
M2A
M2B M2CVBias
Solving for I2 gives:
R=5k
2I2
2I1 1
VGS1-VGS2 1 2I1
= R 1 I2 =
Fig. 4.5-11
R
2 = R 1 1 - 2
1
1
1
I2 = R 2 I2 = I1 =
=
= 18.18A

1
21R2 2110x10-61025x106
Now, Vbias can be written as
2I2
1
1
+ 0.7 = 0.1818+0.7 = 0.8818V
Vbias=VGS1= 1 +VTN = 1R+VTN =
-6
110x10 105x103
Any transistor with VGS = Vbias will have a current flow that is given by 1/2R2.
1
1
2
=

g
=
Therefore,
gm = 2I =
m
R
2R2 R
(This means that the temperature dependence of gm will be that of 1/R which can be used
to achieve temperature controlled performance.)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 5 (5/2/04)

Page 4.5-26

Summary of Reference Performance


Type of Reference
MOSFET-R
BJT-R
Breakdown Diode
Bootstrap GateSource Referenced
Bootstrap Baseemitter Referenced

VREF

S VDD

TCF

<1
>1000ppm/C
<<1
>1000ppm/C
<<1
Can be very small
Good if currents >1000ppm/C
are matched
Good if currents >1000ppm/C
are matched

Comments

BV too large
Requires startup circuit
Requires startup circuit

A MOSFET can have zero temperature dependence of iD for a certain vGS


If one is careful, very good independence of power supply can be achieved
None of the above references have really good temperature independence
Consider the following example:
A 10 bit ADC has a reference voltage of 1V. The LSB is approximately 0.001V.
Therefore, the voltage reference must be stable to within 0.1%. If a 100C change in
temperature is experienced, then the TCF must be 0.001%/C or multiplying by 104 gives a
TCF = 10ppm/C.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-1

SECTION 4.6 - BANDGAP REFERENCES


Temperature Stable References
The previous reference circuits failed to provide small values of temperature coefficient
although sufficient power supply independence was achieved.
This lecture introduces the bandgap voltage concept combined with power supply
independence to create a very stable voltage reference in regard to both temperature and
power supply variations.
Bandgap Voltage Reference Principle
The principle of the bandgap voltage reference is to balance the negative temperature
coefficient of a pn junction with the positive temperature coefficient of the thermal
voltage, Vt = kT/q.
VDD
VBE
Concept:
-2mV/C

I1

Result: References with TCFs


approaching 10 ppm/C.

T
+

-VBE Vt

+0.085mV/C
T

Vt = kT
q

VREF = VBE + KVt

CMOS Analog Circuit Design


Chapter 4 Section 6 (5/2/04)

KVt
Fig. 390-01

P.E. Allen - 2004


Page 4.6-2

Derivation of the Temperature Coefficient of the Base-Emitter Voltage


For small TCF's the dependence VBE must be known more precisely than -2mV/C.
1.) Start with the collector current density, JC:
q Dn npo
V BE

JC = W B
exp Vt

where, JC = IC/Area = collector current density


Dn = average diffusion constant for electrons
WB = base width
VBE = base-emitter voltage
Vt = kT/q
k = Boltzmann's constant (1.38x10-23J/K)
T = Absolute temperature
npo = ni2/NA = equilibrium concentration of electrons in the base
-V GO

ni2 = DT3 exp Vt = intrinsic concentration of carriers

D = temperature independent constant


VGO = bandgap voltage of silicon (1.205V)
NA = acceptor impurity concentration
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-3

Derivation of the Temperature Coefficient of the Base-Emitter Voltage - Continued


2.) Combine the above relationships into one:
q Dn
VBE - VGO
VBE - VGO
= AT exp

where, = 3
JC = N AW B DT3 exp Vt
Vt

3.) The value of JC at a reference temperature of T = T0 is


q

JC0 = AT0 exp kT0 (VBE - VGO)

while the value of JC at a general temperature, T, is


q

JC = AT exp kT (VBE - VGO)


4.) The ratio of JC/JC0 can be expressed as,
T
q V BE - V G0 V BE0 - V G0
JC

=
exp
JC0
T
T0
T0
k

or
JC
T

q
T
ln JC0 = lnT0 + kT VBE - VGO - T0 (VBE0 - VGO)
where VBE0 is the value of VBE at T = T0.
5.) Solving for VBE from the above results gives,
kT T0 kT JC

T
T
VBE(T) = VGO1 - T0 + VBE0T0 + q ln T + q lnJC0
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-4

Derivation of the Temperature Coefficient of the Base-Emitter Voltage - Continued


6.) Next, assume JC T and find VBE/T.
JC


VBE VGO T VGO VBE0 kT ln(T0/T) T0 (kT/q) kT lnJC0 k JC
+ln T T + q +q lnJC0
T = T 1-T0- T0 + T0 + q
T

7.) Assume that T = T0 which means JC = JC0. Since, VGO/T = 0,


VGO VBE0 kT ln(T0/T) kT ln(JC/JC0)
VBE |
=
+ q

T=T
0
T
T0 + T0 + q
T
T

8.) Note that,


ln(T0/T) T (T0/T) T -T0 -1
ln(JC/JC0) JC0 (JC/JC0) JC0 JC
=
=
=
and
= JC
= JC T JC0 = T

T0 T
T0 T2 T
T
T

Therefore,
VGO VBE0 k k
VBE0 - VGO
VBE |
VBE |
k

=
+
+
or
=
+
(

)
T=T
T=T
0
0
T
T0
T0
T
T0
q q
q
Typical values of and are 1 and 3.2. If VBE0 = 0.6V, then at room temperature:
VBE |
0.026
0.6-1.205
0.6-1.205-0.1092

=
=
+
(1-3.2)
= -1.826mV/C
T=T
0
T
300
300
300

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-5

Derivation of the Temperature Coefficient of the Thermal Voltage (kT/q)


1.) Consider two identical pn junctions having different current densities,
VDD

VDD

IC2

IC1

+ VBE Q1
AE1

Q2
AE2
Fig. 390-02

kT JC1
VBE = VBE1- VBE2 = q lnJC2

- Find (VBE)/T,

(VBE) Vt JC1 k JC1


= T lnJC2 = q lnJC2
T

CMOS Analog Circuit Design


Chapter 4 Section 6 (5/2/04)

P.E. Allen - 2004


Page 4.6-6

Derivation of the Gain, K, for the Bandgap Voltage Reference


1.) In order to achieve a zero temperature coefficient at T = T0, the following equation
must be satisfied:
VBE |
(VBE)
where K" is a constant that satisfies the equation.
0 = T T=T0 + K"
2.) Therefore, we get
( - )Vt0
Vt0
JC1
VBE0 - VGO
+
0 = K" T0 lnJC2 +
T0
T0
JC1
3.) Define K = K" lnJC2 , therefore
( - )Vt0
Vt0
VBE0 - VGO
+
0 = K T0 +
T0
T0
VGO - VBE0 - Vt0(-)
4.) Solving for K gives
K=
Vt0
Assuming that JC1/JC2 = AE1/AE2 = 10 and VBE0 = 0.6V gives,
1.205 - 0.6 + (2.2)(0.026)
= 25.469
K=
0.026
5.) The output voltage of the bandgap voltage reference is found as,
|
VREFT=T0 = VBE0 + KVt0 = VBE0 + VGO - VBE0 + (-)Vt0 or VREF = VGO + (-)Vt0
For the previous values, VREF = 1.205 + 0.026(2.2) = 1.262V.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-7

Variation of the Bandgap Reference Voltage with respect to Temperature


The previous derivation is only valid at a given temperature, T0. As the temperature
changes away from T0, the value of VREF/T is no longer zero.
Illustration:
VREF(V)
1.290
T0 = 400K

VREF
=0
T

1.280
VREF= 0
T0 = 300K
T

1.270
1.260
1.250
VREF
=0
T
1.240

T0 = 200K
TC

-60

-40

-20

20

40

60

80

100

120
Fig. 4.6-3

Bandgap curvature correction will be necessary for low ppm/C bandgap references.

CMOS Analog Circuit Design


Chapter 4 Section 6 (5/2/04)

P.E. Allen - 2004


Page 4.6-8

Classical Widlar Bandgap Voltage Reference


Operation:
VCC
VBE1 = VBE2 + I2R3
I
gives
Q4
VBE = VBE1 - VBE2 = I2R3
But,
I1
I2
I1Is2
+
R2
I1
R1
I2
VBE = Vt lnIs1 - Vt lnIs2 = Vt lnI2Is1
Assume VBE1 VBE3, we get
I1R1 = I2R2
Q3
VREF
Therefore,
Q1
Q2
VBE
I1Is2
R2Is2
Vt
Vt
I2 = R3 = R3 lnI2Is1 = R3 lnR1Is1
R3
Now we can express VREF as
R2Is2
R2
Fig. 390-04
VREF = I2R2 + VBE3 = R3 Vt lnR1Is1 + VBE3 = KVt + VBE
Design R1, R2, Is1, and Is2 to get the desired K.
Let K = 25 and Is2 = 10Is1 and design R1, R2, and R3. Choose R2 = 10R1 = 10k.
Therefore, ln(100) = 4.602. Therefore R2/R3 = 25/4.602 or R3 = R2/5.4287 = 1.842k.

R.J. Widlar, New Developments in IC Voltage Regulators, IEEE J. of Solid-State Circuits, Vol. SC-6, pp. 2-7, February 1971.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-9

A CMOS Bandgap Reference using PNP Lateral BJTs


Bootstrapped Voltage Reference using PNP LateralsVDD
+

R3
M3
IREF

R4

R2
VREF Q1
I1

Q2

R1

M1
VSS

I2

M2

Fig. 390-05

I2
Is2
AE2
VBE1 - VBE2
V t I1
Vt
Vt
ln
- ln
=

=
=
ln
ln
R2
R2 Is1
R2
R2 AE1
Is2
Is1
if I1 = I2 which is forced by the current mirror consisting of M1 and M2.
R1
AE2
VREF = VBE1 + I1R1 = VBE1 + R2 lnAE1 Vt = VBE1 + KVt
While an op amp could be used to make I1 = I2 it suffers from offset and noise and leads to
deterioration of the bandgap temperature performance.
VREF is with respect to VDD and therefore is susceptible to changes on VDD.

I2 =

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-10

A CMOS Bandgap Reference using Substrate PNP BJTs


Operation:
The cascode mirror (M5-M8) keeps the currents
in Q1, Q2, and Q3 identical.
Thus,
VBE1 = I2R + VBE2
or
Vt
I2 = R ln(n)
Therefore,
VREF = VBE3 + I2(kR) = VBE3 + kVtln(n)
Use k and n to design the desired value of K (n is
an integer greater than 1).

VDD
M7

M8
M9

M5

M6
M10

M3

M4
+

M1

M2

x1

xn

VSS
CMOS Analog Circuit Design

Q3

Q2

Q1

VREF

I2

I1

kR

xn

Fig. 390-06
P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Weak Inversion Bandgap Voltage Reference


Circuit:
Analysis:

Page 4.6-11

VDD
+
VR1 R1
-

For the p-channel transistors:


V BG
-V BS
-V BD
M2
M4
R2
ID = IDO(W/L) exp nVt exp Vt - exp Vt
ID1=ID2
ID3=ID4
where Vt = kT/q.
M1
M3
V BG V BS
If VBD >> Vt, then ID = IDO(W/L) exp nVt - Vt .
The various transistor currents can be expressed as:
V BG2
V BG4 V BS4
ID1 = ID2 = IDO(W2/L2) exp nVt and ID3 = ID4 = IDO(W4/L4) exp nVt - Vt
Note that VBG2 = VBG4 and VBS4 = VR1.
Therefore,
V R1
ID1
W2/L2

=
exp
ID3
W 4/L 4
Vt
where
W 1W 4L 2L 3
VR1
VR1 = Vt lnL 1L 4W 2W 3 and IR1 = R1
CMOS Analog Circuit Design
Chapter 4 Section 6 (5/2/04)

ID6

M6
+
+
VR2
VREF
Q5
Fig. 390-07

P.E. Allen - 2004


Page 4.6-12

Weak Inversion Bandgap Voltage Reference - Continued


The reference voltage can be expressed as,
VREF = R2I6 + VBE5
However,
W 1W 4L 2L 3
W 6L 3
W 6L 3 V t
I6 = L 6W 3 IR1 = L 6W 3 R1 lnL 1L 4W 2W 3 .
Substituting I6 and the previously derived expression for VBE(T) in VREF gives,
W 1W 4L 2L 3

T
T0
W6L3 R2
T
VREF = L 6W 3 R1 Vt lnL 1L 4W 2W 3 + VGO1 - T0 + VBE0 T0 + 3Vt ln T
To achieve VREF/T = 0 at T = T0, we get
VREF k R2W 6L 3 W 1W 4L 2L 3 VGO
VBE0
3k

ln
=
+
+
T
T0
T0
q
q R1 L 6W 3
L 1L 4W 2W 3
Therefore,
R 2W 6L 3 W 1 W 4 L 2 L 3 q
R1L6W3 lnL 1L 4W 2W 3 = kT0 (VGO - VBE0) - 3
Under the above constraint, VREF has an zero TCF at T = T0 and has a value of
T0
3kT
3kT
VREF = VGO + q 1 + ln T = VGO + q
Practical values of VREF/T for the weak inversion bandgap are less than 100 ppm/C.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-13

Curvature Correction Techniques:


Squared PTAT Correction:
Temperature coefficient 1-20 ppm/C
VBE loop
M. Gunaway, et. al., A CurvatureCorrected Low-Voltage Bandgap
Reference, IEEE Journal of Solid-State
Circuits, vol. 28, no. 6, pp. 667-670, June
1993.

Voltage

VBE

VPTAT

VPTAT2
VRef = VBE + VPTAT + VPTAT2
Temperature

Fig. 400-01

compensation
I. Lee et. al., Exponential Curvature-Compensated BiCMOS Bandgap
References, IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp. 1396-1403,
Nov. 1994.
Nonlinear cancellation
G.M. Meijer et. al., A New Curvature-Corrected Bandgap Reference, IEEE
Journal of Solid-State Circuits, vol. 17, no. 6, pp. 1139-1143, December 1982.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-14

VBE Loop Curvature Correction Technique


Circuit:
VDD
Operation:
VBE1-VBE2 Vt Ic1A2
INL =
= R lnA I
R3
3 1 c2
IPTAT
Vt 2IPTAT
IVBE
= R lnI +I
R3 INL
3 NL Constant
VREF
IPTAT
where
IConstant
Qn1
Qn2
Iconstant = INL + IPTAT + IVBE
R1
x1
x2
R2
Vt VBE
Fig. 400-02
INL + Rx + R2
(a quasi-temperature independent current subject to the TCF of the resistors)
where
Vt = kT/q
Ic1 and Ic2 are the collector currents of Qn1 and Qn2, respectively
Rx = a resistor used to define IPTAT
VBE

Vt 2IPTAT
VREF = R2 + R3 lnINL + Iconstant + IPTAT R1

3-Output Current Mirror (IVBE+INL)

VDD
IVBE+INL
IPTAT

VDD VDD

Temperature coefficient 3 ppm/C with a total quiescent current of 95A..


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-15

Compensation Curvature Correction Technique


Circuit:
Operation:

BT
BT
Vin
VREF = VBE + AT + (1+) R VBE + AT + R
where
I=AT
I=BT
A and B are constant
T = temperature
The temperature dependence of is
R BT
1+

VREF

(T) e-1/T (T) = Ce-1/T

Fig. 400-03

BTe1/T
C
Not good for small values of Vin.
Vin VREF + Vsat. = VGO + Vsat. = 1.4V

VREF = VBE(T) + AT +

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Nonlinear Cancellation Curvature Correction Technique


Objective: Eliminate nonlinear term from the BE.
Result: 0.5 ppm/C from -25C to 85C.
VCC
Operation: From above,
VREF = VPTAT + 4VBE(IPTAT) - 3VBE(IConstant)

Page 4.6-16

VCC
IPTAT
Q8
Q4

IConstant
V
= REF
R2
Q7

IPTAT
Note that,
IPTAT Ic T 1 = 1
Q6
Q3
0
and
Iconstant Ic T = 0,
Q2
Q5
VBE
Previously we found,
T
T
VREF
Q1
VBE
VBE(T) VGO - T0 VGO-VBE(T0) -( -)Vt lnT0

R2 VREF
VPTAT
R1
VPTAT R1
so that
T
T
VBE(IPTAT) =VGO-T VGO-VBE(T0)-(-1)Vt lnT
Conventional
Curvature Corrected
0
0
Bandgap Reference
Bandgap Reference
Fig. 400-04
and
T
T
VBE(IConstant) =VGO - T0 VGO -VBE(T0) -Vt lnT0

Combining the above relationships gives,


VREF(T) = VPTAT + VGO - (T/T0)[VGO - VBE(T0)] - [ - 4] Vt ln(T/T0)

If 4, then VREF(T) VPTAT + VGO1 - (T/T0) + VBE(T0)(T/T0)


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-17

A Practical Version of the Nonlinear Curvature Correction Technique


The last idea was good in concept but not appropriate for CMOS implementation. The
following is a possible implementation.
VDD
VDD
VDD

VDD

IPTAT

IVBE(PTAT)

IVBE(Const)

Iconst

IVBE

VDD

KIPTAT

Iconst
+
VGS(ZTC)

+
Q1

Q2
VREF
R1

R0

R2

Constant Current
Generator
040629-01

VBE(PTAT)
VBE(Const)
R
0
R1
R2
R0
T R0
T
T
T
= R1 VGO-T0VGO-VBE(T0)-(-1)Vt lnT0- R2 VGO-T0VGO-VBE(T0)-Vt lnT0

VREF = R0[IVBE(PTAT) - IVBE(Const)] = R0

R0 R0
R0
R0
R1 -1
Let R1 - R2 = 1 and R1 (-1) = R2 R2 = to cancel the nonlinear curvature term.
CMOS Analog Circuit Design
Chapter 4 Section 6 (5/2/04)

P.E. Allen - 2004


Page 4.6-18

Other Characteristics of Bandgap Voltage References


Noise
Voltage references for high-resolution ADCs are particularly sensitive to noise.
Noise sources: Op amp, resistors, switches, etc.
VCC
PSRR
+
Maximize the PSRR of the op amp.
Q1
Q2
Offset Voltages
+
Becomes a problem when op amps are used.
VREF
VR1V
R
1
VBE2 = VBE1 + VR1 + VOS
- OS
iC2AE1
iC1
iC2
VBE = VBE2 - VBE1 = VR1 + VOS = Vt lniC1AE2
+
Since iC2R3 = iC1R2 - VOS
R3
R2
iC2
R2 VOS
R2
VOS
then
iC1 = R3 - iC1R3 = R3 1 + iC1R2
Fig. 400-05
VEE
Therefore,
R2AE1

VOS
VR1 = -VOS + Vt lnR3AE21 + iC1R2
V R1
R2
VREF = VBE2 - VOS + iC1R2 = VBE2 - VOS + R1 R2 = VBE2 - VOS + R1 VR1

R2AE1
R2 R2
VOS
VREF = VBE2 - VOS1+ R1 + R1 V t ln R3AE21 - iC1R2
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-19

How do you get a Stable Reference Current from the Bandgap?


Assume that a temperature stable reference voltage is available (i.e. bandgap
reference) and use the zero TC NMOS current sink.
The problem is that VREF may not be equal to the value of VGS that gives zero TC.
VDD
1:1 Current Mirror
R1

IR1

IREF

IR2

VREF

1:1 Current Mirror

R2

+
VGS
Fig. 400-06

V
R
VGS = IR2R2 = R R = R VREF
dVGS R2 dVREF VREF dR2 R2 dR1 R2 dVREF dR2 dR1
dT = R1 dT + R1 dT - R 2 dT = R1 dT + dT - dT
1

dR
dR2
1

If the temperature coefficients of R1 and R2 are equal dT = dT , then


dVGS R2 dVREF
dT = R1 dT and VGS is proportional to the temperature dependence of VREF.
If the MOSFET is biased at the zero TC point, then the current should have the same
dependence on temperature as VREF.

REF

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-20

Practical Aspects of Temperature-Independent and Supply-Independent Biasing


A temperature-independent and supply-independent current source and its distribution:
VDD

M7

M8
M9

M5

M6
M10
Bandgap
Voltage,
R4
VBG

R3

M11

M13

M15

M17

M19

M12

M14

M16

M18

M20

M4

M3
M1

M2
IPTAT

R1
Q2

Q1

R2
Q3

IREF

To Slave
Bias Ckt.

To Slave
Bias Ckt.

Rext

xn
Fig. 400-07

Constant current:
VBG
IREF = R
where
ext
CMOS Analog Circuit Design

VT
VBG = VBE3 + IPTATR2 = VBE3 + R1 ln(n)R2
P.E. Allen - 2004

Chapter 4 Section 6 (5/2/04)

Page 4.6-21

Practical Aspects of Bias Distribution Circuits - Continued


Distribution of the current avoids change in bias voltage due to IR drop in bias lines.
Slave bias circuit:
VDD
VPBias1
From Master Bias
Ib

Ib

VPBias2

VNBias2

VNBias1
Fig. 400-08

CMOS Analog Circuit Design


Chapter 4 Section 6 (5/2/04)

P.E. Allen - 2004


Page 4.6-22

SUMMARY OF VOLTAGE AND CURRENT REFERENCES


Reasonably good, simple references are possible
Best power supply sensitivity is approximately 0.01
(10% change in power supply causes a 0.1% change in reference)
Typical simple reference temperature dependence is 1000 ppm/C
Can obtain zero temperature coefficient over a limited range of operation
Bandgap voltage references can achieve temperature dependence less than 50 ppm/C
Correction of second-order effects in the bandgap voltage reference can achieve very
stable (1 ppm/C) voltage references.
Watch out for second-order effects such as noise when using the bandgap voltage
reference in sensitive applications.

We will examine bandgap voltage references once again when we consider low
voltage circuits in Section 6 of Chapter 7.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 4 Section 7 (5/2/04)

Page 4.7-1

CHAPTER 4 - SUMMARY
This chapter covered the analysis and design of sub-blocks or subcircuits including:
- Switches
- MOS diode and floating resistor realizations
- Current sinks and sources
- Current mirrors (amplifiers)
- Current and voltage references - Bandgap reference
Subcircuits represent primitives of circuit design and do not stand alone
The current sink/source is an important subcircuit which is used for biases and ac loads
A current sink/source is characterized by
1.) The independence of the current on the voltage across it (rout)
2.) The voltage range over which the current is not independent of the voltage (VMIN )
A current mirror is characterized by
1.) The independence of the output current on the voltage across it (rout large)
2.) The output voltage range over which output current is dependent (VMIN (out))
3.) The independence of the input voltage on the input current (rin small)
4.) The range of input voltage over which the input current is independent (VMIN(in))
5.) The accuracy of the current out as a function of the current in ratio.
A voltage or current reference is independent of power supply and temperature
The bandgap reference is the best realization of a voltage reference
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Introduction (5/2/04)

Page 5.0-1

CHAPTER 5 CMOS AMPLIFIERS


Chapter Outline
5.1 Inverters
5.2 Differential Amplifiers
5.3 Cascode Amplifiers
5.4 Current Amplifiers
5.5 Output Amplifiers
5.6 High-Gain Architectures
Goal
To develop an understanding of the amplifier building blocks used in CMOS analog
circuit design.
Design Hierarchy

Functional blocks or circuits


(Perform a complex function)

Blocks or circuits
(Combination of primitives, independent)

Chapter 5

Sub-blocks or subcircuits
(A primitive, not independent)
Fig. 5.0-1
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Introduction (5/2/04)

Page 5.0-2

Illustration of Hierarchy in Analog Circuits for an Op Amp


Operational Amplifier

Biasing
Circuits

Current Current Current


Source Mirrors
Sink

Input
Differential
Amplifier

Second
Gain
Stage

Inverter
Source
Current
Coupled Pair Mirror Load

Current
Sink Load

Output
Stage

Source
Follower

Current
Sink Load
Fig. 5.0-2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Introduction (5/2/04)

Page 5.0-3

Active Load Amplifiers


What is an active load amplifier?
VCC

VDD
+
V T+
2VON

+
VT+VON
-

+
VEB +
VEB +
VEC(sat)
-

MOS Loads
IBias

BJT Loads

IBias

IBias

IBias

+
VBE +
VCE(sat)
-

V T+
2VON

+
VBE
-

- V ++V
T ON
MOS Transconductors

BJT Transconductors

Fig320-01

It is a combination of any of the above transconductors and loads to form an amplifier.


(Remember that the above are only some of the examples of transconductors and loads.)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-1

SECTION 5.1 - CMOS INVERTING AMPLIFIERS


Characterization of Amplifiers
Amplifiers will be characterized by the following properties:
Large-signal voltage transfer characteristics
Large-signal voltage swing limitations
Small-signal, frequency independent performance
- Gain
- Input resistance
- Output resistance
Small-signal, frequency response
Other properties
- Noise
- Power dissipation
- Etc.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-2

Inverters
The inverting amplifier is an amplifier which amplifies and inverts the input signal.
The inverting amplifier generally has the source on ac ground or the common-source
configuration.
Various types of inverting CMOS amplifiers:
M2

VDD

M2
M2

ID
vIN

ID

vOUT
M1

vOUT

vIN

M1

ID
vIN

vOUT

M2

VGG2

ID
vIN

M1

Active
Active
Depletion
NMOS Load PMOS Load NMOS Load
Inverter
Inverter
Inverter

M2

I
vOUT vIN D

vOUT

M1

Current
Source Load
Inverter

M1

Pushpull
Inverter
Fig. 5.1-1

We will consider:
Active PMOS Load Inverter (active load inverter)
Current Source Load Inverter
Push-pull Inverter

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-3

Voltage Transfer Characteristic of the Active Load Inverter


vIN=5.0V vIN=4.5V
vIN=4.0V
0.5
vIN=3.5V
K JI
H vIN=3.0V
0.4

5V
vIN=2.5V

ID (mA)

M2

0.3

M1

vIN=2.0V

0.2

+
vIN

M2
0.1

vIN=1.5V

0.0

vOUT

A,B

vOUT

+
vOUT
W1 = 2m
L1 1m
-

vIN=1.0V
5

M2 cutoff
M2 saturated

3
2

0
0

d
ate
r
u
D
at ve
1 s cti
M 1a
M
E
F

1
Fig. 320-02

W2 = 1m
L2 1m
ID

2v
3
IN

J K

The boundary between active and saturation operation for M1 is


vDS1 vGS1 - VTN vOUT vIN - 0.7V
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-4

Large-Signal Voltage Swing Limits of the Active Load Inverter


Maximum output voltage, vOUT(max):
vOUT(max) VDD - |VTP|
(ignores subthreshold current influence on the MOSFET)
Minimum output voltage, vOUT(min):
Assume that M1 is nonsaturated and that VT1 = |VT2| = VT.
vDS1 vGS1 - VTN vOUT vIN - 0.7V
The current through M1 is

2
vDS1

(vOUT)2
iD = 1(vGS1 VT)vDS1 2 = 1 (VDD VT)(vOUT ) 2

and the current through M2 is


2

iD = 2 (vSG2 VT)2 = 2 (VDD vOUT VT)2 = 2 (vOUT + VT VDD)2


Equating these currents gives the minimum vOUT as,
VDD VT
vOUT(min) = VDD VT
1 + (2/1)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-5

Small-Signal Midband Performance of the Active Load Inverter


The development of the small-signal model for the active load inverter is shown below:
VDD

gm2vgs2
M2
ID vOUT G1
D1=D2=G2
+
vIN
vin gm1vgs1
M1
S1=B1

S2=B2
Rout

rds2

rds1

+
vout
-

+
vin
gm1vin
-

rds1

gm2vout

rds2

+
vout
Fig. 320-03

Sum the currents at the output node to get,


gm1vin + gds1vout + gm2vout + gds2vout = 0
Solving for the voltage gain, vout/vin, gives
K'NW 1L2
gm1
vout
gm1

1/2
=

K' L W
vin gds1 + gds2 + gm2
gm2
P 1 2
The small-signal output resistance can also be found from the above by letting vin = 0 to
get,
1
1
Rout = gds1 + gds2 + gm2 gm2
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-6

Frequency Response of the MOS Diode Load Inverter


VDD
Incorporation of the parasitic
Cgs2
capacitors into the small-signal
model:
M2
Cbd2
If we assume the input voltage has a
Vout
small source resistance, then we can Cgd1
Cbd1
write the following:
CL
M1

Vin

CM
+
Vin gmVin
-

+
Rout

Vout
-

Cout

sCM(Vout-Vin) + gmVin
Cgs1
+ GoutVout + sCoutVout = 0
Vout(Gout + sCM + sCout) = - (gm sCM)Vin

Fig. 320-04

s
sCM

g
R
1
1- gm
m out
z1
Vout
-(gm sCM)

Vin = Gout+ sCM + sCout = -gmRout 1+ sRout(CM + Cout) =


s

1 - p1

where
gm1
and z1 = CM

1
p1 = Rout(Cout+CM) ,

gm = gm1,
and

1
Rout = [gds1+gds2+gm2]-1 gm2 , CM = Cgd1 , and Cout = Cbd1+Cbd2+Cgs2+CL
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-7

Frequency Response of the MOS Diode Load Inverter - Continued


If |p1| < z1, then the -3dB frequency is approximately equal to [Rout(Cout+CM)]-1.

dB
20log10(gmRout)

0dB

z1
|p1| -3dB

log10f
Fig. 5.1-4A

Observation:
The poles in a MOSFET circuit can be found by summing the capacitance connected
to a node and multiplying this capacitance times the equivalent resistance from this node
to ground and inverting the product.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-8

Example 5.1-1 - Performance of an Active Resistor-Load Inverter


Calculate the output-voltage swing limits for VDD = 5 volts, the small-signal gain, the
output resistance, and the -3 dB frequency of active load inverter if (W1/L1) is 2 m/1 m
and W2/L2 = 1 m/1 m, Cgd1 = 100fF, Cbd1 = 200fF, Cbd2 = 100fF, Cgs2 = 200fF, CL = 1
pF, and ID1 = ID2 = 100A, using the parameters in Table 3.1-2.
Solution
From the above results we find that:
vOUT(max) = 4.3 volts
vOUT(min) = 0.418 volts
Small-signal voltage gain = -1.92V/V
Rout = 9.17 k including gds1 and gds2 and 10 k ignoring gds1 and gds2
z1 = 2.10x109 rads/sec
p1 = -64.1x106 rads/sec.
Thus, the -3 dB frequency is 10.2 MHz.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-9

Voltage Transfer Characteristic of the Current Source Inverter


vIN=5.0V vIN=4.5V
vIN=4.0V
0.5
vIN=3.5V
v
IN=3.0V
0.4

5V
vIN=2.5V

2.5V

ID (mA)

0.3
0.2

KJIH F

M1

vIN=2.0V

M2

0.1

D
C

0.0
0

M2

A,B

vOUT

vIN=1.5V

+
vOUT
W1 = 2m
L1 1m
-

vIN=1.0V
5 A B C
D

4
vOUT

+
vIN

W2 = 2m
L2 1m
ID

M2 active
3 M2 saturated

ed
rat
u
t
a ve
1 s ti
M 1 ac
M

2
E

1
0
0

2v
3
IN

Regions of operation for the transistors:


M1:
vDS1 vGS1 -VTn vOUT vIN - 0.7V
M2: vSD2 vSG2 - |VTp| VDD - vOUT VDD -VGG2 - |VTp|
CMOS Analog Circuit Design

J K

Fig. 5.1-5

vOUT 3.2V
P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-10

Large-Signal Voltage Swing Limits of the Current Source Load Inverter


Maximum output voltage, vOUT(max):
vOUT (max) VDD
Minimum output voltage, vOUT(min):
Assume that M1 is nonsaturated. The minimum output voltage is,
vOUT(min) = vOUT(min)

= (VDD - VT1)1 -

1-

2

1

VDD - VGG - |VT2|2



VDD - VT1

This result assumes that vIN is taken to VDD.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-11

Small-Signal Midband Performance of the Current Source Load Inverter


Small-Signal Model:
VDD

ID

VGG2
vIN

S2=B2

M2
vOUT G1
+
vin
M1
-

rds2
D1=D2
gm1vgs1

rds1

Rout
+
vout
-

+
vin
gm1vin
-

rds1

S1=B1=G2

rds2

+
vout
Fig. 5.1-5B

Midband Performance:
2K'NW 1
vout
gm1
1
1
1

1/2 1

=
=
!!!
and
R
=

out
vin gds1 + gds2 L1ID 1 + 2
D
gds1 + gds2 ID(1 + 2)
log|Av|
Amax
Amax
10
Amax
100 Weak
inversion
Amax
1000
0.1A
1A

Strong
inversion
10A

100A

1mA

10mA

ID

Fig. 5.1-6

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-12

Frequency Response of the Current Source Load Inverter


Incorporation of the parasitic
VDD
capacitors into the small-signal
Cgs2
model (x is connected to VGG2):
x

If we assume the input voltage


has a small source resistance,
then we can write the following:

gmRout 1 - z
1
Vout(s)

=
Vin(s)
s
1 - p1

M2

Cgd2
Cgd1
Vin

CM

Cbd2
Vout
Cbd1

M1

CL

+
Vin gmVin
-

+
Rout

Cout

Vout
-

Fig. 5.1-4

gm
1
gm = gm1,
p1 = Rout(Cout+CM) , and z1 = CM
1
and Cout = Cgd2 + Cbd1 + Cbd2 + CL CM = Cgd1
and Rout = gds1 + gds2
Therefore, if |p1|<|z1|, then the 3 dB frequency response can be expressed as
gds1 + gds2
-3dB 1 = C
gd1 + Cgd2 + Cbd1 + Cbd2 + CL
where

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-13

Example 5.1-2 - Performance of a Current-Sink Inverter


VDD
+
A current-sink inverter is shown in Fig. 5.1-7. Assume
VSG1
that W 1 = 2 m, L1 = 1 m, W 2 = 1 m, L2 = 1m, VDD = 5
vIN
M1
volts, VGG1 = 3 volts, and the parameters of Table 3.1-2
ID
vOUT
describe M1 and M2. Use the capacitor values of Example
M2
5.1-1 (Cgd1 = Cgd2). Calculate the output-swing limits and
VGG1
the small-signal performance.
Solution
Figure 5.1-7 Current sink CMOS inverter.
To attain the output signal-swing limitations, we treat
Fig. 5.1-7 as a current source CMOS inverter with PMOS parameters for the NMOS and
NMOS parameters for the PMOS and use NMOS equations. Using a prime notation to
designate the results of the current source CMOS inverter that exchanges the PMOS and
NMOS model parameters,

1101 3-0.7

vOUT(max) = 5V and vOUT(min) = (5-0.7)1 - 1 - 502 5-0-0.72 = 0.74V


In terms of the current sink CMOS inverter, these limits are subtracted from 5V to get
vOUT(max) = 4.26V and v OUT (min) = 0V.
To find the small signal performance, first calculate the dc current. The dc current, ID, is
KNW1
1101
ID = 2L1 (VGG1-VTN)2 = 21 (3-0.7)2 = 291A
and
f-3dB = 2.78 MHz.
vout/vin = 9.2V/V, Rout = 38.1 k,
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-14

Voltage Transfer Characteristic of the Push-Pull Inverter


1.0

v =4.5V
vIN=5.0V IN
vIN=4.0V

0.8
vIN=2.0V

ID (mA)

vIN=3.5V

5V

vIN=0.5V
vIN=1.0V
vIN=1.5V

M2

0.6
vIN=2.5V

0.2
H
I

0.0
0

F
vIN=3.0V

J,K 1

vOUT

vIN=2.0V
D

+
vOUT
W1 = 1m
L1 1m
-

M1

vIN

vIN=3.5V vIN=4.5V

vIN=2.5V

0.4
G

W2 = 2m
L2 1m
ID

vIN=3.0V

vIN=1.5V
vIN=1.0V

4 CA,B 5

A B C

D
E

vOUT

ed
rat
u
t
a ve
1 s ti
M 1 ac
M

ve
cti ted
2 a tura
M sa
2
M

2
1

F
G

0
0

Note
the railto-rail
output
voltage
swing

2v
3
IN

J K

Fig. 5.1-8

Regions of operation for M1 and M2:


M1: vDS1 vGS1 - VT1 vOUT vIN - 0.7V
M2: vSD2 vSG2-|VT2| VDD -vOUT VDD -vIN-|VT2| vOUT vIN + 0.7V
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-15

Small-Signal Performance of the Push-Pull Amplifier


5V

CM
M2
+

M1

+
vin
-

gm1vin

rds1

gm2vin

rds2

Cout

+
vout
-

vout

vin

Fig. 5.1-9

Small-signal analysis gives the following results:


K' (W /L ) +
vout (gm1 + gm2)
K'P(W2/L2)
N
1 1

=
=

(2/I
)
D
vin
1 + 2
gds1 + gds2

1
Rout = g + g
ds1
ds2
gm1+gm2 gm1+gm2
z = CM = Cgd1+Cgd2
and
(gds1 + gds2)
p1 = Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL
If z1 > |p1|, then
gds1 + gds2
-3dB = C + C + C + C + C
gd1
gd2
bd1
bd2
L
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-16

Example 5.1-3 - Performance of a Push-Pull Inverter


The performance of a push-pull CMOS inverter is to be examined. Assume that W 1 =
1 m, L1 = 1 m, W 2 = 2 m, L2 = 1m, VDD = 5 volts, and use the parameters of Table
3.1-2 to model M1 and M2. Use the capacitor values of Example 5.1-1 (Cgd1 = Cgd2).
Calculate the output-swing limits and the small-signal performance assuming that ID1 =
ID2 = 300A.
Solution
The output swing is seen to be from 0V to 5V. In order to find the small signal
performance, we will make the important assumption that both transistors are operating
in the saturation region. Therefore:
vout -257S - 245S
vin = 12S + 15S = -18.6V/V
Rout = 37 k
f-3dB = 2.86 MHz
and
z1 = 399 MHz

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-17

Noise Analysis of Inverting Amplifiers


Noise model:
VDD
en22

M2

VDD
M2

eout2

en12
vin

Noise
Free
MOSFETs

M1

eout2

eeq2
vin

Noise
Free
MOSFETs

M1
Fig. 5.1-10

Approach:
1.) Assume a mean-square input-voltage-noise spectral density en2 in series with the
gate of each MOSFET.
(This step assumes that the MOSFET is the common source configuration.)
2.) Calculate the output-voltage-noise spectral density, eout2 (Assume all sources are
additive).
3.) Refer the output-voltage-noise spectral density back to the input to get equivalent
input noise eeq2.
4.) Substitute the type of noise source, 1/f or thermal.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-18

Noise Analysis of the Active Load Inverter


1.) See model to the right.
Noise
Noise
VDD
VDD
g
m1 2
Free
Free
2
e
2
2
2
n2
2.) eout = en1 g + en2
MOSFETs
MOSFETs
m2
M2
M2
*

gm2 en2
2
2
eout2
eout2
3.) eeq2 = en12 1 + gm1 en1
en12
eeq2



vin
M1
M1
Up to now, the type of noise is not defined. vin
*
*
Fig. 5.1-10
1/f Noise
KF
B
Substituting en2= 2fCoxWLK = fWL , into the above gives,
B1
K'2B2 L1 1/2
1/2
2
eeq(1/f) = fW 1L 1 1 + K'1B1 L2



To minimize 1/f noise, 1.) Make L2>>L1, 2.) increase the value of W1 and 3.) choose M1
as a PMOS.
Thermal Noise
8kT
Substituting en2= 3gm into the above gives,

W L K'

8kT
21/21/2
2 1

eeq(th) =3[2K'1(W/L)1I1]1/2 1+ L2W 1K'1

To minimize thermal noise, maximize the gain of the inverter.


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-19

Noise Analysis of the Active Load Inverter - Continued


When calculating the contribution of en22 to eout2, it was assumed that the gain was
unity. To verify this assumption consider the following model:
en22

+
vgs2

gm2vgs2

rds1

rds2

eout2
_
Fig. 5.1-11

We can show that,


eout2 gm2(rds1||rds2) 2
en22 = 1 + gm2(rds1||rds2) 1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-20

Noise Analysis of the Current Source Load Inverting Amplifier


Model:
VDD
en22

VGG2

M2

M2

Noise
Free
MOSFETs
eout2

eeq2
vin

M1

VDD

eout2

en12
vin

Noise
Free
MOSFETs

M1
Fig. 5.1-12.

The output-voltage-noise spectral density of this inverter can be written as,


eout2 = (gm1rout)2en12 + (gm2rout)2en22
or

2
gm2 2 en2
(gm2rout)2

eeq2 = en12 + (gm1rout)2en22 = en12 1 + gm1 en12

This result is identical with the active load inverter.


Thus the noise performance of the two circuits are equivalent although the small-signal
voltage gain is significantly different.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-21

Noise Analysis of the Push-Pull Amplifier


Model:
VDD
en22

*
vin

M2

eout2

en12

Noise
Free
MOSFETs

M1
Fig. 5.1-13.

The equivalent input-voltage-noise spectral density of the push-pull inverter can be found
as
eeq =

g e
g +g

m1 n1 2

m2
m1

g e
+g

m2 n2 2

m2
m1

+ g

If the two transconductances are balanced (gm1 = gm2), then the noise contribution of
each device is divided by two.
The total noise contribution can only be reduced by reducing the noise contribution of
each device.
(Basically, both M1 and M2 act like the load transistor and input transistor, so
there is no defined input transistor that can cause the noise of the load transistor to be
insignificant.)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 1 (5/2/04)

Page 5.1-22

Summary of CMOS Inverting Amplifiers


Inverter

AC Voltage
Gain

AC Output
Resistance

Bandwidth (CGB=0)

Equivalent,
input-referred,meansquare noise voltage

p-channel
active load
inverter
n-channel
active load
inverter

-gm1
gm2

1
gm2

gm2
CBD1+CGS1+CGS2+CBD2

en12

gm2
+ en22g 2

-gm1
gm2+gmb2

1
gm2+gmb2

gm2+gmb2
CBD1+CGD1+CGS2+CBS2

en12

gm2
+ en22g 2

Current
source load
inverter

-gm1
gds1+gds2

1
gds1+gds2

gds1+gds2
CBD1+CGD1+CDG2+CBD2

en12

gm2
+ en22g 2

n-channel
depletion
load inverter

-gm1
~ gmb2

1
gmb2+gds1+gds2

gmb2+gds1+gds2
CBD1+CGD1+CGS2+CBD2

-(gm1+gm2)
gds1+gds2

1
gds1+gds2

gds1+gds2
CBD1+CGD1+CGS2+CBD2

Push-Pull
inverter

en1

m1

m1

m1

gm2

2
en2 g 2
m1

gm1en1 gm1en1
2

g
+ g
g
g
m2 m1
m2
m1

Inverting configurations we did not examine.


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-1

SECTION 5.2 - DIFFERENTIAL AMPLIFIERS


What is a Differential Amplifier?
+
A differential amplifier is an amplifier that amplifies the +
+
difference between two voltages and rejects the average or
+
v
1
common mode value of the two voltages.
vOUT
v2
Differential and common mode voltages:
Fig.
5.2-1A
v1 and v2 are called single-ended voltages. They are
voltages referenced to ac ground.
The differential-mode input voltage, vID, is the voltage difference between v1 and v2.
The common-mode input voltage, vIC, is the average value of v1 and v2 .
v1+v2
vID = v1 - v2 and vIC = 2
v1 = vIC + 0.5vID and v2 = vIC - 0.5vID
v + v
2
vID
1
vOUT = AVDvID AVCvIC = AVD(v1 - v2) AVC 2
2
+
where
+
vID
vIC
vOUT
2
AVD = differential-mode voltage gain
AVC = common-mode voltage gain
Fig. 5.2-1B

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-2

Differential Amplifier Definitions


Common mode rejection rato (CMRR)
AVD
CMRR = A
VC
CMRR is a measure of how well the differential amplifier rejects the common-mode
input voltage in favor of the differential-input voltage.
Input common-mode range (ICMR)
The input common-mode range is the range of common-mode voltages over which
the differential amplifier continues to sense and amplify the difference signal with the
same gain.
Typically, the ICMR is defined by the common-mode voltage range over which all
MOSFETs remain in the saturation region.
Output offset voltage (VOS(out))
The output offset voltage is the voltage which appears at the output of the differential
amplifier when the input terminals are connected together.
Input offset voltage (VOS(in) = VOS)
The input offset voltage is equal to the output offset voltage divided by the differential
voltage gain.
VOS(out)
VOS = AVD
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-3

Transconductance Characteristic of the Differential Amplifier


Consider the following n-channel differential
amplifier (sometimes called a source-coupled
pair):

VDD

vG1 M1

;y ;y

v
IBias ID

Where should bulk be connected? Consider a


p-well, CMOS technology,
D1 G1 S1
n+

n+

S2 G2 D2

p+

n+

n+

VDD

M4

vGS1

iD1

iD2

M2 v
G2
+
vGS2
-

M3 ISS
VBulk
Fig. 5.2-2

n+

p-well

n-substrate

Fig. 5.2-3

1.) Bulks connected to the sources: No modulation of VT but large common mode
parasitic capacitance.
2.) Bulks connected to ground: Smaller common mode parasitic capacitors, but
modulation of VT.
If the technology is n-well CMOS, there is no choice. The bulks must be connected to
ground.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-4

Transconductance Characteristic of the Differential Amplifier - Continued


Defining equations:
2iD1 1/2
2iD2 1/2
vID = vGS1 vGS2 =
and
ISS = iD1 + iD2

Solution:
2

ISS ISS vID 2vID1/2


iD1 = 2 + 2 ISS 2

4ISS

ISS ISS vID 2vID1/2


iD2 = 2 2 ISS 2

4ISS

and

which are valid for vID < 2(ISS/)1/2.


Illustration of the result:

iD/ISS
1.0
0.8
iD1

0.6
0.4

iD2

0.2

Differentiating iD1 (or iD2)


with respect to vID and
setting VID =0V gives

-2.0

0.0

-1.414

1.414

2.0

vID
(ISS/)0.5 Fig. 5.2-4

K'1 I SS W 1
diD1
1/2
gm = dvID(VID = 0) = (ISS/4)1/2 = 4L1
(half the gm of an inverting amplifier)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-5

Voltage Transfer Characteristic of the Differential Amplifier


In order to obtain the voltage transfer characteristic, a load for the differential amplifier
must be defined. We will select a current mirror load as illustrated below.
VDD
2m
1m

2m
1m

M4
iD4 iOUT

M3
iD3
2m
1m

M1
vGS1

vG1
-

iD1

2m
1m

2m
1m

M2
ISS
M5

VBias

iD2
vGS2

VDD
2
vOUT

vG2
-

Fig. 5.2-5

Note that output signal to ground is equivalent to the differential output signal due to the
current mirror.
The short-circuit, transconductance is given as
K'1 I SS W 1
diOUT
1/2
gm = dvID (VID = 0) = (ISS)1/2 = L1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-6

Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load
VDD = 5V

2m
1m

iD1

2m
1m

M1
vGS1 -

vG1

2m
1m

M2
ISS
M5

iD2

+
- vGS2 vOUT
vG2
-

M4 active
M4 saturated

M4 iD4 iOUT

M3

vOUT (Volts)

iD3

2m
1m

2m
1m

VIC = 2V
2

M2 saturated
M2 active

0
-1

VBias

-0.5

0
vID (Volts)

0.5

1
Fig. 330-01

Regions of operation of the transistors:


M2 is saturated when,
vDS2 vGS2-VTN vOUT-VS1 VIC-0.5vID-VS1-VTN vOUT VIC-VTN
where we have assumed that the region of transition for M2 is close to vID = 0V.
M4 is saturated when,
vSD4 vSG4 - |VTP| VDD-vOUT VSG4-|VTP| vOUT VDD-VSG4+|VTP|
The regions of operations shown on the voltage transfer function assume ISS = 100A.
250
Note: VSG4 = 502 +|VTP| = 1 + |VTP| vOUT 5 - 1 - 0.7 + 0.7 = 4V
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-7

Differential Amplifier Using p-channel Input MOSFETs


VDD
M5
VBias

IDD

vSG1
+
M1
iD1
iD3

vG1
M3
-

M2

vSG2
+
iD2 iOUT
iD4

M4

+
vOUT
-

+
vG2
Fig. 5.2-7

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-8

Input Common Mode Range (ICMR)


ICMR is found by setting vID = 0 and varying vIC
until one of the transistors leaves the saturation.
Highest Common Mode Voltage
Path from G1 through M1 and M3 to VDD:
VIC(max) =VG1(max) =VG2(max)
=VDD -VSG3 -VDS1(sat) +VGS1
or
VIC(max) = VDD - VSG3 + VTN1
Path from G2 through M2 and M4 to VDD:
VIC(max) =VDD -VSD4(sat) -VDS2(sat) +VGS2
=VDD -VSD4(sat) + VTN2

VDD
2m
1m

2m
1m

M4
iD4 iOUT

M3
iD3
2m
1m

2m
1m

iD1
M1

vGS1

vG1
-

iD2

M2
-

2m
1m

ISS

vGS2

VDD
2

vOUT

vG2

M5

VBias

Fig. 330-02

VIC(max) = VDD - VSG3 + VTN1

Lowest Common Mode Voltage (Assume a VSS for generality)


VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
where we have assumed that VGS1 = VGS2 during changes in the input common mode
voltage.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-9

Example 5.2-1 - Small-Signal Analysis of the Differential-Mode of the Diff. Amp


A requirement for differential-mode operation is that the differential amplifier is balanced.
VDD

iD3

iD2

iD1
M1

M2

vid

vout
M5
VBias

ISS

C3

D1=G3=D3=G4

M4
iD4 iout

M3

G1
+ vid
+
vg1
-

G2
+
vg2
C1
-

rds1
i3
1
gm3

rds3

S1=S2
rds5

gm2vgs2

gm1vgs1

D2=D4

rds2
i3

S3
G2
G1
+ vid +
+
vgs2
vgs1
gm1vgs1
-

S4

D1=G3=D3=G4
i3
1
rds1 rds3 gm3

rds4 C2

+
vout

D2=D4
C3
C1 gm2vgs2
S1=S2=S3=S4

i3

rds2

rds4 C2

iout'
+
vout
Fig. 330-03

Differential Transconductance:
Assume that the output of the differential amplifier is an ac short.
gm1gm3rp1
iout = 1 + g r vgs1 gm2vgs2 gm1vgs1 gm2vgs2 = gmdvid
m3 p1
where gm1 = gm2 = gmd, rp1 = rds1rds3 and i'out designates the output current into a short
circuit.

It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue to
use the assumption regardless.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-10

Small-Signal Analysis of the Differential-Mode of the Diff. Amplifier - Continued


Output Resistance:
Differential Voltage Gain:
vout
gmd
1
rout = gds2 + gds4 = rds2||rds4
Av = vid = gds2 + gds4
If we assume that all transistors are in saturation and replace the small signal
parameters of gm and rds in terms of their large-signal model equivalents, we achieve
vout (K'1ISSW1/L1)1/2
2 K'1W 11/2
1
Av = vid = (2 + 4)(ISS/2) = 2 + 4 ISSL1

ISS
Note that the small-signal gain is inversely
vout
proportional to the square root of the bias
vin
Stong Inversion
current!
Weak
InversExample:
ion
If W1/L1 = 2m/1m and ISS = 50A
log(IBias)
1A
(10A), then
Fig. 330-04
Av(n-channel) = 46.6V/V (104.23V/V)
Av(p-channel) = 31.4V/V (70.27V/V)
1
1
rout = gds2 + gds4 = 25A0.09V-1 = 0.444M (2.22M)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-11

Common Mode Analysis for the Current Mirror Load Differential Amplifier
The current mirror load differential amplifier is not a good example for common mode
analysis because the current mirror rejects the common mode signal.
VDD
-M3-M4
1
M
M3

M4

M2

+
v 0V
M2 out

M1
vic
+
VBias
-

M5

Fig. 5.2-8A

Total common Common mode Common mode



mode Output = output due to - output due to
due to vic
M1-M3-M4 path
M2 path

Therefore:
The common mode output voltage should ideally be zero.
Any voltage that exists at the output is due to mismatches in the gain between the two
different paths.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-12

Small-Signal Analysis of the Common-Mode of the Differential Amplifier


The common-mode gain of the differential amplifier with a current mirror load is ideally
zero.
To illustrate the common-mode gain, we need a different type of load so we will consider
the following:
VDD

M3
vo1

M1
vid
2

VDD

M4
vo2
M2

vo1
v1

M3

M1

vid
2

VDD

M4

M2

vo1

vo2
v2

ISS
2

ISS
M5

M4

vo2

M2
M1
1
M5x 2
ISS
2

vic

VBias

Differential-mode circuit

M3

vic
VBias

General circuit

Common-mode circuit
Fig. 330-05

Differential-Mode Analysis:
gm1
vo2
gm2
vo1

and

+
vid
2gm3
vid
2gm4
Note that these voltage gains are half of the active load inverter voltage gain.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-13

Small-Signal Analysis of the Common-Mode of the Differential Amplifier Contd


Common-Mode Analysis:
Assume that rds1 is large and can be
+
ignored (greatly simplifies the
vic
analysis).

vgs1 = vg1-vs1 = vic - 2gm1rds5vgs1

+ vgs1 2rds5

gm1vgs1
rds1 rds3

+
1
gm3

vo1
-

Fig. 330-06

Solving for vgs1 gives


vic
vgs1 = 1 + 2g r
m1 ds5
The single-ended output voltage, vo1, as a function of vic can be written as
gm1[rds3||(1/gm3)]
(gm1/gm3)
gds5
vo1
=

1 + 2gm1rds5
1 + 2gm1rds5
vic
2gm3
Common-Mode Rejection Ratio (CMRR):
|vo1/vid| gm1/2gm3
CMRR = |v /v | = g /2g = gm1rds5
o1 ic
ds5 m3
How could you easily increase the CMRR of this differential amplifier?

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-14

Frequency Response of the Differential Amplifier


Back to the current mirror load differential amplifier:
Cbd3

VDD
Cgs3+Cgs4
M4
M3
Cgd4

Cgd1
vid

Cbd4
Cgd2 +
vout
CL
-

Cbd1
Cbd2
M2

M1
M5

G2
G1
D1=G3=D3=G4
+ vid +
+
i3
C3
vgs2
vgs1
1
gm1vgs1
gm3 C1 gm2vgs2
S1=S2=S3=S4

VBias

iout'

D2=D4
i3

rds2

rds4 C2

+
vout
-

Fig. 330-07

Ignore the zeros that occur due to Cgd1, Cgd2 and Cgd4.
C1 = Cgd1 + Cbd1 + Cbd3 + Cgs3 + Cgs4,C2 = Cbd2 + Cbd4 + Cgd2 + CL and C3 = Cgd4
If C3 0, then we can write

2
gm3
ggs2 + gds4
gm1

Vout(s) g + g gm3 + sC1 Vgs1(s) - Vgs2(s) s + where 2


C2
ds2
ds4


2
If we further assume that gm3/C1 >> (gds2+gds4)/C2 = 2
then the frequency response of the differential amplifier reduces to
Vout(s) gm1 2
(A more detailed analysis will be made in Chapter 6)
Vid(s) gds2 + gds4 s + 2
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-15

An Intuitive Method of Small Signal Analysis


Small signal analysis is used so often in analog circuit design that it becomes desirable to
find faster ways of performing this important analysis.
Intuitive Analysis (or Schematic Analysis)
Technique:
1.) Identify the transistor(s) that convert the input voltage to current (these transistors
are called transconductance transistors).
2.) Trace the currents to where they flow into an equivalent resistance to ground.
3.) Multiply this resistance by the current to get the voltage at this node to ground.
4.) Repeat this process until the output is reached.
Simple Example:
VDD

VDD

R1
gm1vin
vin

M2

vo1 gm2vo1
M1

vout

R2
Fig. 5.2-10C

vo1 = -(gm1vin) R1 vout = -(gm2vo1)R2


CMOS Analog Circuit Design

vout = (gm1R1gm2R2)vin
P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-16

Intuitive Analysis of the Current-Mirror Load Differential Amplifier


VDD
M4

M3
gm1vid gm1vid
2
2
M1 gm1vid gm2vid
2
2
+
vid
2 M5

rout
+
M2
vid
vout
+ 2

vid

VBias

Fig. 5.2-11

1.) i1 = 0.5gm1vid and i2 = -0.5gm2vid


2.) i3 = i1 = 0.5gm1vid
3.) i4 = i3 = 0.5gm1vid
1
+
ds2 gds4
gm1vin
gm2vin
vout
gm1
5.) vout = (0.5gm1vid+0.5gm2vid )rout =gds2+gds4 = gds2+gds4 vin = gds2+gds4
4.) The resistance at the output node, rout, is rds2||rds4 or g

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-17

Some Concepts to Help Extend the Intuitive Method of Small-Signal Analysis


1.) Approximate the output resistance of any cascode circuit as
Rout (gm2rds2)rds1
where M1 is a transistor cascoded by M2.
2.) If there is a resistance, R, in series with the source of the transconductance transistor,
let the effective transconductance be
gm
gm(eff) = 1+gmR
Proof:
gm2(eff)vin

gm2(eff)vin

M2

gm2vgs2 iout
+ vgs2 -

M2

rds1

vin

vin

M1 vin
VBias

rds1

Small-signal model
Fig. 5.2-11A

vin
vgs2 = vg2 - vs2 = vin - (gm2rds1)vgs2 vgs2 = 1+gm2rds1
gm2vin
Thus, iout = 1+gm2rds1 = gm2(eff) vin
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-18

Slew Rate of the Differential Amplifier


Slew Rate (SR) = Maximum output-voltage rate (either positive or negative)
dvOUT
It is caused by, iOUT = CL dt . When iOUT is a constant, the rate is a constant.
Consider the following current-mirror load, differential amplifiers:
VDD

VDD

iD3

M1
vGS1

vG1
-

VBias

M2
-

+
CL

vSG1
+
M1
+
iD1

vOUT

vG1

vGS2 +
vG2

ISS

IDD

iD2

iD1
+

M5

M4
iD4 iOUT

M3

M2

VBias

iD2 iOUT

iD3

iD4
M4 CL

M3

M5

vSG2
+

+
vG2
vOUT
Fig. 5.2-11B

Note that slew rate can only occur when the differential input signal is large enough to
cause ISS (IDD) to flow through only one of the differential input transistors.
ISS IDD
SR = C = C
If CL = 5pF and ISS = 10A, the slew rate is SR = 2V/s.
L
L
(For the BJT differential amplifier slewing occurs at 100mV whereas for the MOSFET
differential amplifier it can be 2V or more.)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-19

Noise Analysis of the Differential Amplifier


VDD

VDD
M5

M5

M5
VBias

VBias

en12
M1

M2

en22

eeq2

M1

M2

ito2
M3

en32

en42

M4

vOUT
Vout

M3

M4
Fig. 5.2-11C

Solve for the total output-noise current to get,


ito 2 = gm12en12 + gm22en22 + gm32en32 + gm42en42
This output-noise current can be expressed in terms of an equivalent input noise voltage,
eeq2, given as
ito2 = gm12eeq2
Equating the above two expressions for the total output-noise current gives,
gm3
eeq2 = en12 + en22 + g 2 en32 + en42
m1
2
2
Thermal Noise (en12=en22 and en32=en42):
1/f Noise (en1 =en2 and en32=en42):
KN BN L1
W 3L 1K'3


2BP
16kT

1/2


eeq(1/f)= fW L
1 + K B L eeq(th)= 3[2K' (W/L) I ]1/2 1+ L3W 1K'1
1 1
P P 3

1
1 1


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-20

Current-Source Load Differential Amplifier


Gives a truly balanced differential amplifier.
VDD

M3
X1
M7

v3
v1

IBias

M4

X1

X1

I3

I4

I1

I2

M1 X1
M5

M6
X1

v4
v2

X1 M2
I5
X2
Fig. 5.2-12

Also, the upper input common-mode range is extended.


However, a problem occurs if I1 I3 or if I2 I4.
Current

Current

0
0

I3

I1

I3

VDD

VDS1<VDS(sat)
(a.) I1>I3.

vDS1 0

I1

VSD3<VSD(sat)
(b.) I3>I1.

VDD

vDS1

Fig. 5.2-13

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-21

A Differential-Output, Differential-Input Amplifier


Probably the best way to solve the current mismatch problem is through the use of
common-mode feedback.
Consider the following solution to the previous problem.
VDD
M3
IBias MC3
Commonmode feedback circuit

MC1

v3

MC4
IC4

IC3

M4
I3

I4

MC2A
v1

VCM
MC2B
MC5

M1

M2

v4
Selfresistances
of M1-M4
v2

M5

MB

VSS

Fig. 5.2-14

Operation:
Common mode output voltages are sensed at the gates of MC2A and MC2B and
compared to VCM.
The current in MC3 provides the negative feedback to drive the common mode output
voltage to the desired level.
With large values of output voltage, this common mode feedback scheme has flaws.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-22

Common-Mode Stabilization of the Diff.-Output, Diff.-Input Amplifier - Continued


The following circuit avoids the large differential output signal swing problems.
VDD
M3
IBias MC3
Commonmode feedback circuit

MC4
IC4

IC3
MC1

MC2

v3

MC5

I3

I4

RCM1
RCM2
v1

VCM

M4

M1

M2

v4
Selfresistances
of M1-M4
v2

M5

MB

VSS

Fig. 5.2-145

Note that RCM1 and RCM2 must not load the output of the differential amplifier.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-23

Design of a CMOS Differential Amplifier with a Current Mirror Load


Design Considerations:
VDD
Specifications
Constraints
Power supply
Small-signal gain
M3
M4
Technology
Frequency response (CL)
Temperature
ICMR
Slew rate (CL)
+
vin M1
M2
Power dissipation
Relationships
I5
Av = gm1Rout
M5
VBias
-3dB = 1/RoutCL
VSS
VIC(max) = VDD - VSG3 + VTN1
VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
SR = ISS/CL
Pdiss = (VDD+|VSS|)xAll dc currents flowing from VDD or to VSS

CMOS Analog Circuit Design

vout
CL

ALA20

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-24

Design of a CMOS Differential Amplifier with a Current Mirror Load - Continued


Schematic-wise, the design procedure is illustrated as
shown:

Max. ICMR
VSG4
-

M3

VDD

M4
vout

gm1Rout
+
vin

M2

M1

Min. ICMR
+
VBias
-

CL

I5

I5 = SRCL,
-3dB, Pdiss

M5
VSS

ALA20

Procedure:
1.) Pick ISS to satisfy the slew rate knowing CL or
the power dissipation
2.) Check to see if Rout will satisfy the frequency
response, if not change ISS or modify circuit
3.) Design W3/L3 (W4/L4) to satisfy the upper ICMR
4.) Design W1/L1 (W2/L2) to satisfy the gain
5.) Design W5/L5 to satisfy the lower ICMR
6.) Iterate where necessary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-25

Example 5.2-2 - Design of a MOS Differential Amp. with a Current Mirror Load
Design the currents and W/L values of the current mirror load MOS differential amplifier
to satisfy the following specifications: VDD = -VSS = 2.5V, SR 10V/s (CL=5pF), f-3dB
100kHz (CL=5pF), a small signal gain of 100V/V, -1.5VICMR2V and Pdiss 1mW.
Use the parameters of KN=110A/V2, KP=50A/V2, VTN=0.7V, VTP=-0.7V,
N=0.04V-1 and P=0.05V-1.
Solution
1.) To meet the slew rate, ISS 50A. For maximum Pdiss, ISS 200A.
2
2.) f-3dB of 100kHz implies that Rout 318k. Therefore Rout = (N+P)ISS 318k
ISS 70A Thus, pick ISS = 100A
3.) VIC(max) = VDD - VSG3 + VTN1 2V = 2.5 - VSG3 + 0.7
250A
VSG3 = 1.2V =
50A/V2(W3/L3) + 0.7
W3 W4
2
L3 = L4 = (0.5)2 = 8
gm1
W1 W 2
2110A/V2(W1/L1)
W1
= 23.31

4.) 100=gm1Rout=gds2+gds4 =
L1
L1 = L2 =18.4
(0.04+0.05) 50A

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 2 (5/2/04)

Page 5.2-26

Example 5.2-2 - Continued


5.) VIC(min) = VSS +VDS5(sat)+VGS1 -1.5 = -2.5+VDS5(sat)+

250A
110A/V2(18.4) + 0.7

W5
2ISS
VDS5(sat) = 0.3 - 0.222 = 0.0777 L5 =
KNVDS5(sat)2 = 17.35
We probably should increase W1/L1 to reduce VGS1 and allow for a variation in VTN. If
we choose W1/L1 = 40, then VDS5(sat) = 0.149V and W5/L5 = 9. (Larger than specified
gain should be okay.)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-1

SECTION 5.3 - CASCODE AMPLIFIER


Why Use the Cascode Amplifier?
Can provide higher output resistance and larger gain if the load is also high resistance.
It reduces the Miller effect when the driving source has a large source resistance.
VDD
M3
VGG3
+

VGG2
RS
vS

+
vIN
-

Cgd1

M2
Rs2
+

v1
M1 -

vOUT
Fig. 5.3-1

The Miller effect causes Cgd1 to be increased by the value of 1 + (v1/vin) and appear in
parallel with the gate-source of M1 causing a dominant pole to occur.
The cascode amplifier eliminates this dominant pole by keeping the value of v1/vin
small by making the value of R2 to be approximately 2/gm2.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-2

Large-Signal Characteristics of the Cascode Amplifier


vIN=5.0V

vIN=4.5V

0.5

0.3

vIN=2.5V

ID (mA)

0.4

vIN=4.0V
vIN=3.5V
vIN=3.0V
K

0.2

5V
M3 W3 2m
=
L3 1m
ID

2.3V

M2

G F
E

JIH

M3

0.1
0.0
0

vOUT

M1
vIN=1.5V

+
vIN

A,B

vIN=2.0V 3.4V

vIN=1.0V

+
W2 2m
=
L2 1m
vOUT
W1 2m
=
L1 1m
-

5 A B C
D

4
vOUT

M3 active
M3 saturated

M2 saturated
M2 active

2
F

1
Fig. 5.3-2

0
0

M1 saturated

G H

M1
active

2v
3
IN

J K

M1 sat. when VGG2-VGS2 VGS1-VT vIN 0.5(VGG2+VTN) where VGS1=VGS2


M2 sat. when VDS2VGS2-VTN vOUT-VDS1VGG2-VDS1-VTN vOUT VGG2-VTN
M3 is saturated when VDD-vOUT VDD - VGG3 - |VTP| vOUT VGG3 + |VTP|
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-3

Large-Signal Voltage Swing Limits of the Cascode Amplifier


Maximum output voltage, vOUT(max):
vOUT(max) = VDD
Minimum output voltage, vOUT(min):
Referencing all potentials to the negative power supply (ground in this case), we may
express the current through each of the devices, M1 through M3, as
2

vDS1

iD1 = 1 (VDD - VT1)vDS1 - 2 1(VDD - VT1)vDS1

(vOUT - vDS1)2
iD2 = 2 (VGG2 - vDS1 - VT2)(vOUT - vDS1)
2

2(VGG2 - vDS1 - VT2)(vOUT - vDS1)

and

3
iD3 = (VDD VGG3 |VT3|)2
2
where we have also assumed that both vDS1 and vOUT are small, and vIN = VDD.
Solving for vOUT by realizing that iD1 = iD2 = iD3 and 1 = 2 we get,

3
1
1
vOUT(min) = 22 (VDD VGG3 |VT3|)2 VGG2 VT2 + VDD VT1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-4

Example 5.3-1 - Calculation of the Min. Output Voltage for the Cascode Amplifier
(a.) Assume the values and parameters used for the cascode configuration plotted in the
previous slide on the voltage transfer function and calculate the value of vOUT(min).
(b.) Find the value of vOUT(max) and vOUT(min) where all transistors are in saturation.
Solution
(a.) Using the previous result gives,
vOUT(min) = 0.50 volts.
We note that simulation gives a value of about 0.75 volts. If we include the influence of
the channel modulation on M3 in the previous derivation, the calculated value is 0.62
volts which is closer. The difference is attributable to the assumption that both vDS1 and
vOUT are small.
(b.) The largest output voltage for which all transistors of the cascode amplifier are in
saturation is given as
vOUT(max) = VDD - VSD3(sat)
and the corresponding minimum output voltage is
vOUT(min) = VDS1(sat) + VDS2(sat) .
For the cascode amplifier of Fig. 5.3-2, these limits are 3.0V and 2.7V.
Consequently, the range over which all transistors are saturated is quite small for a 5V
power supply.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-5

Small-Signal Midband Performance of the Cascode Amplifier


Small-signal model:
gm2vgs2= -gm2v1
D1=S2

G1
D2=D3
rds2
+
+
+
vin =
v1
r
v
ds3
out
vgs1 gm1vgs1
rds1
S1=G2=G3
Small-signal model of cascode amplifier neglecting the bulk effect on M2.
C1
rds2
D1=S2
D2=D3
G1
+
+
+
vin
1
v1
g
v
gm1vin
C
r
C
v
m2
1
2
ds3
3
out
rds1 gm2
Simplified equivalent model of the above circuit.
Fig. 5.3-3

Using nodal analysis, we can write,


[gds1 + gds2 + gm2]v1 gds2vout = gm1vin
[gds2 + gm2]v1 + (gds2 + gds3)vout = 0
Solving for vout/vin yields
vout
gm1(gds2 + gm2)
=
vin gds1gds2 + gds1gds3 + gds2gds3 + gds3gm2
The small-signal output resistance is,
rout = [rds1 + rds2 + gm2rds1rds2]||rds3 rds3
CMOS Analog Circuit Design

gm1
gds3 =

2K'1W 1
L1ID23

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-6

Small-Signal Analysis of the Cascode Amplifier - Continued


It is of interest to examine the voltage gain of v1/vin. From the previous nodal equations,
gds2+gds3 gm1
v1
gm1(gds2+gds3)
2gm1
W 1L 2

=
2

vin gds1gds2+gds1gds3+gds2gds3+gds3gm2 gds3 gm2


gm2
L 1W 2
If the W/L ratios of M1 and M2 are equal and gds2 = gds3, then v1/vin is approximately 2.
Why is this gain -2 instead of -1?
gm2vs2
iA
R
s2
Consider the small-signal model looking into the
i1
i
B
source of M2:
rds3
The voltage loop is written as,
vs2
rds2
Fig. 5.3-4
vs2 = (i1 - gm2vs2)rds2 + i1rds3
= i1(rds2 + rds3) - gm2 rds2vs2
Solving this equation for the ratio of vs2 to i1
gives
vs2
rds2 + rds3
Rs2 = i1 = 1 + gm2rds2
We see that Rs2 equals 2/gm2 if rds2 rds3. Thus, if gm1 gm2, the voltage gain v1/vin -2.
Note that:
rds3 =0 that Rs21/gm2 or rds3=rds2 that Rs22/gm2 or rds3rds2gmrds that Rs2rds!!!
Principle: The small-signal resistance looking into the source of a MOSFET depends on
the resistance connected from the drain of the MOSFET to ac ground.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-7

Frequency Response of the Cascode Amplifier


Small-signal model (RS = 0):
C1
rds2
D1=S2
where
G1
+
+
C1 = Cgd1,
vin
1
v
gm2v1
gm1vin
1
rds1 gm2 C2
C2 = Cbd1+Cbs2+Cgs2, and
C3 = Cbd2+Cbd3+Cgd2+Cgd3+CL
The nodal equations now become:
(gm2 + gds1 + gds2 + sC1 + sC2)v1 gds2vout = (gm1 sC1)vin
and
(gds2 + gm2)v1 + (gds2 + gds3 + sC3)vout = 0
Solving for Vout(s)/Vin(s) gives,


(gm1 sC1)(gds2 + gm2)
Vout(s)
1


Vin(s) = 1 + as + bs2 gds1gds2 + gds3(gm2 + gds1 + gds2)
where
C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)
a=
gds1gds2 + gds3(gm2 + gds1 + gds2)
and
C3(C1 + C2)
b = gds1gds2 + gds3(gm2 + gds1 + gds2)
CMOS Analog Circuit Design

D2=D3
rds3

C3

+
vout
-

Fig. 5.3-4A

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-8

A Simplified Method of Finding an Algebraic Expression for the Two Poles


Assume that a general second-order polynomial can be written as:

1
s
s
1
s2
P(s) = 1 + as + bs2 = 1 p1 1 p2
= 1 s p1 + p2 + p1p2

Now if |p2| >> |p1|, then P(s) can be simplified as


s
s2
P(s) 1 p1 + p1p2
Therefore we may write p1 and p2 in terms of a and b as
1
a
p1 = a and p2 = b
Applying this to the previous problem gives,
[gds1gds2 + gds3(gm2 + gds1 + gds2)]
gds3
p1 = C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3) C3
The nondominant root p2 is given as
[C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)]
gm2

p2 =
C1 + C2
C3(C1 + C2)
Assuming C1, C2, and C3 are the same order of magnitude, and gm2 is greater than gds3,
then |p1| is smaller than |p2|. Therefore the approximation of |p2| >> |p1| is valid.
Note that there is a right-half plane zero at z1 = gm1/C1.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-9

Driving Amplifiers from a High Resistance Source - The Miller Effect


VDD
C2
Examine the frequency
M2
response of a current-source
+
+
Vin
VGG2
vout
C
V
V
load inverter driven from a
3
C
1
R
out
1
s
R3
Rs
gm1V1
high resistance source:
M1
vin
C1 Cgs1
C3 = Cbd1 + Cbd2 + Cgd2
Rs
Assuming the input is Iin, Rs
R3 = rds1||rds2
C
C
=
Fig. 5.3-5
2
gd1
the nodal equations are,
[G1 + s(C1 + C2)]V1 sC2Vout = Iin and (gm1sC2)V1+[G3+s(C2+C3)]Vout = 0
where
G1 = Gs (=1/Rs), G3 = gds1 + gds2, C1 = Cgs1, C2 = Cgd1 and C3 = Cbd1+Cbd2 + Cgd2.
Solving for Vout(s)/Vin(s) gives
(sC2gm1)G1
Vout(s)
=
Vin(s) G1G3+s[G3(C1+C2)+G1(C2+C3)+gm1C2]+(C1C2+C1C3+C2C3)s2
or
Vout(s) gm1
[1s(C2/gm1)]
=

Vin(s) G3 1+[R1(C1+C2)+R3(C2+C3)+gm1R1R3C2]s+(C1C2+C1C3+C2C3)R1R3s2
Assuming that the poles are split allows the use of the previous technique to get,
gm1C2
1
1
p1 = R1(C1+C2)+R3(C2+C3)+gm1R1R3C2 gm1R1R3C2 andp2 C1C2+C1C3+C2C3
The Miller effect has caused the input pole, 1/R1C1, to be decreased by a value of gm1R3.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-10

How does the Cascode Amplifier Solve the Miller Effect?


The dominant pole of the inverting amplifier with a large source resistance was found to
be
1
p1(inverter) = R1(C1+C2)+R3(C2+C3)+gm1R1R3C2
Now if a cascode amplifier is used, R3, can be approximated as 2/gm of the cascoding
transistor (assuming the drain sees an rds to ac ground).
1
p1(cascode) =
2
2

R1(C1+C2)+ gm(C2+C3)+gm1R1gmC2

1
1

2
R1(C1+3C2)
R1(C1+C2)+ gm(C2+C3)+2R1C2

Thus we see that p1(cascode) >> p1(inverter).

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-11

High Gain and High Output Resistance Cascode Amplifier


V
If the load of the cascode
M4 DD
D2=D3
amplifier is a cascode
VGG4
current source, then both
M3
VGG3
high output resistance
gm2v1 gmbs2v1 rds2 gm3v4
vout
and high voltage gain is
M2
D1=S2
G1
Rout
achieved.
VGG2
vin

M1

+
gmbs3v4 rds3

vin
gm1vin
-

v1

rds1

G2=G3=G4=S1=S4

D4=S3
+
v4

vout

rds4
-

Fig. 5.3-6

The output resistance is,


-1.5

rout [gm2rds1rds2][gm3rds3rds4] =

ID

12
34
+
2K'2(W/L)2
2K'3(W/L)3

Knowing rout, the gain is simply


-1

2K'1(W/L)1ID
Av = gm1rout gm1{[gm2rds1rds2][gm3rds3rds4]}
12
34
+
2K'2(W/L)2
2K'3(W/L)3
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-12

Example 5.3-2 - Comparison of the Cascode Amplifier Performance


Calculate the small-signal voltage gain, output resistance, the dominant pole, and the
nondominant pole for the low-gain, cascode amplifier and the high-gain, cascode
amplifier. Assume that ID = 200 microamperes, that all W/L ratios are 2m/1m, and
that the parameters of Table 3.1-2 are valid. The capacitors are assumed to be: Cgd = 3.5
fF, Cgs = 30 fF, Cbsn = Cbdn = 24 fF, Cbsp = Cbdp = 12 fF, and CL = 1 pF.
Solution
The low-gain, cascode amplifier has the following small-signal performance:
Av = 37.1V/V
Rout = 125k
p1 -gds3/C3 1.22 MHz
p2 gm2/(C1+C2) 605 MHz.
The high-gain, cascode amplifier has the following small-signal performance:
Av = 414V/V
Rout = 1.40 M
p1 1/RoutC3 108 kHz
p2 gm2/(C1+C2) 579 MHz
(Note at this frequency, the drain of M2 is shorted to ground by the load capacitance, CL)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-13

Designing Cascode Amplifiers


Pertinent design equations for the simple cascode amplifier.

I=

VDD

K PW 3
2
2L3 (VDD - VGG3-|VTP|)

vOUT(max) = VDD - VSD3(sat)


2I
=VDD KP(W3/L3)

M3
VGG3
+

M2
VGG2

VGG2 = VDS1(sat) + VGS2 +


vIN
-

Fig. 5.3-7

CMOS Analog Circuit Design

vOUT(min) =VDS1(sat) + VDS2(sat)


2I
2I
=
+
KN(W1/L1) KN(W2/L2)

vOUT

I = Pdiss = (SR)Cout
VDD

M1
-

g
1/L1)
|Av| = g m1 = 2KN(W
2
ds3
P I

P.E. Allen - 2004

Chapter 5 Section 3 (5/2/04)

Page 5.3-14

Example 5.3-3 - Design of a Cascode Amplifier


The specs for a cascode amplifier are Av = -50V/V, vOUT(max) = 4V, vOUT(min) = 1.5V,
VDD=5V, and Pdiss=1mW. The slew rate with a 10pF load should be 10V/s or greater.
Solution
The slew rate requires a current greater than 100A while the power dissipation
requires a current less than 200A. Compromise with 150A. Beginning with M3,
W3
2I
2150
L3 = KP[VDD-vOUT(max)]2 = 50(1)2 = 6
2I
2150
From this find VGG3: VGG3 = VDD - |VTP| KP(W3/L3) = 5 - 1 506 = 3V
W1 (Av)2I (500.05)2(150)
Next,
= 2.73
L1 = 2KN =
2110
To design W2/L2, we will first calculate VDS1(sat) and use the vOUT(min) specification to
2I
2150
VDS1(sat) =
=
define VDS2(sat).
KN(W1/L1)
1104.26 = 0.8V
Subtracting this value from 1.5V gives VDS2(sat) = 0.7V.
W2
2I
2150

L2 = KNVDS2(sat)2 = 1100.72 = 5.57


2I
Finally,
VGG2 = VDS1(sat) +
KN(W2/L2) + VTN = 0.8V+ 0.7V + 0.7V = 2.2V
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 4 (5/2/04)

Page 5.4-1

SECTION 5.4 - CURRENT AMPLIFIERS


What is a Current Amplifier?
An amplifier that has a defined output-input current relationship
Low input resistance
High output resistance
Application of current amplifiers:
ii
io

ii
Ai
iS

Current
Amplifier

RS

Single-ended input.

RS >> Rin

iS
RL

RS

ii

+
-

io
Ai

Current
Amplifier
Differential input.

RL
Fig. 5.4-1

and Rout >> RL

Advantages of current amplifiers:


Currents are not restricted by the power supply voltages so that wider dynamic
ranges are possible with lower power supply voltages.
-3dB bandwidth of a current amplifier using negative feedback is independent of the
closed loop gain.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 4 (5/2/04)

Page 5.4-2

Frequency Response of a Current Amplifier with Current Feedback


Consider the following current amplifier with resistive
i2 - R2
negative feedback applied.
i
R1

Assuming that the small-signal resistance looking into vin


the current amplifier is much less than R1 or R2,
vin

io = Ai(i1-i2) = Ai R1 - io

Solving for io gives


Ai vin
R2 Ai
vout = R2io = R1 1+Ai vin
io = 1+Ai R1

Ao
If Ai(s) = s
, then
A + 1
vout R2 1 R2
R2 Ao
Ao

1 R1 s
s
vin R1
R1 1+Ao

A +(1+Ao)
1+ Ai(s)
A(1+Ao) +1
-3dB = A(1+Ao)

Ai

io

vout

Fig. 5.4-2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 4 (5/2/04)

Page 5.4-3

Bandwidth Advantage of a Current Feedback Amplifier


The unity-gainbandwidth is,
R2
R2
R2Ao
GB = |Av(0)| -3dB = R1(1+Ao) A(1+Ao) = R AoA = R GBi
1
1
where GBi is the unity-gainbandwidth of the current amplifier.
Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.
Illustration:
Magnitude dB

R
Voltage Amplifier, R2 > K
R2 Ao
1
dB
R2
R1 1+Ao
Voltage Amplifier, R = K >1
1
Ao
dB
K
1+Ao
Current Amplifier
Ao dB
(1+Ao)A
0dB

GBi

GB1 GB2

log10()
Fig. 7.2-10

Note that GB2 > GB1 > GBi


The above illustration assumes that the GB of the voltage amplifier realizing the voltage
buffer is greater than the GB achieved from the above method.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 4 (5/2/04)

Page 5.4-4

Current Amplifier using the Simple Current Mirror


VDD

VDD

I1

iin
M1

I2
R

iout
M2

iin
+
vin
gm1vin
-

iout
C2
rds1

and

gm2vin

rds2

RL
0

C3

Fig. 5.4-3

Current Amplifier

1
1
Rin = gm1 Rout = 1Io

C1

W2/L2
Ai = W 1/L 1 .

Frequency response:
-(gm1+gds1)
-(gm1+gds1)
-gm1
p1 = C1+C2 = Cbd1+Cgs1+Cgs2+Cgd2 Cbd1+Cgs1+Cgs2+Cgd2
Note that the bandwidth can be almost doubled by including the resistor, R.
(R removes Cgs1 from p1)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 4 (5/2/04)

Page 5.4-5

Example 5.4-1- Performance of a Simple Current Mirror as a Current Amplifier


Find the small-signal current gain, Ai, the input resistance, Rin, the output resistance,
Rout, and the -3dB frequency in Hertz for the current amplifier of Fig. 5.4-3(a) if 10I1 = I2
= 100A and W 2/L2 = 10W1/L1 = 10m/1m. Assume that Cbd1 = 10fF, Cgs1 = Cgs2 =
100fF, and Cgs2 = 50fF.
Solution
Ignoring channel modulation and mismatch effects, the small-signal current gain,
W2/L2
Ai = W /L 10A/A.
1 1
The small-signal input resistance, Rin, is approximately 1/gm1 and is
1
1
Rin
= 46.9S = 21.3k
2KN(1/1)10A
The small-signal output resistance is equal to
1
Rout = NI2 = 250k.
The -3dB frequency is
46.9S
-3dB = 260fF = 180.4x106 radians/sec. f-3dB = 28.7 MHz
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 4 (5/2/04)

Page 5.4-6

Self-Biased Cascode Current Mirror Implementation of a Current Amplifier


VDD

I1

iin

VDD

I2

iout

+
R
M3

M4

vin

vout
M1

M2

Current Amplifier

1
Rin R + g ,
m1

Rout rds2gm4rds4,

and

Fig. 5.4-4

W2/L2
Ai = W /L
1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 4 (5/2/04)

Page 5.4-7

Example 5.4 -2 - Current Amplifier Implemented by the Self-Biased, Cascode


Current Mirror
Assume that I1 and I2 of the self-biased cascode current mirror are 100A. R has
been designed to give a VON of 0.1V. Thus R = 1k. Find the value of Rin, Rout, and Ai if
the W/L ratios of all transistors are 182m/1m.
Solution
The input resistance requires gm1 which is 2110182100 = 2mS
Rin 1000 + 500 = 1.5k
From our knowledge of the cascode configuration, the small signal output resistance
should be
Rout gm4rds4rds2 = (2001S)(250k)(250k) = 125M
Because VDS1 = VDS2, the small-signal current gain is
W2/L2
Ai = W 1/L 1 = 1
Simulation results using the level 1 model for this example give
Rin=1.497k, Rout = 164.7M and Ai = 1.000 A/A.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 4 (5/2/04)

Page 5.4-8

Low-Input Resistance Current Amplifier


To decrease Rin below 1/gm
VDD
requires the use of negative, iin
I1
shunt feedback. Consider
the following example.
M3

VDD
I2

iout

iin

I3

+
vin
- gm1vgs1

M2

M1

i=0

VGG3

rds1

vgs3
+

gm3vgs3

+
vgs1
-

rds3

Fig. 5.4-5

Current Amplifier

Feedback concept:
Input resistance without feedback rds1.
gm1 gm3
Loop gain gds1gds3 assuming that the resistances of I1 and I3 are very large.

Rin(no fb.)
rds1
1
Rin = 1 + Loop gain g r g r
=
m1 ds1 m3 ds3 gm1gm3rds3
Small signal analysis:
iin = gm1vgs1 - gds1vgs3
and vgs3 = -vin vgs1 = vin - (gm3 vgs3rds3) = vin(1+gm3rds3)
1
iin = gm1(1+gm3rds3)vin + gds1vin gm1gm3rds3vin
Rin gm1gm3rds3
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 4 (5/2/04)

Page 5.4-9

Differential-Input, Current Amplifiers


Definitions for the differential-mode, iID, and common-mode, iIC, input currents of the
differential-input current amplifier.
i1
iIC
2

iID

iO

i2 iIC
2
Fig. 5.4-6

i1+i2
iO = AIDiID AICiIC = AID(i1 - i2) AIC 2
Implementations:

VDD

VDD
I

2I

i1
i2

i2
M1 M2

M3 M4

M3

VDD

VDD
M4
iO

iO

M1
i1

i1-i2

VGG1

M2
i2
M6

M5
VGG2

Fig. 5.4-7

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 4 (5/2/04)

Page 5.4-10

Summary
Current amplifiers have a low input resistance, high output resistance, and a defined
output-input current relationship
Input resistances less than 1/gm require feedback
However, all feedback loops have internal poles that cause the benefits of negative
feedback to vanish at high frequencies.
In addition, these feedback loops can have a slow time constant from a pole-zero pair.
Voltage amplifiers using a current amplifier have high values of gain-bandwidth
Current amplifiers are useful at low power supplies and for switched current
applications

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-1

SECTION 5.5 - OUTPUT AMPLIFIERS

VDD
f1(vIN)

i1

f2(vIN)
Buffer
Class A

i2

vIN

iOUT

RL

+
vOUT
-

VSS

Current

i1

t
i2=IQ

iOUT

Class AB
i1

Current

General Considerations of Output Amplifiers


Requirements:
1.) Provide sufficient output power in the form of voltage
or current.
2.) Avoid signal distortion.
3.) Be efficient
4.) Provide protection from abnormal conditions (short
circuit, over temperature, etc.)
Types of Output Amplifiers:
1.) Class A amplifiers
2.) Source followers
3.) Push-pull amplifiers
4.) Substrate BJT amplifiers
5.) Amplifiers using negative
shunt feedback

iOUT
t

i2

Class B

Current

i1
iOUT
t
i2
Fig. 5.5-005

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-2

Class A Amplifiers
Current source load inverter:

VDD

VGG2

IQ

VDD+|VSS|
RL

M2
iOUT

vOUT

iD

RL dominates
as the load line

IQ

iD1
RL
vOUT
M1CL
A Class A circuit has current vIN
IQRL
IQRL
VDD
VSS
flow in the MOSFETs during
Fig. 5.5-1
VSS
the entire period of a
sinusoidal signal.
Characteristics of Class A amplifiers:
Unsymmetrical sinking and sourcing
Linear
Poor efficiency
vOUT(peak)2
vOUT(peak)2
vOUT(peak)
2RL
2RL
PRL

2
Efficiency = PSupply = (VDD-VSS)IQ =
(VDD-VSS) = V DD -V SS
(VDD -VSS) 2RL

Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-3

Optimum Value of Load Resistor


Depending on the value of RL, the signal swing can be symmetrical or asymmetrical.
(This ignores the limitations of the transistor.)
iD1
Smaller RL
VDD+|VSS|
RL

Minimum RL for
maximum swing

IQ
0

VSS

CMOS Analog Circuit Design

IQ R L

IQ R L

Larger RL

vDS1
VDD Fig. 040-03

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-4

Specifying the Performance of a Class A Amplifier


Output resistance:
1
1
rout = g + g = ( + )I
ds1 ds2
1 2 D
Current:
Maximum sinking current is,
K'1W1
IOUT= 2L1 (VDD -VSS - VT1)2 - IQ
Maximum sourcing current is,
K'2W2
+
iOUT
Imax due to RL
IOUT = 2L2 (VDD - VGG2 - |VT2|)2 IQ
Requirements:
Imax due to CL
Want rout << RL
t
|IOUT| > CLSR
vOUT(peak)
|IOUT| >
Imax due to RL
RL
Fig. 5.5-015
The maximum current is determined by both the current required to provide the
necessary slew rate (CL) and to provide a voltage across the load resistor (RL).
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-5

Small-Signal Performance of the Class A Amplifier


Although we have considered the small-signal performance of the Class A amplifier as the
current source load inverter, let us include the influence of the load.
The modified small-signal model:
C1
+
vin

gm1vin

rds1

rds2

RL

C2

+
vout
Fig. 5.5-2

The small-signal voltage gain is:


-gm1
vout
=
vin
gds1+gds2+GL
The small-signal frequency response includes:
A zero at
gm1
z = Cgd1
and a pole at
-(gds1+gds2+GL)
p = Cgd1+Cgd2+Cbd1+Cbd2+CL
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-6

Example 5.5-1 - Design of a Simple Class-A Output Stage


Use Table 3.1-2 to design the W/L ratios of M1 and M2 so that a voltage swing of 2V
and a slew rate of 1 V/s is achieved if RL = 20 k and CL = 1000 pF. Assume VDD =
|VSS| = 3V and VGG2 = 0V. Let L = 2 m and assume that Cgd1 = 100fF.
Solution
Let us first consider the effects of RL and CL.
CLSR = 10-9106 = 1000A
iOUT(peak) = 2V/20k = 100A and
Since the slew rate current is so much larger than the current needed to meet the voltage
specification across RL, we can safely assume that all of the current supplied by the
inverter is available to charge CL.
Using a value of 1 mA,
2(IOUT-+IQ)
W1
4000
3m
=
=

L1 KN(VDD+|VSS| -VTN)2 110(5.3)2 2m


and
2IOUT+
W2
2000
15m
=

L2 = K (V -V
2m
P DD GG2-|VTP|)2 50(2.3)2
The small-signal performance is Av = -8.21 V/V (includes RL = 20k) and rout = 50k
The roots are, zero = gm1/Cgd1 .59GHz and pole = 1/[(RL||rout)CL)] -11.14kHz
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-7

Broadband Harmonic Distortion


The linearity of an amplifier can be characterized by its influence on a pure sinusoidal
input signal.
Assume the input is,
Vin() = Vp sin(t)
The output of an amplifier with distortion will be
Vout() = a1Vp sin (t) + a2Vp sin (2t) +...+ anVp sin(nt)
Harmonic distortion (HD) for the ith harmonic can be defined as the ratio of the
magnitude of the ith harmonic to the magnitude of the fundamental.
For example, second-harmonic distortion would be given as
a2
HD2 = a1
Total harmonic distortion (THD) is defined as the square root of the ratio of the sum of all
of the second and higher harmonics to the magnitude of the first or fundamental harmonic.
Thus, THD can be expressed as
2

[a2 + a3 +...+ an]1/2


THD =
a1
The distortion of the class A amplifier is good for small signals and becomes poor at
maximum output swings because of the nonlinearity of the voltage transfer curve for
large-signal swing
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-8

Class-A Source Follower


N-Channel Source Follower
with current sink bias:
VDD

Voltage transfer curve:


vOUT
VDD
VDD-VON1

VDD

Triode
VDD-VGS1

vIN M1

IQ

VSS
M3

M2
VSS

VSS

iOUT

|VSS|+VON2+VGS1

VGS1

vOUT

VDD-VON1+VGS1

RL
Fig. 040-01

Maximum output voltage swings:


vOUT(min) VSS - VON2 (if RL is large)
vOUT(max) = VDD - VON1 (if vIN > VDD)

vIN

IQRL<|VSS|+VON2
Triode

or
or

|VSS|+VON2
|VSS|

Fig. 040-02

vOUT(min) -IQRL (if RL is small)


vOUT(max) VDD - VGS1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-9

Output Voltage Swing of the Follower


The previous results do not include the bulk effect on VT1 of VGS1.
Therefore,
VT1 = VT01 + [ 2|F| -vBS- 2|F|] VT01+ vSB = VT01+1 vOUT(max)-VSS
vOUT(max)-VSS VDD-VSS-VON1-VT1 = VDD-VSS-VON1-VT01-1 vOUT(max)-VSS
Define vOUT(max)-VSS = vOUT(max)
which gives the quadratic,
vOUT(max)+1 vOUT(max)-(VDD-VSS -VON1-VT01)=0
Solving the quadratic gives,
12 1
12+ 4(VDD-VSS-VON1-VT01)
2
vOUT(max) 4 - 2 1 +4(VDD-VSS-VON1-VT01) +
4
If VDD = 2.5V, N = 0.4V1/2, VTN1= 0.7V, and VON1 = 0.2V, then vOUT(max) = 3.661V
and
vOUT(max) = 3.661-2.5 = 0.8661V

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-10

Maximum Sourcing and Sinking Currents for the Source Follower


Maximum Sourcing Current (into a short circuit):
VDD
VDD
We assume that the transistors are in saturation and
vIN M1
VDD = -VSS = 2.5V , thus
IQ
iOUT
K1W1
VSS
vOUT
IOUT(sourcing) = 2L1 [VDD vOUT VT1]2-IQ
M3

M2

RL

where vIN is assumed to be equal to VDD.


VSS
VSS
Fig. 040-01
If W1/L1 =10 and if vOUT = 0V, then
VT1 = 1.08V IOUT equal to 1.11 mA.
However, as vOUT increases above 0V, the current rapidly decreases.
Maximum Sinking Current:
For the current sink load, the sinking current is whatever the sink is biased to provide.
IOUT(sinking) = IQ

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-11

Efficiency of the Source Follower


iD
Assume that the source follower
vIN
I R = VSS
input can swing to power supply. V
-2VT -VT 0 VT 2VT 3VT 4VT
VDD Q L
SS
Plotting

iD = 2 (vIN - vOUT - VT)2


and
IQRL
IQ
vOUT
vOUT
iD = IQ - R
VSS VSS-VT -3VT -2VT -VT
VT 2VT 3VT VDD-VT VDD
L
Fig. 040-035
Efficiency =
vOUT(peak)2
vOUT(peak)2
vOUT(peak)
PRL
2RL
2RL

2
(VDD-VSS) = V DD -V SS
PSupply = (VDD-VSS)IQ =
(VDD -VSS) 2RL

Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%.
Comments:
Maximum efficiency occurs for the minimum value of RL which gives maximum swing.
Other values of RL result in less efficiency (and smaller signal swings before clipping)
We have ignored the fact that the dynamic Q point cannot travel along the full length of
the load line because of minimum and maximum voltage limits.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-12

Small Signal Performance of the Source Follower


v
Small-signal model:
+ gs1 +
vin

C1
gm1vgs1

+
+
vin
-

vgs1

gmbs1vbs1

rds1

RL

rds1

rds2

C2

+
vout
-

C1
gm1vin

rds2

gm1vout

gmbs1vout

RL

C2

+
vout
-

Fig. 040-04

gm1
gm1RL
Vout
gm1
=

Vin gds1 + gds2 + gm1 + gmbs1+GL gm1 + gmbs1+GL 1 +gm1RL


If VDD = -VSS = 2.5V, Vout = 0V, W1/L1 = 10m/1 m, W2/L2 = 1m/1 m,
and ID = 500 A, then
For the current sink load follower (RL = ):
Vout
Vout
=
0.869V/V,
if
the
bulk
effect
were
ignored,
then
Vin
Vin = 0.963V/V
For a finite load, RL = 1000:
Vout
Vin = 0.512V/V
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-13

Small Signal Performance of the Source Follower - Continued


The output resistance is:
1
Rout = g + g
m1
mbs1 + gds1 + gds2
For the current sink load follower:
Rout = 830
The frequency response of the source follower:
(gm1 + sC1)
Vout(s)
=
Vin(s) gds1 + gds2 + gm1 + gmbs1 + GL + s(C1 + C2)
where
C1 = capacitances connected between the input and output CGS1
C2 = Cbs1 +Cbd2 +Cgd2(or Cgs2) + CL
gm1
gm1+GL
z = - C1
and
p - C1+C2
The presence of a LHP zero leads to the possibility that in most cases the pole and zero
will provide some degree of cancellation leading to a broadband response.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-14

Push-Pull Source Follower


Can both sink and source
current and provide a slightly
lower output resistance.

VDD

VDD
M1

vIN

M6

VGG
VSS
iOUT

VBias

VDD

M5 M1

VSS
iOUT

VSS
vOUT

VBias

vOUT

VDD RL
VDD
RL
M4 M2
Efficiency:
VDD
M2
Depends on how the
vIN
M3
transistors are biased.
VSS
Fig. 060-01
VSS
VSS
Class B - one transistor
has current flow for only 180 of the sinusoid (half period)
vOUT(peak)2
PRL
2RL
vOUT(peak)
Efficiency = P
=
=
2 VDD -VSS
1 2vOUT(peak)
VDD
(VDD -VSS)2

RL

Maximum efficiency occurs when vOUT(peak) =VDD and is 78.5%


Class AB - each transistor has current flow for more than 180 of the sinusoid.
Maximum efficiency is between 25% and 78.5%

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-15

Illustration of Class B and Class AB Push-Pull, Source Follower


Output current and voltage characteristics of the push-pull, source follower (RL = 1k):
2V

vG1

1V

1mA
iD1
0mA

vout

vG1

vG2

0V

0mA
vout

-1V

iD2
-2V

-1mA
-2

0
2
1
Vin(V)
Class B, push-pull, source follower
-1

1mA

iD1

1V

0V
-1V

2V

vG2

iD2

-2V
-2

-1mA

0
2
1
Vin(V)
Class AB, push-pull, source follower
-1

Fig. 060-02

Comments:
Note that vOUT cannot reach the extreme values of VDD and VSS

IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL


For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
Note that there is significant distortion at vIN =0V for the Class B push-pull follower

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-16

Small-Signal Performance of the Push-Pull Follower


Model:
vgs1

+
+
vin

+
vin
-

C1
gm1vgs1

vgs1

gmbs1vbs1

rds1

gm2vgs2 gmbs2vbs2

rds2

RL

C2

+
vout
-

C1
gm1vin

1
RL
g
gm1vout gmbs1vout rds1 gm2vin gm2vout m2gmbs2vout rds2

C2

+
vout
Fig. 060-03

vout
gm1 + gm2
vin = gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL
1
Rout = gds1+gds2+gm1+gmbs1+gm2+gmbs2 (does not include RL)
If VDD = -VSS = 2.5V, Vout = 0V, ID1 = ID2 = 500A, and W/L = 20m/2m, Av = 0.787
(RL=) and Rout = 448.
A zero and pole are located at
-(gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL)
-(gm1+gm2)
p
=
.
z=
C1
C1+C2
These roots will be high-frequency because the associated resistances are small.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-17

Push-Pull, Common Source Amplifiers


Similar to the class A but can operate as class B providing higher efficiency.
VDD
M2
VTR2

iOUT

vIN

vOUT
VTR1
M1CL
VSS

RL
Fig. 060-04

Comments:
The batteries VTR1 and VTR2 are necessary to control the bias current in M1 and M2.
The efficiency is the same as the push-pull, source follower.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-18

Practical Implementation of the Push-Pull, Common Source Amplifier Method 1


VDD
M6

M5

VGG3

M1 M3

iOUT

vIN

vOUT
VGG4

M2 M4
M7

RL

CL

M8
VSS

Fig. 060-05

VGG3 and VGG4 can be used to bias this amplifier in class AB or class B operation.
Note, that the bias current in M6 and M8 is not dependent upon VDD or VSS (assuming
VGG3 and VGG4 are not dependent on VDD and VSS).

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-19

Practical Implementation of the Push-Pull, Common Source Amplifier Method 2


VDD
M5
I=2Ib

M7

Ib

vin+

M1
M3 M4

M8

M9

vin-

M2

M6
Ib

I=2Ib
VSS

M10
Fig. 060-055

In steady-state, the current through M5 and M6 is 2Ib. If W4/L4 = W9/L9 and W3/L3 =
W8/L8, then the currents in M1 and M2 can be determined by the following relationship:
W 1 /L 1
W 2 /L 2
I1 = I2 = Ib W /L = Ib W /L
7
7
10 10
If vin+ goes low, M5 pulls the gates of M1 and M2 high. M4 shuts off causing all of the
current flowing through M5 (2Ib) to flow through M3 shutting off M1. The gate of M2 is
high allowing the buffer to strongly sink current. If vin- goes high, M6 pulls the gates of
M1 and M2 low. As before, this shuts off M2 and turns on M1 allowing strong sourcing.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-20

Illustration of Class B and Class AB Push-Pull, Inverting Amplifier


Output current and voltage characteristics of the push-pull, inverting amplifier (RL =
1k):
vG2

2V

iD1
1V

vG1
iD2

iD1

0V

2mA

2V

1mA

1V

0mA
iD2

-1V

vOUT

-2V
-2V

vG1
iD1

-1V

-2mA

-2V

1mA

iD1

0V

-1mA

2mA

vG2

0mA
iD2
vOUT

iD2

-1mA
-2mA

-2V

0V
1V
2V
vIN
Class AB, push-pull, inverting amplifier. Fig.060-06

-1V

0V
1V
2V
vIN
Class B, push-pull, inverting amplifier.

-1V

Comments:
Note that there is significant distortion at vIN =0V for the Class B inverter
Note that vOUT cannot reach the extreme values of VDD and VSS
IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL
For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-21

What about the use of BJTs?


VDD

VDD
M3

VDD

Q1
iB

M2

vout

vout

iB
Q1

M2
M3

CL
VSS
p-well CMOS

VSS

CL
VSS
n-well CMOS

Fig. 5.5-8A

Comments:
Can use either substrate or lateral BJTs.
Small-signal output resistance is 1/gm which can easily be less than 100.
Unfortunately, only PNP or NPN BJTs are available but not both on a standard CMOS
technology.
In order for the BJT to sink (or source) large currents, the base current, iB, must be
large. Providing large currents as the voltage gets to extreme values is difficult for
MOSFET circuits to accomplish.
If one considers the MOSFET driver, the emitter can only pull to within vBE+VON of the
power supply rails. This value can be 1V or more.
We will consider the BJT as an output stage in more detail in Sec. 7.1.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-22

Use of Negative, Shunt Feedback to Reduce the Output Resistance


Concept:
VDD

Error
Amplifier
vIN

Error
Amplifier

M2
+

iOUT
vOUT

+
CL
M1

RL
Fig. 060-07

VSS

rds1||rds2
Rout = 1+Loop Gain
Comments:
Can achieve output resistances as low as 10.
If the error amplifiers are not balanced, it is difficult to control the quiescent current in
M1 and M2
Great linearity because of the strong feedback
Can be efficient if operated in class B or class AB
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-23

Simple Implementation of Neg., Shunt Feedback to Reduce the Output Resistance


VDD
M2

R1

R2

iOUT

vIN

vOUT
CL
M1

VSS

RL
Fig. 060-08

R1 gm1+gm2
Loop gain R1+R2gds1+gds2+GL

rds1||rds2
R1
gm1+gm2
1+R1+R2gds1+gds2+GL

Let R1 = R2, RL = , IBias = 500A, W1/L1 = 100m/1m and W2/L2 = 200m/1m.


Thus, gm1 = 3.316mS, gm2 = 3.162mS, rds1 = 50k and rds2 = 40k.
50k||40k
22.22k
Rout =
(Rout = 5.42k if RL = 1k)
3316+3162 = 1+0.5(143.9) = 304

1+0.5 25+20

Rout =

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-24

Quasi-Complementary Output Stages


Quasi-complementary connections are used to improve the performance of the NMOS or
PMOS transistor.
Composite connections:
D

Q2

G +

G
VGS

M1

VGS

VSG

ID

ID1
G

- ID
S

S
+
VSG

M1
ID1

Q2
ID
D

ID
D
Fig. 5.5-11

PMOS Equivalent:

NMOS Equivalent:

K P W 1
KPW1
2
ID=(1+2)ID1=(1+2) 2L1 (VGS-VT) ID=(1+2)ID1=(1+2) 2L1 (VSG-VT)2

The composite has an enhanced KN


The composite has an enhanced KP

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 5 (5/2/04)

Page 5.5-25

Summary of Output Amplifiers


The objectives are to provide output power in form of voltage and/or current.
In addition, the output amplifier should be linear and be efficient.
Low output resistance is required to provide power efficiently to a small load resistance.
High source/sink currents are required to provide sufficient output voltage rate due to
large load capacitances.
Types of output amplifiers considered:
Class A amplifier
Source follower
Class B and AB amplifier
Use of BJTs
Negative shunt feedback

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 6 (5/2/04)

Page 5.6-1

SECTION 5.6 - HIGH-GAIN AMPLIFIER ARCHITECTURES


High-Gain Amplifiers used in Negative Feedback Circuits
Consider the general, single-loop, negative feedback circuit:

+
xi
x = either voltage or current
xs
A
xo

- xf
xo
A = xi = high-gain amplifier
F = feedback network
F
Fig. 5.6-1
Closed-loop gain:
xo
A
Af = xs = 1+AF
If AF >> 1, then,
xo 1
Af = xs F
Therefore, to precisely define the closed-loop gain, Af, we only need to make A large and
Af becomes dependent on F which can be determined by passive elements.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 6 (5/2/04)

Page 5.6-2

Types of Amplifiers
The gain of an amplifier is given as
xo
A= x
i
Therefore, since x can be voltage or current, there are four types of amplifiers as
summarized below.
Types of
VoltageVoltageCurrentCurrentAmplifers
controlled,
controlled,
controlled,
controlled,
current-source voltage-source current-source voltage-source
xi variable*
Voltage
Voltage
Current
Current
xo variable
Current
Voltage
Current
Voltage
Desired Ri
Large
Large
Small
Small
Desired Ro
Large
Small
Large
Small
* The xi , xs, and xf must all be the same type of variable, voltage or current.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 6 (5/2/04)

Page 5.6-3

Voltage-Controlled, Current-Source (VCCS) Amplifier


RS

io
+
vi R i
-

vs

Ro

Gmvi

+
vi
-

RL

Differential
Amplifier

VCCS

Second
Stage

io

VCCS

Fig. 5.6-2

io
GmRoRi
=
G
=
M
vs
(Ri + RS)(Ro + RL)
This amplifier is sometimes called an operational transconductance amplifier (OTA).

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 6 (5/2/04)

Page 5.6-4

Voltage-Controlled, Voltage-Source (VCVS) Amplifier


RS
vs

+
vi Ri
-

Ro
Avvi

+
vo
-

RL

+
vi
-

Differential
Amplifier

VCVS

Second
Stage
VCVS

Output
Stage

vo

Fig. 5.6

vo
AvRiRL
=
A
=
V
vs
(RS + Ri)(Ro + RL)
This amplifier is normally called an operational amplifier.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 6 (5/2/04)

Page 5.6-5

Current-Controlled, Current-Source (CCCS) Amplifier


ii
is

RS

io
Ri

Gmvi

Ro

i1
ii

RL

i2

Current
Differential
Amplifier

CCCS

Second
Stage

io

CCCS
Fig. 5.6-4

io
AiRSRo
=
A
=
I
is
(RS + Ri)(Ro + RL)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 6 (5/2/04)

Page 5.6-6

Current-Controlled, Voltage-Source (CCVS) Amplifier


ii
is

RS

+
vi Ri
-

i1
Ro
Rmvi

+
vo

RL

CCVS

ii

i2

Current
Differential
Amplifier

Second
Stage

Output
Stage

vo

CCVS
Fig. 5.6-5

vo
RmRSRL
=
R
=
M
is
(Ri + RS)(Ro + RL)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 5 Section 7 (5/2/04)

Page 5.7-1

SECTION 5.7 - SUMMARY


This chapter presented the following subjects:
5.1 Inverting Amplifiers
Class A (diode load and current sink/source load)
Class AB of B (push-pull)
5.2 Differential Amplifiers
Need good common mode rejection
An excellent input stage for integrated circuit amplifiers
5.3 Cascode Amplifiers
Useful for controlling the poles of an amplifier
5.4 Current Amplifiers
Good for low power supplies
5.5 Output Amplifiers
Minimize the output resistance
Maximize the current sinking/sourcing capability
5.6 High-Gain Architectures
Possible block-level implementations using the blocks of this chapter.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Introduction (5/2/04)

Page 6.0-1

CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS


Chapter Outline
6.1 Design of CMOS Op Amps
6.2 Compensation of Op Amps
6.3 Two-Stage Operational Amplifier Design
6.4 Power Supply Rejection Ratio of the Two-Stage Op Amp
6.5 Cascode Op Amps
6.6 Simulation and Measurement of Op Amps
6.7 Macromodels for Op Amps
6.8 Summary
Goal
Understand the analysis, design, and measurement of simple CMOS op amps
Design Hierarchy
Functional blocks or circuits
Chapter 6

The op amps of this chapter


are unbuffered and are OTAs
but we will use the generic
term op amp.

(Perform a complex function)

Blocks or circuits
(Combination of primitives, independent)

Sub-blocks or subcircuits
(A primitive, not independent)
Fig. 6.0-1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-1

SECTION 6.1 - DESIGN OF CMOS OPERATIONAL AMPLIFIERS


High-Level Viewpoint of an Op Amp
Block diagram of a general, two-stage op amp:
Compensation
Circuitry

v1
v2

+ Differential
Transconductance
Stage

High
Gain
Stage

Bias
Circuitry

vOUT

Output vOUT'
Buffer

Fig. 110-01

Differential transconductance stage:


Forms the input and sometimes provides the differential-to-single ended conversion.
High gain stage:
Provides the voltage gain required by the op amp together with the input stage.
Output buffer:
Used if the op amp must drive a low resistance.
Compensation:
Necessary to keep the op amp stable when resistive negative feedback is applied.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-2

Ideal Op Amp
Symbol:
i1
+
v1

VDD

+
i2 vi
- -

+
v2
- -

+
VSS vOUT = Av(v1-v2)
Fig. 110-02

Null port:
If the differential gain of the op amp is large enough then input terminal pair becomes a
null port.
A null port is a pair of terminals where the voltage is zero and the current is zero.
I.e.,
v1 - v2 = vi = 0
and
i1 = 0 and i2 = 0
Therefore, ideal op amps can be analyzed by assuming the differential input voltage is
zero and that no current flows into or out of the differential inputs.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-3

General Configuration of the Op Amp as a Voltage Amplifier


R1

- R2

+
vinn

vinp

+
v2
v1
- -

+
vout
Fig. 110-03

Noniverting voltage amplifier:


vinn = 0

R1+R2
vout = R1 vinp

Inverting voltage amplifier:


vinp = 0

CMOS Analog Circuit Design

R2
vout = -R vinn

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-4

Example 6.1-1 - Simplified Analysis of an Op Amp Circuit


The circuit shown below is an inverting voltage amplifier using an op amp. Find the
voltage transfer function, vout/vin.
R1 i1

i2 R2

+ ii
vi
-

+
vin
-

+
vout

Virtual Ground

Fig. 110-04

Solution
If Av , then vi 0 because of the negative feedback path through R2.
(The op amp with fb. makes its input terminal voltages equal.)
vi = 0 and ii = 0
Note that the null port becomes the familiar virtual ground if one of the op amp input
terminals is on ground. If this is the case, then we can write that
vin
vout
and
i2 = R2
i1 = R1
vout
R2
Since, ii = 0, then i1 + i2 = 0 giving the desired result as vin = - R1 .
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-5

Linear and Static Characterization of the Op Amp


A model for a nonideal op amp that includes some of the linear, static nonidealities:
v1

CMRR

Ricm

IB2

en2

v2

*
VOS

in2

v1

Cid

Rid

Rout

vout

Ideal Op Amp
Ricm

IB1
Fig. 110-05

where
Rid = differential input resistance
Cid = differential input capacitance
Ricm = common mode input resistance
VOS = input-offset voltage
IB1 and IB2 = differential input-bias currents
IOS = input-offset current (IOS = IB1-IB2)
CMRR = common-mode rejection ratio
e2n = voltage-noise spectral density (mean-square volts/Hertz)
i2n = current-noise spectral density (mean-square amps/Hertz)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-6

Linear and Dynamic Characteristics of the Op Amp


Differential and common-mode frequency response:
V (s)+V (s)
2
1
Vout(s) = Av(s)[V1(s) - V2(s)] Ac(s)

Differential-frequency response:
Av0
Av0 p1p2p3
=
Av(s) = s
s
s

(s -p1)(s -p2)(s -p3)

1
1
1

p
p
p

1
2
3

where p1, p2, p3, are the poles of the differential-frequency response (ignoring zeros).
|Av(j)| dB
Asymptotic
Magnitude

20log10(Av0)

Actual
Magnitude

0dB

-6dB/oct.
GB
2 3

1
-12dB/oct.
-18dB/oct.

Fig. 110-06

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-7

Other Characteristics of the Op Amp


Power supply rejection ratio (PSRR):
Vo/Vin (Vdd = 0)
VDD
PSRR = VOUT Av(s) = Vo/Vdd (Vin = 0)
Input common mode range (ICMR):
ICMR = the voltage range over which the input common-mode signal can vary
without influence the differential performance
Slew rate (SR):
SR = output voltage rate limit of the op amp
Settling time (Ts):
vOUT(t)
Upper Tolerance

Final Value +
vIN

vOUT

Final Value

Final Value -

Lower Tolerance

Settling Time
0

CMOS Analog Circuit Design

Ts

Fig. 110-07

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-8

Classification of CMOS Op Amps


Categorization of op amps:
Hierarchy

Conversion
Voltage
to Current

Classic Differential
Amplifier

Current
to Voltage

Differential-to-single ended
Load (Current Mirror)

Voltage
to Current

Transconductance
Grounded Gate

Modified Differential
Amplifier

Source/Sink
Current Loads

Current
Stage

Transconductance
Grounded Source

Second
Voltage
Stage

Class B
(Push-Pull)

Class A (Source
or Sink Load)

Current
to Voltage

MOS Diode
Load

First
Voltage
Stage

Table 110-01

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-9

Two-Stage CMOS Op Amp


Classical two-stage CMOS op amp broken into voltage-to-current and current-to-voltage
stages:
VDD
M3 M4
M6
-

vin

vin
+

VBias

vout

M1 M2

vout

M7

M5

VSS
VI

CMOS Analog Circuit Design

I V

VI

IV

Fig. 6.1-8

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-10

Folded Cascode CMOS Op Amp


Folded cascode CMOS op amp broken into stages.
VDD
VBias

M3
M10 M11

+
vin
-

M1

M2
M8
M6

M7

VBias
M4

M5

M9

vout
vin

vout

VBias

V I

I I

VSS
IV

Fig. 6.1-9

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-11

Design of CMOS Op Amps


Steps:
1.) Choosing or creating the basic structure of the op amp.
This step is results in a schematic showing the transistors and their interconnections.
This diagram does not change throughout the remainder of the design unless the
specifications cannot be met, then a new or modified structure must be developed.
2.) Selection of the dc currents and transistor sizes.
Most of the effort of design is in this category.
Simulators are used to aid the designer in this phase. The general performance of the
circuit should be known a priori.
3.) Physical implementation of the design.
Layout of the transistors
Floorplanning the connections, pin-outs, power supply buses and grounds
Extraction of the physical parasitics and resimulation
Verification that the layout is a physical representation of the circuit.
4.) Fabrication
5.) Measurement
Verification of the specifications
Modification of the design as necessary
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-12

Boundary Conditions and Requirements for CMOS Op Amps


Boundary conditions:
1. Process specification (VT, K', Cox, etc.)
2. Supply voltage and range
3. Supply current and range
4. Operating temperature and range
Requirements:
1. Gain
2. Gain bandwidth
3. Settling time
4. Slew rate
5. Common-mode input range, ICMR
6. Common-mode rejection ratio, CMRR
7. Power-supply rejection ratio, PSRR
8. Output-voltage swing
9. Output resistance
10. Offset
11. Noise
12. Layout area
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-13

Specifications for a Typical Unbuffered CMOS Op Amp


Boundary Conditions
Process Specification
Supply Voltage
Supply Current
Temperature Range
Specifications
Gain
Gainbandwidth
Settling Time
Slew Rate
Input CMR
CMRR
PSRR
Output Swing
Output Resistance
Offset
Noise
Layout Area
CMOS Analog Circuit Design

Requirement
See Tables 3.1-1 and 3.1-2
2.5 V 10%
100 A
0 to 70C
Value
70 dB
5 MHz
1 sec
5 V/sec
1.5 V
60 dB
60 dB
1.5 V
N/A, capacitive load only
10 mV
100nV/ Hz at 1KHz
10,000 min. channel length2
P.E. Allen - 2004

Chapter 6 Section 1 (5/2/04)

Page 6.1-14

Some Practical Thoughts on Op Amp Design


1.) Decide upon a suitable topology.
Experience is a great help
The topology should be the one capable of meeting most of the specifications
Try to avoid inventing a new topology but start with an existing topology
2.) Determine the type of compensation needed to meet the specifications.
Consider the load and stability requirements
Use some form of Miller compensation or a self-compensated approach (shown
later)
3.) Design dc currents and device sizes for proper dc, ac, and transient performance.
This begins with hand calculations based upon approximate design equations.
Compensation components are also sized in this step of the procedure.
After each device is sized by hand, a circuit simulator is used to fine tune the design
Two basic steps of design:
1.) First-cut - this step is to use hand calculations to propose a design that has
potential of satisfying the specifications. Design robustness is developed in this step.
2.) Optimization - this step uses the computer to refine and optimize the design.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-1

SECTION 6.2 - COMPENSATION OF OP AMPS


Compensation
Objective
Objective of compensation is to achieve stable operation when negative feedback is
applied around the op amp.
Types of Compensation
1. Miller - Use of a capacitor feeding back around a high-gain, inverting
stage.
Miller capacitor only
Miller capacitor with an unity-gain buffer to block the forward path through the
compensation capacitor. Can eliminate the RHP zero.
Miller with a nulling resistor. Similar to Miller but with an added series resistance
to gain control over the RHP zero.
2. Self compensating - Load capacitor compensates the op amp (later).
3. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be
less than unity.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-2

Single-Loop, Negative Feedback Systems


F(s)
Block diagram:
A(s) = differential-mode voltage gain of the
op amp
Vin(s)
A(s)
+
F(s) = feedback transfer function from the
output of op amp back to the input.
Definitions:
Open-loop gain = L(s) = -A(s)F(s)
Vout(s)
A(s)
Closed-loop gain = V (s) = 1+A(s)F(s)
in
Stability Requirements:
The requirements for stability for a single-loop, negative feedback system is,
|A(j0)F(j0)| = |L(j0)| < 1
where 0 is defined as
Arg[A(j0)F(j0)] = Arg[L(j0)] = 0
Another convenient way to express this requirement is
Arg[A(j0dB)F(j0dB)] = Arg[L(j0dB)] > 0
where 0dB is defined as
|A(j0dB)F(j0dB)| = |L(j0dB)| = 1

Vout(s)
Fig. 120-01

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-3

|A(j)F(j)|

Illustration of the Stability Requirement using Bode Plots


-20dB/decade

-40dB/decade

Arg[-A(j)F(j)]

0dB
180
135
90
45

0dB
Fig. Fig. 120-02
Frequency (rads/sec.)
A measure of stability is given by the phase when |A(j)F(j)| = 1. This phase is called
phase margin.
Phase margin = M = Arg[-A(j0dB)F(j0dB)] = Arg[L(j0dB)]
0

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-4

Why Do We Want Good Stability?


Consider the step response of second-order system which closely models the closed-loop
gain of the op amp.
1.4
45
50
55

1.2
1.0

60
65
70

vout(t) 0.8
Av0
0.6

0.4
0.2
0
0

5
10
ot = nt (sec.)

15 Fig. 120-03

A good step response is one that quickly reaches its final value.
Therefore, we see that phase margin should be at least 45 and preferably 60 or larger.
(A rule of thumb for satisfactory stability is that there should be less than three rings.)
Note that good stability is not necessarily the quickest risetime.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-5

Uncompensated Frequency Response of Two-Stage Op Amps


Two-Stage Op Amps:
VDD

M3 M4

VCC

Q3

M6

Q4

Q6

vout
vin
+

M1 M2

+
VBias
-

vin
+

+
VBias
-

M7

M5

Q1

vout

Q2

Q7

Q5

VSS

VEE

Fig. 120-04

Small-Signal Model:
D1, D3 (C1, C3)
+
g v
gm1vin
v1 m2 in
R1
C1
2
2

D2, D4 (C2, C4)

gm4v1

R2

C2

D6, D7 (C6, C7)


+
v2
- gm6v2

R3

C3

+
vout
Fig. 120-05

Note that this model neglects the base-collector and gate-drain capacitances for purposes
of simplification.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-6

Uncompensated Frequency Response of Two-Stage Op Amps - Continued


For the MOS two-stage op amp:
1
1
R2 = rds2|| rds4
and R3 = rds6|| rds7
R1 g ||rds3||rds1 g
m3
m3
C1 = Cgs3+Cgs4+Cbd1+Cbd3
C2 = Cgs6+Cbd2+Cbd4
and C3 = CL +Cbd6+Cbd7
For the BJT two-stage op amp:
1
1
R1 = gm3 ||r3||r4||ro1||ro3gm3 R2 = r6|| ro2|| ro4 r6 and R3 = ro6|| ro7
C1 = C3+C4+Ccs1+Ccs3
C2 = C6+Ccs2+Ccs4
and C3 = CL+Ccs6+Ccs7
Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives,
gm1vin

R2

C2

+
v2
- gm6v2

R3

C3

+
vout

gm1Vin

RI

CI

+
VI
- gmIIVI

RII

CII

+
Vout
Fig. 120-06

The locations for the two poles are given by the following equations
1
1
p1 = RICI and p2 = RIICII
where RI (RII) is the resistance to ground seen from the output of the first (second) stage
and CI (CII) is the capacitance to ground seen from the output of the first (second) stage.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-7

Uncompensated Frequency Response of an Op Amp


Avd(0) dB

|A(j)|

-20dB/decade

GB
log10()

0dB
Phase Shift

-40dB/decade
-45/decade

Arg[-A(j)]

180
135

-45/decade

90
45
0

|p1'|

|p2'| 0dB

log10()
Fig. 120-07

If we assume that F(s) = 1 (this is the worst case for stability considerations), then the
above plot is the same as the loop gain.
Note that the phase margin is much less than 45.
Therefore, the op amp must be compensated before using it in a closed-loop
configuration.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-8

Miller Compensation of the Two-Stage Op Amp


VDD
M3

VCC

M4
Q3

M6

CM
Cc
vin
+

M1

Cc

M2

vin
+

CII

Q1

vout

Q2
CII

CI

+
VBias
-

M7

M5

Q6

vout

CI

+
VBias
-

Q4
CM

Q7

Q5

VSS

VEE

Fig. 120-08

The various capacitors are:


Cc = accomplishes the Miller compensation
CM = capacitance associated with the first-stage mirror (mirror pole)
CI = output capacitance to ground of the first-stage
CII = output capacitance to ground of the second-stage

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-9

Compensated Two-Stage, Small-Signal Frequency Response Model Simplified


Use the CMOS op amp to illustrate:
1.) Assume that gm3 >> gds3 + gds1
gm3
2.) Assume that CM >> GB
Therefore,
v1
-gm1vin
2

1
rds1||rds3 CM gm3

v2
gm2vin
2

gm4v1 C1 rds2||rds4 gm6v2

v2
+
vin gm1vin
-

CI

Cc

rds2||rds4

rds6||rds7 CL

+
vout
-

Cc

gm6v2

rds6||rds7

CII

+
vout
Fig. 120-09

Same circuit holds for the BJT op amp with different component relationships.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-10

General Two-Stage Frequency Response Analysis


Cc
where
V2
+
+
gmI = gm1 = gm2, RI = rds2||rds4, CI = C1
Vin gmIVin
Vout
RI gmIIV2
RII CII
and
CI
Fig.120-10
gmII = gm6, RII = rds6||rds7, CII = C2 = CL
Nodal Equations:
-gmIVin = [GI + s(CI + Cc)]V2 - [sCc]Vout and 0 = [gmII - sCc]V2 + [GII + sCII + sCc]Vout
Solving using Cramers rule gives,
Vout(s)
gmI(gmII - sCc)
=
Vin(s) GIGII+s [GII(CI+CII)+GI(CII+Cc)+gmIICc]+s2[CICII+CcCI+CcCII]
Ao[1 - s (Cc/gmII)]
= 1+s [R (C +C )+R (C +C )+g R R C ]+s2[R R (C C +C C +C C )]
I
I
II
II
2
c
mII 1 II c
I II
I II
c I
c II
where, Ao = gmIgmIIRIRII

1
s s
1 s2
s
s2
In general, D(s) = 1-p 1-p = 1-s p + p +p p D(s) 1-p + p p , if |p2|>>|p1|
1
2
2
1 2
1
1 2

1
gmII
-1
-1
p1 = RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc gmIIR1RIICc , z = Cc
p2 =

-[RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc]
-gmIICc
-gmII

CICII+CcCI+CcCII CII , CII > Cc > CI


RIRII(CICII+CcCI+CcCII)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-11

Summary of Results for Miller Compensation of the Two-Stage Op Amp


There are three roots of importance:
1.) Right-half plane zero:
gmII gm6
z1= Cc = Cc
This root is very undesirable- it boosts the magnitude while decreasing the phase.
2.) Dominant left-half plane pole (the Miller pole):
-(gds2+gds4)(gds6+gds7)
-1
p1 gmIIRIRIICc =
gm6Cc
This root accomplishes the desired compensation.
3.) Left-half plane output pole:
-gmII -gm6
p2 CII CL
This pole must be unity-gainbandwidth or the phase margin will not be satisfied.
Root locus plot of the Miller compensation:
Closed-loop poles, Cc0 j
Open-loop poles
Cc=0
p2
CMOS Analog Circuit Design

p2'

p1'

p1

z1

Fig. 120-11

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-12

|A(j)F(j)|

Compensated Open-Loop Frequency Response of the Two-Stage Op Amp


Avd(0) dB

Uncompensated
-20dB/decade
Compensated
GB
log10()

0dB
Phase Shift

-40dB/decade

Arg[-A(j)F(j)|

Uncompensated
180
-45/decade

135

-45/decade

90
45
0

Compensated
|p1|

Phase
Margin
log10()

No phase margin
|p2'| |p2|
|p1'|

Fig. 120-12

Note that the unity-gainbandwidth, GB, is


gmI gm1 gm2
1
=
= C = C
mIIRIRIICc Cc
c
c

GB = Avd(0)|p1| = (gmIgmIIRIRII)g
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-13

Conceptually, where do these roots come from?


1.) The Miller pole:

VDD
Cc

1
|p1| R (g R C )
I m6 II c

RII
vout

RI
M6
vI

gm6RIICc
Fig. 120-13

2.) The left-half plane output pole:

VDD
Cc

gm6
|p2| CII

VDD
RII

RII
vout

M6

CII

vout

1
GBCc 0

M6

CII
Fig. 120-14

3.) Right-half plane zero (One source of zeros is from


multiple paths from the input to output):
g

m6

-R
1

II sC
-gm6RII(1/sCc)

R
c

II

vout = RII + 1/sCc v + RII + 1/sCc v = RII + 1/sCc v


where v = v = v.
CMOS Analog Circuit Design

VDD
Cc

RII
vout

v''

M6
v'
Fig. 120-15

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-14

Influence of the Mirror Pole


Up to this point, we have neglected the influence of the pole, p3, associated with the
current mirror of the input stage. A small-signal model for the input stage that includes
C3 is shown below:
gm1Vin
2

i3
1
rds1 rds3 gm3

gm2Vin
2
C3

i3

+
Vo1
rds2

rds4

Fig. 120-16

The transfer function from the input to the output voltage of the first stage, Vo1(s), can be
written as

sC3 + 2gm3
gm3+gds1+gds3
-gm1
-gm1
Vo1(s)

Vin(s) = 2(gds2+gds4) gm3+ gds1+gds3+sC3 + 1 2(gds2+gds4) sC3 + gm3


We see that there is a pole and a zero given as
gm3
2gm3
p3 = - C
and z3 = - C
3
3

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-15

Influence of the Mirror Pole Continued


Fortunately, the presence of the zero tends to negate the effect of the pole. Generally,
the pole and zero due to C3 is greater than GB and will have very little influence on the
stability of the two-stage op amp.
The plot shown illustrates
the case where these roots are
less than GB and even then
they have little effect on
stability.
In fact, they actually
increase the phase margin
slightly because GB is
decreased.

F=1

Avd(0) dB

-6dB/octave
Cc 0
GB
log10()

0dB
Phase Shift

Magnitude influence of C3

0
45
90
135
180
CMOS Analog Circuit Design

Cc = 0

Cc 0

Cc = 0
-45/decade
Cc 0
-45/decade
Phase margi
ignoring C3

Cc = 0
Phase margin due to C3
|p1|

-12dB/octave

|p3||z3||p2|

log10()
Fig. 120-17
P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-16

Summary of the Conditions for Stability of the Two-Stage Op Amp


Unity-gainbandwith is given as:
gmI
gm1

1
1
GB = Av(0)|p1| = (gmIgmIIRIRII)g R R C = C = (gm1gm2R1R2)g R R C = C
c
c
mII I II c
m2 1 2 c
The requirement for 45 phase margin is:



180 - Arg[AF] = 180 - tan-1|p1| - tan-1|p2| - tan-1 z = 45
Let = GB and assume that z 10GB, therefore we get,
GB
GB
GB
180 - tan-1|p1| - tan-1|p2| - tan-1 z = 45
GB
GB
135 tan-1(Av(0)) + tan-1|p2| + tan-1(0.1) = 90 + tan-1|p2| + 5.7
GB
GB
39.3 tan-1|p2| |p | = 0.818 |p2| 1.22GB
2
The requirement for 60 phase margin:
|p2| 2.2GB if z 10GB
If 60 phase margin is required, then the following relationships apply:
gm6 10gm1
gm6 2.2gm1
>

g
>
10g
and
Cc > 0.22C2
m6
m1
Cc
Cc
C2 > Cc
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-17

Controlling the Right-Half Plane Zero


Why is the RHP zero a problem?
Because it boosts the magnitude but lags the phase - the worst possible combination for
stability.
j
j3
j2

j1

180 > 1 > 2 > 3


3
2
1

z1

Fig. 430-01

Solution of the problem:


If a zero is caused by two paths to the output, then eliminate one of the paths.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-18

Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor
Model:
Cc
+1

VI

Cc

The transfer
+
V
function is given
Vout
CI
v
in gmIvin
RI
OUT
Inverting
RII
High-Gain
gmIIVI
by the following
Stage
equation,
Vo(s)
(gmI)(gmII)(RI)(RII)
=
Vin(s) 1 + s[RICI + RIICII + RICc + gmIIRIRIICc] + s2[RIRIICII(CI + Cc)]
Using the technique as before to approximate p1 and p2 results in the following
1
1
p1 RICI + RIICII + RICc + gmIIRIRIICc gmIIRIRIICc
and
gmIICc
p2 CII(CI + Cc)
Comments:
Poles are approximately what they were before with the zero removed.
For 45 phase margin, |p2| must be greater than GB
For 60 phase margin, |p2| must be greater than 1.73GB

CII

+
Vout
-

Fig. 430-02

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-19

Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero
Assume that the unity-gain buffer has an output resistance of Ro.
Model:
Cc

Ro

Inverting
High-Gain
Stage

+1

VI
vOUT

+
Vin gmIvin
-

CI

RI

Cc
Ro

Vout
Ro
gmIIVI

RII

CII

+
Vout
Fig. 430-03

It can be shown that if the output resistance of the buffer amplifier, Ro, is not neglected
that another pole occurs at,
1
p4 Ro[CICc/(CI + Cc)]
and a LHP zero at
1
z2 RoCc
Closer examination shows that if a resistor, called a nulling resistor, is placed in series
with Cc that the RHP zero can be eliminated or moved to the LHP.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-20

Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)
Cc

Rz
VI

Inverting
High-Gain
Stage

vOUT

+
Vin gmIvin
-

CI

Cc

RI

Rz

gmIIVI

RII

CII

+
Vout
Fig. 430-04

Nodal equations:

VI
sCc
gmIVin + RI + sCIVI + 1 + sCcRz (VI Vout) = 0

Vo
sCc

gmIIVI + RII + sCIIVout + 1 + sCcRz (Vout VI) = 0

Solution:
Vout(s) a{1 s[(Cc/gmII) RzCc]}
Vin(s) =
1 + bs + cs2 + ds3
where
a = gmIgmIIRIRII
b = (CII + Cc)RII + (CI + Cc)RI + gmIIRIRIICc + RzCc
c = [RIRII(CICII + CcCI + CcCII) + RzCc(RICI + RIICII)]
d = RIRIIRzCICIICc

W,J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of CA., Santa Barbara.
CMOS Analog Circuit Design
P.E. Allen - 2004
Chapter 6 Section 2 (5/2/04)

Page 6.2-21

Use of Nulling Resistor to Eliminate the RHP - Continued


If Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots of the
above transfer function can be approximated as
1
1
p1 (1 + gmIIRII)RICc gmIIRIIRICc
gmIICc
gmII
p2 CICII + CcCI + CcCII CII
1
p4 = RzCI
and
1
z1 = Cc(1/gmII Rz)
Note that the zero can be placed anywhere on the real axis.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-22

Conceptual Illustration of the Nulling Resistor Approach


VDD
Cc

Rz

RII
Vout

V''

M6
V'
Fig. Fig. 430-05

The output voltage, Vout, can be written as

gm6
1

-gm6RIIRz + sC
-R
g
R
+
II m6 z sCc - 1
RII
c

V
Vout =
1 V +
1 V =
1
RII + Rz + sCc
RII + Rz + sCc
RII + Rz + sCc
when V = V = V.
Setting the numerator equal to zero and assuming gm6 = gmII gives,
1
z1 = Cc(1/gmII Rz)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-23

A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p2
We desire that z1 = p2 in terms of the previous notation.
Therefore,
gmII
1
j
=
CII
Cc(1/gmII Rz)

-p
z
-p
-p
1
Fig. 430-06
1
4
2
The value of Rz can be found as
Cc + CII
Rz = Cc (1/gmII)

With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz) . For unity-gain
stability, all that is required is that
gmI
Av(0)
|p4| > Av(0)|p1| = gmIIRIIRICc = C
c
and
(1/RzCI) > (gmI/Cc) = GB
Substituting Rz into the above inequality and assuming CII >> Cc results in
gmI
Cc >
gmII CICII
This procedure gives excellent stability for a fixed value of CII ( CL).
Unfortunately, as CL changes, p2 changes and the zero must be readjusted to cancel p2.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-24

Increasing the Magnitude of the Output Pole


The magnitude of the output pole , p2, can be increased by introducing gain in the Miller
capacitor feedback path. For example,
VDD

M12
Cc

M11

M7
vOUT

Cgd6
+
Iin

R1

VBias

M8

Cc

rds8

+
V1
Vs8
- gm8Vs8 - gm6V1

R2

C2

+
Vout
-

M6
Cgd6
M10

M9
VSS

Fig. 6.2-15B

Iin

R1

V1
- gm8Vs8

Cc
+

gm8

Vs8
- gm6V1

R2

+
Vout
-

C2

The resistors R1 and R2 are defined as


1
1
R1 = g + g + g
and
R
=
2
+
g
ds2
ds4
ds9
ds6 gds7
where transistors M2 and M4 are the output transistors of the first stage.
Nodal equations:
gm8sCc

gm8sCc

Iin = G1V1-gm8Vs8 = G1V1-gm8 + sCc Vout and 0 = gm6V1+ G2+sC2+ gm8+sCcVout

B.K. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. of Solid-State Circuits, Vol. SC-18,
No. 6 (Dec. 1983) pp. 629-633.
CMOS Analog Circuit Design
P.E. Allen - 2004
Chapter 6 Section 2 (5/2/04)

Page 6.2-25

Increasing the Magnitude of the Output Pole - Continued


Solving for the transfer function Vout/Iin gives,

sCc

1
+

gm8
Vout -gm6

Cc

CcC2
C
C
g
Iin G1G2
C
c
2
m6
c

1 + s gm8 + G2 + G2 + G1G2 + s2 gm8G2

Using the approximate method of solving for the roots of the denominator gives
-1
-6
p1 = Cc Cc C2 gm6Cc g r 2C
m6 ds c
gm8 + G2 + G2 + G1G2

and
gm6rds2Cc
gm8rds2G2 gm6 gm8rds
6
p2
=
C =
CcC2
6
3 |p2|

2
gm8G2
where all the various channel resistance have been assumed to equal rds and p2 is the
output pole for normal Miller compensation.
Result:
Dominant pole is approximately the same and the output pole is increased by gmrds.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-26

Increasing the Magnitude of the Output Pole - Continued


In addition there is a LHP zero at -gm8/sCc and a RHP zero due to Cgd6 (shown dashed
in the model on Page 6.2-20) at gm6/Cgd6.
Roots are:
j

-gm6gm8rds -gm8
Cc
3C2

-1
gm6rdsCc

gm6
Cgd6

Fig. 6.2-16A

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-27

Concept Behind the Increasing of the Magnitude of the Output Pole


VDD

VDD
Cc

gm8rds8
3

rds7

rds7

vout

vout

1
GBCc 0

M8
M6

CII

M6

CII

Fig. Fig. 430-08

3
3
Rout = rds7||gm6gm8rds8 gm6gm8rds8

Therefore, the output pole is approximately,


gm6gm8rds8
|p2|
3CII

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-28

Identification of Poles from a Schematic


1.) Most poles are equal to the reciprocal product of the resistance from a node to ground
and the capacitance connected to that node.
2.) Exceptions (generally due to feedback):
a.) Negative feedback:
C3
C2

C2
-A

R1

-A
R1

C1

C1 C3(1+A)

RootID01

b.) Positive feedback (A<1):


C3
C2

C2
+A

R1

+A
R1

C1

C1 C3(1-A)

RootID02

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-29

Identification of Zeros from a Schematic


1.) Zeros arise from poles in
the feedback path.

F(s)

vin
+

vout
A(s)
RootID03
s

A(s)p +1
1

Vout
A(s)
A(s)
1

, then Vin = 1+A(s)F(s) =


If F(s) = s
1 =s
1+A(s) s
p1 +1+ A(s)
p1 +1
+1
p1
2.) Zeros are also created by two paths
VDD
from the input to the output and one of
more of the paths is frequency dependent.
Cc

RII
vout

v''

M6
v'
Fig. 120-15

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-30

Feedforward Compensation
Use two parallel paths to achieve a LHP zero for lead compensation purposes.
RHP Zero

LHP Zero

Cc

LHP Zero using Follower

Cc

-A

Vi

Vout

Inverting
High Gain
Amplifier

CII

Cc

Vi

Vout

Inverting
High Gain
Amplifier

RII

CII

Vi

Vout

+1

RII

Cc
+
Vi
-

+
gmIIVi

CII

RII

Vout
-

Fig.430-09

ACc
Vout(s)
s + gmII/ACc

Vin(s) Cc + CII s + 1/[RII(Cc + CII)]


To use the LHP zero for compensation, a compromise must be observed.
Placing the zero below GB will lead to boosting of the loop gain that could deteriorate
the phase margin.
Placing the zero above GB will have less influence on the leading phase caused by the
zero.
Note that a source follower is a good candidate for the use of feedforward compensation.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-31

Self-Compensated Op Amps
Self compensation occurs when the load capacitor is the compensation capacitor (can
never be unstable for resistive feedback)
|dB|
Rout(must be large)

+
Gm
-

vin
+

Av(0) dB
-20dB/dec.

vout
Rout

Fig. 430-10

CL

Increasing CL
0dB

Voltage gain:
vout
vin = Av(0) = GmRout
Dominant pole:
-1
p1 = RoutCL
Unity-gainbandwidth:
Gm
GB = Av(0)|p1| = C
L
Stability:
Large load capacitors simply reduce GB but the phase is still 90 at GB.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 2 (5/2/04)

Page 6.2-32

Slew Rate of a Two-Stage CMOS Op Amp


Remember that slew rate occurs when currents flowing in a capacitor become limited and
is given as
dvC
Ilim = C dt where vC is the voltage across the capacitor C.
VDD

M3

VDD

M4

C c I5

M6
I6 ICL

M3

M4

C c I5

vout
vin>>0
+

M1

Assume a
virtural
ground

M2

CL
I7

vin<<0
+

M1

I5
+
VBias
-

Assume a
virtural
ground

M2

M6
I6=0
ICL

vout

CL
I7

I5

M7

M5

+
VBias
-

VSS
Positive Slew Rate

I5 I6-I5-I7 I5
, CL = Cc because I6>>I5
Cc

SR+ = min

M7

M5
VSS
Negative Slew Rate

Fig. 140-05

I5 I7-I5 I5
,
= C if I7>>I5.
c
Cc CL

SR- = min

Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew rate
of the two-stage op amp should be,
I5
SR = C
c
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-1

SECTION 6.3 - TWO-STAGE OP AMP DESIGN


Unbuffered, Two-Stage CMOS Op Amp
VDD
M6
M3

M4

Cc
vout

vin
+

M1

+
VBias
-

CL

M2

M7

M5
VSS

Fig. 6.3-1

Notation:
Wi
Si = Li = W/L of the ith transistor

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-2

DC Balance Conditions for the Two-Stage Op Amp


For best performance, keep all transistors in
VDD
saturation.
+
VSG6 +
VSG4
M4 is the only transistor that cannot be forced
M6
into saturation by internal connections or
I6
M3
M4 I4
Cc
external voltages.
vout
Therefore, we develop conditions to force M4 to
CL
M1
M2
be in saturation.
vin
I7
1.) First assume that VSG4 = VSG6. This will +
I5
cause proper mirroring in the M3-M4 mirror.
M7
+
M5
VBias
Also, the gate and drain of M4 are at the same
potential so that M4 is guaranteed to be in
VSS
Fig. 6.3-1A
saturation.
S6

2.) If VSG4 = VSG6, then I6 = S4I4

S7
S7

3.) However, I7 = S5I5 = S5 (2I4)

S6 2S7
called the balance conditions
4.) For balance, I6 must equal I7
S4 = S5
5.) So if the balance conditions are satisfied, then VDG4 = 0 and M4 is saturated.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-3

Design Relationships for the Two-Stage Op Amp


I5
Slew rate SR = Cc (Assuming I7 >>I5 and CL > Cc)
gm1
2gm1
First-stage gain Av1 = gds2 + gds4 = I5(2 + 4)
gm6
gm6
Second-stage gain Av2 = gds6 + gds7 = I6(6 + 7)
gm1
Gain-bandwidth GB = Cc
gm6
Output pole p2 = CL
gm6
RHP zero z1 = Cc
60 phase margin requires that gm6 = 2.2gm2(CL/Cc) if all other roots are 10GB.
I5
Positive ICMR Vin(max) = VDD 3 |VT03|(max) + VT1(min))
I5
Negative ICMR Vin(min) = VSS + 1 + VT1(max) + VDS5(sat)
Saturation voltageVDS(sat) =
CMOS Analog Circuit Design

2IDS

(all transistors are saturated)


P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-4

Op Amp Specifications
The following design procedure assumes that specifications for the following parameters
are given.
1. Gain at dc, Av(0)
Max. ICMR
and/or p3
2. Gain-bandwidth, GB
VDD
Vout(max)
+
+
V
3. Phase margin (or settling time)
SG6
VSG4
M6
gm6 or
4. Input common-mode range, ICMR
M3
M4
Proper Mirroring
Cc
I6
5. Load Capacitance, CL
VSG4=VSG6
g
GB = m1
vout
Cc
6. Slew-rate, SR
CL
Cc 0.2CL
vin M1
M2
7. Output voltage swing
(PM = 60)
+
8. Power dissipation, Pdiss
I5
Min. ICMR
I5 = SRCc
Vout(min)

+
VBias
-

M5

M7
VSS

Fig. 160-02

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-5

Unbuffered Op Amp Design Procedure


This design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), input
common mode range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR),
settling time (Ts), output voltage swing (Vout(max) and Vout(min)), and power dissipation
(Pdiss) are given. Choose the smallest device length which will keep the channel
modulation parameter constant and give good matching for current mirrors.
1. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60 phase
margin we use the following relationship. This assumes that z 10GB.
Cc > 0.22CL
2. Determine the minimum value for the tail current (I5) from the largest of the two
values.
VDD + |VSS|

I5 = SR .Cc
or
I5 10
2 .Ts
3. Design for S3 from the maximum input voltage specification.
I5
S3 = K'3[VDD Vin(max) |VT03|(max) + VT1(min)]2
4. Verify that the pole of M3 due to Cgs3 and Cgs4 (= 0.67W3L3Cox) will not be dominant by
assuming it to be greater than 10 GB
gm3
2Cgs3 > 10GB.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-6

Unbuffered Op Amp Design Procedure - Continued


5. Design for S1 (S2) to achieve the desired GB.
gm22
.
gm1 = GB Cc S2 = K'2I5
6. Design for S5 from the minimum input voltage. First calculate VDS5(sat) then find S5.
I5
2I5
VDS5(sat) = Vin(min) VSS 1 VT1(max) 100 mV S5 = K'5[VDS5(sat)]2
7. Find S6 by letting the second pole (p2) be equal to 2.2 times GB and assuming that
VSG4 = VSG6.
2KP'S6I6
S6I6 S6
gm6
gm6
=
=

S
=
gm6 = 2.2gm2(CL/Cc) and gm4 =
6 gm4S4
S4I4 S4
2KP'S4I4
8. Calculate I6 from
gm62
I6 = 2K'6S6
Check to make sure that S6 satisfies the Vout(max) requirement and adjust as necessary.
9. Design S7 to achieve the desired current ratios between I5 and I6.
S7 = (I6/I5)S5
(Check the minimum output voltage requirements)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-7

Unbuffered Op Amp Design Procedure - Continued


10. Check gain and power dissipation specifications.
2gm2gm6
Av = I5(2 + 3)I6(6 + 7)
Pdiss = (I5 + I6)(VDD + |VSS|)
11. If the gain specification is not met, then the currents, I5 and I6, can be decreased or
the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked
to insure that they are satisfied. If the power dissipation is too high, then one can only
reduce the currents I5 and I6. Reduction of currents will probably necessitate increase of
some of the W/L ratios in order to satisfy input and output swings.
12. Simulate the circuit to check to see that all specifications are met.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-8

Example 6.3-1 - Design of a Two-Stage Op Amp


Using the material and device parameters given in Tables 3.1-1 and 3.1-2, design an
amplifier similar to that shown in Fig. 6.3-1 that meets the following specifications.
Assume the channel length is to be 1m and the load capacitor is CL = 10pF.
VSS = -2.5V
Av > 3000V/V
VDD = 2.5V
GB = 5MHz
SR > 10V/s
60 phase margin
Vout range = 2V
ICMR = -1 to 2V
Pdiss 2mW
Solution
1.) The first step is to calculate the minimum value of the compensation capacitor Cc,
Cc > (2.2/10)(10 pF) = 2.2 pF
2.) Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I5.
I5 = (3x10-12)(10x106) = 30 A
3.) Next calculate (W/L)3 using ICMR requirements.
30x10-6

(W/L)3 = (W/L)4 = 15
(W/L)3 = (50x10-6)[2.5 2 .85 + 0.55]2 = 15

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-9

Example 6.3-1 - Continued


4.) Now we can check the value of the mirror pole, p3, to make sure that it is in fact
greater than 10GB. Assume the Cox = 0.4fF/m2. The mirror pole can be found as
-gm3
- 2KpS3I3
p3 2Cgs3 = 2(0.667)W3L3Cox = 2.81x109(rads/sec)
or 448 MHz. Thus, p3, is not of concern in this design because p3 >> 10GB.
5.) The next step in the design is to calculate gm1 to get
gm1 = (5x106)(2)(3x10-12) = 94.25S
Therefore, (W/L)1 is
gm12
(94.25)2
(W/L)1 = (W/L)2 = 2KNI1 = 211015 = 2.79 3.0 (W/L)1 = (W/L)2 = 3
6.) Next calculate VDS5,
30x10-6
VDS5 = (1) (2.5) 110x10-63 - .85 = 0.35V
Using VDS5 calculate (W/L)5 from the saturation relationship.
2(30x10-6)

(W/L)5 = 4.5
(W/L)5 = (110x10-6)(0.35)2 = 4.49 4.5

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-10

Example 6.3-1 - Continued


7.) For 60 phase margin, we know that
gm6 10gm1 942.5S
Assuming that gm6 = 942.5S and knowing that gm4 = 150S, we calculate (W/L)6 as
942.5x10-6
(W/L)6 = 15 (150x10-6) = 94.25 94
8.) Calculate I6 using the small-signal gm expression:
(942.5x10-6)2
I6 = (2)(50x10-6)(94.25) = 94.5A 95A
If we calculate (W/L)6 based on Vout(max), the value is approximately 15. Since 94
exceeds the specification and maintains better phase margin, we will stay with (W/L)6 =
94 and I6 = 95A.
With I6 = 95A the power dissipation is
Pdiss = 5V(30A+95A) = 0.625mW.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-11

Example 6.3-1 - Continued


9.) Finally, calculate (W/L)7
95x10-6
(W/L)7 = 4.5 30x10-6 = 14.25 14

(W/L)7 = 14
Let us check the Vout(min) specification although the W/L of M7 is so large that this is
probably not necessary. The value of Vout(min) is
295
11014 = 0.351V
which is less than required. At this point, the first-cut design is complete.
10.) Now check to see that the gain specification has been met
(92.45x10-6)(942.5x10-6)
Av = 15x10-6(.04 + .05)95x10-6(.04 + .05) = 7,697V/V
which exceeds the specifications by a factor of two. .An easy way to achieve more gain
would be to increase the W and L values by a factor of two which because of the
decreased value of would multiply the above gain by a factor of 20.
11.) The final step in the hand design is to establish true electrical widths and lengths
based upon L and W variations. In this example L will be due to lateral diffusion only.
Unless otherwise noted, W will not be taken into account. All dimensions will be
rounded to integer values. Assume that L = 0.2m. Therefore, we have
Vout(min) = VDS7(sat) =

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-12

Example 6.3-1 - Continued


W1 = W2 = 3(1 0.4) = 1.8 m 2m
W3 = W4 = 15(1 0.4) = 9m
W5 = 4.5(1 - 0.4) = 2.7m 3m
W6 = 94(1 - 0.4) = 56.4m 56m
W7 = 14(1 - 0.4) = 8.4 8m
The figure below shows the results of the first-cut design. The W/L ratios shown do not
account for the lateral diffusion discussed above. The next phase requires simulation.
15m
1m

M3

VDD = 2.5V
M4
15m
1m

M6

Cc = 3pF
M1

30A

vin
+

4.5m
1m

3m
1m

3m
1m

vout

M2

CL =
10pF

95A

30A

14m
1m

4.5m
M5 1m
VSS = -2.5V

M8

94m
1m

M7
Fig. 6.3-3

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-13

Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op Amp
Circuit:
VDD

M11
VA

M3

M4 V
B
CM

M10
VC

vin-

M6
M8

Cc

vout

vin+
M1

M2

CL

IBias

M12

M9

M5
VSS

M7
Fig. 160-03

We saw earlier that the roots were:


gm2
gm1
gm6
p2 = CL
p1 = AvCc = AvCc
1
1
p4 = RzCI
z1 = RzCc Cc/gm6
where Av = gm1gm6RIRII.
(Note that p4 is the pole resulting from the nulling resistor compensation technique.)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-14

Design of the Nulling Resistor (M8)


In order to place the zero on top of the second pole (p2), the following relationship must
hold
1 CL + Cc Cc+CL
1
Rz = gm6 Cc = C
c 2KPS6I6

The resistor, Rz, is realized by the transistor M8 which is operating in the active region
because the dc current through it is zero. Therefore, Rz, can be written as
vDS8
1

Rz = iD8
= KPS8(VSG8-|VTP|)
VDS8=0
The bias circuit is designed so that voltage VA is equal to VB.
W 11
I10 W 6

|VGS10| |VT| = |VGS8| |VT| VSG11 = VSG6


L =I L
11
6 6
In the saturation region
2(I10)
|VGS10| |VT| =
K'P(W10/L10) = |VGS8| |VT|
KPS10 1
S10
1
=
Rz = K S
S8
2I10
2KPI10
P 8
W 8

S10S6I6
Cc

Equating the two expressions for Rz gives L8 = CL + Cc


I10

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-15

Example 6.3-2 - RHP Zero Compensation


Use results of Ex. 6.3-1 and design compensation circuitry so that the RHP zero is
moved from the RHP to the LHP and placed on top of the output pole p2. Use device data
given in Ex. 6.3-1.
Solution
The task at hand is the design of transistors M8, M9, M10, M11, and bias current I10.
The first step in this design is to establish the bias components. In order to set VA equal to
VB, thenVSG11 must equal VSG6. Therefore,
S11 = (I11/I6)S6
Choose I11 = I10 = I9 = 15A which gives S11 = (15A/95A)94 = 14.8 15.
The aspect ratio of M10 is essentially a free parameter, and will be set equal to 1.
There must be sufficient supply voltage to support the sum of VSG11, VSG10, and VDS9.
The ratio of I10/I5 determines the (W/L) of M9. This ratio is
(W/L)9 = (I10/I5)(W/L)5 = (15/30)(4.5) = 2.25 2
Now (W/L)8 is determined to be

3pF
(W/L)8 = 3pF+10pF

CMOS Analog Circuit Design

19495A
= 5.63 6
15A

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-16

Example 6.3-2 - Continued


It is worthwhile to check that the RHP zero has been moved on top of p2. To do this,
first calculate the value of Rz. VSG8 must first be determined. It is equal to VSG10, which is
VSG10 =

2I10
KPS10 + |VTP| =

215
501 + 0.7 = 1.474V

Next determine Rz.


1
106
Rz = KPS8(VSG10-|VTP|) = 505.63(1.474-.7) = 4.590k
The location of z1 is calculated as
1
6
z1 =
3x10-12 = -94.46x10 rads/sec
(4.590 x 103)(3x10-12) 942.5x10-6
The output pole, p2, is
942.5x10-6
p2 = 10x10-12 = -94.25x106 rads/sec
Thus, we see that for all practical purposes, the output pole is canceled by the zero
that has been moved from the RHP to the LHP.
The results of this design are summarized below.
W9 = 2 m W10 = 1 m W11 = 15 m
W8 = 6 m
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-17

An Alternate Form of Nulling Resistor


VDD

To cancel p2,
Cc+CL
1
z1 = p2 Rz = gm6ACC = gm6B
Which gives
C

gm6B = gm6ACc+CL

M11

M3

M6
vout
vin
+

M1

M2

M6B

In the previous example,


+
M5
VBias
gm6A = 942.5S, Cc = 3pF
and CL = 10pF.
Choose I6B = 10A to get
2KPW6BI6B Cc 2KPW6AID6
gm6ACc
= Cc+CL
gm6B = Cc + CL
L6B
L6A
or
W6B 3 2 I6A W6A 3 2 95
L6B = 13 I6B L6A = 13 10(94) = 47.6 W6B = 48m

CMOS Analog Circuit Design

M10

M4

CL

Cc
M8

VSS

M9

M7
Fig. 6.3-4A

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-18

Programmability of the Two-Stage Op Amp


The following relationships depend on the bias
current, Ibias, in the following manner and allow for
programmability after fabrication.
M3
1
Av(0) = gmIgmIIRIRII IBias
gmI
M1
GB = C IBias
vin
c
+
Pdiss = (VDD+|VSS|)(1+K1+K2)IBias Ibias
IBias
K1IBias
SR = Cc IBias
1
1
Rout = 2K2IBias IBias
103
|p1|
Pdiss and SR
IBias2
1
102
1.5
|p1| = gmIIRIRIICc I IBias
Bias
101
GB and z
gmII
100
|z| = C IBias
c
10-1
Ao and Rout
Illustration of the Ibias dependence

VDD
M6
M4
vout

M2

K2IBias
K1IBias
M5
VSS

M7
Fig. 6.3-04D

10-2

10-3
1

10
IBias

100

IBias(ref)

Fig. 160-05

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-19

Simulation of the Electrical Design


Area of source or drain = AS = AD = W[L1 + L2 + L3]
where
L1 = Minimum allowable distance between the contact in the S/D and the
polysilicon (5m)
L2 = Width of a minimum size contact (5m)
L3 = Minimum allowable distance from contact in S/D to edge of S/D (5m)
AS = AD = Wx15m
Perimeter of the source or drain = PD = PS = 2W + 2(L1+L2+L3)
PD = PS = 2W + 30m
Illustration:
L3 L2 L1

L1 L2 L3

Poly
Diffusion

Diffusion

L
CMOS Analog Circuit Design

Fig. 6.3-5
P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-20

;;;;;
;;;
;
;;;;
;
;;
;
;;
;
;;;;
;;;
; ;
;;;;
;
;;
;
;;
;;;;;
;;;;;;;;;;;;
;;;;;;

5-to-1 Current Mirror with Different Physical Performances


Input
Output

Metal 1
Poly
Diffusion
Contacts

Ground

(a)

Input
Output

Ground
(b)
Figure 6.3-6 The layout of a 5-to-1 current mirror. (a) Layout which minimizes
area at the sacrifice of matching. (b) Layout which optimizes matching.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-21

;;;;
;;;;
;;;;
;;

1-to-1.5 Transistor Matching

;;;;
;;;;
;;;;
;;
;
2

;;
;;
;;
;

Drain 2
Gate 2
Source 2

Drain 1
Gate 1
Source 1

Metal 2
Metal 1
Poly
Diffusion Contacts
Figure 6.3-7 The layout of two transistors with a 1.5 to 1 matching using
centroid geometry to improve matching.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-22

Reduction of Parasitics
The major objective of good layout is to minimize the parasitics that influence the design.
Typical parasitics include:
Capacitors to ac ground
Series resistance
Capacitive parasitics is minimized by minimizing area and maximizing the distance
between the conductor and ac ground.
Resistance parasitics are minimized by using wide busses and keeping the bus length
short.
For example:
At 2m/square, a metal run of 1000m and 2m wide will have 1 of resistance.
At 1 mA this amounts to a 1 mV drop which could easily be greater than the least
significant bit of an analog-digital converter. (For example, a 10 bit ADC with VREF =
1V has an LSB of 1mV)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-23

Technique for Reducing the Overlap Capacitance


Square Donut Transistor:
Source

;;
;;
;;
;;
Source

Metal 1
Poly

Gate
Source

Drain

Source

Diffusion
Contacts

Figure 6.3-8 Reduction of Cgd by a donut shaped transistor.

Note: Can get more W/L in less area with the above geometry.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 3 (5/2/04)

Page 6.3-24

Chip Voltage Bias Distribution Scheme


VDD

M7
M5

M8

M6A

M9

M6

VPBias1

Bandgap
Voltage,
V
- BG

M10

VDD

M5A
VPBias2

R4

M11

M13

M12

M14

R2A

R3

Master
Voltage
Reference
Circuit

M4

M3
M1

M2
IPTAT

Q2

Q1

R2

R1

Q3

Slave
Bias
Circuit

M15
M16
R1A

M3A

IREF

VNBias2

M1A

Rext

VNBias1

xn

M4A

M2A

Location of reference voltage


Remote portion of chip
Figure 6.3-9 Generation of a reference voltage which is distributed on the chip
as a current to slave bias circuits.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-1

SECTION 6.4 - PSRR OF THE TWO-STAGE OP AMP


What is PSRR?

Vdd

Av(Vdd=0)
PSRR = A (V =0)
dd

in

Vin

V2

V1

VDD
Vout
Vss

How do you calculate PSRR?


You could calculate Av and Add and divide,
however

VSS
Fig.180-01

Vdd
V2
V2

V1

Av(V1-V2)

VDD
Vout
Vss

V1
VSS

Vout
AddVdd
Fig. 180-02

Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout Vout(1+Av) = AddVdd


Vout Add Add
1
V
=

=
(Good for frequencies up to GB)
dd 1+Av Av PSRR+
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-2

Positive PSRR of the Two-Stage Op Amp


Vdd

M3

Cc

M4

VDD

M6

M2

CII

CI

M5

gm6(V1-Vdd)

I3
rds1

rds2

I3

gm1V5

gm2V5

Vout
Vdd

M1

1
gm3

rds4

Vdd - I3 gm1Vout
gm3

rds5
+

M7

V5 -

V1

rds6

Cc
+

rds7

CII

CI

Vout

VBias

V5 0

gm6(V1-Vdd)

VSS

rds4
Vdd

gds1Vdd
rds2

Fig. 180-03

gm1Vout
+
V1
-

rds6

Cc
CI

CII

+
Vout

rds7

The nodal equations are:


(gds1 + gds4)Vdd = (gds2 + gds4 + sCc + sCI)V1 (gm1 + sCc)Vout
(gm6 + gds6)Vdd = (gm6 sCc)V1 + (gds6 + gds7 + sCc + sCII)Vout
Using the generic notation the nodal equations are:
GIVdd = (GI + sCc + sCI)V1 (gmI + sCc)Vout
(gmII + gds6)Vdd = (gmII sCc)V1 + (GII + sCc + sCII)Vout
whereGI = gds1 + gds4 = gds2 + gds4, GII = gds6 + gds7, gmI = gm1 = gm2 and gmII = gm6
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-3

Positive PSRR of the Two-Stage Op Amp - Continued


Using Cramers rule to solve for the transfer function,Vout/Vdd, and inverting the transfer
function gives the following result.
Vdd s2[CcCI+CICII + CIICc]+ s[GI(Cc+CII) + GII(Cc+CI) + Cc(gmII gmI)] + GIGII+gmIgmII
Vout =
s[Cc(gmII+GI+gds6) + CI(gmII + gds6)] + GIgds6
We may solve for the approximate roots of numerator as
sCc s(CcCI+CICII+CcCII)
+ 1
gmII Cc
Vdd gmIgmII gmI + 1

PSRR+ = Vout GIgds6

sg
C
mII
c

+ 1
G g

I
ds6

where gmII > gmI and that all transconductances are larger than the channel
conductances.

s
s
sCc sCII


+
1
+
1
+
1
+
1
g

GIIAvo GB
|p2|
Vdd gmIgmII gmI
mII

+
PSRR = V
=Gg
=

gds6 sGIIAvo
sgmIICc
out I ds6
GIgds6 + 1
+ 1
g
ds6GB

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-4

Positive PSRR of the Two-Stage Op Amp - Continued


GIIAv0

|PSRR+(j)| dB

gds6

gds6GB
GIIAv0

GB |p2|

Fig. 180-04

At approximately the dominant pole, the PSRR falls off with a -20dB/decade slope and
degrades the higher frequency PSRR + of the two-stage op amp.
Using the values of Example 6.3-1 we get:
PSRR+(0) = 68.8dB,

z1 = -5MHz, z2 = -15MHz

and p1 = -906Hz

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-5

Concept of the PSRR+ for the Two-Stage Op Amp


Vdd

M3

M1

Cc

M4

M2

Vout

CII

CI

M5

M7

Vout
Vdd

VDD

M6

Cc
Vdd

Rout

Vout

0dB

1
RoutCc

Other sources
of PSRR+
besides Cc

VBias
VSS
Fig. 180-05

1.) The M7 current sink causes VSG6 to act like a battery.


2.) Therefore, Vdd couples from the source to gate of M6.
3.) The path to the output is through any capacitance from gate to drain of M6.
Conclusion:
The Miller capacitor Cc couples the positive power supply ripple directly to the output.
Must reduce or eliminate Cc.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-6

Negative PSRR of the Two-Stage Op Amp withVBias Grounded


M3

M4

Cc

VDD

M6
Vout

Cc
M1

M2
M5

VBias

CII

CI

M7 V
ss

VBias grounded

gmIVout

RI

CI

gmIIV1

CII

RII

gm7Vss

+
Vout
-

VSS
Fig. 180-06

Nodal equations for VBias grounded:


0 = (GI + sCc+sCI)V1 - (gmI+sCc)Vo
gm7Vss = (gMII-sCc)V1 + (GII+sCc+sCII)Vo
Solving for Vout/Vss and inverting gives
Vss s2[CcCI+CICII+CIICc]+s[GI(Cc+CII)+GII(Cc+CI)+Cc(gmII gmI)]+GIGII+gmIgmII
Vout =
[s(Cc+CI)+GI]gm7

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-7

Negative PSRR of the Two-Stage Op Amp withVBias Grounded - Continued


Again using techniques described previously, we may solve for the approximate roots as
sCc s(CcCI+CICII+CcCII)
+ 1
gmII Cc
Vss gmIgmII gmI + 1

PSRR- = Vout GIgm7

s(C
+
C
)
c
I

GI + 1

This equation can be rewritten approximately as

s
sCc sCII
s

+
1
+1
+
1
+
1

GB
|p
|
g
g

G
A

Vss gmIgmII mI
mII

II v0

PSRR- = Vout GIgm7


=

g
g
sC
s
c
m7
mI

+1
G + 1

G
GB
I
I

Comments:
PSRR- zeros = PSRR + zeros
DC gain Second-stage gain,
PSRR- pole (Second-stage gain) x (PSRR+ pole)
Assuming the values of Ex. 6.3-1 gives a gain of 23.7 dB and a pole -147 kHz. The dc
value of PSRR- is very poor for this case, however, this case can be avoided by correctly
implementing VBias which we consider next.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-8

Negative PSRR of the Two-Stage Op Amp withVBias Connected to VSS


M3

M1

M4

M2

Cc

VDD

M6
Vout

CII

CI

Cc
Vss

M5
VBias

M7 V
ss

rds5
gmIVout

CI

RI

+
V1 gmIIV1
-

Cgd7

rds7

CII

rds6

+
Vout
-

VSS

VBias connected to VSS

Fig. 180-07

If the value of VBias is independent of Vss, then the model shown results. The nodal
equations for this model are
0 = (GI + sCc + sCI)V1 - (gmI + sCc)Vout
and
(gds7 + sCgd7)Vss = (gmII - sCc)V1 + (GII + sCc + sCII + sCgd7)Vout
Again, solving for Vout/Vss and inverting gives
Vss s2[CcCI+CICII+CIICc+CICgd7+CcCgd7]+s[GI(Cc+CII+Cgd7)+GII(Cc+CI)+Cc(gmIIgmI)]+GIGII+gmIgmII
Vout =
(sCgd7+gds7)(s(CI+Cc)+GI)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-9

Negative PSRR of the Two-Stage Op Amp withVBias Connected to VSS - Continued


Assuming that gmII > gmI and solving for the approximate roots of both the numerator
and denominator gives
sCc s(CcCI+CICII+CcCII)
+ 1
gmII Cc
Vss gmIgmII gmI + 1

PSRR- = Vout GIgds7

sC
s(C
+C
)
gd7
I
c

+1 G
+ 1
g

I
ds7

This equation can be rewritten as



s
s


+
1
+1
Vss GIIAv0 GB |p2|

PSRR- = V g

sCc

out ds7 sCgd7


gds7 +1 GI + 1
Comments:
DC gain has been increased by the ratio of GII to gds7
Two poles instead of one, however the pole at -gds7/Cgd7 is large and can be ignored.
Using the values of Ex. 6.3-1 and assume that Cds7 = 10fF, gives,
PSRR-(0) = 76.7dB
CMOS Analog Circuit Design

and

Poles at -71.2kHz and -149MHz


P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-10

Frequency Response of the Negative PSRR of the Two-Stage Op Amp with VBias
Connected to VSS

;;
;;
;;
;;
;;

GIIAv0
gds7

|PSRR-(j)| dB

Invalid
region
of
analysis

GI
Cc

GB |p2|

Fig. 180-08

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-11

Approximate Model for Negative PSRR with VBias Connected to Ground


M3

M1

M4

M2
M5

VBias

Cc

VDD

M6
Vout

VBias

CII

CI

M5 or M7

iss

Vss
VSS

M7 V
ss
VSS

VBias grounded

Fig. 180-09

Path through the input stage is not important


as long as the CMRR is high.
Path through the output stage:
vout issZout = gm7ZoutVss
Vout

V = gm7Zout = gm7Rout sR C +1
ss
out out

Vout
Vss

20 to
40dB

0dB
CMOS Analog Circuit Design

1
RoutCout

Fig.180-10
P.E. Allen - 2004

Chapter 6 Section 4 (5/2/04)

Page 6.4-12

Approximate Model for Negative PSRR with VBias Connected to VSS


M3

M1

M4

M2

Cc

Vout

rds7
CII

CI

M7

VBias

vout

Vss

rds7
Vss

M5

What is Zout?
Vt
Zout = I
t

VDD

M6

Zout

Path through Cgd7


is negligible

VSS

VBias connected to VSS

Fig. 180-11

gmIVt
It = gmIIV1 = g GI+sCI+sCc

GI+s(CI+Cc)
Thus, Zout = gmIgMII

mII

It

Cc CII+Cgd7

gmIVout

CI

RI

+
V1 gmIIV1
-

rds6||rds7

+
Vout
-

Vt

Fig.180-12

rds7
1+
Vss
Zout s(Cc+CI) + GI+gmIgmIIrds7
-GI
V
= 1 =
Pole at C +C
s(Cc+CI) + GI
out
c I
The two-stage op amp will never have good PSRR because of the Miller compensation.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-1

SECTION 6.5 - CASCODE OP AMPS


Why Cascode Op Amps?
Control of the frequency behavior
Can get more gain by increasing the output resistance of a stage
In the past section, PSRR of the two-stage op amp was insufficient for many applications
A two-stage op amp can become unstable for large load capacitors (if nulling resistor is
not used)
We will see in future sections that the cascode op amp leads to wider ICMR and/or
smaller power supply requirements
Where Should the Cascode Technique be Used?
First stage Good noise performance
Requires level translation to second stage
Degrades the Miller compensation
Second stage Self compensating
Increases the efficiency of the Miller compensation
Increases PSRR

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-2

Use of Cascoding in the First Stage of the Two-Stage Op Amp


M3

VDD
M4

VDD

Implementation of the
floating voltage VBias.

M3

M4
MB3

MB4

MC3
MC3

MC4

MC4
vo1

vo1

R
MB5

MC2

MC1
M1

M2

VBias

+v

vin
+ 2

in

2+
VBias
-

MC1
M1

M5
VSS

+v

+
VBias

MB1

MC2
M2
MB2

in

2+
VBias
-

vin
+ 2

M5
VSS

Fig. 6.5-1

Rout of the first stage is RI (gmC2rdsC2rds2)||(gmC4rdsC4rds4)


vo1
Voltage gain = v = gm1RI
[The gain is increased by approximately 0.5(gMCrdsC)]
in
As a single stage op amp, the compensation capacitor becomes the load capacitor.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-3

Example 6.5-1 Single-Stage, Cascode Op Amp Performance


Assume that all W/L ratios are 10 m/1 m, and that IDS1 = IDS2 = 50 A of single
stage op amp. Find the voltage gain of this op amp and the value of CI if GB = 10 MHz.
Use the model parameters of Table 3.1-2.
Solution
The device transconductances are
gm1 = gm2 = gmI = 331.7 S
gmC2 = 331.7S
gmC4 = 223.6 S.
The output resistance of the NMOS and PMOS devices is 0.5 M and 0.4 M,
respectively.
RI = 25 M
Av(0) = 8290 V/V.
For a unity-gain bandwidth of 10 MHz, the value of CI is 5.28 pF.
What happens if a 100pF capacitor is attached to this op amp?
GB goes from 10MHz to 0.53MHz.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-4

Two-Stage Op Amp with a Cascoded First-Stage


VDD
M3

M4

MT2
MB3

MB4

MC3

M6

MC4

MT1
Cc

vo1

vout

MB5

MC1
M1
+v

+
VBias

MB1

MC2
M2
MB2

vin
+ 2

in

2-

M7

M5

+
VBias
-

VSS

Fig. 6.5-2

MT1 and MT2 are required for level shifting from


the first-stage to the second.

The PSRR+ is improved by the presence of MT1


p3 p2
Internal loop pole at the gate of M6 may cause the
Miller compensation to fail.
The voltage gain of this op amp could easily be 100,000V/V

p1

z1

Fig. 6.5-2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-5

Two-Stage Op Amp with a Cascode Second-Stage


VDD
M6
M3

M4

Rz
vin
+

M1

+
VBias
-

M2

VBP
Cc

MC6

VBN

MC7

vout

CL

M7

M5
VSS

Fig. 6.5-3

Av = gmIgmIIRIRII
where gmI = gm1 = gm2,
gmII = gm6,
1
2
RI = gds2 + gds4 = (2 + 4)ID5 and RII = (gmC6rdsC6rds6)||(gmC7rdsC7rds7)
Comments:
The second-stage gain has greatly increased improving the Miller compensation
The overall gain is approximately (gmrds)3 or very large
Output pole, p2, is approximately the same if Cc is constant
The zero RHP is the same if Cc is constant
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-6

A Balanced, Two-Stage Op Amp using a Cascode Output Stage


gm1gm8 vin
VDD
gm2gm6 vin

vout = g
+ g
R
m3 2
m4 2 II

M6

M4

M15

M8

M3

vin
+

M1

M2

M14

R1
M9

M7
R2

vout

M12
M10

M5
+
VBias
-

CL

M11

M13
VSS

Fig. 6.5-4

m1 gm2
= 2 + 2 kvin RII = gm1kRII vin
where
RII = (gm7rds7rds6)||(gm12rds12rds11)
and
gm8 gm6
k = gm3 = gm4

This op amp is balanced because the drain-to-ground loads for M1 and M2 are identical.
TABLE 1 - Design Relationships for Balanced, Cascode Output Stage Op Amp.
gm1gm8
1 gm1gm8 gm2gm6
Iout
GB = gm3CL
Av = 2 gm3 + gm4 RII
Slew rate = CL

I5 1/2
I5 1/2
Vin(max) = VDD 3 |VTO3|(max) +VT1(min)
Vin(min) = VSS + VDS5 + 1 + VT1(min)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-7

Example 6.5-2 Design of Balanced, Cascoded Output Stage Op Amp


The balanced, cascoded output stage op amp is a useful alternative to the two-stage
op amp. Its design will be illustrated by this example. The pertinent design equations for
the op amp were given above. The specifications of the design are as follows:
Slew rate = 5 V/s with a 50 pF load
VDD = VSS = 2.5 V
GB = 10 MHz with a 25 pF load Av 5000
Input CMR = 1V to +1.5 V
Output swing = 1.5 V
Use the parameters of Table 3.1-2 and let all device lengths be 1 m.
Solution
While numerous approaches can be taken, we shall follow one based on the above
specifications. The steps will be numbered to help illustrate the procedure.
1.) The first step will be to find the maximum source/sink current. This is found from the
slew rate.
Isource/Isink = CL slew rate = 50 pF(5 V/s) = 250 A
2.) Next some W/L constraints based on the maximum output source/sink current are
developed. Under dynamic conditions, all of I5 will flow in M4; thus we can write
Max. Iout(source) = (S6/S4)I5 and Max. Iout(sink) = (S8/S3)I5
The maximum output sinking current is equal to the maximum output sourcing current if
S3 = S4, S6 = S8, and S10 = S11
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-8

Example 6.5-2 - Continued


3.) Choose I5 as 100 A. This current (which can be changed later) gives
S6 = 2.5S4 and S8 = 2.5S3
Note that S8 could equal S3 if S11 = 2.5S10. This would minimize the power dissipation.
4.) Next design for 1.5 V output capability. We shall assume that the output must
source or sink the 250A at the peak values of output. First consider the negative output
peak. Since there is 1 V difference between VSS and the minimum output, let VDS11(sat) =
VDS12(sat) = 0.5 V (we continue to ignore the bulk effects). Under the maximum negative
peak assume that I11 = I12 = 250 A. Therefore
2I11
2I12
500 A
=
=
(110 A/V2)S11
K'NS11
K'NS12
which gives S11 = S12 = 18.2 and S9 = S10 = 18.2. For the positive peak, we get
0.5 =

2I6
2I7
500 A
=
=
K'PS6
K'PS7
(50 A/V2)S6
which gives S6 = S7 = S8 = 40 and S3 = S4 = (40/2.5) = 16.
5.) Next the values of R1 and R2 are designed. For the resistor of the self-biased cascode
we can write
R1 = VDS12(sat)/250A = 2k and R2 = VSD7(sat)/250A = 2k
0.5 =

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-9

Example 6.5-2 - Continued


Using this value of R1 (R2) will cause M11 to slightly be in the active region under
quiescent conditions. One could redesign R1 to avoid this but the minimum output
voltage under maximum sinking current would not be realized.
6.) Now we must consider the possibility of conflict among the specifications.
First consider the input CMR. S3 has already been designed as 16. Using ICMR
relationship, we find that S3 should be at least 4.1. A larger value of S3 will give a higher
value of Vin(max) so that we continue to use S3 = 16 which gives Vin(max) = 1.95V.
Next, check to see if the larger W/L causes a pole below the gainbandwidth.
Assuming a Cox of 0.4fF/m2 gives the first-stage pole of
-gm3
- 2KPS3I3
p3 = Cgs3+Cgs8 = (0.667)(W3L3+W8L8)Cox = 33.15x109 rads/sec or 5.275GHz
which is much greater than 10GB.
7.) Next we find gm1 (gm2). There are two ways of calculating gm1.
(a.) The first is from the Av specification. The gain is
Av = (gm1/2gm4)(gm6 + gm8) RII
Note, a current gain of k could be introduced by making S6/S4 (S8/S3 = S11/S3) equal to k.
2KPS6I6
gm6 gm11
=
=
gm4 gm3
2KPS4I4 = k
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-10

Example 6.5-2 - Continued


Calculating the various transconductances we get gm4 = 282.4 S, gm6 = gm7 = gm8 = 707
S, gm11 = gm12 = 707 S, rds6 = rd7 = 0.16 M, and rds11 = rds12 = 0.2 M. Assuming
that the gain Av must be greater than 5000 and k = 2.5 gives gm1 > 72.43 S.
(b.) The second method of finding gm1 is from the GB specifications. Multiplying the gain
by the dominant pole (1/CIIRII) gives
gm1(gm6 + gm8)
GB =
2gm4CL
Assuming that CL= 25 pF and using the specified GB gives gm1 = 251 S.
Since this is greater than 72.43S, we choose gm1 = gm2 = 251S. Knowing I5 gives S1 =
S2 = 5.7 6.
8.) The next step is to check that S1 and S2 are large enough to meet the 1V input CMR
specification. Use the saturation formula we find that VDS5 is 0.261 V. This gives S5 =
26.7 27. The gain becomes Av = 6,925V/V and GB = 10 MHz for a 25 pF load. We shall
assume that exceeding the specifications in this area is not detrimental to the performance
of the op amp.
9.) With S5 = 7 then we can design S13 from the relationship
I13
125A
S13 = I S5 = 100A 27 = 33.75 34
5
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-11

Example 6.5-2 - Continued


10.) Finally we need to design the value of VBias, which can be done with the values of S5
and I5 known. However, M5 is usually biased from a current source flowing into a MOS
diode in parallel with the gate-source of M5. The value of the current source compared
with I5 would define the W/L ratio of the MOS diode.
Table 2 summarizes the values of W/L that resulted from this design procedure. The
power dissipation for this design is seen to be 2 mW. The next step would be begin
simulation.
Table 2 - Summary of W/L Ratios for Example 6.5-2
S1 = S2 = 6
S3 = S4 = 16
S5 = 27
S6 = S7 = S8 = S14 = S15 = 40
S9 = S10 = S11 = S12 = 18.2
S13 = 34

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-12

;;;
;;

Technological Implications of the Cascode Configuration


A

;;;;;;;

Thin
oxide

Poly I

Poly II

n-channel

n+

n+

p substrate/well

Fig. 6.5-5

If a double poly CMOS process is available, internode parasitics can be minimized.


As an alternative, one should keep the drain/source between the transistors to a minimum
area.
A
A

Minimum Poly
separation

;;;;;;;;

Thin
oxide

Poly I

Poly I

n+ n-channel n+ n-channel

n+

p substrate/well

Fig. 6.5-5A

CMOS Analog Circuit Design


Chapter 6 Section 5 (5/2/04)

P.E. Allen - 2004


Page 6.5-13

Input Common Mode Range for Two Types of Differential Amplifier Loads
VDD-VSG3+VTN
+
VSG3
Input
- M3
Common
Mode
M1
Range
VSS+VDS5+VGS1
+
VBias
-

VDD-VSD3+VTN

VDD

+
VSD4
M4 M2

M5 vicm

VSS
Differential amplifier with
a current mirror load.

VDD

+
V
Input SD3
Common - M3
Mode
Range
M1
VSS+VDS5+VGS1

+
VBias
-

VSD4
M4 VBP
M2

M5 vicm

VSS
Differential amplifier with
Fig. 6.5-6
current source loads.

In order to improve the ICMR, it is desirable to use current source (sink) loads without
losing half the gain.
The resulting solution is the folded cascode op amp.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-14

The Folded Cascode Op Amp


VDD
M14 M4 I4 M5 I5
A
B
RB
RA

I2

I1
+
vin
-

M13 M6 I6

M1

M2

M7 I7

vout

R1
R2

I3
+
VBias
-

M3

M8

CL
M9

M12
M10

M11

VSS
Fig. 6.5-7
Comments:
I4 and I5, should be designed so that I6 and I7 never become zero (i.e. I4=I5=1.5I3)
This amplifier is nearly balanced (would be exactly if RA was equal to RB)
Self compensating
Poor noise performance, the gain occurs at the output so all intermediate transistors
contribute to the noise along with the input transistors. (Some first stage gain can be
achieved if RA and RB are greater than gm1 or gm2.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-15

Small-Signal Analysis of the Folded Cascode Op Amp


Model:
gm6vgs6
R
A
Recalling what we
learned about the
i10
g
v
g
m1
in
m2vin
resistance looking into
r
rds1 rds4 vgs6 ds6 1
2
2
R2+g
the source of the
m10
+
cascode transistor;

gm7vgs7

RB

rds2 rds5

i7

vgs7 rds7 i
10
+

RII

+
vout
-

Fig. 140-07

rds6+R2+(1/gm10) 1
rds7 + RII
RII

and
R
=

B
1 + gm7rds7 gm7rds7 where RII gm9rds9rds11
gm6
1 + gm6rds6
The small-signal voltage transfer function can be found as follows. The current i10 is
written as
-gm1(rds1||rds4)vin -gm1vin
i10 = 2[RA + (rds1||rds4)] 2
and the current i7 can be expressed as
gm2(rds2||rds5)vin
gm2vin
gm2vin
RII(gds2+gds5)
i7 = RII
=
=
where
k
=

RII(gds2+gds5) 2(1+k)
gm7rds7

2g r + (rds2||rds5) 21 + g r

m7 ds7
m7 ds7

The output voltage, vout, is equal to the sum of i7 and i10 flowing through Rout. Thus,
vout gm1
gm2
2+k
=
+
R
=

vin 2 2(1+k) out 2+2k gmIRout


RA =

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-16

Frequency Response of the Folded Cascode Op Amp


The frequency response of the folded cascode op amp is determined primarily by the
output pole which is given as
-1
pout = R C
out out
where Cout is all the capacitance connected from the output of the op amp to ground.
All other poles must be greater than GB = gm1/Cout. The approximate expressions for
each pole is
1.) Pole at node A:
pA - gm6/CA
2.) Pole at node B:
pB - gm7/CB
-1
3.) Pole at drain of M6:
p6 (R2+1/gm10)C6
4.) Pole at source of M8:
p8 -gm8/C8
5.) Pole at source of M9:
p9 -gm9/C9
6.) Pole at gate of M10:
p10 -gm10/C10
where the approximate expressions are found by the reciprocal product of the resistance
and parasitic capacitance seen to ground from a given node. One might feel that because
RB is approximately rds that this pole might be too small. However, at frequencies where
this pole has influence, Cout, causes Rout to be much smaller making pB also non-dominant.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-17

Example 6.5-3 - Folded Cascode, CMOS Op Amp


Assume that all gmN = gmP = 100S, rdsN = 2M, rdsP = 1M, and CL = 10pF. Find all
of the small-signal performance values for the folded-cascode op amp.
0.4x109(0.3x10-6)
RII = 0.4G, RA = 10k, and RB = 4M k =
= 1.2
100
vout 2+1.2

vin = 2+2.4 (100)(57.143) = 4,156V/V


Rout = RII ||[gm7rds7(rds5||rds2)] = 400M||[(100)(0.667M)] = 57.143M
1
1
|pout| = RoutCout = 57.143M10pF = 1,750 rads/sec. 278Hz GB = 1.21MHz

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-18

PSRR of the Folded Cascode Op Amp


Consider the following circuit used to model the PSRR-:
VDD

R
Vss

Cgd11
VGSG9

Cgd9

M9
Vss

Vss
VGS11

rds9

Vout

Cgd9

Vss

Cout

rds11

M11

Vss

Rout

+
Vout
-

Fig. 6.5-9A

This model assumes that gate, source and drain of M11 and the gate and source of M9 all
vary with VSS.
We shall examine Vout/Vss rather than PSRR-. (Small Vout/Vss will lead to large PSRR-.)
The transfer function of Vout/Vss can be found as
sCgd9Rout
Vout

Vss sCoutRout+1 for Cgd9 < Cout


The approximate PSRR- is sketched on the next page.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-19

Frequency Response of the PSRR- of the Folded Cascode Op Amp


dB
|PSRR-|

|Avd()|

1
Cgd9Rout

Dominant
pole frequency

0dB
Cgd9
Cout

GB
Vout
Vss
Other sources of Vss injection, i.e. rds9

log10()
Fig. 6.5-10A

We see that the PSRR of the cascode op amp is much better than the two-stage op amp.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-20

Design Approach for the Folded-Cascode Op Amp


Step
Relationship
Design Equation/Constraint
I
=
SRC
1 Slew Rate
3
L
Bias
currents
in
I
=
I
=
2
4 5 1.2I3 to 1.5I3
output cascodes
2I7
2I5
3 Maximum output S =
,
S
=
voltage, vout(max) 5 KPVSD52 7 KPVSD72 , (S4=S14=S5 &
S13=S6=S7)
2I9
2I11
4 Minimum output S =
, S9=
, (S10=S11&S8=S9)
11 K V
voltage, vout(min)
2
KNVDS92
N DS11
5 Self-bias cascode R1 = VSD14(sat)/I14 and R2 = VDS8(sat)/I6
gm1
gm12 GB2CL2
6
GB = C
S
=S
=
1 2 KNI3 = KNI3
L
2I3
7 Minimum input
S3 =
CM
K N Vin(min)-VSS- (I3/KNS1) -VT1 2

Avoid zero current in


cascodes
VSD5(sat)=VSD7(sat)
= 0.5[VDD-Vout(max)]
VDS9(sat)=VDS11(sat)
= 0.5(Vout(max)-VSS)

Maximum input
CM

2I4
2
S4 = S5 =K V -V (max)+V
P DD in
T1

Differential
Voltage Gain

gm2
vout gm1
2+k

=
+
2(1+k)Rout = 2+2k gmIRout
vin 2

Power dissipation

Pdiss = (VDD-VSS)(I3+I12+I10+I11)

10

Comments

S4 and S5 must meet


or exceed value in step
3
k=

RII(gds2+gds4)
gm7rds7

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-21

Example 6.5-3 Design of a Folded-Cascode Op Amp


Follow the procedure given to design the folded-cascode op amp when the slew rate is
10V/s, the load capacitor is 10pF, the maximum and minimum output voltages are 2V
for 2.5V power supplies, the GB is 10MHz, the minimum input common mode voltage is
-1.5V and the maximum input common mode voltage is 2.5V. The differential voltage
gain should be greater than 5,000V/V and the power dissipation should be less than
5mW. Use channel lengths of 1m.
Solution
Following the approach outlined above we obtain the following results.
I3 = SRCL = 10x10610-11 = 100A
Select I4 = I5 = 125A.
Next, we see that the value of 0.5(VDD-Vout(max)) is 0.5V/2 or 0.25V. Thus,
2125A
212516
S4 = S5 = S14 = 50A/V2(0.25V)2 = 50 = 80
and assuming worst case currents in M6 and M7 gives,
2125A
212516
S6 = S7 = S13 = 50A/V2(0.25V)2 = 50 = 80
The value of 0.5(Vout(min)-|VSS|) is also 0.25V which gives the value of S8, S9, S10 and S11
2I8
2125
as S8 = S9 = S10 = S11 = K V 2 = 110(0.25)2 = 36.36
N DS8
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-22

Example 6.5-3 - Continued


The value of R1 and R2 is equal to 0.25V/125A or 2k. In step 6, the value of GB gives
S1 and S2 as
GB2CL2 (20x106)2(10-11)2
S1 = S2 = K I = 110x10-6100x10-6 = 35.9
N 3
The minimum input common mode voltage defines S3 as
2I3
200x10-6
S3 =
=

= 91.6

I3
100
2

2 110x10-6-1.5+2.5
-0.7
KNVin(min)-VSS- K S - VT1
11035.9

N 1
We need to check that the values of S4 and S5 are large enough to satisfy the maximum
input common mode voltage. The maximum input common mode voltage of 2.5 requires
2I4
2125A
S4 = S5 K [V -V (max)+V ]2 =
-6
50x10 A/V2[0.7V]2 = 10.2
P
DD in
T1
which is much less than 80. In fact, with S4 = S5 = 80, the maximum input common mode
voltage is 3V. Finally, S12, is given as
125
S12 = 100 S3 = 114.53
The power dissipation is found to be
Pdiss = 5V(125A+125A+125A) = 1.875mW
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-23

Example 6.5-3 - Continued


The small-signal voltage gain requires the following values to evaluate:
S4, S5, S13, S14:
S6, S7:

gm = 2755080 = 774.6S

S8, S9, S10, S11:


S1, S2:
Thus,

gm = 21255080 = 1000S and gds = 125x10-60.05 = 6.25S


and gds = 75x10-60.05 = 3.75S

gm = 27511036.36 = 774.6S and gds = 75x10-60.04 = 3S

gmI = 25011035.9 = 628S and gds = 50x10-6(0.04) = 2S

1 1
RII gm9rds9rds11 = (774.6S)3S 3S = 86.07M

1
1
Rout 86.07M||(774.6S)3.75S 2S+6.25S = 19.40M

RII(gds2+gds4) 86.07M(2S+6.25S)(3.75S)
=
= 3.4375
774.6S
gm7rds7
The small-signal, differential-input, voltage gain is
2+k
2+3.4375
Avd = 2+2k gmIRout = 2+6.875 0.628x10-319.40x106 = 7,464 V/V
The gain is larger than required by the specifications which should be okay.
k=

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 5 (5/2/04)

Page 6.5-24

Comments on Folded Cascode Op Amps


Good PSRR
Good ICMR
Self compensated
Can cascade an output stage to get extremely high gain with lower output resistance
(use Miller compensation in this case)
Need first stage gain for good noise performance
Widely used in telecommunication circuits where large dynamic range is required

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-1

SECTION 6.6 - SIMULATION AND MEASUREMENT OF OP AMPS


Simulation and Measurement Considerations
Objectives:
The objective of simulation is to verify and optimize the design.
The objective of measurement is to experimentally confirm the specifications.
Similarity Between Simulation and Measurement:
Same goals
Same approach or technique
Differences Between Simulation and Measurement:
Simulation can idealize a circuit
Measurement must consider all nonidealities

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-2

Simulating or Measuring the Open-Loop Transfer Function of the Op Amp


Circuit (Darkened op amp identifies the op amp under test):
vIN +VOS -

vOUT

VDD

Simulation:
RL
This circuit will give the voltage transfer
CL
VSS
function curve. This curve should identify:
Fig. 240-01
1.) The linear range of operation
2.) The gain in the linear range
3.) The output limits
4.) The systematic input offset voltage
5.) DC operating conditions, power dissipation
6.) When biased in the linear range, the small-signal frequency response can be
obtained
7.) From the open-loop frequency response, the phase margin can be obtained (F = 1)
Measurement:
This circuit probably will not work unless the op amp gain is very low.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-3

A More Robust Method of Measuring the Open-Loop Frequency Response


Circuit:

vOUT

vIN
CL
C

RL

VDD

VSS
Fig. 240-02

Resulting Closed-Loop Frequency Response:


dB

Op Amp
Open Loop
Frequency
Response

Av(0)

0dB

1
RC

Av(0)
RC

log10(w)
Fig. 240-03

Make the RC product as large as possible.


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-4

Magnitude, dB

Example 6.6-1 Measurement of the Op Amp Open-Loop Gain


Develop the closed-loop frequency response for op amp circuit used to measure the openloop frequency response. Sketch the closed-loop frequency response of the magnitude of
Vout/Vin if the low frequency gain is 4000 V/V, the GB = 1MHz, R = 10M, and C = 10F.
Solution
The open-loop transfer function of the op amp is,
2x106
GB
Av(s) = s +(GB/Av(0)) = s +500
The closed-loop transfer function of the op amp can be expressed as,
-1/sC

80
vOUT = Av(s)R+(1/sC)vOUT +vIN
|Av(j)|
60
-1/RC

= Av(s)s+(1/RC)vOUT +vIN
40
Vout(j)
vOUT
-[s +(1/RC)]Av(s)
Vin(j)
20
vIN = s +(1/RC)+Av(s)/RC
0
-(s+0.01)
-[s +(1/RC)]
= s +0.01
= s +(1/RC)
-20
0.001
0.1
10
1000
105
107
Av(s) +0.01
Av(s) +1/RC
S01E2S2
Radian Frequency (radians/sec)
Substituting, Av(s) gives,
-2x106s -2x104
-2x106s -2x104
-2x106(s +0.01)
vOUT
=
=
=
vIN (s+0.01)(s+500)+2x104 s2+500s +2x104 (s+41.07)(s+1529.72)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-5

Simulation and Measurement of Open-Loop Frequency Response with Moderate


Gain Op Amps
R
vIN

R
+
vi
-

vOUT
CL

RL

VDD

VSS

Fig. 240-04

Make R as large and measure vout and vi to get the open loop gain.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-6

Simulation or Measurement of the Input Offset Voltage of an Op Amp

vOUT=VOS

VDD

VOS

CL

VSS

RL

Fig. 6.6-4

Types of offset voltages:


1.) Systematic offset - due to mismatches in current mirrors, exists even with ideally
matched transistors.
2.) Mismatch offset - due to mismatches in transistors (normally not available in
simulation except through Monte Carlo methods).

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-7

Simulation of the Common-Mode Voltage Gain

V
+ OS-

vout

VDD

vcm
-

CL

RL

VSS
Fig. 6.6-5

Make sure that the output voltage of the op amp is in the linear region.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

100k

+
-

Measurement of CMRR and PSRR


Configuration:
vOS
Note that vI 1000
or vOS 1000vI
How Does this Circuit Work?
CMRR:
PSRR:
1.) Set
1.) Set
VDD = VDD + 1V
VDD = VDD + 1V
VSS = VSS + 1V
VSS = VSS
vOUT = 0V
vOUT = vOUT + 1V
2.) Measure vOS
2.) Measure vOS
called vOS1
called vOS3
3.) Set
3.) Set
VDD = VDD - 1V
VDD = VDD - 1V
VSS = VSS - 1V
VSS = VSS
vOUT = vOUT - 1V
vOUT = 0V
4.) Measure vOS
4.) Measure vOS
called vOS2
called vOS4
5.)
5.)
2000
2000
CMRR=|vOS2-vOS1|
PSRR+=|vOS4-vOS3|

Page 6.6-8

vOS

vSET

100k

10k
vOUT

VDD

10

vI
-

CL

VSS

RL

Fig. 240-07

Note:
1.) PSRR- can be measured similar to
PSRR+ by changing only VSS.
2.) The 1V perturbation can be
replaced by a sinusoid to measure
CMRR or PSRR as follows:
1000vdd
1000vss
PSRR+ = vos , PSRR- = vos
1000vcm
and CMRR = v
os

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-9

100k

+
-

How Does the Previous Idea Work?


A circuit is shown which is used to measure
the CMRR and PSRR of an op amp. Prove
that the CMRR can be given as
1000 vicm
CMRR =
vos
Solution
The definition of the common-mode rejection
ratio is
Avd
(vout/vid)
CMRR = Acm = (vout/vicm)

However, in the above circuit the value of vout


is the same so that we get
vicm
CMRR = v
id

vos

100k

vicm

10k
vOUT

VDD

10

vicm

vi
-

CL

RL

VSS
Fig. 240-08

vos
But vid = vi and vos 1000vi = 1000vid vid = 1000

Substituting in the previous expression gives,

CMOS Analog Circuit Design

vicm 1000 vicm


CMRR = v =
vos
os
1000
P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-10

Simulation of CMRR of an Op Amp


None of the above methods are really suitable for simulation of CMRR.
Consider the following:
Vcm
V2
Vcm

VDD

V2 -

Av(V1-V2)

Vout

V1

V1 +

Vcm

VSS

Vcm

Vout
AcVcm
Fig. 6.6-7

V1+V
Vout = Av(V1-V2) A
2 = -AvVout AcmVcm
Acm
Acm
Vout = 1+A Vcm A Vcm
v
v
Av Vcm

|CMRR| = Acm = Vout

cm

(However, PSRR+ must equal PSRR-)


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-11

CMRR of Ex. 6.3-1 using the Above Method of Simulation


200

80

150

Arg[CMRR] Degrees

85

|CMRR| dB

75
70
65
60
55
50

100
50
0
-50
-100
-150

45

-200
10

100

1000

CMOS Analog Circuit Design

104
105
106
Frequency (Hz)

107

108

10

100

1000

104
105
106
Frequency (Hz)

107

108

Fig. 240-10

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-12

Direct Simulation of PSRR


Circuit:
Vdd
V2
V2

V1

Av(V1-V2)

VDD
V1
VSS

Vss

Vout

Vss = 0
AddVdd
Fig. 6.6-9

Vout = Av(V1-V2) AddVdd = -AvVout AddVdd


Add
Add
Vout = 1+A Vdd A Vdd
v
v
Av Vdd
Av V ss
PSRR+ = A = V
and PSRR- = A = V
dd
out
ss
out
Works well as long as CMRR is much greater than 1.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-13

Simulation or Measurement of ICMR


vOUT

IDD
vOUT

VDD

1
1
vIN

vIN

ISS

CL

RL

VSS

ICMR
Also, monitor
IDD or ISS. Fig.240-11

Initial jump in sweep is due to the turn-on of M5.


Should also plot the current in the input stage (or the power supply current).

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-14

Measurement or Simulation of the Open-Loop Output Resistance


Method 1:
vOUT
+

+
vI
-

VDD

vOUT

Without RL
With RL

VO1
VO2
VOS

RL

vI(mV)

VSS
Fig. 240-12

V 01

Rout = RL V02 1

or vary RL until VO2 = 0.5VO1 Rout = RL

Method 2:
R

100R
- VDD

vIN

Rout

VSS

Ro
Fig. 240-13

1
Av -1 100Ro
1

Rout = Ro + 100R + 100Ro Av

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-15

Measurement or Simulation of Slew Rate and Settling Time


Volts Peak Overshoot
vin
IDD
vout

Settling Error
Tolerance

VDD
+SR -SR

vin

1
-

CL

RL

VSS

vout
1

Settling Time
Feedthrough

t
Fig. 240-14

If the slew rate influences the small signal response, then make the input step size small
enough to avoid slew rate (i.e. less than 0.5V for MOS).

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-16

Phase Margin and Peak Overshoot Relationship


It can be shown (Appendix C) that:
Phase Margin (Degrees) = 57.2958cos-1[ 44+1 - 22]
-
80

Overshoot (%) = 100 exp


1-2

100

60
10

50

Phase Margin

40

Overshoot

30

Overshoot (%)

For example, a 5% overshoot


corresponds to a phase margin of
approximately 64.

Phase Margin (Degrees)

70

1.0

20
10
0

0.2

0.4
= 1
2Q

0.6

0.8

0.1

Fig. 240-15

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-17

Example 6.6-2 Simulation of the CMOS Op Amp of Ex. 6.3-1.


VDD = 2.5V
The op amp designed in Example 6.3M3
M4
M6
1 and shown in Fig. 6.3-3 is to be analyzed
15m
15m
94m
1m
1m
by SPICE to determine if the specifications
1m
Cc = 3pF
are met. The device parameters to be used
vout
M1
M2
are those of Tables 3.1-2 and 3.2-1. In 30A
3m
3m
C
L=
1m
1m
addition to verifying the specifications of
10pF
95A
vin
Example 6.3-1, we will simulate PSRR+
+
30A
and PSRR-.
4.5m
14m
1m
4.5m
1m
Solution/Simulation
M5 1m
M8
M7
Fig. 240-16
VSS = -2.5V
The op amp will be treated as a
subcircuit in order to simplify the repeated analyses. The table on the next page gives the
SPICE subcircuit description of Fig. 6.3-3. While the values of AD, AS, PD, and PS could
be calculated if the physical layout was complete, we will make an educated estimate of
these values by using the following approximations.
AS = AD W[L1 + L2 + L3]
PS = PD 2W + 2[L1 + L2 + L3]
where L1 is the minimum allowable distance between the polysilicon and a contact in the
moat (Rule 5C of Table 2.6-1), L2 is the length of a minimum-size square contact to moat
(Rule 5A of Table 2.6-1), and L3 is the minimum allowable distance between a contact to
moat and the edge of the moat (Rule 5D of Table 2.6-1).
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-18

Example 6.6-2 - Continued


Op Amp Subcircuit:
- 2
vin
+ 1

8 VDD
6 vout

+
9 VSS

Fig. 240-17

.SUBCKT OPAMP 1 2 6 8 9
M1 4 2 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M2 5 1 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M3 4 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M4 5 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M5 3 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
M6 6 5 8 8 PMOS1 W=94U L=1U AD=564P AS=564P PD=200U PS=200U
M7 6 7 9 9 NMOS1 W=14U L=1U AD=84P AS=84P PD=40U PS=40U
M8 7 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
CC 5 6 3.0P
.MODEL NMOS1 NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N
.MODEL PMOS1 PMOS VTO=-0.7 KP=50U GAMMA=0..57 LAMBDA=0.05 PHI=0.8
+MJ=0.5 MJSW=.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P +LD=0.014U TOX=14N
IBIAS 8 7 30U
.ENDS

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-19

Example 6.6-2 - Continued


PSPICE Input File for the Open-Loop Configuration:
EXAMPLE 1 OPEN LOOP CONFIGURATION
.OPTION LIMPTS=1000
VIN+ 1 0 DC 0 AC 1.0
VDD 4 0 DC 2.5
VSS 0 5 DC 2.5
VIN - 2 0 DC 0
CL 3 0 10P
X1 1 2 3 4 5 OPAMP
..
.
(Subcircuit of previous slide)
..
.
.OP
.TF V(3) VIN+
.DC VIN+ -0.005 0.005 100U
.PRINT DC V(3)
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3)
.PROBE
(This entry is unique to PSPICE)
.END

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-20

Example 6.6-2 - Continued


Open-loop transfer characteristic of Example 6.3-1:
2.5
2

VOS
vOUT(V)

1
0
-1
-2

-2.5
-2

-1.5

-1.0 -0.5

0
0.5
vIN(mV)

1.5

Fig. 240-18

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-21

Example 6.6-2 - Continued


Open-loop transfer frequency response of Example 6.3-1:
200

80

150

Phase Shift (Degrees)

Magnitude (dB)

60
40
20
0

100
50
0
-50

-100

-20

-150

GB
-40

Phase Margin

GB

-200
10

100

1000

CMOS Analog Circuit Design

105
106
104
Frequency (Hz)

107

108

10

100

1000

104
105
106
Frequency (Hz)

107

108

Fig. 6.6-16

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-22

Example 6.6-2 - Continued


Input common mode range of Example 6.3-1:

VDD

Subckt.
+

vout

vin

VSS

Fig. 6.6-16A

40

ID(M5)

30
20

vOUT (V)

Input CMR
10

ID(M5) A

EXAMPLE 6.6-1 UNITY GAIN CONFIGURATION.


.OPTION LIMPTS=501
VIN+ 1 0 PWL(0 -2 10N -2 20N 2 2U 2 2.01U -2 4U -2 4.01U
+ -.1 6U -.1 6.0 1U .1 8U .1 8.01U -.1 10U -.1)
VDD 4 0 DC 2.5 AC 1.0
VSS 0 5 DC 2.5
CL 3 0 20P
X1 1 3 3 4 5 OPAMP
..
4
.
(Subcircuit of Table 6.6-1)
3
..
.
2
.DC VIN+ -2.5 2.5 0.1
.PRINT DC V(3)
1
.TRAN 0.05U 10U 0 10N
.PRINT TRAN V(3) V(1)
0
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3)
-1
.PROBE (This entry is unique to PSPICE)
.END
-2

-3
-3

-2

-1

0
vIN(V)

Fig. 240-21

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-23

Example 6.6-2 - Continued


Positive PSRR of Example 6.3-1:
100

100
Arg[PSRR+(j)] (Degrees)

|PSRR+(j)| dB

80
60
40
20
0
-20
10

100

1000

CMOS Analog Circuit Design

10
10
10
Frequency (Hz)

10

10

50

-50

-100
10

100

1000

104
105
106
Frequency (Hz)

107

108

Fig. 240-22

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-24

Example 6.6-2 - Continued


Negative PSRR of Example 6.3-1:
200

120
Arg[PSRR-(j)] (Degrees)

150
|PSRR-(j)| dB

100
80
60

PSRR+
40
20
10

100
50
0
-50
-100
-150
-200

100

1000

10
10
10
Frequency (Hz)

10

10

10

100

1000

104
105
106
Frequency (Hz)

107

108

Fig. 240-23

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-25

Example 6.6-2 - Continued


Large-signal and small-signal transient response of Example 6.3-1:
1.5

0.15

0.1
0.05

vout(t)

Volts

Volts

0.5

vin(t)

-0.5

vout(t)

-0.05

vin(t)

-1

-0.1

-1.5

-0.15
0

2
3
Time (Microseconds)

2.5

3.0

3.5
4.0
Time (Microseconds)

Why the negative overshoot on the slew rate?


If M7 cannot sink sufficient current then the output stage
slews and only responds to changes at the output via the
feedback path which involves a delay.
Note that -dvout/dt -2V/0.3s = -6.67V/s. For a 10pF
capacitor this requires 66.7A and only 95A-66.7A = 28A
is available for Cc. For the positive slew rate, M6 can provide
whatever current is required by the capacitors and can
immediately respond to changes at the output.
CMOS Analog Circuit Design

4.5
Fig. 240-24

VDD
M6

Cc iCc

iCL

vout

dvout
dt

CL
95A
+
VBias
-

M7
VSS

Fig. 240-25

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-26

Example 6.6-2 - Continued


Comparison of the Simulation Results with the Specifications of Example 6.3-1:
Specification
(Power supply = 2.5V)
Open Loop Gain
GB (MHz)
Input CMR (Volts)
Slew Rate (V/sec)
Pdiss (mW)
Vout range (V)
PSRR+ (0) (dB)
PSRR- (0) (dB)
Phase margin (degrees)
Output Resistance (k)

Design
(Ex. 6.3-1)
>5000
5 MHz
-1V to 2V
>10 (V/sec)
< 2mW
2V
60
-

Simulation
(Ex. 1)
10,000
5 MHz
-1.2 V to 2.4 V,
+10, -7(V/sec)
0.625mW
+2.3V, -2.2V
87
106
65
122.5k

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 6 (5/2/04)

Page 6.6-27

Example 6.6-3
Why is the negative-going overshoot
larger than the positive-going overshoot
on the small-signal transient response of
the last slide?
Consider the following circuit and
waveform:

VDD = 2.5V
94/1
M6 i6
iCc
iCL

0.1V

vout

Cc
95A

CL
-0.1V

VBias

M7

0.1s

0.1s

Fig. 240-26
VSS = -2.5V
During the rise time,
iCL = CL(dvout/dt )= 10pF(0.2V/0.1s) = 20A and iCc = 3pf(2V/s) = 6A
i6 = 95A + 20A + 6A = 121A gm6 = 1066S (nominal was 942.5S)
During the fall time, iCL = CL(-dvout/dt) = 10pF(-0.2V/0.1s) = -20A
and iCc = -3pf(2V/s) = -6A
i6 = 95A - 20A - 6A = 69A
gm6 = 805S
The dominant pole is p1 (RIgm6RIICc)-1 but the GB is gmI/Cc = 94.25S/3pF =
31.42x106 rads/sec and stays constant. Thus we must look elsewhere for the reason.
Recall that p2 gm6/CL which explains the difference.
p2(95A) = 94.25x106 rads/sec, p2(121A) = 106.6 x106 rads/sec, and p2(69A) =
80.05 x106 rads/sec. Thus, the phase margin is less during the fall time than the rise time.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-1

SECTION 6.7 - MACROMODELS FOR OP AMPS


Macromodel
A macromodel is a model that captures some or all of the performance of a circuit
using different components (generally simpler).
A macromodel uses resistors, capacitors, inductors, controlled sources, and some
active devices (mostly diodes) to capture the essence of the performance of a complex
circuit like an op amp without modeling every internal component of the op amp.
Op Amp Characterization
Small signal, frequency independent
Small signal, frequency dependent
Large signal
Time independent
Time dependent

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-2

SMALL SIGNAL, FREQUENCY INDEPENDENT, OP AMP MODELS


Simple Model
v1
v1
A

vo

v2

R id

v1

Ro v o

R id

Avd (v 1 -v 2 )

v2

v2

(a.)

(b.)

Avd (v -v )
Ro 1 2
(c.)

vo
Ro

Fig. 010-01

Figure 1 - (a.) Op amp symbol. (b.) Thevenin form of simple model. (c.) Norton form of
simple model.
SPICE Description of Fig. 1c
RID 1 2 {Rid}
RO 3 0 {Ro}
GAVD 0 3 1 2 {Avd/Ro}

CMOS Analog Circuit Design

Subcircuit SPICE Description for Fig. 1c


.SUBCKT SIMPLEOPAMP 1 2 3
RID 1 2 {Rid}
RO 3 0 {Ro}
GAVD 0 3 1 2 {Avd/Ro}
.ENDS SIMPLEOPAMP

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-3

Example 6.7-1 - Use of the Simple Op Amp Model


Use SPICE to find the voltage gain, vout/vin, the input resistance, Rin, and the output
resistance, Rout of Fig. 2. The op amp parameters are Avd = 100,000, Rid = 1M, and Ro =
100. Find the input resistance, Rin, the output resistance, Rout, and the voltage gain, Av,
of the noninverting voltage amplifier configuration when R1 = 1k and R2 = 100k.
Solution
Rin
Rout
The circuit with the SPICE node
2
1
v
out
A1
numbers identified is shown in Fig. 2.
+

R1 =
1k

vin

Figure 2 Noninverting
voltage amplifier for Ex. 1.

R2 = 100k
Fig. 010-02

The input file for this example is given as follows.


Example 1
VIN 1 0 DC 0 AC 1
XOPAMP1 1 3 2 SIMPLEOPAMP
R1 3 0 1KOHM
R2 2 3 100KOHM
.SUBCKT SIMPLEOPAMP 1 2 3
RID 1 2 1MEGOHM
RO 3 0 100OHM
GAVD/RO 0 3 1 2 1000
.ENDS SIMPLEOPAMP
.TF V(2) VIN
.END

The command .TF finds the small signal input


resistance, output resistance, and voltage or current
gain of an amplifier. The results extracted from the
output file are:
****

SMALL-SIGNAL CHARACTERISTICS
V(2)/VIN = 1.009E+02
INPUT RESISTANCE AT VIN = 9.901E+08
OUTPUT RESISTANCE AT V(2) = 1.010E-01.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-4

Common Mode Model


Electrical Model:
Acmv1+v2
vo = Avd(v1-v2) + R 2
o
Macromodel:
1
3

Ric1
Rid
Avd(v1 -v2 )
Ro

Avc v1
2Ro

Avc v2
2Ro

+
Ro

vo
-

Ric2
Linear Op Amp Macromodel

Fig. 010-03

Figure 3 - Simple op amp model including differential and common mode behavior.
SPICE File:
.SUBCKT LINOPAMP 1 2 3
RIC1 1 0 {Ric}
RID 1 2 {Rid}
RIC2 2 0 {Ric}
CMOS Analog Circuit Design

GAVD/RO 0 3 1 2 {Avd/Ro}
GAVC1/RO 0 3 1 0 {Avc/2Ro}
GAVC2/RO 0 3 2 0 {Avc/2Ro}
RO 3 0 {Ro}
.ENDS LINOPAMP

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-5

Small Signal, Frequency Dependent Op Amp Models


Dominant Pole Model:
Avd(0)
1
Avd(s) = (s/ ) + 1 where 1= R C (dominant pole)
1
1 1
Model Using Passive Components:
v1

vo
Rid

v2

Avd(0)
(v1 -v2 )
R1

R1

C1

Fig. 010-04

Figure 4 - Macromodel for the op amp including the frequency response of Avd.
Model Using Passive Components with Constant Output Resistance:
v1

Rid
v2

Avd(0)
(v1 -v2 )
R1

R1

C1

v3
Ro

vo

Ro

Fig. 010-05

Figure 5 - Frequency dependent model with constant output resistance.


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-6

Example 6.7-2 - Frequency Response of the Noninverting Voltage Amplifier


Use the model of Fig. 4 to find the frequency response of Fig. 2 if the gain is +1, +10,
and +100 V/V assuming that Avd(0) = 105 and 1= 100 rads/sec.
Solution
The parameters of the model are R2/R1 = 0, 9, and 99. Let us additionally select Rid =
1M and Ro = 100. We will use the circuit of Fig. 2 and insert the model as a
subcircuit. The input file for this example is shown below.
Example 2
R12 32 0 1KOHM
VIN 1 0 DC 0 AC 1
R22 22 32 9KOHM
*Unity Gain Configuration
XOPAMP1
1
31
21 *Gain of 100 Configuration
XOPAMP3
1
33
23
LINFREQOPAMP
LINFREQOPAMP
R11 31 0 15GOHM
R13 33 0 1KOHM
R21 21 31 1OHM
R23 23 33 99KOHM
*Gain of 10 Configuration
XOPAMP2
1
32
22 .SUBCKT
LINFREQOPAMP 1 2 3
LINFREQOPAMP
RID 1 2 1MEGOHM

CMOS Analog Circuit Design

GAVD/RO 0 3 1 2 1000
R1 3 0 100
C1 3 0 100UF
.ENDS
.AC DEC 10 100 10MEG
.PRINT AC V(21) V(22) V(23)
.PROBE
.END

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-7

Example 6.7-2 - Continued


40dB
Gain of 100

30dB
20dB

Gain of 10

10dB
0dB

Gain of 1

-10dB
15.9kHz
-20dB
100Hz

1kHz

159kHz

10kHz

1.59MHz

100kHz

1MHz

10MHz
Fig. 010-06

Figure 6 - Frequency response of the 3 noninverting voltage amplifiers of Ex. 2.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-8

Behavioral Frequency Model


Use of Laplace behavioral modeling capability in PSPICE.
GAVD/RO 0 3 LAPLACE {V(1,2)} = {1000/(0.01s+1)}.
Implements,
Avd(0)
Ro
Avd(s)
GAvd/Ro = Ro = s
1 + 1
where Avd(0) = 100,000, Ro = 100, and 1 = 100 rps

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-9

Differential and Common Mode Frequency Dependent Models


4

Op Amp Macromodel
Avc v1
2Ro

Ric1

Avc v2
2Ro

C2

R2

Rid
5

3
2

+
Ric2

Avd(v1 -v2 )
Ro

C1

v3
Ro

R1

v4
Ro

Ro

Figure 7 - Op amp macromodel for


separate differential and common
voltage gain frequency responses.

vo
-

Fig. 010-07

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-10

Zeros in the Transfer Function


Models:
3

Ro
Avd(v1 -v2 )
Ro

L1

vo Avd(v1 -v2 )
R1

C1

R1

kAvd
(v1 -v2 )
Ro

Ro

vo
-

(a.)

v3
Ro

(b.)

Fig. 010-08

Figure 8 - (a.) Independent zero model. (b.) Method of modeling zeros without
introducing new nodes.
Inductor:
Avd(0)

s
Vo(s) = Ro (sL1 + Ro) [V1(s)-V2(s)] = Avd(0)Ro/L1 + 1 [V1(s)-V2(s)] .

Feedforward:
Avd(0)
Vo(s) = (s/1) +11+k(s/1)+k [V1(s)-V2(s)] .

1
The zero can be expressed as
z1 = -11 + k
where k can be + or - by reversing the direction of the current source.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-11

Example 6.7-3 - Modeling Zeros in the Op Amp Frequency Response


Use the technique of Fig. 8b to model an op amp with a differential voltage gain of
100,000, a pole at 100rps, an output resistance of 100, and a zero in the right-half,
complex frequency plane at 107 rps.
Solution
The transfer function we want to model is given as
105(s/107 - 1)
Vo(s) = (s/100 + 1) .
Let us arbitrarily select R1 as 100k which will make the GAVD/R1 gain unity. To get
the pole at 100rps, C1 = 1/(100R1) = 0.1F. Next, we want z1 to be 107 rps. Since 1 =
100rps, then Eq. (6) gives k as -10-5. The following input file verifies this model.
Example 3
VIN 1 0 DC 0 AC 1
XOPAMP1 1 0 2 LINFREQOPAMP
.SUBCKT LINFREQOPAMP 1 2 4
RID 1 2 1MEGOHM
GAVD/R1 0 3 1 2 1
R1 3 0 100KOHM
C1 3 0 0.1UF

GV3/RO 0 4 3 0 0.01
GAVD/RO 4 0 1 2 0.01
RO 4 0 100
.ENDS
.AC DEC 10 1 100MEG
.PRINT AC V(2) VDB(2) VP(2)
.PROBE
.END

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-12

Example 6.7-3 - Continued


The asymptotic magnitude frequency response of this simulation is shown in Fig. 9.
We note that although the frequency response is plotted in Hertz, there is a pole at 100rps
(15.9Hz) and a zero at 1.59MHz (10Mrps). Unless we examined the phase shift, it is not
possible to determine whether the zero is in the RHP or LHP of the complex frequency
axis.
100dB

VDB(2)

80dB
60dB
40dB
15.9Hz or 100rps
20dB
1.59MHz or 10Mrps
0dB
1Hz

10Hz

100Hz 1kHz 10kHz 100kHz 1MHz 10MHz


Fig. 010-09
Frequency

Figure 9 - Asymptotic magnitude frequency response of the op amp model of Ex. 6.7-3.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-13

Large Signal Macromodels for the Op Amp


Output and Input Voltage Limitations
RLIM

Ric1

Ric2

D2

D1
VIH1
RLIM

VIL1

D4

VIL2

Rid
Avc v4
2Ro

D3
+

VIH2

Nonlinear Op
Amp Macromodel
Avc v5
2Ro

Avd(v -v )
4 5
Ro

D5
Ro

VOH

+
D6
+ 10
+ 11 vo
VOL
-

Fig. 010-10

Figure 10 - Op amp macromodel that limits the input and output voltages.
Subcircuit Description
.SUBCKT NONLINOPAMP 1 2 3
RIC1 1 0 {Ricm}
RLIM1 1 4 0.1
D1 4 6 IDEALMOD
VIH1 6 0 {VIH1}
D2 7 4 IDEALMOD
VIL1 7 0 {VIL1}
RID 4 5 {Rid}
RIC2 2 0 {Ricm}
RLIM2 2 5 0.1
D3 5 8 IDEALMOD
VIH2 8 0 {VIH1}

D4 9 5 IDEALMOD
VIL2 9 0 {VIL2}
GAVD/RO 0 3 4 5 {Avd/Ro}
GAVC1/RO 0 3 4 0 {Avc/Ro}
GAVC2/RO 0 3 5 0 {Avc/Ro}
RO 3 0 {Ro}
D5 3 10 IDEALMOD
VOH 10 0 {VOH}
D6 11 3 IDEALMOD
VOL 11 0 {VOL}
.MODEL IDEALMOD D N=0.001
.ENDS

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-14

Example 6.7-4 - Illustration of the Voltage Limits of the Op Amp


Use the macromodel of Fig. 10 to plot vOUT as a function of vIN for the noninverting,
unity gain, voltage amplifier when vIN is varied from -15V to +15V. The op amp
parameters are Avd(0) = 100,000, Rid = 1M, Ricm = 100M, Avc(0) = 10, Ro = 100,
VOH = -VOL = 10V, VIH1 =VIH2 = -VIL1 = -VIL2 = 5V.
Solution
The input file for this example is given below.
Example 4
VIN 1 0 DC 0
XOPAMP 1 2 2
NONLINOPAMP
.SUBCKT
NONLINOPAMP 1 2 3
RIC1 1 0 100MEG
RLIM1 1 4 0.1
D1 4 6 IDEALMOD
VIH1 6 0 5V
D2 7 4 IDEALMOD

CMOS Analog Circuit Design

VIL1 7 0 -5V
RID 4 5 1MEG
RIC2 2 0 100MEG
RLIM2 2 5 0.1
D3 5 8 IDEALMOD
VIH2 8 0 5V
D4 9 5 IDEALMOD
VIL2 9 0 -5v
GAVD/RO 0 3 4 5 1000
GAVC1/2RO 0 3 4 0 0.05
GAVC2/2RO 0 3 5 0 0.05

RO 3 0 100
D5 3 10 IDEALMOD
VOH 10 0 10V
D6 11 3 IDEALMOD
VOL 11 0 -10V
.MODEL IDEALMOD D N=0.0001
.ENDS
.DC VIN -15 15 0.1
.PRINT V(2)
.PROBE
.END

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-15

Example 6.7-4 - Illustration of the Voltage Limits of the Op Amp - Continued


7.5V
5V
2.5V
V(2) 0V
-2.5V
-5V
-7.5V
-10V

-5V

0V
VIN

5V

10V
Fig. 010-11

Figure 11 - Simulation results for Ex. 4.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-16

Output Current Limiting


Technique:
Io
2

Io
2
Io
ILimit
2

D1

D3

D2

ILimit
D4

Io
ILimit
2

Io
2

Io
2 Fig. 010-12

Macromodel for Output Voltage and Current Limiting:

v1
4

Rid
2

Avd (v -v )
Ro 1 2

v2

Ro

D3

D4
ILimit

D1
D2
6

D5
+

VOH

D6
7

VOL

vo

Fig. 010-13

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-17

Example 6.7-5 - Influence of Current Limiting on the Amplifier Voltage Transfer


Curve
Use the model above to illustrate the influence of current limiting on the voltage
transfer curve of an inverting gain of one amplifier. Assume the VOH = -VOL = 10V, VIH = VIL = 10V, the maximum output current is 20mA, and R1 = R2 = RL = 500 where RL is a
resistor connected from the output to ground. Otherwise, the op amp is ideal.
Solution
For the ideal op amp we will choose Avd = 100,000, Rid = 1M, and Ro = 100 and
assume one cannot tell the difference between these parameters and the ideal parameters.
The remaining model parameters are VOH = -VOL = 10V and ILimit = 20mA.
The input file for this simulation is given below.
Example 5 - Influence of Current Limiting on the Amplifier Voltage Transfer Curve
VIN 1 0 DC 0
D4 6 4 IDEALMOD
R1 1 2 500
ILIMIT 5 6 20MA
R2 2 3 500
D5 3 7 IDEALMOD
RL 3 0 500
VOH 7 0 10V
XOPAMP 0 2 3 NONLINOPAMP
D6 8 3 IDEALMOD
.SUBCKT NONLINOPAMP 1 2 3
VOL 8 0 -10V
RID 1 2 1MEGOHM
.MODEL IDEALMOD D N=0.00001
GAVD 0 4 1 2 1000
.ENDS
RO 4 0 100
.DC VIN -15 15 0.1
D1 3 5 IDEALMOD
.PRINT DC V(3)
D2 6 3 IDEALMOD
.PROBE
D3 4 5 IDEALMOD
.END
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-18

Example 6.7-5 - Continued


The resulting plot of the output voltage, v3, as a function of the input voltage, vIN is shown
in Fig. 14.
10V

V(3)

5V
0V
-5V
-10V
-15V

-10V

-5V

0V
VIN

5V

10V

15V

Fig. 010-14

Figure 14 - Results of Example 5.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-19

Slew Rate Limiting (Time Dependency)


Slew Rate:
dvo ISR
dt = C1 = Slew Rate
Macromodel:
v1

D3

Rid
v2

Avd(0)
(v1 -v2 )
R1

R1

D1

C1

D4
ISR

D2
7

v4 -v5
Ro

vo

Ro

Fig. 010-15

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-20

Example 6.7-6 - Simulation of the Slew Rate of A Noninverting Voltage Amplifier


Let the gain of a noninverting voltage amplifier be 1. If the input signal is given as
vin(t) = 10 sin(4x105t)
use the computer to find the output voltage if the slew rate of the op amp is 10V/s.
Solution
We can calculate that the op amp should slew when the frequency is 159kHz. Let us
assume the op amp parameters of Avd = 100,000, 1 = 100rps, Rid = 1M, and Ro =
100. The simulation input file based on the macromodel of Fig. 15 is given below.
Example 6 - Simulation of slew rate limitation
VIN 1 0 SIN(0 10 200K)
XOPAMP 1 2 2 NONLINOPAMP
.SUBCKT NONLINOPAMP 1 2 3
RID 1 2 1MEGOHM
GAVD/R1 0 4 1 2 1
R1 4 0 100KOHM
C1 4 5 0.1UF
D1 0 6 IDEALMOD

CMOS Analog Circuit Design

D2 7 0 IDEALMOD
D3 5 6 IDEALMOD
D4 7 5 IDEALMOD
ISR 6 7 1A
GVO/R0 0 3 4 5 0.01
RO 3 0 100
.MODEL IDEALMOD D N=0.0001
.ENDS

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-21

Example 6.7-6 - Continued


The simulation results are shown in Fig. 16. The input waveform is shown along with the
output waveform. The influence of the slew rate causes the output waveform not to be
equal to the input waveform.
10V

5V
Output
Voltage
0V

-5V

-10V
0s

Input
Voltage
2s

4s
Time

6s

8s

10s
Fig. 010-16

Figure 16 - Results of Ex. 6 on modeling the slew rate of an op amp.


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 7 (5/2/04)

Page 6.7-22

SPICE Op Amp Library Models


Macromodels developed from the data sheet for various components.
Key Aspects of Op Amp Macromodels:
Use the simplest op amp macromodel for a given simulation.
All things being equal, use the macromodel with the min. no. of nodes.
Use the SUBCKT feature for repeated use of the macromodel.
Be sure to verify the correctness of the macromodels before using.
Macromodels are a good means of trading simulation completeness for decreased
simulation time.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 6 Section 8 (5/2/04)

Page 6.8-1

SECTION 6.8 - SUMMARY


Topics
Design of CMOS op amps
Compensation of op amps
- Miller
- Self-compensating
- Feedforward
Two-stage op amp design
Power supply rejection ratio of the two-stage op amp
Cascode op amps
Simulation and measurement of op amps
Macromodels of op amps
Purpose of this chapter is to introduce the simple two-stage op amp to illustrate the
concepts of op amp design and to form the starting point for the improvement of
performance of the next chapter.
The design procedures given in this chapter are for the purposes of understanding and
applying the design relationships and should not be followed rigorously as the designer
gains experience.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Introduction (5/2/04)

Page 7.0-1

CHAPTER 7 - HIGH-PERFORMANCE CMOS OPERATIONAL


AMPLIFIERS
Chapter Outline
7.1 Buffered Op Amps
7.2 High-Speed/Frequency Op Amps
7.3 Differential Output Op Amps
7.4 Micropower Op Amp
7.5 Low-Noise Op Amps
7.6 Low Voltage Op Amps
7.7 Summary
Goal
To illustrate the degrees of freedom
and choices of different circuit
architectures that can enhance the
performance of a given op amp.

Buffered
High Frequency

Differential
Output
Two-Stage
Op Amp

Low Power

Low Noise
Low Voltage

Fig. 7.0-1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-1

SECTION 7.1 BUFFERED OP AMPS


Objective
The objective of this presentation is:
1.) Illustrate the method of lowering the output resistance of simple op amps
2.) Show examples
Outline
Open-loop MOSFET buffered op amps
Closed-loop MOSFET buffered op amps
BJT output op amps
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-2

What is a Buffered Op Amp?


A buffered op amp is an op amp with a low value of output resistance, Ro.
Typically, 10 Ro 1000
Requirements
Generally the same as for the output amplifier:
Low output resistance
Large output signal swing
Low distortion
High efficiency
Types of Buffered Op Amps
Buffered op amps using MOSFETs
With and without negative feedback
Buffered op amps using BJTs

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-3

Source-Follower, Push-Pull Output Op Amp


VDD
M9

M6
IBias

M12

M2

M18

Cc
M15

R1

M1

VSG18 +
-

M11

M7

M4

I17

M10

M5
R1 M8

+
vin

M17

R1

VSS
vout

CL

VSS

VSG21 +
-

VGS19
I20
M16

M14
VSS

+
VDD V
GS22
-

M19

M13

M3

M22

VDD

M21

M20

Buffer

Fig. 7.1-1

1
Rout = g
1000, Av(0) = 65dB (IBias=50A), and GB = 60MHz for CL = 1pF
m21+gm22
Output bias current?
M18-M19-M21-M22 loop VSG18+VGS19 = VSG21+VGS22
2I18
2I19
2I21
2I22
which gives
+
=
+
KPS18
KNS19
KPS21
KNS22
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-4

Crossover-Inverter, Buffer Stage Op Amp


Principle: If the buffer has high output resistance and voltage gain (common source), this
is okay if when loaded by a small RL the gain of this stage is approximately unity.
VDD

240
14

M7

144
M3 14

100A
C1=8pF

M4

240
14

M6

2400
7.5

C2=5pF

vout

RL
vin +
+
-

vin'

M2

M1

M5

360
7.5

460
7.5
Cross over stage VSS

Input
stage

1400
14
Output Stage

Fig. 7.1-2

This op amp is capable of delivering 160mW to a 100 load while only dissipating 7mW
of quiescent power!

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-5

Crossover-Inverter, Buffer Stage Op Amp - Continued


How does the output buffer work?
The two inverters, M1-M3 and M2-M4 are designed to work over different regions of the
buffer input voltage, vin.
Consider the idealized voltage transfer characteristic of the crossover inverters:
VDD

240
14

M7

144
M3 14

240
14

M4

C1=8pF

C2=5pF

M1

M2

vout

100A
vin'

460
7.5

VDD

M6

M5

360
7.5

RL

vout
M6 Active
M1-M3
M6 SaturInverter
M5 Saturated ated

M2-M4
Inverter

M5 Active

0
VSS

VA

VB

VDD

VSS

vin'

Fig. 7.1-3

Crossover voltage VC = VB-VA 0


VC is designed to be small and positive for worst case variations in processing
(Maximum value of VC 110mV)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-6

Crossover-Inverter, Buffer Stage Op Amp - Continued


Performance Results for the Crossover-Inverter, Buffer Stage CMOS Op Amp
Specification
Supply Voltage
Quiescent Power
Output Swing (100
Load)
Open-Loop Gain (100
Load)
Unity Gainbandwidth
Voltage Spectral Noise
Density at 1kHz
PSRR at 1kHz
CMRR at 1kHz
Input Offset Voltage
(Typical)

Performance
6V
7 mW
8.1 Vpp
78.1 dB
260kHz
1.7 V/ Hz
55 dB
42 dB
10 mV

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-7

Compensation of Op Amps with Output Amplifiers


Compensation of a three-stage amplifier:
Poles
This op amp introduces a third pole, p3 (what
p1' and p2'
about zeros?)
+
v2
+
With no compensation,
vin
-Avo
Vout(s)
Unbuffered
s
s

Vin(s) = s

op amp
p - 1 p - 1 p - 1
1
2
3

Pole p3'

vout

x1
Output
stage

CL

RL
Fig. 7.1-4

Illustration of compensation choices:


j

p2

p3'

Compensated poles
Uncompensated poles

p2'

p 1' p 1

p2
p3=p3' p2'

p1' p1

p3
Miller compensation applied around
both the second and the third stage.
CMOS Analog Circuit Design

Miller compensation applied around


the second stage only.
Fig. 7.1-5
P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-8

Low Output Resistance Op Amp


To get low output resistance using MOSFETs, negative feedback must be used.
Ideal implementation:
VDD

Error
Gain
Amplifier
Amplifier
viin

Error
Amplifier

M2
+

iout
vout

+
CL
M1

RL
Fig. 7.1-5A

VSS

Comments:
The output resistance will be equal to rds1||rds2 divided by the loop gain
If the error amplifiers are not perfectly matched, the bias current in M1 and M2 is not
defined

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-9

Low Output Resistance Op Amp - Continued


Offset correction circuitry:
VDD
+
vin
-

M6

M16

-A1+

Cc

VOS

M9

vout

Error Loop
M8

Unbuffered
op amp
+
VBias
-

M17

+
A2

M10

M8A

M6A
M12

M13
VSS

M11
Fig. 7.1-6

The feedback circuitry of the two error amplifiers tries to insure that the voltages in
the loop sum to zero. Without the M9-M12 feedback circuit, there is no way to adjust the
output for any error in the loop. The circuit works as follows:
When VOS is positive, M6 tries to turn off and so does M6A. IM9 reduces thus
reducing IM12. A reduction in IM12 reduces IM8A thus decreasing VGS8A. VGS8A
ideally decreases by an amount equal to VOS. A similar result holds for negative
offsets and offsets in EA2.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-10

Low Output Resistance Op Amp - Continued


Error amplifiers:
VDD
M6
M3

M4

Cc1
MR1

vin

M1

vout

M2

+
M5
VBias
A1 amplifier

M6A
VSS

Fig. 7.1-7

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-11

Low Output Resistance Op Amp - Complete Schematic


VDD

+
vin
-

+
-

M16

+
VBiasP
-

M4H

M3H
M3

M5A

MP3A

MP4
MP5

M4

MP4A

Cc

M6
MP3
MR1

M9
M8A
Cc2

Cc1

MR2

M10

M1 M2

M2A M1A

MN3A
M6A

M8
M17

M5

MN3

MN4

MN5A
M13

M12

+
VBiasN
-

M3A

M4A

M11

M3HA
MN4A

M4HA

VSS

Compensation:
Uses nulling Miller compensation.
Short circuit protection:
MP3-MN3-MN4-MP4-MP5
MN3A-MP3A-MP4A-MN4A-MN5A
(max. output 60mA)
CMOS Analog Circuit Design

vout
RC

gm1

Fig. 7.1-8

CC

gm6
R1

C1

RL

CL

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-12

Low Output Resistance Op Amp - Continued


Table 7.1-2 Performance Characteristics of the Low Output Resistance Op Amp:
Specification
Power Dissipation
Open Loop Voltage Gain
Unity Gainbandwidth
Input Offset Voltage
PSRR+(0)/PSRR-(0)
PSRR+(1kHz)/PSRR-(1kHz)
THD (Vin = 3.3Vpp)
RL = 300
CL = 1000pF
THD (Vin = 4.0Vpp)
RL = 15K
CL = 200pF
Settling Time (0.1%)
Slew Rate
1/f Noise at 1kHz
Broadband Noise

Simulated Results
7.0 mW
82 dB
500kHz
0.4 mV
85 dB/104 dB
81 dB/98 dB

Measured Results
5.0 mW
83 dB
420 kHz
1 mV
86 dB/106 dB
80 dB/98 dB

0.03%
0.08%

0.13%(1 kHz)
0.32%(4 kHz)

0.05%
0.16%
3 s
0.8 V/s
-

0.13%(1 kHz)
0.20%(4 kHz)
<5 s
0.6 V/s
130 nV/ Hz
49 nV/ Hz

rds6||rds6A 50k
Rout Loop Gain 5000 = 10
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-13

Low-Output Resistance Op Amp - Continued


Component sizes for the low-resistance op amp:
Transistor/Capacitor m/m or pF
M16
184/9
M17
66/12
M8
184/6
M1, M2
36/10
M3, M4
194/6
M3H, M4H
16/12
M5
145/12
M6
2647/6
MRC
48/10
11.0
CC
M1A, M2A
88/12
M3A, M4A
196/6
M3HA, M4HA
10/12
M5A
229/12
M6A
2420/6
10.0
CF
CMOS Analog Circuit Design

Transistor/Capacitor
M8A
M13
M9
M10
M11
M12
MP3
MN3
MP4
MN4
MP5
MN3A
MP3A
MN4A
MP4A
MN5A

m/m or pF
481/6
66/12
27/6
6/22
14/6
140/6
8/6
244/6
43/12
12/6
6/6
6/6
337/6
24/12
20/12
6/6
P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-14

Simpler Implementation of Negative Feedback to Achieve Low Output Resistance


VDD

M8
M3
200A 10/1 1/1

M4

M6
1/1 10/1
vout

+
vin
-

CL

M2

M1
10/1

10/1

1/1
M5

M10

10/1
M9

1/1

10/1
M7

VSS

Fig. 7.1-9

Output Resistance:
Ro
Rout = 1+LG
where
1
Ro = gds6+gds7
and
gm2
|LG| = 2gm4 (gm6+gm7)Ro

Therefore, the output resistance is


1
Rout =

gm2
.

(gds6+gds7)1 + 2gm4(gm6+gm7)Ro

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-15

Example 7.1-1 - Low Output Resistance Using the Simple Shunt Negative Feedback
Buffer
Find the output resistance of above op amp using the model parameters of Table 3.1-2.
Solution
The current flowing in the output transistors, M6 and M7, is 1mA which gives Ro of
1
1000
Ro = ( + )1mA = 0.09 = 11.11k
N P
To calculate the loop gain, we find that
gm2 = 2KN10100A = 469S
gm4 = 2KP1100A = 100S
and
gm6 = 2KP101000A = 1mS
Therefore, the loop gain is
469
|LG| = 100 1211.11 = 104.2
Solving for the output resistance, Rout, gives
11.11k
Rout = 1 + 104.2 = 106 (Assumes that RL is large)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-16

BJTs Available in CMOS Technology


Illustration of an NPN substrate BJT available in a p-well CMOS technology:

;;;
;;
;
;;;
;;;
Emitter

n+ (Emitter)

Base

p+

p- well (Base)

Collector
(VDD)

Collector (VDD)

n+

Base

n- substrate (Collector)

Fig. 7.1-10

Emitter

Comments:
gm of the BJT is larger than the FET so that the output resistance w/o feedback is lower
Can use the lateral or substrate BJT but since the collector is on ac ground, the
substrate BJT is preferred
Current is required to drive the BJT

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-17

Two-Stage Op Amp with a Class-A BJT Output Buffer Stage


Purpose of the M8-M9 source
VDD
follower:
M5
M7
M12
1.) Reduce the output resistance
+
(includes whatever is seen from
vin
the base to ground divided by
M1
M2
I
Bias
1+F)
Cc
2.) Reduces the output load at the
M4
M3
drains of M6 and M7
M6
M13

M8
Q10

vout

M9
CL

RL

M11

Output Buffer
VSS
Fig. 7.1-11
Small-signal output resistance :
r10 + (1/gm9)
1
1
=
+
Rout
gm10 gm9(1+F)
1+F
= 51.6+6.7 = 58.3 where I10=500A, I8=100A, W9/L9=100 and F is 100
Maximum output voltage:
Ic10
2KP

V
ln
vOUT(max) = VDD - VSD8(sat) - vBE10 = VDD t Is10
I8(W 8/L8)
Voltage gain:
gm10RL
vout gm1 gm6
gm9

vin gds2+gds4gds6+gds7gm9+gmbs9+gds8+g101+gm10RL
Compensation will be more complex because of the additional stages.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-18

Example 7.1-2 - Designing the Class-A, Buffered Op Amp


Use the parameters of Table 3.1-2 along with the BJT parameters of Is = 10-14A and
F = 100 to design the class-A, buffered op amp to give the following specifications.
Assume the channel length is to be 1m.
Slew rate 10V/s
VDD = 2.5V VSS = -2.5V GB = 5MHz Avd(0) 5000V/V
RL = 500
Rout 100 CL = 100pF ICMR = -1V to 2V
Solution
Because the specifications above are similar to the two-stage design of Ex. 6.3-1, we
can use these results for the first two stages of our design. However, we must convert the
results of Ex. 6.3-1 to a PMOS input stage. The results of doing this give W 1= W 2 =
6m, W3 = W4 = 7m, W5 = 11m, W6 = 43m, and W7 = 34m.
BJT follower:
SR = 10V/s and 100pF capacitor give I11 = 1mA.
If W13 = 44m, then W11 = 44m(1000A/30A) = 1467m.
I11 = 1mA 1/gm10 = 0.0258V/1mA = 25.8
MOS follower:
To source 1mA, the BJT must provide 2mA which requires 20A from the MOS follower.
Therefore, select a bias current of 100A for M8.
If W12 = 44m, then W8 = 44m(100A/30A) = 146m.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-19

Example 7.1-2 - Continued


If 1/gm10 is 25.8, then design gm9 as
1
1
gm9=R - (1/g )(1+ ) = (100-25.8)(101) = 133.4S gm9 and I9 W/L = 0.809
m10
F
out
Let us select W/L = 10 for M9 in order to make sure that the contribution of M9 to the
output resistance is sufficiently small and to increase the gain closer to unity. This gives a
transconductance of M9 of 300S.
To calculate the voltage gain of the MOS follower we need to find gmbs9.
gm9N
3000.4
=
= 36.5S

gmbs9 =
2 2F + VBS9 2 0.7+2
where we have assumed that the value of VSB9 is approximately 2V.
300S

AMOS = 300S+36.5S+4S+5S = 0.8683 V/V.


The voltage gain of the BJT follower is
500
ABJT = 25.8+500 = 0.951 V/V
Thus, the gain of the op amp is
Avd(0) = (7777)(0.8683)(0.951) = 6422 V/V
The power dissipation of this amplifier is,
Pdiss. = 5V(1255A) = 6.27mW
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-20

Two-Stage Op Amp with a Class-AB BJT Output Buffer Stage


This amplifier can reduce the quiescent power dissipation.
VDD
M5

M10
+
vin
-

M7

Q8
95A
M1

M2

133A

Cc

vout

IBias
M3

M9

M4

CL

RL

M6
VSS

Output
Buffer

Fig. 7.1-12

Slew Rate:
+

IOUT (1 + F)I7
SR+ = CL =
CL

and

SR- =

9(VDD 1V + |VSS| VT0)2


2CL

If F = 100, CL = 1000pF and I7 = 95A then SR+ = 8.59V/s.


Assuming a W9/L9 = 60 (I9 = 133A), 2.5V power supplies and CL = 1000pF gives SR= 35.9V/s.
(The current is not limited by I7 as it is for the positive slew rate.)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-21

Two-Stage Op Amp with a Class-AB BJT Output Buffer Stage


Small-signal characteristics:
C
Cc
+
gmIVin

R1

V1
gmIIV2
-

+ V +
r
R2 V 2
- gm8V

R3

gm9V1

Vout

Fig. 7.1-13
Nodal equations:
gmIVin = (GI + sCc)V1 sCcV2 + 0Vout
0 = (gmII sCc)V1 + (GII + g + sCc + sC)V2 (g + sC)Vout
0 gm9V1 (gm13 + sC)V2 + (gm13 + sC)Vout
where g > G3
The approximate voltage transfer function is:
(s/z1) 1 (s/z2) 1
V9(s)
Vin(s) Av0(s/p1) 1 (s/p2) 1
where
gmIgmII
gm13 gmII
gm9
1
z1 = Cc
z2 = C + Cc 1 + gmII
Av0 = GIGII
C
gm9

gmII gm13 1 + gmII


gm13gmII
C GIGII -1
GIGII
gm9
p1 = gmIICc 1 + FgmII + Cc gm13gmII
p2 (gmII + gm9)C

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-22

vOUT (Volts)

Two-Stage Op Amp with a Class-AB BJT Output Buffer Stage - Continued


Output stage current, IC8:
S9
60
IC8 = ID9 = S6ID6 = 43 95A = 133A
Small-signal output resistance:
r + RII
19.668k + 116.96k
=1353
rout = 1 + F =
101
if I6 =I7 = 95A, and F = 100.
2
Loading effect of RL on the voltage
transfer curve (increasing W9/L9 will
1
improve the negative part at the cost
of power dissipation):
R = 1000
L

RL = 100

RL =50

-1
-2
-3
-2

-1.5

-1

-0.5
0
0.5
vIN (Volts)

1.5

Fig. 7.1-14A

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-23

Example 7.1-3 - Performance of the Two-Stage, Class AB Output Buffer


Using the transistor currents given above for the output stages (output stage of the
two-stage op amp and the buffer stage), find the small-signal output resistance and the
maximum output voltage when RL = 50. Use the W/L values of Example 7.1-2 and
assume that the NPN BJT has the parameters of F = 100 and IS = 10fA.
Solution
It was shown on the previous slide that the small-signal output resistance is
r + rds6||rds7 19.668k + 116.96k
=
= 1353
rout =
101
1+F
Obviously, the MOS buffer of Fig. 7.1-11 would decrease this value.
The maximum output voltage is given above is only valid if the load current is small.
If this is not the case, then a better approach is to assume that all of the current in M7
becomes base current for Q8. This base current is multiplied by 1+F to give the sourcing
current. If M9 is off, then all this current flows through the load resistor to give an output
voltage of
vOUT(max) (1+F)I7RL
If the value of vOUT(max) is close to VDD, then the source-drain voltage across M7 may
be too small to be in saturation causing I7 to decrease. Using the above equation, we
calculate vOUT(max) as (101)95A50 or 0.48V which is close to the simulation results
shown using the parameters of Table 3.1-2.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 1 (5/2/04)

Page 7.1-24

SUMMARY
A buffered op amp requires an output resistance between 10 Ro 1000
Output resistance using MOSFETs only can be reduced by,
- Source follower output (1/gm)
- Negative shunt feedback (frequency is a problem in this approach)
Use of substrate (or lateral) BJTs can reduce the output resistance because gm is
larger than the gm of a MOSFET
Adding a buffer stage to lower the output resistance will most likely complicate the
compensation of the op amp

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-1

SECTION 7.2 HIGH SPEED/FREQUENCY OP AMPS


Objective
The objective of this presentation is:
1.) Explore op amps having high frequency response and/or high slew rate
2.) Give examples
Outline
Extending the GB of conventional op amps
Switched op amps
Current feedback op amps
Programmable gain amplifiers
Parallel path op amps
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-2

What is the Influence of GB on the Frequency Response?


The op amp is primarily designed to be used with negative feedback. When the product
of the op amp gain and feedback gain (loss) is not greater than unity, negative feedback
does not work satisfactorily.
Example of a gain of -10 voltage amplifier:
Magnitude
|Avd(0)| dB

Op amp frequency response


Amplifier with a gain of -10

20dB
0dB

-3dB GB

log10()
Fig. 7.2-1

What causes the GB?


We know that
gm
GB = C
where gm is the transconductance that converts the input voltage to current and C is the
capacitor that causes the dominant pole.
This relationship assumes that all higher-order poles are greater than GB.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-3

What is the Limit of GB?


The following illustrates what
Magnitude
happens when the next higher pole is
|Avd(0)| dB
not greater than GB:

Op amp frequency response


Amplifier with a gain of -10

20dB
0dB

For a two-stage op amp, the poles


and zeros are:
-gm1
1.) Dominant pole
p1 = Av(0)Cc
-gm6
2.) Output pole
p2 = CL
-gm3
3.) Mirror pole
p3 = Cgs3+Cgs4
-1
4.) Nulling pole
p4 = R C
z I
-1
5.) Nulling zero
z1 = RzCc-(Cc/gm6)
CMOS Analog Circuit Design

-40dB/dec
Next higher pole
A

-3dB GB

log10()
Fig. 7.2-2

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-4

A Procedure to Increase the GB of a Two-Stage Op Amp


1.) Use the nulling zero to cancel the closest pole beyond the dominant pole.
2.) The maximum GB would be equal to the magnitude of the second closest pole beyond
the dominant pole.
3.) Adjust the dominant pole so that 2.2GB (second closest pole beyond the dominant
pole)
Illustration which assumes that p2 is the next closest pole beyond the dominant pole:
j
-p3 -p4
Magnitude

-p2 = z1

|Avd(0)| dB
0dB

Fig. 7.2-3

GB
Increase
Old New
|p1|
|p1|

-p1
New
Old
GB

-p1
Old

New
GB |p ||p |
4 3
log10()

|p2|

-40dB/dec
-60dB/dec
-80dB/dec

Before cancelling
p2 by z1 and
increasing p1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-5

Example 7.2-1 - Increasing the GB of the Op Amp Designed in Ex. 6.3-1


Use the two-stage op amp designed
VDD = 2.5V
in Example 6.3-1 and apply the above
M3
M4
M6
15m
15m
94m
approach to increase the gainbandwidth
1m
1m
1m
Rz Cc = 3pF
as much as possible.
vout
M1
M2
Solution
30A
3m
3m
CL =
1m
1m
10pF
95A
1.) First find the values of p2, p3, and p4.
vin
+
(a.) From Ex. 6.3-2, we see that
30A
4.5m
14m
6
p2 = -94.25x10 rads/sec.
1m
4.5m
1m
M5 1m
M8
M7
Fig. 7.2-3A
(b.) p3 was found in Ex. 6.3-1 as
VSS = -2.5V
p3 = -2.81x109 rads/sec.
(c.) To find p4, we must find CI which is the output capacitance of the first stage of the op
amp. CI consists of the following capacitors,
CI = Cbd2 + Cbd4 + Cgs6 + Cgd2 + Cgd4
For Cbd2 the width is 3m L1+L2+L3 = 3m AS/AD=9m2 and PS/PD = 12m.
For Cbd4 the width is 15m L1+L2+L3 = 3m AS/AD=45m2 and PS/PD = 36m.
From Table 3.2-1:
Cbd2 = (9m2)(770x10-6F/m2) + (12m)(380x10-12F/m) = 6.93fF+4.56fF = 11.5fF
Cbd4 = (45m2)(560x10-6F/m2) + (36m)(350x10-12F/m) = 25.2fF+12.6F 37.8fF
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-6

Example 7.2-1 - Continued


Cgs6 is given by Eq. (10b) of Sec. 3.2 and is
Cgs6 = CGDOW6+0.67(CoxW6L6)=(220x10-12)(94x10-6)+(0.67)(24.7x10-4)(94x10-12)
= 20.7fF + 154.8fF = 175.5fF
Cgd2 = 220x10-12x3m = 0.66fF and Cgd4 = 220x10-12x15m = 3.3fF
Therefore, CI = 11.5fF + 37.8fF + 175.5fF + 0.66fF + 3.3fF = 228.8fF. Although Cbd2 and
Cbd4 will be reduced with a reverse bias, let us use these values to provide a margin. In
fact, we probably ought to double the whole capacitance to make sure that other layout
parasitics are included. Thus let CI be 300fF.
In Ex. 6.3-2, Rz was 4.591k which gives p4 = - 0.726x109 rads/sec.
2.) Using the nulling zero, z1, to cancel p2, gives p4 as the next smallest pole.
For 60 phase margin GB = |p4|/2.2 if the next smallest pole is more than 10GB.
GB = 0.726x109/2.2 = 0.330x109 rads/sec. or 52.5MHz.

This value of GB is designed from the relationship that GB = gm1/Cc. Assuming gm1 is
constant, then Cc = gm1/GB = (94.25x10-6)/(0.330x109) = 286fF. It might be useful to
increase gm1 in order to keep Cc above the surrounding parasitic capacitors (Cgd6 =
20.7fF). The success of this method assumes that there are no other roots with a
magnitude smaller than 10GB.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-7

Example 7.2-2 - Increasing the GB of the Folded Cascode Op Amp of Ex. 6.5-3
Use the folded-cascode op amp designed
VDD
in Example 6.5-3 and apply the above
approach to increase the gainbandwidth as
M14 M4 I4 M5 I5
much as possible.
Assume that the
A
B
drain/source areas are equal to 2m times the
RB
RA
width of the transistor and that all voltage
I2
I1
dependent capacitors are at zero voltage.
M13 M6 I6 M7 I7
vout
+
R1
M1 M2
Solution
vin
R2
CL
The poles of the folded cascode op amp are: I3
-1
M9
M8
pA RACA (the pole at the source of M6 )
+
M12
VBias M3
M11
M10
-1
pB R C
(the pole at the source of M7)
VSS
Fig. 6.5-7
B B
-1
p6 (R2+1/gm10)C6 (the pole at the drain of M6)
-gm8
-gm9
p8 C (the pole at the source of M8 )
p

(the pole at the source of M9)


9 C9
8
-gm10
and p10 C
(the pole at the gates of M10 and M11)
10
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-8

Example 7.2-2 - Continued


Let us evaluate each of these poles.
1,) For pA, the resistance RA is approximately equal to gm6 and CA is given as
CA = Cgs6 + Cbd1 + Cgd1 + Cbd4 + Cbs6 + Cgd4
From Ex. 6.5-3, gm6 = 744.6S and capacitors giving CA are found using the parameters
of Table 3.2-1 as,
Cgs6 = (220x10-1280x10-6) + (0.67)(80x10-610-624.7x10-4) = 149fF
Cbd1 = (770x10-6)(35.9x10-62x10-6) + (380x10-12)(237.9x10-6) = 84fF
Cgd1 = (220x10-1235.9x10-6) = 8fF
Cbd4 = Cbs6 = (560x10-6)(80x10-62x10-6) + (350x10-12)(282x10-6) = 147fF
and
Cgd4 = (220x10-12)(80x10-6) = 17.6fF
Therefore,
CA = 149fF + 84fF + 8fF + 147fF + 17.6fF + 147fF = 0.553pF
Thus,
-744.6x10-6
pA = 0.553x10-12 = -1.346x109 rads/sec.
2.) For the pole, pB, the capacitance connected to this node is
CB = Cgd2 + Cbd2 + Cgs7 + Cgd5 + Cbd5 + Cbs7
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-9

Example 7.2-2 - Continued


The various capacitors above are found as
Cgd2 = (220x10-1235.9x10-6) = 8fF
Cbd2 = (770x10-6)(35.9x10-62x10-6) + (380x10-12)(237.9x10-6) = 84fF
Cgs7 = (220x10-1280x10-6) + (0.67)(80x10-610-624.7x10-4) = 149fF
Cgd5 = (220x10-12)(80x10-6) = 17.6fF
and
Cbd5 = Cbs7 = (560x10-6)(80x10-62x10-6) + (350x10-12)(282x10-6) = 147fF
The value of CB is the same as CA and gm6 is assumed to be the same as gm7 giving pB =
pA = -1.346x109 rads/sec.
3.) For the pole, p6, the capacitance connected to this node is
C6= Cbd6 + Cgd6 + Cgs8 + Cgs9
The various capacitors above are found as
Cbd6 = (560x10-6)(80x10-62x10-6) + (350x10-12)(282x10-6) = 147fF
Cgs8 = (220x10-1236.4x10-6) + (0.67)(36.4x10-610-624.7x10-4) = 67.9fF
and
Cgs9 = Cgs8 = 67.9fF
Cgd6 = Cgd5 = 17.6fF
Therefore,
C6 = 147fF + 17.6fF + 67.9fF + 67.9fF= 0.300pF
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-10

Example 7.2-2 - Continued


From Ex. 6.5-3, R2 = 2k and gm6 = 744.6x10-6. Therefore, p6, can be expressed as
1
-p6 = 2x103 + (106/744.6)0.300x10-12 = 0.966x109 rads/sec.

4.) Next, we consider the pole, p8. The capacitance connected to this node is
C8= Cbd10 + Cgd10 + Cgs8 + Cbs8
These capacitors are given as,
Cbs8 = Cbd10 = (770x10-6)(36.4x10-62x10-6) + (380x10-12)(238.4x10-6) = 85.2fF
Cgs8 = (220x10-1236.4x10-6) + (0.67)(36.4x10-610-624.7x10-4) = 67.9fF
and
Cgd10 = (220x10-12)(36.4x10-6) = 8fF
The capacitance C8 is equal to
C8 = 67.9fF + 8fF + 85.2fF + 85.2fF = 0.246pF
Using the gm8 of Ex. 6.5-3 of 774.6S, the pole p8 is found as, -p8 = 3.149x109 rads/sec.
5.) The capacitance for the pole at p9 is identical with C8. Therefore, since gm9 is also
774.6S, the pole p9 is equal to p8 and found to be -p9 = 3.149x109 rads/sec.
6.) Finally, the capacitance associated with p10 is given as
C10 = Cgs10 + Cgs11 + Cbd8
These capacitors are given as
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-11

Example 7.2-2 - Continued


Cgs10 = Cgs11 = (220x10-1236.4x10-6) + (0.67)(36.4x10-610-624.7x10-4) = 67.9fF
and
Cbd8 = (770x10-6)(36.4x10-62x10-6) + (380x10-12)(238.4x10-6) = 85.2fF
Therefore,
C10 = 67.9fF + 67.9fF + 85.2fF = 0.221pF
which gives the pole p10 as -744.6x10-6/0.246x10-12 = -3.505x109 rads/sec.
The poles are summarized below:
pA = -1.346x109 rads/sec pB = -1.346x109 rads/sec p6 = -0.966x109 rads/sec
p8 = -3.149x109 rads/sec
p9 = -3.149x109 rads/sec p10 = -3.505x109 rads/sec
The smallest of these poles is p6. Since pA and pB are not much larger than p6, we
will find the new GB by dividing p6 by 5 (rather than 2.2) to get 200x106 rads/sec. Thus
the new GB will be 200/2 or 32MHz. The magnitude of the dominant pole is given as
GB
200x106
pdominant = Avd(0) = 7,464 = 26,795 rads/sec.
The value of load capacitor that will give this pole is
1
1
CL = pdominantRout = 26.795x10319.4M 1.9pF
Therefore, the new GB = 32MHz compared with the old GB = 10MHz.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-12

Conclusion for Increasing the GB of Op Amps


Maximum GB depends on the input transconductance and the capacitance that causes
the dominant pole.
Quantity

MOSFET Op
Amp

gm dependence

BJT Op Amp

IC
IC
W

2K L ID
kT/q = Vt
Maximum gm
1 mA/V
20 mA/V
GB for 10pF
15 MHz
300 MHz
GB for 1pF
150 MHz
3 GHz
Note that the power dissipation will be large for large GB because current is needed for
large gm.
Assumption:
All higher-order roots are above GB.
The larger GB, the more difficult this becomes.
Conclusion:
The best CMOS op amps have a GB of 10-50MHz
The best BJT op amps have a GB of 100-200MHz

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-13

Switched Amplifiers
Switched amplifiers are time varying circuits that yield circuits with smaller parasitic
capacitors and therefore higher frequency response. Such circuits are called dynamically
biased.
Switched amplifiers require a nonoverlapping clock
Switched amplifiers only work during a portion of a clock period
Bias conditions are setup on one clock phase and then maintained by capacitance on the
active phase
Switched amplifiers use switches and capacitors resulting in feedthrough problems
Simplified circuits on the active phase minimize the parasitics
Typical clock:
1

t
T

0
CMOS Analog Circuit Design

0.5

1.5

t
2 T Fig. 7.2-3B
P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-14

Dynamically Biased Inverting Amplifier


VDD

CB
M2

1 1
2

vin

ID

vout

COS
M1

1
VSS

Fig. 7.2-4

During phase 1 the offset and bias of the inverter is sampled and applied to COS and CB.
During phase 2 COS is connected in series with the input and provides offset canceling
plus bias for M1. CB provides the bias for M2.
(This circuit illustrates the concept of switched amplifiers but is too simple to illustrate
the reduction of bias parasitics.)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-15

Dynamically Biased, Push-Pull, Cascode Op Amp


VDD

M8

+
VB2
-

M4

M7

vin-

IB

C1
1 vin+
C2

M6

M3
vout

M2

M5 +
VB1
-

M1
VSS

Fig.7.2-5

Push-pull, cascode amplifier: M1-M2 and M3-M4


Bias circuitry: M5-M6-C2 and M7-M8-C1
Parasitics can be further reduced by using a double-poly process to eliminate bulk-drain
and bulk-source capacitances at the drain of M1-source of M2 and drain of M4-source of
M3 (see Fig. 6.5-5).
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-16

Dynamically Biased, Push-Pull, Cascode Op Amp - Continued


Operation:
VDD

VDD

+
VB2
-

M8

M7

C1

IB
C2

M6

VDD-VB2-(vin+-vin-)

+
VDD-VB2-vin+
vin+
+
vin+-VSS-VB1
-

M5 +
VB1
-

+
VDD-VB2-vin+
vin- -

C1

+
vin+-VSS-VB1
-

C2

VSS+VB1-(vin+-vin-)

VSS
Equivalent circuit during the 1 clock period

M4

M3
vout

M2

M1

VSS
Equivalent circuit during the 2 clock period.
Fig. 7.2-6

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-17

Dynamically Biased, Push-Pull, Cascode Op Amp - Continued


This circuit will operate on both clock phases .
VDD

+
VB2
M8 -

M7

1C2
vin-

IB

M6

M5 +
VB1
-

C1

M4

M3

C4 2
1

2
C3

vout

vin+

M2

VSS

Performance (1.5m CMOS):


1.6mW dissipation
GB 130MHz (CL=2.2pF)
Settling time of 10ns (CL=10pF)

M1

This amplifier was used with a


28.6MHz clock to realize a 5thorder switched capacitor filter
having a cutoff frequency of
3.5MHz.

Fig. 7.2-7

S. Masuda, et. al., CMOS Sampled Differential Push-Pull Cascode Op Amp, Proc. of 1984 International Symposium on Circuits and Systems,
Montreal, Canada, May 1984, pp. 1211-12-14.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-18

Current Feedback Op Amps


Why current feedback:
Higher GB
Less voltage swing more dynamic range
What is a current amplifier?
Ri2 i
2
i1
Ri1

io

Ro

+
Current
Amplifier

Fig. 7.2-8A

Requirements:
io = Ai(i1-i2)
Ri1 = Ri2 = 0
Ro =
Ideal source and load requirements:
Rsource =
RLoad = 0
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-19

Bandwidth Advantage of a Current Feedback Amplifier


Consider the inverting voltage amplifier
io
shown using a current amplifier with
negative current feedback:
R2
R1 iin i2 vout
io
The output current, io, of the current vin
v
out
+
i1
amplifier can be written as
+
io = Ai(s)(i1-i2) = -Ai(s)(iin + io)
Voltage
Current
Buffer
Amplifier
The closed-loop current gain, io/iin, can be Fig. 7.2-9
found as
io -Ai(s)
iin = 1+Ai(s)
However, vout = ioR2 and vin = iinR1. Solving for the voltage gain, vout/vin gives
vout ioR2 -R2 Ai(s)
vin = iinR1 = R1 1+Ai(s)
Ao
, then
If Ai(s) = s
+
1
A
vout -R2 Ao A(1+Ao)
vin = R1 1+Ao s + A(1+Ao)
CMOS Analog Circuit Design

-R2Ao
Av(0) = R1(1+Ao)

and

-3dB = A(1+Ao)
P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-20

Bandwidth Advantage of a Current Feedback Amplifier - Continued


The unity-gainbandwidth is,
R2
R2
R2Ao
GB = |Av(0)| -3dB = R1(1+Ao) A(1+Ao) = R AoA = R GBi
1
1
where GBi is the unity-gainbandwidth of the current amplifier.
Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.
Illustration:
Magnitude dB

R
Voltage Amplifier, R2 > K
R2 Ao
1
dB
R2
R1 1+Ao
Voltage Amplifier, R = K >1
1
Ao
dB
K
1+Ao
Current Amplifier
Ao dB
(1+Ao)A
0dB

GBi

GB1 GB2

log10()
Fig. 7.2-10

Note that GB2 > GB1 > GBi


The above illustration assumes that the GB of the voltage amplifier realizing the voltage
buffer is greater than the GB achieved from the above method.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-21

A Simple Current Mirror Implementation of a High Frequency Amplifier


Since the gain of the current amplifier does not need to be large, consider a unity-gain
current mirror implementation:
VDD

M4
vin

R1

M5
R2

M6

M7
M3
vout

IBias

M1

M2
VSS

M8

M9
Fig. 7.2-11

An inverting amplifier with a gain of 10 is achieved if R2 = 20R1 assuming the gain of the
current mirror is unity.
What is the GB of this amplifier?
R2Ao
Ao
1
1
GB = |Av(0)|-3dB = R (1+A ) R C = (1+A )R C = 2R C
1
o
2 o
o 1 o
1 o
where Co is the capacitance seen at the output of the current mirror.
If R1 = 10k and Co = 250fF, then GB = 31.83MHz.
Limitations:
R2
R1>Rin = 1/gm1 and R2 < rds2||rds6
R1 << gm1(rds2||rds6)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-22

A Wide-Swing, Cascode Current Mirror Implementation of a High Frequency


Amplifier
The current mirror shown below increases the value of R2 by increasing the output
resistance of the current mirror.
VDD
M14

M7
M13

M8

M9

M6

M5

R4
R1

vin

M12
vout

R2

IBias
M3

M4

M15
M1

M2
VSS

M10

M11
Fig. 7.2-12

New limitations:
R2
1
R1 > gm1 and R2 < gm4rds4rds2||gm6rds6rds8 R1 << gm1(gm4rds4rds2||gm6rds6rds8)
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-23

Example 7.2-3 - Design of a High GB Voltage Amplifier using Current Feedback


Design the wide-swing, cascode voltage amplifier to achieve a gain of -10V/V and a
GB of 500MHz which corresponds to a -3dB frequency of 50MHz.
Solution
Since we know what the gain is to be, let us begin by assuming that Co will be
100fF. Thus to get a GB of 500MHz, R1 must be 3.2k and R2 = 32k. Therefore,
1/gm1 must be less than 3200 (say 300). Therefore we can write
1
W
W
0.0505 = I L
gm1 = 2KI(W/L) = 300 5.56x10-6 = KI L
At this point we have a problem because if W/L is small to minimize Co, the current will
be too high. If we select W/L = 200m/1m we will get a current of 0.25mA. However,
using this W/L for M4 and M6 will give a value of Co that is greater than 100fF.
Therefore, select W/L = 200 for M1, M3, M5 and M7 and W/L = 20m/1m for M2, M4,
M6, and M8 which gives a current in these transistors of 25A.
Since R2/R1 is multiplied by 1/11 let R2 be 110 times R1 or 352k.
Now select a W/L for M12 of 20m/1m which will now permit us to calculate Co.
We will assume zero-bias on all voltage dependent capacitors. Furthermore, we will
assume the diffusion area as 2m times the W. Co can be written as
Co = Cgd4 + Cbd4 + Cgd6 + Cbd6 + Cgs12
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-24

Example 7.2-3 - Design of a High GB Voltage Amplifier using Current Feedback Contd
The information required to calculate these capacitors is found from Table 3.2-1. The
various capacitors are,
Cgd4 = Cgd6 = CGDOx10m = (220x10-12)(20x10-6) = 4.4fF
Cbd4 = CJxAD4+CJSWxPD4 = (770x10-6)(20x10-12)+(380x10-12)(44x10-6)
= 15.4fF+16.7fF = 32.1fF
Cbd6 = (560x10-6)(20x10-12)+(350x10-12)(44x10-6) = 26.6fF
Cgs12 = (220x10-12)(20x10-6) + (0.67)(20x10-610-624.7x10-4) = 37.3fF
Therefore,
Co = 4.4fF+32.1fF+4.4fF+26.6fF+37.3fF = 105fF
Note that if we had not reduced the W/L of M2, M4, M6, and M8 that Co would have
easily exceeded 100fF. Since 105fF is close to our original guess of 100fF, let us keep the
values of R1 and R2. If this value was significantly different, then we would adjust the
values of R1 and R2 so that the GB is 500MHz. One must also check to make sure that
the input pole is greater than 500MHz.
The design is completed by assuming that IBias = 100A and that the current in M9
through M12 be 100A. Thus W13/L13 = W14/L14 = 20m,/1m and W9/L9 through
W12/L12 are 20m/1m.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-25

Example 7.2-3 - Continued


30

R1 = 1k
20

|vout/vin| dB

-20dB/dec

10

R1 = 3.2k

0
-40dB/dec

-10
-20

f-3dB

GB

-30
105

106

107
108
Frequency (Hz)

109

1010
Fig. 7.2-13

Simulation Results:
GB 300MHz
Closed-loop gain = 18dB
f-3dB 38MHz
(Loss of -2dB is attributed to source follower and R1)
Note second pole at about 1GHz. To get these results, it was necessary to bias the input
at -1.7VDC using 3V power supplies.
If R1 is decreased to 1k results in:
Gain of 26.4dB, f-3dB = 32MHz, and GB = 630MHz
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-26

A 71 MHz Programmable Gain Amplifier using a Current Amplifier


The following circuit has been submitted for fabrication in 0.25m CMOS:
VDD
R1
vin+

M1

M2

R2
+1

+ vout -

vin-

R2
+1

VBias
x4
=1/8

x2
= 1/4

x1
=1/2

VSS

x1
=1/2

x2
= 1/4

x4
=1/8
Fig. 7.2-135A

R1 and the current mirrors are used for gain variation. R2 is fixed.
Can cascade this amplifier for higher gains
BW = BW i 21/n-1

for n = 2, BW = 0.64 BWi

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-27

Implementation of a 60dB Gain, 500MHz 3dB Frequency PGA

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-28

Simulation Results
Output voltage swing is 1.26V for a 2.5V power supply.
Voltage gain is 0 to 60dB in 2dB steps (gain error = 0.17dB)
Maximum GB is 1.5GHz
Total current: 3.6mA

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-29

A 71 MHz CMOS Programmable Gain Amplifier


Uses 3 ac-coupled stages.
First stage (0-20dB, common gate for matching and NF):
VDD
CMFB
VBP
vout

vout

VBN
0dB

2dB

0dB

M2

VB1
M2dB

M0dB

vin

2dB

M2
M3

VB1
vin

M0dB

M2dB

Fig. 7.2-137A

Rin = 330 to match source driving requirement


All current sinks are identical for the differential switches.
Dominant pole at 150MHz.

P. Orsatti, F. Piazza, and Q. Huang, A 71 MHz CMOS IF-Basdband Strip for GSM, IEEE JSSC, vol. 35, No. 1, Jan. 2000, pp. 104-108.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-30

A 71 MHz PGA Continued


Second stage (-10dB to 20dB):
VDD

CMFB
2dB

0dB

0dB

2dB

-10dB

VBP

M5

M6
vout

M6
vout

VBN

M4

0dB M2
Load
M3

vin

M5

M4

M2

M2

M2
-10dB
Load

M3

M0dB

M0dB

M2dB

vin
M2dB

-10dB

Fig. 7.2-137A

Dominant pole is also at 150MHz


For VDD = 2.5V, at 60dB gain, the total current is 2.6mA
IIP3 +1dBm
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-31

Parallel Path Op Amps


This type of op amp combines a high-gain, low-frequency path with a low-gain, highfrequency path.
dB

vin
-

+
-A1
+
- A2

|Avd1(0|) dB
vo1
+

vout

+
vo2

Fig. 7.2-14

|Avd1(s)|
|Avd2(s)|

|Avd2(0|) dB
0 dB

|p3|
|p1|

log10(f)

|p2|

GB

Comments:
Op amp will be conditionally stable
Compensation will be challenging

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-32

Multipath Nested Miller Compensation


Cm2
Cm1
vin

gm3

gm2

-gm1

vout

gm4
Fig. 7.2-15

Comments:
All Miller capacitances must be around inverting stages
Ensure that the RHP zeros generated by the Miller compensation are canceled
Avoid pole-zero doublets which can introduce a slow time constant

R.G.H. Eschauzier and J.H.Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers, Kluwer Academic publishers,
1995, Chapter 6.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-33

Illustration of Hybrid Nested Miller Compensation


(Note that this example is not
Cm3
multipath.)
Compensating Results:
Cm2
Cm1
1) Cm1 pushes p4 to higher
p2
p1
p3
frequencies and p3 down to lower
p4 vout
-gm3
-gm1
-gm4
-gm2
vin
frequencies
R1
RL CL
R2
R3
2) Cm2 pushes p2 to higher
Fig. 7.2-16
frequencies and p1 down to lower
frequencies
3) Cm3 pushes p3 to higher frequencies (feedback path) & pulls p1 further to lower
frequencies
Equations:
GB gm1/C m3
p2 gm2/Cm3
p3 gm3Cm3 / (Cm1Cm2)
p4 gm4/CL
Design:
GB < p2, p3, p4

R.G. H. Eschauzier et. al., A Programmable 1.5V CMOS Class-AB Operational Amplifier with Hybrid Nested Miller Compensation for 120dB Gain and 6MHz UGT, IEEE J.
of Solid State Circuits, vol. 29, No. 12, pp. 1497-1504, Dec. 1994.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-34

Illustration of the Hybrid Nested Miller Compensation Technique


j
p4

p3

p2

p1

Cm1

j
p4

p3 p2

p1

Cm2

j
p4

p3

p2

p1

Cm3

j
p4

p3

p2

p1

Fig. 7.2-17

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 2 (5/2/04)

Page 7.2-35

SUMMARY
Normal op amps limited by gm/C
Typical limit for CMOS op amp is GB 50MHz
Other approaches to high frequency CMOS op amps:
Current amplifiers (Transimpedance amplifiers)
Switched amplifier (simplifies the circuit reduce capacitances)
Parallel path op amps (compensation becomes more complex)
What does the future hold?
Reduction of channel lengths mean:
* Reduced capacitances Higher GBs
* Higher transconductances (larger values of K) Higher GBs
* Increased channel conductance Lower gains (more stages required)
* Reduction of power supply Increased capacitances
In otherwords, there should be some improvement in op amp GBs but it wont be
inversely proportional to the decrease in channel length. I.e. maybe GBs 100MHz
for 0.2m CMOS.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-1

SECTION 7.3 DIFFERENTIAL OUTPUT OP AMPS


Objective
The objective of this presentation is:
1.) Design and analysis of differential output op amps
2.) Examine the problem of common mode stabilization
Outline
Advantages and disadvantages of fully differential operation
Six different differential output op amps
Techniques of stabilizing the common mode output voltage
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-2

Why Differential Output Op Amps?


Cancellation of common mode signals including clock feedthrough
Increased signal swing
v1

v1-v2

A
t
-A
A
t
-A

v2

2A
t
-2A

Fig. 7.3-1

Cancellation of even-order harmonics


Symbol:

vin
+

+
-

vout
Fig. 7.3-1A

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-3

Common Mode Output Voltage Stabilization


If the common mode gain not small, it may cause the common mode output voltage to
be poorly defined.
Illustration:
vod
VDD

VSS
CM output voltage = 0
vod
VDD

VSS

CM output voltage =0.5VDD

vod
VDD

VSS

CM output voltage =0.5VSS

Fig. 7.3-2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-4

Two-Stage, Miller, Differential-In, Differential-Out Op Amp


Note that the
upper ICMR is
VDD - VSGP + VTN

VDD
+
VBP
-

M8

Cc

Rz

vo1
vi1

M9

M3

M6
M4

M1

Rz

Cc
vi2

M2
M5

+
VBN
-

vo2

M7

VSS

Fig. 7.3-3

Output common mode range (OCMR) = VDD+ |VSS| - VSDP(sat) - VDSN(sat)


The maximum peak-to-peak output voltage 2OCMR
Conversion between differential outputs and single-ended outputs:
+

+
vid
- -

+
-

Fig. 7.3-4
CMOS Analog Circuit Design

+
vod
-

CL

+
vid
- -

+
-

+
vo2
-

+
vo1
-

2CL

2CL
P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-5

Differential-Output, Folded-Cascode, Class-A Op Amp


VDD
M15

M4

M14

M5
M13

M6

M7
R1

vo2

vi1

M1

R2
M16

vi2

M2

vo1

M3

M12

M8

M9

VBias

M11

M10

M17

VSS

Fig. 7.3-5

OCMR = VDD + |VSS| - 2VSDP(sat) -2VDSN(sat)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-6

Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Push-Pull Output


VDD
+
VBP
-

M3

M4

M13

M7
vo1

Cc

M6
M14

Rz Cc

Rz
vi1

M1

M9

M10

VBN
-

M2
M5
VSS

vo2

vi2

M12

M8
Fig. 7.3-6

Comments:
Able to actively source and sink output current
Output quiescent current poorly defined

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-7

Two-Stage, Differential Output, Folded-Cascode Op Amp


VDD
M12

M20

M4

M5
M19

M6

M14

Rz

M15

M7
R1

M10

vo2

M13

vi1

Cc

M1

M11

vi2

M2

Rz

Cc

vo1

M18
M16

M8

M3

M17

M9

VBias
VSS

Fig. 7.3-7A

Note that the followers M11-M13 and M10-M12 are necessary for level translation to the
output stage.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-8

Unfolded Cascode Op Amp with Differential-Outputs


VDD
M7

M3 M4

M5

M8

M6
M20

M21
M9

M10
R2

vo1

vi1

M1 M2

M22

vo2

R1

M16

M15

M17
M23

M18

VBias
M12

M13
M11

M14

VSS

CMOS Analog Circuit Design

vi2

M19

Fig. 7.3-8

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-9

Cross-Coupled Differential Amplifier Stage


One of the problems with some of the previous stages, is that the quiescent output current
was not well defined.
The following input stage solves this problem.
i1
VGS1

vi1
VSG3

i2

+ M1 M2 +
vGS2
vGS1
+
+
vSG3
vSG4
M3 M4
i2

i1

VGS2

vi2
VSG4

Fig. 7.3-9

Operation:
Voltage loop vi1 - vi2 = -VGS1+ vGS1 + vSG4 - VSG4 = VSG3 - vSG3 - vGS2 + VGS2
Using the notation for ac, dc, and total variables gives,
vi2 - vi1 = vid = (vsg1 + vgs4) = -(vsg3 + vgs2)
If M1 = M2 = M3 = M4, then half of the differential input is applied across each transistor
with the correct polarity.
gm1vid gm4vid
gm2vid
gm3vid
and
i2 = - 2 = - 2
i1 = 2 = 2
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-10

Class AB, Differential Output Op Amp using a Cross-Coupled Differential Input


Stage
VDD

M10

M7 M8

M9

M25

M26
M13

vi1

M1 M2

M21

vo1

M22

M19

M15

M24

vi2
R1

M14
vo2

M20

M3 M4

R2

M16
M27

M11

M17

M18

M28 +
VBias
-

M5

M6
VSS

M23
M12
Fig. 7.3-10

Quiescent output currents are defined by the current in the input cross-coupled
differential amplifier.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-11

Common-Mode Output Voltage Stabilization


VDD

M1

Common-mode
M2
feedback circuit

Ro1

vo1

Ro2
io2(source)

io1(source)
io1(sink)

Ro3

Ro4

vo2

io2(sink)

VSS
Model of output of differential
output op amp

Fig. 7.3-11

Operation:
M1 and M2 sense the common-mode output voltage.
If this voltage rises, the currents in M1 and M2 decrease.
This decreased current flowing through Ro3 and Ro4 cause the common-mode output
voltage to decrease with respect to VSS.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-12

Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Common-Mode


Stabilization
VDD
+
VBP

M10

M7

Cc
vo1

Rz

vi1

M9

M11

M6

M3

M4

M1

+
VBN
-

M2
M5
VSS

Rz

Cc

vo2

vi2

M8
Fig. 7.3-12

Comments:
Simple
Unreferenced

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-13

A Referenced Common-Mode Output Voltage Stabilization Scheme


VDD

vo1

M1 M2

I5

vo2

M3 M4

Vocm

Iocm

To correction
circuitry

I6
M5

M6

VSS

Fig. 7.3-13

Operation:
1.) The desired common-mode output voltage, Vocm, creates Iocm.
2.) The actual common-mode output voltage creates current I5 which is mirrored to I6 .
3.) If M1 through M4 are matched and the current mirror is ideal, then when Iocm = I6
the actual common-mode output voltage should be equal to the desired commonmode output voltage.
4.) The above steps assume that a correction circuitry exists that changes the commonmode output voltage in the correct manner.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-14

Common Mode Feedback Circuits


Implementation of common mode feedback circuit:
VDD
M3
IBias MC3
Commonmode feedback circuit

MC1

v3

MC4
IC4

IC3

M4
I3

I4

MC2A
v1

VCM
MC2B
MC5

M1

M2

v4
Selfresistances
of M1-M4
v2

M5

MB

VSS

Fig. 7.3-13A

This scheme can be applied to any differential output amplifier.


Caution:
Be sure to check the stability of common-mode feedback loops, particularly those that
are connected to op amps that have a cascode output. The gain of the common-mode
feedback loop can easily reach that of a two-stage amplifier.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-15

Common Mode Feedback Circuits Continued


The previous circuit suffers when the input common mode voltage is low because the
transistors MC2A and MC2B have a poor negative input common mode voltage.
The following circuit alleviates this disadvantage:
VDD
M3

M4

IBias MC3
Commonmode feedback circuit

MC1

I3

v3

MC4
IC4

IC3

v1

VCM

v4

RCM2

RCM1

MC2

I4

M1

M2

v2

M5

MC5
MB

Fig. 7.3-15New

VSS

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-16

External Common-Mode Output Voltage Stabilization Scheme for Discrete-Time


Applications
1
+

+
vid
- -

2
vo1

+
-

CMbias
vo2

1
Ccm
1
Ccm

Vocm
Fig. 7.3-14

Operation:
1.) During the 1 phase, both Ccm are charged to the desired value of Vocm and CMbias
= Vocm.
2.) During the 2 phase, the Ccm capacitors are connected between the differential
outputs and the CMbias node. The average value applied to the CMbias node will be
Vocm.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 3 (5/2/04)

Page 7.3-17

SUMMARY
Advantages of differential output op amps:
- 6 dB increase in signal amplitude
- Cancellation of even harmonics
- Cancellation of common mode signals including clock feedthrough
Disadvantages of differential output op amps:
- Need for common mode output voltage stabilization
- Compensation of common mode feedback loop
- Difficult to interface with single-ended circuits
Most differential output op amps are truly balanced
For push-pull outputs, the quiescent current should be well defined
Common mode feedback schemes include,
- Unreferenced
- Referenced

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-1

SECTION 7.4 LOW POWER OP AMPS


Objective
The objective of this presentation is:
1.) Examine op amps that have minimum static power
- Minimize power dissipation
- Work at low values of power supply
- Tradeoff speed for less power
Outline
Weak inversion
Methods of creating an overdrive
Examples
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-2

Subthreshold Operation
Most micropower op amps use transistors in the subthreshold region.
Subthreshold characteristics:
iD

;;;;
Square Law

1A
100nA

iD

Strong Inversion

vGS =VT

Transition

Exponential

100nA

vGS VT

Weak Inversion

vGS

qv
W
GS

iD = L IDO exp nkT (1+vDS)

vDS
2V Fig. 7.4-0A

1V

VT

qID
gm = nkT

and gds ID

Operation with channel length = Lmin also will normally be in weak inversion.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-3

Two-Stage, Miller Op Amp Operating in Weak Inversion


VDD
M6
M3

M4

Cc
vout

vin
+

M1

+
VBias
-

CL

M2

M7

M5
VSS

Fig.7.4-1

Low frequency response:


ro2ro4 ro6ro7
1
1
Avo = gm2gm6 ro2 + ro4 ro6 + ro7 = n2n6(kT/q)2(2 + 4)(6 + 7) (No longer
)

ID
GB and SR:
ID5
ID1
ID1

kT
and
SR = C = 2 C = 2GB n1 q = 2GBn1Vt
GB = (n1kT/q)C
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-4

Example 7.4-1 Gain and GB Calculations for Subthreshold Op Amp.


Calculate the gain, GB, and SR of the op amp shown above. The currents are ID5 =
200 nA and ID7 = 500 nA. The device lengths are 1 m. Values for n are 1.5 and 2.5 for
p-channel and n-channel transistors respectively. The compensation capacitor is 5 pF.
Use Table 3.1-2 as required. Assume that the temperature is 27 C. If VDD = 1.5V and
VSS = -1.5V, what is the power dissipation of this op amp?
Solution
The low-frequency small-signal gain is,
1
Av = (1.5)(2.5)(0.026)2(0.04 + 0.05)(0.04 + 0.05) = 43,701 V/V
The gain bandwidth is
100 10-9
GB = 2.5(0.026)(5 10-12) = 307,690 rps 49.0 kHz
The slew rate is
SR = (2)(307690)(2.5)(0.026) = 0.04 V/s
The power dissipation is,
Pdiss = 3(0.7A) =2.1W

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-5

Push-Pull Output Op Amp in Weak Inversion


VDD

First stage gain is,


gm2 ID2n4Vt ID2n4
Avo = gm4 = ID4n2Vt = ID4n2 1

M3

M4

M8

Total gain is,


gm1(S6/S4)
(S6/S4)
Avo = (gds6 + gds7) = (6 + 7)n1Vt
At room temperature (Vt = 0.0259V) and
for typical device lengths, gains of 60dB M9
can be obtained.
The GB is,
gm1 S6 gm1b
GB = C S4 = C

CMOS Analog Circuit Design

M6
vi2

M1

M2
vout

+
VBias

Cc

M5
M7

VSS

Fig. 7.4-2

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-6

Increasing the Gain of the Previous Op Amp


1.) Can reduce the currents in M3
and M4 and introduce gain in the
M8
current mirrors.
2.) Use a cascode output stage
(cant use self-biased cascode,
currents are too low).
vi2

VDD

M4

M3

M6

VT+2VON
-

M13
M1

M2

M14

vi1

M10
vout

Cc
M5

I5
gm1+gm2
+ M11
M12 M15
+
R
Av =

2
out
VT+2VON
VBias
M9
gm1
M7
= gds6gds10 gds7gds11
Fig. 7.4-3A
VSS
+
gm10
gm11
I5
I5
2nnVt

= I 2 2 I 2 2 = 2I
7 nnVt2(nnn2+npp2)
7 n
7 p
+ I7
I7
nnV t
npV t
Can easily achieve gains greater than 80dB with power dissipation of less than 1W.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-7

Increasing the Output Current for Weak Inversion Operation


A significant disadvantage of the weak inversion is that very small currents are available
to drive output capacitance so the slew rate becomes very small.
Dynamically biased differential amplifier input stage:
VDD

M18

M20

i1v

i1

i2

M3

M4

i1

i2
M2

M1

A(i2-i1)

I5
M5

M22

M24

M28
M26
VSS

M19
i
vi1 2

M21
i2

A(i1-i2)

+
M25
VBiasM29
M27
-

M23
Fig. 7.4-4

Note that the sinking current for M1 and M2 is


Isink = I5 + A(i2-i1) + A(i1-i2) where (i2-i1) and (i1-i2) are only positive or zero.
If vi1>vi2, then i2>i1 and the sinking current is increased by A(i2-i1).
If vi2>vi1, then i1>i2 and the sinking current is increased by A(i1-i2).
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-8

Dynamically Biased Differential Amplifier - Continued


How much output current is available from this circuit if there is no current gain from the
input to output stage?
Assume transistors M18 through M21 are equal to M3 and M4 and that transistors M22
through M27 are all equal.
W 26
W 27
W 29
W 28

Let
L28 = A L26 and L29 = A L27
The output current available can be found by assuming that vin = vi1-vi2 > 0.

i1 + i2 = I5 + A(i2-i1)
The ratio of i2 to i1 can be expressed as
vin
i2

=
exp
nV
i1
t

Defining the output current as iOUT = b(i2-i1) and combining the above two equations
gives,

vin

bI5expnV - 1
vin
t

i
=

when
A
=
2.16
and
iOUT =
OUT
vin
nVt = 1

(1+A) - (A-1)expnVt

where b corresponds to any current gain through current mirrors (M6-M4 and M8-M3).
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-9

Overdrive of the Dynamically Biased Differential Amplifier


The enhanced output current is
accomplished by the use of positive
feedback (M28-M2-M19-M28).
The loop gain is,
gm28 gm19
gm19
LG = gm4 gm26 = A gm4 = A

A=2

A = 1.5

Note that as the output current


IOUT
increases, the transistors leave the weak I5 1
inversion region and the above analysis
is no longer valid.

CMOS Analog Circuit Design

A=1
A = 0.3
A=0

1
vIN nVt

2
Fig. 7.4-5

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-10

Increasing the Output Current for Strong Inversion Operation


An interesting technique is to bias the output transistor of a current mirror in the active
region and then during large overdrive cause the output transistor to become saturated
causing a significant current gain.
Illustration:

i1
M1

i2
M2 +
Vds2
-

Current

531A

i2 for W2/L2 = 5.31(W1/L1)


i1

100A
0.1Vds1(sat)

Vds1(sat)

Volts

Fig. 7.4-6

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-11

Example 7.4-2 Current Mirror with M2 operating in the Active Region


Assume that M2 has a voltage across the drain-source of 0.1Vds(sat). Design the
W2/L2 ratio so that I1 = I2 = 100A if W1/L1 = 10. Find the value of I2 if M2 is saturated.
Solution
Using the parameters of Table 3.1-2, we find that the saturation voltage of M2 is
2I1
200
Vds1(sat) = KN (W 2/L2) = 11010 = 0.4264V
Now using the active equation of M2, we set I2 = 100A and solve for W2/L2.
100A = KN(W2/L2)[Vds1(sat)Vds2 - 0.5Vds22]
= 110A/V2(W2/L2)[0.4260.0426 - 0.50.04262]V2 = 1.883x106(W2/L2)
Thus,
W2
100 =1.883(W2/L2) L2 = 53.12
Now if M2 should become saturated, the value of the output current of the mirror with
100A input would be 531A or a boosting of 5.31 times I1.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-12

Implementation of the Current Mirror Boosting Concept


VDD

M8
M17

M10

M7

M9

M18
M21

M13

i1

vi1

i2

M1 M2

M29

ki1
vo1

i1

M14

M30

M27

i2

M22

vi2

ki2

M28

M3 M4

i1

i2

vo2
ki1

ki2
M25

M26

i2
M5

M23 VBias

M15

i1
M24

M11

M16
M20

M19

M12
-

M6
VSS

Fig.7.4-7

k = overdrive factor of the current mirror


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-13

A Better Way to Achieve the Current Mirror Boosting


It was found that when the current mirror boosting idea illustrated on the previous slide
was used that when the current increased through the cascode device (M16) that VGS16
increased limiting the increase of VDS12. This can be overcome by the following circuit.
VDD
iin+IB

iin

IB
kiin
M3
50/1
M5 M4

1/1
M1
1/1

1/1
M2
210/1
Fig. 7.4-7A

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 4 (5/2/04)

Page 7.4-14

SUMMARY
Operation of transistors is generally in weak inversion
Boosting techniques are needed to get output sourcing and sinking currents that are
larger than that available during quiescent operation
Be careful about using circuits at weak inversion, i.e. the self-biased cascode will cause
the resistor to be too large

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-1

SECTION 7.5 LOW NOISE OP AMPS


Objective
The objective of this presentation is:
1.) Review the principles of low noise design
2.) Show how to reduce the noise of op amps
Outline
Review of noise analysis
Low noise op amps
Low noise op amps using lateral BJTs
Low noise op amps using doubly correlated sampling
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

;;;;

Chapter 7 Section 5 (5/2/04)

Page 7.5-2

Introduction
VDD
Why do we need low noise op amps?
Dynamic range:
Dynamic Range = 6dBx(Number. of bits)
Signal-to-noise ratio (SNR)
Maximum RMS Signal
=
Noise + Distortion
Noise
Fig. 7.5-0B
(SNDR includes both noise and distortion)
Consider a 14 bit digital-to-analog converter with a 1V reference with a bandwidth of
1MHz.
0.5V
= 0.3535 Vrms
Maximum RMS signal is
2
A 14 bit D/A converter requires 14x6dB dynamic range or 84 dB or 16,400.
0.3535
The value of the least significant bit (LSB) = 16,400 = 21.6Vrms
If the equivalent input noise of the op amp is not less than this value, then the LSB
cannot be resolved and the D/A converter will be in error. An op amp with an equivalent
input-noise spectral density of 10nV/ Hz will have an rms noise voltage of approximately
(10nV/ Hz)(1000 Hz) = 10Vrms in a 1MHz bandwidth.

;;;;

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-3

Transistor Noise Sources (Low-Frequency)


Drain current model:
D

M1

M1

2
in1

G
M1 is
noisy S

M1 is
noiseless S

Fig. 7.5-0A

(KF)ID
2 8kTgm(1+) (KF)ID

if vBS 0
or
i
+
n =
3
3
fCoxL2
fCoxL2
gmbs
Recall that = g
m
Gate voltage model assuming common source operation:
2

8kTgm

in =

D
2
en1

M1
G

CMOS Analog Circuit Design

*
M1 is
noiseless S

M1 is
noisy S

2
i
8kT

KF
N
2
en = 2 = 3gm + 2fCoxWLK
gm

M1

or

Fig. 7.5-0C

8kT(1+)
KF

+
if vBS 0
WLK
2fC
3g
m
ox

en =

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-4

Minimization of Noise in Op Amps


1.) Maximize the signal gain as close to the input as possible. (As a consequence, only
the input stage will contribute to the noise of the op amp.)
2.) To minimize the 1/f noise:
a.) Use PMOS input transistors with appropriately selected dc currents and W and L
values.
b.) Use lateral BJTs to eliminate the 1/f noise.
c.) Use chopper stabilization to reduce the low-frequency noise.
Noise Analysis
1.) Insert a noise generator for each transistor that contributes to the noise. (Generally
ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent input noise
voltage.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-5

A Low-Noise, Two-Stage, Miller Op Amp


VDD

VDD

M7

M10

I5

M5
+
vin
-

2
en1

2
en2

M1

*
M1

M2

Cc

2
en8

vout

M11
+
VBias
-

M8 M9
M3

M2

2
en6

M6
M4

M3

2
en4

VBias

M6

*
M4

VSS

eto2

VSS

M7

M8

2
en3

The total output-noise voltage spectral density,

2
M9 en9

VBias

2
en7

VSG7

Fig. 7.5-1

2
eto, is as follows where gm8(eff) 1/rds1,
2

eto = gm62RII2en6+en7 +RI2gm12en1+gm22en2+gm32en3+gm42en4 + (en8/rds12) + (en9/rds22)


2

Divide by (gm1RIgm6RII)2 to get the eq. input-noise voltage spectral density, eeq, as
2

2
eeq


eto
2en6
en8

2 gm32en3
2 gm32en3
= (gm1gm6RIRII)2 = gm12RI2 + 2en11+gm1 2 +
2 2en11+gm1 2
en1
en1 gm12rds12en1
2

where en6 = en7, en3 = en4, en1 = en2 and en8 = en9 and gm1RI is large.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-6

1/f Noise of a Two-Stage, Miller Op Amp


Consider the 1/f noise:
Therefore the noise generators are replaced by,
B
2
2 2BKIi
(V2/Hz)
and
ini = fLi2
(A2/Hz)
eni = fWiLi
Therefore, the approximate equivalent input-noise voltage spectral density is,
KNBN L1
2
2
eeq = 2en1 1 + KPBP L32 (V2/Hz)


Comments;
2

Because we have selected PMOS input transistors, en1 has been minimized if we
choose W1L1 (W2L2) large.
Make L1<<L3 to remove the influence of the second term in the brackets.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-7

Thermal Noise of a Two-Stage, Miller Op Amp


Let us focus next on the thermal noise:
The noise generators are replaced by,
2 8kT
2 8kTgm
(V2/Hz)
and
ini 3
(A2/Hz)
eni 3gm
where the influence of the bulk has been ignored.
The approximate equivalent input-noise voltage spectral density is,
2
eeq

2
2 gm32en3
2en11+gm1 2


en1

2
2en1 1 +

KNW3L1
KPW1L3 (V2/Hz)

Comments:
The choices that reduce the 1/f noise also reduce the thermal noise.
Noise Corner:
Equating the equivalent input-noise voltage spectral density for the 1/f noise and the
thermal noise gives the noise corner, fc, as
3gmB
fc = 8kTWL
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-8

Example 7.5-1 Design of A Two-Stage, Miller Op Amp for Low 1/f Noise
Use the parameters of Table 3.1-2 along with the value of KF = 4x10-28 FA for
NMOS and 0.5x10-28 FA for PMOS and design the previous op amp to minimize the 1/f
noise. Calculate the corresponding thermal noise and solve for the noise corner
frequency. From this information, estimate the rms noise in a frequency range of 1Hz to
100kHz. What is the dynamic range of this op amp if the maximum signal is a 1V peakto-peak sinusoid?
Solution
1.) The 1/f noise constants, BN and BP are calculated as follows.
KF
4x10-28FA
BN = 2CoxKN = 224.7x10-4F/m2110x10-6A2/V = 7.36x10-22 (Vm)2
and
KF
0.5x10-28FA
BP = 2CoxKP = 224.7x10-4F/m250x10-6A2/V = 2.02x10-22 (Vm)2
2.) Now select the geometry of the various transistors that influence the noise
performance.
2

To keep en1 small, let W1 = 100m and L1 = 1m. Select W3 = 100m and L3 =
20m and letW8 and L8 be the same as W1 and L1 since they little influence on the noise.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-9

Example 7.5-1 - Continued


Of course, M1 is matched with M2, M3 with M4, and M8 with M9.
BP
2.02x10-22
2.02x10-12
2
(V2/Hz)
en1 = fW 1L 1 = f100m1m =
f
1107.36 2 1 2
2.02x10-12
4.04x10-12
4.689x10-12
2

1 + 502.02 20 =
1.1606 =
(V2/Hz)
eeq = 2x
f
f
f

Note at 100Hz, the voltage noise in a 1Hz band is 4.7x10-14V2(rms) or 0.216V(rms).


3.) The thermal noise at room temperature is
8kT 81.38x10-23300
2
en1 = 3gm = 3707x10-6 = 1.562x10-17 (V2/Hz)
which gives
2
eeq

21.562x10-171 +

1101001
-17
-17
2
5010020 = 3.124x10 1.33= 4.164x10 (V /Hz)
2

4.) The noise corner frequency is found by equating the two expressions for eeq to get
4.689x10-12
fc = 4.164x10-17 = 112.6kHz
This noise corner is indicative of the fact that the thermal noise is much less than the 1/f
noise.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-10

Example 7.5-1 - Continued


5.) To estimate the rms noise in the bandwidth from 1Hz to 100,000Hz, we will ignore
the thermal noise and consider only the 1/f noise. Performing the integration gives
105

-12
4.689x10
2
df = 4.689x10-12[ln(100,000) - ln(1)]
Veq(rms) =
f
1
= 0.540x10-10 Vrms2 = 7.34 Vrms
The maximum signal in rms is 0.353V. Dividing this by 7.34V gives 48,044 or 93.6dB
which is equivalent to about 15 bits of resolution.
6.) Note that the design of the remainder of the op amp will have little influence on the
noise and is not included in this example.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-11

Lateral BJT
Since the 1/f noise is associated with current flowing at the surface of the channel, the
lateral BJT offers a lower 1/f noise input device because the majority of current flows
beneath the surface.
Vertical
Collector
(VDD)
n+

Lateral
Emitter Collector

;;;;;;;

Vertical Collector (VDD)

Cross-section of a NPN lateral BJT.

Symbol.

Base
p+

n+

n+

n+

p-well
n-substrate

Base

Lateral
Collector

Emitter
Fig. 7.5-3

Comments:
Base of the BJT is the well
Two collectors-one horizontal (desired) and one vertical (undesired)
Lateral collector current
Collector efficiency is defined as Total collector current and is 60-70%
Reverse biased collector-base acts like a photodetector and is often used for lightsensing purposes
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-12

Field-Aided Lateral BJT


Polysilicon gates are used to ensure that the region beneath the gate does not invert
forcing all current flow away from the surface and further eliminating the 1/f noise.
Vertical
Collector
(VDD)

Base

Gates

Emitter Lateral
Collector

;;;;
;;;;;
n+

p+

p-well
n-substrate

n+

n+

n+

Cross-section of a field-aided NPN lateral BJT.

Vertical Collector (VDD)


Lateral
Collector

Gate
Base

Emitter
Symbol.

Fig. 7.5-4

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-13

Physical Layout of a Lateral PNP Transistor

;;
;;;;;;
;;
;;;;;;
;;;;
;;
;;;;
;;;;;;
;;;;
;;
;;
;;
;;;;;;
;;;;
;;
;
;;;;
;;
;;;;;;
;;
;;;;;;;;;;
;;
n-substrate
p-well

n-diffusion
p-diffusion

Polysilicon

Experimental Results for


a x40 PNP lateral BJT:
Characteristic
Value
Transistor area 0.006mm2
Lateral
Lateral
efficiency
Base resistance
en at 5 Hz
en at midband
fc(en)
in at 5 Hz
in at midband

90
70%
150
2.46nV/ Hz
1.92nV/ Hz
3.2Hz

3.53pA/ Hz
Fig. 7.5-7A
Metal
0.61pA/ Hz
fc(in)
162 Hz
Generally, the above structure is made as small as fT
85 MHz
possible and then paralleled with identical geomet- Early voltage
16V
ries to achieve the desired BJT.
1.2m CMOS with n-well
Vertical Base Lateral Emitter Gate
Collector
Collector

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-14

Low-Noise Op Amp using Lateral BJTs at the Input


VDD
46.8
3.6

M13M14

46.8
3.6

vi2
M15M16
58.2
7.2

M5
Q1

58.2
7.2

M7

Q2

VSS
M3 M4

480
R1 18
=34k

D1

511
3.6

1296
3.6

vi1

81.6
3.6

M10 M11
Rz = 300 Cc = 1pF vout

M12

M8 M9

M6
480
18

270
1.2

130 43.8
3.6 6.6

45.6
3.6

VSS

Experimental noise
performance:

384
1.2

Fig. 7.5-6

Noise (nV/ Hz)

10
8

Eq. input noise voltage of low-noise op amp

6
4
Voltage noise of lateral BJT at 170A
2
0

10

100

1000
Frequency (Hz)

104

105
Fig. 7.5-7

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-15

Summary of Experimental Performance for the Low-Noise Op Amp


Experimental Performance
Value
Circuit area (1.2m)
Supply Voltages
Quiescent Current
-3dB frequency (at a gain of 20.8 dB)
en at 1Hz
en (midband)
fc(en)
in at 1Hz
in (midband)
fc(in)
Input bias current
Input offset current
Input offset voltage
CMRR(DC)
PSRR+(DC)
PSRR-(DC)
Positive slew rate (60 pF, 10 k load)
Negative slew rate (60 pF, 10 k load)
CMOS Analog Circuit Design

0.211 mm2
2.5 V
2.1 mA
11.1 MHz
23.8 nV/ Hz
3.2 nV/ Hz
55 Hz
5.2 pA/ Hz
0.73 pA/ Hz
50 Hz
1.68 A
14.0 nA
1.0 mV
99.6 dB
67.6 dB
73.9 dB
39.0 V/S
42.5 V/S
P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-16

Chopper-Stabilized Op Amps - Doubly Correlated Sampling (DCS)


Illustration of the use of chopper stabilization to remove the undesired signal, vu, form the
desired signal, vin.

Vu(f)
Vin(f)

Clock
+1
t
-1

vu

f
VA(f)

VB(f)

VC(f)

vB

vA

vin

A1

T =1
fc

vB

vout

A2

fc

2fc

3fc

fc

2fc

3fc

fc

2fc

3fc

Fig. 7.5-8

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-17

Chopper-Stabilized Amplifier
VDD

Chopper-stabilized Amplifier:

VDD

M3 M4
+
vin
-

M7 M8

1
2

1
2

M1 M2

2
1

M5 M6

2
1

IBias

IBias

V
Circuit equivalent during 1 phase: SS
vu1

vueq

VSS

vu2
+ A1

+ A2

Circuit equivalent during the 2 vphase:

v
vueq = vu1 + u2
A1
vu2

u1

vueq

+ A1
-

+ A2

+
v
u2
v
vueq = -vu1 + u2 , vueq(aver) =
A1
A1
CMOS Analog Circuit Design

+
Fig. 7.5-10
P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-18

Experimental Noise Response of the Chopper-Stabilized Amplifier


1000

nV/ Hz

Without chopper
With chopper
fc = 16kHz
100

With chopper fc = 128kHz

10

10

20
30
Frequency (kHz)

40

50
Fig. 7.5-11

Comments:
The switches in the chopper-stabilized op amp introduce a thermal noise equal to kT/C
where k is Boltzmanns constant, T is absolute temperature and C are capacitors
charged by the switches (parasitics in the case of the chopper-stabilized amplifier).
Requires two-phase, non-overlapping clocks.
Trade-off between the lowering of 1/f noise and the introduction of the kT/C noise.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 5 (5/2/04)

Page 7.5-19

SUMMARY
Primary sources of noise for CMOS circuits is thermal and 1/f
Noise analysis:
1.) Insert a noise generator for each transistor that contributes to the noise.
(Generally ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent input
noise voltage.
Noise is reduced in op amps by making the input stage gain as large as possible and
reducing the noise of this stage as much as possible.
The input stage noise can be reduced by using lateral BJTs (particularily the 1/f noise)
Doubly correlated sampling can transfer the noise at low frequencies to the clock
frequency (this technique is used to achieve low input offset voltage op amps).

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-1

SECTION 7.6 LOW VOLTAGE OP AMPS


Objective
The objective of this presentation is:
1.) How to design standard circuit blocks with reduced power supply voltage
2.) Introduce new methods of designing low voltage circuits
Outline
Low voltage input stages
Low voltage bias circuits
Low voltage op amps
Examples
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-2

Introduction
While low voltage op amps can be easily designed in weak inversion, strong
inversion leads to higher performance and is the focus of this section.
Semiconductor Industry Associates Roadmap for Power Supplies:
Feature Size
0.35m 0.25m 0.18m 0.13m 0.10m 0.07m

Power Supply Voltage

3.0V
2.5V
2.0V
Desktop Systems
1.5V

Single
Cell
Voltage

1.0V
Portable Systems
1995

1998

2001

2004
Year

2007

2010
Fig. 7.6-2

Threshold voltages will remain about 0.5 to 0.7V in order to allow the MOSFET to be
turned off.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-3

Implications of Low-Voltage, Strong-Inversion Operation

Reduced power supply means decreased dynamic range


Nonlinearity will increase because the transistor is working close to VDS(sat)
Large values of because the transistor is working close to VDS(sat)
Increased drain-bulk and source-bulk capacitances because they are less reverse biased.
Large values of currents and W/L ratios to get high transconductance
Small values of currents and large values of W/L will give smallVDS(sat)
Severely reduced input common mode range
Switches will require charge pumps

Approach
Low voltage input stages with reasonable ICMR
Low voltage bias and load circuits
Low voltage op amps

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-4

Differential Amplifier with Current Source Loads


VDD

Minimum power supply (ICMR = 0):


VDD(min) = VSD3(sat)-VT1+VGS1+VDS5(sat)
= VSD3(sat)+VDS1(sat)+VDS5(sat)

+
VBias
-

VSD3(sat)
M3

M4

-VT1

Input common-mode range:


Vicm(upper) = VDD - VSD3(sat) + VT1
Vicm(lower) = VDS5(sat) + VGS1

vicm

VGS1
VDS5(sat)

M1

+
VBias
-

M2

M5
Fig. 7.6-3

Example:
If the threshold magnitudes are 0.7V, VDD = 1.5V and the saturation voltages are
0.3V, then
and
Vicm(lower) = 0.3 + 1.0 = 1.3V
Vicm(upper) = 1.5 - 0.3 + 0.7 = 1.9V
giving an ICMR of 0.6V.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-5

Increasing ICMR using Parallel Input Stages


Turn-on voltage for the n-channel input:
M6
Vonn = VDSN5(sat) + VGSN1
Vicm
Turn-on voltage for the p-channel input:
IBias
Vonp = VDD - VSDP5(sat) - VSGP1
The sum of Vonn and Vonp equals the minimum
M7
power supply.
Regions of operation:
VDD > Vicm > Vonp: (n-channel on and p-channel off)
Vonp Vicm Vonn: (n-channel on and p-channel on)
Vonn > Vicm > 0 : (n-channel off and p-channel on)

VDD
MN3

MN4

MP5

MP1

Vicm

MP2

MN2

MN1

MP4
MP3

MN5
Fig. 7.6-4

gm(eq) = gmN
gm(eq) = gmN + gmP
gm(eq) = gmP

where gm(eq) is the equivalent input transconductance of the above input stage, gmN is
the input transconductance for the n-channel input and gmP is the input transconductance for the p-channel
gm(eff)
input.
gmN+gmP
gmP

n-channel off Vonn n-channel on


p-channel on
p-channel on
0

VSDP5(sat)+VGSN1

Vonp

n-channel on
p-channel off

VDD-VSDP5(sat)+VGSN1 VDD

gmN
Vicm
Fig. 7.6-5

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-6

Removing the Nonlinearity in Transconductances as a Function of ICMR


VDD
Increase the bias current in the differential amplifier that is on when the other
Ib
differential amplifier is off.
Inn

3:1

Ip

Three regions of operation depending on VB2


MP1
MP2
Vicm
Vicm
VB1
MB2
the value of Vicm:
MB1
MN1
MN2
1.) Vicm < Vonn: n-channel diff. amp.
off and p-channel on with Ip = 4Ib:
Ipp
In
K P W P
gm(eff) =
LP 2 Ib
Ib
1:3
2.) Vonn < Vicm < Vonp: both on with
Fig. 7.6-6
In = Ip = Ib :
K N W N
K P W P
I
+
Ib
gm(eff) =
b
LN
LP
3.) Vicm > Vonp: p-channel diff. amp. off and n-channel on with In = 4Ib:
K N W N
gm(eff) =
LN 2 Ib
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-7

How Does the Current Compensation Work?


Set VB1 = Vonn and VB2 = Vonp.
VDD
If vicm <Vonp then Ip = Ib and Inn=0
vicm

vicm

MN1

MB1

Inn

MN2

Vonn

Ipp

In
Ib

If vicm >Vonp then Ip = 0 and Inn=Ib

If vicm >Vonn then In = Ib and Ipp=0


If vicm <Vonn then In = 0 and Ipp=Ib

Ib
Ip

vicm MP1
MB2

MP2 v

icm

Vonp
Fig. 7.6-6A

Result:
gm(eff)
gmN=gmP

Vicm
VDD Fig. 7.6-7

Vonp

Vonn

The above techniques and many similar ones are good for power supply values down to
about 1.5V. Below than, different techniques must be used or the technology must be
modified (natural devices).
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-8

;;

Bulk-Driven MOSFET
A depletion device would permit large ICMR even with very small power supply voltages
because VGS is zero or negative.
When a MOSFET is driven from the bulk with the gate held constant, it acts like a
depletion transistor.
Cross-section of an n-channel
vBS
VDD
VGS
VDS
bulk-driven MOSFET:

;;
;;
;;;;;
;;
;;
;;
;;;;;;
;;
;;;;;
;;
Bulk

p+

Gate

Drain

n+

Channel

Depletion p-well
Region

Source

n+

Substrate

n+

QP

QV

n substrate

Large signal equation:


K NW
iD = 2L VGS - VT0 - 2|F| - vBS + 2|F|2
Small-signal transconductance:
(2KNW/L)ID
gmbs = 2 2| | - V
F
BS
CMOS Analog Circuit Design

Fig. 7.6-8

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-9

Bulk-Driven MOSFET - Continued


Transconductance characteristics:

2000

Drain Current (A)

Bulk-source driven
1500

1000
Saturation: VDS > VBS VP gives,
VBS = VP + VON
500

VBS2
IDSS

Gate-source
iD = IDSS 1 - VP
driven

0
Comments:
-3
-2
-1
0
1
2
3
Fig. 7.6-9
gm (bulk) > gm(gate) if VBS > 0
Gate-Source or Bulk-Source Voltage (Volts)
(forward biased )
Noise of both configurations are the same (any differences comes from the gate versus
bulk noise)
Bulk-driven MOSFET tends to be more linear at lower currents than the gate-driven
MOSFET
Very useful for generation of IDSS floating current sources.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-10

Bulk-Driven, n-channel Differential Amplifier


What is the ICMR?
Vicm(min) = VSS + VDS5(sat) + VBS1 = VSS + VDS5(sat) - |VP1| + VDS1(sat)
Note that Vicm can be less than VSS if |VP1| > VDS5(sat) + VDS1(sat)
Vicm(max) = ?
VDD
As Vicm increases, the current through
M3
M4
M1 and M2 is constant so the source
increases. However, the gate voltage stays
M7
constant so that VGS1 decreases. Since
the current must remain constant through
vi1
vi2
M1 and M2 because of M5, the bulkIBias
source voltage becomes less negative
+
+
+
VBS2
VBS1 M1VGS
M2
causing VTN1 to decrease and maintain
the currents through M1 and M2 constant.
If Vicm is increased sufficiently, the bulkM5
M6
source voltage will become positive.
However, current does not start to flow
VSS
Fig. 7.6-10
until VBS is greater than 0.3 volts so the
effective Vicm(max) is
Vicm(max) VDD - VSD3(sat) - VDS1(sat) + VBS1.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-11

Illustration of the ICMR of the Bulk-Driven, Differential Amplifier


250nA

Bulk-Source Current

200nA

150nA

100nA

50nA

-50nA
-0.50V -0.25V
0.00V 0.25V 0.50V
Input Common-Mode Voltage Fig. 7.6-10A

Comments:
Effective ICMR is from VSS to VDD -0.3V
The transconductance of the input stage can vary as much as 100% over the ICMR
which makes it very difficult to compensate
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-12

Low-Voltage Current Mirrors using the Bulk-Driven MOSFET


The biggest problem with current mirrors is the large minimum input voltage required for
previously examined current mirrors.
If the bulk-driven MOSFET is biased with a current that exceeds IDSS then it is
enhancement and can be used as a current mirror.
VDD

VDD

Cascode Current Mirror


All W/L's = 200m/4m

-5

6 10

iin
iout

M1
+
+
VGS VBS
-

M2
-

+
VGS

Simple bulk-driven
current mirror

+
VGS3
+
VGS1
-

2m CMOS

iout

M4
M3
+
+
VBS3 VGS4
-M2
M1
+
+
VBS1
V
GS2
-

Cascodebulk-driven
current mirror. Fig.7.6-11

5 10-5

Iout (A)

iin

Iin=50A

4 10-5

Iin=40A

3 10-5

Iin=30A

2 10-5

Iin=20A

1 10-5

Iin=10A

0
0

0.2

0.4
0.6
Vout (V)

0.8

1
Fig. 7.6-12

The cascode current mirror gives a minimum input voltage of less than 0.5V for currents
less than 100A
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-13

Simple Current Mirror with Level Shifting


Since the drain can be VT less than the gate, the drain could be biased to reduce the
minimum input voltage as illustrated.
VDD

IBias

iin
VEB +
- Q3

iout

M2

M1

Fig. 7.6-13

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-14

A Low-Voltage Current Mirror with Wide Input and Output Swings


The current mirror below requires a power supply of VT+3VON and has a Vin(min) =
VON and a Vout(min) = 2VON (less for the regulated cascode output mirror).
VDD

I1-IB
iin

VDD

I2

IB

IB

I1

M4

M7

iout

M7

M3

M4

or

M6

M6
M2

M1
M5

I2

IB1

iin

iout

M3

IB2

IB1

M5

M1
IB2

M2
Fig. 7.6-13A

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-15

Bandgap Topologies Compatible with Low Voltage Power Supply


VDD

VDD
VDD
IPTAT

VDD
IVBE

VRef

VDD

VDD

VDD
INL

IVBE

IPTAT

VRef

VRef

VPTAT

IPTAT
INL

VBE

R2
R3
R1

Voltage-mode bandgap topology.

Current-mode bandgap topology.

Voltage-current mode bandgap topology.


Fig. 7.6-14

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-16

Method of Generating Currents with VBE and PTAT Temperature Coefficients


VDD

IVBE
Buss
IPTAT
Buss

M7 M8

IVBE
M3

M6

VBE
R3
-

IVBE
M5

M4

IPTAT
Q1

M9

Q2
+
R1 VPTAT R2
-

IPTAT
R4 Vout2
+
Vout1
-

Figure 7.6-15A

V PTAT
R2
Vout1 = IPTATR2 = R1 R2 = VPTAT R1

V BE
R4
Vout2 = IVBER4 = R R4 = VBE R
3
3

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-17

Technique for Canceling the Bandgap Curvature


VDD
M1

1:K3
M2 M3
INL

I2
IVBE

M2 active
M3 off

M4

Current

1:K2

K3INL

M2 sat.
M3 on
K1IPTAT

K2IVBE

INL

K1IPTAT

Temperature
Illustration of the various currents.

Circuit to generate nonlinear correction term, INL.

Fig. 7.6-16

0,
K2IVBE > K1IPTAT
INL = K I
1 PTAT - K2IVBE, K2IVBE < K1IPTAT

The combination of the above concept with the previous slide yielded a curvaturecorrected bandgap reference of 0.596V with a TC of 20ppm/C from -15C to 90C using
a 1.1V power supply. In addition, the line regulation was 408 ppm/V for 1.2VDD10V
and 2000 ppm/V for 1.1VDD10V. The quiescent current was 14A.

G.A. Rincon-Mora and P.E. Allen, A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference, J. of Solid-State
Circuits, vol. 33, no. 10, October 1998, pp. 1551-1554.
CMOS Analog Circuit Design
P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-18

Low-Voltage Op Amp using Classical Techniques (VDD 2VT)


VDD
M4

M3
M15

IBias

vin
+

M1 M2

VON
-

VT+2VON

+
VT+VON
-

M12
+
VT+VON M7 M11
+
R1 VON
M6
-

M13

Cc

vout

CL
M5

M16

M8

M9

M14
M10
Fig. 7.6-17

Clever use of classical techniques.


Balanced inputs.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-19

Example 7.6-1 - Design of a Low-Voltage Op Amp using the Previous Topology


Use the parameters of Table 3.1-2 to design the op amp above to meet the
specifications given below.
Vicm(max) = 2.5V
Vicm(min) = 1V
VDD = 2V
Vout(max) = 1.75V Vout(min) = 0.5V
GB = 10MHz
Slew rate = 10V/s Phase margin = 60 for CL = 10pF
Solution
Assuming the conditions for a two-stage op amp necessary to achieve 60 phase
margin and that the RHP zero is at least 10GB gives
Cc = 0.2CL = 2pF
The slew rate is directly related to the current in M5 and gives
I5 = CcSR = 2x10-12107 = 20A
We also know the input transconductances from GB and Cc. They are given as
gm1 = gm2 = GBCc = 20x1062x10-12 = 125.67S
Knowing the current flow in M1 and M2 gives the W/L ratios as
gm12
W 1 W2
(125.67x10-6)2
L1 = L2 = 2KN(I1/2) = 2110x10-610x10-6 = 7.18
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-20

Example 7.6-1 - Continued


Next, we find the W/L of M5 that will satisfy Vicm(min) specification.
Vicm(min) = VDS5(sat) + VGS1(10A) = 1V
This gives
210
VDS5(sat) = 1 - 1107.18 - 0.75 = 1-0.159-0.75 = 0.0909V
W5
2I5
220

VDS5(sat) = 0.0909 =
KN(W 5/L5)
L5 = 110(0.0909)2 = 44
The design of M3 and M4 is accomplished from the upper input common mode voltage:
Vicm(max) = VDD-VSD3(sat)+VTN = 2-VSD3(sat)+0.75 = 2.5V
Solving for VSD3(sat) gives 0.25V. Assume that the currents in M6 and M7 are 20A.
This gives a current of 30A in M3 and M4. Knowing the current in M3 (M4) gives
W 3 W4
230
230
L3 = L4 (0.25)250 = 19.2
VSD3(sat) 50(W3/L3)
Next, using the VSD(sat) = V ON of M3 and M4, design M10 through M12. Let us
assume that I10 = I5 = 20A which gives W10/L10 = 44. R1 is designed as R1 =
0.25V/20A = 12.5k. The W/L ratios of M11 and M12 can be expressed as
2I11
W 11 W 12
220
=
=
=
L11 L12 KPVSD11(sat)2 50(0.25)2 = 12.8
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-21

Example 7.6-1 - Continued


Since the source-gate voltages and currents of M6 and M7 are the same as M11 and M12
then the W/L values are equal. Thus
W6/L6 = W7/L7 = 12.8
M8 and M9 should be as small as possible to reduce the parasitic (mirror) pole.
However, the voltage drop across M4, M6 and M8 must be less than the power supply.
Using this to design the gate-source voltage of M8 gives
VGS8 = VDD - 2VON = 2V - 20.25 = 1.5V
Thus,
W 8 W9
2I8
230
=
=
L8 L9 KNVDS8(sat)2 = 110(0.75)2 = 0.97 1
Because M8 and M9 are small, the mirror pole will be insignificant. The next poles of
interest would be those at the sources of M6 and M7. Assuming the channel length is
1m, these poles are given as
gm6
2KP'(W6/L6)I6
25012.820 x10-6
p6 CGS6 = (2/3)W6L6Cox = (2/3)12.812.47x10-15 = 7.59x109 rads/sec
which is about 100 times greater than GB.
Finally, the W/L ratios of the second stage must be designed. We can either use the
relationship for 60 phase margin of gm14 = 10gm1 = 1256.7S or consider proper
mirroring between M9 and M14.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-22

Example 7.6-1 - Continued


Substituting 1256.7S for gm14 and 0.5V for VDS14 in W/L = gm/(KN' VDS(sat)) gives
W14/L14 = 22.85 which gives I14 = 314A. The W/L of M13 is designed by the
necessary current ratio desired between the two transistors and is
W 13 I13
314
=
I
=
L13 I12 12 20 12.8 = 201
Now, check to make sure that the Vout(max) is satisfied. The saturation voltage of M13 is
2I13
2314
=
VSD13(sat) =
50201 = 0.25V
KP' (W13/L13)
which exactly meets the specification. For proper mirroring, the W/L ratio of M14 is,
W 9 I9 W 14
L9 = I14 L14 = 1.46
Since W9/L9 was selected as 1, this is close enough.
The parameters are gds7 = 1S, gds8 = 0.8S, gds13 = 15.7S and gds14 = 12.56S.
Therefore small signal voltage gain is (RI rds9 because M7 is part of a cascode conf.)
vout gm1 gm14 125.6 1256.7
vin gds9 gds13+gds14 = 1.8 28.26 = 69.7844.47 = 3,103V/V
The power dissipation, including Ibias of 20A, is 708W.
The minimum power supply voltage is VT + 3V 1.5V if VT = 0.7V and V 0.25V.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-23

A 1-Volt, Two-Stage Op Amp


Uses a bulk-driven differential input amplifier.
VDD=1V
6000/6
3000/6

6000/6

6000/6
M12

M8 M9
vin-

M10
2000/2

M11
vin+
vout

Cc=30pF
M1 M2

IBias

Rz=1k

Q5

Q6

M3 M4

400/2

400/2

CL
400/2

M7
Fig. 7.6-18

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-24

Performance of the 1-Volt, Two-Stage Op Amp


Specification (VDD=0.5V, VSS=-0.5V)
DC open-loop gain
Power supply current
Unity-gainbandwidth (GB)
Phase margin
Input offset voltage
Input common mode voltage range
Output swing
Positive slew rate
Negative slew rate
THD, closed loop gain of -1V/V
THD, closed loop gain of +1V/V
Spectral noise voltage density

Positive Power Supply Rejection


Negative Power Supply Rejection
CMOS Analog Circuit Design

Measured Performance (CL = 22pF)


49dB (Vicm mid range)
300A
1.3MHz (Vicm mid range)
57 (Vicm mid range)
3mV
-0.475V to 0.450V
-0.475V to 0.491V
+0.7V/sec
-1.6V/sec
-60dB (0.75Vp-p, 1kHz sinewave)
-59dB (0.75Vp-p, 10kHz sinewave)
-59dB (0.75Vp-p, 1kHz sinewave)
-57dB (0.75Vp-p, 10kHz sinewave)
367nV/ Hz @ 1kHz
181nV/ Hz @ 10kHz,
81nV/ Hz @ 100kHz
444nV/ Hz @ 1MHz
61dB at 10kHz, 55dB at 100kHz, 22dB at 1MHz
45dB at 10kHz, 27dB at 100kHz, 5dB at 1MHz
P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-25

Further Considerations of the using the Bulk - Current Driven Bulk


The bulk can be used to reduce the threshold sufficiently to permit low voltage
applications. The key is to keep the substrate current confined.
One possible technique is:

;;
;;

IBB
Reduced Threshold MOSFET

IE

Gate

p+

p+

n+
D
IBB

ICD

ICS

Source

Drain

n-well

p- substrate
Layout

Parasitic BJT

Problem:
Want to limit the BJT current to some value called, Imax.
Therefore,
Imax
IBB = CS + CD + 1

Fig. 7.6-19

T. Lehmann and M. Cassia, 1V Power Supply CMOS Cascode Amplifier, IEEE J. of Solid-State Circuits, Vol. 36, No. 7, 2001
CMOS Analog Circuit Design
P.E. Allen - 2004
Chapter 7 Section 6 (5/2/04)

Current-Driven Bulk Technique - Continued


Bias circuit for keeping the Imax defined
independent of BJT betas.

Page 7.6-26

VDD
VBias1
M7

M3

IS,E
M6

Note:
ID,C = ICD + ID
IS,E = ID + IE + IR

ID,C
M8
VBias2

R
IBB

M5

M1

M2
M4

IR

VBias
-

The circuit feedback causes a bulk bias current


VSS
Fig. 7.6-20
IBB and hence a bias voltage VBIAS such that
IS,E = ID + IBB(1+CS + CD) + IR regardless of the actual values of the s.
Use VBias1 and VBias2 to set ID,C 1.1ID , IS,E 1.3ID and IR 0.1ID which sets Imax
at 0.1ID.
For the circuit to work,
VBE < VTN + IRR and |VTP| + VDS(sat) < VTN + IRR
If |VTP| > VTN, then the level shifter IRR can be eliminated.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-27

A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique


VDD
VBiasP
M6
+
vin

M12

M9

M10

M13

Cx
M1

M11

M17

M2

vout

CL
M7

VBiasN M3

M5

M4

M14

M15

VSS

M8

M16
Fig. 7.6-21

Transistors with forward-biased bulks are in a shaded box.


For large common mode input changes, Cx, is necessary to avoid slewing in the input
stage.
To get more voltage headroom at the output, the transistors of the cascode mirror have
their bulks current driven.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-28

A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique Continued


Experimental results:
0.5m CMOS, 40A total bias current (Cx = 10pF)
Supply Voltage
1.0V
0.8V
0.7V
Common-mode 0.0V-0.65V 0.0V-0.4V 0.0V-0.3V
input range
High gain output
0.35V0.25V-0.5V 0.2V-0.4V
range
0.75V
Output saturation 0.1V-0.9V
0.15V0.1V-0.6V
limits
0.65V
DC gain
62dB-69dB 46dB-53dB 33dB-36dB
Gain-Bandwidth
2.0MHz
0.8MHz
1.3MHz
Slew-Rate
0.5V/s
0.4V/s
0.1V/s
(CL=20pF)
Phase margin
57
54
48
(CL=20pF)
The nominal value of bulk current is 10nA gives a 10% increase in differential pair
quiescent current assuming a BJT of 100.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 6 (5/2/04)

Page 7.6-29

SUMMARY
Integrated circuit power supplies are rapidly decreasing (today 2-3Volts)
Classical analog circuit design techniques begin to deteriorate at 1.5-2 Volts
Approaches for lower voltage circuits:
- Use natural NMOS transistors (VT 0.1V)
- Drive the bulk terminal
- Forward bias the bulk
- Use depeletion devices
The dynamic range will be compressed if the noise is not also reduced
Fortunately, the threshold reduction continues to allow the techniques of this section to
be used in todays technology

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 7 Section 7 (5/2/04)

Page 7.7-1

CHAPTER 7 - SUMMARY
This chapter has considered improved op amp performance in the areas of:
Op amps that can drive low output load resistances and large output capacitances
Op amps with improved bandwidth
Op amps with differential output
Op amps having low power dissipation
Op amps having low noise
Op amps that can work at low voltages
The objective of this chapter has been to show how to improve the performance of an op
amp.
We found that improvements are always possible
The key is to balance the tradeoffs against the particular performance improvement
This chapter is an excellent example of the degrees of freedom and choices that
different circuit architectures can offer.
We also illustrated further the approaches to designing op amps
The next chapter begins the transition from analog to digital with the introduction of the
comparator.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Introduction (5/2/04)

Page 8.0-1

CHAPTER 8 COMPARATORS
Chapter Outline
8.1 Characterization of Comparators
8.2 Two-Stage, Open-Loop Comparators
8.3 Other Open-Loop Comparators
8.4 Improving the Performance of Open-Loop Comparators
8.5 Discrete-Time Comparators
8.6 High-Speed Comparators
8.7 Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-1

SECTION 8.1 CHARACTERIZATION OF COMPARATORS


Objective
The objective of this section is:
1.) Introduction to the comparator
2.) Characterization of the comparator
Outline
Static characterization
Dynamic characterization
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-2

What is a Comparator?
The comparator is essentially a 1-bit analog-digital converter.
Input is analog
Output is digital
Types of comparators:
Open-loop (op amps without compensation)
Regenerative (use of positive feedback - latches)
Combination of open-loop and regenerative comparators

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-3

Circuit Symbol for a Comparator

vP
vN

+
-

vO
Fig. 8.1-1

Static Characteristics
Gain
Output high and low states
Input resolution
Offset
Noise
Dynamic Characteristics
Propagation delay
Slew rate

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-4

Noninverting and Inverting Comparators


The comparator output is binary with the two-level outputs defined as,
VOH = the high output of the comparator
VOL = the low level output of the comparator
Voltage transfer function of an Noninverting and Inverting Comparator:
vo

vo
VOH

VOH

vP-vN

vP-vN

VOL

VOL

Noninverting Comparator

Inverting Comparator
Fig. 8.1-2A

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-5

Static Characteristics - Zero-order Model for a Comparator


Voltage transfer function curve:
vo
VOH
vP-vN
VOL

Fig. 8.1-2

Model:
vP

+
vP-vN

vN

f0(vP-vN)

+
vO

Comparator
VOH for (vP-vN) > 0
f0(vP-vN) =
VOL for (vP-vN) < 0

Fig. 8.1-3

VOH-VOL
where V is the input voltage change
V
V 0

Gain = Av = lim
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-6

Static Characteristics - First-Order Model for a Comparator


Voltage transfer curve:
vo
VOH
VIL

vP-vN

VIH
VOL

Fig. 8.1-4

where for a noninverting comparator,


VIH = smallest input voltage at which the output voltage is VOH
VIL = largest input voltage at which the output voltage is VOL
Model:
vP

+
vP-vN

vN

f1(vP-vN)

+
vO

VOH VOL
The voltage gain is Av = VIH VIL

Comparator
VOH for (vP-vN) > VIH
f1(vP-vN) = Av(vP-vN) for VIL< (vP-vN)<VIH
VOL for (vP-vN) < VIL
Fig. 8.1-5
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-7

Static Characteristics - First-Order Model including Input Offset Voltage


Voltage transfer curve:
vo
VOH

VOS
VIL

vP-vN

VIH
VOL

Fig. 8.1-6

VOH+VOL
VOS = the input voltage necessary to make the output equal
when vP = vN.
2
Model:
vP

+vP'
VOSv '-v '
P N

vN

-v '
N

f1(vP'-vN')

Comparator

+
vO
Fig. 8.1-7

Other aspects of the model:


ICMR = input common mode voltage range (all transistors remain in saturation)
Rin = input differential resistance
Ricm = common mode input resistance
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-8

;;

Static Characteristics - Comparator Noise


Noise of a comparator is modeled as if the comparator were biased in the transition
region.
vo

VOH

Rms Noise

vP-vN

VOL

Transition Uncertainty

Fig. 8.1-8

Noise leads to an uncertainty in the transition region which causes jitter or phase noise.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-9

Dynamic Characteristics - Propagation Time Delay


Rising propagation delay time:
vo
VOH
V +V
vo = OH OL
t 2
VOL
vi = vP-vN
VIH
tp
VIL

Propagation delay time =

CMOS Analog Circuit Design

V +V
vi = IH IL
2
t
Fig. 8.1-9

Rising propagation delay time + Falling propagation delay time


2

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-10

Dynamic Characteristics - Single-Pole Response


Model:
Av(0) Av(0)
= s +1
Av(s) = s
c
c + 1
where
Av(0) = dc voltage gain of the comparator
1
c = c = -3dB frequency of the comparator or the magnitude of the pole
Step Response:
vo(t) = Av(0) [1 - e-t/c]Vin
where
Vin = the magnitude of the step input.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-11

Dynamic Characteristics - Propagation Time Delay


The rising propagation time delay for a single-pole comparator is:
VOH-VOL

1
-t
/
c]V

p
=
A
(0)
[1
e

t
=

ln
v
in
p
c
VOH -VOL
2

1 - 2Av(0)Vin
Define the minimum input voltage to the comparator as,
VOH -VOL

tp = c ln V (min)
Vin(min) = Av(0)
in

1- 2Vin
Define k as the ratio of the input step voltage, Vin, to the minimum input voltage, Vin(min),
Vin
2k
k = Vin(min)

tp = c ln 2k-1
Thus, if k = 1, tp = 0.693c.
vout
Illustration:
VOH

Obviously, the more overdrive vin


applied to the input, the smaller
the propagation delay time.
CMOS Analog Circuit Design

+
-

vout

Vin > Vin(min)

VOH+VOL
2
Vin = Vin(min)

VOL
0 t t (max)
0 p p

t
Fig. 8.1-10
P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-12

Dynamic Characteristics - Slew Rate of a Comparator


If the rate of rise or fall of a comparator becomes large, the dynamics may be limited by
the slew rate.
Slew rate comes from the relationship,
dv
i = C dt
where i is the current through a capacitor and v is the voltage across it.
If the current becomes limited, then the voltage rate becomes limited.
Therefore for a comparator that is slew rate limited we have,
V VOH- VOL
tp = T = SR = 2SR
where
SR = slew rate of the comparator.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 1 (5/2/04)

Page 8.1-13

Example 8.1-1 - Propagation Delay Time of a Comparator


Find the propagation delay time of an open loop comparator that has a dominant pole
at 103 radians/sec, a dc gain of 104, a slew rate of 1V/s, and a binary output voltage
swing of 1V. Assume the applied input voltage is 10mV.
Solution
The input resolution for this comparator is 1V/104 or 0.1mV. Therefore, the 10mV
input is 100 times larger than vin(min) giving a k of 100. Therefore, we get
2100
200
1
tp = 103 ln2100-1 = 10-3 ln199 = 5.01s

For slew rate considerations, we get


1
tp = 21x106 = 0.5s
Therefore, the propagation delay time for this case is the larger or 5.01s.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-1

SECTION 8.2 TWO-STAGE OPEN-LOOP COMPARATORS


Objective
The objective of this section is:
1.) Illustrate the performance and design of a two-stage open-loop comparator
Outline
Two-stage, open-loop comparator performance
Initial states of the two-stage, open-loop comparator
Propagation delay time of a slewing, two-stage, open-loop comparator
Design of a two-stage, open-loop comparator
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-2

Two-Stage Comparator
An important category of comparators are those which use a high-gain stage to drive
their outputs between VOH and VOL for very small input voltage changes.
The two-stage op amp without compensation is an excellent implementation of a highgain, open-loop comparator.
VDD

M3

vin
+

M1

M6
vout

M2

CL
+
VBias
-

CMOS Analog Circuit Design

M4

M7

M5
VSS

Fig. 8.2-1

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-3

Performance of the Two-Stage, Open-Loop Comparator


We know the performance should be similar to the uncompensated two-stage op amp.
Emphasis on comparator performance:
Maximum output voltage

8I7

1 - (V -V (min)-|V |)2
VOH = VDD - (VDD-VG6(min)-|VTP|)1 6 DD G6
TP
Minimum output voltage
VOL = VSS
Small-signal voltage gain

gm1 gm6

Av(0) = gds2+gds4gds6+gds7

Poles
Input:
Output:
-(gds2+gds4)
-(gds6+gds7)
p
=
p1 =
2
CI
CII
Frequency response
Av(0)
Av(s) = s
s

p - 1 p - 1
1
2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-4

Example 8.2-1 - Performance of a Two-Stage Comparator


Evaluate VOH, VOL, Av(0), Vin(min), p1, p2, for the two-stage comparator in Fig. 8.2-1.
Assume that this comparator is the circuit of Ex. 6.3-1 with no compensation capacitor,
Cc, and the minimum value of VG6 = 0V. Also, assume that CI = 0.2pF and CII = 5pF.
Solution
Using the above relations, we find that

VOH = 2.5 - (2.5-0-0.7) 1 -

8234x10-6
= 2.2V
1 - 50x10-6
2
38(2.5-0-0.7)
The value of VOL is -2.5V. The gain was evaluated in Ex. 6.3-1 as Av(0) = 7696.
Therefore, the input resolution is
VOH-VOL 4.7V
Vin(min) = Av(0) = 7696 = 0.611mV
Next, we find the poles of the comparator, p1 and p2. From Ex. 6.3-1 we find that
gds2 + gds4
15x10-6(0.04+0.05)
p1 = =
= -6.75x106 (1.074MHz)
CI
0.2x10-12
and
gds6 + gds7
95x10-6(0.04+0.05)
=
= -1.71x106 (0.272MHz)
p2 = CII
5x10-12
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-5

Linear Step Response of the Two-Stage Comparator


The step response of a circuit with two real poles (p1 p2) is,

p2etp1 p1etp2

vout(t) = Av(0)Vin1 + p -p - p -p

1 2
1 2
Normalizing gives,
p2
vout(t)
m
1
vout(tn ) = A (0)V = 1 - m-1e-tn + m-1e-mtn where m = p 1 and
v
in
1
t
p
t
p
-t
1
1
If p1 = p2 (m =1), then
vout(tn) = 1 - e + tp1e = 1 - e n - tne-tn

tn = -tp1

Normalized Output Voltage

m=4
0.8

m=2

m = 1 m = 0.5

m = 0.25

0.6
0.4

p2
m= p
1
0.2
0

2
4
6
Normalized Time (tn = -tp1 )

10
Fig. 8.2-2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-6

Linear Step Response of the Two-Stage Comparator - Continued


The above results are valid as long as the slope of the linear response does not exceed the
slew rate.
Slope at t = 0 is zero
Maximum slope occurs at (m 1)
ln(m)
tn(max) = m-1
and is
dvout(tn(max)) m -ln(m)

ln(m)
exp
- exp -m
=
dtn
m-1 m-1
m-1

For the two-stage comparator using NMOS input transistors, the slew rate is
I7
SR- = CII
SR+

I6-I7 0.56(VDD-VG6(min)-|VTP|)2 - I7
= CII =
CII

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-7

Example 8.2-2 - Step Response of Ex. 8.2-1


Find the maximum slope of Ex. 8.2-1 and the time at which it occurs if the magnitude
of the input step is vin(min). If the dc bias current in M7 is 100A, at what value of load
capacitance, CL would the transient response become slew limited? If the magnitude of
the input step is 100vin(min), what is the new value of CL at which slewing would occur?
Solution
The poles of the comparator were given in Ex. 8.2-1 as p1 = -6.75x106 rads/sec. and
p2 = -1.71x106 rads/sec. This gives a value of m = 0.253. From the previous expressions,
the maximum slope occurs at tn(max) = 1.84 secs. Dividing by |p1| gives t(max) =
0.272s. The slope of the transient response at this time is found as
dvout(tn(max))
= -0.338[exp(-1.84) - exp(-0.2531.84)] = 0.159 V/sec
dtn
Multiplying the above by |p1| gives
dvout(t(max))
= 1.072V/s
dt
Therefore, if the slew rate is less than 1.072V/s, the transient response will experience
slewing. Also, if CL 100A/1.072V/s or 93.3pF, the comparator will slew.
If the input is 100vin(min), then we must unnormalize the output slope as follows.
vin dvout(t( max))
dvout(t( max))
=
= 1001.072V/s = 107.2V/s
vin(min)
dt
dt
Therefore, the comparator will now slew with a load capacitance of 0.933pF.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-8

Propagation Delay Time (Non-Slew)


To find tp, we want to set 0.5(VOH-VOL) equal to vout(tn). However, vout(tn) given as

m
1
vout(tn) = Av(0)Vin 1 - m-1e-tn + m-1e-mtn
cant be easily solved so approximate the step response as a power series to get

tn2
m2tn2 mtn2Av(0)Vin
m
1

vout(tn) Av(0)Vin1 - m-11-tn+ 2 + + m-11-mtn+ 2 +


2
Therefore, set vout(tn) = 0.5(VOH-VOL)
VOH+VOL mtpn2Av(0)Vin

2
2
or
Vin(min)
1
=
mVin
mk
This approximation is particularly good for large values of k.
tpn

VOH+VOL
mAv(0)Vin =

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-9

Normalized Output Voltage

Example 8.2-3 - Propagation Delay Time of a Two-Pole Comparator (Non-Slew)


Find the propagation time delay of Ex. 8.2-1 if Vin = 10mV, 100mV and 1V.
Solution
From Ex. 8.2-1 we know
that Vin(min) = 0.611mV and m
1
m=4
= 0.253. For Vin = 10mV, k =
16.366 which gives tpn 0.491.
0.8
m=2
m = 1 m = 0.5
The propagation time delay is
m = 0.25
equal to 0.491/6.75x106 or
0.6
72.9nS. This corresponds well
with Fig. 8.2-2 where the
0.4
normalized propagation time
p2
m= p
delay is the time at which the
1
0.2
amplitude is 1/2k or 0.031
which corresponds to tpn of
1 = 0.031
approximately 0.5. Similarly, 2k
0
0
2
4
6
8
10
for Vin = 100mV and 1V we get
0.52
Normalized Time (tn = tp1 = t/1)
a propagation time delay of
tp = 0.52 = 77ns
Fig. 8.2-2A
6.75x106
23ns and 7.3ns, respectively.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-10

Initial Operating States for the Two-Stage, Open-Loop Comparator


What are the initial operating states for
VDD
the two-stage, open-loop comparator?
i4

i3
M3

i1
vG1

M1

M4 vo1

M6

CI

i2
M2

vG2

vout

1.) Assume vG2 = VREF and vG1>VREF


CII
ISS
with i1 < ISS and i2>0.
+
M7
M5
VBias
Initially, i4 > i2 and vo1 increases,
M4 becomes active and i4 decreases
VSS
Fig. 8.2-3
until i3 = i4. vo1 is in the range of,
vG1 > VREF, i1 < ISS and i2 > 0
VDD - VSD4(sat) < vo1 < VDD,
and the value of vout is
vG1 > VREF, i1 < ISS and i2 > 0
vout VSS
2.) Assume vG2 = VREF and vG1 >>VREF, therefore i1 = ISS and i2 = 0 which gives
and
vout = VSS
vo1 = VDD
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-11

Initial Operating States - Continued


3.) Assume vG2 = VREF and vG1 < VREF with i1>0 and i2<ISS.
Initially, i4 < i2 and vo1 decreases. When vo1 VREF - VTN, M2 becomes active and
i2 decreases. When i1 = i2 = ISS/2 the circuit stabilizes and vo1 is in the range of,
VREF - VGS2 < vo1 < VREF - VGS2 + VDS2(sat)
or
vG1 < VG2, i1 > 0 and i2 < ISS
VS2 < vo1 < VS2 + VDS2(sat),
For the above conditions,

vout = VDD - (VDD-vo1-|VTP|)1

7ISS
1
56(VDD-vo1-|VTP|)2
4.) Assume vG2 = VREF and vG1 << VREF, therefore i2 = ISS and i1 = 0.
Same as in 3.) but now as vo1 approaches vS2 with ISS/2 flowing, the value of vGS2
becomes larger and M5 becomes active and ISS decreases. In the limit, ISS 0,vDS2 0
and vDS5 0 resulting in
vo1 VSS and
vout = VDD - (VDD-VSS

7ISS
|VTP|)1 1

56(VDD-VSS-|VTP|)2
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-12

Initial Operating States - Continued


5.) Assume vG1 = VREF and vG2>VREF with i2 < ISS and i1>0.
Initially, i4 < i2 and vo1 falls, M2 becomes active and i2 decreases until i1 = i2 = ISS/2.
Therefore,
VREF - VGS2(ISS/2) < vo1 < VREF - VGS2(ISS/2) +VDS2(sat)
or
VS2(ISS/2) < vo1 < VS2(ISS/2) + VDS2(sat), vG2 > VREF, i1 > 0 and i2 < ISS
and the value of vout is

7ISS
vout = VDD - (VDD-vo1-|VTP|)1 1

56(VDD-vo1-|VTP|)2
6.) Assume that vG1 = VREF and vG2 >> VREF. When the source voltage of M1 or M2
causes M5 to be active, then ISS decreases and

7ISS
vo1 VSS and vout = VDD - (VDD-VSS-|VTP|)1 1

56(VDD -VSS-|VTP|)2
7.) Assume vG1 = VREF and vG2 < VREF and i1 <ISS and i2 > 0. Consequently, i4>i2
which causes vo1 to increase. When M4 becomes active i4 decreases until i2 = i4 at
which vo1 stabilizes at (M6 will be off under these conditions and vout VSS).
vG2 < VREF, i1 < ISS and i2 > 0
VDD - VSD4(sat) < vo1 < VDD,
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-13

Initial Operating States - Continued


8.) Finally if vG2 <<VREF, then i1 = ISS and i2 =0 and
vo1 VDD
and
vout VSS.
Summary of the Initial Operating States of the Two-Stage, Open-Loop Comparator using
a N-channel, Source-coupled Input Pair:
Conditions

Initial State of vo1

Initial State of vout

vG1>VG2, i1<ISS and i2>0

VDD-VSD4(sat) < vo1 < VDD

vG1>>VG2, i1=ISS and i2=0

VDD

VSS
VSS

vo1=VG2-VGS2,act(ISS/2), VSS if M5 Eq. (19), Sec. 5.1 for PMOS


act.
vG1<<VG2, i1>0 and i2<ISS
VSS
Eq. (19), Sec. 5.1 for PMOS
vG2>VG1, i1>0 and i2<ISS VS2(ISS/2)<vo1<VS2(ISS/2)+VDS2(sat) Eq. (19), Sec. 5.1 for PMOS
vG1<VG2, i1>0 and i2<ISS

vG2>>VG1, i1>0 and i2<ISS

VG1-VGS1(ISS/2) , VSS if M5 active

Eq. (19), Sec. 5.1 for PMOS

vG2<VG1, i1<ISS and i2>0

VDD-VSD4(sat) < vo1 < VDD

vG2<<VG1, i1=ISS and i2=0

VDD

VSS
VSS

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-14

Trip Point of an Inverter


In order to determine the propagation delay time, it is
necessary to know when the second stage of the two-stage
comparator begins to turn on.
Second stage:
Trip point:
VBias
Assume that M6 and M7 are saturated. (We know that the
steepest slope occurs for this condition.)
Equate i6 to i7 and solve for vin which becomes the trip point.

vin = VTRP = VDD - |VTP| -

VDD
M6
i6

+
vin
-

vout

i7
M7

VSS

Fig. 8.2-4

KN(W7/L7)
KP(W6/L6) (VBias- VSS -VTN)

Example:
If W7/L7 = W6/L6, VDD = 2.5V, VSS = -2.5V, and VBias = 0V the trip point for the
circuit above is
VTRP = 2.5 - 0.7 - 110/50 (0 +2.5 -0.7) = -0.870V

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-15

Propagation Delay Time of a Slewing, Two-Stage, Open-Loop Comparator


Previously we calculated the propagation delay time for a nonslewing comparator.
If the comparator slews, then the propagation delay time is found from
dvi
vi
ii = Ci dti = Ci ti
where
Ci is the capacitance to ground at the output of the i-th stage
The propagation delay time of the i-th stage is,
Vi
ti = ti = Ci Ii
The propagation delay time is found by summing the delays of each stage.
tp = t1 + t2 + t3 +

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-16

Example 8.2-5 - Propagation Time Delay of a Two-Stage, Open-Loop Comparator


For the two-stage comparator shown
VDD = 2.5V
assume that CI = 0.2pF and CII = 5pF.
M6
M3
M4
4.5m
4.5m
38m
Also, assume that vG1 = 0V and that vG2
1m
1m
1m
vo1
has the waveform shown. If the input
vout
voltage is large enough to cause slew to
CI =
M2
vG1 M1 3m
dominate, find the propagation time delay 30A
3m
CII =
0.2pF
1m
1m
5pF
of the rising and falling output of the
vG2
234A
comparator and give the propagation time
delay of the comparator.
30A
4.5m
1m

vG2
2.5V
0V

0.2

-2.5V

0.4

0.6

t(s)

M8

4.5m
M5 1m
VSS = -2.5V

35m
1m

M7
Fig. 8.2-5A

Fig. 8.2-5

Solution
1.) Total delay = sum of the first and second stage delays, t1 and t2
2.) First, consider the change of vG2 from -2.5V to 2.5V at 0.2s.
The last row of Table 8.2-1 gives vo1 = +2.5V and vout = -2.5V
3.) tf1, requires CI, Vo1, and I5. CI = 0.2pF, I5 = 30A and V1 can be calculated by
finding the trip point of the output stage/
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-17

Example 8.2-5 - Continued


4.) The trip point of the output stage by setting the current of M6 when saturated equal
to 234A.
6

2342
2 = 234A V
(V
-|V
|)
=
0.7
+
SG6
5038 = 1.196V
2 SG6 TP
Therefore, the trip point of the second stage is VTRP2 = 2.5 - 1.196 = 1.304V
Therefore, V1 = 2.5V - 1.304V = VSG6 = 1.196V. Thus the falling propagation time
delay of the first stage is
1.196V
tfo1 = 0.2pF 30A = 8 ns
5.) The rising propagation time delay of the second stage requires CII, Vout, and I6. CII
is given as 5pF, Vout = 2.5V (assuming the trip point of the circuit connected to the
output of the comparator is 0V), and I6 can be found as follows:
VG6(guess) 0.5[VG6(I6=234A) + VG6(min)]
215
VG6(min) = VG1 - VGS1(ISS/2) + VDS2 -VGS1(ISS/2) = -0.7 - 1103 = -1.00V
VG6(guess) 0.5(1.304V-1.00V) = 0.152V
6
3850
Therefore VSG6 = 2.348V and I6 = 2 (VSG6-|VTP|)2 = 2 (2.348 - 0.7)2 = 2,580A
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-18

Example 8.2-5 - Continued


6.) The rising propagation time delay for the output can expressed as

2.5V
trout = 5pF 2,580A-234A = 5.3 ns
Thus the total propagation time delay of the rising output of the comparator is
approximately 13.3 ns and most of this delay is attributable to the first stage.
7.) Next consider the change of vG2 from 2.5V to -2.5V which occurs at 0.4s. We shall
assume that vG2 has been at 2.5V long enough for the conditions of Table 8.2-1 to be
valid. Therefore, vo1 VSS = -2.5V and vout VDD. The propagation time delays for the
first and second stages are calculated as
3V
vout
1.304V-(-1.00V)

= 15.4 ns 2V
tro1 = 0.2pF
30A

V
= 1.304V
TRP6

2.5V
tfout = 5pF 234A = 53.42ns
8.) The total propagation time delay of the
falling output is 68.82 ns. Taking the
average of the rising and falling propagation
time delays gives a propagation time delay
for this two-stage, open-loop comparator of
about 41.06ns.

CMOS Analog Circuit Design

1V
0V
-1V
-2V

vo1

Rising prop.
delay time
-3V
200ns
300ns

Falling prop.
delay time
400ns
Time

500ns

600ns
Fig. 8.2-6

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-19

Design of a Two-Stage, Open-Loop Comparator


Table 8.2-2 Design of the Two-Stage, Open-Loop Comparator of Fig. 8.2-3 for a Linear
Response.
Specifications: tp, CII ,Vin(min), VOH, VOL, Vicm+, Vicm-, and overdrive Constraints: Technology, VDD and VSS
Step
1

Design Relationships
|pII|CII
1
|pI| = |pII| =
,
and I7 = I6 = +
N P
tp mk
W6
2I6
W7
2I7
and
=
L6 = K (V
L
2
7 KN(VDS7(sat))2
P SD6(sat))
2C I
Guess CI as 0.1pF to 0.5pF
I5 = I7 C
II

I5
W3 W 4
=
=
L3 L4 K (V
2
P SG3-|VTP|)

Av(0)(gds2+gds4)(gds6+gds7) W 1 W 2 gm12
L1 = L2 = KNI5
gm6
Find CI and check assumption
gm1 =

CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4
2I5
W5
VDS5(sat) = Vicm--VGS1-VSS L =
5 KN(VDS5(sat))2

Comments
Choose m = 1

VSD6(sat) = VDD-VOH
VDS7(sat) = VOL - VSS
A result of choosing m = 1.
Will check CI later
VSG3 = VDD-Vicm++VTN

gm6 =

2KPW6I6
VOH-VOL
A
(0)
=
v
L6
Vin(min)

If CI is greater than the guess in step 3, then


increase CI and repeat steps 4 through 6
If VDS5(sat) is less than 100mV, increase W1/L1.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-20

Example 8.2-6 - Two-Stage, Open-Loop Comparator Design for a Linear Response.


Assume the specifications of the
VDD
comparator shown are given below.
i4
i3
VOH = 2V VOL = -2V
tp = 50ns
M3
M4 vo1
VSS = -2.5V CII = 5pF
VDD = 2.5V
M6
C
i
I
i
+
1
2
Vin(min) = 1mV Vicm = 2V Vicm = -1.25V
vout
Also assume that the overdrive will be a factor vG1
vG2
M1
M2
CII
of 10. Use this architecture to achieve the
I
SS
above specifications and assume that all
+
M7
channel lengths are to be 1m.
M5
VBias
Solution
VSS
Fig. 8.2-3
Following the procedure outlined in Table
8.2-2, we choose m = 1 to get
109
= 6.32x106 rads/sec
|pI| = |pII| =
50 10
This gives
6.32x1065x10-12
I6 = I7 =
= 351A I6 = I7 = 400A
0.04+0.05
Therefore,
W7
W6
2400
2400
=
=
64
and
=
L6 (0.5)250
L7 (0.5)2110 = 29
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-21

Example 8.2-6 - Continued


Next, we guess CI = 0.2pF. This gives I5 = 32A and we will increase it to 40A
for a margin of safety. Step 4 gives VSG3 as 1.2V which results in
W 3 W4
40
=
=
L3 L4 50(1.2-0.7)2 = 3.2

W3 W 4
L3 = L4 = 4

The desired gain is found to be 4000 which gives an input transconductance of


40000.0920
= 162S
gm1 =
44.44
This gives the W/L ratios of M1 and M2 as
W 1 W 2 (162)2
L1 = L2 = 11040 = 5.96

W1 W 2
L1 = L2 = 6

To check the guess for CI we need to calculate it which is done as


CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4 = 0.9fF+1.3fF+119.5fF+20.4fF+36.8fF = 178.9fF
which is less than what was guessed so we will make no changes.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-22

Example 8.2-6 - Continued


Finally, the W/L value of M5 is found by finding VGS1 as 0.946V which gives
VDS5(sat) = 0.304V. This gives
W5
240
=
L5 (0.304)2110 = 7.87 8
Obviously, M5 and M7 cannot be connected gate-gate and source-source. The value of I5
and I7 must be derived separately as illustrated below. The W values are summarized
below assuming that all channel lengths are 1m.
W3 =W4 = 4m
W5 = 8m
W6 = 64m
W7 = 29m
W1 = W2 = 6m
VDD
8/1

10A 2/1
M10

M8
2/1

M11

10A
M5
M9
2/1

40A
40A
8/1

VSS
CMOS Analog Circuit Design

3/1

M12

M7

400A
29/1
Fig. 8.2-7
P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-23

Design of a Two-Stage Comparator for a Slewing Response


Table 8.2-3 Two-Stage, Open-Loop Comparator Design for a Slewing Response.
Specifications: tp, CII ,Vin(min), VOH, VOL, Vicm+, VicmStep

Constraints: Technology, VDD and VSS

Design Relationships
dvout CII(VOH-VOL)
I7 = I6 = CII dt =
tp

Comments
Assume the trip point of the output is (VOHVOL)/2. Let tp1 = tp2 = 0.5tp

W6
2I6
W7
2I7
and L =
L6 = K (V
2
7 KN(VDS7(sat))2
P SD6(sat))
Guess CI as 0.1pF to 0.5pF

VSD6(sat) = VDD-VOH
Typically 0.1pf<CI<0.5pF

dvo1 CI(VOH-VOL)
I5 = CI dt
tp

Assume that vo1 swings between VOH


VOL.

W3 W 4
I5
L3 = L4 = K (V
2
P SG3-|VTP|)

VSG3 = VDD-Vicm++VTN

Av(0)(gds2+gds4)(gds6+gds7) W1 W 2 gm12
L1 = L2 = KNI5
gm6
Find CI and check assumption
CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4

VOH-VOL
Av(0) = V (min)
in
If CI is greater than the guess in step 3, increase
the value of CI and repeat steps 4 through 6

W5
2I5
VDS5(sat) = Vicm--VGS1-VSS L =
5 KN(VDS5(sat))2

If VDS5(sat) is less than 100mV, increase W1/L1.

1
2

gm1 =

7
8

VDS7(sat) = VOL - VSS

gm6 =

and

2KPW6I6
L6

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-24

Example 8.2-7 - Two-Stage, Open-Loop Comparator Design for a Slewing Response


Assume the specifications of Fig. 8.2-3 are given below.
VOH = 2V
VOL = -2V VDD = 2.5V
VSS = -2.5V
tp = 50ns
Vin(min) = 1mV Vicm+ = 2V Vicm- = -1.25V
CII = 5pF
Design a two-stage, open-loop comparator using the circuit of Fig. 8.2-3 to the above
specifications and assume all channel lengths are to be 1m.
Solution
Following the procedure outlined in Table 8.2-3, we calculate I6 and I7 as
5x10-124
I6 = I7 = 50x10-9 = 400A
Therefore,
W7
W6
2400
2400
=
=
64
and
=
L6 (0.5)250
L7 (0.5)2110 = 29
Next, we guess CI = 0.2pF. This gives
0.2pF(4V)
I5 = 20A
I5 = 50ns = 16A
Step 5 gives VSG3 as 1.2V which results in
W 3 W4
W3 W 4
20
=
=
=
1.6

L3 L4 50(1.2-0.7)2
L3 = L4 = 2
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-25

Example 8.2-7 - Continued


The desired gain is found to be 4000 which gives an input transconductance of
40000.0910
= 81S
44.44
This gives the W/L ratios of M1 and M2 as
gm1 =

W 3 W 4 (81)2
L3 = L4 = 11040 = 1.49

W1 W 2
L1 = L2 = 2

To check the guess for CI we need to calculate it which done as


CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4 = 0.9fF+0.4fF+119.5fF+20.4fF+15.3fF = 156.5fF
which is less than what was guessed.
Finally, the W/L value of M5 is found by finding VGS1 as 1.00V which gives VDS5(sat)
= 0.25V. This gives
W5
220
L5 = (0.25)2110 = 5.8 6
As in the previous example, M5 and M7 cannot be connected gate-gate and sourcesource and a scheme like that of Example 8.2-6 must be used. The W values are
summarized below assuming that all channel lengths are 1m.
W6 = 64m
W7 = 29m
W1 = W2 = 2m W3 =W4 = 4m W5 = 6m
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 2 (5/2/04)

Page 8.2-26

SUMMARY
The two-stage, open-loop comparator has two poles which should as large as possible
The transient response of a two-stage, open-loop comparator will be limited by either
the bandwidth or the slew rate
It is important to know the initial states of a two-stage, open-loop comparator when
finding the propagation delay time
If the comparator is gainbandwidth limited then the poles should be as large as possible
for minimum propagation delay time
If the comparator is slew rate limited, then the current sinking and sourcing ability
should be as large as possible

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 3 (5/2/04)

Page 8.3-1

SECTION 8.3 OTHER OPEN-LOOP COMPARATORS


Objective
The objective of this section is:
1.) Show other types of continuous-time, open-loop comparators
Outline
Push-pull comparators
Comparators that can drive large capacitors

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 3 (5/2/04)

Page 8.3-2

Push-Pull Comparators
Clamped:
VDD
M6

M4

M8

M3
vin
+

M1

vout

M2

CL
M5
+
VBias
-

M9

VSS

M7
Fig. 8.3-1

Comments:
Gain reduced Larger input resolution
Push-pull output Higher slew rates

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 3 (5/2/04)

Page 8.3-3

Push-Pull Comparators - Improved


Cascode output stage:
VDD
M6

M4
M15

M8

M3

vin
+

M1

M2

M14

M7
R2

R1
M9

vout

M12
M10

M5
+
VBias
-

CII

M11

M13
VSS

Fig. 8.3-2

Comments:
Can also use the folded cascode architecture
Cascode output stage result in a slow linear response (dominant pole is small)
Poorer noise performance
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 3 (5/2/04)

Page 8.3-4

Comparators that Can Drive Large Capacitive Loads


VDD

M8
M3

M10

M4
M6

vin
+

M1

vout

M2

CII
+
VBias
-

M5

M7
VSS

M9

M11
Fig. 8.3-3

Comments:
Slew rate = 3V/s into 50pF
Linear rise/fall time = 100ns into 50pF
Propagation delay time 1s
Loop gain 32,000 V/V
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 3 (5/2/04)

Page 8.3-5

Self-Biased Differential Amplifier


VDD
VBias

VDD

M6
M6
M4

M3

M4

M3
vin+

vin-

vout

vin+
M1

M1

Extremely
large sourcing
current

vinM2

M2
M5

VBias

M5
VSS

VSS

Fig. 8.3-4

Advantage:
Large sink or source current with out a large quiescent current.
Disadvantage:
Poor common mode range (vin+ slower than vin-)

M. Bazes, Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers, IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, Feb.
1991, pp. 165-168.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-1

SECTION 8.4 IMPROVING THE PERFORMANCE OF


COMPARATORS
Objective
The objective of this section is:
1.) Improve the performance of continuous-time, open-loop comparators
Outline
Autozeroing techniques
Comparators using hysteresis
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-2

Autozeroing Techniques
Use the comparator as an op amp to sample the dc input offset voltage and cancel the
offset during operation.
Ideal
Comparator

Ideal
Comparator

vIN

VOS

Ideal
Comparator

VOS

vOUT

+ VOS
VOS
VOS
+
-C

CAZ

AZ

Model of Comparator.

Autozero Cycle

Comparison Cycle
Fig. 8.4-1

Comments:
The comparator must be stable in the unity-gain mode (self-compensating comparators
are good, the two-stage op comparator would require compensation to be switched in
during the autozero cycle.)
Complete offset cancellation is limited by charge injection

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-3

Differential Implementation of Autozeroed Comparators


1Ideal

vIN-

Comparator

vIN+
2

vOUT

VOS
CAZ 1

Differential Autozeroed Comparator

CMOS Analog Circuit Design

+
VOS
-

vOUT = VOS

VOS
Comparator during 1 phase
vIN
vOUT
+
vIN+ + VOS VOS
Comparator during 2 phase

Fig. 8.4-2

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-4

Single-Ended Autozeroed Comparators


Noninverting:
2
vIN

1 CAZ

- 1
+

vOUT

1
Fig. 8.4-3

Inverting:
CAZ

vIN
2

vOUT
- 1

+
Fig. 8.4-4

Comment on autozeroing:
Need to be careful about noise that gets sampled onto the autozeroing capacitor and is
present on the comparison phase of the process.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-5

Influence of Input Noise on the Comparator


Comparator without hysteresis:
Comparator
threshold

vin
t

VOH

vout
t

VOL

Fig. 8.4-6A

Comparator with hysteresis:


vin

VTRP+

VTRPVOH

vout
t

VOL
CMOS Analog Circuit Design

Fig. 8.4-6B
P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-6

Use of Hysteresis for Comparators in a Noisy Environment


Transfer curve of a comparator with hysteresis:
vOUT

vOUT

VOH

R1 (V -V )
R2 OH OL
0
0

VTRP+
vIN
VTRP-

VOH
VTRP+
vIN

VTRP-

VOL

VOL

Counterclockwise Bistable

Clockwise Bistable

Fig. 8.4-5

Hysteresis is achieved by the use of positive feedback


Externally
Internally

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-7

Noninverting Comparator using External Positive Feedback


vOUT
Circuit:
V

OH

R2
vIN

R1

vOUT

Fig. 8.4-7

-R1VOH
R2

R1 (V -V )
R2 OH OL
0
0

R V
- 1 OL
R2
vIN

VOL

Upper Trip Point:


Assume that vOUT = VOL, the upper trip point occurs when,
R1
R2
R1
+=0 = R +R VOL + R +R VTRP+

V
TRP
R2 VOL
2
2
1
1
Lower Trip Point:
Assume that vOUT = VOH, the lower trip point occurs when,
R1
R2
R1

VTRP- = - R2 VOH
0 = R1+R2VOH + R1+R2VTRP

Width of the bistable characteristic:


R1

Vin = VTRP+-VTRP- = R VOH -VOL


2
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-8

Inverting Comparator using External Positive Feedback


Circuit:
vOUT
vIN

vOUT

R1

R2

VOH

R1 (V -V )
R1+R2 OH OL
0
0

R1VOL
R1+R2

VOL

vIN
R1VOH
R1+R2
Fig. 8.4-8

Upper Trip Point:


R
vIN = VTRP = R +R VOH
+

2
1

Lower Trip Point:


R
vIN = VTRP = R +R VOL
Width of the bistable characteristic:
R1

+
Vin = VTRP -VTRP = R +R VOH -VOL
1
2

2
1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-9

Horizontal Shifting of the CCW Bistable Characteristic


Circuit:
vOUT
VOH

R2
R1

vIN

vOUT

R1+R2
R2 VREF

0
0

VREF
Fig. 8.4-9

R1 (V -V )
R2 OH OL

R1VOH
R2

VOL

vIN

R1|VOL|
R2

Upper Trip Point:


R1
R2
VREF = R +R VOL + R +R VTRP+
2
2
1
1

R1+R2
R1
VTRP+ = R VREF - R VOL
2
2

R1+R2
R1
VTRP- = R2 VREF - R2 VOH

Lower Trip Point:


R1
R2
VREF = R1+R2VOH + R1+R2VTRP

Shifting Factor:
R1+R2

V
R
2 REF

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-10

Horizontal Shifting of the CW Bistable Characteristic


Circuit:
vIN

vOUT

vOUT

R1

R2

VOH

R1 (V -V )
R1+R2 OH OL
R2
R1+R2VREF

0
0

VREF
VOL

R1|VOL|
R1+R2

vIN

R1VOH
R1+R2
Fig. 8.4-10

Upper Trip Point:


R1
R2
vIN = VTRP+ = R +R VOH + R +R V REF
2
2
1
1

Lower Trip Point:


R1
R2
vIN = VTRP- = R1+R2VOL + R1+R2V REF

Shifting Factor:
R
2

R +R VREF
2
1
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-11

Example 8.4-1 Design of an Inverting Comparator with Hysteresis


Use the inverting bistable to design a high-gain, open-loop comparator having an
upper trip point of 1V and a lower trip point of 0V if VOH = 2V and VOL = -2V.
Solution
Putting the values of this example into the above relationships gives
R2
R1
1 = R1+R2 2 + R1+R2VREF

and
R1
R2
0 = R1+R2 (-2) + R1+R2VREF

Solving these two equations gives 3R1 = R2 and VREF = (2/3)V.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-12

Hysteresis using Internal Positive Feedback


Simple comparator with internal positive feedback:
VDD
M3

IBias

M6

M4

M7

vo1

vi1

vo2

M2

M1

M8

vi2

M5
Fig. 8.4-11

VSS

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-13

Internal Positive Feedback - Upper Trip Point


Assume that the gate of M1 is on ground and the
input to M2 is much smaller than zero. The
resulting circuit is:
M1 on, M2 off M3 and M6 on, M4 and M7 off.

VDD

vo1

vo2 is high.

M3 M6

M1

M7 M4

vo2

M2

i1 = i3
i2 = i6
W6/L6
M6 would like to source the current i6 = W L i1
vin
M5
3 3
I5
As vin begins to increase towards the trip point, the
current flow through M2 increases. When i2 = i6,
Fig. 8.4-12A
VSS
the upper trip point will occur.
W 6 /L 6

W6/L6
i5

i5 = i1+i2 = i3+i6 = i3+W /L i3 = i3 1 + W /L i1 = i3 = 1 + [(W /L )/(W /L )]


3
3 3
6 6
3 3
3

Also, i2 = i5 - i1 = i5 - i3
Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives

VTRP+ = vGS2 - vGS1 =


CMOS Analog Circuit Design

2i2

2 + VT2 -

2i1

1 - VT1
P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-14

Internal Positive Feedback - Lower Trip Point


VDD
Assume that the gate of M1 is on ground and the input
to M2 is much greater than zero. The resulting circuit
is:
M3 M6
M7 M4
vo1
vo2
M2 on, M1 off M4 and M7 on, M3 and M6 off.
vo1 is high.
vi1
vi1
M2
W7/L7
M1
i 2 = i4
i1 = i7
M7 would like to source the current i7 = W /L i2
4 4
vin
As vin begins to decrease towards the trip point, the
I5
current flow through M1 increases. When i1 = i7, the
M5
Fig. 8.4-12B
VSS
lower trip point will occur.
W 7 /L 7

W7/L7

i5 = i1+i2 = i7+i4 = W /L i4 +i4 = i4 1 + W /L


4
4 4
4

i5
i2 = i4 = 1 + [(W /L )/(W /L )]
7 7
4 4
Also, i1 = i5 - i2 = i5 - i4
Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
VTRP- = vGS2 - vGS1 =

2i2

2 + VT2 -

2i1

1 - VT1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-15

Example 8.4-2 - Calculation of Trip Voltages for a Comparator with Hysteresis


Consider the circuit shown. Using the
VDD
transistor device parameters given in Table
3.1-2 calculate the positive and negative
M4
M3
M6 M7
threshold points if the device lengths are all 1 IBias
vo1
vo2
m and the widths are given as: W1 = W 2 = W 6
= W 7 = 10 m and W 3 = W 4 = 2 m. The gate
of M1 is tied to ground and the input is the
vi2
vi1
M2
M1
gate of M2. The current, i5 = 20 A
Solution
M8
M5
To calculate the positive trip point,
Fig. 8.4-11
assume that the input has been negative and is
VSS
heading positive.
i5
(W/L)6
20 A
i6 = (W/L)3 i3 = (5/1)(i3) i3 = 1 + [(W/L)6/(W/L)3] = i1 = 1 + 5 = 3.33 A
2i1 1/2
23.33 1/2
i2 = i5 i1 = 20 3.33 = 16.67 A vGS1 = 1 +VT1 = (5)110 +0.7 = 0.81V
2i2 1/2
216.67 1/2
vGS2 = 2 + VT2 = (5)110 + 0.7 = 0.946V
VTRP+ vGS2vGS1 = 0.9460.810 = 0.136V

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-16

Example 8.4-2 - Continued


Determining the negative trip point, similar analysis yields
i4 = 3.33 A
i1 = 16.67 A
vGS2 = 0.81V
vGS1 = 0.946V
VTRP- vGS2 vGS1 = 0.81 0.946 = 0.136V
PSPICE simulation results of this circuit are shown below.
2.6
2.4
2.2
2
vo2
1.8
(volts)
1.6
1.4
1.2
1
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2
vin (volts)

0.3 0.4 0.5


Fig. 8.4-13

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-17

Complete Comparator with Internal Hysteresis


VDD
M3

IBias

M6

M4

M7

M9

M8
vi1
M2

M1

M10
M8

vout

M11
M5
VSS

CMOS Analog Circuit Design

vi2

Fig. 8.4-14

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-18

Schmitt Trigger
The Schmitt trigger is a circuit that has better defined switching points.
Consider the following circuit:
How does this circuit work?
VDD
Assume the input voltage, vin, is low and the output
M5
voltage, vout , is high.
M3, M4 and M5 are on and M1, M2 and M6 are off.
When vin is increased from zero, M2 starts to turn on causing
M4
M3
vout
vin
M3 to start turning off. Positive feedback causes M2 to turn
on further and eventually both M1 and M2 are on and the
M6
output is at zero.
M2
The upper switching point, VTRP+ is found as follows:
When vin is low, the voltage at the source of M2 (M3) is
M1
vS2 = VDD-VTN3
Fig. 8.4-15

VTRP+ = vin when M2 turns on given as VTRP+ = VTN2 + vS2

VTRP+ occurs when the input voltage causes the currents in M3 and M1 to be equal.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-19

Schmitt Trigger Continued


Thus,
iD1 = 1( VTRP+ - VTN1)2 = 3( VDD - vS2- VTN3) 2 = iD3
which can be written as, assuming that VTN2 = VTN3,
VTN1 + 3/1 VDD
1( VTRP+ - VTN1) 2 = 3( VDD VTRP+)2
VTRP+ =
1 + 3/1
The switching point, VTRP- is found in a similar manner and is:
5( VDD - VTRP- - VTP5)2 = 6( VTRP-)2

The bistable characteristic is,

VTRP- =

5/6 (VDD - VTP5)

1 + 5/6

vout

VDD

0 0

VTRP-

VTRP+ VDD

vin

Fig. 8.4-16
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 4 (5/2/04)

Page 8.4-20

SUMMARY
Open-loop, continuous-time comparators can be improved in the areas of:
- Current sinking and sourcing
- Removal of offset voltages
- Removal of the influence of a noisy signal through hysteresis
Comparators with hysteresis (positive feedback)
- External
- Internal

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-1

SECTION 8.5 DISCRETE-TIME COMPARATORS (LATCHES)


Objective
The objective of this section is:
1.) Illustrate discrete-time comparators
2.) Estimate the propagation delay time
Outline
Switched capacitor comparators
Regenerative comparators (latches)
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-2

A Differential Switched Capacitor Comparator Avoiding Common Mode Problems


V1
V2

VC -

+
C
Cp

+
VOS

V1 - VOS
+ -

Vout

A
V2

Cp

VOS
-

Vout

VOS
-

Equivalent circuit when the 2 switches are closed

A switched capacitor comparator

Fig. 8.5-1

1 Phase:
The V1 input is sampled and the dc input offset voltage is autozeroed.
VCp(1) = VOS
VC(1) = V1 - VOS and
2 Phase:
V 2C
(V1-VOS)C VOSCp
Vout(2) =-A C+Cp - C+Cp + C+Cp + AVOS

C
Cp
C
C
= -A (V2-V1) C+C + VOSC+C + C+C + AVOS = -A(V2-V1) C+C A(V1-V2)
p
p
p
p

if Cp is smaller than C.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-3

Differential-In, Differential-Out Switched Capacitor Comparator


C
+

1
- +

2
1

+-

vin

2
1

vout
-

1
Fig. 8.5-2

Comments:
Reduces the influence of charge injection
Eliminates even harmonics

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-4

Regenerative Comparators
Regenerative comparators use positive feedback to accomplish the comparison of two
signals. Latches have a faster switching speed that the previous bistable comparators.
NMOS and PMOS latch:
VDD

VDD
I1

I2

vo1

vo2

vo1

vo2

I1

M2

M1

M2

M1

NMOS latch

I2

PMOS latch

Fig. 8.5-3

How is the input applied to a latch?


The inputs are initially applied to the outputs of the latch.
Vo1 = initial input applied to vo1
Vo2 = initial input applied to vo2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-5

Step Response of a Latch


Circuit:
Ri and Ci are the
resistance and capacitance
seen to ground from the ith transistor.
Nodal equations:

VDD
I1

VDD
I2
vo2

vo1
M1

M2

C1

Vo2
V '
gm1Vo2 R1 so1
-

C2

Vo1

Vo2

V '
gm2Vo1 R2 so2

Fig. 8.5-4

Vo1
gm1Vo2+G1Vo1+sC Vo1- s = gm1Vo2+G1Vo1+sC1V o1-C1Vo1 = 0

Vo2
gm2Vo1+G2Vo2+sC Vo2- s = gm2Vo1+G2Vo2+sC2V o2-C2Vo2 = 0

Solving for Vo1 and Vo2 gives,


1
R1C1
gm1R1
gm1R1
Vo1 = sR1C1+1 Vo1 - sR1C1+1 Vo2 = s1+1 Vo1 - s1+1 Vo2
2
R2C2
gm2R2
gm2R2
Vo2 = sR2C2+1 Vo2 - sR2C2+1 Vo1 = s2+1 Vo2 - s2+1 Vo1
Defining the output, Vo, and input, Vi, as
Vo = Vo2-Vo1 and
Vi = Vo2-Vo1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-6

Step Response of the Latch - Continued


Solving for Vo gives,
gmR

Vo = Vo2-Vo1 = s+1 Vi + s+1 Vo


or
Vi
Vi
1-gmR
Vi
Vo = s+(1-gmR) = s
= s+1
1-gmR + 1
where

= 1-gmR
Taking the inverse Laplace transform gives

vo(t) = Vi e-t/ = Vi e-t(1-gmR) / egmRt/Vi,

if gmR >>1.

Define the latch time constant as


0.67WLCox

C
L = || gmR = gm =
= 0.67Cox
2K(W/L)I
if C Cgs.
Vout(t) = et/L Vi

WL 3
2KI

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-7

Step Response of a Latch - Continued


Normalize the output voltage by (VOH-VOL) to get
Vout(t)
Vi
t/L
=
e
VOH-VOL
VOH-VOL
which is plotted as,
1

0.5
0.4

0.3

0.8

Vout
VOH-VOL

0.2
0.1
0.05

0.6

Vi
VOH-VOL
0.03
0.01

0.4

0.005
0.2
0
0

t
L

5
Fig. 8.5-5

VOH- VOL

The propagation delay time is tp = L ln 2Vi

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-8

Example 8.5-1 - Time domain characteristics of a latch.


Find the time it takes from the time the latch is enabled until the output voltage,
Vout, equals VOH-VOL if the W/L of the latch NMOS transistors is 10m/1m and the
latch dc current is 10A when Vi = 0.1(VOH-VOL) and Vi = 0.01(VOH-VOL). Find the
propagation time delay (Vout=0.5(VOH-VOL)) for the latch for each of these conditions.
Solution
The transconductance of the latch transistors is
gm = 21101010 = 148S
The output conductance is 0.4S which gives gmR of 370V/V. Since gmR is greater than
1, we can use the above results. Therefore the latch time constant is found as
WL 3
(101)x10-18
L = 0.67Cox 2KI = 0.67(24x10-4) 2110x10-610x10-6 = 108ns
If we assume that the propagation time delay is the time for the output to reach (VOHVOL), then for Vi = 0.01(VOH-VOL) that tp = 4.602L = 497ns and for Vi = 0.1(VOH-VOL)
that tp = 2.306L = 249ns.
If we assume that the propagation time delay is the time when the output is 0.5(VOHVOL), then using the above results or Fig. 8.5-5 we find for Vi = 0.01(VOH-VOL) that tp =
3.91L = 422ns and for Vi = 0.1(VOH-VOL) that tp = 1.61L = 174ns.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-9

Comparator using a Latch with a Built-In Threshold


How does it operate?
1.) Devices in shaded region operate in the
1
M7
triode region.
Latch M9
/Reset
2.) When the latch/reset goes high, the upper
1
M5
cross-coupled inverter-latch regenerates. The
drain currents of M5 and M6 are steered to
M3
vout+
obtain a final state determined by the mismatch
R1
between the R1 and R2 resistances.
M2
M1
vin+

W1
W2
1

=
K
L (vin+ - VT) + L (VREF- - VT)
VREFN
R1

and
W

W2
1
1

+
R2 = KN L (vin - VT) + L (VREF - VT)
3.) The input voltage which causes R1 and R2 to be equal is given by
vin(threshold) = (W2/W1)VREF
W2/W1 = 1/4 generates a threshold of 0.25VREF.
Performance 20Ms/s & 200W

VDD
1
M10 Latch
/Reset
1
M6

M8

M4

voutM2

R2

M1
vin-

VREF+
Fig. 8.5-6

T.B. Cho and P.R. Gray, A 10b, 20Msamples/s, 35mW pipeline A/D Converter, IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March
1995.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-10

Simple, Low Power Latched Comparator


VDD
1
M9

M10

M5

M6
vout+

voutM4

M3
vin+

M8

M7

M1

vin-

M2

Fig. 8.5-7

Dissipated 50W when clocked at 2MHz.

A. Coban, 1.5V, 1mW, 98-dB Delta-Sigma ADC, Ph.D. dissertation, School of ECE, Georgia Tech, Atlanta, GA 30332-0250.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-11

Dynamic Latch
Circuit:
VDD
Latch

M8
VREF

M6

M4 +
vout

M3

vin

vout-

M7

M1

Latch

M2
M5
Fig. 8.5-8

Number
of Samples

Input offset voltage distribution:


20
10
0

;;
;;;
;;;
;;
;;;
;;;

= 5.65

-15

L = 1.2m
(0.6m Process)

-10 -5
0
5
10
Input offset voltage (mV)

15
Fig. 8.5-9

Power dissipation/sampling rate = 4.3W/Ms/s


CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 5 (5/2/04)

Page 8.5-12

SUMMARY
Discrete-time comparators must work with clocks
Switched capacitor comparators use op amps to transfer charge and autozero
Regenerative comparators (latches) use positive feedback
The propagation delay of the regenerative comparator is slow at the beginning and
speeds up rapidly as time increases
The highest speed comparators will use a combination of open-loop comparators and
latches

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 6 (5/2/04)

Page 8.6-1

SECTION 8.6 HIGH-SPEED COMPARATORS


Objective
The objective of this presentation is:
1.) Show how to achieve high-speed comparators
Outline
Concepts of high-speed comparators
Amplifier-latch comparators
Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 6 (5/2/04)

Page 8.6-2

Conceptual Illustration of a Cascaded Comparator


How does a cascaded, high-speed comparator work?
A0
sT+1

A0
sT+1

A0
sT+1

A0
sT+1

A0
sT+1

A0
sT+1

Linear
small
signal

Linear
small
signal

Linear
& large
signal

Large
signal
small C

Large
signal
bigger C

Large
signal
big C

Fig. 8.6-1

Assuming a small overdrive,


1.) The initial stage build the driving capability.
2.) The latter stages swing rail-to-rail and build the ability to quickly charge and
discharge capacitance.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 6 (5/2/04)

Page 8.6-3

Minimizing the Propagation Delay Time in Comparators


Fact:
The input signal is equal to Vin(min) for worst case
Amplifiers have a step response with a negative argument in the exponential
Latches have a step response with a positive argument in the exponential
Result:
Use a cascade of linear amplifier to quickly build up the signal level and apply this
amplified signal level to a latch for quick transition to the full binary output swing.
Illustration of a preamplifier and
vout
latch cascade:
VOH
Minimization of tp:
Latch
Q. If the preamplifer consists of n
stages of gain A having a singlePreamplifier
pole response, what is the value of
n and A that gives minimum
VX
propagation delay time?
t1
t2
A. n = 6 and A = 2.62 but this is a
VOL
t
very broad minimum and n is
Fig. 8.6-2
usually 3 and A 6-7 to save area.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 6 (5/2/04)

Page 8.6-4

Fully Differential, Three-Stage Amplifier and Latch Comparator


Circuit:
FB
Reset

Cv1

Reset
C1

Cv3

+ -+

Cv2
C2

FB

FB
Cv5

+ -

+ -+

-+
Reset

Reset

Cv4

FB

+
Latch vout
-

Reset

Cv6
FB

FB

Clock

+ vin -

Fig. 8.6-3

Comments:
Autozero and reset phase followed by comparison phase
More switches are needed to accomplish the reset and autozero of all preamplifiers
simultaneously
Can run as high as 100Msps

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 6 (5/2/04)

Page 8.6-5

Preamplifier and Latch Circuits


Gain:
gm1
gm2
Av = - gm3 = - gm4 = -

VDD

KN(W1/L1)
Kp(W3/L3)

Dominant Pole:
gm3 gm4
|pdominant| = C = C
where C is the capacitance seen from the
output nodes to ground.

M3

FB

M4
Q
Reset
Q

FB
M1

M5

M6

M2

Latch
Enable
If (W1/L1)/(W3/L3) = 100 and the
bias current is 100A, then A = -3.85
Latch
Preamplifier
and the bandwidth is 15.9MHz if C =
0.5pF.
VBias
Comments:
Fig. 8.6-4
If a buffer is used to reduce the output
capacitance, one must take into account the loss of the buffer.
The use of a preamplifier before the latch reduces the latch offset by the gain of the
preamplifier so that the offset is due to the preamplifier only.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 6 (5/2/04)

Page 8.6-6

An Improved Preamplifier
Circuit:
VDD

VBiasP
vout- M5

M3

VBiasP

M4
M6

vout+

Reset
M12

M10

FB M11

FB

M8

M7
VBias

vin+

vin-

M2

M1
VBiasN

M9
Fig. 8.6-5

Gain:
KN(W1/L1)I1
KN(W1/L1)
=
KP(W3/L3)
KP(W3/L3)I3
If I5 = 24I3, the gain is increased by a factor of 5
gm1
Av = - gm3 = -

I5
1+I3

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 6 (5/2/04)

Page 8.6-7

Charge Transfer Preamplifier


The preamplifier can be replaced by the charge transfer circuit shown.
VPR

vin=VREF

vin=VREF VPR

VREF-VT+V

S2
vin-VT
S1
CT

CO

+
vout
-

Charge transfer amplifier.

CT

vin = VREF+V

CO

+
vout
=VPR
-

Precharge phase.

CT

CO

+
vout =VPR -CT V
CO

Amplification phase.

Fig. 8.6-6

Comments:
Only positive values of voltage will be amplified.
Large offset voltages result as a function of the subthreshold current.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 6 (5/2/04)

Page 8.6-8

A CMOS Charge Transfer Preamplifier


Circuit:
VDD

VDD
CT

VPR
S1
M2
S3

S2

vout

vin

CT

S3
S1

M1

CO

Fig. 8.6-7

Comments:
NMOS and PMOS allow both polarities of input
CMOS switches along with dummy switches reduce the charge injection
Switch S3 prevents the subthreshold current influence
Used as a preamplifier in a comparator with 8-bit resolution at 20Msps and a power
dissipation of less than 5W

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 6 (5/2/04)

Page 8.6-9

A High-Speed Comparator
Circuit:
VDD
Self-biased
diff amp Output
Driver
Preamp
vout
vin+
vin-

IBias
Latch
Fig. 8.6-8

Comments:
Designed to have a tp = 10ns with a 5pF load and a 10mV overdrive
Not synchronous
Comparator gain is greater than 2000V/V and the quiescent current was 100A
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 8 Section 7 (5/2/04)

Page 8.7-1

CHAPTER 8 - SUMMARY
Types of Comparators Presented
High-gain, open-loop
Improved high-gain, open-loop, comparators
Hysteresis
Autozeroing
Regenerative comparators
Discrete-time comparators
Performance Characterization
Propagation delay time
Binary output swing
Input resolution and/or gain
Input offset voltage
Power dissipation
Important Principles
The speed of the comparator depends on the linear and slewing responses
The dc input offset voltage depends on the matching and is reduced by autozeroing.
Charge injection is the limit of autozeroing
The comparator gain should be large enough for a binary output when vin = Vin(min)
Cascaded comparators, the first stages should large GB and the last stages high SR
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Switched Capacitor Circuits

5/2/04

CHAPTER 9 SWITCHED CAPACITOR CIRCUITS


Objective
The objective of this presentation is:
1.) Introduce the principles of switched capacitor circuits
2.) Illustrate the application of switched capacitor circuits to filter design
Outline
Section 9.0 - Introduction
Section 9.1 - Switched Capacitor Circuits
Section 9.2 - Switched Capacitor Amplifiers
Section 9.3 - Switched Capacitor Integrators
Section 9.4 - z-domain Models of Two-Phase, Switched Capacitor Circuits, Simulation
Section 9.5 - First-order, Switched Capacitor Circuits
Section 9.6 - Second-order, Switched Capacitor Circuits
Section 9.7 - Switched Capacitor Filters
Section 9.8 - Summary

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.0-1

9.0 - INTRODUCTION

Organization

;;;
;;;
;;;
;;;;
;;;
;;;;;;;;;;
;;;
;;;
;;;;;;
Chapter 10
D/A and A/D
Converters

Chapter 9
Switched Capacitor Circuits

Systems

Chapter 6
Simple CMOS &
BiCMOS OTA's

Chapter 7
High Performance
OTA's

Chapter 8
CMOS/BiCMOS
Comparators

Complex

Simple

Chapter 4
CMOS/BiCMOS
Subcircuits

Chapter 5
CMOS/BiCMOS
Amplifiers

;;;
;;;;
;;;
;;;;;;;;;;
Circuits

Chapter10
1
Chapter
Introduction
D/ to Analog CMOS Design
Devices

CMOS Analog Circuit Design

Chapter
Chapter11
2
Analog
CMOS
Technology
Systems

Chapter 3
CMOS
Modeling

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.0-2

Advantages of Switched Capacitor Circuits


1.) Compatibility with CMOS technology
2.) Good accuracy of time constants
3.) Good voltage linearity
4.) Good temperature characteristics
Disadvantages of Switched Capacitor Circuits
1.) Experience clock feedthrough
2.) Require a nonoverlapping clock
3.) Bandwidth of the signal must be less than the clock frequency
Philosophical Viewpoint
The implementation of switched capacitors in CMOS technology occurred in the early
1970s and represented a major step in implementing practical analog circuits and
systems in an integrated circuit technology.
Switched capacitor circuits are not new.
James Clerk Maxwell used switches and a capacitor to measure the equivalent
resistance of a galvanometer in the 1860s.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-1

SECTION 9.1 SWITCHED CAPACITOR CIRCUITS


RESISTOR EMULATION
Parallel Switched Capacitor Equivalent Resistor
i1(t)
v1(t)

vC (t)

i1(t)

i2 (t)

v2 (t)

v1(t)

i2 (t)
v2 (t)
Fig 9.1-01

Two-Phase, Nonoverlapping Clock:


1

1
t

0
2

1
0
0

T/2

3T/2 2T

Fig. 9.1-02
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-2

Equivalent Resistance of a Switched Capacitor Circuit


Assume that v1(t) and v2(t) are changing slowly with respect to the clock period.
The average current is,
1T
1 T/2
i1(t)
i2 (t)

1
i1(average) = T i1(t)dt = T i1(t)dt
2
0
0
Charge and current are related as,
v (t)
v1(t)
vC (t)
C 2
dq1(t)
i1(t) = dt
Fig. 9.1-03
Substituting this in the above gives,
1 T/2
q1(T/2)-q1(0) CvC(T/2)-CvC(0)
i1(average) = T dq1(t) =
=
T
T
0

However, vC(T/2) = v1(T/2) and vC(0) = v2(0). Therefore,


C [v1(T/2)-v2(0)] C [V1-V2]
i1(t)
i2 (t)
R

T
T
For the continuous time circuit:
v1(t)
v2 (t)
V1-V2
T
i1(average) = R
RC
Fig. 9.1-04
For v1(t) V1 and v2(t) V2, the signal frequency must be much less than fc.
i1(average) =

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-3

Example 9.1-1 - Design of a Parallel Switched Capacitor Resistor Emulation


If the clock frequency of parallel switched capacitor equivalent resistor is 100kHz,
find the value of the capacitor C that will emulate a 1M resistor.
Solution
The period of a 100kHz clock waveform is 10sec. Therefore, using the previous
relationship, we get that
T 10-5
C = R = 106 = 10pF
We know from previous considerations that the area required for 10pF capacitor is much
less than for a 1M resistor when implemented in CMOS technology.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-4

Power Dissipation in the Resistance Emulation


If the switched capacitor
i1(t)
i2 (t)
1
2
circuit is an equivalent
resistance, how is the power
v (t)
v1(t)
vC (t)
dissipated?
C 2

i1(t)

i2 (t)

v1(t)

v2 (t)
Fig 9.1-01

Continuous Time Resistor:


(V1 - V2)2
Power =
R

Discrete Time Resistor Emulation:


If the switches have an ON resistance of Ron, then power dissipated/clock cycle is,
(V1 -V2) T
Power = i1(aver.)(V1-V2) where i1 (aver.) = RonT e-t/(RonC)dt
0

(V1-V2)2 T

Power = TRon

e -t/(RonC)dt

(V1-V2)2

= (T/C)

-e -T /(RonC) + 1

(V1-V2)2
(T/C) if T >> RonC

Thus, if R = T/C, then the power dissipation is identical in the continuous time and
discrete time realizations.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-5

Other SC Equivalent Resistance Circuits


i1(t)
v1(t)

S1

S2

C
vC (t)

Series

i1(t)

i2 (t)

v2 (t)

C1
v1(t)

S1

vC1 (t)

i2 (t)

i1(t)

S2
v2 (t)
vC2(t)

C2
Series-Parallel

v1(t)

S1 C S2 i2 (t)
vC (t)
S1

S2
v2 (t)

Bilinear

Fig. 9.1-05

Series-Parallel:
The current, i1(t), that flows during both the 1 and 2 clocks is:
T
q1(T/2)-q1(0) q1(T)-q1(T/2)
1T
1 T/2
+
i1(average) = T i1(t)dt = T i1(t)dt + i1(t)dt =
T
T

0
0
T/2
Therefore, i1(average) can be written as,
C2 [vC2(T/2)-vC2(0)] C1 [vC1(T)-vC1(T/2)]
+
i1(average) =
T
T
The sequence of switches cause,vC2(0)=V2, vC2(T/2)=V1, vC1(T/2)=0, and vC1(T)= V1-V2.
Applying these results gives
C2[V1-V2] C1[V1-V2- 0] (C1+C2)(V1-V2)
+
=
i1(average) =
T
T
T
T
Equating the average current to the continuous time circuit gives: R = C1 + C2
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-6

Example 9.1-2 - Design of a Series-Parallel Switched Capacitor Resistor Emulation


If C1 = C2 = C, find the value of C that will emulate a 1M resistor if the clock
frequency is 250kHz.
Solution
The period of the clock waveform is 4sec. Using above relationship we find that C
is given as,
T 4x10-6
2C = R = 106 = 4pF
Therefore, C1 = C2 = C = 2pF.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-7

Summary of the Four Switched Capacitor Resistance Circuits


Switched Capacitor
Schematic
Equivalent
Resistor Emulation
Resistance
Circuit
1

Parallel

v1(t) C

v2 (t)

Series

v1(t)

C
1

Series-Parallel

v1(t)

T
C

v2 (t)

T
C1 + C2

C1

C2
2

C
v1(t)

CMOS Analog Circuit Design

v2 (t)

Bilinear

T
C

v2 (t)

T
4C

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-8

Accuracy of Switched Capacitor Circuits


Consider the following continuous time, first-order, lowpass
circuit:

R1

v2
v1
C2
The transfer function of this simple circuit is,
V2(j)
1
1
Fig. 9.1-06
H(j) = V (j) = jR C + 1 = j + 1
1
1 2
1
where 1 = R1C2 is the time constant of the circuit and determines the accuracy.
Continuous Time Accuracy
Let 1 = C. The accuracy of C can be expressed as,
dC dR1 dC2
C = R1 + C2 5% to 20% depending on the size of the components
Discrete Time Accuracy
T
1
Let 1 = D = C1 C2 = fcC1 C2. The accuracy of D can be expressed as,
dD dC2 dC1 dfc
D = C2 - C1 - fc 0.1% to 1% depending on the size of components
The above is the primary reason for the success of switched capacitor circuits in CMOS
technology.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-9

ANALYSIS OF SWITCHED CAPACITOR CIRCUITS


Analysis Methods for Two-Phase, Nonoverlapping Clocks
Sampled Data Voltage Waveforms for a Two-phase Clock:
v*(t)

v(t)

A sampled-data
voltage waveform
for a two-phase
clock.
1

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

t/T

vO(t)
v(t)

A sampled-data
voltage waveform
for the odd-phase
clock.
1

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

A sampled-data v (t)
voltage waveform
for the even-phase
clock.

t/T

v(t)

Fig. 9.1-065

CMOS Analog Circuit Design

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

t/T
P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-10

Analysis Methods for Two-Phase, Nonoverlapping Clocks - Contd


Time-domain Relationships:
The previous figure showed that,
v*(t) = vo(t) + ve(t)
where the superscript o denotes the odd phase (1) and the superscript e denotes the
even phase (2).
For any given sample point, t = nT/2, the above may be expressed as
nT
nT
nT
v* 2 n=1,2,3,4,5,6, = v o 2 n=1,3,5, + v e 2 n=2,4,5,

z-domain Relationships:
Consider the one-sided z-transform of a sequence, v(nT), defined as

V(z) = v(nT)z- n = v(0) + v(T)z- 1 + v(2T)z- 2 +


n=0

for all z for which the series V(z) converges.


Now, this equation can be expressed in the z-domain as
V*(z) = V o(z) + V e(z) .
The z-domain format for switched capacitor circuits will allow the analysis of transfer
functions.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-11

Transfer Function Viewpoint of Switched Capacitor Circuits


Input-output voltages of a general switched capacitor circuit in the z-domain.

Vi (z) =

o
Vi (z)

Switched
Capacitor
Circuit

+ Vi (z)

Vo (z) = Vo (z) + Vo (z)

Fig. 9.1-07

z-domain transfer functions:


j

V o (z)
H ij (z) = i
V i(z)
e

where i and j can be either e or o. For example, Hoe(z) represents Vo (z)/ V i (z) .
Also, a transfer function, H(z) can be defined as
e

Vo(z) Vo(z) + Vo (z)


H(z) = Vi(z) = e
.
o
V i (z) + V i (z)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-12

Approach for Analyzing Switched Capacitor Circuits


1.) Analyze the circuit in the time-domain during a selected phase period.
2.) The resulting equations are based on q = Cv.
3.) Analyze the following phase period carrying over the initial conditions from the
previous analysis.
4.) Identify the time-domain equation that relates the desired voltage variables.
5.) Convert this equation to the z-domain.
6.) Solve for the desired z-domain transfer function.
7.) Replace z by ejT and examine the frequency response.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-13

Example 9.1-3 - Analysis of a Switched Capacitor, First-order, Low pass Filter


Use the above approach to find the z-domain transfer function of the first-order, low
pass switched capacitor circuit shown below. This circuit was developed by replacing
the resistor, R1, of the previous circuit with the parallel switched capacitor resistor circuit.
The timing of the clocks is also shown. This timing is arbitrary and is used to assist the
analysis and does not change the result.
1

v1

C1

C2

v2

Switched capacitor, low pass filter.

1
1
2
2
2
t
n- 23 n-1 n- 21 n n+ 21 n+1 T
Clock phasing for this example.

Fig. 9.1-08

Solution
1: (n-1)T< t < (n-0.5)T
Equivalent circuit:
C2
v1o(n-1)T C1

C2

v2e(n- 23 )T v2o(n-1)T

Equivalent circuit.

v1o(n-1)T C1

v2e(n- 23 )T v2o(n-1)T

Simplified equivalent circuit.

The voltage at the output (across C2) is vo2(n-1)T = ve2 (n-3/2)T


CMOS Analog Circuit Design

Fig. 9.1-09

(1)
P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-14

Example 9.1-3 - Continued


2: (n-0.5)T< t < nT
Equivalent circuit:

C1

e
v1(n-1/2)T

C2
C1 vo(n-1)T
1

v2e(n- 21 )T
v2o(n-1)T
Fig. 9.1-10

The output of this circuit can be expressed as the superposition of two voltage
sources, vo1 (n-1)T and vo2 (n-1)T given as
C1
C2
ve2 (n-1/2)T = C1+C2 vo1 (n-1)T + C1+C2 vo2 (n-1)T.

If we advance Eq. (1) by one full period, T, it can be rewritten as


vo2(n)T = ve2 (n-1/2)T.
Substituting, Eq. (3) into Eq. (2) yields the desired result given as
C1
C2
vo2 (nT) = C +C vo1 (n-1)T + C +C vo2 (n-1)T.
1
2
1
2

(2)
(3)

(4)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-15

Example 9.1-3 - Continued


z-domain Analysis:
The next step is to write the z-domain equivalent expression for Eq. (4). This can be
done term by term using the sequence shifting property given as
(5)
v(n-n1)T z-n1V(z) .
The result is
C1 -1
C2 -1
Vo2(z) = C +C z Vo1(z) + C +C z Vo2(z).
(6)
1
2
1
2
Finally, solving for V2o(z)/Vo1(z) gives the desired z-domain transfer function for the
switched capacitor circuit of this example as
C1
-1

o
z
V2(z)
z-1
C2
C1+C2
oo
-1 , where =
H (z) = o =
=
(7)
C2
1 + - z
C1 .
V 1(z)
-1

1 - z C1+C2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-16

Discrete-Frequency Domain Analysis


Relationship between the continuous and discrete frequency domains:
z = e j T
Illustration:
j
Continuous
time frequency
response

Discrete
time frequency
response

=0
-1

Imaginary Axis
+j1
r=1
=
= -

=0

+1 Real
Axis

= -
Continuous Frequency Domain

-j1
Discrete Frequency Domain
Fig. 9.1-11

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-17

Example 9.1-4 - Frequency Response of Example 9.1-3


Use the results of the previous example to find the magnitude and phase of the
discrete time frequency response for the switched capacitor circuit of Example 3.
Solution
The first step is to replace z in Hoo(z) of Ex. 3 by e jT. The result is given below as
e-jT
1
1
Hooej = 1+- e-jT = (1+)ejT- = (1+)cos(T)- +j(1+)sin(T)
(1)
where we have used Eulers formula to replace e jT by cos(T)+jsin(T). The magnitude
of Eq. (1) is found by taking the square root of the square of the real and imaginary
components of the denominator to give
1
Hoo =
2
2
(1+) cos (T) - 2(1+)cos(T) + 2 + (1+)2sin2(T)
1
= (1+)2[cos2(T)+sin2(T)]+2-2(1+)cos(T)
1
1
(2)
= 1+2+2 -2(1+)cos(T) = 1+2(1+)(1-cos(T)) .
The phase shift of Eq. (1) is expressed as
(1+)sin(T)
sin(T)

(3)
ArgHoo = - tan-1(1+)cos(T)- = - tan-1

cos(T) - 1+
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-18

The Oversampling Assumption


The oversampling assumption is simply to assume that fsignal << fclock = fc.
This means that,
2
1
fsignal = f << T 2f = << T T << 2.
The importance of the oversampling assumption is that is permits the design of switched
capacitor circuits that approximates the continuous time circuit until the signal frequency
begins to approach the clock frequency.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-19

Example 9.1-5 - Design of Switched Capacitor Circuit and Resulting Frequency


Response
Design the first-order, low pass, switched capacitor circuit of Ex. 3 to have a -3dB
frequency at 1kHz. Assume that the clock frequency is 20kHz Plot the frequency
response for the resulting discrete time circuit and compare with a first-order, low pass,
continuous time filter.
Solution
If we assume that T is less than unity, then cos(T) approaches 1 and sin(T)
approaches T. Substituting these approximations into the magnitude response of Eq. (2)
of Ex. 4 results in
1
1
(1)
Hoo(ejT) (1+) - + j(1+) = 1 + j(1+)T .
Comparing this equation to the simple, first-order, low pass continuous time circuit
results in the following relationship which permits the design of the circuit parameter .
1 = (1+)T
(2)
Solving for gives
1
c
fc
= T - 1 = fc1 - 1 = -3dB - 1 = 2-3dB - 1 .
(3)
Using the values given, we see that = (20/6.28)-1 =2.1831. Therefore, C2 = 2.1831C1.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-20

Example 9.1-5 - Continued


Frequency Response of the First-order, Switched Capacitor, Low Pass Circuit:
100

0.8
0.707
0.6

Phase Shift (Degrees)

Magnitude

oo jT

|H (e

)|

0.4
0.2
0

|H(j)|

= 1/1
0

0.2

0.4

/c

0.6

0.8

50

oo jT

Arg[H (e
= 1/1

0
-50

-100

)]

Arg[H(j)]
0

0.2

0.4

/c

0.6

0.8

Fig. 9.1-12

Better results would be obtained if fc > 20kHz.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Page 9.1-21

SUMMARY
Resistance emulation is the replacement of continuous time resistors with switched
capacitor approximations
- Parallel switched capacitor resistor emulation
- Series switched capacitor resistor emulation
- Series-parallel switched capacitor resistor emulation
- Bilinear switched capacitor resistor emulation
Time constant accuracy of switched capacitor circuits is proportional to the
capacitance ratio and the clock frequency
Analysis of switched capacitor circuits includes the following steps:
1.) Analyze the circuit in the time-domain during a selected phase period.
2.) The resulting equations are based on q = Cv.
3.) Analyze the following phase period carrying over the initial conditions from the
previous analysis.
4.) Identify the time-domain equation that relates the desired voltage variables.
5.) Convert this equation to the z-domain.
6.) Solve for the desired z-domain transfer function.
7.) Replace z by ejT and examine the frequency response.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-1

SECTION 9.2 SWITCHED CAPACITOR AMPLIFIERS


CONTINUOUS TIME AMPLIFIERS
Inverting and Noninverting Amplifiers
R2

R1
vIN

vOUT

vIN

R2

R1

vOUT

Fig. 9.2-01

Gain and GB = :
Vout R1+R2
Vin = R1
Gain , GB = :
Avd(0)R1
R1+R2
Vout(s) R1+R2
=

Avd(0)R1
Vin(s) R1
1 + R1+R2
Gain , GB :
GBR1
R1+R2 H
Vout(s) R1+R2 R1+R2

GBR1 = R1 s+H
Vin(s) = R1
s + R1+R2

Vout
R2
=
Vin
R1
R1Avd(0)
R2
Vout(s)
R1+R2

Vin(s)
Avd(0)R1
R1
1 + R1+R2
GBR1
R2 H
Vout(s) R2 R1+R2

=
=

GBR1 - R1 s+H
Vin(s) R1
s + R1+R2

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-2

Example 9.2-1- Accuracy Limitation of Voltage Amplifiers due to a Finite Voltage


Gain
Assume that the noninverting and inverting voltage amplifiers have been designed for
a voltage gain of +10 and -10. If Avd(0) is 1000, find the actual voltage gains for each
amplifier.
Solution
For the noninverting amplifier, the ratio of R2/R1 is 9.
1000
Avd(0)R1/(R1+R2) = 1+9 = 100.
Vout
100
Vin = 10 101 = 9.901 rather than 10.
For the inverting amplifier, the ratio of R2/R1 is 10.
Avd(0)R1 1000
R1+R2 = 1+10 = 90.909
Vout
90.909
Vin = -(10)1+90.909 = - 9.891 rather than -10.

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-3

Example 9.2-2 - -3dB Frequency of Voltage Amplifiers due to Finite UnityGainbandwidth


Assume that the noninverting and inverting voltage amplifiers have been designed for
a voltage gain of +1 and -1. If the unity-gainbandwidth, GB, of the op amps are
2Mrads/sec, find the upper -3dB frequency for each amplifier.
Solution
In both cases, the upper -3dB frequency is given by
GBR1
H = R1+R2
For the noninverting amplifier with an ideal gain of +1, the value of R2/R1 is zero.
H = GB = 2 Mrads/sec (1MHz)
For the inverting amplifier with an ideal gain of -1, the value of R2/R1 is one.
GB1 GB
H = 1+1 = 2 = Mrads/sec (500kHz)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-4

CHARGE AMPLIFIERS
Noninverting and Inverting Charge Amplifiers
C2

C1

vIN

vOUT

C2

C1

vOUT

Noninverting Charge Amplifier

Gain and GB = :
Vout C1+C2
Vin = C2
Gain , GB = :
Avd(0)C2
Vout C1+C2 C1+C2

Vin = C2
Avd(0)C2
1 + C1+C2
Gain , GB :
GBC2
Vout C1+C2 C1+C2
Vin = C2
GBC2
s + C1+C2
CMOS Analog Circuit Design

vIN

Inverting Charge Amplifier

Vout
C1
=
Vin
C2
Avd(0)C2
Vout C1 C1+C2

Vin = -C2
Avd(0)C2
1 + C1+C2
GBC2
Vout C1 C1+C2
Vin = -C2
GBC2
s + C1+C2
P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-5

SWITCHED CAPACITOR AMPLIFIERS


Parallel Switched Capacitor Amplifier
1

vin

+
C1

vC1

+
vC2
-

C2

vout

vin

C1

+
-

vC2

vout

+
C2

vC1

Modification to prevent open-loop operation

Inverting Switched Capacitor Amplifier

Analysis:
Find the even-odd and the even-even z-domain
transfer function for the above switched capacitor
inverting amplifier.
1: (n -1)T < t < (n -0.5)T

n- 23 n-1 n- 21

n+ 21 n+1 T

Clock phasing for this example.

o
vC1
(n -1)T = vino (n -1)T

and
o

vC2(n -1)T = 0
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-6

Parallel Switched Capacitor Amplifier- Continued


2: (n -0.5)T < t < nT
vC2 = 0 v e
t=0
- + out (n-1/2)T
Equivalent circuit:
+

C1

From the simplified


equivalent circuit we
write,

+ o
vin (n-1)T
-

C1

vino (n-1)T

Equivalent circuit at the moment 2 closes.

vC2 = 0 e
- + vout (n-1/2)T
C2

vC1 = 0
- +

+
Simplified equivalent circuit.

C1
e
o
vout (n-1/2)T = - C2 vin (n-1)T

Converting to the z-domain gives,


C1
e
o
z -1/2 Vout
(z) = -C2 z -1 Vin
(z)
Multiplying by z1/2 gives,
C1
e
o
V out
(z) = -C z -1/ 2 Vin
(z)
2
Solving for the even-odd transfer function, Hoe (z), gives, Hoe (z) =
CMOS Analog Circuit Design

e
V out
(z)
o

Vin (z)

C1
= -C2 z -1/ 2

P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-7

Parallel Switched Capacitor Amplifier- Continued


Solving for the even-even transfer function, Hee (z).
o

Assume that the applied input signal, vin (n-1)T, was unchanged during the previous
2 phase period(from t = (n-3/2)T to t = (n-1)T), then
o

vin (n-1)T = vin (n-3/2)T


which gives
o

V in(z) = z -1/2 Vin(z) .


Substituting this relationship into Hoe(z) gives
C1
e
e

V out(z) = -C z -1 Vin(z)
2
or
e

Hee (z) =

V out(z)
e

Vin(z)

C1

= -C2 z -1

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-8

Frequency Response of Switched Capacitor Amplifiers


Replace z by e jT.
e

Hoe (e jT)

V out( e jT)
e

Vout( e jT)

C1
= - C2 e -jT/2

and
e

Hee (e jT) =

V out(e jT)
o
Vout( e jT)

C1
= -C2 e -jT

If C1/C2 = R2/R1, then the magnitude response is identical to inverting unity gain amp.
However, the phase shift of Hoe(e jT) is
Arg[Hoe(e jT)] = 180 - T/2
and the phase shift of Hee(e jT) is
Arg[Hee(e jT)] = 180 - T.
Comments:
The phase shift of the SC inverting amplifier has an excess linear phase delay.
When the frequency is equal to 0.5fc, this delay is 90.
One must be careful when using switched capacitor circuits in a feedback loop
because of the excess phase delay.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-9

Positive and Negative Transresistance Equivalent Circuits


Transresistance circuits are two-port networks where the voltage across one port
controls the current flowing between the ports. Typically, one of the ports is at zero
potential (virtual ground).
i1(t) 1
i1(t)
vC(t)
vC(t)
i2(t)
i2(t)
Circuits:
2
2
2
C

v1(t)

CP

v1(t)

CP

C
2

CP

CP

Negative Transresistance Realization.

Positive Transresistance Realization.

Analysis (Negative transresistance realization):


v1(t)
v1
RT = i2(t) = i2(average)
If we assume v1(t) is constant over one period of the clock, then we can write
q2(T) - q2(T/2) CvC(T) - CvC(T/2) -Cv1
1 T

=
= T
i2(average) = T i2(t)dt =
T
T
T/2
Substituting this expression into the one above shows that

RT = -T/C

Similarly, it can be shown that the positive transresistance is T/C.


These circuits are insensitive to the parasitic capacitances shown as dotted capacitors.
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-10

Noninverting Stray Insensitive Switched Capacitor Amplifier


Analysis:
1
1
2
2
2
t
T
1: (n -1)T < t < (n -0.5)T
1
3
1
n- 2 n-1 n- 2 n n+ 2 n+1
The voltages across each capacitor can be written as
Clock phasing for this example.
o
o
vC1(n -1)T = vin(n -1)T
1
and
vC2
vC1(t)
vin 1
vout
2
o
o
- +
vC2(n -1)T = vout(n -1)T = 0 .
C2
C1
2: (n -0.5)T < t < nT
2
1
The voltage across C2 is
+

C
o
e
1
vout(n -1/2)T = C2 vin(n -1)T
Noninverting Switched Capacitor Voltage Amplifier.
C1
C1
o
e
V out(z) = C2 z -1/2 Vin(z) Hoe(z) = C2 z-1/2

If the applied input signal, vin(n -1)T, was unchanged during the previous 2 phase, then,
C1
e
e
V out(z) = C2 z-1 Vin(z)

C1
Hee(z) = C2 z-1

Comments:
Excess phase of H oe(e jT) is -T/2 and for H ee(e jT) is -T
CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 2 (5/2/04)

Page 9.2-11

Inverting Stray Insensitive Switched Capacitor Amplifier


Analysis:
1: (n -1)T < t < (n -0.5)T
vC1(t)
The voltages across each capacitor can
vin 2
be written as
C1

vC1(n -1)T = 0

and

vC1(t)
o

o
vout(n

-1)T = 0 .
vC2(n -1)T =
2: (n -0.5)T < t < nT