3.

5 CMOS/TTL Interfacing
There are several factors to consider in
TTL/CMOS interfacing, the first is noise margin;
the next factor is fanout; the last factor is
capacitive loading.
For example : HC or HCT driving TTL

Considering
fanout, an
HC or HCT
output can
drive 10 LS
or only 2 STTL inputs.

CMOS

TTL

VOL max C 0.33V VIL max T 0.8V

VOH min C 3.84V VIH min T 2.0V
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3.5 CMOS/TTL Interfacing

TTL driving HC or VHC

TTL

CMOS

VOL max T 0.55V VIL max C 1.5V

VOH min T 2.7V VIH min C 3.85V

TTL cant drive HC or VHC directly.

VDD
TTL RP

R p m in

CMOS

VDD VIL m axC

440
I OL m axT I IL m axC

VDD VIH m inC

R p m ax
5K
I LeakageHT I IH m axC

RP=(3-5)K.
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