1

Decoding at Destination
Jaweria Amjad

I. I NTRODUCTION
Decoding at destination consists of two stages.
Recovering quantization indices W by running SPA over IRA code graph.
Using these indices and channel information Yd2 to recover message m
A. LLRs for IRA Code
Yd1 can be thought of as an output of a virtual correlation channel that has systematic bits as inputs, thus it can
be used to calculate the channel Log-Likelihood Ratios (LLR) for the systematic bits.
Since we are using a 4-PAM constellation for our frame-work. We shall have two codes.
1) IRA0 :
0
= log
Lch
s

P (W0 [i] = 0 | yd1 [i])

P (W0 [i] = 1 | yd1 [i])
R (w+1+kM )q
P
P
k=

= log P

k=

w{0,1} (w+kM )q
R (w+1+kM )q
w{2,3} (w+kM )q

f (yr | yd1 [i])

f (yr | yd1 [i])

(1)

Since optimum value for M = 4,

R (1+4k)q
k= 4kq
R (4k+4)q
P
k= (4k+3)q
R (4k+2)q
P
k= 4kq
R (4k+5)q
P
k= (4k+3)q
P

0
Lch
s

= log

= log

f (yr | yd1 [i]) +

R (4k+2)q

f (yr | yd1 [i]) +

R (4k+5)q

(4k+1)q
(4k+4)q

f (yr | yd1 [i])

f (yr | yd1 [i])

f (yr | yd1 [i])

f (yr | yd1 [i])

(2)

We have two types of parity bit nodes. LLRs for them can be evaluated as follows:

P (Xr0 [i] = Pr0 | yd2 [i], Lxr1 [i])

= log
P (Xr0 [i] = Pr0 | yd2 [i], Lxr1 [i])
P
P
Lxr1 [i] f (y [i] c
rd0 crd1 csd2 ) + xs2 fg (yd2 [i] crd0 + crd1 csd2 )
g d2
xs2 e
= log P
P
Lxr1 [i] f (y [i] + c
rd0 crd1 csd2 ) + xs2 fg (yd2 [i] + crd0 + crd1 csd2 )
g d2
xs2 e

P (Xr1 [i] = Pr1 | yd2 [i], Lxr0 [i])

ch0

Lp2 = log
P (Xr1 [i] = Pr1 | yd2 [i], Lxr0 [i])
P
P
Lxr0 [i] f (y [i] c
rd1 crd0 csd2 ) + xs2 fg (yd2 [i] crd1 + crd0 csd2 )
g d2
xs2 e
= log P
P
Lxr0 [i] f (y [i] + c
rd1 crd1 csd2 ) + xs2 fg (yd2 [i] + crd1 + crd0 csd2 )
g d2
xs2 e

with crd1 = crd Pr1 , crd0 = crd Pr0 , csd2 = csd Ps2
2) IRA1 :
0
Lch
p1

1
Lch
= log
s

We know that :

P (W1 [i] = 0 | yd1 [i], Lw0 [i])

P (W1 [i] = 1 | yd1 [i], Lw0 [i])

(3)

(4)

(5)

PW1 (w1 | yd1 ) =

P (w0 )P (w1 | yd1 , w0 )

w0

=
=

X P (w0 )P (w1 , w0 | yd1 )

P (w0 | yd1 )
w0
X P (w0 )P (w | yd1 )
w0

(6)

P (w0 | yd1 )

Substituting in the above equation gives:

P P (w0 )P (W1 [i]=0,w0 [i]|yd1 [i])
w0

P (w0 [i]|yd1 [i])

P (w0 )P (W1 [i]=1,w0 [i]|yd1 [i])
w0
P (w0 [i]|yd1 [i])

1
= log P
Lch
s

P (w0 [i] = 0)P (W1 [i] = 0, w0 [i] = 0 | yd1 [i]) + P (w0 [i] = 1)P (W1 [i] = 0, w0 [i] = 1 | yd1 [i])
P (w0 [i] = 0)P (W1 [i] = 1, w0 [i] = 0 | yd1 [i]) + P (w0 [i] = 1)P (W1 [i] = 1, w0 [i] = 1 | yd1 [i])
eLw0 [i] P (W1 [i] = 0, w0 [i] = 0 | yd1 [i]) + P (W1 [i] = 0, w0 [i] = 1 | yd1 [i])
= log L [i]
e w0 P (W1 [i] = 1, w0 [i] = 0 | yd1 [i]) + P (W1 [i] = 1, w0 [i] = 1 | yd1 [i])
= log

For M = 4
R
Lw0 [i] (4k+1)q
k= e
4kq
R (4k+2)q
P
L
[i]
w0
k= e
(4k+1)q

P
1
= log
Lch
s

f (yr | yd1 [i]) +

R (4k+3)q

f (yr | yd1 [i]) +

R (4k+5)q

(4k+2)q
(4k+4)q

f (yr | yd1 [i])

f (yr | yd1 [i])

For the parity bit nodes, the LLRs can be calculated using (3),(4).
B. LLRs for LDPC Codes
Let us first derive the LLRs for a BPSK modulation. For type-2 bit nodes, they can be evaluated as:
L2ch [i]

P (Xs2 [i] = Ps2 | yd2 [i], Lxr [i])

= log
P (Xs2 [i] = Ps2 | yd2 [i], Lxr [i])
p(xr = crd )fg (yd2 [i] csd2 crd ) + p(xr =
crd )fg (yd2 [i] csd2 + crd )
= log
p(xr = crd )fg (yd2 [i] + csd2 crd ) + p(xr =
crd )fg (yd2 [i] + csd2 + crd )
L
xr
e fg (yd2 [i] csd2 crd ) + fg (yd2 [i] csd2 + crd )
= log Lx
e r fg (yd2 [i] + csd2 crd ) + fg (yd2 [i] + csd2 + crd )

For type-1 nodes:

L1ch [i]

P (Xs1 [i] = + Ps1 | yd1 [i], Lw [i])

= log
P (Xs1 [i] = Ps1 | yd1 [i], Lw [i])

P
w P (w)P (Xs1 [i] = +Ps1 | yd1 [i], w[i])
= log P
w P (w)P (Xs1 [i] = Ps1 | yd1 [i], w[i])
P P (w)P (Xs1 [i]=+Ps1 ,w[i]|yd1 [i])
w

P (w[i]|yd1 [i])

P (w)P (Xs1 [i]= Ps1 ,w[i]|yd1 [i])

w
P (w[i]|yd1 [i])

= log P

P
w P (w)P (Xs1 [i] = +Ps1 , w[i] | yd1 [i])
= log P
w P (w)P (Xs1 [i] = Ps1 , w[i] | yd1 [i])

(7)

P
w P (w)P (Xs1 [i] = +Ps1
= log P
P (w)P (Xs1 [i] = Ps1

Pw
w P (w)P (Xs1 [i] = +Ps1
= log P
w P (w)P (Xs1 [i] = Ps1

| yd1 [i])P (w[i] | Xs1 [i] = Ps1 , yd1 [i])

| yd1 [i])P (w[i] | Xs1 [i] = Ps1 , yd1 [i])

| yd1 [i])P (w[i] | Xs1 [i] = Ps1 )

| yd1 [i])P (w[i] | Xs1 [i] = Ps1 )

(8)
(9)

P (w = 0)(1 )fg (yd1 csd ) + P (w = 1)fg (yd1 csd )

P (w = 0)fg (yd1 + csd ) + P (w = 1)(1 )fg (yd1 + csd )
eLw (1 )fg (yd1 csd ) + fg (yd1 csd )
= log Lw
e fg (yd1 + csd ) + (1 )fg (yd1 + csd )


ecsd yd1 [i] eLw (1 ) + 


= log c y [i] L
e sd d1 e w  + (1 )
= log

eLw (1 ) + 
eLw  + (1 )

with  = (1/2)[1 erf (csr / 2)], and csd = csd Ps1 .

Let us now move to the 4-PAM modulation. Similar to IRA code, well have two codes for the LDPC codes.
The decoded indices from IRA codes will be passed to LDPC bit nodes to calculate the channel LLRs. Instead
of hard-thresholding, well use the soft interference cancellation strategy:
= 2
csd yd1 [i] + log

1) LDP C0 : There wil be two types of bit nodes and their LLRs will be calculated accordingly:
q
(0)
(0)
P (Xs2 [i] = Ps2 | yd2 [i], Lxr0 , Lxr1 )
2
q
Lch0 [i] = log
(0)
(0)
P (Xs2 [i] = Ps2 | yd2 [i], Lxr0 , Lxr1 )
p(xr [i] = crd0 , crd1 ) + + p(xr0 [i] = crd0 , crd1 ) + + p(xr0 [i] = crd0 , crd1 ) + + p(xr [i] = crd0 , crd1 ) +
p(xr [i] = crd0 , crd1 ) + p(xr0 [i] = crd0 , crd1 ) + p(xr0 [i] = crd0 , crd1 ) + p(xr [i] = crd0 , crd1 )
eLxr0 [i] eLxr1 [i] + + eLxr1 [i] + + eLxr0 [i] + + +
= log L [i] L [i]
(10)
e xr0 e xr1 + eLxr1 [i] + eLxr0 [i] +
= log

with
(0)

(1)

(0)

(1)

(0)

(1)

(0)

(1)

(0)

(1)

(0)

(1)

(0)

(1)

(0)

(1)

= fg (yd2 [i] csd2 csd2 crd0 crd1 ) + fg (yd2 [i] csd2 + csd2 crd0 crd1 )
= fg (yd2 [i] csd2 csd2 + crd0 crd1 ) + fg (yd2 [i] csd2 + csd2 + crd0 crd1 )
= fg (yd2 [i] csd2 csd2 crd0 + crd1 ) + fg (yd2 [i] csd2 + csd2 crd0 + crd1 )
= fg (yd2 [i] csd2 csd2 + crd0 + crd1 ) + fg (yd2 [i] csd2 + csd2 + crd0 + crd1 )

q
(0)
= + Ps1 | yd1 [i], Lw [i])
q
L1ch0 [i] = log
(0)
(0)
P (Xs1 [i] = Ps1 | yd1 [i], Lw [i])
q
P
(1)
(1)
(0)
(0)
(1)
(1)
xs1 P (xs1 [i] = csd1 )P (Xs1 [i] = + Ps1 | yd1 [i], xs1 [i])
q
= log
P
(1)
(1)
(0)
(0)
(1)
(1)
xs1 P (xs1 [i] = csd1 )P (Xs1 [i] = Ps1 | yd1 [i], xs1 [i])
(0) (1)
(1)
(1)
(0)
P
P (xs1 [i]=csd1 )P (Xs1 [i]=+ Ps1 ,xs1 [i]|yd1 [i])
(0)
P (Xs1 [i]

(1)

(1)

xs1

= log P

P (xs1 [i]|yd1 [i])

(1)

(1)
s1

(1)

(0)

(0)

(1)

P (xs1 [i]=csd1 )P (Xs1 [i]= Ps1 ,xs1 [i]|yd1 [i])

(1)
P (xs1 [i]|yd1 [i])

(11)

(1)
P (xs1 [i]

(1)

xs1

= log

(1)
(0)
csd1 )P (Xs1 [i]

q
=+

(0)

(1)

Ps1 , xs1 [i] | yd1 [i])

q
(0) (1)
(1)
=
= Ps1 , xs1 [i] | yd1 [i])
xs1
q
P P
(0) (1)
(1)
(0)
(1)
w
xs1 P (w[i])P (xs1 [i])P (Xs1 [i] = + Ps1 , xs1 [i] | yd1 [i], w[i])
q
= log
P P
(1)
(0)
(0) (1)
(1)
w
xs1 P (w[i])P (xs1 [i])P (Xs1 [i] = Ps1 , xs1 [i] | yd1 [i], w[i])
(0) (1)
P
(1)
(0)
Ps1 ,xs1 [i],w[i]|yd1 [i])
(1) P (w[i])P (xs1 [i])P (Xs1 [i]=+
P
x
s1
(1)
P (xs1 [i]

(1)
(0)
csd1 )P (Xs1 [i]

= log

P (w[i]|yd1 [i])
(1)

P
x

(1)
s1

(0)

P (w[i])P (xs1 [i])P (Xs1 [i]=

(0)

(1)

Ps1 ,xs1 [i],w[i]|yd1 [i])

P (w[i]|yd1 [i])

q
(0) (1)
(1)
= + Ps1 , xs1 [i], w[i] | yd1 [i])
w
xs1
q
= log
P P
(0) (1)
(1)
(0)
(1)
w
x P (w[i])P (xs1 [i])P (Xs1 [i] = Ps1 , xs1 [i], w[i] | yd1 [i])
(1)
(0)
P (w[i])P (xs1 [i])P (Xs1 [i]

P P

s1

Using the simplification from (8)-(9) :

q
q
(0) (1)
(0)
(0) (1)
(1)
= + Ps1 , xs1 [i] | yd1 [i])P (w[i] | Xs1 [i] = + Ps1 , xs1 [i])
w
xs1
q
q
= log
P P
(1)
(0)
(0) (1)
(0)
(0) (1)
(1)
w
xs1 P (w[i])P (xs1 [i])P (Xs1 [i] = Ps1 , xs1 [i] | yd1 [i])P (w[i] | Xs1 [i] = Ps1 , xs1 [i])
q
q
P P P
(0) (1)
(0)
(0) (1)
(1)
(0)
(1)
w0
w1
xs1 P (w0 [i])P (w1 [i])P (xs1 [i])P (Xs1 [i] = + Ps1 , xs1 [i] | yd1 [i])P (w[i] | Xs1 [i] = + Ps1 , xs1 [i])
q
q
= log
P P P
(0) (1)
(0)
(0) (1)
(1)
(0)
(1)
w0
w1
x P (w0 [i])P (w1 [i])P (xs1 [i])P (Xs1 [i] = Ps1 , xs1 [i] | yd1 [i])P (w[i] | Xs1 [i] = Ps1 , xs1 [i])
P P

(1)
(0)
P (w[i])P (xs1 [i])P (Xs1 [i]

s1

= log

fg (yd1
fg (yd1 +

(0)
csd1
(0)
csd1


X

(0)

(0)

(0)

(0)

(0)

(0)

csd1 )++ + fg (yd1 csd1 + csd1 )+

csd1 )+ + fg (yd1 + csd1 + csd1 )

eLw0 eLw1

(4k+1)q

4kq

k=

Lw1

(0)

(0)

fg (yr [i] csd1 csd1 ) + eLw0

(4k+3)q

fg (yr [i]

+e

(4k+2)q

(0)
csd1

(0)
csd1 )

(4k+2)q

(4k+1)q

(4k+4)q

fg (yr [i]

+
(4k+3)q

(0)

(0)

fg (yr [i] csd1 csd1 )

(12)
(0)
csd1

(0)
csd1 )

2) LDP C1 : There wil be two types of bit nodes and their LLRs will be calculated accordingly:
q
(1)
(1)
P
(X
[i]
=
Ps2 | yd2 [i], Lxr0 , Lxr1 , Lx0s2 )
s2
2
q
Lch1 = log
(1)
(1)
P (Xs2 [i] = Ps2 | yd2 [i], Lxr0 , Lxr1 , Lx0s2 )




L (0) [i]
Lxr1 [i] + + eLxr0 [i] + + + + eLxr0 [i] eLxr1 [i] + + eLxr1 [i] + + eLxr0 [i] + + +
e xs2 eLxr0 [i] eLxr1 [i] +
++e
+
+
+

= log L [i]




(0)

Lx [i]
Lx [i]
Lx [i] Lx [i]
Lx [i]
Lx [i]
e xs2 eLxr0 [i] eLxr1 [i]
+ + e r1 + + e r0 + + + + e r0 e r1 + e r1 + e r0 +
with

(0)

(1)

(0)

(0)

(0)

(0)

(0)

(0)

sd2 csd2 crd0 crd1 )

= fg (yd2 [i] c

sd2 csd2 + crd0 crd1 )

= fg (yd2 [i] c

(13)

sd2 csd2 crd0 + crd1 )

= fg (yd2 [i] c

= fg (yd2 [i] csd2 csd2 + crd0 + crd1 )

LLR for type-1 bit nodes is given by:

L2ch1

with is given by (12)

= log

Lx(0)

fg (yd1 csd1 csd1 )++ + fg (yd1 csd1 + csd1 )+

Lx(0)

fg (yd1 + csd1 csd1 )+ + fg (yd1 + csd1 + csd1 )

sd1

sd1

(0)

(0)

(0)

(0)

(0)

(0)

(0)

(0)

(14)