EEE

51: Second Semester 2014 - 2015

Lecture 4

Single-Stage Ampliers

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Today
Single-Stage Ampliers

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A More PracDcal Common-EmiFer Bias Strategy

The Fixed-Bias CE Amplier only 1 DC source
KVL at the input loop:

VCC I B,Q RB VBE,Q = 0

" I C,Q %
I C,Q
VCC
RB VT ln $
'=0

# IS &
Non-linear! How do we solve this?
Graphical
Numerical / iteraDve
put those EEE 11/13 skills to good use J
DC Block capacitor
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IteraDve SoluDon
VCC = 5V
= 100
RB = 500k
VT = 26mV
I S = 0.2fA

" I C,Q %
I C,Q
VCC
RB VT ln $
'=0

# IS &
Rewrite:

A
C,Q

B %+
" I C,Q
(
= *VCC VT ln $
'RB *)
# I S &-,
B
I C,Q

IniDal guess

A
I C,Q

1mA

0.8479mA

0.8479mA

0.8488mA

0.8488mA

0.8488mA

I C,Q = 848.8 A
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Recall: Basic Common-EmiFer Amplier

For a wide range of currents,

VBE 0.7V
What if we use this approximaDon?

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Fixed-Bias Common-EmiFer Amplier Bias

VCC

VCC = 5V
= 100
RB = 500k

"I %
I C,Q
RB VT ln $ C,Q ' = 0

# IS &
VCC

VT = 26mV
I S = 0.2fA

I C,Q
RB 0.7V = 0

Thus,

VCC 0.7V
RB
= 860 A

I C,Q =

IteraDve soluDon:
I C,Q = 848.8 A (error less than 2%)
Is this approximaDon good enough? It depends on the applicaDon!
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Small Signal Model

Gm = gm
Ri = r || RB

Input resistance
changes

Ro = ro || RL
Av = Gm Ro
= gm ( ro || RL )

Open: at DC
Short: everywhere else
Common-EmiFer refers to the small signal model
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Fixed-Bias LimitaDons
-variaDons

Due to manufacturing imperfecDons

= nominal 50%
doubles for every 80C rise in temp

Recall: I C,Q =

VCC 0.7V
RB

IC,Q can vary by a lot due to variaDons!

Can we do beFer than this?

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EmiFer-Degenerated Common-EmiFer Amplier

KVL at the input loop:

VCC I B,Q RB VBE,Q I E,Q RE = 0

" 1%
I C,Q
VCC
RB 0.7V I C,Q $1+ ' RE = 0

# &
Solving for the collector current:

I C,Q =

VCC 0.7V
RB + ( +1) RE

Is this bias
scheme beFer?

For :

I C,Q

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VCC 0.7V
RE

Independent of

Formalizing Parameter Eects

X
Dene SensiDvity of X to Y as S =
Y

X
X = S Y =
Y
Y

X
Y

Fixed-Bias
I C,Q =
IC,Q

Emi9er-Degenera<on

VCC 0.7V
RB

I C,Q =

I C,Q $ VCC 0.7V '

=
= &
)

%
RB
(
=

VCC 0.7V
RB

X
Y

Constant sensiDvity
Decreasing sensiDvity
as increases

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IC,Q

VCC 0.7V
RB + ( +1) RE

I C,Q #
VCC 0.7V &
(
=
= %%

$ RB + ( +1) RE ('
R
1+ E
V 0.7V
RB
= CC

2
RB
#
RE &
%1+ ( +1) (
RB '
$
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DC Eects of RE
Output KVL:

VCC I C,Q RL VCE,Q I E,Q RE = 0

" 1%
VCC I C,Q RL VCE,Q I C,Q $1+ ' RE = 0
# &
To keep Q1 in the forward-acDve region:
VCE,Q > VCE,sat
Thus, VCE,sat

" 1%
< VCC I C,Q RL I C,Q $1+ ' RE
# &

VCC I C,Q RL VCE,sat

RE <
" 1%
I C,Q $1+ '
# &
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VOUT = ?

11

Small Signal Equivalent Circuit

Lets look at the degenerated transistor rst

Derive the 2-port equivalent circuit
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The EmiFer-Degenerated Transistor (1)

CalculaDng the transconductance

'
iout
G = '
vin
'
m

KCL at the ve' vin'

ve' ve'
+
+ gm ( vin' ve' ) = 0
emiFer node:
r
RE ro
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no load

1
r
ve' = vin'
1 1 1
gm + + +
r ro RE
gm +

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The EmiFer-Degenerated Transistor (2)

KCL at the collector:
'
out

ve'
= gm ( v v )
ro
'
in

'
e

Recall:

1
r
ve' = vin'
1 1 1
gm + + +
r ro RE
gm +

'
iout

1
1

RE gm ro r
= vin' gm
1 1 1
gm + + +
r ro RE

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1
1

'
iout
RE gm ro r
'
Gm = ' = gm
1 1 1
vin
gm + + +
r ro RE
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The EmiFer-Degenerated Transistor (3)

Assume:

gm ro >> 1
gm r = >> 1
ro >> RE
r >> RE

1
1

'
iout
gm
RE gm ro r
'
Gm = ' = gm

< gm
1
1
1
vin
1+ gm RE
gm + + +
r ro RE
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The transconductance
is degenerated by RE

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The EmiFer-Degenerated Transistor (4)

CalculaDng the output resistance

Ro' =

vtest
itest

zero input
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test current source

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The EmiFer-Degenerated Transistor (5)

By inspecDon:

ve' = itest ( r || RE ) = vbe

Current through ro:

iro = itest gm vbe = itest + gm ve'

= itest (1+ gm ( r || RE ))

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Solving for vtest:

vtest = iro ro + ve' = itest "#ro + gm ro ( r || RE ) + ( r || RE )$%

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The EmiFer-Degenerated Transistor (6)

Assume:

gm ro >> 1
gm r = >> 1
ro >> RE
r >> RE

Recall:

Solving for Ro:

vtest = itest "#ro + gm ro ( r || RE ) + ( r || RE )$%

Ro' =

vtest !
= "ro + gm ro ( r || RE ) + ( r || RE )#$
itest

ro + gm ro RE ro (1+ gm RE ) >> ro
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The EmiFer-Degenerated Transistor (7)

CalculaDng the input resistance

'
vtest
R = '
itest
'
i

test current source

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no load

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The EmiFer-Degenerated Transistor (8)

By inspecDon:
'
ve' = (itest
+ gm vbe ) ( ro || RE )
'
= itest
(1+ gmr ) (ro || RE )

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'
'
'
vtest
= vbe + ve' = itest
r + itest
(1+ gmr ) (ro || RE )
'
= itest
"#r + gm r ( ro || RE ) + ( ro || RE )$%

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The EmiFer-Degenerated Transistor (9)

Assume:

gm ro >> 1
gm r = >> 1
ro >> RE
r >> RE

Recall:
'
'
vtest
= itest
"#r + gm r ( ro || RE ) + ( ro || RE )$%

Solving for Ri:

'
vtest
R = ' = !"r + gm r ( ro || RE ) + ( ro || RE )#$
itest
'
i

r (1+ gm RE ) > r
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The EmiFer-Degenerated Transistor (10)

Degenerated transistor small signal equivalent

Transconductance reduced (degenerated) by (1+gmRE)

Resistances increased by (1+gmRE)
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Is this good or bad?

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EmiFer-Degenerated Common-EmiFer Amplier

Overall analysis is now easy!

Assume:

ro >> RL
r >> RB

By inspecDon:

Ri = r (1+ gm RE ) || RB
RB

Gm =

gm
1+ gm RE

Voltage gain: Av = Gm Ro =
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Ro = ro (1+ gm RE ) || RL
RL

gm RL
1+ gm RE
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Next MeeDng
Single-Stage Ampliers
Common-Source Amplier
Common-Base / Common-Gate Amplier
Common-Collector / Common-Drain Amplier

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