BANASTHALI VIDYAPITH

I PERIODICAL TEST-2015
CLASS: M.TECH II SEM. VLSI DESIGN

SUBJECT: ANALOG AND MIXED SIGNAL IC DESIGN

NUMBER OF STUDENTS = 66
NOTE: Attempt all questions. Assume missing data, if any suitably. Write specific answers,
unnecessary long answer can deduct your marks.
MAX. MARKS: 10

TIME: 1:30 Hrs.

Q.1. Attempt all parts (2X2).

(a) In the case of mismatch between the MOSFETs used to design the simple current mirror, show that
the relationship between input and output current is given by the expression:

(b) Describe the small signal model for the circuit shown in Fig. 1 below. Also calculate output
resistance.

ISS

Fig. 1

Fig. 2

Fig. 3

Q.2. Attempt any two parts. (1.5X 2)

(a) Discuss small signal model of Wilson current mirror and obtain the expression for its output
resistance.
(b) Find the small signal output resistance and differential voltage gain, v o/vid, of the circuit in Fig. 2
(shown above). Assume all transistors have a W/L of 10m/1m, KN =110A/V2, KP =50A/V2, N
=0.04V-1,P =0.05V-1, VT0=0.7 V, and ISS=10A.
(c) Calculate the output resistance and the minimum output voltage, while maintaining all devices in
saturation, for the circuit shown in Fig.3 above. Assume that IOUT is actually 10A. You can use the
value of various model parameters given in the question 2 (b) above. Dimensions are in micrometer.

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