Session # 8

Processor, Part 1: Datapath

Today: Building a Datapath Unit
A single-cycle implementation for now.
(Next Time: The Control Unit)
Reference: PH Sections 4.1 4.3.
CANOS ECSE-2660 Session 8: The Processor Datapath

Recall: Five Major Parts of a Computer

We know Processor Performance is determined by:
1. Clock cycle time.
2. Clock cycles per
instruction.
Control
3. Instruction count.
Processor
Control

Datapath

Input

Memory

Control and Datapath determine #1 & #2.

Datapath
by the compilerOutput
& the instruction
. #3 is determined
set architecture, which we covered in Ch. 2 & 3.
. Focus on Datapath today and Control next time.

CANOS ECSE-2660 Session 8: The Processor Datapath

Steps for Designing a Processor

Today: Lay down the roads and buildings
Stuff that the computer does with data.
The Datapath Unit.
Next Class: Build the traffic signals
The Control Unit.

CANOS ECSE-2660 Session 8: The Processor Datapath

Steps for Designing a Datapath

1. Study the Instruction Set Architecture (ISA).
Put one real register for each register in the ISA
(& a few more for internal use).
Put interconnections for each register transfer.
2. Select Datapath components.
3. Establish clocking methodology (skip today).
4. Assemble Datapath, meeting the requirements.
Design Principles:
1. Make the common case fast
2. Simple & regular instruction sets faster Datapath
CANOS ECSE-2660 Session 8: The Processor Datapath

Simplified MIPS ISA

Consider a MIPS processor simplified to
contain only:
Memory-reference instructions:

lw, sw
Arithmetic-logical instructions:

add, sub, or, and, slt

Control flow instructions:

beq, (and later will include j)

CANOS ECSE-2660 Session 8: The Processor Datapath

Basic Steps for Each Instruction

Fetch next instruction
@ address = PC
Read Registers
Execute operation
Update PC

CANOS ECSE-2660 Session 8: The Processor Datapath

Study the MIPS ISA

All instructions are 32 bits long.
Three instruction formats:
R-type:
I-type:
J-type:

op

rs

rt

rd

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

op

6 bits

op

6 bits

rs

5 bits

rt

5 bits

Immediate offset
16 bits

target address
26 bits

op: operation
We wont
rs, rt, rd: 2 source registers and 1 destination register.
worry about
shamt: shift amount.
J-type today
funct: variant of the operation in the op field.
address / immediate: address offset or immediate value.
target address: target address of the jump.
CANOS ECSE-2660 Session 8: The Processor Datapath

RTL Descriptions of Basic Instructions

Instruction Fetch (common to all instructions)
instruction mem[PC]
Instruction Execution

Remember that
Immediate is
a WORD offset

add

R[rd] R[rs] + R[rt]; PC PC + 4

sub

R[rd] R[rs] R[rt]; PC PC + 4

ori

R[rt] R[rs] OR ZeroExt(Imm16); PC PC + 4

load

R[rt] mem[R[rs] + SignExt(Imm16)]; PC PC + 4

store mem[R[rs] + SignExt(Imm16)] R[rt]; PC PC + 4

beq

if (R[rs] == R[rt]) then

PC PC + 4 + SignExt(Imm16 x 4)
else PC PC + 4

CANOS ECSE-2660 Session 8: The Processor Datapath

The Instruction Fetch Unit

1. Fetch the Instruction @ mem[PC]
2. Update the program counter:
Sequential Code: PC PC + 4
Branch and Jump: PC something else

Clk

PC
Next Address
Logic
Address
Instruction
Memory

Instruction Word
32

CANOS ECSE-2660 Session 8: The Processor Datapath

ALU:
A

Select Datapath
Combinational Components
ALU control
3

32

Select

32

Sum
Carry

32

16

Sign
Exten32
der

A
B

16

CANOS ECSE-2660 Session 8: The Processor Datapath

32
32

MUX

Shift
By n

32

Adder

32

ALU

MUXes:

Carry-In

Zero
Result
B

Adder:

32

Zero
Exten32
der
10

Datapath Storage Components

Data In
32

Buffer

Buffers:

Memory:

Write Enable

Write Enable

Data Out
32

Data In
32
Clk

Clk

The Register File:

5
Register
numbers

Data

5
5

Read
register 1

Address

Memory

DataOut
32

Read
data 1

Read
register 2
Registers
Write
register
Read
data 2
Write
data
RegWrite

CANOS ECSE-2660 Session 8: The Processor Datapath

Data

11

Read a
register 1

In
MIPS
n = 32
Read a
register 2

Fig. C.8.8
in PH

Register File Read

Register 0
Register 1
Register n-2
Register n-1

M
U
X

Read data 1

M
U
X

Read data 2

We can read two registers at a time, at any time.

CANOS ECSE-2660 Session 8: The Processor Datapath

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Register File Write

Write

Register
number

Fig. C.8.9
in PH
Register
data

0
1

n-to1
decoder
n-2
n-1

C
D
C
D

Register 0
Register 1

C
Register n-2
D
C
Register n-1
D

We can write one register at a time, on clock edge only.

This allows read & write in same cycle, but not the
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same value. CANOS ECSE-2660 Session 8: The Processor Datapath

Datapath for R-type Instructions

rs
5 bits

op
6 bits

rt
5 bits

rd
5 bits

rs

Read
register 1

rt

Read
register 2

rd

Register
Write
register
File

Instruction

Write
data

shamt
5 bits

funct
6 bits

3
Read
data 1

ALU

Read
data 2

CANOS ECSE-2660 Session 8: The Processor Datapath

ALU operation

Zero
ALU
result

14

Datapath for Load and for Store

op

rs

rt

6 bits

5 bits

5 bits

Immediate offset
16 bits

R[rt] mem[R[rs]+SignExt(Imm16)]
rs
rt
Instruction

rt

Read
register 1

ReadR[rs]
data 1

Read
register 2
Registers
Write
R[rt]
register
Read
data 2
Write
data
RegWrite

imm16

16

Sign
extend

32

ALUoperation

Zero
ALU ALU
result

MemWrite

Address
Write
data

CANOS ECSE-2660 Session 8: The Processor Datapath

Read
data
Data
memory
MemRead

15

Conditional Branch Instruction

op

rs

rt

6 bits

5 bits

5 bits

Immediate offset
16 bits

beq rs, rt, imm16

instruction mem[PC]

#Fetch the instruction from memory

COND R[rs] == R[rt]

#Calculate the branch condition

if (COND eq 0)

#Calculate next instructions address

PC PC + 4 + (SignExt(imm16) x 4)
else
PC PC + 4

Remember that
Immediate is
a WORD offset

CANOS ECSE-2660 Session 8: The Processor Datapath

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Datapath for Branch Operations

op

rs

rt

6 bits

5 bits

5 bits

Immediate offset
16 bits

PC + 4 from instruction datapath

Register File

Shift
left 2

Read
register 1
Read
register 2

Instruction

Write
register
Write
data

16

Read
data 1

Add sum

be used in
case condition
is satisfied)

ALU operation

ALU zero
Read
data 2

Sign
Extender

Branch
Target (to

32

CANOS ECSE-2660 Session 8: The Processor Datapath

To branch
control
logic

Fig. 4.9
in PH
17

Putting it All Together

We can now consolidate the three diagrams to build a
single Datapath.
Will handle:

lw, sw, add, sub, and, or, slt, beq

Our target: A Single Cycle Datapath.
It can do all of the above in 1 cycle
Each part can only be used once per instruction.
Some parts may need to be replicated.
Some parts could still be shared using MUXes.

CANOS ECSE-2660 Session 8: The Processor Datapath

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Combine R-type & Load/Store

Instruction

4 ALU operation

Read
register 1
Read
data1
Read
register 2
Registers Read
Write
data2
register
Write
data
RegWrite
16

Fig. 4.10
in PH

Sign
extend

MemWrite
ALUSrc
M
u
x

Zero
ALU ALU
result

Address

Write
data

Read
data
Data
memory

MemtoReg

M
u
x

32
MemRead

Use multiplexers to
stitch them together
CANOS ECSE-2660 Session 8: The Processor Datapath

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Add Instruction Fetch Circuit

Add
4

PC

Read
address
Instruction
Instruction
memory

Registers
Read
register 1
Read
Read
data
1
register 2

3
ALUSrc

Read
data 2

Write
register
Write
data

M
u
x

ALU operation

MemtoReg
Zero
ALU ALU
result

Address

Write
data

RegWrite
16

MemWrite

Sign 32
extend

CANOS ECSE-2660 Session 8: The Processor Datapath

Read
data

M
u
x

Data
memory

MemRead

20

Add Branch Address Calculation

PCSrc
M
u
x

Add
Add ALU
result

4
Shift
left 2
Registers

PC

Read
address
Instruction
Instruction
memory

Read
register 1
Read
Read
data 1
register 2
Write
register
Write
data
RegWrite
16

ALUSrc

Read
data 2

Sign
extend

M
u
x

ALU operation

Zero
ALU ALU
result

32

CANOS ECSE-2660 Session 8: The Processor Datapath

MemWrite
MemtoReg

Address

Read
data

Data
Write memory
data

M
u
x

MemRead

21

The Full Single-Cycle Datapath

PCSrc
Add
4

RegWrite
Instruction [25 21]
PC

Read
address
Instruction
[31 0]
Instruction
memory

Instruction [20 16]

1
M
u
Instruction [15 11] x
0

RegDst
Instruction [15 0]

Read
register 1
Read
register 2

Read
data 1
Read
data 2

Write
register
Write
Registers
data
16

Shift
left 2

ALU
Add result

1
M
u
x
0

MemWrite
MemtoReg

ALUSrc
1
M
u
x
0

ALU

Zero
ALU
result

Sign 32
extend

Address

Read
data

Data
Write
data memory

MemRead

PH Fig. 4.11

CANOS ECSE-2660 Session 8: The Processor Datapath

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1
M
u
x
0

The Full Single-Cycle Datapath

PH Fig. 4.15

CANOS ECSE-2660 Session 8: The Processor Datapath

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Do Activity 8 Now

For next class: Read Section 4.4.

CANOS ECSE-2660 Session 8: The Processor Datapath

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