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COMP541

Datapaths II &
Control I
Montek Singh
Mar 22, 2010

Topics
Single cycle MIPS
Reading: Chapter 7
Verilog code for MIPS at the end (!)

If you dont feel comfortable with assembly


language, pls review Ch. 6

First, Top Level of CPU


module top(input
clk, reset,
output [31:0] writedata, dataadr,
output
memwrite);
wire [31:0] pc, instr, readdata;
// instantiate processor and memories
mips mips(clk, reset, pc, instr, memwrite, dataadr,
writedata, readdata);
imem imem(pc[7:2], instr);
dmem dmem(clk, memwrite, dataadr, writedata,
readdata);
endmodule

Top Level Schematic (ISE)

imem
MIPS

dmem

Top Level of MIPS


module mips(input
output
input
output
output
input
wire

wire [2:0]

[31:0]
[31:0]
[31:0]
[31:0]

clk, reset,
pc,
instr,
memwrite,
aluout, writedata,
readdata);

memtoreg, branch,
pcsrc, zero,
alusrc, regdst, regwrite, jump;
alucontrol;

controller c(instr[31:26], instr[5:0], zero,


memtoreg, memwrite, pcsrc,
alusrc, regdst, regwrite, jump,
alucontrol);
datapath dp(clk, reset, memtoreg, pcsrc,
alusrc, regdst, regwrite, jump,
alucontrol,
zero, pc, instr,
aluout, writedata, readdata);
endmodule

MIPS Schematic

Datapath

MIPS State Elements

CLK

CLK

PC'

PC

32

32
32

RD

Instruction
Memory

5
32
5

5
32

A1
A2
A3
WD3

CLK
WE3

RD1
RD2

Register
File

WE
32
32

32

32

RD
Data
Memory
WD

32

Well fill out the datapath and control logic for basic single cycle MIPS
First the datapath
then the control logic

Lets Design lw
What does it do?

Single-Cycle Datapath: lw fetch


First consider executing lw
How does lw work?
STEP 1: Fetch instruction

CLK

CLK
PC'

PC

Instr
A

RD

Instruction
Memory

A1

CLK
WE3

WE

RD1
A

A2

RD2

A3
Register
WD3
File

RD
Data
Memory
WD

Single-Cycle Datapath: lw register


read
STEP 2: Read source operands from register file

CLK

CLK
25:21

PC'

PC

RD

Instruction
Memory

Instr

A1

CLK
WE3

WE

RD1
A

A2
A3
WD3

RD2
Register
File

RD
Data
Memory
WD

Single-Cycle Datapath: lw
immediate
STEP 3: Sign-extend the immediate
CLK

CLK
PC'

PC

RD

Instr

25:21

A1

CLK
WE3

WE

RD1
A

Instruction
Memory

RD
Data
Memory
WD

A2
RD2
A3
Register
WD3
File

SignImm

15:0

Sign Extend

Single-Cycle Datapath: lw
address
STEP 4: Compute the memory address
ALUControl2:0

PC

RD

Instr

25:21

Instruction
Memory

A1

WE3

A2
RD2
A3
Register
WD3
File

SrcB

SignImm
15:0

Sign Extend

CLK
Zero

SrcA

RD1

ALU

CLK
PC'

010

CLK

Note Control

ALUResult

WE
A

RD
Data
Memory
WD

Single-Cycle Datapath: lw memory


read
STEP 5: Read data from memory and write it back to
register file

RegWrite
1
CLK

PC'

PC

RD

Instruction
Memory

Instr

25:21

20:16

A1

WE3

A2
RD2
A3
Register
WD3
File

SrcB

SignImm
15:0

Sign Extend

CLK

Zero

SrcA

RD1

ALU

CLK

ALUControl2:0
010

ALUResult

WE
A

RD
Data
Memory
WD

ReadData

Single-Cycle Datapath: lw PC
increment
STEP 6: Determine the address of the next instruction
RegWrite
1
CLK
PC

RD

Instr

Instruction
Memory

PC'

25:21

20:16

A1

WE3

A2
RD2
A3
Register
WD3
File

SrcB

CLK

Zero

SrcA

RD1

ALU

CLK

ALUControl 2:0
010

ALUResult

WE
A

RD
Data
Memory
WD

ReadData

PCPlus4
SignImm
15:0

Sign Extend

Result

Lets be Clear
Although the slides said STEP
all that stuff executed in one cycle!!!
Lets look at sw
and then R-type

16

Single-Cycle Datapath: sw, write


back
Write data in rt to memory
RegWrite
CLK
PC

RD

Instr

Instruction
Memory

25:21

20:16
20:16

A1
A2
A3
WD3

PC'

0
WE3

010

RD2

SrcB

CLK

ALUResult

WriteData

Register
File

MemWrite

Zero

SrcA

RD1

ALU

CLK

ALUControl2:0

1
WE

RD
Data
Memory
WD

ReadData

PCPlus4
SignImm
15:0

Sign Extend

Result

Single-Cycle Datapath: R-type


instr
Read from rs and rt
Write ALUResult to register file
Write to rd (instead of rt)

CLK

CLK
PC

RD

Instr

Instruction
Memory

25:21

20:16

A1
A2
A3
WD3

WE3

varies

0 SrcB

RD2

Register
File

WriteReg4:0

MemWrite
CLK

Zero

SrcA

RD1

15:11

PCPlus4

ALUSrc ALUControl2:0

20:16

PC'

RegDst

ALU

RegWrite

ALUResult

WriteData

MemtoReg
0

0
WE

RD
Data
Memory
WD

ReadData

0
1

0
1

SignImm
15:0

Sign Extend

Result

Single-Cycle Datapath: beq

PCSrc

CLK
0
1

PC'

PC

RD

Instr

Instruction
Memory

25:21

20:16

A1

WE3

RegDst
x

A2
RD2
A3
Register
WD3
File

0 SrcB
1

15:11

WriteReg4:0
Sign Extend

CLK

ALUResult

WriteData

MemtoReg
x

WE
A

RD
Data
Memory
WD

ReadData

0
1

0
1

SignImm
15:0

MemWrite

Zero

SrcA

RD1

20:16

PCPlus4

ALUSrc ALUControl2:0 Branch


0
110
1

ALU

RegWrite
0
CLK

<<2

Determine whether values in rs and rt are equal


Calculate branch target address:
BTA = (sign-extended immediate << 2) + (PC+4)

PCBranch

Result

Complete Single-Cycle Processor


(w/control)

31:26
5:0

MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0
Op
ALUSrc
Funct RegDst

PCSrc

RegWrite
CLK
PC

RD

Instr

Instruction
Memory

25:21

20:16

A1

WE3

A2
RD2
A3
Register
WD3
File

0 SrcB
1

20:16
15:11

WriteReg4:0

PCPlus4

Sign Extend

ALUResult

WriteData

WE
A

RD
Data
Memory
WD

ReadData

0
1

0
1

SignImm
15:0

Zero

SrcA

RD1

ALU

PC'

0
1

CLK

<<2

CLK

PCBranch

Result

Control Unit
Control
Unit

MemtoReg
MemWrite

Opcode5:0

Main
Decoder

Branch
ALUSrc
RegDst
RegWrite

ALUOp1:0

Funct5:0

ALU
Decoder

ALUControl 2:0

Review: ALU

B
N

ALU
N
Y

3F

F2:0

Function

000

A& B

001

A| B

010

A+ B

011

not used

100

A & ~B

101

A | ~B

110

A- B

111

SLT

Review: ALU Design


A

B
N

F2

Cout

+
[N-1] S
Zero
Extend
N

2
N

F1:0

F2:0

Function

000

A& B

001

A| B

010

A+ B

011

not used

100

A & ~B

101

A | ~B

110

A- B

111

SLT

Review: R-Type

Fields:

op:
the operation code or opcode (0 for R-type
instructions)
funct:
the function
together, the opcode and function tell the
computer
what operation to perform

R-Type
op
6 bits

rs
5 bits

rt

rd

shamt

funct

5 bits

5 bits

5 bits

6 bits

Controller (2 modules)
module controller(input [5:0] op, funct,
input
zero,
output
memtoreg, memwrite,
output
pcsrc, alusrc,
output
regdst, regwrite,
output
jump,
output [2:0] alucontrol);
wire [1:0] aluop;
wire
branch;
maindec md(op, memtoreg, memwrite, branch,
alusrc, regdst, regwrite, jump,
aluop);
aludec ad(funct, aluop, alucontrol);
assign pcsrc = branch & zero;
endmodule
25

Main Decoder
module maindec(input [5:0] op,
output
memtoreg, memwrite, branch, alusrc,
output
regdst, regwrite, jump,
output [1:0] aluop);
reg [8:0] controls;
assign {regwrite, regdst, alusrc,
branch, memwrite,
memtoreg, jump, aluop} = controls;
always @(*)
case(op)
6'b000000:
6'b100011:
6'b101011:
6'b000100:
6'b001000:
6'b000010:
default:
endcase
endmodule

controls
controls
controls
controls
controls
controls
controls

<=
<=
<=
<=
<=
<=
<=

9'b110000010;
9'b101001000;
9'b001010000;
9'b000100001;
9'b101000000;
9'b000000100;
9'bxxxxxxxxx;

Why do this?

//Rtype
//LW
//SW
//BEQ
//ADDI
//J
//???

26

ALU Decoder
module aludec(input
[5:0] funct,
input
[1:0] aluop,
output reg [2:0] alucontrol);
always @(*)
case(aluop)
2'b00: alucontrol <= 3'b010;
2'b01: alucontrol <= 3'b110;
default: case(funct)
6'b100000: alucontrol <=
6'b100010: alucontrol <=
6'b100100: alucontrol <=
6'b100101: alucontrol <=
6'b101010: alucontrol <=
default:
alucontrol <=
endcase
endcase
endmodule

// add
// sub
// RTYPE
3'b010; //
3'b110; //
3'b000; //
3'b001; //
3'b111; //
3'bxxx; //

ADD
SUB
AND
OR
SLT
???

27

Control Unit: ALU Decoder


ALUOp1:0

Meaning

00

Add

01

Subtract

10

Look at Funct

11

Not Used

ALUOp1:0 Funct

ALUControl2:0

00

010 (Add)

X1

110 (Subtract)

1X

100000 (add)

010 (Add)

1X

100010 (sub)

110 (Subtract)

1X

100100 (and)

000 (And)

1X

100101 (or)

001 (Or)

1X

101010 (slt)

111 (SLT)

Control Unit: Main Decoder


Instruction

Op5:0

RegWrite

RegDst

AluSrc

Branch

MemWrite

MemtoReg

ALUOp1:0

R-type

000000

10

lw

100011

00

sw

101011

00

beq

000100

01

31:26
5:0

MemtoReg
Control
MemWrite
Unit
Branch
ALUControl 2:0
Op
ALUSrc
Funct RegDst

PCSrc

RegWrite
CLK
PC

RD

Instr

Instruction
Memory

25:21

20:16

A1

RD1

A2
RD2
A3
Register
WD3
File

0 SrcB
1

20:16

WriteReg4:0

WriteData

WE
A

RD
Data
Memory
WD

ReadData

0
1

SignImm
15:0

ALUResult

15:11

PCPlus4

Zero

SrcA

ALU

PC'

0
1

CLK
WE3

Sign Extend

<<2

CLK

PCBranch

Result

Single-Cycle Datapath Example:


or
31:26
5:0

MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0
Op
ALUSrc
Funct RegDst

0
PCSrc

RegWrite

PC

RD

Instr

Instruction
Memory

25:21

20:16

A1

CLK
SrcA

RD1
0

A2
RD2
A3
Register
WD3
File

0 SrcB
1

WriteReg4:0

WriteData

SignImm
15:0

ALUResult

0
ReadData
A
RD
1
Data
Memory
WD

15:11

Zero

0
WE

20:16

PCPlus4

001

ALU

PC'

1
WE3

Sign Extend

<<2

0
1

CLK

CLK

PCBranch

Result

Extended Functionality: addi


No change to datapath

31:26
5:0

MemtoReg
Control
MemWrite
Unit
Branch
ALUControl 2:0
Op
ALUSrc
Funct RegDst

PCSrc

RegWrite
CLK
PC

RD

Instr

Instruction
Memory

25:21

20:16

A1
A2
A3
WD3

WE3

RD2

0 SrcB
1

Register
File

20:16
15:11

WriteReg4:0

PCPlus4

Sign Extend

ALUResult

WriteData

WE
A

RD
Data
Memory
WD

ReadData

0
1

0
1

SignImm
15:0

Zero

SrcA

RD1

ALU

PC'

0
1

CLK

<<2

CLK

PCBranch

Result

Control Unit: addi


Instruction

Op5:0

RegWrite

RegDst

AluSrc

Branch

MemWrite

MemtoReg

ALUOp1:0

R-type

000000

10

lw

100011

00

sw

101011

00

beq

000100

01

addi

001000

00

31:26
5:0

MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0
Op
ALUSrc
Funct RegDst

PCSrc

RegWrite
CLK

PC'

PC

RD

Instr

Instruction
Memory

20:16

A1

CLK
WE3

RD1

A2
RD2
A3
Register
WD3
File

0 SrcB
1

20:16

15:11

WriteReg4:0

PCPlus4

Sign Extend

ALUResult

WriteData

WE
A

RD
Data
Memory
WD

ReadData

0
1

0
1

SignImm
15:0

Zero

SrcA

ALU

25:21

<<2

CLK

PCBranch

Result

Extended Functionality: j
Jump

31:26
5:0

MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0
Op

ALUSrc

Funct

RegDst

PCSrc

RegWrite
CLK

0
1

PC'

PC

RD

Instr

Instruction
Memory

25:21

20:16

A1
A2
A3
WD3

CLK
WE3

RD2

0 SrcB
1

Register
File

20:16

PCJump

WriteReg4:0

PCPlus4

WriteData

SignImm
Sign Extend

<<2

15:0

ALUResult

15:11

Zero

SrcA

RD1

ALU

CLK

27:0

31:28

25:0

<<2

PCBranch

WE
A

RD
Data
Memory
WD

ReadData

0 Result
1

Control Unit: Main Decoder


Instruction

Op5:0

RegWrite

RegDst

AluSrc

Branch

MemWrite

MemtoReg

ALUOp1:0

R-type 000000

10

lw

100011

00

sw

101011

00

beq

000100

01

000100

XX

Jump

31:26
5:0

MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0
Op
ALUSrc
Funct RegDst

PCSrc

RegWrite
CLK

0
1

PC'

PC

RD

Instr

Instruction
Memory

25:21

20:16

A1

CLK
WE3

SrcA

RD1

A2
RD2
A3
Register
WD3
File

0 SrcB
1

20:16

PCJump

WriteReg4:0

PCPlus4

WriteData

SignImm
Sign Extend

<<2

15:0

ALUResult

15:11

Zero

ALU

CLK
0
1

27:0

31:28

25:0

<<2

PCBranch

WE
A

RD
Data
Memory
WD

ReadData

0 Result
1

Jump

Review: Processor Performance


Program Execution Time =
(# instructions)(cycles/instruction)(seconds/cycle)
= # instructions x CPI x TC

Single-Cycle Performance
TC is limited by the critical path (lw)

Single-Cycle Performance
Single-cycle critical path:
Tc = tpcq_PC + tmem + max(tRFread, tsext + tmux) + tALU + tmem
+ tmux + tRFsetup

In most implementations, limiting paths


are:
memory, ALU, register file.
Tc = tpcq_PC + 2tmem + tRFread + tALU + tRFsetup + tmux

Single-Cycle Performance
Example

Tc = tpcq_PC + 2tmem + tRFread + tmux + tALU + tRFsetup


= [30 + 2(250) + 150 + 25 + 200 + 20] ps
= 925 ps

Single-Cycle Performance
Example
For a program with 100 billion instructions
executing on a single-cycle MIPS processor,
Execution Time = # instructions x CPI x TC
= (100 109)(1)(925 10-12 s)
= 92.5 seconds

Any potentials problems?


How do our Block RAMs differ from the RAM

illustrated here?

Do we want a Harvard architecture?


instruction memory and data memory are separate

40

Next Time
Well look at multi-cycle MIPS
Adding functionality to our design

41

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