[April-13]

[EPRVD-202A]

M.Tech. Degree Examination

VLSI Design
II SEMESTER
DIGITAL SYSTEMS TESTING AND TESTABILITY
(Effective from the admitted batch 201213)
Time: 3 Hours
Max.Marks: 60
--------------------------------------------------------------------------------- --------------------Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
--------------------------------------------------------------------------------------- ---------------

UNIT-I
1. a) Define the following
i) Process yield
ii) A.C. Parametric tests
iii) Wired logic and bidirectionality
b) What are fabrication errors how are they modeled?
c) What are the various delay models associated with the behavior
of components in a model? Explain them
OR
2. a) Construct a truth table of a 2 input NAND gate for the
8-valued logic
b) What is meant by fault dominance? What is meant by
dominance fault collapsing?
c) Determine the total number of stuck-at (single and multiple)
faults for a logic circuit with n lines

4
4
4

4
4
4

UNIT-II
3. a) Use D-algorithm to perform ATPG for the SA1 fault on fan-put
brands h in the given circuit below

b) Run PODEM algorithm for the fault detection on line r SAO

of the circuit given below

OR
4. Find tests or redundancy proof for
a) Single fault d SAO b) Single fault m SAO
c) Show that the test pattern and fault effect at q in circuit, if the
fault is testable
d) If any of these faults are redundant, remove the redundancy for
the circuit shown below
12

UNIT-III
5. Show that a test for the fault A SAO in the circuit shown below
cannot be obtained using the five-valued logic of the D-calculus.
Obtain the test for this fault using the nine-valued logic

12

OR
6. An asynchronous circuit shown below is designed to have no
memory state. Derive a test for the SAI fault on the C input of
the NAND gate and show that it is an oscillation fault. Redesign
the fault free function as a combinational circuit

12

UNIT-IV
7. Prove that the following March test algorithm detects all
stuck-open faults in the memory

{ ( w0 ); (r0 , w1 , r1 ); (r1, w0 , r0 ); (r0 , w1, r1 );

(r1 , w0 , r0 ); Delay; (r0 , w1 ); Delay; (r1 )}

12

OR
8. a) What is an appropriate fault models for a bit line shorted to a
word line in an SRAM?
b) Prove that a march test for a CFid will also deted the AND
and OR bridging faults
UNIT-V
9. What are the level sensitive scan design rules? Explain

6
6
12

OR
10. a) Compute the first eight patterns generated by the Modular
LFSR with characteristic polynomial f ( x) x3 x 1
with initial value on it is 001
b) Implement the state transition diagram for MBIST controller
for MARCH C test

6
6

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