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COMPAL CONFIDENTIAL
1

MODEL NAME : QAL81


LA-7782P (DAA00002J00)
PCB NO :
BOM P/N : TBD

GPIO MAP: E4_VC_GPIO_map_rev_0.8

Dalmore 14 DSC

Ivy Bridge + Panther POINT

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2011-05-12

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REV : 0.1 (X00)


@ : Nopop Component
CONN@ : Connector Component

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MB Type

BOM P/N

TPM

1@

3@

TCM

2@

4@

TPM DIS/TCM DIS

2@

3@

MB PCB
Part Number

Description

DAA00002J00

PCB 0LE LA-7782P REV0 M/B DSC

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
C

Title

Cover Sheet
Size

Rev
0.1

LA-7782
Date:

Document Number
Tuesday, May 24, 2011

Sheet
E

of

66

Block Diagram Compal confidential


Memory BUS (DDR3)
1

iLVDS

LVDS Switch
MAX14979

LVDS CONN
PAGE 23

Ivy Bridge

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
PAGE 12-13
1

PAGE 22

rPGA CPU

dLVDS

HDMI CONN
PAGE 26

DDRIII-DIMM X2

1333/1600 MHz

Touch Screen

Nvidia
N13M

DPE

PS8171
PAGE 26

PAGE 23

988 pins

PEG Gen3

BT 4.0

PAGE 41

PAGE 6-11

DPC
DPD
VGA

DOCKING PORT
PAGE 38

PAGE 44-51

USB2.0 [3,8]

DMI2

Lane x 8

Lane x 4

dVGA
iVGA

Video Switch
MAX14885E

DAI

CRT CONN

Camera

FDI

INTEL

SATA Repeater
PS8513B

SATA

USB

Trough LVDS Cable

E-SATA

PAGE 37

PAGE 24

SATA5

USB 2.0 Port

Panther Point-M

DOCK LAN
USB3.0 [4]

PAGE 37

On IO board

USB3.0

iLVDS

USB3.0/2.0

BGA

PAGE 36

PI5USB1457A USB
Power Share PAGE 36

PAGE 14-21

EXPRESS
Card

PCIE2

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PCI Express BUS 100MHz

1/2 Mini Card


PP

PAGE 35

PAGE 34

USB10

USB6

PAGE 34

USB4

CPU XDP Port


PCH XDP Port

RFID

S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s

LPC BUS

China TCM1.2
SSX44B

PAGE 34

33MHz

PAGE 29

PAGE 29
3

HeadPhone &
MIC Jack

MDC

HDD

PAGE 14

32M 4K sector

on IO board
DAI

Fingerprint
CONN

FP_USB

PCIE4

USH Module

E-Module

Dig.
MIC

RJ11
on IO board

SMSC SIO
ECE5048

Trough LVDS Cable

BC BUS
FFS LNG3DM
PAGE 27

PAGE 39

SMSC KBC
MEC5055

Thermal

PWM FAN

GUARDIAN III
EMC4022

PAGE 40

PAGE 22

Discrete TPM
AT97SC3204

DELL CONFIDENTIAL/PROPRIETARY
PAGE 32

Compal Electronics, Inc.

PAGE 22

TP CONN
B

KB CONN

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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PAGE 41

To Docking side

USB7

PAGE 28

Power On/Off
SW & LED

RJ45

PAGE 27

WiFi ON/OFF
DC/DC Interface

INT.Speaker

PAGE 27

W25Q32BVSSIG

USH
BCM5882

TDA8034HN

LAN SWITCH
PI3L720 PAGE 31

PAGE 14

64M 4K sector

USB5

PAGE 31

DOCK LAN

HDA Codec
92HD93

SATA Repeater
PS8520B

W25Q64CVSSIG

PAGE 32

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Smart Card

SPI

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1/2 Mini Card Full Mini Card


WLAN
WWAN

Intel Lewisville
82579LM

HD Audio I/F

Option

PCIE1

on IO board

USB Port

PAGE 33

PCI Express BUS 100MHz


PCIE5

PAGE 36

PCIE x1

OZ600FJ0

PAGE 33

PCIE3

USB3.0/2.0+PS

Card Reader

SDXC/MMC

USB3.0

PAGE 41

Title

DIS Block Diagram


Size

Rev
0.1

LA-7782
Date:

Document Number
Monday, May 30, 2011

Sheet
E

of

66

POWER STATES
USB PORT#
Signal

SLP
S3#

SLP
S4#

SLP
S5#

SLP
A#

S0 (Full ON) / M0

HIGH

HIGH

HIGH

HIGH

S3 (Suspend to RAM) / M3

LOW

HIGH

HIGH

S4 (Suspend to DISK) / M3

LOW

LOW

S5 (SOFT OFF) / M3

LOW

S3 (Suspend to RAM) / M-OFF

LOW

State

ALWAYS
PLANE

M
PLANE

SUS
PLANE

RUN
PLANE

ON

ON

ON

ON

HIGH

ON

ON

ON

HIGH

HIGH

ON

ON

LOW

LOW

HIGH

ON

HIGH

HIGH

LOW

ON

DESTINATION

CLOCKS

JUSB1 (Right side Top)

ON

JUSB2 (Right side Bottom)

OFF

OFF

JESA1 (Right side ESATA)

OFF

OFF

OFF

MLK DOCK

ON

OFF

OFF

OFF

WLAN

OFF

ON

OFF

OFF

WWAN

JMINI3(Flash)

USH->BIO

DOCKING

JUSB (Left side)

10

Express card

11

Bluetooth

12

Camera

S4 (Suspend to DISK) / M-OFF

LOW

LOW

HIGH

LOW

ON

OFF

OFF

OFF

OFF

S5 (SOFT OFF) / M-OFF

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

OFF

PCH

PM TABLE
C

power
plane

+15V_ALW

+3.3V_SUS

+5V_RUN

+3.3V_M

+5V_ALW

+1.5V_MEM

+3.3V_RUN

+1.05V_M +1.05V_M

+3.3V_ALW_PCH

+1.8V_RUN

+3.3V_RTC_LDO

+1.5V_RUN

+3.3V_M
(M-OFF)

+0.75V_DDR_VTT

SATA

DESTINATION

SATA 0

HDD

SATA 1

ODD/ E3 Module Bay

SATA 2

NA

SATA 3

NA

SATA 4

ESATA

+VCC_CORE
+1.05V_RUN_VTT

S0

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+1.05V_RUN

State

ON

ON

ON

ON

ON

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S3

ON

ON

OFF

ON

OFF

S5 S4/AC

ON

OFF

OFF

ON

OFF

S5 S4/AC don't exist

OFF

OFF

OFF

OFF

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OFF

SATA 5

Dock

need to update Power Status and PM


Table

USH

13

LCD Touch

BIO

NA

PCI EXPRESS

DESTINATION

Lane 1

MINI CARD-1 WWAN

Lane 2

MINI CARD-2 WLAN

Lane 3

Express card

Lane 4

E3 Module Bay (USB3)

Connetion

Lane 5

1/2vMINI CARD-3 PCIE

Port C

Dock DP port 2

Lane 6

MMI

Port D

Dock DP port 1

Lane 7

10/100/1G LOM

Port E

MB HDMI Conn

Lane 8

None

DSC DP/HDMI Port

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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3

Title

Index and Config.


Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, May 20, 2011

Sheet
1

of

66

EN_INVPWR

FDC654P
(Q21)

+BL_PWR_SRC

ISL62883
(PU1000)

+GPU_CORE

MODC_EN

HDDC_EN

SI3456BDV
(Q27)

SI3456BDV
(Q30)

+5V_HDD

+5V_MOD

MCARD_MISC_PWREN

DGPU_PWR_EN

+PWR_SRC
BATTERY

+VCC_CORE
1.05V_0.8V_PWROK

MCARD_WWAN_PWREN

ADAPTER
D

SI3456
(Q42)

VT1318M
(PU700)

SI3456
(Q40)

+VCC_GFXCORE
ALWON

CHARGER

+3.3V_FLASH
RT8205
(PU100)

+3.3V_WWAN

+5V_ALW

CPU1.5V_S3_GATE

AO4728
(QC3)

SIO_SLP_S3#

SIO_SLP_A#

+1.05V_M

NTGS4141N
(Q59)

+1.8V_RUN

TPS51461
(PU600)

+VCC_SA

SI3456
(Q38)

+3.3V_WLAN

SI3456
(Q49)

S13456
(Q54)

+1.5V_CPU_VDDQ

+1.5V_RUN

SIO_SLP_A#

SIO_SLP_S3#

SIO_SLP_S3#

SI3456
(Q34)

TPS22966
(U78)

SI3456
(Q58)
B

+3.3V_ALW_PCH

+3.3V_SUS

+3.3V_LAN

+3.3V_M

Pop option
Pop option

+1.0V_LAN

+3.3V_M

SI4164
(Q63)

AUX_ON

SUS_ON

PCH_ALW_ON

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SY8033
(PU300)

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+1.05V_RUN_VTT

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AUX_EN_WOWL

(PU400)

1.05V_VTTPWRGD

(PU500)

SIO_SLP_S3#

+1.5V_MEM

TPS51212

CPU_VTT_ON

0.75V_DDR_VTT_ON

DDR_ON

RT8207
(PU200)

TPS51212

SIO_SLP_S3#

+3.3V_ALW

+3.3V_RUN

+5V_RUN

+0.75V_DDR_VTT

DELL CONFIDENTIAL/PROPRIETARY

+1.05V_RUN

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

Power Rail
Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, May 20, 2011

Sheet
1

of

66

2.2K

SMBUS Address [0x9a]

+3.3V_ALW_PCH

2.2K
H14

MEM_SMBCLK

C9

MEM_SMBDATA

202

2N7002

200

DIMMA

SMBUS Address [A0]

DIMMB

SMBUS Address [A4]

2N7002
2.2K

202

PCH
D

+3.3V_LAN

2.2K
C8
G12
M16

28

LAN_SMBDATA

31

200

53

SML1_SMBCLK
A5

SMBUS Address [C8]

LOM

E14
SML1_SMBDATA

3A

LAN_SMBCLK

2.2K

53

3A

2.2K
B4

DOCK_SMB_CLK

A3

DOCK_SMB_DAT

+3.3V_ALW

SMBUS Address
127
129

DOCKING

2.2K
C

2.2K

XDP2

51

2.2K

1A

SMBUS Address [TBD]

+3.3V_ALW_PCH

B6

1A

XDP1

51

2.2K

SMBUS Address [TBD]

10K

APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13

+3.3V_RUN

10K
4

G Sensor

SMBUS Address [0x3B]


C

+3.3V_ALW
30

1B
1B

B5

LCD_SMBCLK

A4

LCD_SMDATA

WWAN

32

SMBUS Address [TBD]

2.2K

KBC

2.2K
1C
1C

A56
B59

PBAT_SMBCLK
PBAT_SMBDAT

100 ohm

100 ohm

BATTERY
CONN

SMBUS Address [0x16]

2.2K

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2.2K

USH_SMBCLK

1E

B53

USH_SMBDAT

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MEC 5065

+3.3V_ALW

M9

1E

A50

2B

A49

CARD_SMBCLK

2B

B52

CARD_SMBDAT

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+3.3V_ALW

L9

USH

SMBUS Address [0xa4]

2.2K

2.2K

+3.3V_SUS

7
8

Express card

SMBUS Address [TBD]

2.2K
2.2K
CHARGER_SMBCLK

A47

CHARGER_SMBDAT

1G
1G

+3.3V_ALW

B50

Charger

SMBUS Address [0x12]

2.2K
2.2K

2D

B7

BAY_SMBDAT

2D

A7

BAY_SMBCLK

+3.3V_ALW
29
30

E3 Module Bay

SMBUS Address [0xd2]

2.2K
2.2K
2A
2A

+3.3V_RUN

B49

GPU_SMBCLK

T4

B48

GPU_SMBDAT

T3

Compal Electronics, Inc.


GPU

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3

Title

SMBUS Address [0xXX]

SMBUS TOPOLOGY
Size

Document Number

Rev
0.1

LA-7782
Date:
2

Friday, May 20, 2011

Sheet
1

of

66

(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2.
(2)PEG_ICOMPO use 12mil connect to RC2

JCPU1I

+1.05V_RUN_VTT

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B28
B26
A24
B23

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

G21
E22
F21
D21

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

G22
D22
F20
C21

<16>
<16>
<16>
<16>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

A21
H19
E19
F18
B21
C20
D18
E17

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

A22
G19
E20
G18
B20
C19
D19
F17

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI_FSYNC0
FDI_FSYNC1

J18
J17

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

H20

FDI_LSYNC0
FDI_LSYNC1

J19
H17

FDI0_LSYNC
FDI1_LSYNC

A18
A17
B16

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#

<16> FDI_FSYNC0
<16> FDI_FSYNC1
<16> FDI_INT
<16> FDI_LSYNC0
<16> FDI_LSYNC1

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

PCI EXPRESS* - GRAPHICS

B27
B25
A25
B24

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

<16>
<16>
<16>
<16>

FDI_INT

(1) EDP_COMPIO use 4mil trace to RC1


(2) EDP_ICOMPO use 12mil to RC1
EDP_COMP

C15
D15

C18
E16
D16
F15

PEG_COMP

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

PEG_CRX_GTX_N0
PEG_CRX_GTX_N1
PEG_CRX_GTX_N2
PEG_CRX_GTX_N3
PEG_CRX_GTX_N4
PEG_CRX_GTX_N5
PEG_CRX_GTX_N6
PEG_CRX_GTX_N7
PEG_CRX_GTX_N8
PEG_CRX_GTX_N9
PEG_CRX_GTX_N10
PEG_CRX_GTX_N11
PEG_CRX_GTX_N12
PEG_CRX_GTX_N13
PEG_CRX_GTX_N14
PEG_CRX_GTX_N15

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

PEG_CRX_GTX_P0
PEG_CRX_GTX_P1
PEG_CRX_GTX_P2
PEG_CRX_GTX_P3
PEG_CRX_GTX_P4
PEG_CRX_GTX_P5
PEG_CRX_GTX_P6
PEG_CRX_GTX_P7
PEG_CRX_GTX_P8
PEG_CRX_GTX_P9
PEG_CRX_GTX_P10
PEG_CRX_GTX_P11
PEG_CRX_GTX_P12
PEG_CRX_GTX_P13
PEG_CRX_GTX_P14
PEG_CRX_GTX_P15

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

PEG_CTX_GRX_C_N0
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_C_N8
PEG_CTX_GRX_C_N9
PEG_CTX_GRX_C_N10
PEG_CTX_GRX_C_N11
PEG_CTX_GRX_C_N12
PEG_CTX_GRX_C_N13
PEG_CTX_GRX_C_N14
PEG_CTX_GRX_C_N15

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_P15

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

PEG_CRX_GTX_N[0..15] <45>

PEG_CRX_GTX_P[0..15] <45>

eDP

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

PEG_CTX_GRX_P[0..15]

PEG_CTX_GRX_P[0..15] <45>

PEG_CTX_GRX_N[0..15]

PEG_CTX_GRX_N[0..15] <45>

PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_N0

CC1
CC2

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CTX_GRX_P0
PEG_CTX_GRX_N0

PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_N1

CC3
CC4

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CTX_GRX_P1
PEG_CTX_GRX_N1

PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_N2

CC5
CC6

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CTX_GRX_P2
PEG_CTX_GRX_N2

PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_N3

CC7
CC8

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CTX_GRX_P3
PEG_CTX_GRX_N3

PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_N4

CC9 2
CC10 2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CTX_GRX_P4
PEG_CTX_GRX_N4

PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_N5

CC11 2
CC12 2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CTX_GRX_P5
PEG_CTX_GRX_N5

PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_N6

CC13 2
CC14 2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CTX_GRX_P6
PEG_CTX_GRX_N6

PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_N7

CC15 2
CC16 2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CTX_GRX_P7
PEG_CTX_GRX_N7

PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_N8

CC17 1
CC18 1

2 0.22U_0402_16V7K~D
2 0.22U_0402_16V7K~D

PEG_CTX_GRX_P8
PEG_CTX_GRX_N8

PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_N9

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

VSS

m
o
c
.
x
i
f
n
a
ub

h
z
.
w
w

w
/
/
:
p
htt

eDP_AUX
eDP_AUX#

C17
F16
C16
G15

J22
J21
H22

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

Intel(R) FDI

JCPU1A

RC2
24.9_0402_1%~D
D

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

CC19 1
CC20 1

2 0.22U_0402_16V7K~D
2 0.22U_0402_16V7K~D

PEG_CTX_GRX_P9
PEG_CTX_GRX_N9

PEG_CTX_GRX_C_P10 CC21 1
PEG_CTX_GRX_C_N10 CC22 1

2 0.22U_0402_16V7K~D
2 0.22U_0402_16V7K~D

PEG_CTX_GRX_P10
PEG_CTX_GRX_N10

PEG_CTX_GRX_C_P11 CC23 1
PEG_CTX_GRX_C_N11 CC24 1

2 0.22U_0402_16V7K~D
2 0.22U_0402_16V7K~D

PEG_CTX_GRX_P11
PEG_CTX_GRX_N11

PEG_CTX_GRX_C_P12 CC25 1
PEG_CTX_GRX_C_N12 CC26 1

2 0.22U_0402_16V7K~D
2 0.22U_0402_16V7K~D

PEG_CTX_GRX_P12
PEG_CTX_GRX_N12

PEG_CTX_GRX_C_P13 CC27 1
PEG_CTX_GRX_C_N13 CC28 1

2 0.22U_0402_16V7K~D
2 0.22U_0402_16V7K~D

PEG_CTX_GRX_P13
PEG_CTX_GRX_N13

PEG_CTX_GRX_C_P14 CC29 1
PEG_CTX_GRX_C_N14 CC30 1

2 0.22U_0402_16V7K~D
2 0.22U_0402_16V7K~D

PEG_CTX_GRX_P14
PEG_CTX_GRX_N14

PEG_CTX_GRX_C_P15 CC31 1
PEG_CTX_GRX_C_N15 CC32 1

2 0.22U_0402_16V7K~D
2 0.22U_0402_16V7K~D

PEG_CTX_GRX_P15
PEG_CTX_GRX_N15

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

DP Compensation

+1.05V_RUN_VTT

RC1
24.9_0402_1%~D
A

EDP_COMP

DELL CONFIDENTIAL/PROPRIETARY

eDP_COMPIO and ICOMPO signals should be shorted near


balls and routed with typical impedance <25 mohms

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

Ivy Bridge (1/6)


Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

of

66

1
@ RC124
1K_0402_1%~D
2 PM_DRAM_PWRGD_CPU
130_0402_1%~D

1
RC28

5
P
3

<16> PM_DRAM_PWRGD

RUNPWROK_AND

O
A

RC12
200_0402_1%~D

SYS_PWROK_XDP

74AHC1G09GW_TSSOP5~D

RC64 @
39_0402_5%~D

+1.05V_RUN_VTT

CC66
0.1U_0402_25V6K~D

2
2
200_0402_1%~D

0.1U_0402_25V6K~D
2

CC65
0.1U_0402_25V6K~D

+3.3V_ALW_PCH

1
RC18

XDP_OBS0
XDP_OBS1

Place near JXDP1

1 1

XDP_OBS2
XDP_OBS3
D

<9>
<9>

QC1 @
SSM3K7002FU_SC70-3~D

2
G
3

<11,43> RUN_ON_CPU1.5VS3#

CFG10
CFG11

CFG10
CFG11

XDP_OBS4
XDP_OBS5

The resistor for HOOK2 should beplaced


such that the stub is very small on CFG0 net
H_CPUPWRGD

INTEL suggest RC64 and QC1 NO stuff by default

1
RC51
RC6
1
RC71
@RC9
@
RC9
1
RC1251
RC127

<14,16> SIO_PWRBTN#_R
CFG0
+1.05V_RUN_VTT

<16,40> SYS_PWROK
<12,13,14,15,28,35> DDR_XDP_WAN_SMBDAT
<12,13,14,15,28,35> DDR_XDP_WAN_SMBCLK

H_THERMTRIP#
2
56_0402_5%~D
H_CATERR#
2
49.9_0402_1%~D
H_PROCHOT#
2
62_0402_5%~D

AL32

PROCHOT#

Close to JCPU1
<22> H_THERMTRIP#

2 H_THERMTRIP#_R
0_0402_5%~D

1
RC129

AN32

THERMTRIP#

<18> H_CPUPWRGD

2 VCCPWRGOOD_0_R
0_0402_5%~D

1
RC25

/
:
p
t
t
h

AP33

PM_DRAM_PWRGD_CPU

PCH_PLTRST#_R

V8

AR33

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

1
RC16 1
RC17

2
2 1K_0402_1%~D
1K_0402_1%~D

CFG16
CFG17

<9>
<9>

CFG0
CFG1

CFG0
CFG1

<9>
<9>

CFG2
CFG3

CFG2
CFG3

<9>
<9>

CFG8
CFG9

CFG8
CFG9

<9>
<9>

CFG4
CFG5

CFG4
CFG5

<9>
<9>

CFG6
CFG7

CFG6
CFG7

<9>
<9>

CLK_XDP
CLK_XDP#
XDP_RST#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

XDP_RST#_R

1
1K_0402_1%~D

PLTRST_XDP# <17>

+1.05V_RUN_VTT

Remove DPLL Ref clock (for eDP only)

1
@ RC48

CLK_XDP

2
0_0402_5%~D

CLK_XDP#
DDR3_DRAMRST#_CPU

R8

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

AK1
A5
A4

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

SM_RCOMP2 --> 15mil


SM_RCOMP1/0 --> 20mil

TCK
TMS
TRST#

TDI
TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

XDP_PRDY#
XDP_PREQ#

AR26
AR27
AP30

XDP_TCLK
XDP_TMS
XDP_TRST#

AR28
AP26

XDP_TDI_R
XDP_TDO_R

AL35

XDP_DBRESET#_R

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS3_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R

CLK_CPU_ITP <15>
CLK_CPU_ITP# <15>

1
@ RH109
1
@ RH108

2
0_0402_5%~D
2
0_0402_5%~D

CC177
0.047U_0402_16V4Z~D

2
0_0402_5%~D
2
0_0402_5%~D

RC46

1
@RC47
@
RC47

DDR_HVREF_RST <12>

M3 control
B

1
0_0402_5%~D

XDP_DBRESET#

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D

<9> CLK_XDP_ITP#

<41> DDR_HVREF_RST_GATE

RC30
RC31
RC33
RC34
RC36
RC37
RC38
RC39

<9> CLK_XDP_ITP

DDR_HVREF_RST

<15> DDR_HVREF_RST_PCH

RC26

2
0_0402_5%~D
2
0_0402_5%~D

DDR3_DRAMRST# <12>

QC2
BSS138W-7-F_SOT323-3~D

RC50
4.99K_0402_1%~D

AP29
AP27

1
RH107
1
RH106

m
o
c
.
x
i
f
n
a
ub

Max 500mils

h
z
.
w
/ww

JTAG & BPM

AM34

PWR MANAGEMENT

H_PM_SYNC

CFG16
CFG17

DPLL_REF_CLK
DPLL_REF_CLK#

PRDY#
PREQ#

<16> H_PM_SYNC

CPU_DPLL
CPU_DPLL#

RC8

SM_DRAMRST#

place RC129 near CPU

A16
A15

CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>

H_PROCHOT#_R
56_0402_5%~D

2
2 0_0402_5%~D
0_0402_5%~D

PECI

1
RC13 1
RC15

1
RC57

DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

PECI_EC

VR1 TOPOLOGY

CPU_DMI
CPU_DMI#

AN33

CATERR#

A28
A27

AL33

CLOCKS

H_CATERR#

SKTOCC#

BCLK
BCLK#

DDR3
MISC

AN34

PROC_SELECT#

MISC

<40> CPU_DETECT#

<41,60,62> H_PROCHOT#

XDP_HOOK2
SYS_PWROK_XDP

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

SAMTE_BSH-030-01-L-D-A CONN@

THERMAL

C26

<41>

H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP

2
2 1K_0402_1%~D
0_0402_5%~D
2
2 1K_0402_1%~D
0_0402_5%~D
2
20_0402_5%~D
0_0402_5%~D

JCPU1B

Follow check list 0.5

XDP_OBS6
XDP_OBS7

XDP_TCLK

<18> H_SNB_IVB#

+1.05V_RUN_VTT

JXDP1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

XDP_PREQ#
XDP_PRDY#

1
@ RC126
1
@ RC128
1
RC44

+3.3V_ALW_PCH

+1.5V_CPU_VDDQ

+3.3V_ALW_PCH
CC156
1
UC2
1 B

+1.05V_RUN_VTT

Follow DG Rev0.71 SM_DRAMPWROK topology

<40,41> RUNPWROK

XDP_DBRESET# <14,16>

XDP_TDI_R
1
RC23

XDP_TDI
0_0402_5%~D

XDP_TDO_R
1
RC24

XDP_TDO
0_0402_5%~D

PU/PD for JTAG signals


+3.3V_RUN
XDP_DBRESET#RC19 2

1 1K_0402_1%~D

XDP_TMS

RC27 2

1 51_0402_1%~D

XDP_TDI

+1.05V_RUN_VTT

For ESD concern, please put near CPU

TYCO_2013620-3_IVYBRIDGE

+3.3V_RUN
+1.05V_RUN_VTT

5
4

PCH_PLTRST#_BUF

1
2

1
2

1
RC10

2 PCH_PLTRST#_R
43_0402_5%~D

SN74LVC1G07DCKR_SC70-5~D

RC45
200_0402_1%~D
2
1

<14,17> PCH_PLTRST#

NC VCC
A
GND
Y

RC43
25.5_0402_1%~D
2
1

1
2
3

SM_RCOMP2
SM_RCOMP1
SM_RCOMP0
RC130
10K_0402_5%~D

RC4

UC1

75_0402_1%~D

CC140
0.1U_0402_25V6K~D

VCCPWRGOOD_0_R

RC42
140_0402_1%~D
2
1

Buffered reset to CPU

Avoid stub in the PWRGD path


while placing resistors RC25 & RC130

RC29 2

1 51_0402_1%~D

XDP_PREQ# @ RC32 2

1 51_0402_1%~D

XDP_TDO

RC35 2

1 51_0402_1%~D

XDP_TCLK

RC40 2

XDP_TRST#

RC41 2

51_0402_1%~D
51_0402_1%~D
A

DELL CONFIDENTIAL/PROPRIETARY

Open drain buffer

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

Ivy Bridge (1/6)


Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

of

66

JCPU1D
JCPU1C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

<12> DDR_A_BS0
<12> DDR_A_BS1
<12> DDR_A_BS2

<12> DDR_A_CAS#
<12> DDR_A_RAS#
<12> DDR_A_WE#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

AE10
AF10
V6

AE8
AD9
AF9

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_CK[0]
SA_CLK#[0]
SA_CKE[0]

AB6
AA6
V9

M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

SA_CK[1]
SA_CLK#[1]
SA_CKE[1]

AA5
AB5
V10

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

SA_CK[2]
SA_CLK#[2]
SA_CKE[2]

AB4
AA4
W9

SA_CK[3]
SA_CLK#[3]
SA_CKE[3]

AB3
AA3
W10

AK3
AL3
AG1
AH1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

AH3
AG3
AG2
AH2

M_ODT0
M_ODT1

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

C4
G6
J3
M6
AL6
AM8
AR12
AM15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

D4
F6
K3
N6
AL5
AM9
AR11
AM14

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_CAS#
SA_RAS#
SA_WE#

M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>

M_ODT0
M_ODT1

<12>
<12>

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

<12>

DDR_A_MA[0..15] <12>

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

AA9
AA7
R6

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_CK[0]
SB_CLK#[0]
SB_CKE[0]

AE2
AD2
R9

M_CLK_DDR2
M_CLK_DDR#2
DDR_CKE2_DIMMB

SB_CK[1]
SB_CLK#[1]
SB_CKE[1]

AE1
AD1
R10

M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB

SB_CK[2]
SB_CLK#[2]
SB_CKE[2]

SB_CK[3]
SB_CLK#[3]
SB_CKE[3]

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

<13> DDR_B_BS0
<13> DDR_B_BS1
<13> DDR_B_BS2

<13> DDR_B_CAS#
<13> DDR_B_RAS#
<13> DDR_B_WE#

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

AA10
AB8
AB9

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT2
M_ODT3

D7
F3
K6
N3
AN5
AP9
AK12
AP15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

C7
G3
J6
M3
AN6
AP8
AK11
AP14

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>

M_ODT2
M_ODT3

<13>
<13>

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_DQS#[0..7]

<13>

DDR_B_DQS[0..7]

<13>

m
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ub

<12>

h
z
.
w
w
w
/
/
:
p

htt

SA_BS[0]
SA_BS[1]
SA_BS[2]

<13> DDR_B_D[0..63]
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>

DDR SYSTEM MEMORY B

<12> DDR_A_D[0..63]

DDR SYSTEM MEMORY A

DDR_B_MA[0..15] <13>

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

Ivy Bridge (1/6)


Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

of

66

CFG Straps for Processor

CFG2

@ RC51
1K_0402_1%~D
D

VCC_DIE_SENSE
VSS_DIE_SENSE

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

AH27
AH26

@ T39

PAD~D

L7
AG7
AE7
AK2

@ T1
@ T2
@ T3
@ T4

PAD~D
PAD~D
PAD~D
PAD~D

W8

@ T5

PAD~D

AT26
AM33
AJ27

@ T6
@ T7
@ T8

PAD~D
PAD~D
PAD~D

T8
J16
H16
G16

@ T11
@ T13
@ T15
@ T16

PAD~D
PAD~D
PAD~D
PAD~D

PEG Static Lane Reversal - CFG2 is for the 16x

VSSAXG_VAL_SENSE
2
49.9_0402_1%~D

1
@RC123
@
RC123

PAD~D

+VCC_CORE

VCC_VAL_SNESE
2
49.9_0402_1%~D

@RC120
@
RC120

AJ26

VSS_VAL_SNESE
2
49.9_0402_1%~D

1
@RC121
@
RC121

@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

PAD~D
PAD~D

T47 @
T48 @

J20
B18

RSVD24
RSVD25

PAD~D

T52 @

J15

1
2

RSVD5

T28
T29
T30
T31
T33
T35
T36
T37
T38
T40
T41
T42
T43
T44
T45
T46

/
:
p
t
t
h

RSVD37
RSVD38
RSVD39
RSVD40

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D

@ RC71
100_0402_1%~D

T22 @

AJ31
AH31
AJ33
AH33

@ RC52
1K_0402_1%~D

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

Display Port Presence Strap

AR35
AT34
AT33
AP35
AR34

@ T17
@ T18
@ T19
@ T20
@ T21

PAD~D
PAD~D
PAD~D
PAD~D
PAD~D

B34
A33
A34
B35
C35

@ T23
@ T24
@ T25
@ T26
@ T27

PAD~D
PAD~D
PAD~D
PAD~D
PAD~D

AJ32
AK32

@ T32
@ T34

PAD~D
PAD~D

1 : Disabled; No Physical Display Port


attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG6
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10

RSVD51
RSVD52

m
o
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ub

h
z
.
w
/ww
RSVD27

CFG4

CFG5

@ RC54
1K_0402_1%~D

@ RC53
1K_0402_1%~D

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SNESE
VSS_VAL_SNESE

1:(Default) Normal Operation; Lane #


definition matches socket pin map definition
0:Lane Reversed
CFG4

RSVD33
RSVD34
RSVD35

RESERVED

@ RC69
100_0402_1%~D

CFG2

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

CFG16
CFG17

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

BCLK_ITP
BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

KEY

AN35
AM35

CLK_XDP_ITP <7>
CLK_XDP_ITP# <7>

AT2
AT1
AR1

@ T49
@ T50
@ T51

PAD~D
PAD~D
PAD~D

B1

@ T53

PAD~D

VAXG_VAL_SENSE
2
49.9_0402_1%~D

1
@RC122
@
RC122

<7>
<7>

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
PAD~D
PAD~D
PAD~D
PAD~D

CFG

<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
@ T9
@ T10
@ T12
@ T14

+VCC_GFXCORE

JCPU1E

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled


CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2


disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7
1

TYCO_2013620-3_IVYBRIDGE

@ RC56
1K_0402_1%~D

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately


following xxRESETB de assertion
0: PEG Wait for BIOS for training

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

Ivy Bridge (1/6)


Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

of

66

JCPU1F

POWER
+1.05V_RUN_VTT

+VCC_CORE

94A
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

VCCIO40

J23

+1.05V_RUN_VTT
1

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

Note: Place the PU resistors close to CPU


RC61 close to CPU 300 - 1500mils
2

m
o
c
.
x
i
f
n
a
ub

H_CPU_SVIDALRT#
1
RC61

<60>

SVID

VIDALERT#
VIDSCLK
VIDSOUT

AJ29
AJ30
AJ28

H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT

VIDSCLK

CAD Note: Place the PU


resistors close to CPU
RC63 close to CPU 300 - 1500mils

RC63
130_0402_1%~D

<60>

Iccmax current changed for PDDG Rev0.7

VIDSOUT

<60>

CPU Power Rail Table

H_CPU_SVIDALRT# must be routed between the


VIDSOUT and VIDSCLK lines to reduce cross
talk. 18 mils spacing to others.

Voltage Rail

Voltage

VCC

0.65-1.3

VCCIO

+VCC_CORE

RC66
100_0402_1%~D

1.05

8.5

0.0-1.1

26

VCCPLL

1.8

VDDQ

1.5

VCCSA

0.65-0.9

VTT_SENSE
VSSIO_SENSE_R

VCCSENSE
VSSSENSE
+1.05V_RUN_VTT

+1.5V_MEM

<60>
<60>

1.5

12-16

RC70
100_0402_1%~D

VTT_SENSE <58>
VSSIO_SENSE_R <58>

Description

5A to Mem controller(+1.5V_CPU_VDDQ)
5-6A to 2 DIMMs/channel
2-5A to +1.5V_RUN & +0.75V_DDR_VTT
A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

TYCO_2013620-3_IVYBRIDGE
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

53

2
20_0402_5%~D
0_0402_5%~D
2
1
RC98
10_0402_1%~D

B10
A10

1
RC67 1
RC68

VCCIO_SENSE
VSS_SENSE_VCCIO

VCCSENSE_R
VSSSENSE_R

VCC_SENSE
VSS_SENSE

AJ35
AJ34

@ RC75
100_0402_1%~D
1
2

S0 Iccmax
Current (A)

Place RC66, RC70, RC75 near CPU

RC133
10_0402_1%~D

VIDALERT_N

VAXG

SENSE LINES

htt

2
43_0402_5%~D

+1.05V_RUN_VTT

h
z
.
w
w
w
/
/
:
p

RC60
75_0402_1%~D

PEG AND DDR

8.5A
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

CORE SUPPLY

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

www.vinafix.vn
3

Ivy Bridge (1/6)


Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

10

of

66

+1.5V_CPU_VDDQ Source

1
2

2
1

3
1

1
2

@ QC5
NTR4503NT1G_SOT23-3~D

@
2

2
3
4

1
1
2

2
0_0402_5%~D

JCPU1H

+V_SM_VREF_CNT

RC78
1K_0402_1%~D

+1.5V_CPU_VDDQ

1
@ RC134

RC84
1K_0402_1%~D

+V_DDR_SMREF

RC81
1K_0402_1%~D

QC4A
DMN66D0LDW-7_SOT363-6~D

+1.5V_MEM
RC80
1K_0402_1%~D

2
0_0402_5%~D

RC73
20K_0402_5%~D

1
@RC79
@
RC79

CC136
0.1U_0603_50V7K~D

RC143
330K_0402_1%~D

<41> CPU1.5V_S3_GATE

2
0_0402_5%~D

RUN_ON_CPU1.5VS3
QC4B
DMN66D0LDW-7_SOT363-6~D

RUN_ON_CPU1.5VS3#

1
RC82

CC135
10U_0603_6.3V6M~D

+1.5V_CPU_VDDQ
1
2
3

RC72
100K_0402_5%~D

RC74
100K_0402_5%~D

<16,28,36,40,43,56> SIO_SLP_S3#

QC3
AO4728L_SO8~D

8
7
6
5

+PWR_SRC_S

+1.5V_MEM
+3.3V_ALW2

RUN_ON_CPU1.5VS3

RUN_ON_CPU1.5VS3# <7,43>

+VCC_GFXCORE
1

POWER

+VCC_GFXCORE

RC99
10_0402_1%~D

JCPU1G

VREF

2
SM_VREF

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

SA RAIL

GRAPHICS

+
2

CC1792

1 0.1U_0402_10V7K~D

CC1492

1 0.1U_0402_10V7K~D

CC1502

1 0.1U_0402_10V7K~D

+1.5V_MEM

6A
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_SENSE

M27
M26
L26
J26
J25
J24
H26
H25

1
+
2

CC172
330U_D2_2VM_R6M~D

VSS

H23

+VCC_SA

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

TYCO_2013620-3_IVYBRIDGE

VCCSA_SENSE <59>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

VCCSA_VID[0]
VCCSA_VID[1]

C22
C24

VCCIO_SEL

A19

VCCSA_VID_0 <59>
VCCSA_VID_1 <59>

DELL CONFIDENTIAL/PROPRIETARY
1
RC140

2
0_0402_5%~D

Compal Electronics, Inc.

VCCP_PWRCTRL <58>
Title

Ivy Bridge (1/6)

TYCO_2013620-3_IVYBRIDGE

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

added VCCSA_VID_0 to Power page

MISC

1.8V RAIL

1 0.1U_0402_10V7K~D

CC167

330U_D2_2VM_R6M~D

CC166
10U_0402_6.3V6M

CC1782

6A

CC171
10U_0603_6.3V6M~D

VCCPLL1
VCCPLL2
VCCPLL3

CC170
10U_0603_6.3V6M~D

B6
A6
A2

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

+1.5V_CPU_VDDQ

CC165
10U_0402_6.3V6M

h
z
.
w
w

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

5A

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

m
o
c
.
x
i
f
n
a
ub

+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU

CC169
10U_0603_6.3V6M~D

CC175
1U_0402_6.3V6K~D

CC174
1U_0402_6.3V6K~D

CC173
10U_0603_6.3V6M~D

CC176
330U_D2_2.5VM_R6M~D

+1.8V_RUN

+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU

B4
D1

CC168
10U_0603_6.3V6M~D

1.5A

+V_SM_VREF should
have 10 mil trace width

AL1

CC164
10U_0402_6.3V6M

2 +DIMM0_1_VREF_CPU
1K_0402_1%~D
2 +DIMM0_1_CA_CPU
1K_0402_1%~D

+V_SM_VREF_CNT

CC163
10U_0402_6.3V6M

1
@ RC96
1
@ RC97

VCC_AXG_SENSE <60>
VSS_AXG_SENSE <60>
RC100
10_0402_1%~D

w
/
/
:
p
htt

AK35
AK34
1

SENSE
LINES

VAXG_SENSE
VSSAXG_SENSE

CC162
10U_0402_6.3V6M

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

CC161
10U_0402_6.3V6M

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

DDR3 -1.5V RAILS

46A

@ RC76
100_0402_1%~D
1
2

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

www.vinafix.vn
3

Size

Document Number

Rev
0.1

LA-7782
Date:
2

Friday, June 10, 2011

Sheet
1

11

of

66

2
0_0402_5%~D

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9

DDR_A_D10
DDR_A_D11

Populate RD1, De-Populate RD7 for Intel DDR3


VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3

DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19

DDR_A_D26
DDR_A_D27

<8> DDR_A_D[0..63]
<8> DDR_A_DQS[0..7]
<8> DDR_A_MA[0..15]
<8> DDR_CKE0_DIMMA

Layout Note:
Place near JDIMM1

DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

CD6
1U_0402_6.3V6K~D

CD5
1U_0402_6.3V6K~D

CD4
1U_0402_6.3V6K~D

CD3
1U_0402_6.3V6K~D

<8> M_CLK_DDR0
<8> M_CLK_DDR#0
<8> DDR_A_BS0
<8> DDR_A_WE#
<8> DDR_A_CAS#

M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#

htt

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51

Layout Note:
Place near JDIMM1.203,204

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59
RD21
+0.75V_DDR_VTT

CD20
1U_0402_6.3V6K~D

CD19
1U_0402_6.3V6K~D

CD18
1U_0402_6.3V6K~D

CD17
1U_0402_6.3V6K~D

CD22
2.2U_0603_6.3V6K~D

2 10K_0402_5%~D
+3.3V_RUN
2
10K_0402_5%~D

CD21
0.1U_0402_25V6K~D

1
RD3

205

GND1

+0.75V_DDR_VTT

GND2

206

DDR3_DRAMRST#_R 1
RD28

2
1K_0402_1%~D

DDR3_DRAMRST# <7>

DDR_A_D20
DDR_A_D21
@ RD29 1

DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
<7> DDR_HVREF_RST

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

QD1
1 BSS138_NL_SOT23-3

+V_DDR_REFA_M3

DDR_HVREF_RST

@ RD30 1

2 0_0402_5%~D

DDR_CKE1_DIMMA <8>

DDR_A_MA15
DDR_A_MA14

QD2
1 BSS138_NL_SOT23-3

+DIMM0_1_CA_CPU

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4

+V_DDR_REFB_M3

DDR_HVREF_RST

DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1

2 0_0402_5%~D

+DIMM0_1_VREF_CPU

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

m
o
c
.
x
i
f
n
a
ub

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#
M_ODT0
M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>

DDR_CS0_DIMMA# <8>
M_ODT0
<8>
+DIMM1_VREF_CA
M_ODT1
<8>

2
RD11

1
0_0402_5%~D

+V_DDR_REF

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

DDR_XDP_WAN_SMBDAT <7,13,14,15,28,35>
DDR_XDP_WAN_SMBCLK <7,13,14,15,28,35>
+0.75V_DDR_VTT
A

TYCO_2-2013289-2~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DDR_A_D14
DDR_A_D15

CD16
0.1U_0402_25V6K~D

DDR_A_D34
DDR_A_D35

<13> DDR3_DRAMRST#_R

DDR3_DRAMRST#_R

CD15

CD14
330U_SX_2VY~D

@ CD13

10U_0603_6.3V6M~D
CD51

10U_0603_6.3V6M~D
CD11

10U_0603_6.3V6M~D
CD10

10U_0603_6.3V6M~D
CD9

10U_0603_6.3V6M~D
CD8

10U_0603_6.3V6M~D
CD7

10U_0603_6.3V6M~D

DDR_A_DQS#4
DDR_A_DQS4

RD27
1K_0402_1%~D

DDR_A_D12
DDR_A_D13

2.2U_0603_6.3V6K~D

DDR_A_D32
DDR_A_D33

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_D6
DDR_A_D7

h
z
.
w
w
w
/
/
:
p
<8> DDR_CS1_DIMMA#

+1.5V_MEM

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

+1.5V_MEM
DDR_A_DQS#0
DDR_A_DQS0

DDR_A_MA12
DDR_A_MA9

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

DDR_A_D4
DDR_A_D5

DDR_A_BS2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

<8> DDR_A_BS2

DDR_CKE0_DIMMA

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

<8> DDR_A_DQS#[0..7]

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

DDR_A_D24
DDR_A_D25

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

All VREF traces should


have 10 mil trace width

+1.5V_MEM

2-3A to 1 DIMMs/channel

+1.5V_MEM
JDIMM1 CONN@

DDR_A_DQS#1
DDR_A_DQS1

JDIMM1 H=5.2

+1.5V_MEM

CD2
0.1U_0402_25V6K~D

2
D

CD1
2.2U_0603_6.3V6K~D

+DIMM1_VREF_DQ

2
0_0402_5%~D

1
RD1

+V_DDR_REF

1
RD7

+V_DDR_REFA_M3

www.vinafix.vn
3

DDRIII-SODIMM SLOT1
Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

12

of

66

2-3A to 1 DIMMs/channel
+DIMM2_VREF_DQ

+1.5V_MEM

+1.5V_MEM
JDIMM2 CONN@

+V_DDR_REFB_M3

1
RD4

2
0_0402_5%~D

CD24
0.1U_0402_25V6K~D

2
0_0402_5%~D

CD23
2.2U_0603_6.3V6K~D

+V_DDR_REF

1
RD8

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19

Populate RD4, De-Populate RD8 for Intel DDR3


VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

<8> DDR_B_DQS#[0..7]

All VREF traces should


have 10 mil trace width

<8> DDR_B_D[0..63]
<8> DDR_B_DQS[0..7]

DDR_CKE2_DIMMB

<8> DDR_CKE2_DIMMB

<8> DDR_B_MA[0..15]

DDR_B_BS2

<8> DDR_B_BS2
C

DDR_B_MA12
DDR_B_MA9

Layout Note:
Place near JDIMM2

DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2

<8> M_CLK_DDR2
<8> M_CLK_DDR#2

+1.5V_MEM

DDR_B_MA10
DDR_B_BS0

<8> DDR_B_BS0

DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57

Layout Note:
Place near JDIMM2.203,204

DDR_B_D58
DDR_B_D59

CD42
1U_0402_6.3V6K~D

CD41
1U_0402_6.3V6K~D

CD40
1U_0402_6.3V6K~D

CD39
1U_0402_6.3V6K~D

CD44
2.2U_0603_6.3V6K~D

+0.75V_DDR_VTT
CD43
0.1U_0402_25V6K~D

+3.3V_RUN
1
10K_0402_5%~D

RD6
10K_0402_5%~D

2
RD5

+0.75V_DDR_VTT

+3.3V_RUN

205

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D4
DDR_B_D5

DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#_R

DDR3_DRAMRST#_R <12>

DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB <8>

DDR_B_MA15
DDR_B_MA14
C

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3

GND1

GND2

DDR_B_BS1
DDR_B_RAS#

M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>

DDR_CS2_DIMMB#
M_ODT2
M_ODT3

DDR_B_BS1 <8>
DDR_B_RAS# <8>

DDR_CS2_DIMMB# <8>
M_ODT2
<8>
+DIMM2_VREF_CA
M_ODT3
<8>

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45

2
RD15

1
0_0402_5%~D

+V_DDR_REF

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63

DDR_XDP_WAN_SMBDAT <7,12,14,15,28,35>
DDR_XDP_WAN_SMBCLK <7,12,14,15,28,35>
+0.75V_DDR_VTT

206

TYCO_2-2013310-2~D

www.vinafix.vn
3

DDR_B_D14
DDR_B_D15

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

JDIMM2 H=9.2

DDR_B_DQS#0
DDR_B_DQS0

CD38
0.1U_0402_25V6K~D

CD36
330U_SX_2VY~D

@ CD35
10U_0603_6.3V6M~D

/
:
p
t
t
h

DDR_B_DQS#4
DDR_B_DQS4

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

m
o
c
.
x
i
f
n
a
ub

h
z
.
w
/ww
DDR_B_D32
DDR_B_D33

CD34
10U_0603_6.3V6M~D

CD33
10U_0603_6.3V6M~D

CD32
10U_0603_6.3V6M~D

CD31
10U_0603_6.3V6M~D

CD30
10U_0603_6.3V6M~D

CD29
10U_0603_6.3V6M~D

DDR_B_MA13
DDR_CS3_DIMMB#

<8> DDR_CS3_DIMMB#

+1.5V_MEM

DDR_B_WE#
DDR_B_CAS#

<8> DDR_B_WE#
<8> DDR_B_CAS#

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

CD37
2.2U_0603_6.3V6K~D

CD28
1U_0402_6.3V6K~D

CD27
1U_0402_6.3V6K~D

CD26
1U_0402_6.3V6K~D

CD25
1U_0402_6.3V6K~D

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

Title

DDRIII-SODIMM SLOT2
Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

13

of

66

Keep ME RTC Registers

+RTC_CELL

<18> PCH_GPIO36
<18> PCH_GPIO37
<18> PCH_GPIO16
<18,40> TEMP_ALERT#
<18> PCH_GPIO15
<18> SIO_EXT_SCI#_R

PCH_AZ_SYNC

RH282 @
100K_0402_5%~D

33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
2 RSMRST#_XDP
1K_0402_1%~D

<16,42> PCH_RSMRST#_Q

PXDP@ RH24

PCH_INTVRMEN

CH2
15P_0402_50V8J~D
2
1

PCH_RTCX1

On Die PLL VR is supplied by


1.5V when sampled high, 1.8 V
when sampled low

YH1
32.768KHZ_12.5PF_Q13FC1350000~D

RH2
10M_0402_5%~D

1
RH22
1
RH23
1
RH11

+RTC_CELL

PCH_RTCX2_R 1
RH286

2
0_0402_5%~D

2
20K_0402_5%~D
2
20K_0402_5%~D
2
1M_0402_5%~D

<31> PCH_AZ_MDC_BITCLK
@
ME1

1
CH5

<31> PCH_AZ_MDC_SYNC

@
CMOS1 SHORT PADS~D
1
2
1U_0402_6.3V6K~D
CH4

SHORT PADS~D
2
1U_0402_6.3V6K~D

<30>

<30> PCH_AZ_CODEC_SDOUT
<30> PCH_AZ_CODEC_SYNC
<30> PCH_AZ_CODEC_RST#
<30> PCH_AZ_CODEC_BITCLK

INTVRMEN

N34

HDA_BCLK

T10

2
1K_0402_1%~D
2
33_0402_5%~D
2
1K_0402_1%~D

1
RH36
1
RH50

<31> PCH_AZ_MDC_SDOUT
ME_FWP

PCH_AZ_RST#

K34

PCH_AZ_CODEC_SDIN0

E34

PCH_AZ_MDC_SDIN1

G34
C34

<40>

INTRUDER#

<29> USB30_SMI#

RH288
0_0603_5%~D

HDA_RST#

A36

HDA_SDO

1 51_0402_1%~D

PCH_JTAG_TCK

J3

RH44 2

1 200_0402_1%~D

PCH_JTAG_TMS

H7

RH45 2

1 200_0402_1%~D

PCH_JTAG_TDI

K5

RH43 2

1 200_0402_1%~D

PCH_JTAG_TDO

H1

E36
K36

LPC_LDRQ0#
LPC_LDRQ1#

V5

IRQ_SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

HDA_SDIN2

C36
N32

LDRQ0#
LDRQ1# / GPIO23

HDA_SDIN1

PCH_GPIO33
USB30_SMI#

LPC_LFRAME#

HDA_SDIN0

PCH_AZ_SDOUT

RH59 2

SPKR

HDA_SDIN3

D36

SERIRQ

HDA_SYNC

A34

+3.3V_ALW_PCH

+3.3V_ALW_PCH_JTAG

L34

FWH4 / LFRAME#

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

SRTCRST#

K22

2
33_0402_5%~D

@ RH287

RTCRST#

C17

1
RH34

<31> PCH_AZ_MDC_SDIN1
+3.3V_ALW_PCH

RTCX2

PCH_INTVRMEN

PCH_AZ_BITCLK
2
33_0402_5%~D
PCH_AZ_SYNC
2PCH_AZ_SYNC_Q
33_0402_5%~D

@ CH101
@CH101
27P_0402_50V8J~D

2 PCH_AZ_SDOUT
33_0402_5%~D
2 PCH_AZ_SYNC_Q
33_0402_5%~D
2 PCH_AZ_RST#
33_0402_5%~D
2 PCH_AZ_BITCLK
33_0402_5%~D

G22

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

RTCX1

INTRUDER#

1
RH32
1
RH33

<30> PCH_AZ_CODEC_SDIN0

1
RH29
1
RH26
1
RH27
1
RH25

D20

SPKR

<31> PCH_AZ_MDC_RST#

CMOS place near DIMM

C20

PCH_RTCRST#
SRTCRST#

2
1
@CH100
@
CH100
27P_0402_50V8J~D
1

PCH_RTCX2

C38
A38
B37
C37

LPC

Low - Enable External VRs

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

HDA_DOCK_EN# / GPIO33

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_RST# / GPIO13

JTAG_TCK

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TMS

SATAICOMPO

JTAG_TDI
JTAG_TDO

SATAICOMPI

+5V_RUN

INTEL HDA_SYNC
isolation circuit

SATA3COMPI

PCH_SPI_CLK

T3

PCH_SPI_CS0#

Y14

PCH_SPI_CS1#

T1

PCH_SPI_DO

V4

PCH_SPI_DIN

U3

SPI_CLK

SATA3RBIAS

XDP_FN10
XDP_FN11

XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15

+3.3V_ALW_PCH

RSMRST#_XDP
XDP_DBRESET#

XDP_DBRESET# <7,16>

PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TMS

CONN@

SPI_CS1#

SPI_MOSI

SATALED#

SATA0GP / GPIO21

SPI_MISO

SATA1GP / GPIO19

LPC_LDRQ0#
LPC_LDRQ1#

<40>
<40>

IRQ_SERIRQ

<33,40,41>

PCH_GPIO33 2
RH355

1
100K_0402_5%~D

IRQ_SERIRQ 2
RH28

1
8.2K_0402_5%~D

SATA_ODD_PRX_DTX_N1_C
SATA_ODD_PRX_DTX_P1_C
SATA_ODD_PTX_DRX_N1_C
SATA_ODD_PTX_DRX_P1_C

ODD/ E Module Bay

BBS_BIT0_R

<29>
<29>
<29>
<29>

2
1
RH52
4.7K_0402_5%~D
INTEL feedback 0302

+3.3V_RUN

AD7
AD5
AH5
AH4

SPKR

AB8
AB10
AF3
AF1

2
@ RH35

1
10K_0402_5%~D

No Reboot Strap
Low = Default
SPKR

Y7
Y5
AD3
AD1

ESATA_PRX_DTX_N4_C
ESATA_PRX_DTX_P4_C
ESATA_PTX_DRX_N4_C
ESATA_PTX_DRX_P4_C

SATA_COMP

Y10
AB12
AB13

P3

E-SATA

SATA_PRX_DKTX_N5_C <39>
SATA_PRX_DKTX_P5_C <39>
SATA_PTX_DKRX_N5_C <39>
SATA_PTX_DKRX_P5_C <39>
+1.05V_RUN

Y11

AH1

High = No Reboot

<38>
<38>
<38>
<38>

m
o
c
.
x
i
f
n
a
ub

Y3
Y1
AB3
AB1

1
RH40

DOCK

2
37.4_0402_1%~D

+1.05V_RUN

SATA3_COMP

1
RH42

2
49.9_0402_1%~D

RBIAS_SATA3

1
RH46

2
750_0402_1%~D

+3.3V_RUN

RH30
10K_0402_5%~D

SATA_ACT#

V14

HDD_DET#_R

P1

BBS_BIT0_R

BBS_BIT0 - BIOS BOOT STRAP BIT 0

+3.3V_SPI

+3.3V_RUN

LPC_LFRAME# <33,35,40,41>

AM10
AM8
AP11
AP10

BD82PPSM-QNHN-A0_BGA989~D

C746
0.1U_0402_25V6K~D
1
2

LPC_LAD0 <33,35,40,41>
LPC_LAD1 <33,35,40,41>
LPC_LAD2 <33,35,40,41>
LPC_LAD3 <33,35,40,41>

SATA_ACT#

<44>

1
RH290
3

1
QH1

2
0_0402_5%~D

HDD_DET#

<28>
B

PCH_SATA_MOD_EN#

<41>

BSS138W-7-F_SOT323-3~D

<7,17> PCH_PLTRST#

C745
0.1U_0402_25V6K~D
1
2

+3.3V_SPI

XDP_FN8
XDP_FN9

HDD

SPI_CS0#

SPI

2
1
RH48
100_0402_1%~D
2
1
RH49
100_0402_1%~D
2
1
RH47
100_0402_1%~D

QH7
SSM3K7002FU_SC70-3~D

XDP_FN16
XDP_FN17

PSATA_PRX_DTX_N0_C <28>
PSATA_PRX_DTX_P0_C <28>
PSATA_PTX_DRX_N0_C <28>
PSATA_PTX_DRX_P0_C <28>

PCH_AZ_SYNC

2
1M_0402_5%~D

htt
D

PCH_AZ_SYNC_Q

1
RH31

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

AM3
AM1
AP7
AP5

h
z
.
w
w
w
/
/
:
p
SATA3RCOMPO

Follow INTEL CRB 0.7

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

SAMTE_BSH-030-01-L-D-A

A20

CH3
15P_0402_50V8J~D
2
1

* High - Enable Internal VRs

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

UH4A

INTVRMEN- Integrated SUS


1.1V VRM Enable

<7,12,13,15,28,35>
<7,12,13,15,28,35>

@ RH39
@RH39
330K_0402_1%~D

SATA 6G

RH38
330K_0402_1%~D

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

SATA

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Open

RH66
1K_0402_1%~D

RH1
RH3
RH4
RH5
RH6
RH7
RH8
RH9
RH10
RH12
RH13
RH14
RH15
RH16
RH17
RH18
RH19
RH20

Clear ME RTC Registers


2

Shunt

PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@
PXDP@

JXDP2

ME_CLR1 TPM setting

USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
SLP_ME_CSW_DEV#
USB_MCARD1_DET#
HDD_DET#_R
BBS_BIT0_R
PCH_GPIO36
PCH_GPIO37
PCH_GPIO16
TEMP_ALERT#
PCH_GPIO15
SIO_EXT_SCI#_R

<17> USB_OC0#_R
<17> USB_OC1#_R
<17> USB_OC2#
<17> USB_OC3#
<17> USB_OC4#_R
<17> USB_OC5#
<17> USB_OC6#
<17,41> SIO_EXT_SMI#
<18,40> SLP_ME_CSW_DEV#
<18,35> USB_MCARD1_DET#

+3.3V_ALW_PCH

RTC

Keep CMOS

IHDA

Clear CMOS

Open

+3.3V_ALW_PCH
XDP_FN0
1
+3.3V_ALW_PCH
XDP_FN1
3
XDP_FN2
5
XDP_FN3
7
1
XDP_FN4
XDP_FN0
PXDP@
9
CH1
XDP_FN5
XDP_FN1
11
XDP_FN6
0.1U_0402_25V6K~D
13
2
XDP_FN7
XDP_FN2
15
XDP_FN8
XDP_FN3
17
XDP_FN9
19
XDP_FN10
21
XDP_FN11
23
XDP_FN12
25
XDP_FN13
XDP_FN4
27
XDP_FN14
XDP_FN5
29
XDP_FN15
31
XDP_FN16
XDP_FN6
33
XDP_FN17
XDP_FN7
35
PXDP@ RH283
1K_0402_1%~D
37
1.05V_0.8V_PWROK_R
1
2
39
<41,60> 1.05V_0.8V_PWROK
PCH_PWRBTN#_XDP
1
2
41
<7,16> SIO_PWRBTN#_R
PXDP@ RH21
0_0402_5%~D
43
45
47
PXDP@ RH284
0_0402_5%~D
49
1
2 DDR_XDP_WAN_SMBDAT_R2
51
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK_R2
1
2
53
DDR_XDP_WAN_SMBCLK
PXDP@ RH285
0_0402_5%~D
55
PCH_JTAG_TCK
57
59

JTAG

Shunt

PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
So signal should be PU to the ALWAYS rail.

CMOS setting

2
G

CMOS_CLR1

<40> SPI_WP#_SEL

2 SPI_PCH_CS0#_R
47_0402_5%~D
2 SPI_DIN64
33_0402_5%~D
2 SPI_WP#_SEL_R
0_0402_5%~D

1
2
3
4

/CS
DO

JSPI1

16Mb Flash ROM

U52

U53

VCC
/HOLD

/WP

CLK

GND

DIO

1
R935
SPI_PCH_DIN
1
R894
SPI_WP#_SEL
1
@ R898

R891
3.3K_0402_5%~D

64Mb Flash ROM


2

SPI_PCH_CS0#

200 MIL SO8

200 MIL SO8

R890
3.3K_0402_5%~D

SPI_HOLD#

7
6
5

SPI_CLK64

1
R899
SPI_DO64
1
R901

2 SPI_PCH_CLK
33_0402_5%~D
2 SPI_PCH_DO
33_0402_5%~D

SPI_PCH_CS1# 1
R936
SPI_PCH_DIN 1
R895
SPI_WP#_SEL_R

2 SPI_PCH_CS1#_R
47_0402_5%~D
2 SPI_DIN32
33_0402_5%~D

1
2
3
4

CS#
DO
WP#
GND

VCC
HOLD#
CLK
DI

8
7
6
5

W25Q32BVSSIG_SO8~D

SPI_CLK32

1
R897
SPI_DO32
1
R900

SPI_HOLD#
2 SPI_PCH_CLK
33_0402_5%~D
2 SPI_PCH_DO
33_0402_5%~D

W25Q64CVSSIG_SO8~D

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

G1
G2

17
18

SPI_PCH_CS1#
PCH_SPI_CS1#
SPI_PCH_DO
PCH_SPI_DO
SPI_PCH_DIN
PCH_SPI_DIN
SPI_PCH_CLK
PCH_SPI_CLK
SPI_PCH_CS0#
PCH_SPI_CS0#

RH345

0_0402_5%~D

RH346

0_0402_5%~D

RH347

0_0402_5%~D

RH348

0_0402_5%~D

RH349

0_0402_5%~D
+3.3V_SPI

+3.3V_M

RH350

0_0402_5%~D

HRS_FH12-16S-0P5SH(55)~D
CONN@

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Title

www.vinafix.vn
Size

Date:

PCH (1/8)

Document Number

Rev
0.1

LA-7782

Friday, June 10, 2011

Sheet
1

14

of

66

+3.3V_RUN

MEM_SMBCLK

QH5A
DMN66D0LDW-7_SOT363-6~D
1

DDR_XDP_WAN_SMBCLK <7,12,13,14,28,35>

MEM_SMBDATA

DDR_XDP_WAN_SMBDAT <7,12,13,14,28,35>

QH5B
DMN66D0LDW-7_SOT363-6~D

UH4B

<32>
<32>
<32>
<32>

PCIE_PRX_MMITX_N6
PCIE_PRX_MMITX_P6
PCIE_PTX_MMIRX_N6
PCIE_PTX_MMIRX_P6
PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7

PCIE_PRX_MMITX_N6
PCIE_PRX_MMITX_P6
PCIE_PTX_MMIRX_N6
PCIE_PTX_MMIRX_P6

BJ38
BG38
AU36
AV36

PERN6
PERP6
PETN6
PETP6

PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7

BG40
BJ40
AY40
BB40
BE38
BC38
AW38
AY38

WWAN (Mini Card 1)--->

10/100/1G LAN --->

<35> CLK_PCIE_MINI1#
<35> CLK_PCIE_MINI1
+3.3V_ALW_PCH
<35> MINI1CLK_REQ#

<32> CLK_PCIE_LAN#
<32> CLK_PCIE_LAN

2
RH3072
RH3082
RH81

1
10_0402_5%~D
10_0402_5%~D
10K_0402_5%~D

PCIE_MINI1#
PCIE_MINI1

2
RH82 2
RH83

1
1 0_0402_5%~D
0_0402_5%~D

PCIE_LAN#
PCIE_LAN

PP (Mini Card 3)--->

Express card--->

WLAN (Mini Card 2)--->

<34> CLK_PCIE_MMI#
<34> CLK_PCIE_MMI
+3.3V_RUN
<34> MMICLK_REQ#

MINI1CLK_REQ#

J2
AB49
AB47

2
RH85 2
RH86 1
RH87

1
1 0_0402_5%~D
2 0_0402_5%~D
10K_0402_5%~D

PCIE_MMI#
PCIE_MMI

M1

AA48
AA47

w
/
/
:
p
htt

<35> CLK_PCIE_MINI3#
<35> CLK_PCIE_MINI3
+3.3V_ALW_PCH
<35> MINI3CLK_REQ#

2
RH88 2
RH90 2
RH152

1
1 0_0402_5%~D
1 0_0402_5%~D
10K_0402_5%~D

MMICLK_REQ#
PCIE_MINI3#
PCIE_MINI3

MINI3CLK_REQ#

V10
Y37
Y36
A8

<36> CLK_PCIE_EXP#
<36> CLK_PCIE_EXP
+3.3V_ALW_PCH
<36> EXPCLK_REQ#

2
RH92 2
RH93 2
RH94

1
1 0_0402_5%~D
1 0_0402_5%~D
10K_0402_5%~D

PCIE_EXP#
PCIE_EXP

Y43
Y45

EXPCLK_REQ#

L12

<35> CLK_PCIE_MINI2#
<35> CLK_PCIE_MINI2
+3.3V_ALW_PCH
<35> MINI2CLK_REQ#

2
RH95 2
RH96 2
RH97

1
1 0_0402_5%~D
1 0_0402_5%~D
10K_0402_5%~D

PCIE_MINI2#
PCIE_MINI2

V45
V46

MINI2CLK_REQ#

L14
AB42
AB40

+3.3V_ALW_PCH

1
RH98

2
10K_0402_5%~D

PEG_B_CLKRQ#

E6
V40
V42
T13

eModule Bay--->

<29> CLK_PCIE_EMB#
<29> CLK_PCIE_EMB
+3.3V_ALW_PCH
<29> EMBCLK_REQ#

2
RH3102
RH3122
RH104

1
10_0402_5%~D
10_0402_5%~D
10K_0402_5%~D

PCIE_EMB#
PCIE_EMB

<7> CLK_CPU_ITP#
<7> CLK_CPU_ITP

2
RH2802
RH281

1
10_0402_5%~D
0_0402_5%~D

CLK_BCLK_ITP# AK14
CLK_BCLK_ITP AK13

EMBCLK_REQ#

SML0CLK
SML0DATA

SML1ALERT# / PCHHOT# / GPIO74

SML1DATA / GPIO75

V38
V37
K12

A12

DDR_HVREF_RST_PCH

C8

LAN_SMBCLK

G12

LAN_SMBDATA

C13

PCH_GPIO74

E14

SML1_SMBCLK

M16

SML1_SMBDATA

2
2.2K_0402_5%~D
2
2.2K_0402_5%~D

DDR_HVREF_RST_PCH <7>

+3.3V_ALW_PCH

LAN_SMBCLK <32>
DDR_HVREF_RST_PCH 2
RH300
PCH_GPIO74
2
RH301
MEM_SMBCLK
2
RH302
MEM_SMBDATA
2
RH303
PCH_SMB_ALERT#
2
RH304

LAN_SMBDATA <32>

SML1_SMBCLK <41>
SML1_SMBDATA <41>

PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8

CL_CLK1

M7

PCH_CL_CLK1

T11

PCH_CL_DATA1

P10

PCH_CL_RST1#

LAN_SMBCLK

PCH_CL_CLK1 <35>

1
1K_0402_1%~D
1
10K_0402_5%~D
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
1
10K_0402_5%~D

2
RH305
2
RH306

LAN_SMBDATA
CL_DATA1
CL_RST1#

PCH_CL_DATA1 <35>

1
2.2K_0402_5%~D
1
2.2K_0402_5%~D

PCH_CL_RST1# <35>
RH80
2

+3.3V_ALW_PCH

GFX_CLK_REQ#

10K_0402_5%~D
M10

GFX_CLK_REQ#

m
o
c
.
x
i
f
n
a
ub

PEG_A_CLKRQ# / GPIO47

PCIECLKRQ0# / GPIO73

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_PCIE1N
CLKOUT_PCIE1P

CLKOUT_DMI_N
CLKOUT_DMI_P

PCIECLKRQ1# / GPIO18

CLKOUT_DP_N
CLKOUT_DP_P

CLKOUT_PCIE2N
CLKOUT_PCIE2P

CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLK_BUF_DMI#
CLK_BUF_DMI

AM12
AM13
BF18
BE18

1
RH74 1
RH75

CLK_BUF_DMI#
CLK_BUF_DMI

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLKIN_SATA_N
CLKIN_SATA_P

AK7
AK5

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

REFCLK14IN

K45

CLK_PCH_14M

H45

CLK_PCI_LOOPBACK

V47
V49

XTAL25_IN
XTAL25_OUT

CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT

2
2 10K_0402_5%~D
10K_0402_5%~D

RH91

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLKOUT_PCIE4N
CLKOUT_PCIE4P

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>

G24
E24

CLKIN_DOT_96N
CLKIN_DOT_96P

PCIECLKRQ5# / GPIO44

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_BUF_BCLK
CLK_BUF_BCLK

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE5N
CLKOUT_PCIE5P

AV22
AU22

QH2
SSM3K7002FU_SC70-3~D

CLK_PCIE_VGA# <45>
CLK_PCIE_VGA <45>

BJ30
BG30

CLKIN_GND1_N
CLKIN_GND1_P

PCIECLKRQ4# / GPIO26

CLK_PCIE_VGA#
CLK_PCIE_VGA

CLK_BUF_BCLK

CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ2# / GPIO20

AB37
AB38

2
G

<40,49> 3.3V_RUN_GFX_ON

CLKOUT_PCIE0N
CLKOUT_PCIE0P

10K_0402_5%~D

1
RH76 1
RH77

2
2 10K_0402_5%~D
10K_0402_5%~D

CLK_BUF_CKSSCD#
1
CLK_BUF_CKSSCD
RH78 1
RH79

2
2 10K_0402_5%~D
10K_0402_5%~D

CLK_PCH_14M

1
RH183

10K_0402_5%~D

CLOCK TERMINATION for FCIM and need close to PCH


CLK_PCI_LOOPBACK <17>
2
RH309

1
0_0402_5%~D

RH99
1M_0402_5%~D

PEG_B_CLKRQ# / GPIO56
Y47

XCLK_RCOMP

1
RH100

K43

PCI_TPM_TCM

RH311

1 22_0402_5%~D

F47

SIO_14M

RH313

1 22_0402_5%~D

CLK_SIO_14M <40>

CLKOUTFLEX2 / GPIO66

H47

CLK_80H

RH314

1 22_0402_5%~D

PCLK_80H

CLKOUTFLEX3 / GPIO67

K49

JETWAY_14M @ RH315

1 22_0402_5%~D

XCLK_RCOMP
CLKOUT_PCIE6N
CLKOUT_PCIE6P

2
+1.05V_RUN
90.9_0402_1%~D

PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65

BD82PPSM-QNHN-A0_BGA989~D

PCIE REQ power rail:


suspend: 0 3 4 5 6 7
core: 1 2

1
RH298
1
RH299

+3.3V_LAN

h
z
.
w
w

LANCLK_REQ#

<32> LANCLK_REQ#

MMI --->

Y40
Y39

SML0ALERT# / GPIO60

SML1CLK / GPIO58
PERN5
PERP5
PETN5
PETP5

SML1_SMBCLK

YH2
25MHZ_10PF_Q22FA2380049900~D
3 OUT
IN 1

CLK_PCI_TPM_TCM <33>

<35>

4
2

GND

GND

2
2

CH19
12P_0402_50V8J~D

<34>
<34>
<34>
<34>

PERN4
PERP4
PETN4
PETP4

BG37
BH37
AY36
BB36

MEM_SMBDATA

SML1_SMBDATA

PERN3
PERP3
PETN3
PETP3

PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
PCIE_PTX_WPANRX_N5
PCIE_PTX_WPANRX_P5

C9

+3.3V_ALW_PCH

10/100/1G LAN --->

PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
PCIE_PTX_WPANRX_N5
PCIE_PTX_WPANRX_P5

BF36
BE36
AY34
BB34

MEM_SMBCLK

MMI --->
C

<35>
<35>
<35>
<35>

PCIE_PRX_EMBTX_N4
PCIE_PRX_EMBTX_P4
PCIE_PTX_EMBRX_N4
PCIE_PTX_EMBRX_P4

SMBDATA

PCH_SMB_ALERT#

H14

1/2 MINI CARD-3 PCIE


(Mini Card 3)--->

BG36
BJ36
AV34
AU34

PERN2
PERP2
PETN2
PETP2

E12

PCIE_PRX_EMBTX_N4
PCIE_PRX_EMBTX_P4
PCIE_PTX_EMBRX_N4
PCIE_PTX_EMBRX_P4

PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3

SMBCLK

CH18
12P_0402_50V8J~D

E3 Module Bay--->

<29>
<29>
<29>
<29>

BE34
BF34
BB32
AY32

SMBALERT# / GPIO11

Link

PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

PERN1
PERP1
PETN1
PETP1

SMBUS

EXPRESS Card--->

<36>
<36>
<36>
<36>

BG34
BJ34
AV32
AU32

Controller

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1

FLEX CLOCKS

<35>
<35>
<35>
<35>

PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1

CLOCKS

WLAN (Mini Card 2)--->

<35>
<35>
<35>
<35>

PCI-E*

WWAN (Mini Card 1)--->

JETWAY_CLK14M <33>

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

PCH (2/8)
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

15

of

66

2 PCH_CRT_BLU
150_0402_1%~D
2 PCH_CRT_GRN
150_0402_1%~D
2 PCH_CRT_RED
150_0402_1%~D
2 ENVDD_PCH
100K_0402_5%~D

2 0_0402_5%~D

RH131

+3.3V_RUN

RH132

5
B

PCH_PCIE_WAKE#
2
10K_0402_5%~D

1 ME_RESET# 2
8.2K_0402_5%~D

2
@ RH141

O
A

RH134
SYS_RESET#

1
RH142

<7,14> XDP_DBRESET#

ME_SUS_PWR_ACK
2
10K_0402_5%~D

1
0.1U_0402_25V6K~D

@
RH317

1
RH144

@ UC3
1

2.2K_0402_5%~D

SUS_STAT#/LPCPD#
2
10K_0402_5%~D

+3.3V_RUN

@
RH316

1
@ RH318

1
RH133

2.2K_0402_5%~D

@ CH99
1
2

RH357 1

+3.3V_ALW_PCH

MAX14885EETL has internal 3K pu for


PCH_CRT_DDC_CLK and PCH_CRT_DDC_DAT

74AHC1G09GW_TSSOP5~D

DSWODVREN - On Die DSW VR Enable

PCH_CRT_DDC_CLK

PCH_CRT_DDC_CLK

PCH_CRT_DDC_DAT

PCH_DPWROK 1
RH113

<25>

Disabled

2 PCH_RSMRST#_R
0_0402_5%~D

LOW: RH129 STUFFED,


RH127 UNSTUFFED

+3.3V_RUN
RESET_OUT#

2 SYS_PWROK
0_0402_5%~D

1
@ RH321

CLKRUN#
2
8.2K_0402_5%~D
ME_RESET#
2
8.2K_0402_5%~D
ME_SUS_PWR_ACK_R 1
RH323

2 SUSACK#_R
0_0402_5%~D

Intel request DDPB can not support eDP

UH4C

<6>
<6>
<6>
<6>

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BC24
BE20
BG18
BG20
BE24
BC20
BJ18
BJ20

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT

+1.05V_RUN

BJ24
1
RH111
1
RH112

DMI_COMP_R
2
49.9_0402_1%~D
RBIAS_CPY
2
750_0402_1%~D

BG25
BH21

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0
FDI_LSYNC1

SUSACK#

SUSACK#_R
2
0_0402_5%~D

1
@ RH114

SYS_RESET#

C12
K3

SUSACK#
SYS_RESET#

1
RH116

SYS_PWROK_R
2
0_0402_5%~D

P12

<41> RESET_OUT#

1
RH117

PCH_PWROK
2
0_0402_5%~D

L22

<41> PM_APWROK

1
RH118

PM_APWROK_R
2
0_0402_5%~D

L10

<7,40> SYS_PWROK

<7> PM_DRAM_PWRGD

1
RH320

2
0_0402_5%~D

PM_DRAM_PWRGD_R

B13

<14,42> PCH_RSMRST#_Q

1
RH120

PCH_RSMRST#_R
2
0_0402_5%~D

C21

<41> ME_SUS_PWR_ACK

1
RH121

ME_SUS_PWR_ACK_R
2
0_0402_5%~D

K16

1
RH122

SIO_PWRBTN#_R
2
0_0402_5%~D

E20

<7,14> SIO_PWRBTN#_R
<41> SIO_PWRBTN#

SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#

System Power Management

DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

AW16

FDI_INT

AV12

FDI_FSYNC0
FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

DSWODVREN

SUSWARN#/SUSPWRDNACK/GPIO30
PWRBTN#

SLP_S3#
SLP_A#

H20

ACPRESENT / GPIO31

SLP_SUS#

PCH_DPWROK
PCH_PCIE_WAKE#

N3

CLKRUN#

T56

PAD~D

T57

PAD~D

T58

PAD~D

D10

SIO_SLP_S5#
SIO_SLP_S4#

SIO_SLP_S3#

G10

SIO_SLP_A#

G16

SIO_SLP_SUS#

PCH_BATLOW#
2
8.2K_0402_5%~D

1
RH139

A10

BATLOW# / GPIO72
RI#

PMSYNCH
SLP_LAN# / GPIO29

AP14

H_PM_SYNC

K14

SIO_SLP_LAN#

<23> LCD_A0+_PCH
<23> LCD_A1+_PCH
<23> LCD_A2+_PCH

<23> LCD_BCLK-_PCH
<23> LCD_BCLK+_PCH
<23> LCD_B0-_PCH
<23> LCD_B1-_PCH
<23> LCD_B2-_PCH

<41>

<33,40,41>
<23> LCD_B0+_PCH
<23> LCD_B1+_PCH
<23> LCD_B2+_PCH

<25> PCH_CRT_BLU
<25> PCH_CRT_GRN
<25> PCH_CRT_RED

SIO_SLP_S5# <41>
PAD~D

SIO_SLP_S4# <40>

SIO_SLP_S3# <11,28,36,40,43,56>
SIO_SLP_A#

<25> PCH_CRT_HSYNC
<25> PCH_CRT_VSYNC

<40,43,57>

T40
K47

AF37
AF36

RH123
1
1
RH124

LCD_ACLK-_PCH
LCD_ACLK+_PCH

AK39
AK40

LCD_A0-_PCH
LCD_A1-_PCH
LCD_A2-_PCH

AN48
AM47
AK47
AJ48

LCD_A0+_PCH
LCD_A1+_PCH
LCD_A2+_PCH

AN47
AM49
AK49
AJ47

LCD_BCLK-_PCH
LCD_BCLK+_PCH

AF40
AF39

LCD_B0-_PCH
LCD_B1-_PCH
LCD_B2-_PCH

AH45
AH47
AF49
AF45

LCD_B0+_PCH
LCD_B1+_PCH
LCD_B2+_PCH

AH43
AH49
AF47
AF43

PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED

N48
P49
T49

PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT

T39
M40

20_0402_1%~D
2 HSYNC
2 VSYNC
20_0402_1%~D

M47
M49

L_BKLTEN
L_VDD_EN

SDVO_TVCLKINN
SDVO_TVCLKINP

L_BKLTCTL

SDVO_STALLN
SDVO_STALLP

L_DDC_CLK
L_DDC_DATA

SDVO_INTN
SDVO_INTP

CRT_IREF

<40>

PAD~D

H_PM_SYNC

SIO_SLP_LAN#

<7>

T43
T42

AM42
AM40
C

AP39
AP40

L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG

SDVO_CTRLCLK
SDVO_CTRLDATA

LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC

PAD~D

SIO_SLP_SUS#

AP43
AP45

DAC_IREF
CRT_IRTN

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

BD82PPSM-QNHN-A0_BGA989~D
RH126
1K_0402_0.5%~D

<32,40>

PCH_RI#

E10

<23> LCD_A0-_PCH
<23> LCD_A1-_PCH
<23> LCD_A2-_PCH

<6>
+RTC_CELL

SUSCLK

LDDC_CLK_PCH
LDDC_DATA_PCH

AE48
AE47

<6>

SUS_STAT#/LPCPD#

P45

2 LVD_IBG
2.37K_0402_1%~D

1
RH344

FDI_LSYNC1

CLKRUN#

J47
M45

BIA_PWM_PCH

Minimum speacing of 20mils for LVD_IBG

FDI_LSYNC0

PCH_PCIE_WAKE#

PANEL_BKEN_PCH
ENVDD_PCH

T45
P39

<6>

N14

F4

<23> LDDC_CLK_PCH
<23> LDDC_DATA_PCH

FDI_FSYNC1

G8

H4

<24> BIA_PWM_PCH

<23> LCD_ACLK-_PCH
<23> LCD_ACLK+_PCH

2 330K_0402_1%~D
PCH_DPWROK <40>

B9

<24> PANEL_BKEN_PCH
<24,40> ENVDD_PCH

<6>

2 330K_0402_1%~D

E22

UH4D

<6>

RH127 1

T63
+3.3V_ALW_PCH

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

@ RH129 1

T62
AC_PRESENT

<41> AC_PRESENT

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0

T59

SLP_S4#

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

FDI_INT

BC10

A18

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<6>
<6>
<6>
<6>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

FDI

<6>
<6>
<6>
<6>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

<6>
<6>
<6>
<6>

Digital Display Interface

@ RH138

LVDS

CRT

1
RH137

<40>

PCH_CRT_DDC_DAT

HIGH: RH127 STUFFED,


RH129 UNSTUFFED

PCH_RI#
2
10K_0402_5%~D

1
RH140

<25>

Enabled (DEFAULT)

SIO_SLP_LAN#
2
10K_0402_5%~D

1
@ RH319

BD82PPSM-QNHN-A0_BGA989~D
A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

PCH (3/8)
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

16

of

66

+3.3V_RUN

1
RH324

PCI_PIRQA#
2
8.2K_0402_5%~D

1
RH325

PCI_PIRQB#
2
8.2K_0402_5%~D

1
RH327

PCI_REQ1#
2
10K_0402_5%~D

1
RH330

LCD_CBL_DET#
2
10K_0402_5%~D

1
RH328

BT_DET#
2
10K_0402_5%~D

1
@ RH332
1
RH331

PCH_GPIO3
2
10K_0402_5%~D
CAM_MIC_CBL_DET#
2
10K_0402_5%~D

USB3RN1
USB3RN2

<39>
<37>
<37>

USB3RN4
USB3RP1
USB3RP2

<39>
<37>
<37>

USB3RP4
USB3TN1
USB3TN2

@ RH333
1K_0402_1%~D

<39>
<37>
<37>

USB3TN4
USB3TP1
USB3TP2

<39>

USB3TP4

A16 swap override Strap/Top-Block

B21
M20
AY16
BG46

TP21
TP22
TP23
TP24

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

PCI_GNT3#

<37>
<37>

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

K40
K38
H38
G38

PCI_REQ1#

C46
C44
E40

Swap Override jumper


<35> PCIE_MCARD2_DET#
<42> BT_DET#

Low = A16 swap


PCI_GNT#3

BT_DET#
BBS_BIT1

High = Default
B

D47
E42
F46

PCI_GNT3#

<45>
<33>
<34>
<7>
<32>
<29>

1
RH3431
RH3351
RH3361
RH3371
RH3381
RH340

PLTRST_GPU#
PLTRST_USH#
PLTRST_MMI#
PLTRST_XDP#
PLTRST_LAN#
PLTRST_EMB#

2
2
2
2
2
2

<40> CLK_PCI_5048
<41> CLK_PCI_MEC
<39> CLK_PCI_DOCK
<15> CLK_PCI_LOOPBACK

LCD_CBL_DET#
<24> LCD_CBL_DET#
PCH_GPIO3
CAM_MIC_CBL_DET#
<24> CAM_MIC_CBL_DET#
FFS_PCH_INT
1
2
<28> HDD_FALL_INT
RH334
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
PAD~D T104 @
0_0402_5%~D
PCH_PLTRST#
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
PCI_5048
2
1
PCI_MEC
RH160 2
1 22_0402_5%~D
PCI_DOCK
RH102 2
1 22_0402_5%~D
RH103
22_0402_5%~D
PCI_LOOPBACKOUT
2
1
RH105
22_0402_5%~D

USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3TP1
USB3Tp2
USB3Tp3
USB3Tp4

PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

RSVD5
RSVD6

AT10
BC8

RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

RSVD23
RSVD24

AV5
AV10

RSVD25

AT8

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

K10

PME#

H49
H43
J48
K42
H40

AY7
AV7
AU3
BG4

RSVD28
RSVD29

G42
G40
C42
D44

C6

RSVD1
RSVD2
RSVD3
RSVD4

RSVD26
RSVD27

USB

1
RH329

PCI_PIRQD#
2
8.2K_0402_5%~D

USB30

PCI_PIRQC#
2
8.2K_0402_5%~D

PCI

1
RH326

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

RSVD

UH4E
D

USBRBIAS#
USBRBIAS

PLTRST#

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

AY5
BA2

AT12
BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
USBP12USBP12+
USBP13USBP13+

C33

USBRBIAS

----->Right Side Top


----->Right Side Bottom
----->Right side E-SATA
----->MLK DOCK
----->WLAN/WIMAX
----->WWAN/UWB
----->Flash
----->USH
----->DOCK
----->Left side
----->Express Card
----->Blue Tooth
----->Camera
----->LCD Touch

1
2
RH151
22.6_0402_1%~D

USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#

1
RH3391
RH341

2
2 0_0402_5%~D
0_0402_5%~D

USB_OC5#
USB_OC6#
SIO_EXT_SMI#
USB_OC2#

1
RH356

2
0_0402_5%~D

SIO_EXT_SMI#

RPH1
4
3
2
1

5
6
7
8

10K_1206_8P4R_5%~D
RPH2
4
5
3
6
2
7
1
8
10K_1206_8P4R_5%~D

USB_OC0#
<37>
USB_OC1#
<37>
USB_OC2#
<14>
USB_OC3#
<14>
USB_OC4#
<31>
USB_OC5#
<14>
USB_OC6#
<14>
SIO_EXT_SMI# <14,41>
USB_OC0#_R <14>
USB_OC1#_R <14>
USB_OC4#_R <14>

BD82PPSM-QNHN-A0_BGA989~D

+3.3V_RUN

+3.3V_ALW_PCH
INTEL feedback 0307
USB_OC0#_R
USB_OC1#_R
USB_OC3#
USB_OC4#_R

Route single-end 50-ohms and max 500-mils length.


Minimum spacing to other signals: 15 mils

B33
A14
K20
B17
C16
L16
A16
D14
C14

USBP0- <37>
USBP0+ <37>
USBP1- <37>
USBP1+ <37>
USBP2- <38>
USBP2+ <38>
USBP3- <39>
USBP3+ <39>
USBP4- <35>
USBP4+ <35>
USBP5- <35>
USBP5+ <35>
USBP6- <35>
USBP6+ <35>
USBP7- <33>
USBP7+ <33>
USBP8- <39>
USBP8+ <39>
USBP9- <31>
USBP9+ <31>
USBP10- <36>
USBP10+ <36>
USBP11- <42>
USBP11+ <42>
USBP12- <24>
USBP12+ <24>
USBP13- <24>
USBP13+ <24>

CH102
0.1U_0402_25V6K~D
1
2

BBS_BIT1
O

PCH_PLTRST#_EC

Boot BIOS Location


BBS_BIT1

LPC

Reserved (NAND)

PCI

TC7SH08FU_SSOP5~D

@ RH342
1K_0402_1%~D

www.vinafix.vn
*

SATA_SLPD
(BBS_BIT0)

PCH_PLTRST#_EC <33,35,36,40,41>

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

PCH_PLTRST#

<7,14> PCH_PLTRST#

UH3

Boot BIOS Strap


A

PCH (4/8)
Size

SPI
3

Document Number

Rev
0.1

LA-7782
Date:
2

Friday, June 10, 2011

Sheet
1

17

of

66

+3.3V_ALW_PCH
2

+3.3V_RUN
CONTACTLESS_DET# 2
RH256

SIO_EXT_SCI# 1
RH259
USH_DET#

<31> IO_LOOP#

2
T7
0_0402_5%~D
A42

IO_LOOP#

H36

PCH_GPIO7

E38
C10

<40> SIO_EXT_WAKE#

Note: PCH has internal pull up 20k ohm on


E3_PAID_TS_DET# (GPIO27)
SLP_ME_CSW_DEV#

PLL ON DIE VR ENABLE

<32> PM_LANPHY_ENABLE
<14> PCH_GPIO15
<14> PCH_GPIO16

PM_LANPHY_ENABLE

C4

PCH_GPIO15

G2

PCH_GPIO16

U2

PCH_GPIO17

D40

TACH4 / GPIO68

TACH1 / GPIO1

TACH5 / GPIO69

B41

TACH2 / GPIO6

TACH6 / GPIO70

C41

TACH3 / GPIO7

TACH7 / GPIO71

GPIO15

A20GATE
PECI

SATA4GP / GPIO16

<14,40> SLP_ME_CSW_DEV#
2
RH177
1
RH354

SIO_EXT_WAKE#
1
10K_0402_5%~D
PCH_GPIO15
2
1K_0402_1%~D

<45> DGPU_HOLD_RST#

<14> PCH_GPIO36
<14> PCH_GPIO37

<28>

FFS_INT2

<14,40> TEMP_ALERT#
<42> KB_DET#

SCLOCK / GPIO22
GPIO24

E16

SLP_ME_CSW_DEV#

P8

DGPU_HOLD_RST#

K1

USB_MCARD1_DET#

<14,35> USB_MCARD1_DET#

T5
E8

GPIO27
GPIO28

V8

PCH_GPIO37

M5

TPM_ID0

N2

TPM_ID1

M3

FFS_INT2

V13

TEMP_ALERT#

V3

KB_DET#

D6

THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1
TS_VSS2

GPIO35
TS_VSS3
SATA2GP / GPIO36

TS_VSS4
SLOAD / GPIO38

A44

INTEL feedback 0302


2
1 PCH_GPIO36
RH174
10K_0402_5%~D
2
1 PCH_GPIO37
RH172
10K_0402_5%~D

VSS_NCTF_3

A45

VSS_NCTF_4

A46

VSS_NCTF_5

A5

2
@ RH273

1 PCH_GPIO17
1K_0402_1%~D

VSS_NCTF_6

A6

VSS_NCTF_7
1 PCH_GPIO16
10K_0402_5%~D

B3

2
@ RH265

VSS_NCTF_8

Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45from the pad.

NC_1

SDATAOUT1 / GPIO48

VSS_NCTF_15

SATA5GP / GPIO49 / TEMP_ALERT#

VSS_NCTF_16

GPIO57

VSS_NCTF_17

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_4
VSS_NCTF_5

USB_MCARD2_DET# <35>

P4

SIO_A20GATE

P5

SIO_RCIN#

AY11

H_CPUPWRGD

AY10

SIO_RCIN#

<41>

+3.3V_RUN
+1.05V_RUN_VTT

H_CPUPWRGD <7>

PCH_THRMTRIP#_R

T14

INIT3_3V#

AY1

DF_TVS

2
RH262
PAD~D
@

T106

SIO_A20GATE

1
56_0402_5%~D

SIO_RCIN#

1
CH97
0.1U_0402_25V6K~D

SIO_EXT_SCI#

AH8

USH_DET#

AK11

2
RH158
2
RH203

1
10K_0402_5%~D
1
10K_0402_5%~D

1
RH263
1
RH164

2
10K_0402_5%~D
2
100K_0402_5%~D

AH10
AK10
P37

NC_1

VSS_NCTF_22
VSS_NCTF_23

BG2

VSS_NCTF_15

BG48

VSS_NCTF_16

BH3

VSS_NCTF_17

BH47

VSS_NCTF_18

BJ4

VSS_NCTF_19

BJ44

VSS_NCTF_20

BJ45

VSS_NCTF_21

BJ46

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ6

VSS_NCTF_24

C2

VSS_NCTF_25

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

B47

VSS_NCTF_8

VSS_NCTF_26

C48

VSS_NCTF_26

VSS_NCTF_9

BD1

VSS_NCTF_9

VSS_NCTF_27

D1

VSS_NCTF_27

VSS_NCTF_10

BD49

VSS_NCTF_10

VSS_NCTF_28

D49

VSS_NCTF_28

VSS_NCTF_11

BE1

VSS_NCTF_11

VSS_NCTF_29

E1

VSS_NCTF_29

VSS_NCTF_12

BE49

VSS_NCTF_12

VSS_NCTF_30

E49

VSS_NCTF_30

VSS_NCTF_13

BF1

VSS_NCTF_13

VSS_NCTF_31

F1

VSS_NCTF_31

VSS_NCTF_14

BF49

VSS_NCTF_14

VSS_NCTF_32

F49

VSS_NCTF_32

KB_DET#
1
10K_0402_5%~D

SIO_A20GATE <41>

AU16

VSS_NCTF_6

+3.3V_ALW_PCH

PAD~D T108 @

Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45from the pad.

PLACE RH150 CLOSE TO THE BRANCHING POINT


( TO CPU and NVRAM CONNECTOR)

+VCCDFTERM

RH149 need to close to CPU


RH149
2.2K_0402_5%~D

BD82PPSM-QNHN-A0_BGA989~D
2

2
RH170

PCIE_MCARD3_DET# <35>

SDATAOUT0 / GPIO39

NCTF

A4

VSS_NCTF_2

A40

SATA3GP / GPIO37

VSS_NCTF_18
VSS_NCTF_1

DGPU_PWROK <40,64>
PCIE_MCARD3_DET#

STP_PCI# / GPIO34

K4

PCH_GPIO36

PROCPWRGD

CPU/MISC

E3_PAID_TS_DET#

<24> E3_PAID_TS_DET#

+3.3V_ALW_PCH

TACH0 / GPIO17

GPIO

PCH_GPIO22

CONTACTLESS_DET# <33>

LAN_PHY_PWR_CTRL / GPIO12

RCIN#

<35> PCIE_MCARD1_DET#

CONTACTLESS_DET#

GPIO8

DBC_ENABLE for E4 12"


ENABLED - HIGH DEFAULT
DISABLED - LOW

C40

BMBUSY# / GPIO0

<33> USH_DET#

UH4F

<14> SIO_EXT_SCI#_R
<41> SIO_EXT_SCI#

RH353
1K_0402_1%~D
@

1
10K_0402_5%~D
D

SLP_ME_CSW_DEV#

RH53
4.7K_0402_5%~D

<7> H_SNB_IVB#

1
RH150

2
0_0402_5%~D

DF_TVS_R 1
RH358

DF_TVS
2
1K_0402_1%~D

PCH_GPIO36
1
10K_0402_5%~D
PCH_GPIO37
1
1K_0402_1%~D

+3.3V_RUN

+3.3V_RUN

2
@ RH171
2
@ RH173

+3.3V_RUN

DMI & FDI Termination Voltage

PCH_GPIO17
2
8.2K_0402_5%~D
IO_LOOP#
2
10K_0402_5%~D

1
RH272

PCH_GPIO16
2
10K_0402_5%~D

TPM_ID1

No TPM, No China TPM


4@ RH271
2.2K_0402_5%~D

DF_TVS

DELL CONFIDENTIAL/PROPRIETARY

TBD
TPM

Set to Vcc when HIGH

Compal Electronics, Inc.


Title

1
RH163

2@ RH270
10K_0402_5%~D

TPM_ID0
China TPM

TPM_ID1
2

TPM_ID0

Set to Vss when LOW

3@ RH268
20K_0402_5%~D
2

1
RH269

1@ RH267
10K_0402_5%~D
1

TEMP_ALERT#
1
10K_0402_5%~D
PCH_GPIO22
1
10K_0402_5%~D
PCH_GPIO7
1
10K_0402_5%~D

2
RH266
2
RH181
2
RH178

PCH (5/8)

www.vinafix.vn
3

Size

Document Number

Rev
0.1

LA-7782
Date:
2

Friday, June 10, 2011

Sheet
1

18

of

66

+3.3V_RUN

AN21
AN26

AP21

AP23

AP24
AP26
AT24

VCCIO[16]
VCCIO[17]

VCCIO[24]

CRT

VCCDMI[1]

VCCIO[26]

CH51
0.1U_0402_10V7K~D

BG6

+1.05V_RUN

AP17

+1.05V_RUN_VTT

AU20

AP37

V33

VCC3_3[3]

VCCDFTERM[2]

VCCVRM[2]
VccAFDIPLL

0.001

Vcc3_3

3.3

0.228

VccADAC3

3.3

0.063

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

1.7

VccDMI

1.1

0.047

VccIO

1.05

3.711

VccASW

1.05

0.903

VccSPI

3.3

0.01

VccDSW3_3

3.3

0.001

VCCDFTERM

1.8

0.002

VccRTC

3.3

2 (mA)

VccSus3_3

3.3

0.095

VccSusHDA

3.3

0.01

VccVRM

1.5

0.167

VccClkDMI

1.05

0.07

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.04

CH43
0.1U_0402_10V7K~D

V34

AT16

AT20

+1.05V_RUN_VTT

AB36

+1.05V_RUN_VCCCLKDMI
1
CH50
1U_0402_6.3V6K~D

AG16

2 CH49
1U_0402_6.3V6K~D
2
1
@ RH205
0_0603_5%~D
1

+VCCDFTERM

AG17

+1.05V_RUN

VCCDFTERM[3]
VCCDFTERM[4]

AJ16

@ RH276
0_0805_5%~D
2
1

AJ17

CH52
0.1U_0402_10V7K~D

+3.3V_RUN

+1.8V_RUN

PAD-OPEN1x1m

+VCCSPI

VCCSPI

V1

2
RH202
2
@ RH204

BD82PPSM-QNHN-A0_BGA989~D
2

CH54
1U_0402_6.3V6K~D

INTEL feedback 0302

@PJP66
@
PJP66

VCCIO[27]
VCCDMI[2]

0.001

0.1uH inductor, 200mA


CPN: SHI0110BJ0L

+3.3V_RUN

1
VCCCLKDMI

VCCDFTERM[1]

FDI

AP16

2
VCCIO[25]

+1.05V_+1.5V_1.8V_RUN

+VCCAPLL_FDI

AP36

VCCVRM[3]

VCCIO[21]

AN34
BH29

1
AM38

LH8
100NH_HK1608R10J-T_5%_0603~D
2
1

VCCIO[20]

VCCIO[23]

V5REF_Sus

+1.05V_+1.5V_1.8V_RUN

VCCIO[19]

AN33

+3.3V_RUN

+1.8V_RUN_LVDS

AM37

VCCIO[18]

VCCIO[22]

V5REF

1
VCC3_3[7]

0.001

+3.3V_RUN

+1.8V_RUN

CH106
10U_0603_6.3V6M~D

CH48
1U_0402_6.3V6K~D

CH47
1U_0402_6.3V6K~D

CH46
1U_0402_6.3V6K~D

CH45
1U_0402_6.3V6K~D

CH44
10U_0603_6.3V6M~D

HVCMOS

AN17

VCC3_3[6]
VCCIO[15]

S0 Iccmax
Current (A)

Voltage
1.05

V_PROC_IO

AK37

VCCAPLLEXP

DMI

AN16

AN27

VCCTX_LVDS[2]

VCCTX_LVDS[4]

DFT / SPI

BJ22

+1.05V_RUN

VCCTX_LVDS[1]

Voltage Rail

AK36

VCCIO[28]

VCCIO

VSSALVDS

CH105
22U_0805_6.3V6M~D

CH40
10U_0603_6.3V6M~D

1UH_LB2012T1R0M_20%~D

VCCALVDS

CH104
0.01U_0402_16V7K~D

+VCCAPLLEXP

U47

CH36
10U_0603_6.3V6M~D

AN19

VSSADAC

VCCTX_LVDS[3]

+1.05V_RUN
1
@ RH247

VCCADAC

U48

CH103
0.01U_0402_16V7K~D

+1.05V_RUN

PCH Power Rail Table

2
1
BLM18PG181SN1_0603~D

CH35
0.1U_0402_10V7K~D

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

+VCCADAC
CH34
0.01U_0402_16V7K~D

CH31
1U_0402_6.3V6K~D

CH33
1U_0402_6.3V6K~D

CH32
1U_0402_6.3V6K~D

CH30
10U_0603_6.3V6M~D

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

LVDS

UH4G

VCC CORE

+1.05V_RUN

LH1

POWER

1
0_0603_5%~D
1
0_0603_5%~D

+3.3V_M
+3.3V_RUN
B

INTEL feedback 0307

+1.05V_RUN

1
@ RH195

2 +VCCAPLL_FDI
0.022_0805_1%
+1.5V_RUN

+1.05V_+1.5V_1.8V_RUN

2
RH197

1
0_0603_5%~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

PCH (6/8)
Size

Document Number

Date:

Tuesday, June 07, 2011

Rev
0.1

LA-7782
Sheet
1

19

of

66

+1.05V_RUN
+5V_ALW

+VCCAPLL_CPY_PCH

BH23
AL29

+VCCSUS1

AL24

VCCSUS3_3[7]
VCCAPLLDMI2
VCCSUS3_3[8]
VCCIO[14]
VCCSUS3_3[9]

DCPSUS[3]

VCCSUS3_3[10]

VCCSUS3_3[6]

AA21

+1.05V_M

AA24

CH65
22U_0805_6.3V6M~D

CH64
22U_0805_6.3V6M~D

AA26
AA27
AA29
AA31
AC26

CH69
1U_0402_6.3V6K~D

+3.3V_RUN

CH68
1U_0402_6.3V6K~D

CH67
1U_0402_6.3V6K~D

AC27
AC29
AC31
AD29
AD31
W21
W23

+3.3V_RUN_VCC_CLKF33
1
1
@

Note: If EMI concern, pop


with SHI00008S0L, 10UH +-20%

W24

CH74
1U_0402_6.3V6K~D

2
0.022_0805_1%

CH73
10U_0603_6.3V6M~D

1
RH215

W26
W29
W31
W33

VCCIO[34]

N16

VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]

V5REF_SUS
DCPSUS[4]
VCCSUS3_3[1]

V5REF
VCCSUS3_3[2]

VCCASW[16]

+1.05V_RUN_VCCA_B_DPL

AF17
AF33
AF34
AG34

2 CH81
1U_0402_6.3V6K~D

AG33

1
+VCCSST

+
2

CH93
1U_0402_6.3V6K~D

CH95
220U_B2_2.5VM_R35M~D

CH92
1U_0402_6.3V6K~D

M26
AN23

+VCCA_USBSUS

AN24

P34

+PCH_V5REF_RUN

+3.3V_ALW_PCH

VCCSUS3_3[5]

VCCVRM[4]

VCCIO[13]
VCCIO[6]

VCCADPLLA
VCCADPLLB

VCCAPLLSATA
VCCVRM[1]

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

1
2

CH63
0.1U_0402_10V7K~D

+5V_RUN +3.3V_RUN

RH213
10_0402_1%~D

+3.3V_ALW_PCH

CH70
1U_0603_10V7K~D

DH3
RB751S40T1_SOD523-2~D

+3.3V_RUN

+PCH_V5REF_RUN

1
CH71
1U_0603_10V7K~D

1
AA16
2

W16

CH72
0.1U_0402_10V7K~D

+3.3V_RUN

T34
1

+VCCA_USBSUS
CH75
0.1U_0402_10V7K~D

AJ2
1
AF13
2

DCPRTC

P22

VCCASW[20]

+PCH_V5REF_SUS

CRB 0.7 RH208,RH213 trace width 20mil.

N20

P20

VCC3_3[2]

RH278
20K_0402_5%~D

S
2
G

DH2
RB751S40T1_SOD523-2~D

+1.05V_RUN

VCCASW[19]

2
CH76
0.1U_0402_10V7K~D

+1.05V_RUN
1

AH13
2

AH14

CH77
1U_0402_6.3V6K~D

LH5
@
10UH_LBR2012T100M_20%~D
1
2

AF14
+VCCSATAPLL
+1.05V_+1.5V_1.8V_RUN

AK1

@CH62
@CH62
1U_0402_6.3V6K~D

AF11

+1.05V_RUN

@ CH80
10U_0603_6.3V6M~D

2
VCCIO[2]

VCCSSC

AC16

VCCIO[3]

AC17

VCCIO[4]

AD17

+1.05V_RUN
1
CH82
1U_0402_6.3V6K~D
+1.05V_M

DCPSST

V_PROC_IO

A22
1

VCCRTC

VCCASW[22]

MISC

DCPSUS[1]
DCPSUS[2]

+RTC_CELL

+1.05V_RUN_VCCA_B_DPL
1

CH83 @
1U_0402_6.3V6K~D
BJ8

+1.05V_RUN_VCCA_A_DPL

CH94
220U_B2_2.5VM_R35M~D

1
2
LH7
10UH_LBR2012T100M_20%~D

+3.3V_ALW_PCH

1
+PCH_V5REF_SUS

VCCASW[18]

VCCASW[23]
VCCASW[21]

VCCSUSHDA

HDA

+1.05V_RUN

CH87
0.1U_0402_10V7K~D

LH6
10UH_LBR2012T100M_20%~D
1
2

CH86
0.1U_0402_10V7K~D

CH85
4.7U_0603_6.3V6K~D
2
2

T17
V19

1
2
2

+5V_ALW_PCH

RH208
10_0402_1%~D

+3.3V_RUN

CPU

CH84
0.1U_0402_10V7K~D

+3.3V_ALW_PCH

+1.05V_M_VCCSUS

+1.05V_RUN_VTT

V16

CH89
0.1U_0402_10V7K~D

2 +1.05V_M_VCCSUS
0.022_0805_1%

CH96
1U_0402_6.3V6K~D

CH88
0.1U_0402_10V7K~D

+1.05V_M
1
@ RH248

BF47

T26

N22

VCC3_3[4]

RTC

CH79
1U_0402_6.3V6K~D

BD47

VCCASW[17]

SATA

+1.05V_RUN_VCCA_A_DPL

P24

VCCSUS3_3[4]

VCC3_3[8]

+1.05V_+1.5V_1.8V_RUN
Y49

V24

VCCSUS3_3[3]

VCC3_3[1]

+1.05V_RUN

V23

+3.3V_ALW_PCH
1

VCCIO[12]

CH78
0.1U_0402_10V7K~D

T24

VCCASW[2]

VCCIO[5]
+VCCRTCEXT

Note: Place VCCDIFFCLKN with a trace


specially for XCLK_RCOMP (RH100.2)

VCCASW[1]

PCI/GPIO/LPC

AA19

Clock and Miscellaneous

CH61
1U_0402_6.3V6K~D

T23

+1.05V_RUN
@

T29

CH98
0.1U_0402_10V7K~D

VCCIO[33]
VCC3_3[5]

VCCIO[32]

T27

<43> ALW_ENABLE

DCPSUSBYP

CH56
1U_0402_6.3V6K~D

CH58
10U_0603_6.3V6M~D

+3.3V_RUN_VCC_CLKF33 T38

1
CH57
0.1U_0402_10V7K~D

P28

V12

P26

VCCIO[31]

QH4
SSM3K7002FU_SC70-3~D

+PCH_VCCDSW

VCCIO[30]
VCCDSW3_3

+1.05V_RUN

T16

N26

CH66
0.1U_0402_10V7K~D

+VCCDSW3_3

VCCIO[29]

CH60
0.1U_0402_10V7K~D

CH55
0.1U_0402_10V7K~D

VCCACLK

CH59

@ LH3
10UH_LBR2012T100M_20%~D
1
2

POWER
1

AD49

0.1U_0402_10V7K~D

2
0_0402_5%~D
2
0_0402_5%~D

+1.05V_RUN

+5V_ALW_PCH

UH4J
1
RH201
1
@ RH253

USB

+3.3V_ALW2

+VCCACLK
2
0.022_0805_1%

1
@ RH200

+3.3V_ALW_PCH

V21
T19

P32

+3.3V_ALW_PCH
1

BD82PPSM-QNHN-A0_BGA989~D
CH90
1U_0402_6.3V6K~D

T21

CH91
0.1U_0402_10V7K~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

PCH (7/8)

www.vinafix.vn
3

Size

Document Number

Rev
0.1

LA-7782
Date:
2

Friday, June 10, 2011

Sheet
1

20

of

66

UH4I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

UH4H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

BD82PPSM-QNHN-A0_BGA989~D

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

BD82PPSM-QNHN-A0_BGA989~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

PCH (8/8)
Size

Rev
0.1

LA-7782
Date:

Document Number
Monday, May 23, 2011

Sheet
1

21

of

66

DSC only
VGA_THERMDN

2
B
Q12
MMBT3904WT1G_SC70-3~D

@
C266
100P_0402_50V8J~D

REM_DIODE1_N_4022

FAN1_DET#

1
2
3
4

FAN1_TACH_FB
C219
22U_0805_6.3V6M~D

D2
RB751S40T1_SOD523-2~D

REM_DIODE1_P_4022

JFAN1

+FAN1_VOUT

Place under CPU


Place C266 close to the Q12 as possible

1
2
3 G1
4 G2

C738
0.1U_0402_25V6K~D

(1) DP3/DN3 for SODIMM on Q14, place Q14 close to SODIMM and C272 close to Q14
(2) DP5/DN5 for Skin on Q13, place Q13 close to Vcore VR choke.

+3.3V_M

+3.3V_RUN_EMC_VDDL
2
0_0603_5%~D

1
R1639

2
3
6
13

2 VDD_PWRGD
10K_0402_5%~D

1
R389

3
1

1
3

Q14
MMBT3904WT1G_SC70-3~D

VDDH
VDDH
VDDL
VDD_PWRGD

THERMTRIP2#
THERMTRIP3#

17

THERMATRIP2#

18

THERMATRIP3#

1
C270

2
2200P_0402_50V7K~D

REM_DIODE1_N_4022
REM_DIODE1_P_4022

23
24

1
C271

2
2200P_0402_50V7K~D

REM_DIODE2_N_4022
REM_DIODE2_P_4022

26
27

DN2/DP4
DP2/DN4

POWER_SW#

20

POWER_SW#

30
29

DP3/DN5
DN3/DP5

ACAVAIL_CLR
ATF_INT#/BC_IRQ#

21
9

BC_INT#_EMC4022

31
25

VCP
VIN

28

VSET

FAN1_TACH_FB

10

TACH/GPIO1

EMC4022_GPIO2

11

FAN1_DET#

15

BC_INT#_EMC4022

2
R385

1
10K_0402_5%~D

FAN1_TACH_FB

2
R426

1
10K_0402_5%~D

FAN1_DET#

2
R402

1
10K_0402_5%~D

EMC4022_GPIO2

2
R404

1
10K_0402_5%~D

VGA_THERMDP
VGA_THERMDN

2
Q13
MMBT3904WT1G_SC70-3~D
REM_DIODE2_N_4022
<62> MAX8731_IINP

VCP2

4.7K_0402_5%~D

R387
VSET_4022

+3.3V_M

DN1/THERM
DP1/VREF_T

SYS_SHDN#

FAN_OUT
FAN_OUT

SMCLK/BC_CLK
SMDATA/BC_DATA

19

THERM_STP#

5
4

1
@R390
@
R390

2
47K_0402_1%~D

ACAV_IN
<41,62,63>
BC_INT#_EMC4022 <41>

+FAN1_VOUT

8
7

BC_CLK_EMC4022 <41>
BC_DAT_EMC4022 <41>

GPIO2
GPIO3/PWM/THERMTRIP_SIO

+3.3V_M
1

+3.3V_M

2
2
R393

+VCC_4022

14
22
33

EMC4022-1-EZK-TR_QFN32_5X5~D

R403
10K_0402_5%~D

SMSC request

2
B

1
R396
8.2K_0402_5%~D
2

THERMATRIP3#
+RTC_CELL

1
C281

U10
TC7SH08FU_SSOP5~D
POWER_SW#
4 O

<45> THERMTRIP_VGA#

R406
953_0402_1%~D

THERMB3 2
B
Q115 E
PMST3904_SOT323-3~D

VSET_4022
C279
0.1U_0402_25V6K~D

C282
0.1U_0402_25V6K~D

1
C

2
0.1U_0402_25V6K~D

DOCK_PWR_SW# <41>

POWER_SW_IN# <41>

1
2

R399
2.2K_0402_5%~D

R400
10K_0402_5%~D

+3.3V_RUN_GFX

RTC_PWR3V

+VCC_4022
+ADDR_XEN
1
4.7K_0402_5%~D

16

+RTC_CELL

TEST1
TEST2
VSS

1
32

2
1
3

VDD
ADDR_MODE/XEN

C274
1U_0402_6.3V6K~D

R388
22_0402_5%~D

3V_PWROK#

1U_0402_6.3V6K~D
C1179

<7> H_THERMTRIP#

12

0.1U_0402_25V6K~D
C273

C278
0.1U_0402_25V6K~D

2 3V_PWROK#
1K_0402_1%~D

1
R391

<41> PCH_PWRGD#

THERMATRIP2#

R398
C
2.2K_0402_5%~D
1
2
2
B
Q15 E
PMST3904_SOT323-3~D

<54>

+RTC_CELL

R395
8.2K_0402_5%~D
+1.05V_RUN_VTT

U9

+3.3V_M

2
B
2

C277

@C272
@
C272
100P_0402_50V8J~D

100P_0402_50V8J~D

VGA_THERMDP <46>

MOLEX_53398-0471~D
CONN@

REM_DIODE2_P_4022
1

C1104
470P_0402_50V7K~D

+3.3V_RUN
C305
10U_0603_6.3V6M~D

C275
0.1U_0402_25V6K~D

C276
10U_0805_10V6K~D

VGA_THERMDP

5
6

+5V_RUN

VGA_THERMDN <46>

Rest=953, Tp=88degree

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

FAN & Thermal Sensor


Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

22

of

66

Channel A

NO0+
NO0NO1+
NO1NO2+
NO2NO3+
NO3AUX2B
AUX2A
AUX2

COM0+
COM0COM1+
COM1COM2+
COM2COM3+
COM3AUX0A
AUX0B
AUX0

SEL

35

36
1
2
3
7
8
9
10
4
12
34

U85

SW_LVDS_ACLK+ <24>
SW_LVDS_ACLK- <24>
SW_LVDS_A2+ <24>
SW_LVDS_A2- <24>
SW_LVDS_A1+ <24>
SW_LVDS_A1- <24>
SW_LVDS_A0+ <24>
SW_LVDS_A0- <24>
LDDC_DATA_SW <24>
LDDC_CLK_SW <24>

DGPU_SELECT#

27

DGPU_SELECT# <24,25,40>

SEL
GND
TPAD

11
37

MAX14979EETX+T_TQFN36_6X6~D

Chanel

<46> LCD_BCLK+_GPU
<46> LCD_BCLK-_GPU
<46> LCD_B2+_GPU
<46> LCD_B2-_GPU
<46> LCD_B1+_GPU
<46> LCD_B1-_GPU
<46> LCD_B0+_GPU
<46> LCD_B0-_GPU

31
30
26
25
22
21
18
17
5
13
33

NC0+
NC0NC1+
NC1NC2+
NC2NC3+
NC3AUX1B
AUX1A
AUX1

<16> LCD_BCLK+_PCH
<16> LCD_BCLK-_PCH
<16> LCD_B2+_PCH
<16> LCD_B2-_PCH
<16> LCD_B1+_PCH
<16> LCD_B1-_PCH
<16> LCD_B0+_PCH
<16> LCD_B0-_PCH

29
28
24
23
20
19
16
15
6
14
32

NO0+
NO0NO1+
NO1NO2+
NO2NO3+
NO3AUX2B
AUX2A
AUX2

2
V+

COM0+
COM0COM1+
COM1COM2+
COM2COM3+
COM3AUX0A
AUX0B
AUX0

SEL

35

36
1
2
3
7
8
9
10
4
12
34

27

COM=NC

GPU

COM=NO

PCH

SW_LVDS_BCLK+ <24>
SW_LVDS_BCLK- <24>
SW_LVDS_B2+ <24>
SW_LVDS_B2- <24>
SW_LVDS_B1+ <24>
SW_LVDS_B1- <24>
SW_LVDS_B0+ <24>
SW_LVDS_B0- <24>

DGPU_SELECT#

Source

C1149
0.1U_0402_25V6K~D

29
28
24
23
20
19
16
15
6
14
32

2
V+

+3.3V_RUN

@ C1150
0.1U_0402_25V6K~D

LDDC_CLK_PCH
LDDC_DATA_PCH

NC0+
NC0NC1+
NC1NC2+
NC2NC3+
NC3AUX1B
AUX1A
AUX1

C1145
0.1U_0402_25V6K~D

<16> LCD_ACLK+_PCH
<16> LCD_ACLK-_PCH
<16> LCD_A2+_PCH
<16> LCD_A2-_PCH
<16> LCD_A1+_PCH
<16> LCD_A1-_PCH
<16> LCD_A0+_PCH
<16> LCD_A0-_PCH
<16> LDDC_CLK_PCH
<16> LDDC_DATA_PCH

LDDC_CLK_GPU
LDDC_DATA_GPU

31
30
26
25
22
21
18
17
5
13
33

@ C1146
0.1U_0402_25V6K~D

<46> LCD_ACLK+_GPU
<46> LCD_ACLK-_GPU
<46> LCD_A2+_GPU
<46> LCD_A2-_GPU
<46> LCD_A1+_GPU
<46> LCD_A1-_GPU
<46> LCD_A0+_GPU
<46> LCD_A0-_GPU
<45> LDDC_CLK_GPU
<45> LDDC_DATA_GPU

Channel B

+3.3V_RUN

U84

SEL
GND
TPAD

11
37

MAX14979EETX+T_TQFN36_6X6~D

Chanel

Source

COM=NC

GPU

COM=NO

PCH

+3.3V_RUN_GFX
LDDC_CLK_GPU
2
2.2K_0402_5%~D
LDDC_DATA_GPU
2
2.2K_0402_5%~D

1
R1122
1
R1121
+3.3V_RUN
B

LDDC_CLK_PCH
2
2.2K_0402_5%~D
LDDC_DATA_PCH
2
2.2K_0402_5%~D

1
R1124
1
R1123

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

LVDS SW
Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

23

of

66

LCD Power

Q18
SI3456DDV-T1-GE3_TSOP6~D
+3.3V_ALW
6
4
5
2
R412
1
100K_0402_5%~D
1
D

+PWR_SRC_S +LCDVDD

BIA_PWM_GPU <45>

DISP_ON

3
2
4

D69
RB751V-40GTE-17_SOD323-2~D
1
2

FDC654P: P CHANNAL

Panel backlight power control by EC


PANEL_BKEN_EC <40>

Touch Screen Connector

<17>

USBP12-

<17>

USBP12+

1
R427

2
0_0402_5%~D

1
R428

2
0_0402_5%~D

+5V_TSP
JTCH1
1 1
2 2
3
3
4 4
5 5
6 6

<18> E3_PAID_TS_DET#
<17>
<17>

USBP13USBP13+

Place close JTCH1


+5V_TSP

G2

1
G1

TYCO_1734595-6

2
G

2
6
<40> TOUCH_SCREEN_PD#

@ L10
@L10
DLW21SN121SQ2L_4P~D
4 4
3 3
1

3
USBP12+

<30>

+5V_RUN

Q32

PMV65XP_SOT23-3~D

USBP12_DCONN@
USBP12_D+

Q125B
DMN66D0LDW-7_SOT363-6~D

@D86
@
D86
PESD5V0U2BT_SOT23-3~D

5
4

Webcam PWR CTRL

USBP12-

DMIC0

+5V_TSP

CCD_OFF

<30>

JST_BM08B-SRSS-TB1-LF-SN~D
CONN@

DMIC0

DMIC_CLK

C302
0.1U_0402_10V7K~D

2
G

+3.3V_RUN

+5V_RUN

DMIC_CLK

3
C301
0.1U_0402_25V6K~D

C300
10U_0805_10V6K~D

C299
0.1U_0402_25V6K~D

CAM_MIC_CBL_DET# <17>

C306
0.1U_0402_25V6K~D

PMV65XP_SOT23-3~D

CAM_MIC_CBL_DET#
USBP12_D+
USBP12_D-

1
2
3
4
5
6
7
8
9
10

R431 DMN66D0LDW-7_SOT363-6~D
10K_0402_5%~D
Q125A

Q23

+CAMERA_VDD

CCD_OFF

1
3

EN_INVPWR

<41> EN_INVPWR

D8
PESD5V0U2BT_SOT23-3~D

1
2
3
4
5
6
7
8
G1
G2

<40>

2
1
47K_0402_5%~D

PANEL_BKEN_DGPU <45>

R1138
100K_0402_5%~D

BIA_PWM_EC <41>

For Webcam

1
2

6 2
1

1
R423

+CAMERA_VDD

74AHCT1G125GW_SOT353-5~D

D64
RB751V-40GTE-17_SOD323-2~D
1
2

JCAM1

C296
0.1U_0603_50V7K~D

PWR_SRC_ON

U3

D68
RB751V-40GTE-17_SOD323-2~D
1
2

Q22
SSM3K7002FU_SC70-3~D

P
A

PANEL_BKEN_PCH <16>

1
R1137
10K_0402_5%~D

+BL_PWR_SRC

R422
100K_0402_5%~D

C244
0.1U_0402_10V7K~D
1
2

D67
RB751V-40GTE-17_SOD323-2~D
1
2

BIA_PWM_PCH <16>

Close to JLVD1.41

40mil

6
5
2
1

2
G

BIA_PWM_LVDS

OE#

<23,25,40> DGPU_SELECT#

Close to JLVDS1.42,43

+3.3V_RUN

Q21
FDC654P-G_SSOT-6~D

+PWR_SRC

40mil
S

+3.3V_RUN

+LCDVDD

C297
1000P_0402_50V7K~D

D66
RB751V-40GTE-17_SOD323-2~D
1
2

Q20
PDTC124EU_SC70-3~D

Place near to JLVDS1

+LCDVDD
LCD_CBL_DET# <17>

ACES_59003-0400C-001
CONN@

C292
0.1U_0402_25V6K~D

SW_LVDS_ACLK+ <23>
SW_LVDS_ACLK- <23>

BAT54CW_SOT323-3~D

C243
0.1U_0402_25V6K~D

LDDC_CLK_SW
2
2.2K_0402_5%~D
LDDC_DATA_SW
2
2.2K_0402_5%~D

1
R159
1
R160

EN_LCDPWR 2

<45> ENVDD_GPU

C298
0.1U_0402_25V6K~D

LDDC_DATA_SW
LDDC_CLK_SW
LCD_TST

<40> LCD_VCC_TEST_EN
+3.3V_RUN

C43
5P_0402_50V8C~D

SW_LVDS_A2+ <23>
SW_LVDS_A2- <23>
SW_LVDS_A1+ <23>
SW_LVDS_A1- <23>
SW_LVDS_A0+ <23>
SW_LVDS_A0- <23>
LDDC_DATA_SW <23>
LDDC_CLK_SW <23>
LCD_TST
<40>
+3.3V_RUN

SW_LVDS_BCLK+ <23>
SW_LVDS_BCLK- <23>

C293
0.1U_0402_25V6K~D

<23>
<23>
<23>
<23>
<23>
<23>

C41
5P_0402_50V8C~D

SW_LVDS_B2+
SW_LVDS_B2SW_LVDS_B1+
SW_LVDS_B1SW_LVDS_B0+
SW_LVDS_B0-

D6

R1632
1M_0402_5%~D

<16,40> ENVDD_PCH

Q19B
DMN66D0LDW-7_SOT363-6~D

DISP_ON
BIA_PWM_LVDS
1
2
LE92 BLM18BB221SN1D_2P~D

D53
RB751V-40GTE-17_SOD323-2~D
2
1

R414
10K_0402_5%~D

PANEL_HDD_LED <44>

+3.3V_ALW

R413
130_0402_1%~D

1
2
C246 0.1U_0603_50V7K~D

C42
5P_0402_50V8C~D

panel side LED power

C40
5P_0402_50V8C~D

46
45
44
43
42
41

+5V_ALW for
+5V_ALW
BATT_WHITE_LED <44>
BATT_YELLOW_LED <44>
BREATH_WHITE_LED <44>
+BL_PWR_SRC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Q19A
DMN66D0LDW-7_SOT363-6~D

GND
BATT_WHITE_LED
BATT_YELLOW_LED
BREATH_WHITE_LED
VR_SRC
VR_SRC
VR_SRC
NC
DISP_ON/OFF#
PWM
CONNTST_GND
VR_GND
VR_GND
VR_GND
LCD_B_CLK+
LCD_B_CLKGND
LVDS_B2+
LVDS_B2LVDS_B1+
LVDS_B1LVDS_B0+
LVDS_B0GND
LVDS_A_CLK+
LVDS_A_CLKGND
LVDS_A2+
LVDS_A2LVDS_A1+
LVDS_A1LVDS_A0+
LVDS_A0EDID_DATA
MGND6
EDID_CLK
MGND5
BIST
MGND4
V_EDID
MGND3
LCD_VDD
MGND2
LCD_VDD
MGND1
CONNTST

+LCDVDD

JLVDS1

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

eDP & CAM &TS Conn


Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

24

of

66

+5V_RUN

U18
B

Channel A --> GPU

Channel B --> PCH

MAX14885E

<45> GPU_CRT_RED
<16> PCH_CRT_RED

7
17

<45> GPU_CRT_GRN
<16> PCH_CRT_GRN

8
18

<45> GPU_CRT_BLU
<16> PCH_CRT_BLU

9
19

BLUA
BLUB

<45> GPU_CRT_CLK_DDC
<16> PCH_CRT_DDC_CLK

5
15

SCLA
SCLB

<45> GPU_CRT_DAT_DDC
<16> PCH_CRT_DDC_DAT

6
16

+3.3V_RUN

1
R416

2 CRT_EN
100K_0402_5%~D

GRNA
GRNB

VL

RED1
RED2
GRN1
GRN2

SDAA
SDAB

21

33
24

SCL1
SCL2
SDA1
SDA2

34
25

1
40
39
38

S00
S01
S10
S11

SH1
SH2

37
28

30
20
10

GND
GND
GND

41

SV1
SV2
NC

RED_CRT
RED_DOCK

32
23

SVA
SVB

4
14

EN

C1181
1U_0402_6.3V6K~D

11

SHA
SHB

<45> GPU_CRT_VSYNC
<16> PCH_CRT_VSYNC

CRT_SWITCH

VCC

1
C1182
1U_0603_10V7K~D

29

35
26

<45> GPU_CRT_HSYNC
<16> PCH_CRT_HSYNC

CRT_SWITCH

VCC

31
22

3
13

<40> EDID_SELECT#
<40> CRT_SWITCH
<23,24,40> DGPU_SELECT#

REDA
REDB

BLU1
BLU2

+3.3V_RUN

<31>
<39>

GREEN_CRT <31>
GREEN_DOCK <39>
BLUE_CRT
BLUE_DOCK

Port 1 --> MB Port RGB

<31>
<39>

CLK_DDC2_CRT <31>
CLK_DDC2_DOCK <39>

Port 2 --> Docking Port RGB

DAT_DDC2_CRT <31>
DAT_DDC2_DOCK <39>
HSYNC_BUF <31>
HSYNC_DOCK <39>

36
27

VSYNC_BUF <31>
VSYNC_DOCK <39>

12

GPAD
MAX14885EETL+T_TQFN40_5X5~D

CRT_SWITCH

DGPU_SELECT#

EDID_SELECT#

A --> Port 1

B --> Port 1

A --> Port 2

B --> Port 2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn

CRT/Video switch
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
1

Sheet

25

of

66

NC

2
3

+5V_RUN

D4
BAT1000-7-F_SOT23-3~D
+5V_RUN_HDMI

R475 1

+3.3V_RUN_HDMI

2 4.7K_0402_5%~D

HDMI_APD
HDMI_EMI0
HDMI_EMI1

+3.3V_RUN_HDMI

HDMI_PEQ
1

2
1
3

HDMI_OE#
D

HDMI_HPD_SINK 2
G

C358
2.2U_0603_6.3V6K~D

R467
499_0402_1%~D

R443
4.7K_0402_5%~D

HDMI_PRE

25

29
28
4
1
12
11
27
33
6
3
10
35

2
15
21
26
40
46
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

22
23
19
20
16
17
13
14

HPDX

2
1

2
1

2
2 1.5K_0402_5%~D HDMI_SDA_SINK
2 1.5K_0402_5%~D HDMI_SCL_SINK
HDMI_PIO

R460 1
R461 1

+5V_HDMI_DDC

32
34

OUT1p
OUT1n
OUT2p
OUT2n
OUT3p
OUT3n
OUT4p
OUT4n

HDMI_HPD_SINK

R1164
10K_0402_5%~D
1
2 HDMI_HPD_SINK_R
HDMI_SDA_SINK
HDMI_SCL_SINK
HDMI_CEC
TMDSE_CON_CLK#
TMDSE_CON_CLK
TMDSE_CON_N0
TMDSE_CON_P0
TMDSE_CON_N1

TMDSE_RP_P2
TMDSE_RP_N2
TMDSE_RP_P1
TMDSE_RP_N1
TMDSE_RP_P0
TMDSE_RP_N0
TMDSE_RP_CLK
TMDSE_RP_CLK#

TMDSE_CON_P1
TMDSE_CON_N2
TMDSE_CON_P2

OE#

SDA
SCL

SDA_SINK
SCL_SINK
PIO
ASQ0
ASQ1
APD
EMI0
EMI1
REXT
PEQ
CEXT
PRE

8
9

1
@ R451
L19

DPE_GPU_HPD <45>

TMDS_E_GPU_DDC# <46>
TMDS_E_GPU_DDC <46>

@ R476

TMDSE_CON_CLK#

TMDSE_RP_CLK

TMDSE_CON_CLK

1
@ R462
L20

PS8171QFN48G_QFN48_7X7

TMDSE_RP_N0

TMDSE_RP_P0

+3.3V_RUN_HDMI

@ R478

2 4.7K_0402_5%~D

HDMI_APD
4.7K_0402_5%~D
@R479
@
R479 1

+3.3V_RUN_HDMI

@ R480

2 4.7K_0402_5%~D

HDMI_EMI0
4.7K_0402_5%~D
@R481
@
R481 1

HDMI_EMI1

@ R482

2 4.7K_0402_5%~D

4.7K_0402_5%~D
@R483
@
R483 1

TMDSE_RP_N1

TMDSE_RP_P1

HIGH
DDCBUF (Active Buffer)
Setting1
PIO (HPD setting)
HPD=HPD_SINK#
APD (Auto power down)
Enable
PEQ (level of EQ)
High level
PRE (pre-emphasis)
Low level

LOW
No
HPD=HPD_SINK
Disable
Mid level
No

MID
Setting2

TMDSE_RP_N2

2 4.7K_0402_5%~D

4.7K_0402_5%~D
@R485
@
R485 1

+3.3V_RUN_HDMI

1
@ R486

TMDSE_CON_N0

TMDSE_CON_P0

2
0_0402_5%~D

TMDSE_CON_N1

TMDSE_CON_P1

Low level
High level

HDMI_PEQ

@ R484

DLW21SN900HQ2L_0805_4P~D
1
2
@ R469
0_0402_5%~D

TMDSE_RP_P2
+3.3V_RUN_HDMI

2
0_0402_5%~D

DLW21SN900HQ2L_0805_4P~D
1
2
@ R466
0_0402_5%~D

4.7K_0402_5%~D
@R477
@
R477 1

20
21
22
23

2
0_0402_5%~D

TMDSE_RP_CLK#

1
@ R468
L21
+3.3V_RUN_HDMI

DLW21SN900HQ2L_0805_4P~D
1
2
@ R459
0_0402_5%~D

HDMI_PIO

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+
GND

DDC_EN
DDCBUF

Q25
SSM3K7002FU_SC70-3~D

JHDMI1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

TYCO_2041270-1
CONN@

HPD_SINK

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

2 4.7K_0402_5%~D
2 4.7K_0402_5%~D
1 4.7K_0402_5%~D
HDMI_OE#

30

IN1p
IN1n
IN2p
IN2n
IN3p
IN3n
IN4p
IN4n

5
18
24
31
36
37
43
49

R472 1
@ R473 1
@ R474 2

+3.3V_RUN_HDMI
+3.3V_RUN_HDMI

1
2

HDMI_HPD_SINK

39
38
42
41
45
44
48
47

C338
10U_0805_10V6K~D

TMDSE_GPU_C_P2
TMDSE_GPU_C_N2
TMDSE_GPU_C_P1
TMDSE_GPU_C_N1
TMDSE_GPU_C_P0
TMDSE_GPU_C_N0
TMDSE_GPU_C_CLK
TMDSE_GPU_C_CLK#

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D

C344
0.1U_0402_25V6K~D

1
1
1
1
1
1
1
1

C342
0.1U_0402_25V6K~D

R1168
0_0402_5%~D

D70
RB751V-40GTE-17_SOD323-2~D

+5V_RUN

TMDSE_GPU_P2
TMDSE_GPU_N2
TMDSE_GPU_P1
TMDSE_GPU_N1
TMDSE_GPU_P0
TMDSE_GPU_N0
TMDSE_GPU_CLK
TMDSE_GPU_CLK#

2
2
2
2
2
2
2
2

C340
0.1U_0402_25V6K~D

<46>
<46>
<46>
<46>
<46>
<46>
<46>
<46>

C346
C347
C348
C349
C350
C351
C352
C353

C355
0.1U_0402_25V6K~D

U19
B

C354
0.01U_0402_25V7K~D

C337
0.1U_0402_10V7K~D

+3.3V_RUN_HDMI

Close to U19 VCC pins

+VDISPLAY_VCC
@ R5
0_1206_5%~D

PJP54@
PAD-OPEN1x1m

F2
0.5A_15V_SMD1812P050TF

+3.3V_RUN

1
@ R470
L22
4 4
1

2
0_0402_5%~D
3
2

TMDSE_CON_N2

TMDSE_CON_P2

DLW21SN900HQ2L_0805_4P~D
1
2
@ R471
0_0402_5%~D

2 4.7K_0402_5%~D

HDMI_PRE

2
4.7K_0402_5%~D

@R487
@
R487 1

2 4.7K_0402_5%~D

+3.3V_RUN_HDMI

HDMI_CEC

2
R1165

DPE_GPU_HPD

1
R1128

DELL CONFIDENTIAL/PROPRIETARY

1
10K_0402_5%~D

Compal Electronics, Inc.

2
100K_0402_5%~D

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn

HDMI port
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
1

Sheet

26

of

66

+3.3V_RUN

AUX/DDC GPU for DPC to E-DOCK

+3.3V_RUN

AUX/DDC GPU for DPD to E-DOCK

C356
0.1U_0402_25V6K~D

<46> DPC_GPU_AUX/DDC

C357
0.1U_0402_10V7K~D
DPC_GPU_AUX/DDC
2
1 DPC_GPU_AUX_C

<46> DPC_GPU_AUX#/DDC

U20
1
2

DPC_DOCK_AUX

<39> DPC_DOCK_AUX
DPC_GPU_AUX#/DDC 2
C360

1 DPC_GPU_AUX#_C
0.1U_0402_10V7K~D
DPC_DOCK_AUX#

<39> DPC_DOCK_AUX#

2
C366
0.1U_0402_25V6K~D

BE0
A0
B0

A3

4
5

BE1
A1

B1

VCC
BE3

B3
BE2

GND

C367
0.1U_0402_10V7K~D
DPD_GPU_AUX/DDC
2
1 DPD_GPU_AUX_C

14
13
<46> DPD_GPU_AUX/DDC

DPC_GPU_AUX/DDC

12

A2

B2

DPD_DOCK_AUX

<39> DPD_DOCK_AUX

11
10

DPD_GPU_AUX#/DDC 2
C368

<46> DPD_GPU_AUX#/DDC

DPC_GPU_AUX#/DDC

BE0
A0

VCC
BE3

B0

4
5

1 DPD_GPU_AUX#_C
0.1U_0402_10V7K~D
DPD_DOCK_AUX#

<39> DPD_DOCK_AUX#

U23
1
2

A3

BE1
A1

6
7

PI3C3125LEX_TSSOP14~D

B3
BE2

B1

A2

GND

B2

14
13
DPD_GPU_AUX/DDC

12
11
10

DPD_GPU_AUX#/DDC

9
8

PI3C3125LEX_TSSOP14~D

+5V_RUN
+5V_RUN
1

DPC_CA_DET#
DPD_CA_DET

<39> DPD_CA_DET

U21
NC7SZ04P5X-G_SC70-5~D

A
3

C369
0.1U_0402_25V6K~D
4

5
P

<39> DPC_CA_DET

NC

C365
0.1U_0402_25V6K~D
DPC_CA_DET

NC

DPD_CA_DET#

U24
NC7SZ04P5X-G_SC70-5~D

There is a new die for PI3C3125. Sample availabe on May.

+3.3V_RUN

R1539
2.2K_0402_5%~D

6
1
1

2
0_0402_5%~D

DPD_DOCK_AUX

3
4

5
4

1
@ R1064

R1066
2.2K_0402_5%~D

DPC_DOCK_AUX#

1
@ R1067

Q111B
DMN66D0LDW-7_SOT363-6~D

Q113B
DMN66D0LDW-7_SOT363-6~D

2
0_0402_5%~D

+3.3V_RUN

DPD_CA_DET

1
@R1523
@
R1523

1
2

1
1

R1530
2.2K_0402_5%~D

3
4

2
R1065
100K_0402_5%~D
DPC_DOCK_AUX

1
2
6

R1063
100K_0402_5%~D

C1175
0.01U_0402_16V7K~D

+3.3V_ALW2

DMN66D0LDW-7_SOT363-6~D
Q109B

+3.3V_RUN

2
0_0402_5%~D

DMN66D0LDW-7_SOT363-6~D
Q109A

DMN66D0LDW-7_SOT363-6~D
Q110A

C1174
0.01U_0402_16V7K~D

DPC_CA_DET
1

DMN66D0LDW-7_SOT363-6~D
Q110B

1
@ R1538

Q111A
DMN66D0LDW-7_SOT363-6~D

R1062
2.2K_0402_5%~D
Q113A
DMN66D0LDW-7_SOT363-6~D

R1537
100K_0402_5%~D

R1532
100K_0402_5%~D

+5V_RUN

+3.3V_ALW2

+3.3V_RUN
+5V_RUN

2
0_0402_5%~D

DPD_DOCK_AUX#

DELL CONFIDENTIAL/PROPRIETARY
1
R491
1
R492

DPD_CA_DET
2
1M_0402_5%~D
DPC_CA_DET
2
1M_0402_5%~D

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

DP AUX SW
Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

27

of

66

+3.3V_RUN

PJP53
PAD-OPEN1x1m

Free Fall Sensor


+3.3V_RUN_FFS

C388
0.1U_0402_25V6K~D

C387
10U_0603_6.3V6M~D

1
C

U88

LNG3DM
1
14

<17> HDD_FALL_INT

HDD_FALL_INT
FFS_INT2

11
9

INT 1
INT 2

<7,12,13,14,15,35> DDR_XDP_WAN_SMBDAT
<7,12,13,14,15,35> DDR_XDP_WAN_SMBCLK

5
12

GND
GND
SDO/SA0
SDA / SDI / SDO
SCL/SPC
NC
CS
NC

7
6
4
8

10
13
15
16

RES
RES
RES
RES

VDD_IO
VDD

2
3

HDD PWR

LNG3DMTR_LGA16_3X3~D
+5V_ALW

+PWR_SRC_S

JSATA1

@ R506
100K_0402_5%~D

1
2

C396
0.1U_0402_25V6K~D

FFS_INT2_Q
C395
1000P_0402_50V7K~D

<36,40,43,56,64> RUN_ON
<11,16,36,40,43,56> SIO_SLP_S3#

GND1
GND2

1
@ R1621
1
R1624

2
0_0402_5%~D
2
0_0402_5%~D
@ R505
100K_0402_5%~D

23
24

1
2
5
6

+5V_RUN
@ PJP3
1 1
2

+5V_HDD
2

JUMP_43X79

SHORT DEFAULT

R504
100K_0402_5%~D
2

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

@ Q27
SI3456DDV-T1-GE3_TSOP6~D

+5V_HDD Source

JAE_SP100421-HDD
CONN@

Main SATA +5V Default

Pleace near HDD CONN


+3.3V_RUN_HDD

C399
0.1U_0402_25V6K~D

C402
0.1U_0402_25V6K~D

Q29A
DMN66D0LDW-7_SOT363-6~D

FFS_INT2_Q
Q29B
DMN66D0LDW-7_SOT363-6~D

FFS_INT2

HDD_DET#
+5V_HDD

+5V_HDD
R508
100K_0402_5%~D

<18> FFS_INT2

+3.3V_RUN_HDD

PAD-OPEN1x1m
<14> HDD_DET#

1
+3.3V_RUN

+5V_HDD

PJP64
B

D
G
HDD_EN_5V

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

GND
RX+
RXGND
TXTX+
GND

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

C394
10U_0805_10V6K~D

+3.3V_RUN

1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D

Q28A
DMN66D0LDW-7_SOT363-6~D

<14> PSATA_PRX_DTX_N0_C
<14> PSATA_PRX_DTX_P0_C

2
C383 2
C384
2
C385 2
C386

<14> PSATA_PTX_DRX_P0_C
<14> PSATA_PTX_DRX_N0_C

C393
0.1U_0603_50V7K~D

2 DDR_XDP_WAN_SMBDAT
10K_0402_5%~D
2 DDR_XDP_WAN_SMBCLK
10K_0402_5%~D
2 HDD_FALL_INT
100K_0402_5%~D

R500
100K_0402_5%~D

Q28B
DMN66D0LDW-7_SOT363-6~D

1
R501
1
R502
1
R503

1
2
3
4
5
6
7

R499
100K_0402_5%~D

+3.3V_RUN

+3.3V_ALW2

For HDD Temp.

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

Pleace near HDD CONN

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

HDD CONNECTOR
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

28

of

66

+3.3V_ALW

1
R510

2 ZODD_WAKE#
10K_0402_5%~D

1
R513

2 MOD_MD
10K_0402_5%~D

1
R514

2 USB30_SMI#
100K_0402_5%~D

For ODD

+3.3V_ALW_PCH
D

+5VMOD Source

0.1U_0402_10V7K~D 2
0.1U_0402_10V7K~D 2

<15> PCIE_PTX_EMBRX_P4
<15> PCIE_PTX_EMBRX_N4

EMBCLK_REQ#
PCIE_WAKE#
PLTRST_EMB#
BAY_SMBDAT
BAY_SMBCLK

<15> EMBCLK_REQ#
<35,36,41> PCIE_WAKE#
<17> PLTRST_EMB#
<41,53> BAY_SMBDAT
<41,53> BAY_SMBCLK
<40> MOD_SATA_PCIE#_DET

+3.3V_ALW

1
R1183

1 C409 PCIE_PTX_EMBRX_P4_C
1 C408 PCIE_PTX_EMBRX_N4_C

+5V_MOD

2
10K_0402_5%~D

+5V
CLKREQ#
WAKE#
PERST#
SMB_DATA
SMB_CLK
HPD

R512
100K_0402_5%~D

GND1
GND2

1
2
5
6
+5V_MOD

+5V_RUN

@ PJP4
1 1
2

JUMP_43X79
R511
100K_0402_5%~D

+3.3V_ALW
B

TYCO_2-2129116-3
CONN@

SSM3K7002FU_SC70-3~D
MOD_MD

32
33

Q76

SI3456DDV-T1-GE3_TSOP6~D

25
26
27
28
29
30
31

<40> MODC_EN

GND
REFCLK+
REFCLKGND
PETX+
PETXGND
GND
PERX+
PERXGND

14
15
16
17
18
19
20
21
22
23
24

<15> PCIE_PRX_EMBTX_P4
<15> PCIE_PRX_EMBTX_N4

1
2

MODC_EN# 5

MOD_EN

C401
10U_0805_10V6K~D

Pleace near ODD CONN

<15> CLK_PCIE_EMB
<15> CLK_PCIE_EMB#

D Q30
G
2

DP
+5V
+5V
MD
GND
GND

Q31A
DMN66D0LDW-7_SOT363-6~D

C398
0.1U_0402_25V6K~D

C397
1000P_0402_50V7K~D

R507
100K_0402_5%~D
R509
100K_0402_5%~D

C400
0.1U_0603_50V7K~D

MOD_MD
1

+5V_ALW

Q31B
DMN66D0LDW-7_SOT363-6~D

+5V_MOD

8
9
10
11
12
13

+3.3V_ALW2

<41> DEVICE_DET#

+5V_MOD

+PWR_SRC_S

GND
A+
AGND
BB+
GND

SATA_ODD_PRX_DTX_N1
SATA_ODD_PRX_DTX_P1

1
2
3
4
5
6
7

<14> SATA_ODD_PRX_DTX_N1_C
<14> SATA_ODD_PRX_DTX_P1_C

SATA_ODD_PTX_DRX_P1
SATA_ODD_PTX_DRX_N1

<14> SATA_ODD_PTX_DRX_P1_C
<14> SATA_ODD_PTX_DRX_N1_C

1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D

JSATA2

2
C407 2
C406
2
C405 2
C404

ZODD_WAKE#

R515
100K_0402_5%~D

ZODD_WAKE# <40>
2

MODC_EN#

USB30_EN

DMN66D0LDW-7_SOT363-6~D
USB30_SMI#
3

Q123B
USB30_SMI# <14>

USB30_EN

Q123A
DMN66D0LDW-7_SOT363-6~D

2
1

MOD_SATA_PCIE#_DET

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

ODD CONNECTOR
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

29

of

66

2
1

<14> PCH_AZ_CODEC_SDOUT
<14> PCH_AZ_CODEC_SYNC

<14> PCH_AZ_CODEC_RST#

PCH_AZ_CODEC_BITCLK

PCH_AZ_CODEC_SDOUT

5
10

PCH_AZ_SDIN0_R
2
33_0402_5%~D
PCH_AZ_CODEC_RST#

1
R1096

8
11

DVDD_CORE

AVDD1
AVDD2

DVDD_IO

PVDD
PVDD

DVDD

SENSE_A
SENSE_B
PORTA_L
PORTA_R
VrefOut_A

BITCLK
SDATA_OUT

PORTB_L
PORTB_R

SYNC
SDATA_IN

PORTD_+L
PORTD_-L

RESET#
PORTD_+R
PORTD_-R

I2S_MCLK

15

I2S_BCLK

16

I2S_DO

1
R1097

2
33_0402_5%~D

17

I2S_LRCLK
I2S_DI#

18

Place R1097 close to codec

24

Close to U72 pin6

I2S_MCLK

MONO_OUT

I2S_SCLK

PC_BEEP

I2S_DOUT
DMIC_CLK/GPIO 1
DMIC_0/GPIO 2
DMIC1/GPIO0/SPDIFOUT1
SPDIFOUT0//GPIO3/Aux_Out

I2S_LRCLK
I2S_DIN

CAP+
PCH_AZ_CODEC_BITCLK

20

<40> AUD_NB_MUTE#

47

2
10K_0402_5%~D

42

MIC_IN_L
MIC_IN_R
+VREFOUT

31
32

AUD_HP_OUT_L
AUD_HP_OUT_R

40
41

INT_SPK_L+
INT_SPK_L-

44
43

INT_SPK_R+
INT_SPK_R-

EAPD

VREFFILT
CAP2
VVreg

DVSS
PVSS

AVSS1
AVSS
AVSS

GND

C1163

2
1U_0402_6.3V6K~D
+VREFOUT
1
R1143

+VDDA_AVDD

AUD_PC_BEEP

2
4
46
48

DMIC_CLK_L 1
LE3

35

1
+3.3V_RUN

PORT E

20K

PORT B

PORT F

10K

NA

DMIC0

5.11K
R1082
100K_0402_5%~D

PORT A

SPDIFOUT0

14
<40> EN_I2S_NB_CODEC#

EN_I2S_NB_CODEC#
1
2
1
15
R1540
1K_0402_1%~D

1Y#

2A

2Y#

3A

3Y#

4A

4Y#

5A

5Y#

6A

6Y#

OE1#
OE2#

3
1

3
1

GND

DAI_BCLK#

DAI_LRCK#

DAI_DO#

DAI_12MHZ#

DAI_BCLK#

<39>

DAI_LRCK#

<39>

DAI_DO#

11
+3.3V_RUN
I2S_DI# 1
@ R166

13

DAI_DI
2
0_0402_5%~D

8
@ D58
DA204U_SOT323-3~D

CD74HC366M96_SO16~D

SPDIFOUT1 (DMIC1)

DAI_DI

2.49K

<39>

DAI_12MHZ# <39>

6
10

1A

39.2K

VCC

DAI_DI

Pull-up to AVDD

<39>

DAI_12MHZ#

SENSE_B

U73

16

1
2
4

1
1

+3.3V_RUN

12

R1078
2.49K_0402_1%~D
2
1
C979
1000P_0402_50V7K~D

2
10K_0402_5%~D
2
10K_0402_5%~D

@ D57
DA204U_SOT323-3~D

SENSE_A

1
@ R162
1
@ R163
1
@ R164
1
@ R165

2 I2S_BCLK
22_0402_5%~D
2 I2S_LRCLK
0_0402_5%~D
2 I2S_DO
0_0402_5%~D
2 I2S_MCLK
22_0402_5%~D

+VDDA_AVDD

@ D56
DA204U_SOT323-3~D

Place closely to Pin 14

@ D55
DA204U_SOT323-3~D

1
R162, R163, R164, R165,R166 CO-lay with U73

DAI_DO#

@ D54
DA204U_SOT323-3~D

Resistor

R1081
100K_0402_5%~D

1
@ R1141
1
@ R1142

Place C962 close to Codec

26
30
33

<31,40>

<41>

Place C963~C966 close to Codec

@ C967
0.1U_0402_25V6K~D

DAI_LRCK#

R1080
20K_0402_1%~D

<14>

BEEP

C962
4.7U_0603_6.3V6K~D

+3.3V_RUN

Add for solve pop noise and detect issue

R1079
39.2K_0402_1%~D

SPKR

DAI_BCLK#

2
100K_0402_5%~D
2
100K_0402_5%~D

<24>
<24>

2
0_0402_5%~D
PAD~D

21
22
34
37

C983
100P_0402_50V8J~D

AUD_HP_NB_SENSE

+3.3V_RUN

1
R1119
1
R1120

Place LE3 close to codec

1
@ R169
@ T90

36

C1103
0.1U_0402_10V7K~D

AUD_SENSE_B

PAD-OPEN1x1m
R1087
100K_0402_5%~D

Q107B
DMN66D0LDW-7_SOT363-6~D

<31>

AUD_HP_OUT_L <31>
AUD_HP_OUT_R <31>

2
1
C1105
0.1U_0402_25V6K~D
2
1
C1106
0.1U_0402_25V6K~D
2
DMIC_CLK
BLM18BB221SN1D_2P~D
DMIC0

12

2
Q107A
DMN66D0LDW-7_SOT363-6~D

+VREFOUT

place at Codec bottom side


@ PJP62
1
2

C982
100P_0402_50V8J~D

25

+3.3V_RUN

Notes:
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals

C981
100P_0402_50V8J~D

C980
0.1U_0402_10V7K~D

R1086
20K_0402_1%~D

1
@

AUD_SENSE_A

place at AGND and DGND plane

R1083
2.49K_0402_1%~D
2
1

MIC_IN_R

2
2.2K_0402_5%~D

92HD90B2X5NLGXYAX8_QFN48_7X7~D

Place closely to Pin 13.

1
1

49

28
29
23

C966
10U_0805_10V6K~D

1
R1099

AUD_SENSE_A
AUD_SENSE_B

C965
1U_0603_10V7K~D

7
@ C977
10P_0402_50V8J~D

13
14

C964
4.7U_0603_6.3V6K~D

No Connect

+3.3V_RUN

1
@C978
@
C978
0.1U_0402_10V7K~D

+VDDA_PVDD

C963
4.7U_0603_6.3V6K~D

45
39

No Connect
CAP-

@ R1076
10_0402_1%~D

@ R1077
47_0402_5%~D

19

BCLK: Audio serial data bus bit clock input/output


LRCK: Audio serial data bus word clock input/output

PCH_AZ_CODEC_SDOUT

27
38

Close to U72 pin5

U72

Place R1096 close to codec

<14> PCH_AZ_CODEC_SDIN0

3
1

3
1

<14> PCH_AZ_CODEC_BITCLK

C1180
1U_0603_10V7K~D

@ DE1
PESD5V0U2BT_SOT23-3~D

@ DE2
PESD5V0U2BT_SOT23-3~D

680P_0402_50V7K~D

680P_0402_50V7K~D

Place C994, C952~C957 close to Codec

@ C976

@ C975

680P_0402_50V7K~D

680P_0402_50V7K~D

@ C974

@ C973

C960
10U_0805_10V6K~D

MOLEX_53398-0471~D

C961
0.1U_0402_25V6K~D

PAD-OPEN1x1m

5
6

C959
0.1U_0402_25V6K~D

1
2
3 G1
4 G2

C958
10U_0805_10V6K~D

1
2
3
4

C956
1U_0603_10V7K~D

INT_SPKL_L+
INT_SPKR_LINT_SPKR_R+
INT_SPKR_R-

C954
10U_0805_10V6K~D

BLM18BD121SN1D_2P~D
BLM18BD121SN1D_2P~D
BLM18BD121SN1D_2P~D
BLM18BD121SN1D_2P~D

+DVDD_CORE
1

C953
0.1U_0402_25V6K~D

2
2
2
2

C994
0.1U_0402_25V6K~D

1
1
1
1

C952
1U_0603_10V7K~D

L91
L92
L93
L94

INT_SPK_L+
INT_SPK_LINT_SPK_R+
INT_SPK_R-

JSPK1 CONN@

R1095
0_0805_5%~D

+3.3V_RUN_DVDD

@ PJP65

C955
10U_0805_10V6K~D

+3.3V_RUN_DVDD

DVDD_IO should match


with HDA Bus level

C957
0.1U_0402_25V6K~D

+3.3V_RUN

15 mils trace

+5V_RUN

place close to pin38


L77
BLM21PG600SN1D_0805~D
1
2
+5V_RUN

+VDDA_AVDD

place close to pin27

Internal Speakers Header

5
4

Q106A
DMN66D0LDW-7_SOT363-6~D

<40> DOCK_HP_DET

DOCK_MIC_DET

Q106B
DMN66D0LDW-7_SOT363-6~D

PORT A

External MIC

PORT B

HeadPhone Out

PORT C

Dock Audio

PORT D

Internal SPK

DELL CONFIDENTIAL/PROPRIETARY

<40>

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn

Title

Azalia (HD) Codec


Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet

30

of

66

I/O board CONN.


Change to TYCO_2041300-2_60P-T and Horizonal reverse

to SSI

JIO1
<32> SW_LAN_TX0+
<32> SW_LAN_TX0-

<32> SW_LAN_TX1<32> SW_LAN_TX1+


<32> SW_LAN_TX2+
<32> SW_LAN_TX2-

POWER_SW#_MB

<41,42> POWER_SW#_MB

<32> SW_LAN_TX3<32> SW_LAN_TX3+

SW1
NTC033-XJ1J-X260CM_4P
3
1
+5V_ALW

@D23
@
D23
3
2

PESD24VS2UT_SOT23-3~D

POWER & INSTANT ON SWITCH


Media Board

Defult on,
WIRELESS_ON/OFF#:
LOW: ON
+3.3V_ALW
HIGH: OFF

<17> USB_OC4#
<17>
<17>

USBP9+
USBP9-

<40> USB_SIDE_EN#
<30,40> AUD_HP_NB_SENSE
DETECT_GND

JMDIA1
1
2
3
4
5
6
7
8

<41> VOL_MUTE
<41> VOL_DOWN
<41>
VOL_UP

<40> WIRELESS_ON#/OFF
<40,44> LID_CL#
1

1
2
3
4
5
6
7
8

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

62
64
66

GND
GND
GND

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

GND
GND
GND

61
63
65

IO_LOOP#
<18>
VSYNC_BUF <25>
HSYNC_BUF <25>

RED_CRT
<25>
GREEN_CRT <25>
BLUE_CRT
<25>
DAT_DDC2_CRT <25>
CLK_DDC2_CRT <25>

MIC_IN_R

AUD_HP_OUT_R <30>
MIC_IN_R <30>
AUD_HP_OUT_L <30>

+5V_ALW

1
+3.3V_ALW_PCH
2

PCH_AZ_MDC_RST1#

C1003
0.1U_0402_25V6K~D

PCH_AZ_MDC_SDIN1 <14>
PCH_AZ_MDC_SYNC <14>
PCH_AZ_MDC_SDOUT <14>
PCH_AZ_MDC_BITCLK <14>

Analog_GND
C

G1
G2

9
10

TYCO_2041300-2
CONN@

+3.3V_LAN

+3.3V_ALW_PCH
1

TYCO_2041070-8~D
CONN@

C1001
0.1U_0402_25V6K~D

C50
0.1U_0402_25V6K~D

+5V_RUN
+3.3V_LAN
<32> LED_100_ORG#
<32> LED_10_GRN#
<32> LAN_ACTLED_YEL#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

C1000
0.1U_0402_25V6K~D

C997
0.1U_0402_25V6K~D

Place close
to JIO1.35

Place close
to JIO1.13

LED Board
+5V_ALW

1
2
3
4
5
6

<44> SATA_LED
<44> BATT_WHITE
<44> BATT_YELLOW
<44> WLAN_LED

1
B

JLED1

C1002
0.1U_0402_25V6K~D

1
2
3
4
5 G1
6 G2

7
8

TYCO_2041084-6~D
CONN@

Q44
SSM3K7002FU_SC70-3~D

<14> PCH_AZ_MDC_RST#

PCH_AZ_MDC_RST1#

2
G

+5V_ALW
A

DELL CONFIDENTIAL/PROPRIETARY

R752
10K_0402_5%~D

R751
100K_0402_5%~D

Compal Electronics, Inc.

<40> MDC_RST_DIS#
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

PWR SW/Sub-board Connector


Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

31

of

66

+3.3V_LAN
+3.3V_RUN
1

TP_LAN_JTAG_TMS
2
10K_0402_5%~D
TP_LAN_JTAG_TCK
2
10K_0402_5%~D

R547
10K_0402_5%~D
2

1
@ R545
1
@ R546

U31

<15> PCIE_PTX_GLANRX_P7

1
2

MDI_PLUS1
MDI_MINUS1

17
18

LAN_TX1+
LAN_TX1-

38
39

PETp
PETn

MDI_PLUS2
MDI_MINUS2

20
21

LAN_TX2+
LAN_TX2-

41
42

PERp
PERn

MDI_PLUS3
MDI_MINUS3

23
24

LAN_TX3+
LAN_TX3-

LAN_DISABLE#_R

SMB_CLK
SMB_DATA

RSVD_NC

1
2
5

RSVD_VCC3P3_1
RSVD_VCC3P3_2
VDD3P3_IN

LAN_DISABLE_N

LED

LED0
LED1
LED2

XTAL_OUT
XTAL_IN

LAN_TEST_EN

30

TEST_EN

RES_BIAS

12

RBIAS

JTAG

Place R548, C462, C463 and L29 close to U31

+1.0V_LAN

1
11
40
22
16
8

VDD1P0_40
VDD1P0_22
VDD1P0_16
VDD1P0_8
CTRL_1P0

VSS_EPAD

49

+3.3V_LAN

REGCTL_PNP10

Place C1178 close to pin5

82579_QFN48_6X6~D

+3.3V_M

+1.0V_LAN POWER OPTIONS


Shared with PCH
1.05V SVR

@ R563
0_1206_5%~D

* Internal SRV

STUFF: R548
NO STUFF: L29

STUFF: L29
NO STUFF: R548

Q34

+3.3V_ALW

DOCK_LOM_TRD2DOCK_LOM_TRD2+

27
26

DOCK_LOM_TRD1DOCK_LOM_TRD1+

C3+
C3-

23
22

DOCK_LOM_TRD0DOCK_LOM_TRD0+

LEDC0
LEDC1
LEDC2

19
20
40

DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD10LED_GRN#

LAN_TX1+R

10

LAN_TX01
2
L31
12NH_0603CS-120EJTS_5%~D
LAN_TX0+ 1
2
L30
12NH_0603CS-120EJTS_5%~D

LAN_TX0-R

11

LAN_TX0+R

12

LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#

Layout Notice : Place bead as


close PI3L500 as possible

15
16
42
5
43

FROM NIC

DOCKED

A1-

B3+
B3-

A2+
A2-

LEDB0
LEDB1
LEDB2

A3+

C0+
C0-

A3-

C1+
C1-

SEL

C2+
C2-

LEDA0
LEDA1
LEDA2
PD

LAN_ACTLED_YEL# <31>
LED_100_ORG# <31>
LED_10_GRN# <31>

DOCK_LOM_TRD2- <39>
DOCK_LOM_TRD2+ <39>
DOCK_LOM_TRD1- <39>
DOCK_LOM_TRD1+ <39>

LOM_SPD100LED_ORG#

LOM_SPD10LED_GRN#

DOCK_LOM_TRD0- <39>
DOCK_LOM_TRD0+ <39>

D
G

WLAN_LAN_DISB# <40>

TC7SH08FU_SSOP5~D
U15

Compal Electronics, Inc.

TO
DOCK

www.vinafix.vn
3

DELL CONFIDENTIAL/PROPRIETARY

PAD_GND

DOCK_LOM_ACTLED_YEL# <39>
DOCK_LOM_SPD100LED_ORG# <39>
DOCK_LOM_SPD10LED_GRN# <39>

PI3L720ZHEX_TQFN42_9X3P5~D

+3.3V_LAN
C478
0.1U_0402_10V7K~D
1
2

DOCK_LOM_TRD3- <39>
DOCK_LOM_TRD3+ <39>

1: TO DOCK
0: TO RJ45

SW_LAN_TX0- <31>
SW_LAN_TX0+ <31>

32
31

LAN_TX1-R

SW_LAN_TX1- <31>
SW_LAN_TX1+ <31>

DOCK_LOM_TRD3DOCK_LOM_TRD3+

LAN_TX11
2
L32
12NH_0603CS-120EJTS_5%~D
LAN_TX1+ 1
2
L33
12NH_0603CS-120EJTS_5%~D

13

1
36
35

B2+
B2-

LAN_ACTLED_YEL#
LED_100_ORG#
LED_10_GRN#

A1+

LAN_TX2+R

17
18
41

SW_LAN_TX0SW_LAN_TX0+

LAN_TX2-R

SW_LAN_TX1SW_LAN_TX1+

25
24

A0-

LAN_TX21
2
L35
12NH_0603CS-120EJTS_5%~D
LAN_TX2+ 1
2
L34
12NH_0603CS-120EJTS_5%~D

<16,40> SIO_SLP_LAN#

SW_LAN_TX2- <31>
SW_LAN_TX2+ <31>

29
28

B1+
B1-

A0+

SW_LAN_TX2SW_LAN_TX2+

LAN_TX3+R

39
30
21
14
8
4
1
VDD
VDD
VDD
VDD
VDD
VDD
VDD

34
33

LAN_TX3-R

SW_LAN_TX3- <31>
SW_LAN_TX3+ <31>

C476
0.1U_0402_10V7K~D

SW_LAN_TX3SW_LAN_TX3+

C475
10U_0603_6.3V6M~D

DOCKED

C477
2200P_0402_50V7K~D

5
38
37

B0+
B0-

Q35A
DMN66D0LDW-7_SOT363-6~D

<40>

ENAB_3VLAN
R1638
1M_0402_5%~D

U32

LAN_TX31
2
L37
12NH_0603CS-120EJTS_5%~D
LAN_TX3+ 1
2
L36
12NH_0603CS-120EJTS_5%~D

DOCKED

R565
100K_0402_5%~D

LAN ANALOG
SWITCH

Q35B
DMN66D0LDW-7_SOT363-6~D

6
5
2
1

R564
100K_0402_5%~D

C474
0.1U_0402_25V6K~D

C473
0.1U_0402_25V6K~D

C472
0.1U_0402_25V6K~D

+3.3V_LAN

SI3456DDV-T1-GE3_TSOP6~D

+3.3V_ALW2
+3.3V_LAN
1

Note:
+1.0V_LAN will work at 0.95V to 1.15V

+PWR_SRC_S

C464
1U_0603_10V7K~D

43

VDD1P0_11

Need to verify A3 silicon drive


power before removing C427
KDS crystal vender verify
driving level in A3

9
10

R562
3.01K_0402_1%~D

R561
1K_0402_1%~D

GND

XTALO
XTALI

1
+1.0V_LAN
2

VDD1P0_43

+1.05V_M
@ R548
@R548
0_0805_5%~D
1
2

C1178
22U_0805_6.3V6M~D

GND

C471
33P_0402_50V8J~D

C470
33P_0402_50V8J~D

JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK

+3.3V_LAN

47
46
37

VDD1P0_47
VDD1P0_46
VDD1P0_37

C1177
22U_0805_6.3V6M~D

Y3
25MHZ_18PF_X3G025000DI1H-H~D
1 IN
OUT 3

32
34
33
35

1
14.7K_0402_5%~D
4.7K_0402_5%~D

C469
0.1U_0402_10V7K~D

2
0_0402_5%~D

C468
0.1U_0402_10V7K~D

TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK

2
R5532
R554

C467
0.1U_0402_10V7K~D

1
R1144

+3.3V_LAN_OUT

15
19
29

VDD3P3_15
VDD3P3_19
VDD3P3_29

26
27
25

+RSVD_VCC3P3_1
+RSVD_VCC3P3_2

C466
0.1U_0402_10V7K~D

REGCTL_PNP10

Idc max=330mA

VDD3P3_OUT
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#

T142 PAD~D
T143 PAD~D

+1.0V_LAN
L29

<40> LAN_DISABLE#_R
@ R557
10K_0402_5%~D

4.7UH_CBC2012T4R7M_20%~D

SMBus Device Address 0xC8

2
0_0402_5%~D

MDI

PE_CLKP
PE_CLKN

C463
0.1U_0402_10V7K~D

1
R555

<18> PM_LANPHY_ENABLE

44
45

28
31

2 LAN_SMBCLK_R
0_0402_5%~D
2 LAN_SMBDATA_R
0_0402_5%~D

1
R551
1
R552

<15> LAN_SMBCLK
<15> LAN_SMBDATA

LAN_TX0+
LAN_TX0-

C462
10U_0603_6.3V6M~D

<15> PCIE_PTX_GLANRX_N7

R549
10K_0402_5%~D

13
14

+3.3V_LAN

2
C458
2
C459
1
C460
1
C461

MDI_PLUS0
MDI_MINUS0

<15> PCIE_PRX_GLANTX_N7

CLK_PCIE_LAN
CLK_PCIE_LAN#
1 PCIE_PRX_GLANTX_P7_C
0.1U_0402_10V7K~D
1 PCIE_PRX_GLANTX_N7_C
0.1U_0402_10V7K~D
2 PCIE_PTX_GLANRX_P7_C
0.1U_0402_10V7K~D
2 PCIE_PTX_GLANRX_N7_C
0.1U_0402_10V7K~D

CLK_REQ_N
PE_RST_N

PCIE

<15> CLK_PCIE_LAN
<15> CLK_PCIE_LAN#
<15> PCIE_PRX_GLANTX_P7

48
36

SMBUS

LANCLK_REQ#_R
2
0_0402_5%~D

1
R1187

<15> LANCLK_REQ#
<17> PLTRST_LAN#

Title

Intel 82579 (Hanksville) / LAN SW


Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
2

Sheet
1

32

of

66

+3.3V_RUN

+3.3V_RUN_TPM

PJP61
1

2
+3.3V_SB3V

PAD-OPEN1x1m
+3.3V_SB3V

28

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

26
23
20
17

VCC_0
VCC_1
VCC_2

SB3V

LPCPD#

V_BAT
NBO_13
NBO_14

LAD0
LAD1
LAD2
LAD3

GPIO6
CLK_PCI_TPM_TCM
LPC_LFRAME#
PCH_PLTRST#_EC
IRQ_SERIRQ
CLKRUN#

<15> CLK_PCI_TPM_TCM
<14,35,40,41> LPC_LFRAME#
<17,35,36,40,41> PCH_PLTRST#_EC
<14,40,41> IRQ_SERIRQ
<16,40,41> CLKRUN#

21
22
16
27
15

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#

TESTBI
TESTI

JUSH1

JETWAY_CLK14M
JETWAY_CLK14M <15>
NC_P
1
2
C554
1U_0402_6.3V6K~D

2
TCM_BA0

ATEST_1
ATEST_2
ATEST_3

GND_4
GND_11
GND_18
GND_25

PP

1
@R656
@
R656

2
4.7K_0402_5%~D

<42> BT_COEX_STATUS2
<42> BT_PRI_STATUS
<17> PLTRST_USH#
<40> USH_PWR_STATE#
<18> CONTACTLESS_DET#
+5V_RUN

4
11
18
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

USBP7USBP7+

<41> USH_SMBCLK
<41> USH_SMBDAT
<40> BCM5882_ALERT#

+3.3V_RUN_TPM

AT97SC3204-X2A14-AB_TSSOP28

<17>
<17>

+3.3V_SUS

6
9
8

USH_SMBCLK
2
2.2K_0402_5%~D
USH_SMBDAT
2
2.2K_0402_5%~D

1
R589
1
R585

CE3
27P_0402_50V8J~D

<18> USH_DET#

21
22

C52
0.1U_0402_25V6K~D

1
2
3

C51
0.1U_0402_25V6K~D

TCM_BA1
RE5
33_0402_5%~D

12
13
14

+3.3V_RUN
NC_7

CLK_PCI_TPM_TCM

10
19
24

C53
0.1U_0402_25V6K~D

SP_TPM_LPC_EN

C553
0.1U_0402_25V6K~D

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

1@ U39

C552
2200P_0402_50V7K~D

<40> SP_TPM_LPC_EN
<14,35,40,41>
<14,35,40,41>
<14,35,40,41>
<14,35,40,41>

1@

C551
2200P_0402_50V7K~D

1@ 1

ATMEL TPM for E4


C550
2200P_0402_50V7K~D

C45
4700P_0402_25V7K~D

2
0_0402_5%~D

C44
0.1U_0402_25V6K~D

1
1@ R873

+3.3V_SUS

+3.3V_RUN_TPM

+3.3V_RUN_TPM

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

GND1
GND2

TYCO_2-2041070-0

Co-lay U37 and U38


LPC layout: Place TCM first and then end LPC with TPM.

China TCM: NationZ & Jetway co-lay


+3.3V_RUN_TPM

LOW:Power Down Mode


High:Working Mode

SP_TPM_LPC_EN
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

28
26
23
20
17

CLK_PCI_TPM_TCM
LPC_LFRAME#
PCH_PLTRST#_EC
IRQ_SERIRQ
CLKRUN#
PP
TCM_BA1
TCM_BA0

21
22
16
27
15
7
3
9

LPCPD#
LAD0
LAD1
LAD2
LAD3

VDD_0
VDD_1
VDD_2

10
19
24

GND_11
GND_18
GND_25
GND_4

11
18
25
4
+3.3V_SB3V

TCM_BA0
TCM_BA1

NC_1
NC_2
NC_6
NC_8
NC_P

1
2
6
8
14

JETWAY_CLK14M
1

NC_5
NC_12
NC_13

R660
10K_0402_5%~D

JETWAY_CLK14M

@
RE6
33_0402_5%~D
NC_P

R659
10K_0402_5%~D

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP
BA_1
BA_0

5
12
13

@R658
@
R658
10K_0402_5%~D
2

@ R657
10K_0402_5%~D

+3.3V_RUN_TPM

4@ U37

@
CE4
27P_0402_50V8J~D

SSX44-B-D-T1_TSSOP28~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

USH conn/TPM
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

33

of

66

+3.3V_RUN

2
2
2
2

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
R677

PCIE_PRX_MMITX_P6_C
PCIE_PRX_MMITX_N6_C
PCIE_PTX_MMIRX_P6_C
PCIE_PTX_MMIRX_N6_C
2
191_0402_1%~D

6
7
5
4
3
33

place close to pin U38.32

PE_TXP
PE_TXM
PE_RXP
PE_RXM
PE_REXT
GPAD

13

PE_RST#

14
31

MULTI-IO1
MULTI-IO2

<17> PLTRST_MMI#

<15> MMICLK_REQ#

C560
4.7U_0603_6.3V6K~D

PCIE_PRX_MMITX_P6
PCIE_PRX_MMITX_N6
PCIE_PTX_MMIRX_P6
PCIE_PTX_MMIRX_N6

1
1
1
1

DVDD
AVDD

10
8

+OZ_DVDD
+OZ_AVDD

SKT_VCC
MMI_VCC_OUT

17
15

+SKT_VCC

28
26
29
27
25
24
23
22
21
20

SD/MMCDAT1_R
SD/MMCDAT2_R
SD/MMCDAT0_R

R663 1
R664 1
R665 1

2 33_0402_5%~D SD/MMCDAT1
2 33_0402_5%~D SD/MMCDAT2
2 33_0402_5%~D SD/MMCDAT0

SD/MMCDAT3_R
SD/MMCDAT4_R
SD/MMCDAT5_R
SD/MMCDAT6_R
SD/MMCDAT7_R

R668
R669
R670
R672
R673

2
2
2
2
2

SD/MMCCMD_R
SD/MMCCLK_R
SD/MMCCD#
SDWP

R674 1
1
R676

3.3VDDH
VDDH
PE_VDDH

PE_REFCLKP
PE_REFCLKM

C559
0.1U_0402_25V6K~D

<15>
<15>
<15>
<15>

C569
C571
C567
C568

C564
4.7U_0603_6.3V6K~D

<15> CLK_PCIE_MMI
<15> CLK_PCIE_MMI#

+3.3VDDH
16
+VDDH_SD
9
+PE_VDDH
2
32
BLM18BD601SN1D_0603~D
1
4.7U_0603_6.3V6K~D
2
1

C563
0.1U_0402_25V6K~D

C574
0.01U_0402_16V7K~D

C573
0.1U_0402_25V6K~D

1
U38

C566
4.7U_0603_6.3V6K~D

2
C578

C565
0.1U_0402_25V6K~D

1
L44

+PE_VDDH
1

C575
0.1U_0402_25V6K~D

C576
0.1U_0402_25V6K~D

C562
0.1U_0402_25V6K~D

C561
4.7U_0603_6.3V6K~D

L47
1
2
BLM18BD601SN1D_0603~D

C577
4.7U_0603_6.3V6K~D

L45
BLM18PG471SN1D_2P~D
1
2
1

+1.5V_RUN

SD_D1
SD_D2
MMI_D0
MS_D1
MS_D2
MMI_D3
MMI_D4
MMI_D5
MMI_D6
MMI_D7
MS_CD#
SD_CMD/MS_BS
MMI_CLK
SD_CD#
SD_WPI

11
19
18
12
30

1
1
1
1
1

33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D

+3.3V_RUN_CARD

SD/MMCDAT3
SD/MMCDAT4
SD/MMCDAT5
SD/MMCDAT6
SD/MMCDAT7

2 33_0402_5%~D SD/MMCCMD
SD/MMCCLK
2
33_0402_5%~D

OZ600FJ0LN_QFN32_5X5~D

Note: The trace need to route as


daisy-chain and the trace of SD signals
need to route as short as possible

+3.3V_RUN_CARD

JSD1 CONN@

2
1

@ RE678
@RE678
33_0402_5%~D

R826
10K_0402_5%~D

C572
4.7U_0603_6.3V6K~D

SD/MMCCLK

C570
0.1U_0402_25V6K~D

EMI request

SD/MMCCLK
SD/MMCCMD

8
9
10
12

SD/MMCDAT0
SD/MMCDAT1
SD/MMCDAT2
SD/MMCDAT3
SD/MMCDAT4
SD/MMCDAT5
SD/MMCDAT6
SD/MMCDAT7

4
3
15
14
13
11
7
5

SDWP
SD/MMCCD#

1
2

SD/MMCCD#

16
17

@CE757
@
CE757
10P_0402_50V8J~D

SDWP

18
19
20
6

CLK/SD-5
VCC/VDD/SD-4
VSS1/SD-3
CMD/SD-2
DAT0/SD-7
DAT1/SD-8
DAT2/SD-9
DAT3/SD-1
DAT4/MMC-10
DAT5/MMC-11
DAT6/MMC-12
DAT7/MMC-13
WP SW/SD
CD SW/SD
GND SW
CD SW
WP SW
CD&WP/SW/GND
CD&WP/SW/GND
GND/VSS2/SD6

GND1
GND2

21
22

T-SOL_156-3000000901~D

only for MMC/SD


4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
C

Card Reader OZ600FJ0


Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
E

34

of

66

+3.3V_PCIE_WWAN
1
@ R693

2
100K_0402_5%~D
2
R1157
2
R1158

<7,12,13,14,15,28> DDR_XDP_WAN_SMBCLK
<7,12,13,14,15,28> DDR_XDP_WAN_SMBDAT

1
0_0402_5%~D
1
0_0402_5%~D

<40> WLAN_RADIO_DIS#

+3.3V_ALW_PCH

2
0_0402_5%~D
1

PCIE_MCARD1_DET# 1
R692

WLAN_RADIO_DIS#_R

D31
RB751S40T1_SOD523-2~D

USB_MCARD1_DET#
1
@ R698

WWAN_SMBDAT

+3.3V_WLAN

<40> HW_GPS_DISABLE2#

GND2

2
R719
1

+-9%

1000

750

+3.3Vaux

+-9%

330

250

+1.5V

+-5%

500

375

UIM_VPP
UIM_DATA

WIMAX_LED#

WLAN_LED#

DMN66D0LDW-7_SOT363-6~D

WIRELESS_LED#

Q124B
DMN66D0LDW-7_SOT363-6~D

+3.3V_PCIE_FLASH
USB_MCARD3_DET#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1
R710

2 PCIE_MCARD3_DET#
0_0402_5%~D

1
@R708
@
R708

+1.5V_RUN
LPC_LFRAME# <14,33,40,41>
LPC_LAD3 <14,33,40,41>
LPC_LAD2 <14,33,40,41>
LPC_LAD1 <14,33,40,41>
LPC_LAD0 <14,33,40,41>

LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

2 PCH_PLTRST#_EC
0_0402_5%~D

USBP6USBP6+
USB_MCARD3_DET#

USBP6- <17>
USBP6+ <17>

2
@ R712

just reserve

1
100K_0402_5%~D

+3.3V_ALW_PCH

WPAN Noise
USB_MCARD3_DET#

54

TYCO_1775861-1~D

C626
4.7U_0603_6.3V6K~D

C625
0.1U_0402_25V6K~D

C624
0.1U_0402_25V6K~D

C623
0.047U_0402_16V4Z~D

C622
0.047U_0402_16V4Z~D

UIM_DATA

C608
4.7U_0603_6.3V6K~D

Normal

@ C621
0.1U_0402_25V6K~D

SRV05-4.TCT_SOT23-6~D

+3.3V_PCIE_FLASH
CONN@
JMINI3
1 1
2
3 3
Normal
4
5 5
6
7 7
8
9 9
10
CLK_PCIE_MINI3#
11 11
<15> CLK_PCIE_MINI3#
12
CLK_PCIE_MINI3
13 13
250 (Wake enable)
<15> CLK_PCIE_MINI3
14
15
5 (Not wake enable)
15
16
PCH_PLTRST#_EC
17 17
18
PCLK_80H
19 19
<15>
PCLK_80H
20
21
NA
21
22
PCIE_PRX_WPANTX_N5
23 23
24
<15> PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
25 25
26
<15> PCIE_PRX_WPANTX_P5
27
27
28
C617
0.1U_0402_10V7K~D
29 29
30
PCIE_PTX_WPANRX_N5_C
1
2
31
<15> PCIE_PTX_WPANRX_N5
31
32
PCIE_PTX_WPANRX_P5_C
1
2
33
<15> PCIE_PTX_WPANRX_P5
33
34
C618
0.1U_0402_10V7K~D
35 35
36
PCIE_MCARD3_DET#
37 37
<18> PCIE_MCARD3_DET#
38
39 39
40
1
2
41 41
+3.3V_RUN
42
R711
100K_0402_5%~D
43 43
44
45 45
46
47 47
48
49
49
50
51 51
52
+1.5V_RUN
+3.3V_PCIE_FLASH
53
GND1 GND2

C620
0.047U_0402_16V4Z~D

C607
0.1U_0402_25V6K~D

+3.3V

Peak

@ C631
33P_0402_50V8J~D

PCIE_WAKE#
COEX2_WLAN_ACTIVE
1
2
R709
0_0402_5%~D
MINI3CLK_REQ#
<15> MINI3CLK_REQ#

+SIM_PWR

@ C630
33P_0402_50V8J~D

@ C629
33P_0402_50V8J~D

@ C628
33P_0402_50V8J~D

+3.3V_WLAN

Aux Power

C619
0.047U_0402_16V4Z~D

UIM_CLK

C606
0.1U_0402_25V6K~D

Voltage
Tolerance

Primary Power

54

WIRELESS_LED# <40,44>

UIM_VPP

C605
0.047U_0402_16V4Z~D

PWR
Rail

@ U40

C604
0.047U_0402_16V4Z~D

C616
1U_0402_6.3V6K~D

GND
VPP
I/O
NC
GND
GND
MOLEX_475531001
CONN@

@ C603
0.1U_0402_25V6K~D

5
6
7
8
9
10

VCC
RST
CLK
NC

GND2

<41>

1/2 Minicard Pink Pather/60GHz Card H=4

JSIM1
1
2
3
4

GND1

MSDATA

WIMAX_LED# STUDY FOR DEBUG

Q77
SSM3K7002FU_SC70-3~D

+SIM_PWR

UIM_RESET
UIM_CLK

53

+3.3V_WLAN
C602
0.047U_0402_16V4Z~D

MSDATA
2
0_0402_5%~D

1
@ R706

Q124A
S

@ C1176
330U_D2E_6.3VM_R25~D

C615
330U_D2E_6.3VM_R25~D

C614
33P_0402_50V8J~D

C613
22U_0805_6.3V6M~D

LED_WWAN_OUT#

SIM Card Push-Push

UIM_RESET

+1.5V_RUN

2 PCIE_MCARD2_DET#
0_0402_5%~D

2
0_0402_5%~D

USBP4- <17>
USBP4+ <17>
USB_MCARD1_DET# <14,18>

USB_MCARD2_DET# 1
@ R697
+3.3V_PCIE_WWAN

<15> PCH_CL_CLK1
<15> PCH_CL_DATA1
1
<15> PCH_CL_RST1#
R707

USBP4USBP4+
USB_MCARD1_DET#
WIMAX_LED#
WLAN_LED#

TYCO_1775861-1~D

TYCO_1775861-1~D

C612
33P_0402_50V8J~D

C611
0.047U_0402_16V4Z~D

C610
0.047U_0402_16V4Z~D

1
@ C600
33P_0402_50V8J~D

check

54

+3.3V_PCIE_WWAN

USBP5<17>
USBP5+
<17>
USB_MCARD2_DET# <18>

C601
0.047U_0402_16V4Z~D

GND1

COEX2_WLAN_ACTIVE

USBP5USBP5+
USB_MCARD2_DET#
LED_WWAN_OUT#

C594
0.047U_0402_16V4Z~D

C593
33P_0402_50V8J~D

53

0.1U_0402_10V7K~D
2 PCIE_PTX_WLANRX_N2_C
2 PCIE_PTX_WLANRX_P2_C
0.1U_0402_10V7K~D
PCIE_MCARD1_DET#

<18> PCIE_MCARD1_DET#
WWAN_SMBCLK
WWAN_SMBDAT

100K_0402_5%~D

C596
1
1
C598

<15> PCIE_PTX_WLANRX_N2
<15> PCIE_PTX_WLANRX_P2

+1.5V_RUN

WWAN_RADIO_DIS# <40>
2
PCH_PLTRST#_EC <17,33,36,40,41>
0_0402_5%~D

1
R704

C595 4700P_0402_25V7K~D
HOST_DEBUG_TX <41>

0.1U_0402_10V7K~D
2 PCIE_PTX_WANRX_N1_C
2 PCIE_PTX_WANRX_P1_C
0.1U_0402_10V7K~D
2 PCIE_MCARD2_DET#_R
0_0402_5%~D

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2

<15> PCIE_PRX_WLANTX_N2
<15> PCIE_PRX_WLANTX_P2

2
100K_0402_5%~D
2
100K_0402_5%~D

WLAN_RADIO_DIS#_R
2
1 PCH_PLTRST#_EC
R703
0_0402_5%~D

C597
1
<15> PCIE_PTX_WANRX_N1
1
<15> PCIE_PTX_WANRX_P1
C599
<17> PCIE_MCARD2_DET# R7251

<41> HOST_DEBUG_RX
<41> MSCLK

R705

<15> PCIE_PRX_WANTX_N1
<15> PCIE_PRX_WANTX_P1

+1.5V_RUN
+SIM_PWR

UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

1
MSDATA

PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1

<15> MINI2CLK_REQ#
<15> CLK_PCIE_MINI2#
<15> CLK_PCIE_MINI2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

PCIE_MCARD1_DET# 1
@ R699
USB_MCARD1_DET#
1
R701

100K_0402_5%~D

CLK_PCIE_MINI1#
CLK_PCIE_MINI1

<15> CLK_PCIE_MINI1#
<15> CLK_PCIE_MINI1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

MINI1CLK_REQ#

<15> MINI1CLK_REQ#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

<42> COEX2_WLAN_ACTIVE
<42> COEX1_BT_ACTIVE

+3.3V_PCIE_WWAN

+1.5V_RUN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

R718

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

CONN@
JMINI1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

+3.3V_PCIE_WWAN

PCIE_WAKE#
1
2
R7001
20_0402_5%~D
R702
0_0402_5%~D

<29,36,41> PCIE_WAKE#
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE

+3.3V_RUN

2 PCIE_MCARD1_DET#
0_0402_5%~D

+3.3V_WLAN
CONN@
JMINI2

Mini WWAN/GPS/LTE H=5.2

2
100K_0402_5%~D

Mini WLAN/WIMAX H=4

WWAN_SMBCLK

100K_0402_5%~D

PCIE_MCARD2_DET#_R 1
R695

+3.3V_PCIE_WWAN

@ R1160
2.2K_0402_5%~D

@ R1159
2.2K_0402_5%~D

1
100K_0402_5%~D

+3.3V_RUN
USB_MCARD2_DET# 2
R694

@ C627
4700P_0402_25V7K~D
A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

Mini Card
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

35

of

66

Express Card PWR S/W

Power Control for Mini card2


+3.3V_ALW
Q38
+3.3V_WLAN
SI3456DDV-T1-GE3_TSOP6~D

+PWR_SRC_S

+3.3V_ALW

+1.5V_RUN

+3.3V_SUS

+3.3V_RUN

+3.3V_CARDAUX

+1.5V_CARD

+3.3V_CARD

G
3

1
2

2
3

1
2
6
1

U41
17
2
12

1
R734
1
@R717
@
R717

<11,16,28,40,43,56> SIO_SLP_S3#
<28,40,43,56,64> RUN_ON
<17,33,35,40,41> PCH_PLTRST#_EC

2
0_0402_5%~D
2
0_0402_5%~D

20
1
6
19

EXPRCRD_STBY_R#

4
5
13
14
16

+3.3V_RUN
+3.3V_CARD
+1.5V_CARD
+1.5V_RUN

R716
100K_0402_5%~D

AUXIN
3.3VIN
1.5VIN

AUXOUT
3.3VOUT
1.5VOUT

SHDN#
STBY#
SYSRST#
OC#

PERST#
CPPE#
CPUSB#

NC
NC
NC
NC
NC

RCLKEN
GND
PAD

C638
10U_0603_6.3V6M~D

C637
0.1U_0402_25V6K~D

C641
10U_0603_6.3V6M~D

C640
0.1U_0402_25V6K~D

C643
10U_0603_6.3V6M~D

C642
0.1U_0402_25V6K~D

C633
0.1U_0402_25V6K~D

C634
0.1U_0402_25V6K~D

1
R715
20K_0402_5%~D

C635
0.1U_0402_25V6K~D

<40> AUX_EN_WOWL

C632
4700P_0402_25V7K~D

6
5
2
1

R1620
1M_0402_5%~D

Q39A
DMN66D0LDW-7_SOT363-6~D

R714
DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D
Q39B

R713
100K_0402_5%~D
5

15
3
11
8
10
9

CARD_RESET#
EXPRCRD_CPPE#
CPUSB#

18
7
21

TPS2231MRGPR-2_QFN20_4X4~D

Power Control for Mini card1


D

1
G

2
0_0402_5%~D

1
@R727
@
R727
1 1

2
0_0402_5%~D
2 2

<17> USBP10-

<17> USBP10+

4
L49

Power Control for Mini card3

2
R730
20K_0402_5%~D

3
1
2

CARD_SMBCLK
CARD_SMBDAT

CARD_RESET#

1
2
3

1
2
6
1

C649
0.1U_0402_25V6K~D

<29,35,41> PCIE_WAKE#

+3.3V_CARDAUX

C646
0.1U_0402_25V6K~D

<40> MCARD_MISC_PWREN

6
5
2
1

C650
4700P_0402_25V7K~D

CONN@
JEXP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

+3.3V_CARD

R1628
1M_0402_5%~D

Q43A
DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D
R729
Q43B
100K_0402_5%~D

R728
100K_0402_5%~D
5

USBP10_DUSBP10_D+
CPUSB#

<41> CARD_SMBCLK
<41> CARD_SMBDAT

Q42
+3.3V_PCIE_FLASH
SI3456DDV-T1-GE3_TSOP6~D

DLW21SN900SQ2L_0805_4P~D

+3.3V_ALW
+PWR_SRC_S

1
1
@R724
@
R724

1
2

1
2
3

1
2
6
1
2

MCARD_WWAN_PWREN#

<15> EXPCLK_REQ#

EXPRCRD_CPPE#

<15> CLK_PCIE_EXP#
<15> CLK_PCIE_EXP
<15> PCIE_PRX_EXPTX_N3
<15> PCIE_PRX_EXPTX_P3
<15> PCIE_PTX_EXPRX_N3
<15> PCIE_PTX_EXPRX_P3

C647
1
1
C648

C645
0.1U_0402_25V6K~D

2
G
S

+3.3V_ALW

+1.5V_CARD

R732
2.2K_0402_5%~D

+3.3V_SUS

R731
2.2K_0402_5%~D

Express Card Conn.

R723
1K_0402_1%~D

SSM3K7002FU_SC70-3~D
Q73

R726
100K_0402_5%~D

C644
4700P_0402_25V7K~D

<40> MCARD_WWAN_PWREN

6
5
2
1

R1625
1M_0402_5%~D

R722
DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D
Q41B

R721
100K_0402_5%~D
MCARD_WWAN_PWREN# 5

Q41A
DMN66D0LDW-7_SOT363-6~D

Q40
SI3456DDV-T1-GE3_TSOP6~D

+PWR_SRC_S

+3.3V_ALW

Note: Add connection on pin4, pin5, pin 13


and pin14 to support GMT 2nd source part

+3.3V_PCIE_WWAN
+3.3V_ALW

0.1U_0402_10V7K~D
2 PCIE_PTX_EXPRX_N3_C
2 PCIE_PTX_EXPRX_P3_C
0.1U_0402_10V7K~D

GND1
USB_DUSB_D+
CPUSB#
RESERVED
RESERVED
SMB_CLK
SMB_DAT
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PER_N0
PER_P0
GND
PET_N0
PET_P0
GND

27
28
29
30

GND
GND
GND
GND
T-SOL_5421005002000-9_NR

R733
100K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

PCIE-SATA SW / PCIE PWR


Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

36

of

66

D79

USB3RP2

USB3RN2_D-

10

USB3RN2_D-

USB3RP2_D+

USB3RP2_D+

USB3TN2_D-

USB3TN2_D-

USB3TP2_D+

USB3TP2_D+

USB3RP2_D+

DLW21SN900HQ2L_0805_4P~D
1
2
@ R1608
0_0402_5%~D

+5V_USB_CHG_PWR

USB3RN2_D-

JUSB2
USB3TP2_D+

1
@ R1609

2
0_0402_5%~D

2
8

IP4292CZ10-TB_XSON10U10~D
L98

<17>

USB3TN2
USB3TP2

2
C410

USB3TN2_C
1
0.01U_0402_16V7K~D

2
C411

USB3TP2_C
1
0.01U_0402_16V7K~D

L52

USB3TN2_D-

USB3TP2_D+

<17>

USBP1+

USBP1_D+

<17>

USBP1-

USBP1_D-

<17>

DLW21SN900HQ2L_0805_4P~D
1
2
@ R1612
0_0402_5%~D

DLW21SN900SQ2L_0805_4P~D
1
2
@ R737
0_0402_5%~D

1
@ R1607

1
@ R739

2
0_0402_5%~D

USBP1_D+
USB3RP2_D+
D73
PESD5V0U2BT_SOT23-3~D

USB3TN2_DUSBP1_D-

USB3RP2

C655
0.1U_0402_25V6K~D

<17>

USB3RN2

USB3RN2

L97
<17>

USB3RN2_D-

9
1
8
2
7
3
6
4
5

SSTX+
VBUS
SSTXDGND
D+
SSRX+
GND
SSRX-

GND
GND
GND
GND

10
11
12
13

SANTA_370300-1

2
0_0402_5%~D

+SATA_SIDE_PWR
+5V_ALW

SLG55584AVTR_TDFN8_2X2

PWRSHARE_EN#
D

<40> ESATA_USB_PWR_EN#
PWRSHARE_EN#

USB_OC1#

<17>

USB_OC0#

<17>

R748
24.9K_0402_1%~D

TPS2560DRCR-PG1.1_SON10_3X3~D
2

2
R816
100K_0402_5%~D

PWRSHARE_EN
USBP0_DUSBP0_D+
SEL
+5V_ALW

1
2
3
4
9

10
9
8
7
6
11

GND FAULT1#
IN
OUT1
IN
OUT2
EN1#
ILIM
EN2# FAULT#2
T-PAD

Q48
SSM3K7002FU_SC70-3~D

2
R1614
G
10K_0402_5%~D
1

2
B

CEN
DM
DP
SELCDP
Thermal Pad

1
2
3
4
5

C715
0.1U_0402_25V6K~D

+5V_ALW

CB
TDM
TDP
VDD

8
7
6
5

USBP0USBP0+

SB#
<17>
<17>

2
0_0402_5%~D

1
R1626

C675
0.1U_0402_25V6K~D

U2
<40> USB_PWR_SHR_EN#

+5V_USB_CHG_PWR

U48
C676
10U_0805_10V6K~D

2
0_0402_5%~D

+5V_ALW
1
R784

<40> USB_PWR_SHR_VBUS_EN

@ R1613
10K_0402_5%~D

D78

USB3RP1

USB3RN1_D-

10

USB3RN1_D-

USB3RP1_D+

USB3RP1_D+

USB3TN1_D-

USB3TN1_D-

USB3TP1_D+

USB3TP1_D+

USB3RP1_D+

DLW21SN900HQ2L_0805_4P~D
1
2
@ R1605
0_0402_5%~D

+5V_USB_CHG_PWR

USB3RN1_D-

JUSB1
USB3TP1_D+

1
@ R1604

2
0_0402_5%~D

2
8

USB3TN1_DUSBP0_R_D-

IP4292CZ10-TB_XSON10U10~D
L96

<17>

USB3TN1
USB3TP1

2
C412

1 USB3TN1_C
0.01U_0402_16V7K~D

2
C413

1 USB3TP1_C
0.01U_0402_16V7K~D

L51
3

USB3TN1_D-

USBP0_D+

USB3TP1_D+

USBP0_D-

USBP0_R_D+

USBP0_R_D-

<17>

DLW21SN900HQ2L_0805_4P~D
1
2
@ R1606
0_0402_5%~D

DLW21SN900SQ2L_0805_4P~D
1
2
@ R736
0_0402_5%~D

1
@ R1603

1
@ R740

2
0_0402_5%~D

USBP0_R_D+
USB3RP1_D+
D72
PESD5V0U2BT_SOT23-3~D

C654
0.1U_0402_25V6K~D

USB3RP1

C651
150U_B2_6.3V-M~D

<17>

USB3RN1

USB3RN1

L95
<17>

USB3RN1_D-

9
1
8
2
7
3
6
4
5

SSTX+
VBUS
SSTXDGND
D+
SSRX+
GND
SSRX-

GND
GND
GND
GND

10
11
12
13

SANTA_370300-1

DELL CONFIDENTIAL/PROPRIETARY

2
0_0402_5%~D

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

USB x2
Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

37

of

66

ESATA Repeater

+3.3V_RUN

+3.3V_RUN_U44

<14> ESATA_PRX_DTX_P4_C

2
2

1
2

1
2

1
2

R743
0_0402_5%~D

<14> ESATA_PRX_DTX_N4_C

@ R742
0_0402_5%~D

<14> ESATA_PTX_DRX_N4_C

U44
7
17
19
18

ESATA_PTX_DRX_P4
0.01U_0402_16V7K~D
1 ESATA_PTX_DRX_N4
0.01U_0402_16V7K~D
1 ESATA_PRX_DTX_N4
0.01U_0402_16V7K~D
1 ESATA_PRX_DTX_P4
0.01U_0402_16V7K~D

R1594
0_0402_5%~D

ESATA_PTX_DRX_P4_C
C663
ESATA_PTX_DRX_N4_C
C664
ESATA_PRX_DTX_N4_C
C665
ESATA_PRX_DTX_P4_C
C666

<14> ESATA_PTX_DRX_P4_C

2
0_0402_5%~D

R1595
0_0402_5%~D

1
R741

C662
0.1U_0402_25V6K~D

2
+3.3V_RUN_U44
D

C661
0.01U_0402_16V7K~D

PJP9
PAD-OPEN1x1m
1
2

1
2
4
5
3
13
21

EN
VCC
NC_GND_VDD
VCC
NC_GND_VDD
PREXT/NC/VDD
NC_GND_VDDNC/GND/VDD
A_INp
A_INn
B_OUTn
B_OUTp
GND
GND
GND

A_PRE
B_PRE
A_OUTp
A_OUTn
B_INp
B_INn

6
16
20
10
9
8

REXT
ESATA_PE1
ESATA_PE2

15
14

ESATA_PTX_DRX_P4_RP
ESATA_PTX_DRX_N4_RP

11
12

ESATA_PRX_DTX_P4_RP
ESATA_PRX_DTX_N4_RP

PS8513BTQFN20GTR-A0_TQFN20_4X4

+SATA_SIDE_PWR

C668
0.1U_0402_25V6K~D

C667
150U_B2_6.3V-M~D

JESA1
USBP2_DUSBP2_D+

1
2
3
4

VBUS
DD+
GND

USB

ESATA_PTX_DRX_P4_RP
1
C671
ESATA_PTX_DRX_N4_RP
1
C672
ESATA_PRX_DTX_N4_RP
1
C673
ESATA_PRX_DTX_P4_RP
1
C674

USBP2-

1
4

2
3

USBP2_D+

USBP2_D-

DLW21SN900SQ2L_0805_4P~D
1
2
@ R1150
0_0402_5%~D
1
@ R1151

<17>

USBP2+

L90
<17>

2 SATA_PTX_DRX_P4
0.01U_0402_16V7K~D
2 SATA_PTX_DRX_N4
0.01U_0402_16V7K~D
2 SATA_PRX_DTX_N4
0.01U_0402_16V7K~D
2 SATA_PRX_DTX_P4
0.01U_0402_16V7K~D

2
0_0402_5%~D

5
6
7
8
9
10
11

GND
A+
ESATA
AGND
BB+
GND

12
13
14
15

GND
GND
GND
GND

D74
TYCO_2129156-3

PESD5V0U2BT_SOT23-3~D
1

CONN@

Place D74 close to JESATA1

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

USB/ESATA/IO/MDC
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

38

of

66

CONN@
JDOCK1

DPD_DOCK_LANE_P1
DPD_DOCK_LANE_N1

C692
C685

2
2

1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D

DPD_DOCK_LANE_P2
DPD_DOCK_LANE_N2

C687
C689

2
2

1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D

DPD_DOCK_LANE_P3
DPD_DOCK_LANE_N3
DPD_DOCK_AUX
DPD_DOCK_AUX#

<27> DPD_DOCK_AUX
<27> DPD_DOCK_AUX#
B

DPD_GPU_HPD

<45> DPD_GPU_HPD

BLUE_DOCK

<25> BLUE_DOCK

RED_DOCK

<25> RED_DOCK

GREEN_DOCK

<25> GREEN_DOCK
<25> HSYNC_DOCK
<25> VSYNC_DOCK

DPD_GPU_HPD

<41> CLK_MSE
<41> DAT_MSE
1

<30> DAI_BCLK#
<30> DAI_LRCK#
R757
100K_0402_5%~D

<30> DAI_DI
<30> DAI_DO#
<30> DAI_12MHZ#

<40>
<40>

D_LAD0
D_LAD1

<40>
<40>

D_LAD2
D_LAD3

<40> D_LFRAME#
<40> D_CLKRUN#
<40> D_SERIRQ
<40> D_DLDRQ1#
<17> CLK_PCI_DOCK
<41> DOCK_SMB_CLK
<41> DOCK_SMB_DAT
<40,63> DOCK_SMB_ALERT#
<53> DOCK_PSID
<41> DOCK_PWR_BTN#
SLICE_BAT_PRES#

<40,63> SLICE_BAT_PRES#

3
1

153
154
155
156
157
158

GND1
PWR1
PWR1
PWR1
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G

PWR2
PWR2
PWR2
GND2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G

DPC_DOCK_LANE_P0
DPC_DOCK_LANE_N0

C691 2
C680 2

1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D

DPC_DOCK_LANE_P1
DPC_DOCK_LANE_N1

C682 2
C684 2

1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D

DPC_DOCK_LANE_P2
DPC_DOCK_LANE_N2

C693 2
C686 2

1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D

DPC_DOCK_LANE_P3
DPC_DOCK_LANE_N3

C688 2
C694 2

1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D

DPC_DOCK_AUX
DPC_DOCK_AUX#

DPC_GPU_LANE_P1 <46>
DPC_GPU_LANE_N1 <46>
DPC_GPU_LANE_P2 <46>
DPC_GPU_LANE_N2 <46>
DPC_GPU_LANE_P3 <46>
DPC_GPU_LANE_N3 <46>

DPC_DOCK_AUX <27>
DPC_DOCK_AUX# <27>

DPC_GPU_HPD

DPC_GPU_HPD <45>
ACAV_DOCK_SRC# <63>

DAT_DDC2_DOCK <25>
CLK_DDC2_DOCK <25>
2
SATA_PRX_DKTX_P5
SATA_PRX_DKTX_N5
SATA_PTX_DKRX_P5
SATA_PTX_DKRX_N5

2
C697 2
C698
1
C699 1
C700

1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
2
2 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D

SATA_PRX_DKTX_P5_C <14>
SATA_PRX_DKTX_N5_C <14>
SATA_PTX_DKRX_P5_C <14>
SATA_PTX_DKRX_N5_C <14>

USBP8+ <17>
USBP8- <17>

Close to DOCK
Its for Enhance ESD on dock issue.

DPC_GPU_HPD

CLK_KBD <41>
DAT_KBD <41>

R758
100K_0402_5%~D

USB3RN4 <17>
USB3RP4 <17>
USB3TN4 <17>
USB3TP4 <17>

BREATH_LED# <40,44>
DOCK_LOM_ACTLED_YEL# <32>
DOCK_LOM_TRD0+ <32>
DOCK_LOM_TRD0- <32>
+3.3V_ALW

DOCK_LOM_TRD1+ <32>
DOCK_LOM_TRD1- <32>

+LOM_VCT
1

+LOM_VCT
DOCK_LOM_TRD2+ <32>
DOCK_LOM_TRD2- <32>

DOCK_DET#
@
C701
1U_0402_6.3V6K~D

1
R755

2
100K_0402_5%~D

DOCK_LOM_TRD3+ <32>
DOCK_LOM_TRD3- <32>
DOCK_DCIN_IS+ <62>
DOCK_DCIN_IS- <62>
D32
RB751S40T1_SOD523-2~D
1
2

DOCK_POR_RST# <41>
DOCK_DET_R#

DOCK_DET#

<40>

+DOCK_PWR_BAR

DAI_12MHZ#
JAE_WD2F144WB1

USBP3+ <17>
USBP3- <17>

149
150
151
152
159
160
161
162
163
164

DPC_GPU_LANE_P0 <46>
DPC_GPU_LANE_N0 <46>

C703
0.1U_0603_50V7K~D

C702
0.1U_0603_50V7K~D

2
A

CE6
4.7U_0805_25V6K~D

D33
PESD24VS2UT_SOT23-3~D

+DOCK_PWR_BAR

145
146
147
148

DOCK_AC_OFF <40,63>
DOCK_LOM_SPD100LED_ORG# <32>
DPC_CA_DET <27>

C696
0.033U_0402_16V7K~D

Close to DOCK
Its for Enhance ESD on dock issue.

+NBDOCK_DC_IN_SS

C695
0.033U_0402_16V7K~D

DPC_CA_DET

DPD_DOCK_LANE_P0
DPD_DOCK_LANE_N0

1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D

DOCK_AC_OFF

<46> DPD_GPU_LANE_P3
<46> DPD_GPU_LANE_N3

1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D

2
2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

DAI_BCLK#

@ RE11
@RE11
10_0402_1%~D

CLK_PCI_DOCK
1

<46> DPD_GPU_LANE_P2
<46> DPD_GPU_LANE_N2

2
2

C681
C683

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

@ RE12
10_0402_1%~D

R756
33_0402_5%~D
2

<46> DPD_GPU_LANE_P1
<46> DPD_GPU_LANE_N1

C690
C679

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

<46> DPD_GPU_LANE_P0
<46> DPD_GPU_LANE_N0

DPD_CA_DET

<32> DOCK_LOM_SPD10LED_GRN#
<27> DPD_CA_DET

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

DOCK_DET_1

1
@CE8
@CE8
4.7P_0402_50V8C~D

1
@CE9
@CE9
4.7P_0402_50V8C~D

C704
12P_0402_50V8J~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn

DOCKING CONN
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
1

Sheet

39

of

66

+3.3V_ALW

WWAN_RADIO_DIS#
2
100K_0402_5%~D

1
R776

USB_PWR_SHR_EN#
2
100K_0402_5%~D

1
R768

USB_SIDE_EN#
2
10K_0402_5%~D

<25> CRT_SWITCH
<31> MDC_RST_DIS#
<36> MCARD_MISC_PWREN
<62> PROCHOT_GATE
<39,63> DOCK_SMB_ALERT#
<24> TOUCH_SCREEN_PD#

1
R778

USB_PWR_SHR_VBUS_EN
2
100K_0402_5%~D

1
R762

DOCK_SMB_ALERT#
2
10K_0402_5%~D

1
R775
1
R1582
1
R1583
1
R1154
1
R3

MCARD_PCIE_SATA#
2
100K_0402_5%~D
WIRELESS_ON#/OFF
2
100K_0402_5%~D
SP_TPM_LPC_EN
2
10K_0402_5%~D
LCD_TST
2
100K_0402_5%~D
SYS_LED_MASK#
2
10K_0402_5%~D
DGPU_PWR_EN
2
100K_0402_5%~D
GFX_MEM_VTT_ON
2
100K_0402_5%~D
DP_HDMI_HPD
2
100K_0402_5%~D
CHARGE_EN
2
100K_0402_5%~D

<31> USB_SIDE_EN#
<30> EN_I2S_NB_CODEC#
<33> USH_PWR_STATE#
<63> EN_DOCK_PWR_BAR
<24> PANEL_BKEN_EC
<16,24> ENVDD_PCH
<24> LCD_TST
<53> PSID_DISABLE#
<53,63> PBAT_PRES#
<32>
DOCKED
<39> DOCK_DET#
<30> AUD_NB_MUTE#
<36> MCARD_WWAN_PWREN
<24> LCD_VCC_TEST_EN
<24> CCD_OFF
<30,31> AUD_HP_NB_SENSE
<37> ESATA_USB_PWR_EN#
<63> MODULE_ON
<63> SLICE_BAT_ON
<39,63> SLICE_BAT_PRES#
<53,63> MODULE_BATT_PRES#
<63> CHARGE_MODULE_BATT
<63> CHARGE_PBATT
<63> DEFAULT_OVRDE

<37> USB_PWR_SHR_EN#
<49> GFX_MEM_VTT_ON
<7> CPU_DETECT#
<45,64> DGPU_PWR_EN
<29> MOD_SATA_PCIE#_DET
<45> DP_HDMI_HPD
<29> ZODD_WAKE#
<33> BCM5882_ALERT#
<16> SUSACK#
<25> EDID_SELECT#
<18,64> DGPU_PWROK
<15,49> 3.3V_RUN_GFX_ON
<14,18> SLP_ME_CSW_DEV#
<32> LAN_DISABLE#_R

<44> SYS_LED_MASK#
<18> SIO_EXT_WAKE#
<35,44> WIRELESS_LED#
<37> USB_PWR_SHR_VBUS_EN
<35> WLAN_RADIO_DIS#

+3.3V_ALW

VGA_ID
2
100K_0402_5%~D

1
@ R800

VGA_ID

1
R803

2
100K_0402_5%~D

<31> WIRELESS_ON#/OFF
<42> BT_RADIO_DIS#
<35> WWAN_RADIO_DIS#
<7,16> SYS_PWROK
<23,24,25> DGPU_SELECT#
<58> CPU_VTT_ON
<16> PCH_DPWROK

CRT_SWITCH
MDC_RST_DIS#
MCARD_MISC_PWREN
PROCHOT_GATE
LID_CL_SIO#
DOCK_SMB_ALERT#

B52
A49
B53
A50
B54
A51
B55
A52

USB_SIDE_EN#
EN_I2S_NB_CODEC#
USH_PWR_STATE#
EN_DOCK_PWR_BAR
PANEL_BKEN_EC
ENVDD_PCH
LCD_TST
PSID_DISABLE#
PBAT_PRES#
DOCKED
DOCK_DET#
AUD_NB_MUTE#
MCARD_WWAN_PWREN
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR_EN#

A33
B36
A34
B37
A35
B38
A36
A37
B40
A38
B41
A39
B42
A40
B43
A41
B44

MODULE_ON
SLICE_BAT_ON
SLICE_BAT_PRES#
MODULE_BATT_PRES#
CHARGE_MODULE_BATT
CHARGE_PBATT
DEFAULT_OVRDE

B32
A31
B33
B15
A15
B16
A16

USB_PWR_SHR_EN#
GFX_MEM_VTT_ON
MCARD_PCIE_SATA#
CPU_DETECT#
DGPU_PWR_EN
MOD_SATA_PCIE#_DET
DP_HDMI_HPD
ZODD_WAKE#
BCM5882_ALERT#
EDID_SELECT#
DGPU_PWROK
VGA_ID
3.3V_RUN_GFX_ON
SLP_ME_CSW_DEV#
LAN_DISABLE#_R
CHARGE_EN
SYS_LED_MASK#
DYN_TURB_PWR_ALRT#
R797 1
2 0_0402_5%~D
WIRELESS_LED#
USB_PWR_SHR_VBUS_EN
WLAN_RADIO_DIS#
WIRELESS_ON#/OFF
BT_RADIO_DIS#
WWAN_RADIO_DIS#
SYS_PWROK
DGPU_SELECT#

GPIOB0
GPIOB1
GPOC2
GPOC3
GPOC4
GPOC5
GPOC6/TACH4
GPIOC7
GPIOD0
GPIOC1
GPIOC0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7

A1
B2
A2
B3
A3
B45
A42
B4

GPIOE0/RXD
GPIOE1/TXD
GPIOE2/RTS#
GPIOE3/DSR#
GPIOE4/CTS#
GPIOE5/DTR#
GPIOE6/RI#
GPIOE7/DCD#

A59
B62
A58
B61
A56
B59
A55
B58

GPIOF0
GPIOF1
GPIOF2
GPIOF3/TACH8
GPIOF4/TACH7
GPIOF5
GPIOF6
GPIOF7

B47
A45
B48
A46
B49
A47
B50
A48

B13
A13
A53
B57
B14
A14
B17
2
B18
0_0402_5%~D

CPU_VTT_ON
1
@R802
@
R802

GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7

GPIOG0/TACH5
GPIOG1
GPIOG2
GPIOG3
GPIOG4
GPIOG5
GPIOG6
GPIOG7/TACH6

GPIOI1
GPIOI2/TACH0
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7

UMA

2
0_0402_5%~D

SIO_SLP_LAN#
SIO_SLP_SUS#
MODC_EN
DOCK_HP_DET
DOCK_MIC_DET

GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL6
GPIOL7/PWM5

B60
A57
B64
B68
A9
B1
A18
A44

SUS_ON

B34
B39
B51

HW_GPS_DISABLE2#
BREATH_LED#

A27
A26
B26
B25
A21
B22
A28
B20
A23
A22
B21
A32
B35

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
CLK_PCI_5048
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
CLK_SIO_14M

B29
B28
A25
A24
B23
A19
B24
A20

D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ

BC_INT#
BC_DAT
BC_CLK

A29
B31
A30

BC_INT#_ECE5048
BC_DAT_ECE5048
BC_CLK_ECE5048

PWRGD

A4

RUNPWROK

B56

SP_TPM_LPC_EN

B19

1
R804
+CAP_LDO

LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
14.318MHZ/GPIOM0
CLK32/GPIOM2
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ

GPIOH0
GPIOH1
SYSOPT1/GPIOH2
SYSOPT0/GPIOH3
GPIOH4
GPIOH5
GPIOH6
GPIOH7

OUT65
TEST_PIN

DB Version 0.4
ECE5048-LZY_DQFN132_11X11~D

B46

DOCK_AC_OFF_EC

ME_FWP
MASK_SATA_LED#

GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6

+3.3V_ALW
@ C711
1

<41,62,63>

SIO_SLP_A#
<16,43,57>
0.75V_DDR_VTT_ON <55>
SIO_SLP_S4# <16>
SIO_SLP_S3# <11,16,28,36,43,56>
IMVP_PWRGD <60>
IMVP_VR_ON <60>

LED_SATA_DIAG_OUT#
TEMP_ALERT#_R
RUN_ON

AUX_EN_WOWL <36>
WLAN_LAN_DISB# <32>
SIO_SLP_LAN# <16,32>
SIO_SLP_SUS# <16>
GPIO_PSID_SELECT <53>
MODC_EN
<29>
DOCK_HP_DET <30>
DOCK_MIC_DET <30>
ME_FWP
<14>
MASK_SATA_LED# <44>
1.8V_RUN_PWRGD <56>
LED_SATA_DIAG_OUT# <44>

4
2
1
O
D34 @
RB751S40T1_SOD523-2~D
U47 @
TC7SH08FU_SSOP5~D

DOCK_AC_OFF <39,63>

R770 @
33K_0402_5%~D

TEMP_ALERT# <14,18>

+3.3V_RUN
D_CLKRUN#

SUS_ON

D_SERIRQ

BAT2_LED#
USH_PWR_ON

<43>

BAT1_LED#

<44> trace width 20 mils

BAT2_LED#

<44> trace width 20 mils

2
R777
2
R780
2
R782

1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D

RUN_ON

2
R786

1
100K_0402_5%~D

CPU_VTT_ON

2
R789

1
100K_0402_5%~D

0.75V_DDR_VTT_ON 2
R790
SLICE_BAT_ON
2
R791
SUS_ON
2
R878

1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D

D_DLDRQ1#

HW_GPS_DISABLE2# <35>
BREATH_LED# <39,44>

LPC_LAD0 <14,33,35,41>
LPC_LAD1 <14,33,35,41>
LPC_LAD2 <14,33,35,41>
LPC_LAD3 <14,33,35,41>
LPC_LFRAME# <14,33,35,41>
PCH_PLTRST#_EC <17,33,35,36,41>
CLK_PCI_5048 <17>
CLKRUN# <16,33,41>
LPC_LDRQ0# <14>
LPC_LDRQ1# <14>
IRQ_SERIRQ <14,33,41>
CLK_SIO_14M <15>
EC_32KHZ_ECE5048 <41>

D_LAD0
<39>
D_LAD1
<39>
D_LAD2
<39>
D_LAD3
<39>
D_LFRAME# <39>
D_CLKRUN# <39>
D_DLDRQ1# <39>
D_SERIRQ <39>

BC_INT#_ECE5048 <41>
BC_DAT_ECE5048 <41>
BC_CLK_ECE5048 <41>

RUNPWROK

<7,41>

SP_TPM_LPC_EN <33>

+3.3V_ALW

+CAP_LDO trace width 20 mils


CLK_SIO_14M

1
C714
4.7U_0603_6.3V6K~D

CLK_PCI_5048

@R794
@
R794
10_0402_1%~D

R805
100K_0402_5%~D

@ R795
10_0402_1%~D

LID_CL_SIO#

2
R807

1
LID_CL#
10_0402_1%~D

<31,44>

1
@ C713
4.7P_0402_50V8C~D

ME_FWP PCH has internal 20K PD.


(suspend power rail)

C716
0.047U_0402_16V4Z~D
A

DELL CONFIDENTIAL/PROPRIETARY

ME_FWP

Compal Electronics, Inc.

@ R793
1K_0402_1%~D
2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

PAD~D T117 @

2
1K_0402_1%~D

0.1U_0402_25V6K~D
2

SPI_WP#_SEL <14>

BAT1_LED#

B27
C1

2TEMP_ALERT#
0_0402_5%~D

1
R738
<28,36,43,56,64>

RUN_ON

@ C712
4.7P_0402_50V8C~D

C705
10U_0603_6.3V6M~D

DOCK_AC_OFF_EC <63>

B67
A64
A5
B6
A6
B7
A7
B8

1
R765

A8
B9
B10
A10
B11
A11
B12
A12

VSS
EP

VGA_ID0

B63
A60
A61
B65
A62
B66
A63

ACAV_IN_NB

SIO_SLP_A#
0.75V_DDR_VTT_ON

GPIOK0
GPIOK1/TACH3
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7

CAP_LDO

Discrete

1
C706
0.1U_0402_25V6K~D

B5
A17
B30
A43
A54

U46

ESATA_USB_PWR_EN#
2
100K_0402_5%~D

1
R457
1
R766
1
@ R772
1
R767

1
C707
0.1U_0402_25V6K~D

1
R769

+3.3V_RUN

1
C708
0.1U_0402_10V7K~D

1
R774

1
C709
0.1U_0402_25V6K~D

SLICE_BAT_PRES#
2
100K_0402_5%~D

VCC1
VCC1
VCC1
VCC1
VCC1

1
C710
0.1U_0402_25V6K~D

1
R760

CPU_DETECT#
2
100K_0402_5%~D

+3.3V_ALW
PJP7
PAD-OPEN1x1m
2
1

1
R763

+3.3V_ALW_U46

PROCHOT_GATE
2
100K_0402_5%~D

1
R761

HW_GPS_DISABLE2#
2
100K_0402_5%~D

1
R798

DYN_TURB_PWR_ALRT#
2
10K_0402_5%~D

1
R796

Title

ECE5048
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

40

of

66

+3.3V_ALW

+RTC_CELL

VCCSAPWROK

B
A

O
3

Modify name net

@ C721
1U_0402_6.3V6K~D
1
2

R810
100K_0402_5%~D
U50

5
1.05V_VTTPWRGD

<59> VCCSAPWROK

<58,59> 1.05V_VTTPWRGD

C720
0.1U_0402_25V6K~D
2

1.05V_0.8V_PWROK

1.05V_0.8V_PWROK

<14,60>

POWER_SW_IN#

<22> POWER_SW_IN#

1
R811

TC7SH08FU_SSOP5~D

2
10K_0402_5%~D

POWER_SW#_MB <31,42>

C722
1U_0402_6.3V6K~D

2
+3.3V_ALW_U51

2
1

Y6
32.768KHZ_12.5PF_Q13FC1350000~D

<40> EC_32KHZ_ECE5048

MEC_XTAL2 2
R1068
1
R867

A11
A22
B35
A41
A58
A52
B3
A26

DDR_ON
<55>
HOST_DEBUG_TX <35>
HOST_DEBUG_RX <35>
RUNPWROK
<7,40>
EN_INVPWR <24>
PCH_SATA_MOD_EN# <14>

A61
A62
B62

BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#
VCI_OVRD_IN
VCI_IN3#

PECI
DB Version 0.12

B66

15mil

VR_CAP

NC1
NC2
NC3

+VR_CAP B12

B34
A64
B68

22P_0402_50V8J~D

PECI_VREF
PECI

I2S

1
R870
100K_0402_5%~D

DDR_HVREF_RST_GATE <7>
DYN_TUR_CURRNT_SET#
<62>
CPU1.5V_S3_GATE <11>
MSDATA
<35>
MSCLK
<35>
SIO_A20GATE <18>
PS_ID
<53>

LAT_ON_SW#

FWP#
PROCHOT#_EC

2 1K_0402_1%~D

VOL_MUTE

VOL_UP
2 1K_0402_1%~D
VOL_DOWN
2 1K_0402_1%~D
ME_SUS_PWR_ACK <16>
1.5V_SUS_PWRGD <55>
PM_APWROK <16>
1.05V_A_PWRGD <57>
ALW_PWRGD_3V_5V <54>
DEVICE_DET# <29>
RESET_OUT# <16>

R886 1
R887 1
ME_SUS_PWR_ACK
1.5V_SUS_PWRGD
PM_APWROK
1.05V_A_PWRGD
ALW_PWRGD_3V_5V
DEVICE_DET#
RESET_OUT#
PCH_RSMRST#
AC_PRESENT
SIO_PWRBTN#

VOL_MUTE

<31>

VOL_UP
VOL_DOWN

<31>
<31>

1
@ R1179

1
@ R812

DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
BAY_SMBDAT
BAY_SMBCLK
GPU_SMBDAT
GPU_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
CARD_SMBDAT
CARD_SMBCLK
USH_SMBDAT
USH_SMBCLK

20mA drive pins

I2S_DAT
I2S_CLK
I2S_WS

A59
B63
A60
A63
B67
B1
A1

LAT_ON_SW#
ALWON
VCI_IN1#
POWER_SW_IN#
ACAV_IN
DOCK_PWR_SW#

B51
A48

+PECI_VREF
PECI_EC_R

ALWON

1
<43> RUN_ON_ENABLE#

PECI_EC

43_0402_5%~D

<7>

B17
B27
B28

+1.05V_RUN_VTT
R863 close to
U51& least 250mils
1
2
R862
0_0402_5%~D

1
2
@ C747
4.7P_0402_50V8C~D

LCD_SMBCLK

2
R418
2
R420
2
R838
2
R841

1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D

2
R854
2
R856
2
R1171
2
R1125

1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D

LCD_SMBDAT
DOCK_SMB_DAT

BAY_SMBDAT
BAY_SMBCLK
DYN_TUR_CURRNT_SET#
DEVICE_DET#

+RTC_CELL

DAT_KBD
VCI_IN1#

2
R1156

1
100K_0402_5%~D

1
R869

MSDATA
2
10K_0402_5%~D

1
R876

DDR_ON
2
100K_0402_5%~D

CLK_MSE

1
R880
1
R881
1
R882
1
R883

PCH_ALW_ON
2
100K_0402_5%~D
DOCK_POR_RST#
2
100K_0402_5%~D
EN_INVPWR
2
100K_0402_5%~D
2 1.05V_0.8V_PWROK
10K_0402_5%~D

2
R845
2
R846
2
R851
2
R852

1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D

+3.3V_RUN

1
R872
10K_0402_5%~D

FWP#
<22>

BOARD_ID

Q50
SSM3K7002FU_SC70-3~D

2
G

RESET_OUT#

R871
1K_0402_1%~D

R875
240K_0402_5%~D

@ R879
10K_0402_5%~D

PCH_PWRGD#
D

SYSTEM_ID

C744
4700P_0402_25V7K~D

+5V_RUN
CLK_KBD

C740
4.7U_0603_6.3V6K~D

+3.3V_ALW

REV

BOARD_ID rise time is measured from 5%~68%.


5

1
10K_0402_5%~D

DOCK_SMB_CLK

C737
0.1U_0402_25V6K~D

GPIO024/THSEL_STRAP note
i.THSEL_STRAP =1 (selects thermistor on diode channel 1)
ii.THSEL_STRAP = 0 (selects remote diode on diode channel 1)

C744

+3.3V_ALW_PCH

2
R835

+3.3V_ALW

C742
4700P_0402_25V7K~D

AC_PRESENT

+3.3V_ALW

<22,62,63>

R863

2
G

<54>

ACAV_IN

+3.3V_M

130K 4700p X01


62K 4700p X02
33K 4700p A00
8.2K 4700p
4.3K 4700p
2K 4700p
1K 4700p

@ R885
10_0402_1%~D

2
0_0402_5%~D

RUNPWROK

MEC5055-LZY_DQFN132_11X11~D

HOST_DEBUG_TX
HOST_DEBUG_RX

* 240K 4700p X00


CLK_PCI_MEC

1
R1180

R799
10K_0402_5%~D

BAY_SMBDAT <29,53>
BAY_SMBCLK <29,53>
GPU_SMBDAT <45>
GPU_SMBCLK <45>
CHARGER_SMBDAT <62>
CHARGER_SMBCLK <62>
CARD_SMBDAT <36>
CARD_SMBCLK <36>
USH_SMBDAT <33>
USH_SMBCLK <33>

+3.3V_ALW

Place closely pin A29

DAT_MSE

R875

2
100K_0402_5%~D

DOCK_SMB_DAT <39>
DOCK_SMB_CLK <39>

R893
100K_0402_5%~D

G1
G2
G3
G4
ACES_87153-10411

@ Q47
SSM3K7002FU_SC70-3~D

A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50

1
2

1
2

1
2

2
2 0_0402_5%~D
0_0402_5%~D

2
G

Bat2 = Amber LED


Bat1 = Blue LED

PCH_RSMRST# <42>
AC_PRESENT <16>
SIO_PWRBTN# <16>

@ R850
100K_0402_5%~D

R849
10K_0402_5%~D

1
R853 1
R855

R848
10K_0402_5%~D

JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
MSCLK
MSDATA
HOST_DEB_TX
HOST_DEB_RX

C740 close to U51.B12


R847
10K_0402_5%~D

10
11
12
13
14

R860
10K_0402_5%~D

R861
10K_0402_5%~D

1
2
3
4
5
6
7
8
9
10

R859
10K_0402_5%~D

1
2
3
4
5
6
7
8
9
10

R858
10K_0402_5%~D

R864
49.9_0402_1%~D

CONN@
JDEG2

<7,60,62>

PROCHOT#_EC

1
+3.3V_ALW

H_PROCHOT#

2
10K_0402_5%~D
1

R884 1

least
15mil

+3.3V_ALW

<39>

DDR_HVREF_RST_GATE
DYN_TUR_CURRNT_SET#
CPU1.5V_S3_GATE
MSDATA
MSCLK
SIO_A20GATE
PS_ID

DELL PWR SW INF

XTAL1
XTAL2
GPIO160/32KHZ_OUT

DOCK_PWR_BTN#

+RTC_CELL

B64

GPIO011/nSMI
GPIO061/LPCPD#
LDRQ#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/nEC_SCI

MASTER CLOCK

MEC_XTAL1
MEC_XTAL2_R
1
20_0402_5%~D
0_0402_5%~D

2
10K_0402_5%~D

A6
A27
B29
A28
B30
A29
B31
A30
B32
A31
B33
A32
A33

1
1 R825

+3.3V_RUN

GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA
GPIO006/I2C1B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK
GPIO130/I2C2A_DATA
GPIO131/I2C2A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK

HOST INTERFACE

SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC
IRQ_SERIRQ
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#

B2
A2
B8
B18
A8
B9
A9
A14
B15
A17
B39
A44
B47
A54
B58

SMBUS INTERFACE

VSS[1]
VSS[4]

C743
1

PCH_PCIE_WAKE#
PCIE_WAKE#
BC_CLK_ECE1117
BC_DAT_ECE1117
BC_INT#_ECE1117
BEEP
SIO_SLP_S5#
ACAV_IN_NB

GPIO123/BCM_A_CLK
GPIO122/BCM_A_DAT
GPIO121/BCM_A_INT#
GPIO022/BCM_B_CLK
GPIO023/BCM_B_DAT
GPIO024/BCM_B_INT#
GPIO044/BCM_C_CLK
GPIO043/BCM_C_DAT
GPIO042/BCM_C_INT#
GPIO047/LSBCM_D_CLK
GPIO046/LSBCM_D_DAT
GPIO045/LSBCM_D_INT#
GPIO032/GPTP-IN3/BCM_E_CLK
GPIO31/GPTP-OUT2/BCM_E_DAT
GPIO30/GPTP-IN2/BCM_E_INT#

AGND

MEC_XTAL1
B

SYSTEM_ID
BOARD_ID
DDR_ON
HOST_DEBUG_TX
HOST_DEBUG_RX
RUNPWROK
EN_INVPWR

EP

22P_0402_50V8J~D
MEC_XTAL2

GPIO001/ECSPI_CS1
GPIO002/ECSPI_CS2
GPIO014/GPTP-IN7/HSPI_CS1
GPIO040/GPTP-OUT3/HSPI_CS2
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO026/GPTP-IN1
GPIO027/GPTP-OUT1
GPIO041
GPIO107/nRESET_OUT
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4

BC-LINK
A43
B45
A42
A12
B13
A13
B20
A18
B19
A20
B21
A19
A16
B16
A15

DOCK_PWR_SW#

+1.05V_RUN_VTT

GPIO050/FAN_TACH1
GPIO051/FAN_TACH2
GPIO052/FAN_TACH3
GPIO053/PWM0
GPIO054/PWM1
GPIO055/PWM2
GPIO056/PWM3

VSS_RO

<14,33,40> IRQ_SERIRQ
<17,33,35,36,40> PCH_PLTRST#_EC
<17> CLK_PCI_MEC
<14,33,35,40> LPC_LFRAME#
<14,33,35,40> LPC_LAD0
<14,33,35,40> LPC_LAD1
<14,33,35,40> LPC_LAD2
<14,33,35,40> LPC_LAD3
<16,33,40> CLKRUN#
<18> SIO_EXT_SCI#

A10
B10
B14
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
A55
A57
B61
B65
A46

GENERAL PURPOSE I/O

C1

<14,17> SIO_EXT_SMI#
<18> SIO_RCIN#

C741
1

GPIO145/I2C1K_DATA/JTAG_TDI
GPIO146/I2C1K_CLK/JTAG_TDO
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
JTAG_RST#

@ C733
R819
1U_0402_6.3V6K~D
100K_0402_5%~D
1
2

Q45
SSM3K7002FU_SC70-3~D

<16> PCH_PCIE_WAKE#
<29,35,36> PCIE_WAKE#
<42> BC_CLK_ECE1117
<42> BC_DAT_ECE1117
<42> BC_INT#_ECE1117
<30> BEEP
<16> SIO_SLP_S5#
<40,62,63> ACAV_IN_NB

32 KHz Clock

GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO025/UART_CLK
GPIO120/UART_TX
GPIO124/GPTP-OUT5/UART_RX
VCC_PRWGD
GPIO060/KBRST
GPIO101/ECGP_SCLK
GPIO103/ECGP_MISO
GPIO105/ECGP_MOSI
GPIO102/HSPI_SCLK
GPIO104/HSPI_MISO
GPIO106/HSPI_MOSI
GPIO116/MSDATA
GPIO117/MSCLK
GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2
nFWP
PROCHOT#/PWM4

B54

2
1

PCH_ALW_ON
BIA_PWM_EC

BC_CLK_ECE5048
BC_DAT_ECE5048
BC_INT#_ECE5048
BC_CLK_EMC4022
BC_DAT_EMC4022
BC_INT#_EMC4022

<40> BC_CLK_ECE5048
<40> BC_DAT_ECE5048
<40> BC_INT#_ECE5048
<22> BC_CLK_EMC4022
<22> BC_DAT_EMC4022
<22> BC_INT#_EMC4022

JTAG1 CONN@
@SHORT PADS~D

C735
0.1U_0402_25V6K~D

R836
100_0402_1%~D
@

<43> PCH_ALW_ON
<24> BIA_PWM_EC

R824
10K_0402_5%~D

JTAG_RST#

JTAG_RST# citcuit
close to U51.B57

<22> DOCK_PWR_SW#

FAN PWM & TACH


B22
A21
B23
B24
A23
B25
A24

<39> DOCK_POR_RST#

VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]

VBAT
1 0.1U_0402_25V6K~D
DOCK_POR_RST#

C730
10U_0603_6.3V6M~D

C736 2

C725
0.1U_0402_25V6K~D

+3.3V_ALW

A51
B55
B56
A53
B57

MISC INTERFACE

GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK
GPIO110/PS2_CLK2/GPTP-IN6
GPIO111/PS2_DAT2/GPTP-OUT6
GPIO112/PS2_CLK1A
GPIO113/PS2_DAT1A
GPIO114/PS2_CLK0A
GPIO115/PS2_DAT0A
GPIO154/I2C1C_DATA/PS2_CLK1B
GPIO155/I2C1C_CLK/PS2_DAT1B

JTAG INTERFACE

JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#

C739
0.1U_0402_25V6K~D

A5
B6
A37
B40
A38
B41
A39
B42
B59
A56

C734
1U_0402_6.3V6K~D

PS/2 INTERFACE

SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK

C728
0.1U_0402_25V6K~D

<15> SML1_SMBDATA
<15> SML1_SMBCLK
<42> CLK_TP_SIO
<42> DAT_TP_SIO
<39> CLK_KBD
<39> DAT_KBD
<39> CLK_MSE
<39> DAT_MSE
<53> PBAT_SMBDAT
<53> PBAT_SMBCLK

CHARGER_SMBDAT
2
2.2K_0402_5%~D
CHARGER_SMBCLK
2
2.2K_0402_5%~D

1
R827
1
R828

C726
0.1U_0402_25V6K~D

PBAT_SMBDAT
2
2.2K_0402_5%~D
PBAT_SMBCLK
2
2.2K_0402_5%~D
LPC_LDRQ#_MEC
2
100K_0402_5%~D

1
R818
1
R820
1
@ R823

C731
0.1U_0402_25V6K~D

U51

+RTC_CELL
C729
0.1U_0402_25V6K~D

PJP8
PAD-OPEN1x1m
2
1

C727
0.1U_0402_25V6K~D

BC_DAT_EMC4022
1
100K_0402_5%~D
BC_DAT_ECE5048
2
100K_0402_5%~D
BC_DAT_ECE1117
2
100K_0402_5%~D

+3.3V_ALW

C732
0.1U_0402_25V6K~D

PCIE_WAKE#
2
10K_0402_5%~D

2
R821
1
R814
1
R817

C723
0.1U_0402_25V6K~D

1
R759

B11
B60

R815
0_0402_5%~D
1
2+RTC_CELL_VBAT

+RTC_CELL

+3.3V_ALW

1
@ R843
1
R889
1
R892

VOL_MUTE

2
R1169
VOL_DOWN
2
R1197
VOL_UP
2
R1118

1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D

GPU_SMBDAT
2
R829
GPU_SMBCLK
2
R822

1
4.7K_0402_5%~D
1
4.7K_0402_5%~D

2 RESET_OUT#
8.2K_0402_5%~D
2 CPU1.5V_S3_GATE
100K_0402_5%~D
2 PCH_RSMRST#
10K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY
CHIPSET_ID for BID
function

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

MEC5055
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

41

of

66

+3.3V_TP

BlueTooth

1
2

TP_CLK

1 BLM18AG601SN1D_0603~D

10P_0402_50V8J~D
C749

JTP1

TP_CLK
TP_DATA

+3.3V_TP

PS2_DAT_TS
PS2_CLK_TS

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8

G1
G2

<17> BT_DET#
<35> COEX1_BT_ACTIVE
<33> BT_COEX_STATUS2
<33> BT_PRI_STATUS
<44> BT_ACTIVE
<40> BT_RADIO_DIS#
<35> COEX2_WLAN_ACTIVE

9
10

TYCO_2041070-8
CONN@

<17>
<17>

C748
0.1U_0402_25V6K~D

1
TP_DATA

1 BLM18AG601SN1D_0603~D

L55 2

<41> CLK_TP_SIO

+3.3V_RUN

Touch Pad Conn. Pitch=0.5mm


L54 2

10P_0402_50V8J~D
C750

Touch Pad

C751
10P_0402_50V8J~D

Place close to JTP1

<41> DAT_TP_SIO

C752
10P_0402_50V8J~D

R902
4.7K_0402_5%~D

C755
0.1U_0402_25V6K~D

D37
PESD5V0U2BT_SOT23-3~D

R903
4.7K_0402_5%~D

+3.3V_TP
TP_CLK
TP_DATA

Pin reverse for PT

CONN@
JBT1
D

1
2
3
4
5
6
7
8
9
10
11
12
13
14

BT_COEX_STATUS2
BT_PRI_STATUS

USBP11USBP11+

1
2
3
4
5
6
7
8
9
10
11
12
G1
G2

E&T_3703-E12N-03R

2
0_0603_5%~D

1
@ R1162

2
0_0603_5%~D

2 BT_COEX_STATUS2
1K_0402_1%~D
2 BT_PRI_STATUS
1K_0402_1%~D

1
R1133
1
R1134

+3.3V_RUN
C

1
1
R1161

RSMRST circuit

@ C754
100P_0402_50V8J~D

+3.3V_TP

R904
10K_0402_5%~D

+3.3V_RUN

C753
33P_0402_50V8J~D

+3.3V_ALW

+3.3V_ALW
R1622
10K_0402_5%~D
1
2

+3.3V_ALW

VCC
RESET#

EC SIDE
<41> PCH_RSMRST#

PCH_RSMRST#

RSMRST#

B
A

Power Switch for debug

2
0.1U_0402_25V6K~D

U7
O

GND
3

C289
0.01U_0402_16V7K~D

1
C288
PCH_RSMRST#_Q

U4

@ R1623
0_0402_5%~D
1
2

+5V_ALW

PCH_RSMRST#_Q <14,16>

<31,41> POWER_SW#_MB

TC7SH08FU_SSOP5~D
@ C759
100P_0402_50V8J~D

RT9818A-46GU3_SC70-3~D

@ PWRSW1
@SHORT PADS~D

Place on Bottom

@ LVDS cable
Part Number

Change KB connector to same as JSC1


B

DC020003Y0L

KB Conn. Pitch=1.0mm
+3.3V_ALW

+5V_RUN

1
C756
0.1U_0402_25V6K~D

C758
0.1U_0402_25V6K~D

KB_DET#

+3.3V_ALW
+5V_RUN
<41> BC_INT#_ECE1117
<41> BC_DAT_ECE1117
<41> BC_CLK_ECE1117

KB_DET#
PS2_CLK_TS
PS2_DAT_TS

1
2
3
4
5
6
7
8
9
10
11
12

Place close to JKB1

@ MDC wire set cable

Part Number
NBX0000RP0L

Part Number

Description
FFC 6P H P1 PAD=0.7 87.4MM MB-LED/B 0FD

DC30100BL0L

@MEDIA Board FFC


@ RTC BATT
Part Number

JKB1
<18>

@LED Board FFC

Description
H-CONN SET ZJX MB-LCD
14 WXGA+(-1ch)

Part Number

Part Number

@ FAN

GND
GND

@ Speak

BATT CR2032 3V
220MAH MAXELL

Part Number
DC28A000800

DC02C00180L
Description

FCI_10089709-010010LF~D
CONN@

PK230003Q0L

NBX0000RR0L
Description

FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA

Part Number

Part Number
SP070007V0L

Description

Part Number

SPK PACK ZJX 2.0W 4 OHM FG

DC020014Z10

Description
S SOCKET TYCO 1770551-1
10P H5.9 SMART

@BT wire cable

CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF

Part Number

@ Battery bridge cable


Description

Description
FFC 8P F P0.5
PAD=0.3 136MM
MB-TP/B 0FD

@KB FFC

H-CONN SET 0FD MB-LCD CAM LED 2CHANNEL

@ UMA DC_IN wire cable

DC30100BN0

Part Number

FFC 12P G P.5 PAD.3 75MM MB-VOLUME/B 0FD

@ LVDS cable
Part Number

@ T/P FFC

Description

Description
NBX0000RS0L

GC20323MX00

1
2
3
4
5
6
7
8
9
10

Description
CONN SET 0FD
MDC-RJ11

DC020014Y0L

Description
H-CONN SET 0FD MB-BT

Description
H-CONN SET 0FD M/B-BATTERY 9PIN

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

TP/KB/BT/FAN/RESET
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

42

of

66

DC/DC Interface

+1.5V_RUN Source

+3.3V_ALW_PCH Source
1

1
2

G
4

2
1
1
1
R749

2
3
0_0402_5%~D
4

<28,36,40,56,64> RUN_ON

1
@ R747

2
5
0_0402_5%~D
6
7

CT1

A_ON_3.3V#

2
G

PJP6
1

+5V_ALW

PAD-OPEN 1x3m

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

+5V_ALW_U78
C1198
1U_0603_10V7K~D

VBIAS

12
11
10
9
8

C1196
2

1
1

270P_0402_50V7K~D
@C1197
@
C1197
1
2
270P_0402_50V7K~D

+5V_RUN Source

15
+5V_RUN

SLG59M232VTR
1
1
2
2

C770
4700P_0402_25V7K~D

<11,16,28,36,40,56> SIO_SLP_S3#

R913
20K_0402_5%~D
2

ON1

R910
20K_0402_5%~D

VOUT1
VOUT1

C761
0.1U_0402_25V6K~D

@ R919
20K_0402_5%~D
2

2
3

R916
39_0603_5%~D

Q60
SSM3K7002FU_SC70-3~D

VIN1
VIN1

14
13

1
S

1
G

+3.3V_M_CHG

1
U78
1
2

+3.3V_M

C768
10U_0603_6.3V6M~D

2
1

+3.3V_ALW_U78
C1199
1U_0603_10V7K~D
2
1

+3.3V_M

D
1

6
5
2
1

R1617
1M_0402_5%~D

+3.3V_RUN Source

2
6
1

Q58
SI3456DDV-T1-GE3_TSOP6~D

A_ENABLE
Q57B
DMN66D0LDW-7_SOT363-6~D

Q57A
DMN66D0LDW-7_SOT363-6~D
SIO_SLP_A# 2

C764
0.1U_0402_25V6K~D

+3.3V_ALW

R917
100K_0402_5%~D

<16,40,57> SIO_SLP_A#

R931
20K_0402_5%~D

+3.3V_RUN

+3.3V_ALW2

C773
2200P_0402_50V7K~D

+3.3V_ALW

PAD-OPEN 1x3m
PJP5

+PWR_SRC_S

A_ON_3.3V# 5

+1.05V_RUN

2
R1611
470K_0402_5%~D

C767
4700P_0402_25V7K~D

+3.3V_M Source

R918
100K_0402_5%~D

2
G

1.05V_RUN_ENABLE

Q64

Q53A
DMN66D0LDW-7_SOT363-6~D
2
<40> SUS_ON

R1618
1M_0402_5%~D

Q53B
DMN66D0LDW-7_SOT363-6~D

SUS_ON_3.3V#
C

R914
20K_0402_5%~D
2

SUS_ENABLE

C771
4700P_0402_25V7K~D

+1.05V_M Q63
SI4164DY-T1-GE3_SO8~D
8
1
7
2
R930
6
3
100K_0402_5%~D
5

S
3

+1.05V_RUN Source

1
2

C772
10U_0603_6.3V6M~D

6
5
2
1

R921
20K_0402_5%~D

+PWR_SRC_S

Q54
SI3456DDV-T1-GE3_TSOP6~D +3.3V_SUS

C765
10U_0603_6.3V6M~D

R911
100K_0402_5%~D

R915
100K_0402_5%~D

2
6
2
0_0402_5%~D

2
0_0402_5%~D

1
@ R744

+PWR_SRC_S

+3.3V_ALW2

<28,36,40,56,64> RUN_ON

1
R735

5
4

1
2

RUN_ON_ENABLE#

<41> RUN_ON_ENABLE#

<11,16,28,36,40,56> SIO_SLP_S3#

+3.3V_ALW

G
3

2
3
4

+3.3V_SUS Source

1.5V_RUN_ENABLE

C762
3300P_0402_50V7K~D

R1610
470K_0402_5%~D

R909
100K_0402_5%~D

Q52B
DMN66D0LDW-7_SOT363-6~D

R908
20K_0402_5%~D

Q52A
DMN66D0LDW-7_SOT363-6~D

Q51A
DMN66D0LDW-7_SOT363-6~D
2
<41> PCH_ALW_ON

R1619
1M_0402_5%~D

Q51B
DMN66D0LDW-7_SOT363-6~D

ALW_ON_3.3V#

1
1
2

<20> ALW_ENABLE

ALW_ENABLE

6
5
2
1

R920
100K_0402_5%~D

C769
10U_0603_6.3V6M~D

R905
100K_0402_5%~D

+3.3V_ALW2

6
5
2
1

C760
10U_0603_6.3V6M~D

R907
100K_0402_5%~D

Q59
NTGS4141NT1G_TSOP6~D
+1.5V_RUN
D

+PWR_SRC_S

+3.3V_ALW2

+1.5V_MEM

Q49
+3.3V_ALW_PCH
SI3456DDV-T1-GE3_TSOP6~D

+3.3V_ALW

SSM3K7002FU_SC70-3~D

+PWR_SRC_S

Discharg Circuit
1
2
1

2
G

1
3

1
3

2
1

1
2

1
3

2
G

<7,11> RUN_ON_CPU1.5VS3#

2
G

Q72
SSM3K7002FU_SC70-3~D

R927
22_0603_5%~D

+DDR_CHG

Q71
SSM3K7002FU_SC70-3~D

+0.75V_DDR_VTT

R926
220_0402_5%~D
+1.5V_CPU_VDDQ_CHG

@ Q70
SSM3K7002FU_SC70-3~D

2
G

+1.05V_RUN_CHG

2
G

Q69
SSM3K7002FU_SC70-3~D

+1.5V_CPU_VDDQ

@ R925
39_0402_5%~D

+3.3V_RUN_CHG

2
G

+1.05V_RUN

@ R929
39_0603_5%~D

@ R924
1K_0402_1%~D

@ Q68
SSM3K7002FU_SC70-3~D

+3.3V_RUN

+1.5V_RUN_CHG

RUN_ON_ENABLE#

@ Q67
SSM3K7002FU_SC70-3~D

+5V_RUN_CHG

ALW_ON_3.3V# 2
G

@ Q66
SSM3K7002FU_SC70-3~D

@ Q65
SSM3K7002FU_SC70-3~D

2
G

+1.5V_RUN

@ R923
1K_0402_1%~D

+3.3V_ALWPCH_CHG

+3.3V_SUS_CHG

@ R928
@R928
1K_0402_1%~D
2

@ R922
1K_0402_1%~D

SUS_ON_3.3V#

+5V_RUN

+3.3V_ALW_PCH

+3.3V_SUS

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

POWER CONTROL
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

43

of

66

HDD LED solution for White LED

Battery LED

+3.3V_ALW

Q83B

+5V_ALW
<40> BAT2_LED#

3
2

Q74B
DMN66D0LDW-7_SOT363-6~D
4

R949
4.7K_0402_5%~D
1
2

BAT2_LED#_Q

BATT_WHITE

<31>

BATT_YELLOW

MASK_BASE_LEDS#

<31>
D

Q74A
DMN66D0LDW-7_SOT363-6~D
1
6 2

D59
<14> SATA_ACT#

R932
10K_0402_5%~D
D

DMN66D0LDW-7_SOT363-6~D
4
3

Q75
PDTA114EU_SC70-3~D

R958
4.7K_0402_5%~D
2

BATT_WHITE_LED

<24>

RB751S40T1_SOD523-2~D

<40> MASK_SATA_LED#

BATT_YELLOW_LED

D62
1

<40> LED_SATA_DIAG_OUT#

1
R934

MASK_BASE_LEDS#

2
4.7K_0402_5%~D

SATA_LED

<31>

PANEL_HDD_LED

<24>

RB751S40T1_SOD523-2~D

Q83A
DMN66D0LDW-7_SOT363-6~D
1
6

<40> BAT1_LED#

PANEL_HDD_LED

R953
475_0402_1%~D
1
2

Q81
PDTA114EU_SC70-3~D
1

R951
475_0402_1%~D
1
2

MASK_BASE_LEDS#

Q80A
DMN66D0LDW-7_SOT363-6~D
1
6 2

Q80B
DMN66D0LDW-7_SOT363-6~D
4
3

BAT1_LED#_Q

<24>

1
R938

SYS_LED_MASK#

1
2

Breath LED

+5V_ALW

Q84A
DMN66D0LDW-7_SOT363-6~D
1
6

<39,40> BREATH_LED#

+5V_ALW

LED1
LTW-193ZDS5_WHITE~D
BREATH_WHITE_LED_SNIFF
1
2

BREATH_LED#_Q

1
R957

2
1K_0402_1%~D

R937
100K_0402_5%~D

Place LED1 close to SW1

MASK_BASE_LEDS#

Q78A
DMN66D0LDW-7_SOT363-6~D
1
6
2
Q79
PDTA114EU_SC70-3~D

<35,40> WIRELESS_LED#

Q84B
DMN66D0LDW-7_SOT363-6~D
4
3

WLAN LED solution for White LED

+3.3V_ALW

2
4.7K_0402_5%~D

R955
4.7K_0402_5%~D
2

BREATH_WHITE_LED

<24>

MASK_BASE_LEDS#

Q78B
DMN66D0LDW-7_SOT363-6~D
5
4

<42> BT_ACTIVE

1
R939

2
4.7K_0402_5%~D

WLAN_LED

<31>

R950
100K_0402_5%~D

+3.3V_ALW

@ FD1
1

<40> SYS_LED_MASK#

LID_CL#

<31,40> LID_CL#

SYS_LED_MASK#

LID_CL#

O
A

SYS_LED_MASK#

FIDUCIAL MARK~D

Mask All LEDs (Sniffer Function)


Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened)

@ FD2
1
FIDUCIAL MARK~D

0
1
1

CLIP1
EMI_CLIP

U58

GND
4

CLIP2
EMI_CLIP

TC7SH08FU_SSOP5~D
GND

X
0
1

@ FD3
1

@ H16
H_3P0

@ H17
H_2P3

@ H19
H_3P0x2P0

@ H20
H_2P0N

@ H22
H_3P0

Compal Electronics, Inc.

@ H23
H_2P3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
1

@ H15
H_3P0

@ H14
H_3P0

@ H13
H_3P0

@ H12
H_3P0

@ H10
H_3P3

@ H9
H_3P0

@ H8
H_3P2

@ H7
H_3P0

@ H6
H_3P0

@ H5
H_3P0

@ H4
H_3P3

@ H3
H_3P0

@ H2
H_3P3

@ H1
H_3P3

FIDUCIAL MARK~D

DELL CONFIDENTIAL/PROPRIETARY

FIDUCIAL MARK~D
@ FD4
1

MASK_BASE_LEDS#

LED Circuit Control Table

Fiducial Mark

EMI CLIP

0.1U_0402_25V6K~D
2

C778
1

Title

PAD and Standoff


Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

44

of

66

UV1A

DV2
DPC_GPU_HPD

PEG_CRX_GTX_C_P0
PEG_CRX_GTX_C_N0

PEG_CRX_GTX_P1
PEG_CRX_GTX_N1

CV4
CV3

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_N1

PEG_CRX_GTX_P2
PEG_CRX_GTX_N2

CV5
CV6

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N2

PEG_CRX_GTX_P3
PEG_CRX_GTX_N3

CV7
CV8

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_N3

PEG_CRX_GTX_P4
PEG_CRX_GTX_N4

CV9
CV10

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_N4

PEG_CRX_GTX_P5
PEG_CRX_GTX_N5

CV11
CV12

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_N5

PEG_CRX_GTX_P6
PEG_CRX_GTX_N6

CV14
CV15

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_N6

PEG_CRX_GTX_P7
PEG_CRX_GTX_N7

CV16
CV17

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_N7

PEG_CRX_GTX_P8
PEG_CRX_GTX_N8

CV18
CV19

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_N8

PEG_CRX_GTX_P9
PEG_CRX_GTX_N9

CV20
CV21

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_N9

PEG_CRX_GTX_P10
PEG_CRX_GTX_N10

CV22
CV23

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_N10

PEG_CRX_GTX_P11
PEG_CRX_GTX_N11

CV24
CV25

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_N11

PEG_CRX_GTX_P12
PEG_CRX_GTX_N12

CV26
CV27

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_N12

PEG_CRX_GTX_P13
PEG_CRX_GTX_N13

CV28
CV29

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_N13

PEG_CRX_GTX_P14
PEG_CRX_GTX_N14

CV30
CV31

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_N14

PEG_CRX_GTX_P15
PEG_CRX_GTX_N15

CV32
CV33

2
2

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

PEG_CRX_GTX_C_P15
PEG_CRX_GTX_C_N15

PEG_CRX_GTX_C_P0
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_P15
PEG_CRX_GTX_C_N15

AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_WAKE_N

GPU_CRT_RED
GPU_CRT_GRN
GPU_CRT_BLU

DACA_HSYNC
DACA_VSYNC

AM9
AN9

GPU_CRT_HSYNC
GPU_CRT_VSYNC

GPU_CRT_CLK_DDC_R
GPU_CRT_DAT_DDC_R

I2CB_SCL
I2CB_SDA

R7
R6

I2CB_SCL
I2CB_SDA

I2CC_SCL
I2CC_SDA

R2
R3

I2CS_SCL
I2CS_SDA

T4
T3

CLK

LDDC_CLK_GPU <23>
LDDC_DATA_GPU <23>

GPU_SMBCLK_R
GPU_SMBDAT_R

+CLK_PLLVDD
1

CLK_27M_IN
CLK_27M_OUT
XTALSSIN
1
XTALOUTBUFF
RV12 1
RV16

RV29
2.2K_0402_5%~D

YV1
27MHZ_12PF_X1E000021042600~D
1 IN
OUT 3
2

GND

GND

2
10K_0402_5%~D
2
10K_0402_5%~D

LV8
2
1
+1.05V_PEX_VDD
BLM18PG181SN1D_2P

CLK_27M_OUT
CV35
20P_0402_50V8J~D

CV34
20P_0402_50V8J~D

+3.3V_RUN_GFX

5
B

<17> PLTRST_GPU#

0.1U_0402_10V7K~D
CV87

1
2
<18> DGPU_HOLD_RST#

GPU_CRT_CLK_DDC <25>
GPU_CRT_DAT_DDC <25>

AD7

H1
J4

LV13
2
1
+3.3V_RUN_GFX
BLM18PG300SN1D_2P~D

CV73
22U_0805_6.3V6M~D

CLK_27M_IN

AE8

H3
H2

CV112
4.7U_0603_6.3V6K~D

RV33
100K_0402_5%~D

XTAL_SSIN
XTAL_OUTBUFF

RV10
33_0402_5%~D
2
1
RV14 1
2
33_0402_5%~D

LDDC_CLK_GPU
LDDC_DATA_GPU

AD8

PEX_RST_N
PEX_TERMP

+3.3V_RUN

AG10 +DACA_VDD
AP9 DACA_VREF CV13 1
2 0.01U_0402_16V7K~D
DACA_RSET
AP8
1
2
RV6
124_0402_1%~D

N13M_FCBGA908~D

don't connect to PCH


+3.3V_RUN

AJ12
AP29

GPU_CRT_HSYNC <25>
GPU_CRT_VSYNC <25>

R4
R5

XTAL_IN
XTAL_OUT

2
150_0402_1%~D
2
150_0402_1%~D
2
150_0402_1%~D

CV89
0.1U_0402_10V7K~D

RV18
DGPU_PEX_RST_R
1 0_0402_5%~D
2
2
1
RV15
2.49K_0402_1%~D

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

1
RV3
GPU_CRT_GRN
1
RV4
GPU_CRT_BLU
1
RV5

GPU_CRT_RED <25>
GPU_CRT_GRN <25>
GPU_CRT_BLU <25>

I2CA_SCL
I2CA_SDA

VID_PLLVDD

2
100K_0402_5%~D

Close to GPU

CV88
0.1U_0402_10V7K~D

DGPU_PEX_RST

AJ26
AK26

AJ11

AK9
AL10
AL9

SP_PLLVDD
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

1
RV1

CV86
0.1U_0402_10V7K~D

AL13
AK13
AK12

ENVDD_GPU

DPD_GPU_HPD <39>
DPE_GPU_HPD <26>

CV85
0.1U_0402_10V7K~D

<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#
CLK_REQ#
1
2
+3.3V_RUN_GFX
RV21
10K_0402_5%~D
PEX_TSTCLK_OUT
1
2
@ RV13 200_0402_1%~D PEX_TSTCLK_OUT#

DPC_GPU_HPD <39>

DPD_GPU_HPD
DPE_GPU_HPD

DACA_RED
DACA_GREEN
DACA_BLUE

PLLVDD

RB751V-40GTE-17_SOD323-2~D

FBVREF_ALTV <51,52>
GPU_VID_1
<64>
GPU_HOT# <64>
GPU_VID_6
<64>

DPC_GPU_HPD

DV4
DPE_GPU_HPD

THERMTRIP_VGA# <22>

GPU_CRT_RED

DACA_VDD
DACA_VREF
DACA_RSET

CV111
4.7U_0603_6.3V6K~D

1 0.22U_0402_16V7K~D
1 0.22U_0402_16V7K~D

DP_HDMI_HPD <40>

RB751V-40GTE-17_SOD323-2~D

CV107
1U_0603_10V7K~D

2
2

DPD_GPU_HPD

CV200
0.1U_0402_10V7K~D

CV1
CV2

DV3

CV202
0.1U_0402_10V7K~D

PEG_CRX_GTX_P0
PEG_CRX_GTX_N0

THERMTRIP_VGA#
GPU_GPIO9
FBVREF_ALTV
GPU_VID_1
GPU_HOT#
GPU_VID_6

RB751V-40GTE-17_SOD323-2~D

GPU_VID_5
<64>
GPU_VID_4
<64>
BIA_PWM_GPU <24>
ENVDD_GPU <24>
PANEL_BKEN_DGPU <24>
GPU_VID_2
<64>
GPU_VID_3
<64>

PEG_CRX_GTX_N[0..15]

<6> PEG_CRX_GTX_N[0..15]

GPU_VID_5
GPU_VID_4
BIA_PWM_GPU
ENVDD_GPU
PANEL_BKEN_DGPU
GPU_VID_2
GPU_VID_3

P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1

<6> PEG_CRX_GTX_P[0..15]

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

GPIO

PEG_CRX_GTX_P[0..15]

Part 1 of 7

DACs

PEG_CTX_GRX_N[0..15]

<6> PEG_CTX_GRX_N[0..15]

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

I2C

<6> PEG_CTX_GRX_P[0..15]

AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27

PCI EXPRESS

PEG_CTX_GRX_P[0..15]

PEG_CTX_GRX_P0
PEG_CTX_GRX_N0
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P4
PEG_CTX_GRX_N4
PEG_CTX_GRX_P5
PEG_CTX_GRX_N5
PEG_CTX_GRX_P6
PEG_CTX_GRX_N6
PEG_CTX_GRX_P7
PEG_CTX_GRX_N7
PEG_CTX_GRX_P8
PEG_CTX_GRX_N8
PEG_CTX_GRX_P9
PEG_CTX_GRX_N9
PEG_CTX_GRX_P10
PEG_CTX_GRX_N10
PEG_CTX_GRX_P11
PEG_CTX_GRX_N11
PEG_CTX_GRX_P12
PEG_CTX_GRX_N12
PEG_CTX_GRX_P13
PEG_CTX_GRX_N13
PEG_CTX_GRX_P14
PEG_CTX_GRX_N14
PEG_CTX_GRX_P15
PEG_CTX_GRX_N15

MAX14885EETL has internal 3K pu for


GPU_CRT_CLK_DDC and GPU_CRT_DAT_DDC

+3.3V_RUN_GFX
1
1
@ RV23
1
@ RV24

GPU_CRT_CLK_DDC
2
4.7K_0402_5%~D
GPU_CRT_DAT_DDC
2
4.7K_0402_5%~D

DGPU_PEX_RST

74AHC1G09GW_TSSOP5~D
UV14

1
2
RV30
0_0402_5%~D
@ QV14B
GPU_SMBCLK
4
3

GPU_SMBCLK_R

GPU_SMBDAT_R

DMN66D0LDW-7_SOT363-6~D
DGPU_PWR_EN

GPU_SMBCLK <41>

DGPU_PWR_EN <40,64>

DMN66D0LDW-7_SOT363-6~D
6

GPU_SMBDAT

1
RV104
2
RV27
2
RV28
1
RV102
1
RV103

GPU_HOT#
2
10K_0402_5%~D
I2CB_SCL
1
2.2K_0402_5%~D
I2CB_SDA
1
2.2K_0402_5%~D
GPU_GPIO9
2
10K_0402_5%~D
THERMTRIP_VGA#
2
10K_0402_5%~D
A

GPU_SMBDAT <41>

@ QV14A
1
2
RV26
0_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

N12P PCIE,I2C,DAC,GPIO
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

45

of

66

UV1F
UV1D

AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

DPD_GPU_LANE_P0
DPD_GPU_LANE_N0
DPD_GPU_LANE_P1
DPD_GPU_LANE_N1
DPD_GPU_LANE_P2
DPD_GPU_LANE_N2
DPD_GPU_LANE_P3
DPD_GPU_LANE_N3

AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

TMDSE_GPU_P2
TMDSE_GPU_N2
TMDSE_GPU_P1
TMDSE_GPU_N1
TMDSE_GPU_P0
TMDSE_GPU_N0
TMDSE_GPU_CLK
TMDSE_GPU_CLK#

AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

<39>
<39>
<39>
<39>
<39>
<39>
<39>
<39>

DPC_GPU_LANE_P0
DPC_GPU_LANE_N0
DPC_GPU_LANE_P1
DPC_GPU_LANE_N1
DPC_GPU_LANE_P2
DPC_GPU_LANE_N2
DPC_GPU_LANE_P3
DPC_GPU_LANE_N3

<39>
<39>
<39>
<39>
<39>
<39>
<39>
<39>
<26>
<26>
<26>
<26>
<26>
<26>
<26>
<26>

1
RV35
1
RV36

DPD_GPU_AUX/DDC
2
100K_0402_5%~D
DPD_GPU_AUX#/DDC
2
100K_0402_5%~D

AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1

<27> DPC_GPU_AUX/DDC
<27> DPC_GPU_AUX#/DDC

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

NC

MULTI_STRAP_REF0_GND

IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

THERMDP
THERMDN

L3
J2
J7
J6
J5
J3

J1

+3.3V_RUN_GFX

MULTI_STRAP_REF0_GND 1
RV93

K3

2
40.2K_0402_1%~D

VGA_THERMDP <22>
1

K4
2

VDD_SENSE

10K_0402_5%~D
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

L4

@ CV37
@CV37
100P_0402_50V8J~D
VGA_THERMDN <22>

GPU_VDD_SENSE <64>

Use 16mils trace for sense pin


GND_SENSE

L5

+3.3V_RUN_GFX

GPU_VSS_SENSE <64>

TMDS_E_GPU_DDC
TMDS_E_GPU_DDC#

AK3
AK2
AB3
AB4

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N

TEST

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

SERIAL

AK11 GPU_TESTMODE
AM10 GPU_JTAG_TCK
AM11 GPU_JTAG_TDI
AP12 GPU_JTAG_TDO
AP11 GPU_JTAG_TMS
AN11 GPU_JTAG_TRST#

@ TV2
@ TV3
@ TV4
2

1
RV9

<26> TMDS_E_GPU_DDC
<26> TMDS_E_GPU_DDC#

DPD_GPU_AUX/DDC
DPD_GPU_AUX#/DDC

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N

RV39
+3.3V_RUN_GFX

RV40

???

TMDS_E_GPU_DDC
1.5K_0402_5%~D
TMDS_E_GPU_DDC#
1.5K_0402_5%~D

ROM_SI_GPU
ROM_SO_GPU
ROM_SCLK_GPU

@ RV98
10K_0402_1%~D
1
2

RV54
10K_0402_1%~D
1
2

RV53
34.8K_0402_1%~D
1
2

RV52
4.99K_0402_1%~D
1
2

RV97
34.8K_0402_1%~D
1
2

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU

RV99
20K_0402_1%~D
1
2

@ RV41
4.99K_0402_1%~D
1
2

@ RV60
10K_0402_1%~D
1
2

@ RV59
15K_0402_1%~D
1
2

@ RV58
15K_0402_1%~D
1
2

RV57
34.8K_0402_1%~D
1
2

RV56
34.8K_0402_1%~D
1
2

H6
H5
H7
H4

N13M_FCBGA908~D

@ RV51
45.3K_0402_1%~D
1
2

@ RV50
34.8K_0402_1%~D
1
2

RV49
45.3K_0402_1%~D
1
2

1K_0402_1%~D

ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK

+3.3V_RUN_GFX

@ RV55
4.99K_0402_1%~D
1
2

AF3
AF2

RV8
10K_0402_5%~D

Decive ID change to 0x1056

DPC_GPU_AUX/DDC AG3
DPC_GPU_AUX#/DDC AG2

RV25
10K_0402_5%~D

<27> DPD_GPU_AUX/DDC
<27> DPD_GPU_AUX#/DDC
B

RV11
CEC

DPC_GPU_AUX/DDC
2
100K_0402_5%~D
DPC_GPU_AUX#/DDC
2
100K_0402_5%~D

L2

RV20
10K_0402_5%~D

1
RV38
1
RV37

BUFRST_N

TO MB HDMI

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32

TO DOCKING
C

AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13

TO DOCKING

LCD_BCLK+_GPU
LCD_BCLK-_GPU
LCD_B0+_GPU
LCD_B0-_GPU
LCD_B1+_GPU
LCD_B1-_GPU
LCD_B2+_GPU
LCD_B2-_GPU

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>

AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6

GENERAL

LCD_ACLK+_GPU
LCD_ACLK-_GPU
LCD_A0+_GPU
LCD_A0-_GPU
LCD_A1+_GPU
LCD_A1-_GPU
LCD_A2+_GPU
LCD_A2-_GPU

LVDS/TMDS

<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>

**

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100

Part 6 of 7

GND

AG11
A2
A33
AA13
AA15
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7

Part 4 of 7

GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199

D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11

GND_OPT
GND_OPT

C16
W32

N13M_FCBGA908~D
A

DELL CONFIDENTIAL/PROPRIETARY
Hynix 128Mx16 GDDR5 part stuff RV53=35K
Samsung 128Mx16 GDDR5 part stuff RV53=45K

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

N12P DP, STRAP, GND


Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

46

of

66

UV1E

+1.05V_PEX_VDD
Part 5 of 7

1
2

POWER

H27

1
RV44

2
40.2_0402_1%~D

FB_GND_SENSE
FB_VDDQ_SENSE

IFPC_PLLVDD
IFPC_RSET
IFPC_IOVDD

H25

1
RV43
1
RV126

2
100_0402_1%~D

F1

1
RV125

2
100_0402_1%~D

PEX_PLL_HVDD

AH12

PEX_SVDD_3V3

AG12

AB8
AD6
AC7
AC8

IFPEF_PLLVDD
IFPEF_RSET
IFPE_IOVDD
IFPF_IOVDD

+1.05V_PEX_VDD

+1.5V_MEM_GFX

+1.5V_MEM_GFX

+3.3V_RUN_GFX
1

2
+IFPEF_PLLVDD
IFPEF_RSET
+IFPEF_IOVDD

2
60.4_0402_1%~D

F2

IFPD_PLLVDD
IFPD_RSET
IFPD_IOVDD

CV77
22U_0805_6.3V6M~D

FB_CAL_PU_GND

CV74
22U_0805_6.3V6M~D

2
40.2_0402_1%~D

LV14
BLM18AG121SN1D_0603~D

CV71
22U_0805_6.3V6M~D

1
RV42

+1.05V_PEX_VDD

PLACE NEAR GPU


1

CV67
22U_0805_6.3V6M~D

IFPD_RSET

AG7
AN2
AG6

J27

CV53
10U_0603_6.3V6M~D

AF7
AF8
AF6

FB_CAL_PD_VDDQ

2
+3.3V_RUN_VDD33

CV106
4.7U_0603_6.3V6K~D

+IFPCD_PLLVDD
IFPC_RSET
+IFPCD_IOVDD

J8
K8
L8
M8

CV108
4.7U_0603_6.3V6K~D

+IFPAB_IOVDD

VDD33_0
VDD33_1
VDD33_2
VDD33_3

CV64
0.1U_0402_10V7K~D

CV174
0.1U_0402_10V7K~D

CV166
0.1U_0402_10V7K~D

CV172
1U_0402_6.3V6K~D

CV175
4.7U_0603_6.3V6K~D

CV173
1U_0402_6.3V6K~D

+IFPAB_IOVDD

CV51
10U_0603_6.3V6M~D

LV11
BLM18PG181SN1D_2P
1
2

FB_CAL_TERM_GND

IFPAB_PLLVDD
IFPAB_RSET
IFPA_IOVDD
IFPB_IOVDD

AG26

CV54
10U_0603_6.3V6M~D

+1.8V_RUN_GFX

AH8
AJ8
AG8
AG9

CV204
1U_0402_6.3V6K~D

+IFPAB_PLLVDD
IFPAB_RSET

CV52
10U_0603_6.3V6M~D

CV99
4.7U_0603_6.3V6K~D

CV167
0.1U_0402_10V7K~D

CV168
1U_0603_10V7K~D

CV109
4.7U_0603_6.3V6K~D

2
C

CV169
1U_0402_6.3V6K~D

+IFPAB_PLLVDD

PEX_PLLVDD

AG19
AG21
AG22
AG24
AH21
AH25

CV205
1U_0402_6.3V6K~D

LV10
BLM18AG121SN1D_0603~D
1
2

1
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

PLACE UNDER BGA

CV63
0.1U_0402_10V7K~D

+1.05V_PEX_VDD

CV70
4.7U_0603_6.3V6K~D

CV213
1U_0402_6.3V6K~D

AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28

CV214
1U_0402_6.3V6K~D

CV161
0.1U_0402_10V7K~D

CV116
0.1U_0402_10V7K~D

CV160
0.1U_0402_10V7K~D

CV115
0.1U_0402_10V7K~D

CV127
1U_0402_6.3V6K~D

CV125
1U_0402_6.3V6K~D

CV126
1U_0402_6.3V6K~D

CV124
1U_0402_6.3V6K~D

CV56
4.7U_0603_6.3V6K~D

CV48
4.7U_0603_6.3V6K~D

CV55
4.7U_0603_6.3V6K~D

A/B

CV40
10U_0603_6.3V6M~D

CV79
22U_0805_6.3V6M~D

CV47
4.7U_0603_6.3V6K~D

CV39
10U_0603_6.3V6M~D

CV78
22U_0805_6.3V6M~D

Close to Pin

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13

CV65
4.7U_0603_6.3V6K~D

close to the GPU

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43

CV211
1U_0402_6.3V6K~D

+1.5V_MEM_GFX

CV212
1U_0402_6.3V6K~D

AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27

C/D
N13M_FCBGA908~D
+3.3V_RUN_GFX

+3.3V_RUN_GFX

LV15
MMZ1608R301AT_2P~D
1
2

1
2

CV215
0.1U_0402_10V7K~D

CV197
0.1U_0402_10V7K~D

CV69
0.1U_0402_10V7K~D

CV76
0.1U_0402_10V7K~D

CV68
0.1U_0402_10V7K~D

CV75
1U_0402_6.3V6K~D

CV198
1U_0402_6.3V6K~D

CV170
4.7U_0603_6.3V6K~D

Near Ball

+3.3V_RUN_VDD33
2
0_0603_5%~D
CV123
4.7U_0603_6.3V6K~D

1
RV7

Near GPU

+1.05V_PEX_VDD
LV12
BLM18PG221SN1D_2P~D
1
2

CV193
0.1U_0402_10V7K~D

CV184
0.1U_0402_10V7K~D

+IFPEF_IOVDD
CV183
1U_0603_10V7K~D

CV110
4.7U_0603_6.3V6K~D

CV195
1U_0402_6.3V6K~D

IFPAB_RSET

CV101
0.1U_0402_10V7K~D

CV105
0.1U_0402_10V7K~D

CV104
0.1U_0402_10V7K~D

CV206
0.1U_0402_10V7K~D

CV194
0.1U_0402_10V7K~D

CV122
0.1U_0402_10V7K~D

CV121
0.1U_0402_10V7K~D

CV120
1U_0402_6.3V6K~D

CV119
4.7U_0603_6.3V6K~D

CV118
1U_0402_6.3V6K~D

+IFPCD_IOVDD

CV103
1U_0603_10V7K~D

2
+1.05V_PEX_VDD
LV9
BLM18PG221SN1D_2P~D
1
2

+IFPEF_PLLVDD

CV102
4.7U_0603_6.3V6K~D

+3.3V_RUN_GFX

1
2

E/F

CV100
0.1U_0402_10V7K~D

CV98
0.1U_0402_10V7K~D

CV97
0.1U_0402_10V7K~D

CV96
1U_0603_10V7K~D

+IFPCD_PLLVDD

CV95
4.7U_0603_6.3V6K~D

CV94
4.7U_0603_6.3V6K~D

LV6
MMZ1608R301AT_2P~D
1
2

1 @ RV32 2
1K_0402_1%~D

IFPC_RSET

1 RV45
2
1K_0402_1%~D

DELL CONFIDENTIAL/PROPRIETARY

IFPD_RSET 1
RV47 2
1K_0402_1%~D
IFPEF_RSET

Compal Electronics, Inc.

1 RV48
2
1K_0402_1%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

N12P Power
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

47

of

66

+GPU_CORE
UV1G

Caps on Power Side

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

+GPU_CORE
Part 7 of 7

POWER

AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71

V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22

XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38

U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8

N13M_FCBGA908~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

N12P Power GFX Core


Size

Document Number

Date:

Friday, May 20, 2011

Rev
0.1

LA-7782
Sheet
1

48

of

66

FBA_D[0..63]

FBA_D[0..63] <51,52>
FBA_CMD[0..31] <51,52>

+1.8V_RUN_GFX Source
+1.8V_RUN_GFX
QV7
PMV45EN_SOT23-3~D

<51,52>
D

2
G

D
1
2

1
2

G
3

2
3
4

1
1
2
6
1

3.3V_RUN_GFX_ON#

4
1

+1.05V_M

8
7
6
5

2
G

1
2

QV3
+1.05V_PEX_VDD
SI4164DY-T1-GE3_SO8~D
1
2
3
1

1.05V_RUN_VTT_GFX#_EN

2
G

+1.5V_MEM_GFX

+1.05V_RUN_VTT_GFX Source
+PWR_SRC_S

2
2
G

1
2
3

1
2
6
1
S

2
G

QV1
SI4164DY-T1-GE3_SO8~D
1
2
3

GFX_MEM_VTT_EN

+3.3V_RUN_GFX

2
G

J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

+1.05V_PEX_VDD
1

+1.5V_MEM_GFX

<52>
<52> +1.8V_RUN_GFX

FBA_WCK01 <51>
FBA_WCK01# <51>
FBA_WCK23 <51>
FBA_WCK23# <51>
FBA_WCK45 <52>
FBA_WCK45# <52>
FBA_WCK67 <52>
FBA_WCK67# <52>

<51>
<51>

CLKA1
CLKA1#

8
7
6
5

CV132
2200P_0402_50V7K~D

2
1
RV46
60.4_0402_1%~D
2
1
RV61
60.4_0402_1%~D

CLKA0
CLKA0#

AB31
AC31

1
2
1
2
1

R30
R31

+1.5V_MEM

RV81
470K_0402_5%~D

CV81
0.1U_0402_10V7K~D

CV135
1U_0402_6.3V6K~D

CV199
1U_0402_6.3V6K~D

CV72
22U_0805_6.3V6M~D

+FBA_PLL_AVDD
LV7
BLM18PG300SN1D_2P~D
+FBA_PLL_AVDD
1
2

<40> GFX_MEM_VTT_ON

GFX_MEM_VTT_ON#
+1.05V_PEX_VDD

RV74
20K_0402_5%~D

GFX_MEM_VTT_ON# 5

N13M_FCBGA908~D
A

+PWR_SRC_S

QV4
SSM3K7002FU_SC70-3~D

FBA_DEBUG0
FBA_DEBUG1
THE FBA_ECKBxx ARE
USED ON GK107.
NC FBA_WCKB01
ON GF108 AND GF117 FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N

RV70
20K_0402_5%~D

FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7

K31 FBA_WCK01
L30 FBA_WCK01#
H34 FBA_WCK23
J34 FBA_WCK23#
AG30 FBA_WCK45
AG31 FBA_WCK45#
AJ34 FBA_WCK67
AK34 FBA_WCK67#

CV46
10U_0603_6.3V6M~D

FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N

3.3V_RUN_GFX_EN

RV73
100K_0402_5%~D

+1.5V_MEM_GFX

FBA_CLK1
FBA_CLK1_N

+1.5V_MEM_GFX Source
+3.3V_ALW2

QV13
SSM3K7002FU_SC70-3~D
RV130
39_0402_5%~D
+3.3V_RUN_GFX_CHG

@ CV128
0.01U_0402_16V7K~D

@ RV78

R28
AC28

FB_CLAMP

FBA_DBI0
FBA_DBI1
FBA_DBI2
FBA_DBI3
FBA_DBI4
FBA_DBI5
FBA_DBI6
FBA_DBI7

QV12
RV129
SSM3K7002FU_SC70-3~D
39_0402_5%~D
+1.05V_PEX_VDD_CHG

+FB_VREF

E1

FBA_CLK0
FBA_CLK0_N

FB_DLL_AVDD

QV6A
DMN66D0LDW-7_SOT363-6~D
2
<15,40> 3.3V_RUN_GFX_ON

QV11
RV128
SSM3K7002FU_SC70-3~D
39_0402_5%~D
+1.5V_MEM_GFX_CHG

CV82
0.1U_0402_10V7K~D

16mil

K27

R32
AC32

FBA_PLL_AVDD
FB_VREF

3.3V_RUN_GFX_ON# 5

QV10
RV127
SSM3K7002FU_SC70-3~D
39_0402_5%~D
+1.8V_RUN_GFX_CHG

@RV77
@
RV77

1.1K_0402_1%~D 1.1K_0402_1%~D

1+FBA_PLL_AVDD

FBA_CMD_RFU0
FBA_CMD_RFU1

6
5
2
1

RV91
100K_0402_5%~D

CV45
10U_0603_6.3V6M~D

H26

M31
G31
E33
M33
AE31
AK30
AN33
AF33

QV5
+3.3V_RUN_GFX
SI3456DDV-T1-GE3_TSOP6~D

CV129
2200P_0402_50V7K~D

+FB_VREF

RV92
100K_0402_5%~D

M30
H30
E34
M34
AF30
AK31
AM34
AF32

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

+3.3V_ALW

RV80
470K_0402_5%~D

+1.5V_MEM_GFX

U27

+PWR_SRC_S
+3.3V_ALW2

QV2B
DMN66D0LDW-7_SOT363-6~D

+FBA_PLL_AVDD

for Test/Debug

+3.3V_RUN_GFX Source

QV2A
DMN66D0LDW-7_SOT363-6~D

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

RAS#
CAS#
WE#
CS#
ABI#
A0_A10
A1_A9
A2_BA0
A3_BA3
A4_BA2
A5_BA1
A6_A11
A7_A8
A12_FRU
CKE#
RESET#

RV69
100K_0402_5%~D

RV72
10K_0402_5%~D

RST_L*

P30
F31
F34
M32
AD31
AL29
AM32
AF34

CMD28
CMD31
CMD21
CMD16
CMD24
CMD26
CMD27
CMD18
CMD17
CMD19
CMD20
CMD23
CMD22
CMD25
CMD30
CMD29

Memory

RV67
100K_0402_5%~D

FBA_CMD13

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

CMD12
CMD15
CMD5
CMD0
CMD8
CMD10
CMD11
CMD2
CMD1
CMD3
CMD4
CMD7
CMD6
CMD9
CMD14
CMD13

2
1
2

RV71
10K_0402_5%~D

RST_H*

<32..63>

2 1.05V_RUN_VTT_GFX#_EN_R
0_0402_5%~D

RV90
20K_0402_5%~D

FBA_CMD29

<0..31>

1.05V_RUN_VTT_GFX#_EN 1
RV95

CV186
3300P_0402_50V7K~D

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

RV94
1M_0402_5%~D

FBA_CMD14

U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31

CV49
10U_0603_6.3V6M~D

CKE_L

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

QV6B
DMN66D0LDW-7_SOT363-6~D

RV68
10K_0402_5%~D

+1.5V_MEM_GFX

Part 2 of 7

FBA_CMD30

FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

CKE_H

L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33

MEMORY INTERFACE
A

1
2

RV66
10K_0402_5%~D

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

RV96
20K_0402_5%~D

GDDR5 CMD Mapping Table

UV1B

CV50
10U_0603_6.3V6M~D

+1.5V_MEM_GFX

FBA_EDC[0..7]

+1.8V_RUN
FBA_EDC[0..7]

<51,52>

FBA_DBI[0..7]

FBA_DBI[0..7]

FBA_CMD[0..31]

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

N12P Memory
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

49

of

66

CHANNEL-B NOT TO USE, NEED TO BE DISABLED


UV1C
D

Part 3 of 7

+FBA_PLL_AVDD
+FBA_PLL_AVDD

+1.5V_MEM_GFX

G14
G20

2
1
RV63
60.4_0402_1%~D
2
1
RV62
60.4_0402_1%~D

H17

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_CMD_RFU0
FBB_CMD_RFU1

D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17

E11
E3
A3
C9
F23
F27
C30
A24
D9
E4
B2
A9
D22
D28
A30
B23
D10
D5
C3
B9
E23
E28
B30
A23
C12
C20
B

FBB_CLK0
FBB_CLK0_N
FBB_PLL_AVDD
FBB_CLK1
FBB_CLK1_N

CV83
0.1U_0402_10V7K~D

FBB_D00
FBB_D01
FBB_D02
FBB_D03
FBB_D04
FBB_D05
FBB_D06
FBB_D07
FBB_D08
FBB_D09
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

MEMORY INTERFACE
B

G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26

FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N

FBB_DEBUG0
FBB_DEBUG1
THE FBA_ECKBxx ARE
FBB_WCKB01
USED ON GK107.
FBB_WCKB01_N
NC ON GF108 AND
FBB_WCKB23
GF117
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N

D12
E12
E20
F20
F8
E8
A5
A6
D24
D25
B27
C27
D6
D7
C6
B6
F26
E26
A26
A27

N13M_FCBGA908~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

Title

N12P Memory (2)


Size

Document Number

Date:

Friday, May 20, 2011

Rev
0.1

LA-7782
Sheet
1

50

of

66

64X32 GDDR5

Memory Partition A - Lower


32
NORMAL
bits

MIRROR

UV5
MF=0

MF=1

MF=1

MF=0

UV4

MF=0

FBA_EDC0

???

FBA_EDC2

MF=1

C2
C13
R13
R2

EDC0
EDC1
EDC2
EDC3

EDC3
EDC2
EDC1
EDC0

D2
D13
P13
P2

DBI0#
DBI1#
DBI2#
DBI3#

DBI3#
DBI2#
DBI1#
DBI0#

FBA_DBI2

<49> CLKA0
<49> CLKA0#

RV105
40.2_0402_1%~D
1
2
1
2
RV106
40.2_0402_1%~D

FBA_CMD9

J5

FBA_CMD6
FBA_CMD7
FBA_CMD4
FBA_CMD3

K4
K5
K10
K11

FBA_CMD1
FBA_CMD2
FBA_CMD11
FBA_CMD10

H10
H11
H5
H4

CLKA0#

A5
U5

CV165
0.01U_0402_16V7K~D

CLKA0

FBA_CMD14

J12
J11
J3

RV17
RV22
RV108

2 1K_0402_1%~D
2 1K_0402_1%~D
2 121_0402_1%~D

1
1
1

J1
FBA_SEN0J10
J13

FBA_CMD8
FBA_CMD12
FBA_CMD0
FBA_CMD15
FBA_CMD5

<49> FBA_WCK01#
<49> FBA_WCK01

549_0402_1%~D
+FBA_VREFC_L

1
<45,52> FBVREF_ALTV

SGRAM GDDR5

QV8
SSM3K7002FU_SC70-3~D

2
G

H5GQ2H24MFR-T2C

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

+FBA_VREFC_L

A10
U10
J14

FBA_CMD13

+1.5V_MEM_GFX

J2

CV151
0.1U_0402_10V7K~D

931_0402_1%
A

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS170-BALL

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

P5
P4

CV155
0.1U_0402_10V7K~D

549_0402_1%~D
RV114
2
1

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

D5
D4

FBA_WCK01#
FBA_WCK01
+FBA_VREFD_L

CV154
0.1U_0402_10V7K~D

931_0402_1%
RV113
2
1

G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

<49> FBA_WCK01#
<49> FBA_WCK01

J4
G3
G12
L3
L12

FBA_WCK23#
FBA_WCK23

CV143
0.1U_0402_10V7K~D

CV208
CV207
820P_0402_50V7K~D
820P_0402_50V7K~D
2
1
2
1
RV110
RV109
1.33K_0402_1%~D 1.33K_0402_1%~D

RESET#

J1
J10
J13

G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14

A8/A7
A11/A6
BA1/A5
BA2/A4

A10/A0
A9/A1
BA3/A3
BA0/A2

BA3/A3
BA0/A2
A9/A1
A10/A0

BA1/A5
BA2/A4
A11/A6
A8/A7

VPP/NC
VPP/NC

FBA_CMD[0..31]

FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31

FBA_D[0..31] <49>

FBA_DBI[0..3]

FBA_DBI[0..3]

FBA_EDC[0..3]

<49>

FBA_EDC[0..3]

<49>

FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15

+1.5V_MEM_GFX

MF
SEN
ZQ
ABI#
RAS#
CS#
CAS#
WE#

CAS#
WE#
RAS#
CS#

WCK01#
WCK01

WCK23#
WCK23

WCK23#
WCK23

WCK01#
WCK01

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VREFD
VREFD
VREFC

RESET#

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS170-BALL
SGRAM GDDR5

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

H5GQ2H24MFR-T2C

FBA_CMD[0..31] <49,52>

FBA_D[0..31]

CV182
0.1U_0402_10V7K~D

VREFD
VREFD
VREFC

A5
U5

A12/RFU/NC

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

CV179
0.1U_0402_10V7K~D

WCK01#
WCK01

J5

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

CV140
0.1U_0402_10V7K~D

WCK23#
WCK23

WCK23#
WCK23

CK
CK#
CKE#

H10
H11
H5
H4

<49> FBA_WCK23#
<49> FBA_WCK23

CV131
1U_0402_6.3V6K~D

WCK01#
WCK01

J12
J11
J3

FBA_CMD4
FBA_CMD3
FBA_CMD7
FBA_CMD6

CV142
0.1U_0402_10V7K~D

RV112
1

CAS#
WE#
RAS#
CS#

DBI3#
DBI2#
DBI1#
DBI0#

K4
K5
K10
K11

FBA_SEN0
2
RV107
121_0402_1%~D
FBA_CMD8
FBA_CMD15
FBA_CMD5
FBA_CMD12
FBA_CMD0

CV141
0.1U_0402_10V7K~D

+1.5V_MEM_GFX

RV111

ABI#
RAS#
CS#
CAS#
WE#

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

DBI0#
DBI1#
DBI2#
DBI3#

FBA_CMD10
FBA_CMD11
FBA_CMD1
FBA_CMD2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

D2
D13
P13
P2

RV19
1K_0402_1%~D
1
2

+1.5V_MEM_GFX

CV130
1U_0402_6.3V6K~D

+FBA_VREFD_L

CV153
0.1U_0402_10V7K~D

J2

MF
SEN
ZQ

EDC3
EDC2
EDC1
EDC0

FBA_CMD9
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23

+1.5V_MEM_GFX

+1.5V_MEM_GFX

CV152
0.1U_0402_10V7K~D

CV177
1U_0402_6.3V6K~D

CV176
1U_0402_6.3V6K~D

CV41
10U_0603_6.3V6M~D

FBA_CMD13

VPP/NC
VPP/NC

CLKA0
CLKA0#
FBA_CMD14

CV188
1U_0402_6.3V6K~D

A10
U10
J14

BA1/A5
BA2/A4
A11/A6
A8/A7

FBA_DBI1

CV178
1U_0402_6.3V6K~D

P5
P4

BA3/A3
BA0/A2
A9/A1
A10/A0

FBA_DBI3

CV42
10U_0603_6.3V6M~D

+FBA_VREFC_L
1

FBA_WCK23#
FBA_WCK23

A10/A0
A9/A1
BA3/A3
BA0/A2

FBA_EDC1

EDC0
EDC1
EDC2
EDC3

CV139
0.1U_0402_10V7K~D

D5
D4

A8/A7
A11/A6
BA1/A5
BA2/A4

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7

C2
C13
R13
R2

CV138
1U_0402_6.3V6K~D

+FBA_VREFD_L
1

FBA_WCK01#
FBA_WCK01

A12/RFU/NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

???

CV137
1U_0402_6.3V6K~D

<49> FBA_WCK23#
<49> FBA_WCK23

J4
G3
G12
L3
L12

CK
CK#
CKE#

FBA_EDC3

MF=0

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

FBA_DBI0

MF=1

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

Title

VRAM A Lower
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

51

of

66

Memory Partition A - Upper MIRROR


32 bits

NORMAL

UV6
MF=0

MF=1

MF=1

MF=0
FBA_CMD[0..31]

UV3

MF=0

FBA_EDC7

???

FBA_EDC5

FBA_DBI7
FBA_DBI5

<49> CLKA1
<49> CLKA1#

RV115
40.2_0402_1%~D
1
2
1

CLKA1

+1.5V_MEM_GFX
RV34
RV118

FBA_CMD20
FBA_CMD19
FBA_CMD23
FBA_CMD22

H10
H11
H5
H4
A5
U5

<49> FBA_WCK67#
<49> FBA_WCK67

J1
FBA_SEN2J10
J13
J4
G3
G12
L3
L12

DBI3#
DBI2#
DBI1#
DBI0#

A12/RFU/NC
A8/A7
A11/A6
BA1/A5
BA2/A4

A10/A0
A9/A1
BA3/A3
BA0/A2

BA3/A3
BA0/A2
A9/A1
A10/A0

BA1/A5
BA2/A4
A11/A6
A8/A7

VPP/NC
VPP/NC

RESET#

<45,51> FBVREF_ALTV

QV9
SSM3K7002FU_SC70-3~D

2
G

BA1/A5
BA2/A4
A11/A6
A8/A7

VPP/NC
VPP/NC

J4
G3
G12
L3
L12

ABI#
RAS#
CS#
CAS#
WE#

CAS#
WE#
RAS#
CS#

WCK01#
WCK01

WCK23#
WCK23

P5
P4

WCK23#
WCK23

WCK01#
WCK01

A10
U10
J14

J2

G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14

FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39

FBA_CMD[0..31] <49,51>

FBA_D[32..63]

FBA_D[32..63] <49>

FBA_DBI[4..7]

FBA_DBI[4..7]

FBA_EDC[4..7]

<49>

FBA_EDC[4..7]

<49>

FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VREFD
VREFD
VREFC

RESET#

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS170-BALL
SGRAM GDDR5

H5GQ2H24MFR-T2C

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.

H5GQ2H24MFR-T2C

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
3

+1.5V_MEM_GFX

D5
D4

+1.5V_MEM_GFX

BA3/A3
BA0/A2
A9/A1
A10/A0

MF
SEN
ZQ

CV156
0.1U_0402_10V7K~D

A10/A0
A9/A1
BA3/A3
BA0/A2

FBA_WCK67#
FBA_WCK67

CV162
0.1U_0402_10V7K~D

SGRAM GDDR5

A8/A7
A11/A6
BA1/A5
BA2/A4

J1
J10
J13

FBA_CMD29

A12/RFU/NC

FBA_WCK45#
FBA_WCK45

CV144
0.1U_0402_10V7K~D

549_0402_1%~D
+FBA_VREFC_H

A5
U5

+FBA_VREFC_H

CV159
0.1U_0402_10V7K~D

931_0402_1%

H10
H11
H5
H4

CV146
0.1U_0402_10V7K~D

549_0402_1%~D
RV124
2
1

FBA_CMD17
FBA_CMD18
FBA_CMD27
FBA_CMD26

+FBA_VREFD_H

CV133
1U_0402_6.3V6K~D

931_0402_1%
RV123
2
1

J5

<49> FBA_WCK67#
<49> FBA_WCK67

CV145
0.1U_0402_10V7K~D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS170-BALL

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

CK
CK#
CKE#

K4
K5
K10
K11

<49> FBA_WCK45#
<49> FBA_WCK45

CV134
1U_0402_6.3V6K~D

RV122
1

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

J12
J11
J3

FBA_CMD22
FBA_CMD23
FBA_CMD20
FBA_CMD19

FBA_SEN2
2
RV117
121_0402_1%~D
FBA_CMD24
FBA_CMD28
FBA_CMD16
FBA_CMD31
FBA_CMD21

CV189
1U_0402_6.3V6K~D

+1.5V_MEM_GFX

RV121
2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DBI3#
DBI2#
DBI1#
DBI0#

FBA_CMD25

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

DBI0#
DBI1#
DBI2#
DBI3#

RV65
1K_0402_1%~D
1
2

CV180
1U_0402_6.3V6K~D

+FBA_VREFD_H

CV158
0.1U_0402_10V7K~D

CV157
0.1U_0402_10V7K~D

CV192
1U_0402_6.3V6K~D

CV191
1U_0402_6.3V6K~D

CV43
10U_0603_6.3V6M~D

FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47

CV44
10U_0603_6.3V6M~D

FBA_DBI6
CLKA1
CLKA1#
FBA_CMD30

D2
D13
P13
P2

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

CV185
0.1U_0402_10V7K~D

VREFD
VREFD
VREFC

+1.5V_MEM_GFX

G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

FBA_DBI4

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

CV181
0.1U_0402_10V7K~D

WCK01#
WCK01

FBA_EDC6

EDC3
EDC2
EDC1
EDC0

CV150
0.1U_0402_10V7K~D

WCK23#
WCK23

+FBA_VREFC_H
1

FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

EDC0
EDC1
EDC2
EDC3

CV147
0.1U_0402_10V7K~D

WCK23#
WCK23

P5
P4

J2

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

C2
C13
R13
R2

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CV148
1U_0402_6.3V6K~D

WCK01#
WCK01

FBA_WCK45#
FBA_WCK45

FBA_CMD29

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CAS#
WE#
RAS#
CS#

D5
D4

A10
U10
J14

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

???

+1.5V_MEM_GFX

MF
SEN
ZQ
ABI#
RAS#
CS#
CAS#
WE#

FBA_EDC4

MF=0

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

EDC3
EDC2
EDC1
EDC0

FBA_WCK67#
FBA_WCK67

+FBA_VREFD_H

CV210
CV209
820P_0402_50V7K~D
820P_0402_50V7K~D
2
1
2
1
RV120
RV119
1.33K_0402_1%~D 1.33K_0402_1%~D

MF=1

CV149
1U_0402_6.3V6K~D

<49> FBA_WCK45#
<49> FBA_WCK45

CK
CK#
CKE#

J5

FBA_CMD24
FBA_CMD31
FBA_CMD21
FBA_CMD28
FBA_CMD16

J12
J11
J3

K4
K5
K10
K11

2 1K_0402_1%~D
2 121_0402_1%~D

1
1

DBI0#
DBI1#
DBI2#
DBI3#

FBA_CMD26
FBA_CMD27
FBA_CMD17
FBA_CMD18

RV64
1K_0402_1%~D
1
2

EDC0
EDC1
EDC2
EDC3

D2
D13
P13
P2

FBA_CMD25

CLKA1#

CV190
0.01U_0402_16V7K~D

2
RV116
40.2_0402_1%~D

FBA_CMD30

C2
C13
R13
R2

MF=1

Title

VRAM A Upper
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

52

of

66

+COINCELL

ESD Diodes

1
PL1
FBMJ4516HS720NT_2P~D
1
2

GND
GND

BAY_SMBCLK
BAY_SMBDAT

<29,41>
<29,41>

7
8

PAD-OPEN 1x2m~D

JRTC1

Z4012

MPBATT+

1
2

+COINCELL

1 G
2 G

3
4
D

TYCO_2-1775293-2~D

PR5
100_0402_5%~D
1
2

Z5304
Z5305
Z5306

PR4
100_0402_5%~D
1
2

PJP1

+RTC_CELL
MODULE_BATT_PRES#

<40,63>
PD4

1
2
3
4
5
6

PC1
0.1U_0603_25V7K~D
2
1

PC2
2200P_0402_50V7K~D
2
1

1
2
3
4
5
6

PR3
100_0402_5%~D
1
2

PR1
1K_0402_5%~D

+3.3V_RTC_LDO

PR2
100K_0402_5%~D
2
1

@
2

MBATT+_C
MBATT1

+3.3V_ALW

1
2

Media Bay Battery Connector

@
PD2
PESD24VS2UT_SOT23-3~D

COIN RTC Battery


@
PD1
PESD24VS2UT_SOT23-3~D

RB715FGT106_UMD3

SUYIN_150010GR006M500ZR

PC3
1U_0603_10V4Z~D

ESD Diodes
PL2
FBMJ4516HS720NT_2P~D
1
2

@
PD6
PESD24VS2UT_SOT23-3~D

PL3
FBMJ4516HS720NT_2P~D
1
2

PR7
100_0402_5%~D
1
2

Z4304
Z4305
Z4306

PR9
100_0402_5%~D
1
2

PR8
100_0402_5%~D
1
2

PBAT_SMBCLK
PBAT_SMBDAT

PC4
0.1U_0603_25V7K~D
2
1

PC5
2200P_0402_50V7K~D
2
1

11
10
9
8
7
6
5
4
3
2
1

<41>
<41>

PJP2
2

PBATT+

PAD-OPEN 1x3m

PR6
100K_0402_5%~D
2
1

@
1

PBATT+_C
GND
GND
9
8
7
6
5
4
3
2
1

+3.3V_ALW

@
PD5
PESD24VS2UT_SOT23-3~D

Primary Battery Connector

GND

PBAT_PRES#

<40,63>

PBATT1
SUYIN_200275MR009G50PZR

GND

+3.3V_ALW

PR13
33_0402_5%~D
1
2

NO

2
NB_PSID_TS5A63157

IN

GND

PQ2
FDV301N_G_NL_SOT23-3~D

V+

NC

COM

GPIO_PSID_SELECT

+5V_ALW

PS_ID

PQ3
MMST3904-7-F_SOT323~D
E

PR17
1

PSID_DISABLE#

<40>

10K_0402_5%~D

+PWR_SRC_S

+PWR_SRC

1VSB_N_003

PR25
0_0402_5%
2VSB_N_002
1

PC17
.1U_0402_16V7K

+3.3V_ALW

1
2

PC15
10U_1206_25V6M~D

PR22
100K_0402_5%~D
2
1

<63>

PC14
0.1U_0603_25V7K~D
2
1

SOFT_START_GC

PC12
0.1U_0603_25V7K~D
2
1

1M_0402_5%~D

PL6
FBMA-L18-453215-900LMA90T_1812~D
1
2

10K_0402_5%~D

PC11
0.1U_0603_25V7K~D
2
1

1M_0402_5%~D

PR20
2

PC10
0.022U_0805_50V7K~D
1
2

1
PR26

PR24
1

+DCIN_JACK

@
2

@ PR23
4.7K_0805_5%~D
2
1

-DCIN_JACK

1
2
2

PC8
0.22U_0603_25V7K

PQ4
TP0610K-T1-E3_SOT23-3

VSB_N_001

PQ6
SSM3K7002FU_SC70-3

2
G

DELL CONFIDENTIAL/PROPRIETARY
PC18
0.1U_0603_25V7K~D
2
1

PC13
0.1U_0603_25V7K~D
2
1

1
MOLEX_87438-0743
7
7
6
6
5
5
4
4
3
3
2
2
1
1
PJPDC1

PD13
VZ0603M260APT_0603
PC16
0.1U_0603_25V7K~D
2
1

PR21
22K_0402_1%
1
2

2
1
PR19
100K_0402_1%

PQ5
FDS6679AZ_G_SO8~D
1
8
S
D
2
7
S
D
3
6
S
D
4
5
G
D

3
+DC_IN_SS

PC9
0.1U_0603_25V7K

+DC_IN

+DC_IN

<41>

TS5A63157DCKR_SC70-6~D

DC_IN+ Source

PL5
FBMA-L18-453215-900LMA90T_1812~D
1
2

<40>

+5V_ALW

2
B

PR16
15K_0402_1%~D
1
2

2
G

PR14
100K_0402_1%~D
1
2

PU1
1

<39> DOCK_PSID

PR15
10K_0402_1%~D

PL4
BLM18BD102SN1D_0603~D
2
1

NB_PSID

PR12
2.2K_0402_5%~D
1
2

PR11
1
2
0_0402_5%~D

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

www.vinafix.vn
3

+DCIN
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

53

of

66

2VREF_6182

PJP100
1

PR101
13K_0402_1%
1

PC101
1U_0603_16V6K

PR102
30.9K_0402_1%
2

PAD-OPEN 1x3m

+DC1_PWR_SRC

+PWR_SRC
@ PL100
1UH_PCMB053T-1R0MS_7A_20%
2
1

FB_3V

FB_5V 1

PR104
20K_0402_1%
2

+DC1_PWR_SRC

VO1

PC118
10U_0805_25V6K
2
1

PC106
10U_0805_25V6K
2
1

PC105
2200P_0402_50V7K
2
1

PC104
0.1U_0402_25V6
2
1

2
FB1

REF

VO2

24

PQ101
FDMC8884_POWER33-8-5

1
2
3

ENTRIP1

P PAD

PR106
86.6K_0402_1%
ENTRIP1
1
2

TONSEL

25
2

PC107
10U_0805_6.3V6M

PU100

FB2

PQ100
FDMC8884_POWER33-8-5

PR105
143K_0402_1%~D
1
2 ENTRIP2

ENTRIP2

PR100
0_0402_5%
1
2

PC119
10U_0805_25V6K
2
1

PC103
10U_0805_25V6K
2
1

+3.3V_ALW2
PC102
2200P_0402_50V7K
2
1

PC100
0.1U_0402_25V6
2
1

PR103
20K_0402_1%
1
2

+3.3V_RTC_LDO

3
2
1

1
2
1
2

ENTRIP1

ALW_PWRGD_3V_5V <41>

5VALWP
TDC 9.044A
Peak Current 12.874A
OCP current 15.5A

DMN66D0LDW-7 2N_SOT363-6~D
1

PJP101
1
PR114

100K_0402_1%
1
2

<22> THERM_STP#

PR115
2K_0402_1%~D
1
2

2
PAD-OPEN 1x3m
PJP102

+5V_ALW2

+5V_ALWP

+5V_ALW

PAD-OPEN 1x3m
PJP103

PQ105
PDTC115EU_SOT323-3

+3.3V_ALWP

+3.3V_ALW

PAD-OPEN 1x3m
PJP104

PR116
0_0402_5%
1
2

ALWON

PC116
0.1U_0603_25V7K

PQ104A
5

+
2

PR112
100K_0402_1%

3
PQ104B
DMN66D0LDW-7 2N_SOT363-6~D

1
2

+DC1_PWR_SRC

+3.3V_ALW

PC114
4.7U_0805_10V6K

PC113
680P_0603_50V7K

PQ103
FDMC7692S_POWER33-8-5

SNUB_5V

@
4

PD100
PR113
MMSZ5229BS_SOD323~D 499K_0402_1%~D
1
2
2
1

2VREF_6182

<41>

3
2
1

+5V_ALWP

PC111
220U_D_6.3VM_R25M

LG_5V

18

17

16

EN

14

13

19

PL102
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
1
2

+PWR_SRC
ENTRIP2

LX_5V

+5V_ALW2

3.3VALWP
TDC 4.729A
Peak Current 6.756A
OCP current 8.107A

20

RT8205LZQW(2) WQFN 24P PWM

PC115
1U_0603_10V6K
2
1

PR111
300K_0402_1%

SNUB_3V

21

PR110
4.7_1206_5%
2
1

LGATE1

22

BST_5V 1 PR108 2
2.2_0603_5%
UG_5V

PC109
0.22U_0603_16V7K
BST1_5V 1
2

LGATE2

23

NC

PHASE1

VREG5

PHASE2

VIN

UGATE1

GND

12

BOOT1

UGATE2

15

LG_3V

PGOOD

BOOT2

11

VREG3

1
2
3

UG_3V 10

PQ102
FDMC8878_POWER33-8-5

PC112
680P_0603_50V7K

BST_3V

LX_3V
5

PR109
4.7_1206_5%

PC110
220U_D_6.3VM_R25M

+3.3V_ALWP

PL101
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
1
2

SKIPSEL

PC108
0.22U_0603_16V7K
BST1_3V 1 PR107 2
1
2
2.2_0603_5%

PC117
1U_0603_10V6K
2
1

PAD-OPEN 1x3m

Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

www.vinafix.vn
C

+5V_ALW/+3.3V_ALW
Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
E

54

of

66

0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A

1.5Volt +/- 5%
TDC 9.74A
Peak Current 13.915A
OCP current 16.698A
+PWR_SRC

PJP200

1.5V_B+

PJP204
PR200
1
2
2.2_0603_5%~D

PAD-OPEN 1x2m~D

BOOT_1.5V

VLDOIN_1.5V

+1.5V_MEN_P

CS

GND

VTTREF

VDDQ

Level
L
L
H

+0.75V_P
off
off
on

+V_DDR_REF
off
on
on

S3

FB

PC211
0.033U_0402_16V7~D

@ PR207
0_0402_5%~D
2
1

1.5V_SUS_PW RGD

PR205
1M_0402_1%~D
1
2

PR209
0_0402_5%~D

S5_1.5V

Mode
S5
S3
S0

+1.5V_MEN_P

PR204
100K_0402_1%~D

1.5V_B+

+V_DDR_REF

+V_DDR_REF

+5V_ALW

S5

+3.3V_ALW 1U_0603_10V6K~D

VDD

TON

11

VDDP

PC210

<41> 1.5V_SUS_PW RGD


PR206
0_0402_5%~D
1
2

PC206
10U_0805_6.3V6M~D

VTTSNS

VTT

20

19

18
BOOT

21
1

RT8207MZQW _W QFN20_3X3

PGOOD

VDD_1.5V

12

10

VLDOIN

13

UGATE

PGND

PC207
1U_0603_10V6K~D

+5V_ALW

17

16
14

PAD

VTTGND

CS_1.5V

PR202
5.1_0603_5%~D

PHASE
LGATE

PC213
@ 0.1U_0402_16V7K~D

<41> DDR_ON

15

PU200

PC205
10U_0805_6.3V6M~D

0.22U_0603_16V7K~D

2
1

PR201
5.1K_0402_1%~D
1
2

PQ201
SIR818DP-T1-GE3_POWERPAK8-5
1
2
3
5

PR203
4.7_1206_5%

0.1U_0603_25V7K~D

@ PC209
1

1SNUB_1.5V

DL_1.5V

PC208
330U_SX_2VY~D

@ PC214
330U_SX_2VY~D

PL200
1UH 20% FDUE1040D-H-1R0M=P3_21.3A_20%~D
1
2

+0.75V_P

SW _1.5V

+1.5V_MEN_P

PC204

PQ200
SIR472DP-T1-GE3_POWERPAK8-5~D
1
2
3
5

1
2

PC203
2200P_0402_50V7K~D

1
2

PC202
0.1U_0402_25V6K~D

PC201
4.7U_0805_25V6K~D

PC200
4.7U_0805_25V6K~D

PAD-OPEN1x1m
DH_1.5V

PC212
@ 0.1U_0402_16V7K~D

S3_1.5V

PR208
0_0402_5%~D
1
2

<40> 0.75V_DDR_VTT_ON

Note: S3 - sleep ; S5 - power off

+1.5V_MEN_P
PJP201

JUMP_1x3m
PJP203

+1.5V_MEN_P

PJP202

+1.5V_MEM

+0.75V_P

+0.75V_DDR_VTT

JUMP_1x3m
PAD-OPEN1x1m

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

www.vinafix.vn
3

+1.5V_MEN/+0.75V_DDR_VTT
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

55

of

66

PR300

10K_0402_5%~D
1.8V_RUN_PWRGD <40>

PC306
47P_0402_50V8J~D

1
2

PC303
22U_0805_6.3VAM

1
2

SNUB_1.8VSP

PC302
22U_0805_6.3VAM

NC
7

11
1

PR305
10K_0402_1%

PR306 0_0402_5%

SYN470DBC_DFN10_3X3

PC305
680P_0603_50V7K

<11,16,28,36,40,43> SIO_SLP_S3#

@PR304
@
PR304
47K_0402_5%

@PR303
@
PR303 0_0402_5%

PC304
0.1U_0402_10V7K

EN_1.8VSP
1

<28,36,40,43,64> RUN_ON

PR302
20K_0402_1%

PC301
22P_0402_50V8J
2
1

1.8VSP_FB

FB

EN

+1.8V_RUNP

SVIN

LX

LX

1.8VSP_LX

PR301
4.7_0805_5%~D

PVIN

NC

PC307
0.1U_0603_25V7K~D

PVIN

PC300
22U_0805_6.3VAM

PAD-OPEN 1x2m~D

10

PG

1.8VSP_VIN

TP

PL301
1UH_PH041H-1R0MS_3.8A_20%
1
2

PU300
PJP301

+3.3V_ALW

1.8Volt +/-5%
TDC 0.85A
Peak Current 1.215A
OCP current 1.458A

+3.3V_RUN

<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR64/PR67)=0.6*(1+20K/10K)=1.8V

PJP300

+1.8V_RUNP

+1.8V_RUN

PAD-OPEN 1x2m~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.8V_RUN
Size

www.vinafix.vn

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
D

56

of

66

PJP400
+V1.05SP_B+

+PWR_SRC

PC400
4.7U_0805_25V6K

1
2

PR400
100K_0402_1%~D
2
1

3
2
1
DRVH

UG_+V1.05SP

SW

SW_+V1.05SP

VFB

V5IN

RF

DRVL

EN

FB_+V1.05SP

RF_+V1.05SP

PL400
1UH_FDVE0630-H-1R0M-P3_11.9A_20%~D
1
2

+1.05V_MP

TRIP

EN_+V1.05SP

PC406
220U_D2_4VM

+5V_ALW

LG_+V1.05SP

PC405
1U_0603_6.3V6M

@PR404
@
PR404
4.7_1206_5%

4
PQ401
FDMC7692S_POWER33-8-5

3
2
1

TPS51212DSCR_SON10_3X3

TP

11

10

PQ400
FDMC8884_POWER33-8-5

BST_+V1.05SP

VBST

PGOOD

TRIP_+V1.05SP

S0 mode be high level


@
PC407
0.1U_0402_16V7K

PC404
0.1U_0603_25V7K
1
2

PU400
1

PR403
0_0402_5%
1
2

<16,40,43> SIO_SLP_A#

4
PR401
2.2_0603_5%
1
2

<41> 1.05V_A_PWRGD
PR402
60.4K_0402_1%
1
2

PC403
4.7U_0805_25V6K
2
1

+3.3V_ALW
D

PC402
2200P_0402_50V7K
2
1

PC401
0.1U_0402_25V6
2
1

PAD-OPEN 1x2m~D

PR405
470K_0402_1%

1
+
2
C

@PC408
@
PC408

1000P_0603_50V7K

PR406

4.99K_0402_1%
2
1

+1.05Volt +/- 5%
TDC 4.7A
Peak Current 6.5A
OCP current 7.8A

PJP401
PR407
10K_0402_1%

PAD-OPEN 1x2m~D

+1.05V_MP

PJP402
2

+1.05V_M

PAD-OPEN 1x2m~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.05V_M
Size

www.vinafix.vn

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

57

of

66

PJP500
+V1.05S_VCCPP_B+

+PWR_SRC

PR502
2.2_0603_5%
1
2

<41,59> 1.05V_VTTPWRGD

PC504
0.1U_0603_25V7K
1
2

1
2

PC500
4.7U_0805_25V6K

PQ500
FDMC8884_POWER33-8-5

PC503
4.7U_0805_25V6K
2
1

PR500
100K_0402_5%

PC501
0.1U_0402_25V6
2
1

+3.3V_RUN

PC502
2200P_0402_50V7K
2
1

PAD-OPEN 1x2m~D

PU500

SW_+V1.05S_VCCPP

VFB

V5IN

RF

DRVL

FB_+V1.05S_VCCPP

RF_+V1.05S_VCCPP

PL500
1UH_FDVE0630-H-1R0M-P3_11.9A_20%~D
1
2

+1.05VTTP

+5V_ALW

LG_+V1.05S_VCCPP

PC505
1U_0603_6.3V6M

@ PR504
4.7_1206_5%
2

TPS51212DSCR_SON10_3X3

1
PR505
470K_0402_1%

+
2
C

@ PC508
1000P_0603_50V7K

3
2
1

PQ501
FDMC7692S_POWER33-8-5

@
PC510
.1U_0402_16V7K

11

PC507
220U_D2_4VM

EN

UG_+V1.05S_VCCPP

SW

TRIP

3
2
1

DRVH

TP
2

@ PC506
0.1U_0402_16V7K

10

<40> CPU_VTT_ON

BST_+V1.05S_VCCPP

VBST

PGOOD

EN_+V1.05S_VCCPP

PR503
0_0402_5%
1
2

PR501
84.5K_0402_1%~D
1
2 TRIP_+V1.05S_VCCPP

Local sense put on HW site


PR507
4.32K_0402_1%
2
1

PR508
0_0402_5%
2
1

VTT_SENSE_FB

VTT_SENSE

PR513
0_0402_5%
2
1

VSSIO_SENSE_R <10>

VSSIO_SENSE_R_FB

<10>

+3.3V_RUN

PR509
71.5K_0402_1%
B

VCCP_PWRCTRL = "High" ,
VCCP_PWRCTRL = "Low" ,

PR510
10K_0402_1%

Vo = 1.05V (SNB)
Vo = 1V (IVB)

PR511
10K_0402_5%
1
1

2
G

VCCP_PWRCTRL <11>

PC509
.01U_0402_16V7K~D
2
1

PQ502
1
2

@PR514
@
PR514
10_0402_1%~D

SSM3K7002FU_SC70-3

+1.05Volt +/- 2%
TDC 6A
Peak Current 8.5A
OCP current 10.2A

From GPIO

PJP501
2

PAD-OPEN 1x2m~D
A

PJP502

+1.05VTTP

DELL CONFIDENTIAL/PROPRIETARY

+1.05V_RUN_VTT

Compal Electronics, Inc.

PAD-OPEN 1x2m~D
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

www.vinafix.vn

+1.05V_RUN_VTT
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

58

of

66

VID [0]
0
0
1
1

The 1k PD on the VCCSA VIDs are empty.


These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

PR603
100K_0402_5%
1

+3.3V_RUN

<11>

PR604
0_0402_5%
1
2

VCCSA_VID_0

<11>

SW

23

SW

24

VIN

MODE

TP

25

SLEW

VOUT
5

GND
1

COMP

@
VREF

+VCCSA_PWR_SRC

PAD-OPEN 1x2m

+VCCSA_PWR_SRC

@ PC604
1000P_0603_50V7K

VIN

PC612
22U_0805_6.3V6M
1
2

SW

1 2

TPS51461RGER_QFN24_4X4~D
VIN

+VCCSA_P
PC611
22U_0805_6.3V6M
1
2

PGND

PJP600
1

10

SW

22

PL600
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

+VCCSA_PHASE

PGND

21

11

PR608
PC603
2.2_0603_1%
0.1U_0603_25V7K
2+VCCSA_BT_1 1
2

PR609
4.7_0805_5%~D

10U_0805_25V6M
PC615

10U_0805_25V6M
PC614

0.1U_0603_25V7K
PC613
1
2

2200P_0402_50V7K
PC600

+3.3V_ALW

+VCCSA_BT 1

PC610
2200P_0402_50V7K
2
1

SW

12

PC609
22U_0805_6.3V6M
1
2

14

15

13
EN

VID0

BST

20

<41,58>

PC607
0.1U_0402_25V6K~D
2
1

PGND

VID1

16

V5FILT

19

PGOOD

V5DRV

PU600

1.05V_VTTPWRGD

PC606
22U_0805_6.3V6M
1
2

17

PR607
0_0402_5%
1
2

+VCCSA_EN

PC602
2.2U_0603_10V7K
1
2

PC605
22U_0805_6.3V6M
1
2

18

2
PR606
10_0402_1%
2
1

PC601
1U_0603_10V6K

+5V_ALW

VCCSA Vout
0.9V
0.8V
0.725V
0.675V

VCCSA
TDC 4.2A
Peak Current 6A
OCP current 7.2A

PR605
1K_0402_5%
2
1

+VCCSA_PWRGD

<41> VCCSAPWROK

VCCSA_VID_1

VID[1]
0
1
0
1

output voltage adjustable network

PR600
0_0402_5%
2
1

PR601
1K_0402_5%
2
1
PR602
0_0402_5%
1
2

PC608
22U_0805_6.3V6M
1
2

@ PR610
2

33K_0402_5%

GNDA_VCCSA

PR611
100_0402_5%
2
1

PC616
1

0.22U_0402_10V6K

PC617
3300P_0402_50V7K

PR612
0_0402_5%
2
1

PR613
5.1K_0402_1%~D

PC618
0.01U_0402_25V7K
1
2

VCCSA_SENSE

<11>

PJP601

+VCCSA_P

PAD-OPEN 1x3m

+VCC_SA

PJP602
2

1
PAD-OPEN1x1m

GNDA_VCCSA

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

www.vinafix.vn

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+VCC_SA
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

59

of

66

3.57K_0402_1%

PC703
1

PR703
267K_0402_1%

PR704
330P_0402_50V7K~D

499_0402_1%~D

PC706
1
2

<11> VSS_AXG_SENSE

PC704
2
1

390P_0402_50V7K

VCC_core
TDC 52A
Peak Current 94A
OCP current 116A
Load line -1.9mV/A
FSW=400kHz

PC702
2
1

150P_0402_50V8F~D

PC705
2

47P_0402_50V8J~D

42.2K_0402_1%~D

PR702

PR705

Local sense put on HW site

<11> VCC_AXG_SENSE

PR701
PC701
2K_0402_1%
330P_0402_50V7K~D
2
1
2
1

0.01U_0402_50V7K
D

+5V_RUN

PR736
27.4K_0402_1%
2
1

PR737
2

UGATE2

75_0402_5%
1 ALERT#

PR746
2

130_0402_1%
SDA
1

PC733
2
1

VSUM-

PC766
1

PC736
2
PC738
2

0.1U_0402_25V6K~D

499_0402_1%~D

47P_0402_50V8J~D

1
0.22U_0402_6.3V6K
PR749

1
0.22U_0402_6.3V6K

PR750

LGATE2

PC734
2

PR751
5.76K_0402_1%
1
2

PC737
1

267K_0402_1% 150P_0402_50V8F~D
PR753
PC739
2K_0402_1%
680P_0402_50V7K~D
1
2
1
2

UGATE1

330P_0402_50V7K
PC748
1
2

VCCSENSE

<10>

VSSSENSE

<10>

PHASE1

Local sense put on HW site


PC751

649_0402_1%~D 2200P_0402_25V7K~D

1
2

PC749
0.22U_0603_16V7K
LGATE1

PC767
2200P_0402_50V7K~D
1
2

PC724

100U_25V_M

PC723

100U_25V_M

PC722

100U_25V_M

PC768
2200P_0402_50V7K~D
1
2

PL701
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
2
1

+VCC_CORE

PR761
ISEN1 1
10K_0603_1%

@PR762
@
PR762
2
1
10K_0402_1%

ISEN2

@PR765
@
PR765
2
1
10K_0402_1%

ISEN3

PR766
VSUM-

www.vinafix.vn

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

PR752
1
1_0402_5%

PR764
VSUM+
1
2
3.65K_0603_1%

DELL CONFIDENTIAL/PROPRIETARY

ISEN3

@ PR748
2
1
10K_0402_1%

P1_SW

PR760
4.7_1206_5%
2
1

2
1
523_0402_1%

@PR763
@
PR763

7
6
5

3
4

PR758
BOOT1 2
1 1
4.7_0603_5%~D

0.01U_0402_50V7K
PR759

PQ701
CSD87351Q5D_SON8~D

PC744

PR747
VSUM+
1
2
3.65K_0603_1%

+VCC_PWR_SRC

1
2

0.068U_0402_16V7K

0.22U_0603_10V7K

PC746 2

@ PC747

0.01UF_0402_25V7K

PC745 2

1
11K_0402_1%
2
PR756

@ PR743
2
1ISEN1
10K_0402_1%

VSUM-

PC774
2200P_0402_50V7K~D
1
2

10KB_0402_5%_ERTJ0ER103J

PR755
2.61K_0402_1%
12
1
PH703

PC750
.1U_0402_16V7K
2
1

VSUM-

PR742
ISEN2 1
10K_0603_1%

VSUM+
@

@
3.57K_0402_1%

1
0.22U_0402_6.3V6K

+VCC_CORE

PC743
0.1U_0402_25V6K~D
2
1

PR744
2

PC731
0.22U_0603_16V7K

PC732
PR745
390P_0402_50V7K
1
2
1

PC742
10U_0805_25V6K
2
1

0_0402_5%
2

PL702
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
2
1

P2_SW

PC752
680P_0603_50V7K

+5V_RUN

4
PR738
BOOT2 2
1 1
4.7_0603_5%~D

@ PR741
1

SCLK

7
6
5

PC741
10U_0805_25V6K
2
1

PR729
1
1_0402_5%

PC773
2200P_0402_50V7K~D
1
2

VSUM2

@ PR724
2
1ISEN2
10K_0402_1%

PR725
1
2
3.65K_0603_1%

+3.3V_RUN

@
PC730 10P_0402_25V8J
COMP 2
1

54.9_0402_1%

PQ702
CSD87351Q5D_SON8~D

PHASE2
PR739

2
+VCC_PWR_SRC

IMVP_PWRGD <40>
1.91K_0402_1%
1

VSUM+

PC769
2200P_0402_50V7K~D
1
2

0_0402_5%
2

@ PR717
2
1ISEN1
10K_0402_1%

PC728
0.1U_0402_25V6K~D
2
1

PR735
1

+VCC_CORE

BOOT1

+PWR_SRC

2
PAD-OPEN 1x3m

PR720
ISEN3 1
10K_0603_1%

PC727
10U_0805_25V6K
2
1

ISL95836HRTZ-T_TQFN40_5X5~D

1_0402_1%~D

PC719
680P_0603_50V7K

PR719
4.7_1206_5%
2
1

PR723

0_0402_5%~D
PR728
2
1

PJP700

PL703
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
2
1

P3_SW

PC726
10U_0805_25V6K
2
1

+5V_RUN

UGATE1

7
6
5

3
4

LGATE1

@PR718
@
PR718
0_0402_5%~D
1
2

PWM3

PC700
0.1U_0402_25V6K~D
2
1

PC715
10U_0805_25V6K
2
1

PQ703
CSD87351Q5D_SON8~D

LGATE3

PC714
10U_0805_25V6K
2
1

PHASE3

ISL6208CRZ-T_QFN8_3X3

VCCP

PHASE1

PC713
10U_0805_25V6K
2
1

UGATE3

PC735
680P_0603_50V7K

1
PH702
470K_0402_5%_ TSM0B474J4702RE

PC707
2
1

LGATE2

LGATE
PGND

1
2

30
29
28
27
26
25
24
23
22
21

PHASE

PC725
10U_0805_25V6K
2
1

11
12
13
14
15
16
17
18
19
20

3.83K_0402_1%

PHASE2

BOOT2
UGATE2
PHASE2
LGATE2
VCCP
VDD
PWM3
LGATE1
PHASE1
UGATE1

PWM

PC740
10U_0805_25V6K
2
1

ISEN3
ISEN2
ISEN1

1
2

PR734

PR716

TP

2
0_0402_5%

0_0402_5%

PC729
43P_0402_50V8J

+1.05V_RUN_VTT

1
PR732

<14,41> 1.05V_0.8V_PWROK

41

UGATE2

0_0402_5%~D

ISUMPG
ISEN1G
ISEN2G
NTCG
SCLK
ALERT#
SDA
VR_HOT#
VR_ON
NTC

BOOT2

UGATE

GND

BOOT

FCCM

PR740
4.7_1206_5%
2
1

VR_EN
NTC

SDA

VR_HOT#
2
0_0402_5%
@PR731
@
PR731
0_0402_5%
<40> IMVP_VR_ON
1
2
@ PR733
1

PWM3_12

VCC

0_0402_5%
2
0_0402_5%
2
0_0402_5%
2

1
2
3
4
5
6
7
8
9
10

ISEN1G
ISEN2G
NTCG
SCLK
ALERT#

1
PR730

<7,41,62> H_PROCHOT#

<10> VIDSOUT

<10> VIDALERT_N

<61>

PC772
2200P_0402_50V7K~D
1
2

PR722
1
PR726
1
PR727
1

<10> VIDSCLK

<61>

BOOT1G

PC712
0.22U_0603_16V7K

1U_0603_10V6K

PR721 1
27.4K_0402_1%

UGATE1G

PU701

PC721
1

<61>

PC720
1

@ PR715
1
2
0_0402_5%

+5V_RUN

PHASE1G

2
1
4.7_0603_5%~D
BOOT3

40
39
38
37
36
35
34
33
32
31

PU700

ISEN2G

COMP
PGOOD

0.22U_0402_16V7K~D
2
1
PH701
470K_0402_5%_ TSM0B474J4702RE

<61>

ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G

<61>

LGATE1G

@ PL706
HCB4532KF-800T90_1812
1
2
PR711

PGOODG

ISEN1G

PWMG2

+VCC_PWR_SRC

1U_0603_10V6K

1
<61>

@ PC711
@PC711
3300P_0402_50V7K~D

PR714

3.83K_0402_1%

2
1
0_0603_5%

PR710
@ PR712
@PR712
649_0402_1%~D
1
2

0.22U_0402_16V7K~D
<61>
PC718
2
1

VSUMG-

IMVP_PWRGD

0_0402_5%

PR713
348_0402_1%~D
1
2

PC717
2
1

1U_0603_10V6K

PC710
0.1U_0402_10V7K~D

PC709
0.068U_0603_50V7K~D
2
1

1
2

@ PC708
0.022U_0402_25V7K
2
1

@ PR708
1

ISEN3/FB2
ISEN2
ISEN1
ISUMP
ISUMN
RTN
FB
COMP
PGOOD
BOOT1

<61>

10KB_0402_5%_ERTJ0ER103J

PH700

VSUMGPC716
.1U_0402_16V7K
2
1

<61>

1
PR709
11K_0402_1%

VSUMG+
PR707
2.61K_0402_1%
1 2
1

<61>

1
1_0402_5%

Compal Electronics, Inc.


Title

+VCC_CORE
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

60

of

66

PJP702
+GFX_PWR_SRC

UGATE2G

PC770
2200P_0402_50V7K~D
1
2

PC756
0.1U_0402_25V6K~D
2
1

PC755
10U_0805_25V6K
2
1

PAD-OPEN 1x3m
@ PL707
HCB4532KF-800T90_1812
1
2

7
6
5

UGATE

PWM

PHASE

GND

LGATE

PGND

PC758
0.22U_0603_16V7K
PHASE2G
LGATE2G

ISL6208CRZ-T_QFN8_3X3

PR769
4.7_1206_5%
2
1

FCCM

+VCC_GFXCORE

1
PR770
10K_0603_1%
2
1
PR771
3.65K_0603_1%

2
4

PL705
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
2
1

GP2_SW

PR772
2

1_0402_5%
1

VSUMG-

<60>

ISEN1G

<60>

PC759
680P_0603_50V7K
2
1

PR768
4.7_0603_5%~D
1
2BOOT2G 1 1

BOOT

PC775
2200P_0402_50V7K~D
1
2

VCC

+VCC_PWR_SRC

PC757
2
1

PR767
2
1
0_0603_5%
5
PWMG2

PQ705
CSD87351Q5D_SON8~D

PU702
<60>

PC754
10U_0805_25V6K
2
1

PC753
10U_0805_25V6K
2
1

1U_0603_10V6K

+5V_RUN
D

VCC_GFXCORE
TDC 38A
Peak Current 46A
OCP current 57.18A
Load line -3.9mV/A
FSW=400kHz

VSUMG+
ISEN2G

PR773
1

<60>

10K_0402_1%
2

<60>
C

7
6
5

PHASE1G

@
<60>

LGATE1G

PR775
1_0402_5%
1
2
PR778
10K_0402_1%

2
PR777
10K_0603_1%
1
2
PR774
3.65K_0603_1%

1
2

PR776
4.7_1206_5%
1

BOOT1G

ISEN2G
VSUMG+

<60>

<60>

<60>
VSUMG-

PR779
4.7_0603_5%~D

+VCC_GFXCORE

@
PC776
2200P_0402_50V7K~D
1
2

1 1

PC764
0.22U_0603_16V7K

PL704
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
2
1

GP1_SW

<60>

PC771
2200P_0402_50V7K~D
1
2

<60>

UGATE1G

<60>

PC765
680P_0603_50V7K

PC763
0.1U_0402_25V6K~D
2
1

PC762
10U_0805_25V6K
2
1

PQ704
CSD87351Q5D_SON8~D

PC761
10U_0805_25V6K
2
1

PC760
10U_0805_25V6K
2
1

+GFX_PWR_SRC

<60>

ISEN1G

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+VCC_GFXCORE
Size

www.vinafix.vn

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

61

of

66

@ PD1300
2
1
ES2AA-13-F
PQ1300
SI4835DDY-T1-GE3_SO8~D
8
1
7
2
6
3
5

PR1301
0.01_1206_1%~D

+SDC_IN

PR1306
100K_0402_1%~D
1

PC1309
1U_0603_10V6K~D
2
1

PR1307
100K_0402_1%~D
2
1

27
PGND
CSOP

CE

CSON

@ PC1317
220P_0402_50V7K~D
CHG_LGATE

@ PR1327
1
2
10K_0402_5%~D

7
12
29

PQ1305

17
15 VFB

VFB
GND

1 PR1328 2
100_0402_5%~D

16

NC

+VCHGR

TP

ISL88731C_QFN28_5X5~D
PJP1301
1

PAD-OPEN1x1m
GNDA_CHG
GNDA_CHG

Maximum charging current is 7.2A

PC1315
10U_1206_25V6M~D
2
1
+VCHGR

PR1326
PL1301
0.01_1206_1%~D
5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D
2
1+VCHGR_L
4
1

19
18

3
PC1322
1000P_0603_50V7K~D

PR1332
4.7_1206_5%~D

@ PC1333
0.1U_0603_25V7K~D
1
2

PC1334
1
2

PC1332
10U_1206_25V6M~D
2
1

VREF

20

LGATE

PC1331
10U_1206_25V6M~D
2
1

2
EAO

3
2
1

EAI

PC1320
56P_0402_50V8~D
1
2

@
@ PC1321
120P_0402_50VNPO~D
1
2

PC1328
0.1U_0402_10V7K~D
2
1

MAX8731_REF

PC1327
1U_0603_10V6K~D
2
1

@ PR1324
1
2
7.5K_0402_5%~D

+VCHGR_B

1
0_0603_5%~D

PHASE
FBO

PR1330
10_0402_5%~D
2
1

23

PC1314
10U_1206_25V6M~D
2
1

PR1322

VICM

2200P_0402_50V7K~D

PC1326
0.01U_0402_25V7K~D
2
1

Vref
TI bq24747 = 3.3V
Intersil ISL88731C = 3.2V
VDDP
TI bq24747 = 6V
Intersil ISL88731C = 5.1V

PC1323
220P_0402_50V8J~D
2
1

PR1329
8.45K_0402_1%~D
2
1

<22> MAX8731_IINP

PC1325
0.01U_0402_25V7K~D
2
1

<41> CHARGER_SMBDAT

5
@ PC1318
2
1

@ PR1323
200K_0402_5%~D

PC1324
0.01U_0402_25V7K~D
2
1

PR1325
4.7K_0402_5%~D
2
1

GNDA_CHG
<41> CHARGER_SMBCLK

PC1330
10U_1206_25V6M~D
2
1

UGATE

SIR472DP-T1-GE3_POWERPAK8-5

1U_0603_10V6K~D

CHG_UGATE

PC1329
0.1U_0603_25V7K~D
2
1

24

PQ1304

PC1311
1
2

PR1331
0_0402_5%~D
2
1

NC

GNDA_CHG

PC1313
0.1U_0603_25V7K~D
2
1

21 MAX8731A_LDO

VDDP

PC1312
2200P_0402_50V7K~D
2
1

SCL

28
CSSP

CSSN

ICREF

BOOT
VDDSMB

6
1

<63>

DK_CSS_GC

SI7716ADN-T1-GE3_POWERPAK8-5

MAX8731_IINP

PR1312
0_0402_5%~D
1
2

3
2
1

14

GNDA_CHG

PR1319
4.7_0603_5%~D
PR1318
2.2_0603_1%~D
BOOT_D
2

BOOT
25
1

ACOK

SDA

<39>

DOCK_DCIN_IS-

PC1319
3300P_0402_50V7K~D
2
1

10

ACIN

PD1301
BAT54HT1G_SOD323-2~D
2
1

11

ICOUT
26

ICOUT

PC1310
0.1U_0603_25V7K~D
2
1

13

PC1316
0.1U_0402_10V7K~D

PR1305
CSSN_1
1
10_0402_5%~D

PR1304
10_0402_5%~D
CSSP_1
1

PR1320
1
2
0_0402_5%~D

<39>

GNDA_CHG

+5V_ALW

0.1U_0603_25V7K~D
PC1306
GNDA_CHG
PU1300
0.1U_0805_50V7M~D
+DCIN 22
2
1
DCIN

PR1316
15.8K_0402_1%~D
2
1

0.01U_0402_25V7K~D
GNDA_CHG

PR1311
10K_0402_5%~D
2
1

PR1310
10K_0402_1%~D
2
1

PR1313
226K_0402_1%~D
1
2

PC1305
1
2

ACAV_IN

PC1304
0.047U_0603_25V7M~D
1
2

DOCK_DCIN_IS+

<22,41,63>

PQ1303B
NTGD4161PT1G_TSOP6~D

PR1303
10K_0402_5%~D
2
1

1_0805_5%~D

PC1303
0.1U_0603_25V7K~D
1
2

@ PR1309
1
2

MAX8731_REF

PR1317
49.9K_0402_1%~D
2
1
PC1307

PQ1303A
NTGD4161PT1G_TSOP6~D

+SDC_IN

2
G
PQ1302
NTR4502PT1G_SOT23-3~D

BAT54CW_SOT323~D

<63> +CHGR_DC_IN

PQ1301
NTR4502PT1G_SOT23-3~D

2
G

PC1302
0.1U_0603_25V7K~D
2
1

+DC_IN_SS

PAD-OPEN 4x4m

PR1313
TI bq24745 = 316K
Intersil ISL88731 = 226K
Maxim = 383K

+DOCK_PWR_BAR

PC1301
47P_0402_50V8J~D
2
1

PD1302

E2 AC_OK=17.7 Volt

CSS_GC

PR1302

<63>
<63>

DC_BLOCK_GC

1
2

0_0402_5%~D

MAX8731A_LDO

CHAGER_SRC

4
@

PR1300
1
0_0402_5%~D

+PWR_SRC
PJP1300

PC1300
0.1U_0603_25V7K~D

+DC_IN_SS

@ PL1300
1UH_PCMB053T-1R0MS_7A_20%
2
1

@ PC1335
1
2

0.22U_0603_25V7K~D

0.1U_0603_25V7K~D

GNDA_CHG
GNDA_CHG
MAX8731_REF

ACAV_IN_NB

<40,41,63>

PR1348
41.2K_0402_1%~D
2
1

8
P
4

LM393DR_SO8~D

@
+3.3V_ALW

PR1351
100K_0402_5%~D

PC1342
0.1U_0402_25V4Z~D
1

Adapter Protection Circuit for Turbo Mode

O
3

PU1302

1
2

TC7SH08FU_SSOP5~D

PROCHOT_GATE

<40>

To preset system to throtlle


switching from AC to DC

2
G

ACAV_IN

<22,41,63>

PQ1309
RHU002N06_SOT323-3~D

PR1342
0_0402_5%~D

PU1303B
O

+3.3V_ALW

2
G

<41> DYN_TUR_CURRNT_SET#

PR1338
10K_0402_1%~D
2
1

PR1336
47K_0402_1%~D
2
1

PR1335
232K_0402_1%~D
2
1

+5V_ALW

PC1339
100P_0402_50V8J~D
2
1

2
LM393DR_SO8~D

PR1333
1M_0402_1%~D
1
2

PR1347
42.2K_0402_1%~D
2
1

PR1346
22.6K_0402_1%~D
2
1

PC1338
100P_0402_50V8J~D
2
1

2
PR1339

PU1303A

MAX8731_REF

5
PQ1307B
DMN66D0LDW-7 2N_SOT363-6~D
4
3

1
S

PC1341
100P_0402_50V8J~D
2
1

PR1350
113K_0402_1%~D
2
1

PR1349
162K_0402_1%~D
2
1
1

PC1340
220P_0402_50V8J~D

<7,41,60>

0_0402_5%~D

1
3

PR1343
20K_0402_1%~D
1
2

MAX8731_IINP

PR1341
150K_0402_1%~D

DMN66D0LDW-7 2N_SOT363-6~D
PQ1307A

221K_0402_1%~D

PR1340
1.8M_0402_1%
1
2

PR1334
2

+5V_ALW

H_PROCHOT#

Low

130W

+3.3V_ALW2

High
1

90W

+DC_IN

PC1337
0.01U_0402_25V7K~D
2
1

DYN_TUR_CURRENT_SET#
3

PC1336
100P_0402_50V8J~D
2
1

+5V_ALW

PQ1306
RHU002N06_SOT323-3~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

www.vinafix.vn

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Charger
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
D

Sheet

62

of

66

PR901
330K_0402_5%~D

@ PR934
1

PD908
RB751V-40GTE-17_SOD323~D
2
1

DEFAULT_OVRDE
PR923
10K_0402_5%~D
2
1

PQ911
2N7002W-7-F_SOT323-3~D

2
G

ACAV_IN

<22,41,62>

100K_0402_5%~D
2

PR937
0_0402_5%~D
2
MODULE_BATT_PRES#

<40,53>

2
+DOCK_PWR_BAR

1
PR939
1
PR940

2
0_0402_5%~D
2
0_0402_5%~D

PR941
0_0402_5%~D

1
PR948

+SDC_IN

1
PR951

2ACAVDK_SRC
0_0402_5%~D

2
0_0402_5%~D
CD3301_SDC_IN

<62> DC_BLOCK_GC
ACAV_IN

1
PR955

+3.3V_ALW2

1
PR957

1
2
ERC1
3
4
5
6
7
ACAVIN
8
P33ALW2 9

2
0_0402_5%~D

37

TP

2
5

PC914
1500P_0402_7K~D

1
ERC2

PC913
0.1U_0402_25V4Z~D
2
1

ERC3

1
2
0_0402_5%~D

<39,40>

<62>
CSS_GC
<62> DK_CSS_GC

PC912
0.047U_0603_25V7K~D
2
1

DOCK_SMB_ALERT#

PR961

PC911
0.1U_0603_25V7K~D
2
1

2
2

P50ALW
PBATT_OFF
DK_AC_OFF_EN
ACAV_IN_NB
GND
DK_AC_OFF_EN
SL_BAT_PRES#
BLKNG_MOSFET_GC
NBDK_DCINSS

27
26
25
24
23
22
21
20
19

1
PR945

+5V_ALW
2
0_0402_5%~D

CD_PBATT_OFF 1
PR947

2
0_0402_5%~D

SLICE_BAT_ON

<40>

1
PR949

2
0_0402_5%~D

DOCK_AC_OFF

<39,40>

DK_AC_OFF

1
3301_ACAV_IN_NB

DK_AC_OFF_EN
SL_BAT_PRES#

1
PR953

2
0_0402_5%~D
1
PR954
BLKNG_MOSFET_GC

1
PR956
1
PR958

2
0_0402_5%~D
2
0_0402_5%~D

ACAV_IN_NB
2
0_0402_5%~D

SLICE_BAT_PRES#

<40,41,62>
DOCK_AC_OFF_EC

1M_0402_5%~D
PR952
<40>

<39,40>

+NBDOCK_DC_IN_SS

CD3301RHHR_QFN36_6X6~D

10
11
12
13
14
15
16
17
18

2
0_0402_5%~D

DC_IN
SS_GC
ERC1
ACAVDK_SRC
GND
SDC_IN
DC_BLK_GC
ACAV_IN
P33ALW2

PQ915
FDN338P_G_NL_SOT23-3~D
1

1
PD917
2

RB751V-40GTE-17_SOD323~D

1
PD916
2

RB751V-40GTE-17_SOD323~D

<22,41,62>

36
35
34
33
32
31
30
29
28

100K_0402_5%~D

NC
CHARGERVR_DCIN
DC_IN_SS
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+

PR946

P50ALW

CSS_GC
DK_CSS_GC
ERC3
ERC2
GND
PWR_SRC
SS_DCBLK_GC
EN_DK_PWRBAR
P33ALW

PU900

<53> SOFT_START_GC
1
2

<39> ACAV_DOCK_SRC#

<39,40> SLICE_BAT_PRES#

CHGVR_DCIN
DC_IN_SS
DK_PWRBAR

0.1U_0603_50V4Z~D

+3.3V_ALW2

2
0_0402_5%~D

CD3301_DCIN

2
47_0805_5%~D
PC910

1
PR943

@ PR942
0_0402_5%~D

+DC_IN_SS

PBAT_PRES#

1
PR944

PC905
2200P_0402_50V7K~D
2
1

PD907
RB751V-40GTE-17_SOD323~D
2
1

PBATT+

<62> +CHGR_DC_IN
+DC_IN

+PWR_SRC

PR924
499K_0402_1%~D
2
1

PDS5100H-13_POWERDI5-3~D
PQ914
1
D
S
2
D
S
3
D
S
4
D
G

FDS6679AZ_G_SO8~D

PC907
0.01U_0603_25V7K~D

PBATT_IN_SS

MPBATT+

PR933
510K_0402_5%~D
2
1

PD915
RB751V-40GTE-17_SOD323~D

1
3

<40>

<40>

PR911
0_0402_5%~D

MODULE_ON

PR907
330K_0402_5%~D

1
PR928
499K_0402_1%~D

2
0_0402_5%~D

FDS6679AZ_G_SO8~D

390K_0402_5%~D

1
PQ906B
DMN66D0LDW-7 2N_SOT363-6~D
4
3

2
SLICE_BAT_PRES#

PR925
51

PQ905B
DMN66D0LDW-7 2N_SOT363-6~D
4
3
1

<39,40>

PD913
RB751V-40GTE-17_SOD323~D
1
2

6
PR932
PD912
0_0402_5%~D
RB751V-40GTE-17_SOD323~D
2
1
1
2
1

PD911
RB751V-40GTE-17_SOD323~D

DMN66D0LDW-7 2N_SOT363-6~D
PQ906A

1
3
PR936
0_0402_5%~D
1
2 4

PR922

2
PR921
20K_0402_1%~D

DMN66D0LDW-7 2N_SOT363-6~D
PQ907B

<40,53>

@
B

PQ908A
DMN66D0LDW-7 2N_SOT363-6~D
1
6

3
4
2

PR938
499K_0402_1%~D
2
1

2
0_0402_5%~D

1
PR935

PD910
RB751V-40GTE-17_SOD323~D
1
2

PR931
200K_0402_1%~D
6
2
1

<40> SLICE_BAT_ON

DMN66D0LDW-7 2N_SOT363-6~D
PQ907A

PBATT+

<40> DEFAULT_OVRDE

DMN66D0LDW-7 2N_SOT363-6~D
PQ908B

PR926
0_0402_5%~D

2
G

DMN66D0LDW-7 2N_SOT363-6~D
PQ910A

PR919
10K_0402_5%~D
6
2
1

PR920
10K_0402_5%~D
2
1
1
3

<40,53> PBAT_PRES#

2N7002W-7-F_SOT323-3~D

PQ916

1
2
3
4

S
S
S
G

PD905

PR917
820_0603_1%~D
1
2

PQ905A
DMN66D0LDW-7 2N_SOT363-6~D
1
6

PR916
20K_0402_1%~D

8
7
6
5

DMN66D0LDW-7 2N_SOT363-6~D
PQ910B

PR914
620K_0402_5%~D
2
1

TC7SH08FU_SSOP5~D

PR913
390K_0402_5%~D
2
1

O
A

PC904
0.1U_0603_25V7K~D
2
1

5
2

<40> CHARGE_PBATT

ACAV_IN

<22,41,62>

PR915
100K_0402_5%~D
1
2

+VCHGR

PU901

PQ912
FDS6679AZ_G_SO8~D
1
8
S
D
2
7
S
D
3
6
S
D
4
5
G
D

D
D
D
D

PD904
RB751V-40GTE-17_SOD323~D
2
1

PC903
0.01U_0603_25V7K~D

PQ904B
DMN66D0LDW-7 2N_SOT363-6~D

PBATT+

+DOCK_PWR_BAR

PD903
RB751V-40GTE-17_SOD323~D
2
1

PR912
330K_0402_5%~D

PQ913
SI4835DDY-T1-GE3_SO8~D
1
8
2
7
3
6
5

PQ903
8
7
6
5

FDS6679AZ_G_SO8~D

1
+3.3V_ALW2

ES2AA-13-F SMA
PD902
2
1

MPBATT_IN_SS

3
DMN66D0LDW-7 2N_SOT363-6~D

PC916
0.1U_0402_10V7K~D
1
2

8
7
6
5

PR905
820_0603_1%~D
1
2

PDS5100H-13_POWERDI5-3~D
PQ902
1
D
S
2
D
S
3
D
S
4
D
G

FDS6679AZ_G_SO8~D
PQ901

1
3

PC902
0.47U_0805_25V7K~D

8
7
6
5

D
D
D
D

PC906
0.1U_0603_25V7K~D
2
1

S
S
S
G

STSTART_DCBLOCK_GC

PR904
620K_0402_5%~D
2
1

PQ904A
S

1
2
3
4

PR910
499K_0402_1%~D
2
1

2
G

<40,53> MODULE_BATT_PRES#

PR909
390K_0402_5%~D
2
1

PQ909
2N7002W-7-F_SOT323-3~D

MPBATT+

PR906
10K_0402_5%~D
2
1

PR908
10K_0402_5%~D
2
1

3
TC7SH08FU_SSOP5~D

O
A

PC900
0.1U_0603_25V7K~D
2
1

<40> CHARGE_MODULE_BATT

PU902

ACAV_IN

<22,41,62>

PR900
100K_0402_5%~D
1
2

+VCHGR

PD901

PR903
390K_0402_5%~D
2
1

+3.3V_ALW2
PC915
0.1U_0402_10V7K~D
1
2

PQ900
SI4835DDY-T1-GE3_SO8~D
1
8
2
7
3
6
5

P33ALW

1
PR959

2
+3.3V_ALW
0_0402_5%~D

EN_DK_PWRBAR
1
PR960

2
0_0402_5%~D

EN_DOCK_PWR_BAR
1

STSTART_DCBLOCK_GC

<40>

DELL CONFIDENTIAL/PROPRIETARY

1M_0402_5%~D
@ PR962

Compal Electronics, Inc.


Title

3301_PWRSRC

1
PR963

2
0_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
+PWR_SRC

Selector
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

63

of

66

Initial voltage is 0.975V

+VGA_B+

+3.3V_RUN_GFX

PJP1000

PR1020
47K_0402_1%~D
2
1

GNDA_GPU_CORE
@ PR1050
0_0402_5%
1

<45> GPU_HOT#

PR1019
100K_0402_5%
2

GPU_VID6
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0

+3.3V_RUN

PU1000
2

GNDA_GPU_CORE
PR1046
1.4K_0402_1%
2
1

PH1001
470K_0402_5%_TSM0B474J4702RE
1
2

AGND

GPU_VID_5

<45>

GPU_VID_4

<45>

GPU_VID_3

<45>

7
6
5

GPU_VID_2

<45>

GPU_VID_1

<45>

PL1000
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
2
1

P2_VGA_SW

LGATE2_VGA

PR1009
1_0402_5%

1
+

PR1015
10K_0402_1%~D
1
2+GPU_CORE

VSUM+_VGA

@ PR1007
2.2_1206_5%

+GPU_CORE

2
VSUM-_VGA

ISEN2_VGA
F

30
29
28
27
26
25
24
23
22
21

PR1022
1

0_0402_5%
2

+GPU_CORE
TDC 35A
Peak Current 42A
OCP current 51A
No Load line
FSW=400kHz

+5V_RUN

PR1021
0_0402_5%

PC1010
1U_0603_10V6K

41

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

PR1025
499_0402_1%~D
2
1

11
12
13
14
15
16
17
18
19
20

1
2

@ PC1009
22P_0402_50V8J

PC1011
1000P_0402_50V7K

PR1024
6.81K_0402_1%~D
2
1

@ PR1023
249K_0402_1%
1
2

1
2
3
4
5
6
7
8
9
10

PHASE2_VGA

40
39
38
37
36
35
34
33
32
31

CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

,40> DGPU_PWROK

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

PR1017
0_0402_5%
1

PR1013
1.91K_0402_1%

UGATE2_VGA

<45>

PC1006
470U_D2_2VM_R4.5M

CLK_ENABLE#_VGA

GPU_VID_6

PR1010
1.91K_0402_1%
1
2
1

+3.3V_RUN

1
PR1002
0_0402_5%
2
1
PR1005
0_0402_5%
2
1
PR1006
0_0402_5%
2
1
PR1011
0_0402_5%
2
1
PR1014
0_0402_5%
2
1
PR1016
0_0402_5%
2
1
PR1018
1K_0402_1%~D

GNDA_GPU_CORE

PQ1001
CSD87351Q5D_SON8~D

PC1005
0.22U_0603_10V7K
BOOT2_2_VGA
1
2

PR1003
4.7_0603_5%~D
2
1

@ PC1008
2200P_0402_50V7K
2
1

PR1004
10K_0402_1%
1
2

+PWR_SRC

10K_0402_1%
2

PR1047
1

BOOT2_VGA
G

PC1000
10U_1206_25V6M
2
1

10K_0402_1%
2

PR1012
10K_0402_1%~D

@ PR1059
1

10K_0402_1%
2

PC1003
10U_0805_25V6K

10K_0402_1%
2

10K_0402_1%
2

PC1002
2200P_0402_50V7K
2
1

PR1052
1

PR1049
1
@ PR1062
1

PC1001
0.1U_0402_25V6K~D
2
1

10K_0402_1%
2

PC1004
22P_0402_50V8J
1
2

@ PR1058
1

JUMP_1X3m

GNDA_GPU_CORE

10K_0402_1%
2

10K_0402_1%
2
10K_0402_1%
2

PR1008
3.65K_0402_1%
2
1

@ PR1001
10K_0402_1%
1
2

PR1054
1

PR1051
1
@ PR1061
1

PC1007
1000P_0603_50V7K
2
1

RUN_ON

<28,36,40,43,56>

10K_0402_1%
2

10K_0402_1%
2

PR1000
10K_0402_1%
1
2

<40,45> DGPU_PWR_EN

@ PR1057
1

@ PR1060
1

10K_0402_1%
2

PR1056
1

PC1012
2

ISL62883CHRTZ-T_TQFN40_5X5

GNDA_GPU_CORE

470P_0402_50V8J~D

PC1013
47P_0402_50V8J~D
1
2

PR1027
3.57K_0402_1%
1
2

+5V_RUN

PR1026
0_0402_5%

+VGA_B+

1
2

PC1022
10U_0805_25V6K

PC1021
2200P_0402_50V7K
2
1

PC1023
10U_1206_25V6M
2
1
PL1001
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
2
1

Layout Note:
Place near Phase1 Choke

VSUM+_VGA

1
2

1
1
PR1040
1_0402_5% +
2

PR1039
10K_0402_1%~D

PH1000
10K_0402_1%_TSM0A103F34D1RZ

PR1038
3.65K_0402_1%
2
1

PC1032
1000P_0603_50V7K
1
2
1

LGATE1_VGA

PR1042
10K_0402_1%~D
1
2+GPU_CORE

1
+
2

VSUM-_VGA

@ PR1037
2.2_1206_5%
ISEN1_VGA

PC1033
0.1U_0402_16V7K

PAD-OPEN1x1m

DELL CONFIDENTIAL/PROPRIETARY

GNDA_GPU_CORE

+GPU_CORE
PC1030
470U_D2_2VM_R4.5M

P1_VGA_SW

VSUM-_VGA

PJP1004
1

7
6
5

PR1045
953_0402_1%
1
2

PR1044
10_0402_5%
1
2

PHASE1_VGA

PR1043
0_0402_5%
1
2

<46> GPU_VSS_SENSE

PR1041
11K_0402_1%
2
1

PC1031
1000P_0402_50V7K

PC1028
0.1U_0402_16V7K
2
1

@
GNDA_GPU_CORE

PC1027
0.068U_0603_50V7K~D
2
1

1
PC1025
330P_0402_50V7K

PC1026
0.01U_0402_25V7K

2
PR1036
0_0402_5%

<46> GPU_VDD_SENSE

PC1029
470U_D2_2VM_R4.5M

PR1035
2.61K_0402_1%
2
1

PQ1000
CSD87351Q5D_SON8~D

PR1034
PC1024
4.7_0603_5%~D
0.22U_0603_10V7K
2
1 BOOT1_1_VGA
1
2

PR1033
82.5_0402_5%

PR1032
10_0402_5%

UGATE1_VGA

VSUM+_VGA

VSUM-_VGA
1

+GPU_CORE

PC1020
0.1U_0402_25V6K~D
2
1

+5V_RUN

GNDA_GPU_CORE

+VGA_B+

PC1019
0.22U_0603_25V7K

PC1018
1U_0603_10V6K
2
1

1
2

2
GNDA_GPU_CORE

2
PR1029
0_0402_5%
1
2
PR1031
1_0402_5%

BOOT1_VGA

PR1030
249K_0402_1%

PR1028
324K_0402_1%~D

PC1017
0.22U_0402_10V4Z

ISEN1_VGA

@ PC1014
2200P_0402_50V7K
2
1

ISEN2_VGA

PC1015
150P_0402_50V8J

PC1016
0.22U_0402_10V4Z

GNDA_GPU_CORE

Compal Electronics, Inc.


Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

www.vinafix.vn
5

+GPU_CORE
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
2

64

Sheet
1

of

66

+VCC_CORE

+VCC_CORE

1
PC1100
10U_0805_4VAM

1
PC1101
10U_0805_4VAM

1
PC1102
10U_0805_4VAM

Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_GFXCORE

Socket Bottom

5 x 22 F (0805)
5 x (0805) no-stuff
sites

Socket Top

7 x 22 F (0805)
2 x (0805) no-stuff
sites

1
PC1103
10U_0805_4VAM

PC1104
10U_0805_4VAM

+VCC_GFXCORE

PC1118
22U_0805_6.3V6M

PC1117
22U_0805_6.3V6M

+VCC_CORE

PC1116
22U_0805_6.3V6M

1
PC1109
10U_0805_4VAM

PC1115
22U_0805_6.3V6M

1
PC1108
10U_0805_4VAM

PC1114
22U_0805_6.3V6M

1
PC1107
10U_0805_4VAM

PC1113
22U_0805_6.3V6M

1
PC1106
10U_0805_4VAM

PC1112
22U_0805_6.3V6M

1
PC1105
10U_0805_4VAM

PC1111
22U_0805_6.3V6M

+1.05V_RUN_VTT

1
+

1
+

1
+

PC1164
22U_0805_6.3VAM

1
+

1
+

PC1187
470U_D2_2VM_R4.5M

PC1175
470U_D2_2VM_R4.5M

1
PC1163
22U_0805_6.3VAM

PC1174
470U_D2_2VM_R4.5M

PC1168
22U_0805_6.3VAM

PC1173
470U_D2_2VM_R4.5M

PC1172
470U_D2_2VM_R4.5M

1
PC1162
22U_0805_6.3VAM

PC1155
22U_0805_6.3VAM

1
PC1161
22U_0805_6.3VAM

PC1134
22U_0805_6.3VAM

1
PC1160
22U_0805_6.3VAM

PC1166
330U_X_2VM_R6M

PC1165
330U_X_2VM_R6M

PC1154
22U_0805_6.3VAM

PC1133
22U_0805_6.3VAM

PC1152
22U_0805_6.3VAM

2
1

PC1132
22U_0805_6.3VAM

PC1153
22U_0805_6.3VAM

PC1151
22U_0805_6.3VAM

PC1131
22U_0805_6.3VAM

PC1146
22U_0805_6.3VAM

PC1150
22U_0805_6.3VAM

PC1130
22U_0805_6.3VAM

PC1145
22U_0805_6.3VAM

PC1149
22U_0805_6.3VAM

PC1129
22U_0805_6.3VAM

PC1144
22U_0805_6.3VAM

PC1157
470U_D2_2VM_R4.5M

PC1148
22U_0805_6.3VAM

PC1143
22U_0805_6.3VAM

PC1156
470U_D2_2VM_R4.5M

PC1147
22U_0805_6.3VAM

+1.05V_RUN_VTT
1
1
1
@
PC1128
22U_0805_6.3VAM

PC1127
22U_0805_6.3VAM

PC1126
22U_0805_6.3VAM

PC1123
22U_0805_6.3VAM

PC1125
22U_0805_6.3VAM

PC1122
22U_0805_6.3VAM

PC1138
22U_0805_6.3V6M

PC1121
22U_0805_6.3VAM

1
PC1137
22U_0805_6.3V6M

PC1120
22U_0805_6.3VAM

PC1136
22U_0805_6.3V6M

PC1119
22U_0805_6.3VAM

PC1135
22U_0805_6.3V6M

PC1124
22U_0805_6.3VAM

1
1

2 @

(place under GPU)

+GPU_CORE

+GPU_CORE

(place near GPU)

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1
2

2
1
2

PC1218
4.7U_0603_6.3V6K~D

PC1217
4.7U_0603_6.3V6K~D

PC1216
4.7U_0603_6.3V6K~D

PC1215
4.7U_0603_6.3V6K~D

PC1214
4.7U_0603_6.3V6K~D

PC1213
22U_0805_6.3V6M

PC1197
4.7U_0603_6.3V6K~D

PC1196
4.7U_0603_6.3V6K~D

PC1195
4.7U_0603_6.3V6K~D

PC1212
47U_0805_6.3V6M~D

PC1186
4.7U_0603_6.3V6K~D

PC1185
4.7U_0603_6.3V6K~D

PC1194
4.7U_0603_6.3V6K~D

PC1184
4.7U_0603_6.3V6K~D

PC1211
.1U_0402_16V7K

PC1183
4.7U_0603_6.3V6K~D

PC1210
.1U_0402_16V7K

PC1182
4.7U_0603_6.3V6K~D

PC1209
.1U_0402_16V7K

PC1193
.1U_0402_16V7K

PC1192
.1U_0402_16V7K

PC1191
.1U_0402_16V7K

PC1190
.1U_0402_16V7K

+GPU_CORE

+GPU_CORE

PC1181
4.7U_0603_6.3V6K~D

PC1180
4.7U_0603_6.3V6K~D

PC1179
4.7U_0603_6.3V6K~D

PC1178
4.7U_0603_6.3V6K~D

PC1177
4.7U_0603_6.3V6K~D

PC1189
.1U_0402_16V7K

PC1176
4.7U_0603_6.3V6K~D

+GPU_CORE

+GPU_CORE

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

www.vinafix.vn
3

PROCESSOR DECOUPLING
Size

Document Number

Date:

Friday, June 10, 2011

Rev
0.1

LA-7782
Sheet
1

65

of

66

V ersion Change L ist ( P. I. R . L ist )


Item Page#

Title

D ate

R equest
O w ner

Page 1

Issue D escription

Solution D escription

R ev.

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

www.vinafix.vn
3

PWR_PIR 1
Size

Rev
0.1

LA-7782
Date:

Document Number
Friday, June 10, 2011

Sheet
1

66

of

66