library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dulces is
port(clk: in std_logic;
DN : in std_logic_vector(1 downto 0);
RC : out std_logic_vector(1 downto 0));
end dulces;
architecture candy of dulces is
type estados is ( Q0,Q5,Q10,Q15);
signal edo_pres ,edo_futuro:estados;
begin
proceso1: process(edo_pres,DN)begin
case edo_pres is
when Q0=>
if DN="10" then
RC<="00";
edo_futuro<=Q5;
elsif DN="01"then
RC<="00";
edo_futuro<=Q10;
elsif DN="00" then
RC<="00";
edo_futuro<=Q0;
elsif DN="11" then
RC<="00";
edo_futuro<=Q0;
end if;
when Q5=>
if DN="10" then
RC<="00";
edo_futuro<=Q10;
elsif DN="01"then
RC<="00";
edo_futuro<=Q15;
elsif DN="00" then
RC<="00";
edo_futuro<=Q5;
elsif DN="11" then
RC<="00";
edo_futuro<=Q0;
end if;
when Q10=>
if DN="10" then
RC<="00";
edo_futuro<=Q15;
elsif DN="01"then
RC<="10";
edo_futuro<=Q0;
elsif DN="00" then
RC<="00";

edo_futuro<=Q10;
elsif DN="11" then
RC<="00";
edo_futuro<=Q0;
end if;
when Q15=>
if DN="10" then
RC<="10";
edo_futuro<=Q0;
elsif DN="01" then
RC<="11";
edo_futuro<=Q0;
elsif DN="00" then
RC<="00";
edo_futuro<=Q15;
elsif DN="11" then
RC<="00";
edo_futuro<=Q0;
end if;
end case;
end process proceso1;
proceso2:process(clk)begin
if(clk'event and clk='1') then
edo_pres<=edo_futuro;
end if;
end process proceso2;
end candy;