[Piease write your Exam Rott No.) END TERM EXAMINATION Finst Semusrer [MCA] December 2011 i \Paper Code: MCA 107 3 ‘Subject; Computer Organization_ gi 3 Hours Sri ‘Maxima Marks 160 Note: Qo: Tis conpulaary. Aitempt any question from cach unit] (2x10=20) QI. Answer the following: .ss bus is unidirectional in ef Why data bus is bidi rost microprocessors? What is non-maskable Interrupts? What is race around condition? W\? fa Subtract -24 from 21 in 2 complement fors fof Define pipeline speedup and throughput. Determine the reverse polise nation for A/(B+C} software pipelining? What happens when an RET instruction at the ond of a subroutine ectional and addr Tau cated computer? ictions limit the RISC architecture? following functions 02. {a} Desing multiplexer implementations for th using the numerical method. The simulation should be used to check the workings. @) Z=((A.B, (, 1,2,3,5,7,8,10,12,1 (o) Explain the working mechanism of edge trige 15}. ed and level triggered Flip-Flops. 6) (a) Discuss about various microoperations, ” {b) Discuss master slave Filp-Flop. (3) far 04. ta) n multiple bus organizational in det @) ib) WE ack? Hlustrate th Jack in subroutine processing with suitable diagram 7 ia) Discuss the different addressing (6) State the d mictu programmed control unit (4) Unit-1 Q6. (a) Explain ho erformance of the instructio e improved. 010 with 110011 using Booth’s algor Where ¢ =2) seam Rott No.Q.2%.LSA044)BI {i) What is the cycle time that maximizes performances without allocating multiple cycles to a segment? (ii) What is the total time to execute the function through all YZ Why does DMA have priority over the CPU when both request @ memory transfer? (2) {ip What is the importance of an 1/0 interface? @) os sy y hierarchy with the following specifications: eh ‘The design goal is to achieve an effective memory-access time t= Boone with a cache hit ratio hi=0.97 and a hit ratio he-0.99 in main memory. Find the main memory access time we Q9.- (a) What is virtual memory? Explain how the logic (ranslated into physical address in the virtual memory system with a neat diagram. 8) ate the merits and demerits of associative memory (4) (o) A digital computer has a memory unit of K x16 and a cache memory of 1k words. The cache uses pping with a bisek size of four words. How many bits are there in the tag, index, block and word fields of the address format? How m blocks car ne cache accommodate? ‘s) mented 28 RB