SEMI 4200 ISONSEC, STATIC, TTLIN/QUT, 4096x1 N-#NBS FEATURES = Completely Static # Access Time as low as 160 nsec max * Cycle Time as low as 300 nsec max 1 Typical Operating Power Under 450 mur 1 Typical Standby Power Under 35 mw * Data Retention with Low Vo * Pin and Voltage Compatible with Standard 22.Pin 4K Dynamic Rams = TTL Compatible Three-State Outputs = Fully Decoded * Active Low Chip Select exami BLOCK DIAGRAM GENERAL DESCRIPTION The SEMI 4200 is an N-Channel MOS Random Access Memory, organized as 4096 words by one bit. Ituses a fully static memory cell which eliminates the need for any refresh or charge pump circuitry All inputs can be driven by standard TTL devices and the three-state data output can directly drive one TTL load of any type. The Chip Select input provides far simple ‘memory expansion and low system power, by putting unselected devices into a high output impedance and low power state. For additional power savings Vop can be reduced significantly, thus allowing data to be retained economically under battery power. i g i El 3 5 5 i 5 mcmama hye im aes mmm PIN CONFIGURATION [Ay Address Inputs DL Dats Input BO. Data Cutout GS_ Chip Select Input R/w Read/Write Input N/@. No Internal Connection Vas’ Ground Supply Voltage (SV) © Supply Voltage (7 5V) Vos. Supply Voltage (=12V)EMM SEMI 4200 150NSEC, STATIC, TTL IN/OUT, 4096x1 N-MOS RAM RECOMMENDED OPERATING CONDITIONS Taso G1970.6 ee PARAMETER Syuscl | MN ont ‘Substrate Voltage vee 5 Inout Low Love v 4 ‘Chip Select igh Lovel ‘ 8 5 DC ELECTRICAL CHARACTERISTICS (Ful Overstng Vollage an Temperature Range Uness Cirense Notoz ed et soe cnamscremsnics —, rMBOL IN | max | Min | AX “UT | Soe becer nt cent le oe OuputCuren Unedsces) "ke =o) io a0 a fram “Soo “ao ee, wee - i Se | Substrate Current. = = 3 ees 7 - ee ee yew Twa TOC e358, - 6 - 6 oma YS READ CYCLE — AC CHARACTERISTICS Il "e200 22008 ___chanactensrics SYMBOL MIN [Max MINT MAK UNIT CONDITIONS. Chip Select essPuise ist "Team | 200 190 ne ChipselectRiseane FalTine” fea er’ = 100 =| TBD ne eae Up Time pero geo tea OPERATING [Loveie time. tortor 1008 go 7 =) on a AND Data Hota Tire too 100” 7 ng TEMPERATURE uur Recovery Tine ee is | Read Recovery Tine ten 188 i= ne WRITE CYCLE — AC CHARACTERISTICS T 2008 003 __chapacrenisrics syMao Min Tmax wn [MAX UNIT CONDITIONS: Gh Select wrte Pulse wet Tous 200 vp Select Aigo and Fal Time" Tox a a a) onthe [Setup Tine w oo = oe pone ‘Gye Time tors te 80 Dw ‘AND “rypica Gp Selact ise ana Fal fime (Tex ana Te i 1Ors For Ress and Wnt Oye! CAPACITANCE (Over Ful Temperature Range an Worst Caps Votags Con i pease | mai TT ‘UN [ONO Sa ae Me. Sv ‘Output Capacitance {A Subsidiary of Electronic Memories & Magnetics Corporation « 3883 North 28th Avenue, Phoenix, Arizona 86017 » (602) 268-0202EMM SEMI 4200 150NSEC, STATIC, TTL IN/OUT, 4096x1 N-MOS RAM ABSOLUTE MAXIMUM RATINGS (See Note 1) (Referenced to GND) f RATING symeo.! VALUE [UNIT] This device contains circuitry to protect the inputs against damage Yoo | =e ial vac | due to igh state voltages o electric Helen nonever ts adised Supply Vohages Ver [Sto=7 [vse] that normal precautfonebe taken to avoid application of any Wco_ | S12 7-{_¥ée | Voltage nigh than maximum rated voltagesto this Nigh input &Oulput Vahages } impedance circu, {Except Chip Select) Vi.Wo | Vee to 15) Vde NOTE 1: Permanent device damage may occur it ABSOLUTE Chip Select Input Votage | Ves Vac | MAXIMUM RATINGS are oxcesdes. Functional operation should Power Dissipation Po W | __berestricted to RECOMMENDED OPERATING CONDITIONS ao 4 Exposure to higher than recommended or maximum voltages Tea et ice | tae | oro-70 | ¢ | extended periods of ime couldattect device reliably Sorage Temperature Range] es to==se0letcul Menor eee eee Figure 1 — READ CYCLE oN STABLE —f EMM sew {A Subsidiary of Electronic Memories & Magnetics Corporation + 3883 North 28th Avenue, Phoenix, Arizona 85017 « (602) 263-0202EMM SEMI 4200 150NSEC, STATIC, TTL IN/OUT, 4096x1 N-MOS RAM Figure 3. OPERATING IDD AS A FUNCTION OF CYCLE TIME Figure 4. MEMORY CELL Figure 5. OUTPUT TEST LOAD deem eS Ln na RAR Figure 6. TYPICAL CHIP SELECT DRIVER FUNCTIONAL DESCRIPTION EMM/SEMI 4200 is a 4096 bit static RAM with memory cells organized in an array of 64 rows by 64 columns (4096 words x 1 bit). Each memory cell is addressed by simul- taneously decoding the X addresses (Ac through As) forthe rows and the Y addresses (Ac through A) for the columns. Data is written or read on separate input (D1) and output (BO) pins. Logic level 1 is represented by ahigh state on pin Di butis represented on DO by a low state. The operation of the memory is controlled by chip select (CS) and read/write (R7W). When Gis high, all pins are in an inopera- tive high impedance state, and power is supplied only to the memory elements. When GSis low, the memory is enabled for reading or writing, The negative going edge of CS begins timing for a read cycle. Dataon R/W and address pins (Au) must be stable for time Tu. R/Wand An will then have been latched into D type flip flops and no longer need to beheld stable. Output data wil be pre- sented on DG within time Ta and will remain until time Tos after CS goes high. Data will then be invalid. After time Te another read or write cycle can be initiated The negative going edge of GS also begins timing for a write cycle. A7W, Ax and DI must be held stable for time Tx. These inputs will then have been latched and DI will be entered within time Tesw. Another read or write cycle can be initiated after time Te The memory cells (because they are cross coupled high impedance static cells) will retain data down to Veo ~ 4V, Vas ~ —4V.EMM. SEMI 4200 1S0NBEC; STATIO, TTL IN/OUT, 4086x1 N-MOS FAR CERAMIC PACKAGE DIMENSIONS aS C+ PLASTIC PACKAGE DIMENSIONS.ORDERING INFORMATION Spood 3 Part Number Access cycle Package ‘Temperature Range = 4200406 200 350 Ceramic "6 to ~70°C 4200A0P. 200 350 Plastic O°C to ~70°C 42008CC 450 300 Ceramic 0°C 10 ~70°C 4200BCP 180 300, Plastic OC to ~70"C WARNING: MOS CIRCUITS ARE SUBJECT TO DAMAGE FROM STATIC DISCHARGE Internal static discharge circuits are provided to minimize part damage due to environmental static electrical charge build-ups. Industry established recommen- gations for handling MOS circuits include: 1, Ship and store product in conductive shipping tubes or in conductive foam plastic. Never ship or store product in non-conductive plastic containers or non-conductive plastic foam material Handle MOS parts only at conductive work stations | : 3, Ground all assembly and repair tools. | 8 Represented in Your Area By EMM sem A Subsidiary of Electronic Memories & Magnetics Corporation ‘3883 North 28th Avenue, Phoenix, Arizona 85017 Telephone (602) 263-0202 * TWX 910-951-1383