Power Electronic-EE IIT Kharagpur

Module
1
Power Semiconductor
Devices
Version 2 EE IIT, Kharagpur 1
Lesson
1
Power Electronics
Introduction
This lesson provides the reader the following:
(i) Create an awareness of the general nature of Power electronic equipment;

(ii) Brief idea about topics of study involved,
(iii) The key features of the principal Power Electronic Devices;
(iv) An idea about which device to choose for a particular application.
(v) A few issues like base drive and protection of PE devices and equipment common to
most varieties.
Power Electronics is the art of converting electrical energy from one form to another in an
efficient, clean, compact, and robust manner for convenient utilisation.
A passenger lift in a modern building equipped with a Variable-Voltage-Variable-Speed

induction-machine drive offers a comfortable ride and stops exactly at the floor level. Behind the
scene it consumes less power with reduced stresses on the motor and corruption of the utility
mains.
Fig. 1.1 The block diagram of a typical Power Electronic converter

Power Electronics involves the study of
• Power semiconductor devices - their physics, characteristics, drive requirements and their
protection for optimum utilisation of their capacities,
• Power converter topologies involving them,
• Control strategies of the converters,
• Digital, analogue and microelectronics involved,
• Capacitive and magnetic energy storage elements,
• Rotating and static electrical devices,
• Quality of waveforms generated,
• Electro Magnetic and Radio Frequency Interference,

• Thermal Management
The typical converter in Fig. 1.1 illustrates the multidisciplinary nature of this subject.
How is Power electronics distinct from linear electronics?

It is not primarily in their power handling capacities.
While power management IC's in mobile sets working on Power Electronic principles are
meant to handle only a few milliwatts, large linear audio amplifiers are rated at a few thousand
watts.
The utilisation of the Bipolar junction transistor, Fig. 1.2 in the two types of amplifiers best
symbolises the difference. In Power Electronics all devices are operated in the switching mode -
either 'FULLY-ON' or 'FULLY-OFF' states. The linear amplifier concentrates on fidelity in
signal amplification, requiring transistors to operate strictly in the linear (active) zone, Fig 1.3.
Saturation and cutoff zones in the VCE - IC plane are avoided. In a Power electronic switching
amplifier, only those areas in the VCE - IC plane which have been skirted above, are suitable. On-
state dissipation is minimum if the device is in saturation (or quasi-saturation for optimising
other losses). In the off-state also, losses are minimum if the BJT is reverse biased. A BJT switch
will try to traverse the active zone as fast as possible to minimise switching losses.
Fig. 1.2 Typical Bipolar transistor based (a) linear (common emitter) (voltage)
amplifier stage and (b) switching (power) amplifier

Fig 1.3 Operating zones for operating a Bipolar Junction Transistor as a linear and a
switching amplifier
Linear operation Switching operation

Active zone selected: Active zone avoided :
Good linearity between input/output High losses, encountered only during
transients
Saturation & cut-off zones avoided: poor Saturation & cut-off (negative bias) zones
linearity selected: low losses
Transistor biased to operate around No concept of quiescent point
quiescent point
Common emitter, Common collector, Transistor driven directly at base - emitter
common base modes and load either on collector or emitter
Output transistor barely protected Switching-Aid-Network (SAN) and other
protection to main transistor
Utilisation of transistor rating of secondary Utilisation of transistor rating optimised

importance

An example illustrating the linear and switching solutions to a power supply specification will
emphasise the difference.
Spec: Input : 230 V, 50 Hz, Output: 12 V regulated DC, 20 W
Ferrite core HF transfr:

Light, efficient
Series regulator -
high losses
230 V
230 V
Line freq transformer: (a) (b)

heavy, lossy High-freq Duty-ratio
(ON/OFF) control
- low losses
Fig. 1.4 (a) A Linear regulator and (b) a switching regulator solution of the specification
above
The linear solution, Fig. 1.4 (a), to this quite common specification would first step down the
supply voltage to 12-0-12 V through a power frequency transformer. The output would be
rectified using Power frequency diodes, electrolytic capacitor filter and then series regulated
using a chip or a audio power transistor. The tantalum capacitor filter would follow. The balance
of the voltage between the output of the rectifier and the output drops across the regulator device
which also carries the full load current. The power loss is therefore considerable. Also, the step-
down iron-core transformer is both heavy, and lossy. However, only twice-line-frequency ripples
appear at the output and material cost and technical know-how required is low.
In the switching solution Fig. 1.4 (b) using a MOSFET driven flyback converter, first the line
voltage is rectified and then isolated, stepped-down and regulated. A ferrite-core high-frequency
(HF) transformer is used. Losses are negligible compared to the first solution and the converter is
extremely light. However significant high frequency (related to the switching frequency) noise
appear at the output which can only be minimised through the use of costly 'grass' capacitors.
Power Semiconductor device - history

Power electronics and converters utilizing them made a head start when the first device the
Silicon Controlled Rectifier was proposed by Bell Labs and commercially produced by General
Electric in the earlier fifties. The Mercury Arc Rectifiers were well in use by that time and the
robust and compact SCR first started replacing it in the rectifiers and cycloconverters. The
necessity arose of extending the application of the SCR beyond the line-commutated mode of
action, which called for external measures to circumvent its turn-off incapability via its control
terminals. Various turn-off schemes were proposed and their classification was suggested but it
became increasingly obvious that a device with turn-off capability was desirable, which would
permit it a wider application. The turn-off networks and aids were impractical at higher powers.
The Bipolar transistor, which had by the sixties been developed to handle a few tens of
amperes and block a few hundred volts, arrived as the first competitor to the SCR. It is superior
to the SCR in its turn-off capability, which could be exercised via its control terminals. This
permitted the replacement of the SCR in all forced-commutated inverters and choppers.
However, the gain (power) of the SCR is a few decades superior to that of the Bipolar transistor

and the high base currents required to switch the Bipolar spawned the Darlington. Three or more
stage Darlingtons are available as a single chip complete with accessories for its convenient
drive. Higher operating frequencies were obtainable with a discrete Bipolars compared to the
'fast' inverter-grade SCRs permitting reduction of filter components. But the Darlington's
operating frequency had to be reduced to permit a sequential turn-off of the drivers and the main
transistor. Further, the incapability of the Bipolar to block reverse voltages restricted its use.
The Power MOSFET burst into the scene commercially near the end seventies. This device
also represents the first successful marriage between modern integrated circuit and discrete
power semiconductor manufacturing technologies. Its voltage drive capability – giving it again a
higher gain, the ease of its paralleling and most importantly the much higher operating
frequencies reaching upto a few MHz saw it replacing the Bipolar also at the sub-10 KW range
mainly for SMPS type of applications. Extension of VLSI manufacturing facilities for the
MOSFET reduced its price vis-à-vis the Bipolar also. However, being a majority carrier device
its on-state voltage is dictated by the RDS(ON) of the device, which in turn is proportional to about
VDSS2.3 rating of the MOSFET. Consequently, high-voltage MOSFETS are not commercially
viable.
Improvements were being tried out on the SCR regarding its turn-off capability mostly by
reducing the turn-on gain. Different versions of the Gate-turn-off device, the Gate turn-off
Thyristor (GTO), were proposed by various manufacturers - each advocating their own symbol
for the device. The requirement for an extremely high turn-off control current via the gate and
the comparatively higher cost of the device restricted its application only to inverters rated above
a few hundred KVA.
The lookout for a more efficient, cheap, fast and robust turn-off-able device proceeded in
different directions with MOS drives for both the basic thysistor and the Bipolar. The Insulated
Gate Bipolar Transistor (IGBT) – basically a MOSFET driven Bipolar from its terminal
characteristics has been a successful proposition with devices being made available at about 4
KV and 4 KA. Its switching frequency of about 25 KHz and ease of connection and drive saw
it totally removing the Bipolar from practically all applications. Industrially, only the MOSFET
has been able to continue in the sub – 10 KVA range primarily because of its high switching
frequency. The IGBT has also pushed up the GTO to applications above 2-5 MVA.
Subsequent developments in converter topologies – especially the three-level inverter

permitted use of the IGBT in converters of 5 MVA range. However at ratings above that the
GTO (6KV/6KA device of Mitsubishi) based converters had some space. Only SCR based
converters are possible at the highest range where line-commutated or load-commutated
converters were the only solution. The surge current, the peak repetition voltage and I2t ratings
are applicable only to the thyristors making them more robust, specially thermally, than the
transistors of all varieties.
1200V Version 3 ASIPM
Presently there are few hybrid devices and Intelligent Power Modules (IPM) are marketed by
some manufacturers. The IPMs have already gathered wide acceptance. The 4500 V, 1200 A
IEGT (injection-enhanced gate transistor) of Toshiba or the 6000 V, 3500 A IGCT (Integrated
Gate Commutated Thyristors) of ABB which are promising at the higher power ranges.
However these new devices must prove themselves before they are accepted by the industry at
large.
Silicon carbide is a wide band gap semiconductor with an energy band gap wider than about
2 eV that possesses extremely high thermal, chemical, and mechanical stability. Silicon carbide
is the only wide band gap semiconductor among gallium nitride (GaN, EG = 3.4 eV), aluminum
nitride (AlN, EG = 6.2 eV), and silicon carbide that possesses a high-quality native oxide suitable
for use as an MOS insulator in electronic devices The breakdown field in SiC is about 8 times
higher than in silicon. This is important for high-voltage power switching transistors. For
example, a device of a given size in SiC will have a blocking voltage 8 times higher than the
same device in silicon. More importantly, the on-resistance of the SiC device will be about two
decades lower than the silicon device. Consequently, the efficiency of the power converter is
higher. In addition, SiC-based semiconductor switches can operate at high temperatures
(~600 C) without much change in their electrical properties. Thus the converter has a higher
reliability. Reduced losses and allowable higher operating temperatures result in smaller heatsink
size. Moreover, the high frequency operating capability of SiC converters lowers the filtering
requirement and the filter size. As a result, they are compact, light, reliable, and efficient and
have a high power density. These qualities satisfy the requirements of power converters for most
applications and they are expected to be the devices of the future.
Ratings have been progressively increasing for all devices while the newer devices offer
substantially better performance. With the SCR and the pin-diodes, so called because of the
sandwiched intrinsic ‘i’-layer between the ‘p’ and ‘n’ layers, having mostly line-commutated
converter applications, emphasis was mostly on their static characteristics - forward and reverse
voltage blocking, current carrying and over-current ratings, on-state forward voltage etc and also
on issues like paralleling and series operation of the devices. As the operating speeds of the
devices increased, the dynamic (switching) characteristics of the devices assumed greater
importance as most of the dissipation was during these transients. Attention turned to the
development of efficient drive networks and protection techniques which were found to enhance
the performance of the devices and their peak power handling capacities. Issues related to
paralleling were resolved by the system designer within the device itself like in MOSFETS,
while the converter topology was required to take care of their series operation as in multi-level
converters.
The range of power devices thus developed over the last few decades can be represented as a
tree, Fig. 1.5, on the basis of their controllability and other dominant features.

POWER SEMICONDUCTOR
DEVICES
UNCONTROLLED CONTROLLED
RECTIFIERS ACCESSORIES REGENERATIVE NON-REGENERATIVE INTEGRATED
POWER SILICON SCR BJT IGCT

DIAC TRIAC MOSFET PIC
DIODES
Zenner GTO IGBT INTELLIGENT
FREDS
MOV POWER MODULES
SCHOTTKY
Fig. 1.5 Power semiconductor device variety
Power Diodes
diF /dt
t0 t1 t2 SNAPPY
SOFT
Q1 Q2
Δ to
IRM
VRM
Fig. 1.6 Typical turn-off dynamics of a soft and a 'snappy' diode'
Silicon Power diodes are the successors of Selenium rectifiers having significantly improved
forward characteristics and voltage ratings. They are classified mainly by their turn-off
(dynamic) characteristics Fig. 1.6. The minority carriers in the diodes require finite time - trr
(reverse recovery time) to recombine with opposite charges and neutralise. Large values of Qrr (=
Q1 + Q2) - the charge to be dissipated as a negative current when the and diode turns off and trr
(= t2 - t0) - the time it takes to regain its blocking features, impose strong current stresses on the
controlled device in series. Also a 'snappy' type of recovery of the diode effects high di/dt
voltages on all associated power device in the converter because of load or stray inductances
present in the network. There are broadly three types of diodes used in Power electronic
applications:
Line-frequency diodes: These PIN diodes with general-purpose rectifier type applications, are
available at the highest voltage (~5kV) and current ratings (~5kA) and have excellent over-
current (surge rating about six times average current rating) and surge-voltage withstand
capability. They have relatively large Qrr and trr specifications.

Fast recovery diodes: Fast recovery diffused diodes and fast recovery epitaxial diodes, FRED's,
have significantly lower Qrr and trr (~ 1.0 sec). They are available at high powers and are
mainly used in association with fast controlled-devices as free-wheeling or DC-DC choppers and
rectifier applications. Fast recovery diodes also find application in induction heating, UPS and
traction.
Schottky rectifiers: These are the fastest rectifiers being majority carrier devices without any
Qrr.. However, they are available with voltage ratings up to a hundred volts only though current
ratings may be high. Their conduction voltages specifications are excellent (~0.2V). The freedom
from minority carrier recovery permits reduced snubber requirements. Schottky diodes face no
competition in low voltage SPMS applications and in instrumentation.
Silicon Controlled Rectifier (SCR)

The Silicon Controlled Rectifier is the most popular of the thyristor family of four layer
regenerative devices. It is normally turned on by the application of a gate pulse when a forward
bias voltage is present at the main terminals. However, being regenerative or 'latching', it cannot
be turned off via the gate terminals specially at the extremely high amplification factor of the
gate. There are two main types of SCR's.
Converter grade or Phase Control thyristors These devices are the work horses of the
Power Electronics. They are turned off by natural (line) commutation and are reverse biased at
least for a few milliseconds subsequent to a conduction period. No fast switching feature is
desired of these devices. They are available at voltage ratings in excess of 5 KV starting from
about 50 V and current ratings of about 5 KA. The largest converters for HVDC transmission are
built with series-parallel combination of these devices. Conduction voltages are device voltage
rating dependent and range between 1.5 V (600V) to about 3.0 V (+5 KV). These devices are
unsuitable for any 'forced-commutated' circuit requiring unwieldy large commutation
components.
The dynamic di/dt and dv/dt capabilities of the SCR have vastly improved over the years
borrowing emitter shorting and other techniques adopted for the faster variety. The requirement
for hard gate drives and di/dt limting inductors have been eliminated in the process.
Inverter grade thyristors: Turn-off times of these thyristors range from about 5 to 50 μsecs
when hard switched. They are thus called fast or 'inverter grade' SCR's. The SCR's are mainly
used in circuits that are operated on DC supplies and no alternating voltage is available to turn
them off. Commutation networks have to be added to the basic converter only to turn-off the
SCR's. The efficiency, size and weight of these networks are directly related to the turn-off time,
tq of the SCR. The commutation circuits utilised resonant networks or charged capacitors. Quite
a few commutation networks were designed and some like the McMurray-Bedford became
widely accepted.
Asymmetrical, light-activated, reverse conducting SCR's Quite a few varieties of the

basic SCR have been proposed for specific applications. The Asymmetrical thyristor is
convenient when reactive powers are involved and the light activated SCR assists in paralleling
or series operation.

MOSFET
The Power MOSFET technology has mostly reached maturity and is the most popular device
for SMPS, lighting ballast type of application where high switching frequencies are desired but
operating voltages are low. Being a voltage fed, majority carrier device (resistive behaviour)
with a typically rectangular Safe Operating Area, it can be conveniently utilized. Utilising shared
manufacturing processes, comparative costs of MOSFETs are attractive. For low frequency
applications, where the currents drawn by the equivalent capacitances across its terminals are
small, it can also be driven directly by integrated circuits. These capacitances are the main
hindrance to operating the MOSFETS at speeds of several MHz. The resistive characteristics of
its main terminals permit easy paralleling externally also. At high current low voltage
applications the MOSFET offers best conduction voltage specifications as the RDS(ON)
specification is current rating dependent. However, the inferior features of the inherent anti-
parallel diode and its higher conduction losses at power frequencies and voltage levels restrict its
wider application.
The IGBT
It is a voltage controlled four-layer device with the advantages of the MOSFET driver
and the Bipolar Main terminal. IGBTs can be classified as punch-through (PT) and non-punch-
through (NPT) structures. In the punch-through IGBT, a better trade-off between the forward
voltage drop and turn-off time can be achieved. Punch-through IGBTs are available up to about
1200 V. NPT IGBTs of up to about 4 KV have been reported in literature and they are more
robust than PT IGBTs particularly under short circuit conditions. However they have a higher
forward voltage drop than the PT IGBTs. Its switching times can be controlled by suitably
shaping the drive signal. This gives the IGBT a number of advantages: it does not require
protective circuits, it can be connected in parallel without difficulty, and series connection is
possible without dv/dt snubbers. The IGBT is presently one of the most popular device in view
of its wide ratings, switching speed of about 100 KHz a easy voltage drive and a square Safe
Operating Area devoid of a Second Breakdown region.
The GTO
The GTO is a power switching device that can be turned on by a short pulse of gate current and
turned off by a reverse gate pulse. This reverse gate current amplitude is dependent on the anode
current to be turned off. Hence there is no need for an external commutation circuit to turn it off.
Because turn-off is provided by bypassing carriers directly to the gate circuit, its turn-off time is
short, thus giving it more capability for highfrequency operation than thyristors. The GTO
symbol and turn-off characteristics are shown in Fig. 30.3. GTOs have the I2t withstand
capability and hence can be protected by semiconductor fuses. For reliable operation of GTOs,
the critical aspects are proper design of the gate turn-off circuit and the snubber circuit.
Power Converter Topologies

A Power Electronic Converter processes the available form to another having a different
frequency and/or voltage magnitude. There can be four basic types of converters depending upon
the function performed:

CONVERSION
FROM/TO NAME FUNCTION SYMBOL
DC to DC Chopper Constant to variable DC or

variable to constant DC
DC to AC Inverter DC to AC of desired voltage and

frequency
~
AC to DC Rectifier AC to unipolar (DC) current

~
Cycloconverter,
AC to AC AC-PAC, AC of desired frequency and/or
~
Matrix
converter
magnitude from generally line
AC ~
Base / gate drive circuit

All discrete controlled devices, regenerative or otherwise have three terminals. Two of these are
the Main Terminals. One of the Main Terminals and the third form the Control Terminal. The
amplification factor of all the devices (barring the now practically obsolete BJT) are quite high,
though turn-on gain is not equal to turn-off gain. The drive circuit is required to satisfy the
control terminal characteristics to efficiently tun-on each of the devices of the converter, turn
them off, if possible, again optimally and also to protect the device against faults, mostly over-
currents. Being driven by a common controller, the drives must also be isolated from each other
as the potentials of the Main Terminal which doubles as a Control terminal are different at
various locations of the converter. Gate-turn-off-able devices require precise gate drive
waveform for optimal switching. This necessitates a wave-shaping amplifier. This amplifier is
located after the isolation stage.
Thus separate isolated power supplies are also required for each Power device in the
converter (the ones having a common Control Terminal - say the Emitter in an IGBT - may
require a few less). There are functionally two types of isolators: the pulse transformer which
can transmit after isolation, in a multi-device converter, both the un-shaped signal and power and
optical isolators which transmit only the signal. The former is sufficient for a SCR without
isolated power supplies at the secondary. The latter is a must for practically all other devices.
Fig. 1.7 illustrates to typical drive circuits for an IGBT and an SCR.

IGBT
Vref
COMPARATOR TIMER
Fig. 1.7 Simple gate-drive and protection circuit for a stand-alone IGBT and a SCR
Protection of Power devices and converters

Power electronic converters often operate from the utility mains and are exposed to the
disturbances associated with it. Even otherwise, the transients associated with switching circuits
and faults that occur at the load point stress converters and devices. Consequently, several
protection schemes must be incorporated in a converter. It is necessary to protect both the Main
Terminals and the control terminals. Some of these techniques are common for all devices and
converters. However, differences in essential features of devices call for special protection
schemes particular for those devices. The IGBT must be protected against latching, and similarly
the GTO's turn-off drive is to be disabled if the Anode current exceeds the maximum permissible
turn-off-able current specification. Power semiconductor devices are commonly protected
against:
1. Over-current;
2. di/dt;
3. Voltage spike or over-voltage;
4. dv/dt ;
5. Gate-under voltage;
6. Over voltage at gate;
7. Excessive temperature rise;
8. Electro-static discharge;
Semiconductor devices of all types exhibit similar responses to most of the stresses, however
there are marked differences. The SCR is the most robust device on practically all counts. That it
has an I2t rating is proof that its internal thermal capacities are excellent. A HRC fuse, suitably
selected, and in co-ordination with fast circuit breakers would mostly protect it. This sometimes
becomes a curse when the cost of the fuse becomes exorbitant. All transistors, specially the BJT
and the IGBT is actively protected (without any operating cost!) by sensing the Main Terminal
voltage, as shown in Fig. 1.7. This voltage is related to the current carried by the device. Further,
the transistors permit designed gate current waveforms to minimise voltage spikes as a
consequence of sharply rising Main terminal currents. Gate resistances have significant effect on
turn-on and turn-off times of these devices - permitting optimisation of switching times for the
reduction of switching losses and voltage spikes.

Protection schemes for over-voltages - the prolonged ones and those of short duration - are
guided by the energy content of the surges. Metal Oxide Varistors (MOV's), capacitive dynamic
voltage-clamps and crow-bar circuits are some of the strategies commonly used. For high dv/dt
stresses, which again have similar effect on all devices, R-C or R-C-D clamps are used
depending on the speed of the device. These 'snubbers' or 'switching-aid-networks', additionally
minimise switching losses of the device - thus reducing its temperature rise.
Gates of all devices are required to be protected against over-voltages (typically + 20 V)
specially for the voltage driven ones. This is achieved with the help of Zener clamps - the zener
being also a very fast-acting device.
Protection against issues like excessive case temperatures and ESD follow well-set practices.
Forced-cooling techniques are very important for the higher rated converters and whole
environments are air-cooled to lower the ambient.
Objective type questions

Qs#1 Which is the Power semiconductor device having
a) Highest switching speed;

b) Highest voltage / current ratings;
c) Easy drive features;
d) Can be most effectively paralleled;
e) Can be protected against over-currents with a fuse;
f) Gate-turn off capability with regenerative features;
g) Easy drive and High power handling capability
Ans: a) MOSFET; b) SCR; c) MOSFET; d) MOSFET; e) SCR ; (f) GTO; (g) IGBT
Qs#2 An SCR requires 50 mA gate current to switch it on. It has a resistive load and is supplied
from a 100 V DC supply. Specify the Pulse transformer details and the circuit following it, if the
driver circuit supply voltage is 10 V and the gate-cathode drop is about 1 V.
Ans: The most important ratings of the Pulse transformer are its volt-secs rating, the isolation
voltage and the turns ratio.
The volt-secs is decided by the product of the primary pulse-voltage multiplied by the period for
which the pulse is applied to the winding
If the primary pulse voltage = (Supply voltage – drive transistor drop)

The turn-on time of he SCR may be in the range 50 μsecs for an SCR of this rating.
Consequently the volt secs may be in the range of 9 x 50 = 450 μvolt-secs
The Pulse transformer may be chosen as: 1:1, 450 μVs, Visol = 2.5 KV, IM = 150 mA
The circuit shown in Fig. 1.7 may be used. Diodes 1N4002
Series resistance
= (Supply voltage – drive transistor drop – gate-cathode drop)/100mA
= (10 –1 –1) / 100 E-3
= 80 Ohm
= 49 or 57 Ohm (nearest available lower value)

Module
1
Power Semiconductor
Devices
Lesson
2
Constructional Features,
Operating Principle,
Characteristics and
Specification of Power
Semiconductor Diode
Instructional Objective
On Completion the student will be able to
1. Draw the spatial distribution of charge density, electric field and electric potential in a
step junction p-n diode.
2. Calculate the voltage drop across a forward biased diode for a given forward current and
vice-verse.
3. Identify the constructional features that distinguish a power diode from a signal level
diode.
4. Differentiate between different reverse voltage ratings found in a Power Diode speciation
sheet.
5. Identify the difference between the forward characteristic of a power diode and a signal
level diode and explain it.
6. Evaluate the forward current specifications of a diode for a given application.
7. Draw the “Turn On” and “Turn Off” characteristics of a power diode.
8. Define “Forward recovery voltage”, “Reverse recovery current” “Reverse Recovery
charge” as applicable to a power diode.

Power Semiconductor Diodes
2.1 Introduction
Power semiconductor diode is the “power level” counter part of the “low power signal diodes”
with which most of us have some degree of familiarity. These power devices, however, are
required to carry up to several KA of current under forward bias condition and block up to
several KV under reverse biased condition. These extreme requirements call for important
structural changes in a power diode which significantly affect their operating characteristics.
These structural modifications are generic in the sense that the same basic modifications are
applied to all other low power semiconductor devices (all of which have one or more p-n
junctions) to scale up their power capabilities. It is, therefore, important to understand the nature
and implication of these modifications in relation to the simplest of the power devices, i.e., a
power semiconductor diode.
2.2 Review of Basic p-n Diode Characteristics

A p-n junction diode is formed by placing p and n type semiconductor materials in intimate
contact on an atomic scale. This may be achieved by diffusing acceptor impurities in to an n type
silicon crystal or by the opposite sequence.
In an open circuit p-n junction diode, majority carriers from either side will defuse across the
junction to the opposite side where they are in minority. These diffusing carriers will leave
behind a region of ionized atoms at the immediate vicinity of the metallurgical junction. This
region of immobile ionized atoms is called the space charge region. This process continues till
the resultant electric field (created by the space charge density) and the potential barrier at the
junction builds up to sufficient level to prevent any further migration of carriers. At this point the
p-n junction is said to be in thermal equilibrium condition. Variation of the space charge density,
the electric field and the potential along the device is shown in Fig 2.1 (a).

(a) (b) (c)
Fig 2.1: Space change density the electric field and the electric potential in side a p-n
junction under (a) thermal equilibrium condition, (b) reverse biased condition,
(c) forward biased condition.
When an external voltage is applied with p side move negative then the n side the junction is
said to be under reverse bias condition. This reverse bias adds to the height of the potential
barrier. The electric field strength at the junction and the width of the space change region (also
called “the depletion region” because of the absence of free carriers) also increases. On the other
hand, free minority carrier densities (np in the p side and pn in the n side) will be zero at the edge
of the depletion region on either side (Fig 2.1 (b)). This gradient in minority carrier density
causes a small flux of minority carriers to defuse towards the deletion layer where they are swept
immediately by the large electric field into the electrical neutral region of the opposite side. This
will constitute a small leakage current across the junction from the n side to the p side. There
will also be a contribution to the leakage current by the electron hole pairs generated in the space
change layer by the thermal ionization process. These two components of current together is
called the “reverse saturation current Is” of the diode. Value of Is is independent of the reverse
voltage magnitude (up to a certain level) but extremely sensitive to temperature variation.
When the applied reverse voltage exceeds some threshold value (for a given diode) the reverse
current increases rapidly. The diode is said to have undergone “reverse break down”.
Reverse break down is caused by "impact ionization" as explained below. Electrons accelerated
by the large depletion layer electric field due to the applied reverse voltage may attain sufficient
knick energy to liberate another electron from the covalent bonds when it strikes a silicon atom.
The liberated electron in turn may repeat the process. This cascading effect (avalanche) may
produce a large number of free electrons very quickly resulting in a large reverse current. The
power dissipated in the device increases manifold and may cause its destruction. Therefore,
operation of a diode in the reverse breakdown region must be avoided.

When the diode is forward biased (i.e., p side more positive than n side) the potential barrier is
lowered and a very large number of minority carriers are injected to both sides of the junction.
The injected minority carriers eventually recombines with the majority carries as they defuse
further into the electrically neutral drift region. The excess free carrier density in both p and n
side follows exponential decay characteristics. The characteristic decay length is called the
"minority carrier diffusion length"
Carrier density gradients on either side of the junction are supported by a forward current IF
(flowing from p side to n side) which can be expressed as
IF = IS ( exp ( qv/kT ) ) -1 (2.1)

Where Is = Reverse saturation current ( Amps)
v = Applied forward voltage across the device (volts)
q = Change of an electron
k = Boltzman’s constant
T = Temperature in Kelvin
From the foregoing discussion the i-v characteristics of a p-n junction diode can be drawn as
shown in Fig 2.2. While drawing this characteristics the ohmic drop in the bulk of the
semiconductor body has been neglected.
Fig 2.2: Volt-Ampere ( i-v ) characteristics of a p-n junction diode
Exercise 2.1
(1) Fill in the blanks with the appropriate word(s).
(i) The width of the space charge region increases as the applied ______________ voltage
increases.
(ii) The maximum electric field strength at the center of the depletion layer increases
with _______________ in the reverse voltage.
(iii) Reverse saturation current in a power diode is extremely sensitive to ___________
variation.
(iv) Donor atoms are _____________________ carrier providers in the p type and
_________________ carrier providers in the n type semiconductor materials.
(v) Forward current density in a diode is __________________________ proportional to the
life time of carriers.
Answer: (i) Reverse, (ii) increase, (iii) temperature, (iv) Minority Majority, (v) inversely
(2) A p-n junction diode has a reverse saturation current rating of 50 nA at 32°C. What
should be the value of the forward current for a forward voltage drop of 0.5V. Assume VT =
KT/q at 32°C = 26 mv.
Answer
⎛ V ⎞
I F = I s ⎜ e VT - 1 ⎟ , Is = 5×10-8 A, VT = 26×10-3 V V = 0.5V
⎝ ⎠
∴ I F = 11.24 Am ps.
di
(3) For the diode of Problem-2 calculate the dynamic ac resistance ra c = F d v F at 32°C and a
forward voltage drop of 0.5V.
Answer:
⎛ VF VT ⎞ diF Is VF
iF = Is ⎜ e -1⎟ ∴ = e VT
⎝ ⎠ dVF VT
N ow I s = 5 × 10 -8 A , V F = 0.5V ,
-3
VT = 26 ×10 V at 32o C
V
dVF V - F
∴ = ra c = T e V T = 2 .3 1 3 m Ω
diF Is
2.3 Construction and Characteristics of Power Diodes

As mention in the introduction Power Diodes of largest power rating are required to conduct
several kilo amps of current in the forward direction with very little power loss while blocking
several kilo volts in the reverse direction. Large blocking voltage requires wide depletion layer in
order to restrict the maximum electric field strength below the “impact ionization” level. Space
charge density in the depletion layer should also be low in order to yield a wide depletion layer
for a given maximum Electric fields strength. These two requirements will be satisfied in a
lightly doped p-n junction diode of sufficient width to accommodate the required depletion layer.
Such a construction, however, will result in a device with high resistively in the forward
direction. Consequently, the power loss at the required rated current will be unacceptably high.
On the other hand if forward resistance (and hence power loss) is reduced by increasing the
doping level, reverse break down voltage will reduce. This apparent contradiction in the
requirements of a power diode is resolved by introducing a lightly doped “drift layer” of required

thickness between two heavily doped p and n layers as shown in Fig 2.3(c). Fig 2.3 (a) and (b)
shows the circuit symbol and the photograph of a typical power diode respectively.
(b)
Fig. 2.3: Diagram of a power; (a) circuit symbol (b) photograph; (c) schematic cross
section.
To arrive at the structure shown in Fig 2.3 (c) a lightly doped n- epitaxial layer of specified width
(depending on the required break down voltage) and donor atom density (NdD) is grown on a
heavily doped n+ substrate (NdK donor atoms.Cm -3) which acts as the cathode. Finally the p-n
junction is formed by defusing a heavily doped (NaA acceptor atoms.Cm-3) p+ region into the
epitaxial layer. This p type region acts as the anode.
Impurity atom densities in the heavily doped cathode (Ndk .Cm -3) and anode (NaA.Cm -3) are
approximately of the same order of magnitude (10 19 Cm -3) while that of the epitaxial layer (also
called the drift region) is lower by several orders of magnitude (NdD ≈ 10 14 Cm-3). In a low
power diode this drift region is absent. The Implication of introducing this drift region in a power
diode is explained next.
2.3.1 Power Diode under Reverse Bias Conditions Back
As in the case of a low power diode the applied reverse voltage is supported by the depletion
layer formed at the p+ n- metallurgical junction. Overall neutrality of the space change region
dictates that the number of ionized atoms in the p+ region should be same as that in the n- region.
However, since NdD << NaA, the space charge region almost exclusively extends into the n- drift

region. Now the physical width of the drift region (WD) can be either larger or smaller than the
depletion layer width at the break down voltage. Consequently two type of diodes exist, (i) non
punch through type, (ii) punch through type. In “non-punch through” diodes the depletion layer
boundary doesn’t reach the end of the drift layer. On the other hand in “punch through” diodes
the depletion layer spans the entire drift region and is in contact with the n+ cathode. However,
due to very large doping density of the cathode, penetration of drift region inside cathode is
negligible. Electric field strength inside the drift region of both these type of diodes at break
down voltage is shown in Fig 2.4.
Fig 2.4: Electric field strength in reverse biased power Diodes; (a) Non-punch through
type; (b) punch through type.
In non-punch through type diodes the electric field strength is maximum at the p+ n- junction and
decrease to zero at the end of the depletion region. Where as, in the punch through construction
the field strength is more uniform. In fact, by choosing a very lightly doped n- drift region,
Electric field strength in this region can be mode almost constant. Under the assumption of
uniform electric field strength it can be shown that for the same break down voltage, the “punch
through” construction will require approximately half the drift region width of a comparable “
non - punch through” construction.
Lower drift region doping in a “punch through” diode does not carry the penalty of higher
conduction lasses due to “conductivity modulation” to be discussed shortly. In fact, reduced
width of the drift region in these diodes lowers the on-state voltage drop for the same forward
current density compared to a non-punch through diode.
Under reverse bias condition only a small leakage current (less than 100mA for a rated forward
current in excess of 1000A) flows in the reverse direction (i.e from cathode to anode). This
reverse current is independent of the applied reverse voltage but highly sensitive to junction
temperature variation. When the applied reverse voltage reaches the break down voltage, reverse
current increases very rapidly due to impact ionization and consequent avalanche multiplication
process. Voltage across the device dose not increase any further while the reverse current is
limited by the external circuit. Excessive power loss and consequent increase in the junction
temperature due to continued operation in the reverse brake down region quickly destroies the
diode. Therefore, continued operation in the reverse break down region should be avoided. A
typical I-V characteristic of a power diode under reverse bias condition is shown in Fig 2.5.

Fig 2.5: Reverse bias i-v characteristics of a power Diode.
A few other important specifications of a power Diode under reverse bias condition usually
found in manufacturer’s data sheet are explained below.
DC Blocking Voltage (VRDC): Maximum direct voltage that can be applied in the reverse
direction (i.e cathode positive with respect to anode) across the device for indefinite period of
time. It is useful for selecting free-wheeling diodes in DC-DC Choppers and DC-AC voltage
source inverter circuits.
RMS Reverse Voltage (VRMS): It is the RMS value of the power frequency (50/60 HZ) since
wave voltage that can be directly applied across the device. Useful for selecting diodes for
controlled / uncontrolled power frequency line commutated AC to DC rectifiers. It is given by
the manufacturer under the assumption that the supply voltage may rise by 10% at the most. This
rating is different for resistive and capacitive loads.
Peak Repetitive Reverse Voltage (VRRM): This is the maximum permissible value of the
instantiations reverse voltage appearing periodically across the device. The time period between
two consecutive appearances is assumed to be equal to half the power cycle (i.e 10ms for 50 HZ
supply). This type of period reverse voltage may appear due to “commutation” in a converter.
Peak Non-Repetitive Reverse Voltage (VRSM): It is the maximum allowable value of the
instantaneous reverse voltage across the device that must not recur. Such transient reverse
voltage can be generated by power line switching (i.e circuit Breaker opening / closing) or
lightning surges.
Fig. 2.6 shows the relationship among these different reverse voltage specifications.

Fig. 2.6: Reverse Voltage ratings of a power diode; (a) Supply voltage wave form; (b)
Reverse i-v characteristics
2.3.2 Power Diode under Forward Bias Condition

In the previous section it was shown how the introduction of a lightly doped drift region in the p-
n structure of a diode boosts its blocking voltage capacity. It may appear that this lightly doped
drift region will offer high resistance during forward conduction. However, the effective
resistance of this region in the ON state is much less than the apparent ohmic resistance
calculated on the basis of the geometric size and the thermal equilibrium carrier densities. This is
due to substantial injection of excess carriers from both the p+ and the n+ regions in the drift
region as explained next.
As the metallurgical p+ n- junction becomes forward biased there will be injection of excess p
type carrier into the n- side. At low level of injections (i.e δp << nno) all excess p type carriers
recombine with n type carriers in the n- drift region. However at high level of injection (i.e large
forward current density) the excess p type carrier density distribution reaches the n- n+ junction
and attracts electron from the n+ cathode. This leads to electron injection into the drift region
across the n- n+ junction with carrier densities δn = δp. This mechanism is called “double
injection”
Excess p and n type carriers defuse and recombine inside the drift region. If the width of the drift
region is less than the diffusion length of carries the spatial distribution of excess carrier density
in the drift region will be fairly flat and several orders of magnitude higher than the thermal
equilibrium carrier density of this region. Conductivity of the drift region will be greatly
enhanced as a consequence (also called conductivity modulation).
The voltage dropt across a forward conducting power diode has two components i.e
Vak = Vj + VRD (2.2)
Where Vj is the drop across the p+n- junction and can be calculated from equation (2.1) for a
given forward current jF. The component VRD is due to ohmic drop mostly in the drift region.
Detailed calculation shows
VRD ∞ JF WD (2.3)
Where JF is the forword current density in the diode and WD is the width of the drift region.
Therefore
Vak = Vj + RON IF (2.3)
The ohmic drop makes the forward i-v characteristic of a power diode more linear.

Fig 2.7: Characteristics of a forward biased power Diode; (a) Excess free carrier density
distribution; (b) i-v characteristics.
Both Vj and VAK have negative temperature coefficient as shown in the figure.
Few other important specifications related to forward bias operation of power diode as found in
manufacturer’s data sheet are explained next.
Maximum RMS Forward current (IFRMS): Due to predominantly resistive nature of the
forward voltage drop across a forward biased power diode, RMS value of the forward current
determines the conduction power loss. The specification gives the maximum allowable RMS
value of the forward current of a given wave shape (usually a half cycle sine wave of power
frequency) and at a specified case temperature. However, this specification can be used as a
guideline for almost all wave shapes of the forward current.
Maximum Average Forward Current (IFAVM): Diodes are often used in rectifier circuits
supplying a DC (average) current to be load. In such cases the average load current and the diode
forward current usually have a simple relationship. Therefore, it will be of interest to know the

maximum average current a diode can conduct in the forward direction. This specification gives
the maximum average value of power frequency half cycle sine wave current allowed to flow
through the diode in the forward direction. Average current rating of a diode decreases with
reduction in conduction angle due to increase in current “form factor”.
Both IFRMS and IFAVM ratings are given at a specified case temperature. If the case temperature
increases beyond this limit these ratings has to be reduced correspondingly. “Derating curves”
provide by the manufacturers give the relationship between IFAVM (IFRMS) with allowable case
temperature as shown in Fig. 2.8.
Fig 2.8: Derating curves for the forward current of a Power Diode.
Average Forward Power loss (PAVF): Almost all power loss in a diode occurs during forward
conduction state. The forward power loss is therefore an important parameter in designing the
cooling arrangement. Average forward power loss over a full cycle is specified by the
manufacturers as a function of the average forward current (IAVF) for different conduction angles
as shown in Fig 2.9.
Fig 2.9: Average forward power loss vs. average forward current of a power Diode.
Surge and Fault Current: In some rectifier applications a diode may be required to conduct
forward currents far in excess of its RMS or average forward current rating for some duration
(several cycles of the power frequency). This is called the repetitive surge forward current of a
diode. A diode is expected to operate normally after the surge duration is over.
On the other hand, fault current arising due to some abnormality in the power circuit may have a
higher peak valve but exists for shorter duration (usually less than an half cycle of the power
frequency). A diode circuit is expected to be disconnected from the power line following a fault.
Therefore, a fault current is a non repetitive surge current. Power diodes are capable of
withstanding both types of surge currents and this capability is expressed in terms of two surge
current ratings as discussed next.
Peak Repetitive surge current rating (IFRM): This is the peak valve of the repetitive surge
current that can be allowed to flow through the diode for a specific duration and for specified
conditions before and after the surge. The surge current waveform is assumed to be half
sinusoidal of power frequency with current pulses separated by “OFF” periods of equal duration.
The case temperature is usually specified at its maximum allowable valve before the surge. The
diode should be capable of withstanding maximum repetitive peak reverse voltage (VRRM) and
Maximum allowable average forward current (IFAVM) following the surge. The surge current
specification is usually given as a function of the surge duration in number of cycles of the
power frequency as shown in figure 2.10
Fig 2.10: Peak Repetitive surge current VS time curve of a power diode.
In case the surge current is specified only for a fixed number of cycles ‘m’
then the surge current specification applicable to some other cycle number ‘n’ can be found from
the approximate formula.
m
I FRM \ n = I \ (2.4)
n FRM m
Peak Non-Repetitive surge current (IFRM): This specification is similar to the previous one
except that the current pulse duration is assumed to be within one half cycle of the power

frequency. This specification is given as a function of the current pulse duration as shown in Fig
2.11.
Maximum surge current Integral (∫i2dt): This is a surge current related specification and gives
a measure of the heat energy generated inside the device during a non-repetitive surge. It is
useful for selecting the protective fuse to be connected in series with the diode. This specification
is also given as a function of the current pulse duration as shown Fig 2.11
Fig. 2.11: Non-repetitive surge current and surge current integral vs. current pulse width
characteristics of a power Diode.
Exercise 2.2
(1) Fill in the blanks with the appropriate word(s).
i. The ____________ region in a power diode increases its reverse voltage blocking
capacity.
ii. The maximum DC voltage rating (VRDC) of a power diode is useful for selecting
________________ diodes in a DC-DC chopper.
iii. The reverse breakdown voltage of a Power Diode must be greater than
________________ .
iv. The i-v characteristics of a power diode for large forward current is __________ .
v. The average current rating of a power diode _______________ with reduction in the
conduction angle due to increase in the current ___________________ .
vi. The derating curves of a Power diode provides relationship between the ______________
and the _________________ .
∫ i dt rating of a power diode is useful for selecting the ________________ .
2
vii.
Answer: (i) drift, (ii) free wheeling, (iii) VRSM, (iv) linear, (v) decrease, form factor, (vi)
IFAVM/IFRM, case temperature, (vii) protective fuse.

(2). (a) For the single phase half wove rectifier shown find out the VRRM rating of D.
(b) Will the required VRRM rating change if a inductor is placed between the diode and
n capacitor.
(c) What will be the required VRRM rating if the capacitor is removed. Assume a resistive
load.
(d) The source of the single phase rectifier circuit has an internal resistance of 2 Ω. Find
out the required Non repetitive peak surge current rating of the diode. Also find the i2t
rating of the protective fuse to be connected in series with the diode.
Answer: (a) During every positive half cycle of the supply the capacitor charges to the peak
value of the supply voltage. If the load disconnected the capacitor voltage will not change when
the supply goes through its negative peak as shown in the associated waveform. Therefore the
diode will be subjected to a reverse voltage equal to the peak to peak supply voltage in each
cycle. Hence, the required VRRM rating will be
VRRM = 2 × 2 × 230V = 650V

(b) When an inductor is connected between the diode and the capacitor the inductor current
will have some positive value at t = t1. If the load is disconnected the stored energy in the
inductor will charge the capacitor beyond the peak supply voltage. Since there is no discharge
path for the capacitor this voltage across the capacitor will be maintained when the supply
voltage goes through negative peak. Therefore, the diode will be subjected to a reverse voltage
greater than the peak to peak supply voltage. The required VRRM rating will increase.

(c) If the capacitor is removed and the load is resistive the voltage VKN during negative half
cycle of the supply will be zero since the load current will be zero. Therefore the reverse voltage
across the diode will be equal to the peak supply voltage. So the required VRRM rating will be
VRRM = 2 × 230V = 325 Volts
(d) Peak surge current will flow through the circuit when the load is accidentally short circuited.
The peak surge current rating will be
2 × 230
I FSM = A = 162.64 A
2
The peak non repetitive surge current should not recur. Therefore, the protective fuse (to
be connected in series with the diode) must blow during the negative half cycle following the
fault. Therefore the maximum i2t rating of the fuse is
π
∫i
2
dt = ∫ I 2 F S M S in 2 w td w t = π I 2 F S m = 4 1 .5 5 × 1 0 3 A 2 s e c
M ax o 2
2.3.3 Switching Characteristics of Power Diodes

Power Diodes take finite time to make transition from reverse bias to forward bias condition
(switch ON) and vice versa (switch OFF).
Behavior of the diode current and voltage during these switching periods are important due to the
following reasons.
• Severe over voltage / over current may be caused by a diode switching at different points
in the circuit using the diode.
• Voltage and current exist simultaneously during switching operation of a diode.
Therefore, every switching of the diode is associated with some energy loss. At high
switching frequency this may contribute significantly to the overall power loss in the
diode.
Observed Turn ON behavior of a power Diode: Diodes are often used in circuits with di/dt
limiting inductors. The rate of rise of the forward current through the diode during Turn ON has
significant effect on the forward voltage drop characteristics. A typical turn on transient is shown
in Fig. 2.12.

Fig. 2.12: Forward current and voltage waveforms of a power diode during Turn On
operation.
It is observed that the forward diode voltage during turn ON may transiently reach a significantly
higher value Vfr compared to the steady slate voltage drop at the steady current IF.
In some power converter circuits (e.g voltage source inverter) where a free wheeling diode is
used across an asymmetrical blocking power switch (i.e GTO) this transient over voltage may be
high enough to destroy the main power switch.
Vfr (called forward recovery voltage) is given as a function of the forward di/dt in the
manufacturer’s data sheet. Typical values lie within the range of 10-30V. Forward recovery time
(tfr) is typically within 10 us.
Observed Turn OFF behavior of a Power Diode: Figure 2.13 shows a typical turn off
behavior of a power diode assuming controlled rate of decrease of the forward current.

Fig. 2.13: Reverse Recovery characteristics of a power diode
Salient features of this characteristics are:

• The diode current does not stop at zero, instead it grows in the negative direction to Irr
called “peak reverse recovery current” which can be comparable to IF. In many power
electronic circuits (e.g. choppers, inverters) this reverse current flows through the main
power switch in addition to the load current. Therefore, this reverse recovery current has
to be accounted for while selecting the main switch.
• Voltage drop across the diode does not change appreciably from its steady state value till
the diode current reaches reverse recovery level. In many power electric circuits
(choppers, inverters) this may create an effective short circuit across the supply, current
being limited only by the stray wiring inductance. Also in high frequency switching
circuits (e.g, SMPS) if the time period t4 is comparable to switching cycle qualitative
modification to the circuit behavior is possible.
• Towards the end of the reverse recovery period if the reverse current falls too sharply,
(low value of S), stray circuit inductance may cause dangerous over voltage (Vrr) across
the device. It may be required to protect the diode using an RC snubber.
During the period t5 large current and voltage exist simultaneously in the device. At high
switching frequency this may result in considerable increase in the total power loss.
Important parameters defining the turn off characteristics are, peak reverse recovery current (Irr),
reverse recovery time (trr), reverse recovery charge (Qrr) and the snappiness factor S.
Of these parameters, the snappiness factor S depends mainly on the construction of the diode
(e.g. drift region width, doping lever, carrier life time etc.). Other parameters are interrelated and
also depend on S. Manufacturers usually specify these parameters as functions of diF/dt for
different values of IF. Both Irr and Qrr increases with IF and diF/dt while trr increases with IF and
decreases with diF/dt.
The reverse recovery characteristics shown in Fig. 2.13 is typical of a particular type of diodes
called “normal recovery” or “soft recovery” diode (S>1). The total recovery time (trr) in this case
is a few tens of microseconds. While this is acceptable for line frequency rectifiers (these diodes
are also called rectifier grade diodes) high frequency circuits (e.g PWM inverters, SMPS)
demand faster diode recovery. Diode reverse recovery time can be reduce by increasing the rate
of decrease of the forward current (i.e, by reducing stray circuit inductance) and by using
“snappy” recovery (S<<1) diode. The problems with this approach are:
i) Increase of diF/dt also increases the magnitude of Irr
ii) Large recovery current coupled with ”snappy” recovery may give rise to current and
voltage oscillation in the diode due to the resonant circuit formed by the stray circuit
inductance and the diode depletion layer capacitance. A typical recovery characteristics
of a “snappy” recovery diode is shown in Fig 2.14 (a).
Fig. 2.14: Diode overvoltage protection circuit; (a) “Snappy recovery characteristics; (b)
Capacitive snubber circuit; (c) snubber characteristics.
Large reverse recovery current may lead to reverse voltage peak (Vrr) in excess of VRSM and
destroy the device. A capacitive protection circuit (also called a “snubber circuit) as shown in
Fig. 2.14 (b) may to used to restrict Vrr. Here the current flowing through Ll at the time of diode
current “snapping” is bypassed to Cs. Ll,Rs & Cs forms a damped resonance circuit and the initial
energy stored in Ll is partially dissipated in Rs, thereby, restricting Vrr . Normalized values of Vrr
as a function of the damping factor ξ with normalized Irr as a parameter is shown in Fig. 2.14(c).
However, it is difficult to correctly estimate the value of Ll and hence design a proper snubber
circuit. Also snubber circuits increase the overall power loss in the circuit since the energy stored
in the snubber capacitor is dissipated in the snubber resistance during turning ON of the diode.
Therefore, in high frequency circuits other types of fast recovery diodes (Inverter grade) are
preferred. Fast recovery diodes offer significant reduction in both Irr and trr (10% - 20% of a
rectifier grade diode of comparable rating). This improvement in turn OFF performance,
however, comes at the expense of the steady state performance. It can be shown that the forward
voltage drop in a diode is directly proportion to the width of the drift region and inversely
proportional to the carrier life time in the drift region. On the other hand both Irr and trr increases
with increase in carrier life time and drift region width. Therefore if Irr and trr are reduced by
reducing the carrier life time, forward voltage drop increases. On the other hand, if the drift

region width is reduced the reverse break down voltage of the diode reduces. The performance of
a fast recovery diode is therefore, a compromise between the steady state performance and the
switching performance. In high voltage high frequency circuits switching loss is the dominant
component of the overall power loss. Therefore, some increase in the forward voltage drop in the
diode (and hence conduction power lass) can be tolerated since the Turn OFF loss associated
with reverse recovery is greatly reduced.
In some very high frequency applications (fsw >100KHZ), improvement in the reverse recovery
performance offered by normal fast recovery diode is not sufficient. If the required reverse
blocking voltage is less (<100v) schottky diodes are preferred over fast recovery diodes.
Compared to p-n junction diodes schottky diodes have very little Turn OFF transient and almost
no Turn ON transient. On state voltage drop is also less compared to a p-n junction diode for
equal forward current densities. However, reverse breakdown voltage of these diodes are less
(below 200V) Power schottky diodes with forward current rating in excess of 100A are
available.
Exerciser 2.3
1. Fill in the blanks with appropriate word(s)
i. Forward recovery voltage appears due to higher ohmic drop in the ______________ region
of a power diode in the beginning of the Turn On process.
ii. The magnitude of the forward recovery voltage is typically of the order of few
______________ of volts.
iii. The magnitude of the forward recovery voltage also depends on the _______________ of
the diode forward current.
iv. The reverse recovery charge of a power diode increases with the _______________ of the
diode forward current.
v. For a given forward current the reverse recovery current of a Power Diode ______________
with the rate of decrease of the forward current.
vi. For a given forward current the reverse recovery time of a Power diode ______________
with the rate of decrease of the forward current.
vii. A “snappy” recovery diode is subjected to _________________ voltage over shoot on
recovery.
viii. A fast recovery diode has _______________________ reverse recovery current and time
compared to a __________________ recovery diode.
ix. A Schottky diode has _______________ forward voltage drop and ______________ reverse
voltage blocking capacity.
x. Schottky diodes have no __________________ transient and very little
_________________ transient.
Answer: (i) drift, (ii) tens, (iii) rate of rise, (iv) magnitude, (v) increases, (vi) decreases, (vii)
large, (viii) lower, (ix) low, law, (x) Turn On, Turn Off.
2. In the buck converter shown the diode D has a lead inductance of 0.2μH and a reverse
recovery change of 10μC at iF =10A. Find peak current through Q.

Answer: Assuming iL=10A (constant) the above waveforms can be drawn
As soon as Q is turned ON. a reverse voltage is applied across D and its lead inductance.
diF 20
∴ = A S ec = 10 7 A S ec
dt .2 × 1 0 -6
Assuming a snappy recovery diode (s ≈ o)
1 ⎛ diF ⎞ 2
Q rr = 1 I rr t rr = ⎜ ⎟ t rr
2 2 ⎝ dt ⎠
= 1 0 × 1 0 -6 C
∴ t rr = 1 . 4 1 4 μ s
diF
∴ I rr = t rr = 1 4 . 1 4 A
dt
∴i =I +I = 24.14 A
Q peak L rr

References
1. Ned Mohan, Tore M. Undeland, William P. Robbins, “Power Electronics, Converters,
Application and Design” John Wiley & Sons(Asia), Publishers. Third Edition 2003.
2. P. C. Sen, “Power Electronics” Tata McGraw Hill Publishing Company Limited, New
Delhi, 1987.
3. Jacob Millman, Christos C. Halkias, “Integrated Electronics, Analog and Digital Circuits
and Systems”, Tata McGraw-Hill Publishing Company Limited, New Delhi, 1991.

Module Summary
• A p-n junction diode is a minority carrier, unidirectional, uncontrolled switching device.
• A power diode incorporates a lightly doped drift region between two heavily doped p
type and n type regions.
• Maximum reverse voltage withstanding capability of a power diode depends on the width
and the doping level of the drift region.
• A power diode should never be subjected to a reverse voltage greater than the reverse
break down voltage.
• The i-v characteristics of a forward biased power diode is comparatively more linear due
to the voltage drop in the drift region.
• The forward voltage drop across a conducting power diode depends on the width of the
drift region but not affected significantly by its doping density.
• For continuous forward biased operation the RMS value of the diode forward current
should always be less than its rated RMS current at a given case temperature.
• Surge forward current through a diode should be less than the applicable surge current
rating.
• During “Turn On” the instantaneous forward voltage drop across a diode may reach a
level considerably higher than its steady state voltage drop for the given forward current.
This is called forward recovery voltage.
• During “Turn Off” the diode current goes negative first before reducing to zero. This is
called reverse recovery of a diode.
• The peak negative current flowing through a diode during Turn Off is called the “reverse
recovery current” of the diode.
• The total time for which the diode current remains negative during Turn Off is called “the
reverse recovery time” of the diode.
• A diode can not block reverse voltage till the reverse current through the diode reaches its
peak value.
• Both the “reverse recovery current” and the “reverse recovery time” of a diode depends
on the forward current during Turn Off, rate of decrease of the forward current and the
type of the diode.
• Normal or slow recovery diodes have smaller reverse recovery current but longer reverse
recovery time. They are suitable for line frequency rectifier operation.
• Fast recovery diodes have faster switching times but comparatively lower break down
voltages. They are suitable for high frequency rectifier or inverter freewheeling
operation.
• Fast recovery diodes need to be protected against voltage transients during Turn Off”
using R-C snubber circuit.

• Schottky diodes have lower forward voltage drop and faster switching times but
comparatively lower break down voltage. They are suitable for low voltage very high
frequency switching power supply applications.

Practice Problems and Answers

Practice Problems (Module-2)
1. If a number of p-n junction diodes with identical i-v characteristics are connected in
parallel will they share current equally? Justify your answer.
2. A power diode have a reverse saturation current of 15μA at 32°C which doubles for
every 10° rise in temperature. The dc resistance of the diode is 2.5 mΩ. Find the forward
voltage drop and power loss for a forward current of 200 Amps. Assume that the
maximum junction temperature is restricted to 102°C.
VT = k T = 26 m v at 32 o C
q
3. In the voltage commutated chopper T & TA are turned ON alternately at 400 HZ. C is
initially charged to 200 V with polarity as shown. Find the IFRMS and VRRM ratings of DI
& DF.
4. In the voltage commutated chopper of Problem 5 the voltage on C reduces by 1% due to

reverse recovery of DI. Find out Irr & trr for DI. (Assume S = 1 for DI).
5. What precaution must be taken regarding the forward recovery voltage of the free
wheeling diodes in a PWM voltage source inverter employing Bipolar Junction
Transistors of the n-p-n type?

Answers to Practice Problems
1. The reverse saturation current of a p-n junction diode increases rapidly with temperature. If
follows then (from Eqn. 2.1) the voltage drop across a diode for a given forward current
decreases with increase in temperature. In other words if the volt ampere characteristics of a
diode is modeled as a non linear (current dependent) resistant it will have a negative
temperature coefficient.
Let us now consider the situation where a number of diodes are connected in parallel. If due
to some transient disturbance the current in a diode increases momentarily the junction
temperature of that diode will increase due increased power dissipation. The voltage drop
across that particular diode will decrease as a result and more current will be diverted
towards that diode. This “positive feedback mechanism” will continue to increase its current
share till parasitic lead resistance drop becomes large enough to prevent farther voltage drop
across that diode. Therefore, it can be concluded that a number of p-n junction diodes conned
in parallel will not, in general, share current equally even if it is assumed that they have
identical i-v characteristics.
However, equal current sharing can be forced by connecting suitable resistances in series
with the diodes so that the total resistance of each branch has positive temperature
coefficient.
2. Since the reverse saturation current double with every 10°C rise in junction temperature.
1 0 2 -3 2
Is 102o C
= 2 10
× Is 32o C
= 1 .9 2 m A
KT
Vt = = 26mv at 32 o C ∴ Vt at 102 o = 31.97mv
q
∴ V j fo r i F = 2 0 0 A is
iF
V j = Vt o
102 C
× ln = 0 .3 7 V
Is 102o C
Voltage drop across drift region VR = iF ×RD = 0.5V
Therefore, the total voltage drop across the diode is

VD = VR + V j = 0.87V

3. Important wave forms of the system are shown in the figure.
As soon as T is turned ON the capacitor voltage starts reversing due to the L-C resenant
circuit formed by C-T-L & DI. Neglecting all the capacitor voltage reaches a -200V.
The current idi is given by
i D I = I D IP S in ω n 0 ≤ ωn ≤ 7
w here I D IP = 200 C = 89.44 A
L
1
& ωn = = 22.36×103
LC

∴ Capacitor voltage reversal time
Tn 1 π
= = = = 140μs.
2 2 fn ωn
Capacitor voltage remains at -200 V till TA is turned ON when it is charged linearly towards
+200 V. Time taken for charging is
2 × 200 × C
TC = = 400μs
IL
At the end of charging DF turns ON and remains on till T is turned on again.
I DIP 140
∴ I FRMS For D I is = 10.58 Amps
2 5000
2100
I FRMS For D F is 20 = 12.96 Amps
5000
From figure VRRM for D I is 200 V
VRRM for D F is 400 V
4. Since the Capacitor voltage reduces by 1%
Q rr = 0.01× C × 200 = 40μc

d i dI
w ith S = 1 Q rr = I rr t rr = t rr 2
dt
Now id I = I DIP Sin ω n t
di dI
∴ = ω n I D IP C osω n t
dt
di dI 1 C
at ω n t = π, = ω n I DIP = , 200 = 2A
dt LC L μs
∴ t rr 2 = 20 ×10-12 sec 2 or t rr = 4.472 μs

∴ I rr = 8.94 Am ps
5. Figure shows one leg of a PWM VSI using n-p-n transistor and freewheeling diode.

Consider turning off operation of Q1. As the current through Q1 reduces D1 turns On. The
forward recovery voltage of D1 appears as a reverse voltage across the n-p-n transistor whose
base emitter junction must with stand this reverse voltage. Therefore, the forward recovery
voltage of the free wheel diodes must be less them the reverse break down voltage of the base-
emitter junction of the n-p-n transistors for safe operation of the inverter.

Module
1
Power Semiconductor
Devices
Lesson
3
Power Bipolar Junction
Transistor (BJT)
Constructional Features, Operating Principles, Characteristics and specifications of Power
Bipolar Junction transistors.
Objective: On completion the student will be able to
1. Distinguish between, cut off, active, and saturation region operation of a Bipolar Junction
Transistor.
2. Draw the input and output characteristics of a junction transistor and explain their nature.
3. List the salient constructional features of a power BJT and explain their importance.
4. Draw the output characteristics of a Power BJT and explain the applicable operating
limits under Forward and Reverse bias conditions.
5. Interpret manufacturer’s data sheet ratings for a Power BJT.
6. Differentiate between the characteristics of an ideal switch and a BJT.
7. Draw and explain the Turn On characteristics of a BJT.
8. Draw and explain the Turn Off characteristics of a BJT.
9. Calculate switching and conduction losses of a Power BJT.
10. Design a BJT base drive circuit.

3.1 Introduction
Power Bipolar Junction Transistor (BJT) is the first semiconductor device to allow full control
over its Turn on and Turn off operations. It simplified the design of a large number of Power
Electronic circuits that used forced commutated thyristors at that time and also helped realize a
number of new circuits. Subsequently, many other devices that can broadly be classified as
“Transistors” have been developed. Many of them have superior performance compared to the
BJT in some respects. They have, by now, almost completely replaced BJTs. However, it should
be emphasized that the BJT was the first semiconductor device to closely approximate an ideal
fully controlled Power switch. Other “transistors” have characteristics that are qualitatively
similar to those of the BJT (although the physics of operation may differ). Hence, it will be
worthwhile studying the characteristics and operation a BJT in some depth. From the point of
view of construction and operation BJT is a bipolar (i.e. minority carrier) current controlled
device. It has been used at signal level power for a long time. However, the construction and
operating characteristics of a Power BJT differs significantly from its signal level counterpart
due to the requirement for a large blocking voltage in the “OFF” state and a high current carrying
capacity in the “ON” state. In this module, the construction, operating principle and
characteristics of a Power BJT will be explored.
3.2 Basic Operating Principle of a Bipolar Junction Transistor

A junction transistor consists of a semiconductor crystal in which a p type region is sandwiched
between two n type regions. This is called an n-p-n transistor. Alternatively an n type region
may be placed in between two p type regions to give a p-n-p transistor. Fig 3.1 shows the circuit
symbols and schematic representations of an n-p-n and a p-n-p transistor. The terminals of a
transistor are called Emitter (E), Base (B) & Collector (C) as shown in the figure.
VCE
VCE
E (n) C (n) E (p) C (p)
-
iE VBE + i iC
C
iE VBE
iB B (p) B (n)
RC RC
VBB RB VBB
iB
VCC VCC

(Emitter) (Base) (Collector) (Emitter) (Base) (Collector)
n p n n p n
(E) (B) (C) (E) (B) (C)
S
WBE 0
A
φCB
A
φBE A
0
φCB
S S φCB φ φBE
S
φBE φCB BE
S
x
A
φCB
0 φ 0 x WS
CB
S
WBE
φBE BE
S
φCB A
WCB WCB
A
WBE
A
WBE 0
WCB
0 0 0
WCB
WBE A WBE
WCB
JBE JCB JBE JCB
n SpB pSnB
pSnE pSnC n SpE n SpC

n poB p noB
p AnE p noE p noC
n ApE
n poE n poC
A
n A
pB
p nC p A
nB
n ApC
x x
(a) (b)
Fig. 3.1: Bipolar junction transistor under different biasing condition.
(a) n – p – n transistor ; (b) p – n – p transistor.
If no external biasing voltages are applied (i.e.; VBB and VCC are open circuited) all transistor
currents must be zero. The transistor will be in thermal equilibrium condition with potential
barriers φοΒΕ and φCB o
at the base emitter and the base collector functions respectively.
O O
Corresponding depletion layer widths will be WBE and WCB . It is clear from the diagram that p
type carriers in the base region of an n-p-n transistor are trapped in a “potential well” and cannot
escape. Similarly, in a p-n-p transistor p type carriers in the emitter and collector regions are
separated by a “potential hill”.
When biasing voltages are applied as shown in the figure, the base emitter junction (JBE)
becomes forward biased where as the base collector junction is reverse biased. Potential barrier
Α
and depletion layer width at JBE reduces to φΒΕ and WBE A
respectively. Both these quantities
increase at JCB ( φACB , WCB
A
) . As the potential barrier at JBE is reduced a large number of minority
A
carriers are introduced in to Base and the Emitter regions as shown in Fig. 3.1 ( PnE , n ApB for n-p-n

transistor and n ApE , p AnB for p-n-p transistor). A portion of the minority carriers reaching the base
recombines with majority carriers. The rest, defuse to the edge of the depletion region at JCB
where they are swept away to the collector region by the large electric field. Under this condition
the transistor is said to be in the Active region.
As VBE is increased injected minority charge into the base region increases and so does the base
current and the collector current. For a fixed collector bias voltage VCC, the voltage VCB reduces
with increase in collector current due to increasing drop in the external resistance RC. Therefore,
the potential barrier at JCB starts reducing. At one point JCB becomes forward biased. The
potential barriers and depletion layer widths under this condition are indicated in Fig. 3.1 by
variables with a super script “s”. Due to forward biasing of JCB there will be minority carrier
injection into the base from this junction also as shown in Fig. 3.1. The total voltage drop
between collector and emitter will be the difference between the forward bias voltage drops at
JBE and JCB. Under this condition the transistor is said to be in the saturation region.
From the operating principle described above one can form a qualitative idea about the input (iB B
vs VBE) and output (iC Vs VCE) characteristics of a transistor. In the following section these
characteristics of an n-p-n transistor will be discussed qualitatively. Similar explanation applies
to a p-n-p transistor.
When a biasing voltage VBB of appropriate polarity is applied across the junction JBE the
potential barrier at this junction reduces and at one point the junction becomes forward biased.
The current crossing this junction is governed by the forward biased p-n junction equation for
a given collector emitter voltage. The base current iB is related to the recombination of minority
B
carriers injected into the base from the emitter. The rate of recombination is directly proportional
to the amount of excess minority carrier stored in the base. Since, in a normal transistor the
emitter is much more heavily doped compared to the base the current crossing JBE is almost
entirely determined by the excess minority carrier distribution in the base. Thus, it can be
concluded that the relationship between iB and VBE will be similar to the i-v characteristics of a
B
p-n junction diode. VCE, however have some effect on this characteristic. As VCE increases
reverse bias of JCB increases and the depletion region at JCB moves deeper into the base. The
effective base width thus reduces, reducing the rate of recombination in the base region and
hence the base current. Therefore iB for a given VBE reduces with increasing VCE as shown in
B
Fig. 3.2(a).
It has been mentioned before that only a fraction (denoted by the letter “∝”) of the total minority
carriers injected into the base reaches junction JCB where they are swept in to the collector region
by the large electric field at JCB. These minority carriers constitute the major component of the
total collector current. The other component of the collector current consists of the small reverse
saturation current of the reverse biased junction JCB.
Therefore IC = ∝IE + Ics (3.1)

Where Ics is the reverse saturation current of junction JCB
But IE = IB + IC
B (3.2)

ICS ∝
∴ IC = + IB
1- ∝ 1- ∝ (3.3)
∝
By defining
β
1− ∝
IC = βIB + (β+1) Ics (3.4)
β is called the large signal common emitter current gain of the transistor and remains fairly
constant for a large range of IC, as shown in Fig. 3.2 (c). Fig: 3 (b) shows the complete out put
characteristics (ic vs VCE) of an n-p-n transistor.
With VBB = 0 or negative there is little injected minority carrier into the base from the
emitter side. Therefore, iB = 0 and iC is negligibly small. The transistor is said to be in the “cut
B
off” region under this condition.
As VBB is increased from zero, base current starts flowing. From equation (3.4) it will be
expected that the collector current should increase proportionately independent of VCE. However
Fig 3.2 (b) does indicate a slight increase in iC with VCE for a given iB. This is expected because
B
with increasing VCE a larger value of VBE will be required to maintain a given iB (Fig. 3.2 (a)).
B
Therefore, the component “∝IE” of collector current will increase. ICS is ,for all practical
purpose, independent of VCE. This is the active or “amplifier mode” of operation of a transistor.
In the active region as iB increases iC also increases. For a given value of VCC, VCE reduces with
B
increasing iC due to increased drop in an external load (i.e., Rc in Fig 3.1). At one point the
junction JCB becomes forward biased. VCE, now is just the difference between the voltages across
two forward biased junction JBE and JCB (a few handed milli volts). This is when the transistor
enters the saturation mode of operation. The ratio iC/iB at the onset of saturation is called βMin and
B
is an important parameter for a power transistor. In saturation iC is almost entirely determined by

the external load and further increase in iB changes iC or VCE very little.

iC iB6
iB5
iB4
iB iB3 iB
Saturation
vCE Active increasing
iB2
increasing iB1
iB = 0
vBE Cut off
vCE
(a) (b)
β
(c)
Fig. 3.2: Input and output characteristics of an n – p – n transistor.
(a) Input characteristics; (b) Output characteristics; (c) Current
gain[β] characteristics
Exercise 3.1
Fill in the blank(s) with the appropriate word(s)
a) Under forward bias condition a large number of ___________________ carriers are

introduced in the base region.
b) Some minority charge carriers reaching base __________________ with majority
carriers there and the rest of them ___________________ to the collector.
c) When the base-emitter junction of a BJT is forward biased while the base-collector
junction is reverse biased the BJT is said to be in the _______________ region.
d) When both B-E & C-B junction of a BJT are reverse biased it is said to be in the
_________________ region.
e) When both B-E & C-B junction of a BJT are forward biased it is said to be in the
_______________ region.

Answer: (a) minority; (b) recombine, diffuse; (c) active; (d) cut-off; (e) saturation.
Exercise 3.2
Why does the collector current of a BJT in the active region increases with increasing collector
voltage for a given base current.
Answer: In the active region as the VCE voltage is increased the depletion layer width at the CB
junction increases and the effective base width reduces. Therefore, for a given VBE
recombination of minority carriers in the base region reduces and base current also
reduces. In order to main constant base current with increasing VCE, VBE must
increased. Therefore, for a constant base current the number of minority carriers in the
base region will increase and consequently, collector current will increase.
Exercise 3.3
A power BJT has IC = 20 A at IB = 2.5 A. Ics = 15 mA. Find out β & ∝.

B
Answer: Ic = β IB + (β + 1) Ics = β( IB + Ics) + Ics.

B B
∴ β = 7.95,
3.3 Constructional Features of a Power BJT

Power transistors face the same conflicting design requirements (i.e. large off state blocking
voltage and large on state current density) as that of a power diode. Therefore, it is only natural
to extend some of the constructional features of power diodes to power BJT. Following Section
summarizes some of the constructional features of a Power BJT. Since Power Transistors are
predominantly of the n-p-n type, in this section and subsequently only this type of transistor will
be discussed.
• A power BJT has a vertically oriented alternating layers of n type and p type
semiconductor materials as shown in Fig 3.3(a). The vertical structure is preferred for
power transistors because it maximizes the cross sectional area through which the on
state current flows. Thus, on state resistance and power lass is minimized.
• In order to maintain a large current gain “β” (and hence reduce base drive current) the
emitter doping density is made several orders of magnitude higher than the base region.
The thickness of the base region is also made as small as possible.
• In order to block large voltage during “OFF” state a lightly doped “collector drift region”
is introduced between the moderately doped base region and the heavily doped collector
region. The function of this drift region is similar to that in a Power Diode. However, the
doping density donation of the base region being “moderate” the depletion region does
penetrate considerably into the base. Therefore, the width of the base region in a power
transistor can not be made as small as that in a signal level transistor. This comparatively
larger base width has adverse effect on the current gain (β) of a Power transistor which

typically varies within 5-20. As will be discusses later the collector drift region has
significant effect on the out put characteristics of a Power BJT.
• Practical Power transistors have their emitters and bases interleaved as narrow fingers.
This is necessary to prevent “current crowding” and consequent “second break down”.
In addition multiple emitter structure also reduces parasitic ohmic resistance in the base
current path.
These constructional features of a Power BJT are shown schematically in Fig 3.3(a). Fig.3.3 (b)
shows the photograph of some community available Power transistors in different packages.
Emitter contact
Base
contact
n+ (emitter) n+ n+
p (Base)
n- (Collector Drift)
n+ (Collector)
(a) Collector contact

(b)
Fig. 3.3: Constructional Features of a Power Bipolar Junction Transistor

(a) Schematic of Construction,
(b) Photograph of commercial packages.
Exercise 3.4
a) Doping density of the emitter of a Power BJT is several orders of magnitude

______________ than the base doping density.
b) Collector drift region is introduced in a Power BJT to block _______________ voltage.
c) Doping density of the base region in a power BJT is ________________.
d) Power BJT has ________________ DC current gain compared to signal level transistors.
e) In a Power BJT multiple, narrow finger like distributed emitter structure is used to avoid
emitter ___________________.
Answer: (a) higher; (b) high reverse; (c) moderate; (d) low; (e) current crowding.
Exercise 3.5
What are the constructional features of a power transistor that affect the dc current gain?
• Large doping density of the emitter increases dc current gain.

• Moderately doped base regain of relatively larger width tend to reduce the dc current
gain. The base width in a power transistor cannot be reduced below a certain level in
order to avoid “reach through” of the base region under large applied voltage.
• Multiple, narrow emitter regions distributed uniformly over the entire device cross
section also tends to improve dc current gain by minimizing “current crowding”.
3.4 Output i-v characteristics of a Power Transistor

A typical output (iC vs VCE) characteristics of an n-p-n type power transistor is shown in
Fig 3.4 A power transistor exhibits “Cut off”, “Active” and “Saturation regions” of operation in
its output characteristics similar to a signal level transistor. In fact output characteristics of a

Power Transistor in the “Cut off” and “Active” regions are qualitatively identical to a signal
level transistor. Certain quantitative restrictions apply, however, which are discussed next.
iC
Hard Saturation
Quasi Saturation
iB10 Second break down limit
iB9
iB8
iB7 Active
iB6 Total Power dissipation limit
iB5
iB4
iB3
iB2 Increasing iB
Primary break down voltage
iB1
iB ≤ 0
ϑCE
Cut off
VSUS
VCE0 VCB0
(iB = 0) (iB < 0)
Fig. 3.4 Output ( ic – vCE ) characteristics of an n – p – n type Power Transistor
In the cut off region (iB ≤ 0) the collector current is almost zero. The maximum voltage between
B
collector and emitter under this condition is termed “Maximum forward blocking voltage with
base terminal open (iB = 0)” and is denoted by VCEO. For all practical purpose this is the
B
maximum voltage that can be applied in the forward direction (C positive with respect to E)
across a power transistor since a power transistor is expected to see any significant forward
voltage only with iB = 0. This blocking voltage can however be increased to a value VCBO by
B
keeping the emitter terminal open. In this case iB < o. Actually VCBO is the breakdown voltage of
the collector base junction. However, since the open base configuration is more common the
value of VCEO is used by the manufacturers as the maximum voltage rating of a power transistor.
Power transistors have poor reverse voltage withstanding capability due to low break down
voltage of the base-emitter junction. Therefore, reverse voltage (C negative with respect to E)
should not appear across a power transistor.
In the active region the ratio of collector current to base current (DC current Gain (β)) remains
fairly constant upto certain value of the collector current after which it falls off rapidly.
Manufacturers usually provide a graph showing the variation of β as a function of the collector
current for different junction temperatures and collector emitter voltages. This graph is useful for
designing the base drive of a Power transistor. Typically, the value of the dc current gain of a
Power transistor is much smaller compared to their signal level counterpart.

The maximum collector-emitter voltage that a power transistor can withstand in active region is
determined by the Base collector avalanche break down voltage. This voltage, denoted by VSUS
in Fig, 3.4 is usually smaller than VCEO. The voltage VSUS can be attained only for relatively
lower values of collector current. At higher collector current the limit on the “total power
dissipation” defines the boundary of the allowable active region as shown in Fig 3.4.
At still higher levels of collector currents the allowable active region is further restricted by a
potential failure mode called “the Second Break down”. It appears on the output characteristics
of the BJT as a precipitous drop in the collector-emitter voltage at large collector currents. The
collector voltage drop is often accompanied by significant rise in the collector current and a
substantial increase in the power dissipation. Most importantly this dissipation is not uniformly
spread over the entire volume of the device but is concentrated in highly localized regions. This
localized heating is a combined effect of the intrinsic non uniformity of the collector current
density distribution across the cross section of the device and the negative temperature
coefficient of resistively of minority carrier devices which leads to the formation of “current
filamements” (localized areas of very high current density) by a positive feed-back mechanism.
Once current filaments are formed localized “thermal runaway” quickly takes the junction
temperature beyond the safe limit and the device is destroyed.
It is in the saturation region that the output characteristics of a Power transistor differs
significantly from its signal level counterpart. In fact the saturation region of a Power transistor
can be further subdivided into a quasi saturation region and a hard saturation region.
Appearance of the quasi saturation region in the output characteristics of a power transistor is a
direct consequence of introducing the drift region into the structure of a power transistor. In the
quasi saturation region the base-collector junction is forward biased but the lightly doped drift
region is not completely shorted out by excess minority carrier injection from the base. The
resistivity of this region depends to some extent on the base current. Therefore, in the quasi
saturation region, the base current still retains some control over the collector current although
the value of β decreases significantly. Also, since the resistivity of the drift region is still
significant the total voltage drop across the device in this mode of operation is higher for a given
collector current compared to what it will be in the hard saturation region.
In the hard saturation region base current looses control over the collector current which is
determined entirely by the collector load and the biasing voltage VCC. This behavior is similar to
what happens in a signal transistor except that the drift region of a power transistor continues to
offer a small resistance even when it is completely shorted out (by excess carrier injection from
the base). Therefore, for larger collector currents the collector-emitter voltage drop is almost
proportional to the collector current. Manufacturers usually provide the plots of the variation of
VCE (sat) vs. iC for different values of base current and junction temperature. Curves showing
the variation of VCE (sat) with iB for different values of iC and junction temperature are also
B
provided by certain manufacturers.
Applicable operating limits on a power transistors are compactly represented in two diagrams
called the Forward Bias Safe Operating Area (FBSOA) and the Reverse Bias Safe Operating
Area. (RBSOA) applicable to iB > 0 and iB ≤ 0 conditions respectively. Typical safe operating
B B
areas of power transistors are shown in Fig 3.5.

iC
iC
ICM
ICM
10-5sec
10-4sec
10-3sec
10-2sec
DC
Log ϑCE ϑCE
(a) VSUS (b) VCE0 VCB0
(VBE = 0) (VBE < 0)
Fig. 3.5: Safe operating areas of a Power Transistor.
(a) FBSOA; (b) RBSOA.
The horizontal upper limit of the FBSOA is determined by the maximum allowable collector
current (ICM) that should not be exceeded even as a pulse. Exceeding this current limit may cause
bonding wire or metallization of the wafer to vaporize or otherwise fail. Since a power transistor
does not have any appreciable reverse voltage blocking capacity they are usually not used in ac
circuits. However, if the collector current, for some reason is not dc or a pulse, the rms value of
the collector current waveform should not exceed this limit.
The next applicable limit in the FBSOA (green lines) corresponds to the restriction on the
maximum allowable power dissipation and maximum junction temperature. Since FBSOA is
shown on a log-log scale constant Power dissipation (Pd = VCE iC) limits appear as straight lines.
This limit is different for dc and pulsed operation due to the thermal time constant of the device.
The “DC” limit is applicable to the average power loss if the transistor remains continuously in
the conduction state (active, quasi saturation or saturation). On the other hand the pulsed power
dissipation limits are applicable to conduction duration up to the value marked on them (the
figures on the right of Fig 3.5 (a)). Pulsed power dissipation limits are specified for a low value
(1%-2%) of duty cycle and are useful for shaping the switching trajectory of the transistor as will
be seen later.
The third limit of the FBSOA (red line) arises due to the “second break down” failure mode of
a Power transistor. It shows the limiting combinations of collector voltage and current so that
second break down does not occur. On the log –log scale of the FBSOA this limit also appears as
a straight limit. Like the maximum power dissipation limit, the second break down limit is also
different for “DC” and “Pulsed” operation of different pulse durations. The interpretation of the
pulse duration (marked on the right side of Fig 3.5 (a)) corresponding to a particular limit is also
same.
The final limit of the FBSOA corresponds to the forward biased avalanche break down voltage
(VSUS) of the transistor and appear as a vertical line in the FBSOA at VCE = VSuS
The FBSOA of a Power transistor is given at a specified case temperature. Both the maximum
power dissipation limit and the second break down limits are to be derated as per the derating
characteristics provided by the manufacturers when the case temperature exceeds the specified
value.
In contrast to the FBSOA, the RBSOA (Fig 3.5 (b)) is plotted on a linear scale and has a more
rectangular shape. RBSOA is a switching SOA since a transistor can not conduct current for any
appreciable duration under reverse biased condition. It essentially shows the limiting permissible
combinations of VCE & iC with base emitter junction reverse biased. The upper horizontal limit
corresponds to the maximum allowable collector current (ICM) and is same as that in the FBSOA.
The right hand side vertical limit corresponds the avalanche break down voltage of the transistor
with reverse bias. If the base terminal is open (i,e, iB = 0) then this voltage is VCEO. If a negative
B
voltage is applied across the BE junction the right hand side limit of the RBSOA increases
somewhat to the value VCBO at low value of the collector current.
In addition to the applicable limits on the output characteristics as represented in the FBSOA and
the RBSOA, limiting specification with respect to the base emitter junction is also provided by
the manufacturer. Typical specifications that are provided are
VEBO : This is maximum allowable reverse bias voltage across the B-E junction
IBB : Maximum allowable average base current at a given case temperature.
IBM : Maximum allowable peak base current at a given case temperature and of
specified pulse duration.
The input characteristics (iB Vs VBE) at a given case temperature is also provided.
B
Exercise 3.6
a) In the “Cut off” region collector current of a Power Transistor is _____________.

b) In the __________________ region of a Power Transistor the dc current gain remains
fairly constant.
c) Saturation region of a Power Transistor can be divided into _______________ region and
______________________ region.
d) Active region operation of a Power BJT is limited mostly by _______________
consideration.
e) “Second breakdown” in a Power BJT occurs due to ________________ of the collector
current distribution.
Answer: (a) negligible; (b) active; (c) Quasi saturation, hard saturation; (d) Power
dissipation; (e) non uniformity.
3.5 Switching characteristics of a Power Transistor

In a power electronic circuit the power transistor is usually employed as a switch i.e. it operates
in either “cut off” (switch OFF) or saturation (switch ON) regions. However, the operating

characteristics of a power transistor differs significantly from an ideal controlled switch in the
following respects.
• It can conduct only finite amount of current in one direction when “ON”
• It can block only a finite voltage in one direction.
• It has a voltage drop during “ON” condition
• It carries a small leakage current during OFF condition
• Switching operation is not instantaneous
• It requires non zero control power for switching
Of these the exact nature and implication of the first two has been discussed in some depth in the
previous section. The third and fourth non idealities give rise to power loss termed the
conduction power loss. In this section the nature and implications of the last two non idealities
will be discussed in detail.
Exercise 3.7
a) An ideal switch can conduct current in ______________ directions. While a power

transistor conducts current in _______________ direction.
b) In power transistor there will be power loss due to ON state ________________ and OFF
state _________________.
c) Unlike an ideal switch the switching of a power transistor is not ____________.
Answer: (a) two, one; (b) voltage drop, leakage current; (c) instantaneous.
3.5.1Turn On characteristics of a Power Transistor

From the description of the basic operating principle of a power transistor presented in the
previous sections it is clear that minority carriers must be moved across different regions of a
power transistor in order to make it switch between cut off and saturation regions of operation.
The time delay in the switching operation of a power transistor is due to the time taken by the
minority carriers to reach appropriate density levels in different regions. The exact level of
minority carrier densities (and depletion region widths) required for proper switching is
determined by the collector current and biasing collector voltage during switching, both of which
are determined by external circuits. The rate at which these densities are attained is determined
by the base current waveform. Therefore, the switching characteristics of a power transistor is
always specified in relation to the external load circuit and the base current waveform as shown
in Fig 3.6 which shows a clamped inductive switching circuit with a flat base drive.

VCC
iD
D IL
iC
+
RB iB
Q VCE
VBE
-
VBB
(a)

td tri tfv1 tfv2
VBB
VBE
VBE sat
0 t
VBB - VBE(sat)
RB
iB
t
ic
id
IL IL
vCE
VCC VCE (sat)
Pe VCC IL
vCE (sat) IL
(b)
Fig 3.6 Turn ON characteristics of a power transistor;
(a) Switching circuit, (b) Switching wave forms
The switching wave forms shown in Fig 3.6 (b) are the expanded and to some extent “idealized”
version of the actual waveforms that will be observed in a clamped inductive switching circuit as
shown in Fig.3.6 (a). Some simplifying assumptions have been made to draw these waveforms.
These are

• The load inductor has been assumed to be large enough so that the load current does not
change during Turn ON period.
• Reverse recovery characteristics of D has been ignored.
• All parasitic elements have been ignored.
Before t = 0, the transistor (Q) was in the “OFF” state. In order to utilize the increased break
down voltage (VCBO) the base-emitter junction of a Power Transistor is usually reverse biased
during OFF state. Under this condition only negligible leakage current flows through the
transistor. Power loss due to this leakage current is negligible compared to other components of
power loss in a transistor. Therefore, it is not shown in Fig 3.6 (b). The entire load current flows
through the diode and VCE is clamped to VCC (approximately).
To turn the transistor ON at t = 0, the base biasing voltage VBB changes to a suitable positive
value. This starts the process of charge redistribution at the base-emitter junction. The process is
akin to charging of a capacitor. Indeed, the reverse biased base emitter junction is often
represented by a voltage dependent capacitor, the value of which is given by the manufacturer as
a function of the base-emitter reverse bias voltage. The rising base current that flows during this
period can be thought of as this capacitor charging current. Finally at t = td the BE junction is
forward biased. The junction voltage and the base current settles down to their steady state
values. During this period, called the “Turn ON delay time” no appreciable collector current
flows. The values of iO and VCE remains essentially at their OFF state levels.
At the end of the delay time (td ON) the minority carrier density at the base region quickly
approaches its steady state distribution and the collector current starts rising while the diode
current (id) starts falling. At t = tdON + tri the collector current becomes equal to the load current
(and id becomes zero) IL. At this point D starts blocking reverse voltage and VCE becomes
unclamped. tri is called the current rise time of the transistor.
At the end of the current rise time the diode D regains reverse blocking capacity. The collector
voltage VCE which has so far been clamped to VCC because of the conducting diode “D” starts
falling towards its saturation voltage VCE (sat). The initial fall of VCE is rapid. During this period
the switching trajectory traverses through the active region of the output characteristics of the
transistor. At the end of this rapid fall (tfv1) the transistor enters “quasi saturation region”. The
fall of VCE in the quasi saturation region is considerably slower. At the end of this slow fall (tfv2)
the transistor enters “hard saturation” region and the collector voltage settles down to the
saturation voltage level VCE (sat) corresponding to the load current IL. Turn ON process ends
here. The total turn on time is thus, TSW (ON) = td (ON) + tri + tfv1 + tfv2.
Power loss occurs at all time during the operation of a power transistor. However, the collector
leakage current is usually negligibly small and power loss due it can be safely neglected in
comparison to the power loss during ON condition. Power loss occurs during Turning ON a
Power transistor due to simultaneous existence of non-zero VCE and ic during tri, tfv1, and tfv2. The
energy lost during these periods is called the Turn ON loss and given by the area under the Pl
curve in Fig 3.6 (b). The average Turn ON loss is obtained by dividing this area by (tri + tfv1 +
tfv2). For safe Turn ON this average power loss must be less than the limit set on the maximum

power dissipation in the FBSOA corresponding to a pulse width greater than tri + tfv1 + tfv2.
Similar restriction with respect to second break down should also be observed.
Turn ON time can be reduced by increasing the base current. However large base current
increases the quantity of excess carrier in the base and collector drift region which has to be
removed during Turn Off. As will be seen later this increases the Turn OFF time. The Turn ON
delay time can however be reduced by boosting the base current at the beginning of the Turn ON
process. This can be achieved by connecting a small capacitance across RB. This increases the
B
rate of rise of VBE & iB. Therefore, Turn ON delay time decreases. However, in steady state iB
B B
settle downs to a value determined by RB & VBB and no adverse effect on the Turn OFF time is
B
observed.
In figure 3.6 (b) the reverse recovery current of D has been neglected. If this current is not
negligible then for safe Turn ON operation the sum of the load current and the diode reverse
recovery current must be less than the ICM rating of the transistor. Thermal and second break
down limits must also be observed.
It should be noted that there is some power loss at the BE junction as well. This power loss
depends on the current gain of the transistor during hard saturation. Since current gain reduces
during saturation (typically between 5 to 10) this power loss may become significant.
Manufacturers usually provide the values of td (ON), tri, tfv as functions of ic for a given base
current and case temperature.
Exercise 3.8
a) For faster switching of a BJT _______________ carriers are to be swept quickly from the
________________ region.
b) The reverse biased base emitter junction can be represented as a ______________
dependent __________________.
c) In the quasi saturation region collector-emitter voltage falls at a ______________ rate.
d) Turn ON delay can be reduced by __________________ the rate of rise of the base
current.
Answer: (a) minority, base; (b) voltage, capacitor; (c) slow; (d) increasing.
3.5.2 Turn Off Characteristics of a Power Transistor

During Turn OFF a power transistor makes transition from saturation to cut off region of
operation. Just as in the case of Turn ON, substantial redistribution of minority charge carriers
are involved in the Turn OFF process. Idealized waveforms of several important variables in the
clamped inductive switching circuit of Fig. 3.6 (a) during the Turn OFF process of Q are shown
in Fig 3.7 (a)

VBB VBE(sat)
VBE t
VBB
iB
iC
id
IL IL
VCE
VCE(Sat)
VCC
Pe
t
ts trv1
trv2 tfi
(a)

log iC Reverse recovery current of D
ICM P’ FBSOA
P RBSOA
Forward recovery
Voltage of D
Turn off Turn on

Trajectory Trajectory
VCBO
log vCE
V(sus) VCEO
(b)
Fig. 3.7: Turn off, characteristics of a BJT.
(a) Switching wave forms
(b) Switching trajectory
The “Turn OFF” process starts with the base drive voltage going negative to a value -VBB.
The base-emitter voltage however does not change from its forward bias value of VBE(sat)
immediately, due to the excess, minority carriers stored in the base region. A negative base
current starts removing this excess carrier at a rate determined by the negative base drive voltage
and the base drive resistance. After a time “ts” called the storage time of the transistor, the
remaining stored charge in the base becomes insufficient to support the transistor in the hard
saturation region. At this point the transistor enters quasi saturation region and the collector
voltage starts rising with a small slope. After a further time interval “trv1” the transistor completes
traversing through the quasi saturation region and enters the active region. The stored charge in
the base region at this point is insufficient to support the full negative base current. VBE starts
falling forward –VBB and the negative base current starts reducing. In the active region, VCE
increases rapidly towards VCC and at the end of the time interval “trv2” exceeds it to turn on D.
VCE remains clamped at VCC, thereafter by the conducting diode D. At the end of trv2 the stored
base charge can no longer support the full load current through the collector and the collector
current starts falling. At the end of the current fall time tfi the collector current becomes zero and
the load current freewheels through the diode D. Turn OFF process of the transistor ends at this
point. The total Turn OFF time is given by Ts (OFF) = ts + trv1 + trv2 + tfi
As in the case of “Turn ON” considerable power loss takes place during Turn OFF due to
simultaneous existence of ic and VCE in the intervals trv1, trv2 and tfi. The last trace of Fig 3.7 (a)
shows the instantaneous power loss profile during these intervals. The total energy last per turn
off operation is given by the area under this curve. For safe turn off the average power
dissipation during trv1 + trv2 + tfi should be less than the power dissipation limit set by the FBSOA
corresponding to a pulse width greater than trv1 + trv2 + tfi.

Turn OFF time intervals of a power transistor are strongly influenced by the operating conditions
and the base drive design. Manufacturers usually specify these values as functions of collector
current for given positive and negative base current and case temperatures. Variations of these
time intervals as function of the ratio of positive to negative base currents for different collector
currents are also specified.
In this section and the precious one inductive load switching have been considered. However, if
the load is resistive. The freewheeling diode D will not be used. In that case the collector voltage
(VCE) and collector current (ic) will fall and rise respectively together during Turn ON and rise
and fall respectively together during Turn OFF. Other characteristics of the switching process
will remain same. The switching Power loss in this case will also be substantially lower.
Exercise 3.9
a) Turn OFF process in a BJT is associated with transition from the _______________
region to the ______________ region.
b) Negative _______________ current is required to remove excess charge carriers from the
______________ region of a BJT during Turn OFF process.
c) VCE increases rapidly in the ________________ region.
Answer: (a) Saturation, Cut-off; (b) base, base; (c) active.
3.5.3 Switching Trajectory and Switching Losses in a Power

Transistor
It has been mentioned in the earlier sections that energy loss takes place in a power transistor
during each switching operation. Instantaneous power loss during switching can be calculated
and plotted as shown in Fig 3.6 (b) and 3.7 (a). The areas under these curves indicate the energy
loss during each switching operation (Turn ON and Turn OFF). Indicating these areas as EON and
EOFF during Turn ON and Turn OFF operations respectively one can write.
E ON =
1⎡
2 ⎣ ( )
VCC I L t ri + ( VCC + VCEf1 ) I L t fv1 + VCEf1 + VCE (sat ) I L t fv2 ⎤ ( 3.5 )
⎦
Where VCEf1 is the value of VCE at the end of the interval tfv1
Similarly
E OFF = 1 ⎡⎣( VCE ( sat ) + VCEr1 ) I L t rv1 + ( VCEr1 + VCC ) I L t rv2 + VCC I L t fi ⎤⎦ ( 3.6 )
2
If the switching frequency of the transistor is fSW, then the average switching power loss is given
by
PSW = ( E ON + E OFF ) fSW ( 3.7 )

On the other hand the conduction energy loss is given by the area hatched black in Fig 3.6 (b)
and 3.7(a). From these figures the conduction power loss is given by
PC = VCE ( sat ) IL ( TON - t d ( ON ) - t ri - t fv1 - t fv2 + t s ) fSW ( 3.8)

Where TON is the time period for which the base drive voltage remain positive. Usually ts –
TSW(ON) << TON, Therefore
PC = VCE ( sat ) IL TON fSW = VCE ( sat ) IL D ( 3.9)

Where D is the switching duly cycle.
For a given VCC and IL and base drive design, EON and EOFF are constant. Therefore, the
switching power loss is proportional to the switching frequency. Being a minority carrier device
a BJT has comparatively larger switching times (compared to some other devices broadly
categorized as transistors) and hence larger switching power loss for a given frequency. On the
other hand a BJT has the lowest ON state voltage drop VCE (sat) among all fully controlled
switches. Therefore, a BJT is suitable for switching large current at moderate (around a few
KHZ) switching frequency. At high frequency BJT based circuits tend to become inefficient due
to increased switching power loss.
Even without any restriction on the switching power loss the maximum switching frequency of a
BJT is limited by its Turn ON and Turn OFF times. The value of the maximum switching
frequency is given by
1
FSW ( Max ) = ( 3.10 )
TSW ( ON ) + TSW ( OFF )
For a given collector current and base drive design.
For safe switching operation, however it is not sufficient to merely restrict the switching power
loss. It will be necessary to restrict the switching trajectory (an instantaneous plot of ic vs VCE
during switching with time as a parameter) within the FBSOA /RBSOA region corresponding to
a pulse width greater than TSW (ON) or TSW (OFF). Fig 3.7 (b) shows these switching trajectories
superimposed on the FBSOA /RBSOA. In this diagram the green line corresponds to the Turn
ON trajectory while the blue line corresponds to the Turn OFF trajectory. These trajectories are
rectangular in nature. Clearly full voltage (VCEO) or current rating (ICM) of the transistor can not
be utilized in such a trajectory. The situation becomes worse a when the reverse recovery current
and forward recovery voltage of D is considered. Switching aid circuits or “snubbers” (as they
are popularly known) are used to enhance the switching performance of a power transistor. They
serve two specific purpose.
• Shape the switching trajectory such that the voltage and current rating of a transistor can
be fully utilized.

• Reduce the switching power loss inside the device.
Fig. 3.8 shows a typical snubber circuit for a power transistor and the corresponding switching
trajectories.
VCC
IL
LS RS
iC
+ DS
Q VCE
RB iB CS
-
VBB +
(a)
logic
ICM
IL
RBSO
FBSO
A
Turn VCBO
on VCC
Turn off
log vCE
VCE(sus) VCEO
(b)
Fig. 3.8: Switching characteristics of a BJT with Snubber
(a) Clamped inductive switching circuit with snubber
(b) Switching trajectory.
Fig 3.8 (a) shows the same clamped inductive switching circuit of Fig 3.6 (a) but with the
snubber elements. The inductor LS connected between the load and the collector is the Turn ON
snubber. In decouples the collector from the supply voltage during Turn ON. Therefore, as the
junction VBE becomes forward biased VCE starts falling. At the same time ic also starts rising
towards IL. The resultant switching trajectory is shown by the solid green line in Fig 3.8 (b). This
should be compared with the unsnubbed Turn ON trajectory (broken green line). In the
unsnubbed case, the collector current rises to the maximum value before VCE starts falling from
VCC. VCC, therefore, must necessarily be smaller than VCE (SUS). In the snubber assisted
trajectory VCE falls substantially before ic rises to any appreciable value. Therefore, VCC can be
made larger than VCE(sat) and can be chosen closer to VCEO. Maximum collector current that can
be handled is also considerably higher (I L Max )
= ICM - Irr ( D ) . In the unsnubbed case
maximum IL is restricted essentially by the maximum power dissipation consideration and not by
ICM. LS also helps to reduce Irr (D) by restricting the rate of decrease of current through D. This
also helps to increase I L Max
Rs-Cs-Ds constitute the Turn OFF snubber. This is popularly known as the “R-C-D snubber”.
During Turn OFF as the base drive of Q is removed ic starts falling and the remaining load
current is bypassed to Cs through Ds. Therefore, the collector voltage rises simultaneously giving
rise to the Turn OFF trajectory shown by the solid blue line in Fig 3.8 (b). At the end of the Turn
OFF process VCE shoots over VCC due to Ls-Cs oscillation. However, by proper design VCE Max
can be restricted well below VCBO. Therefore, the turn OFF snubber circuit can effectively utilize
the enhanced voltage withstanding capability of a power transistor with base reverse biased.
Comparison of the switching trajectories with and with out snubber circuit makes it evident that
the snubber circuit can considerably enhance the voltage and current capacity utilization of a
Power transistor.
The area enclosed under the switching trajectories is a measure of the switching loss occurring in
the device at each switching. Therefore, it is evident from Fig 3.8 (b) that the snubber circuit
reduces the switching power loss inside the device considerably. However, it should be
emphasized that the total switching loss (device + snubber resistance) may not reduce. It is also
necessary to place the snubber components very close to the transistor since any stray inductance
in the Rs – Cs – Ds loop may give rise to an unacceptably large voltage spike across Q.
Components should also be chosen very carefully. Rs must be non inductive and the lead
inductances of Ds and Cs must be kept to a minimum Power loss in Rs can be considerably large
and its wattage should selected accordingly. To avoid excessive power loss in Rs, lossless
(regenerate) snubber circuits have been proposed.
Exercise 3.10
a) BJT has large switching times, since it is a _________________ carrier device.

b) BJT has _______________ ON state voltage drop.
c) BJT is inefficient at ______________ switching frequencies.

d) Turn OFF snubber circuit is used to improve _______________ withstand capacity of a
BJT.
Answer: (a) minority; (b) low; (c) high; (d) voltage.
Exercise 3.11
What are the effects of introducing a drift region in the output i-v characteristics of a power
transistor?
Answer: The drift region in a power transistor is introduced in order to block large forward
voltage. However, one effect of introducing the drift region is the appearance of a
“quasi saturation region” in the output i-v characteristics of a power transistor. In the
quasi saturation state the drift region is not completely shorted out by “conductivity
modulation” by excess carriers from the base region. In offers a resistance which is a
function of the base current. Although the base current retain some control over
collector current in this state the value of dc current gain reduces substantially due to
increased effective base width.
Another effect of introducing the drift region is to make the VCE saturation voltage
depend linearly on the collector current in the hard saturation region due to the ohmic
resistance of the “conductivity modulated” drift region.
Exercise 3.12
Explain the importance of the following manufacturer’s specifications

(a) FBSOA, (b) β vs ic characteristics, (c) iB vs VBE characteristics
B
Answer: (a) FBOSOA compactly represents the safe operating limits of a power transistor in
terms of maximum forward current, maximum forward voltage, maximum average &
instantaneous power dissipation and second break down limits. It is most useful in
designing the switching trajectory of a power transistor.
(b) This characteristics gives the amount of base current required so that the transistor
can operate in the saturation mode for a given collector current.
(c) After the base current is determined, this characteristics is used to design the base
drive circuit for a given base power source.
3.5.4 Base Drive Design and Power Darlington

The performance of a Power transistor depends largely on the base drive design.
• The rate of rise of base current in the beginning of the turn on process determines the turn on
delay time.
• The magnitude of the base current during turn on decides the values of the voltage fall time,
current rise time and VCE (sat) for a given collector current.
• The negative base current during turn off determines the storage time, voltage rise time and
current fall time.
• A negative bias at the base also enhances the voltage withstanding capacity of a power
transistor.
From the discussion of the switching characteristics of a BJT it is evident that the base drive
voltage source should be bipolar and the base drive resistance should be different during turn
on and turn off. The following step by step procedure can be followed to arrive at the values.
• From the load current value (to be switched) and desired conduction power loss the desired
value of VCE (sat) is determined.
• Using the desired value of VCE (sat) for the given load current, the required value of forward
base current (iBP) and the corresponding VBE (sat) is obtained from the manufacturer’s data
sheet.
• The forward and reverse base drive voltages (VBB + & VBB -) are decided on the basis of the
availability of control power supply. These should be kept as low as possible in order to
reduce base drive power requirement.
• The forward base drive resistance RBP is given by
VBB+ - VBE ( sat )

R BP = ( 3.11)
i BP
It has been mentioned earlier that the turn on delay time can be reduced by increasing the rate
of rise of iBP at the beginning of the turn ON process. This is achieved by connecting a small
capacitor across RBP.
• Once iBP is known the turn on loss is fixed. The allowable turn off loss is determined by
subtracting the turn on loss for the desired total switching loss. The required current fall and
voltage rise times for the calculated turn off loss is determined for the given load current and
VCC.
• A suitable negative base current (iBN) to give the desired voltage rise time is determined from
the manufacturer’s data sheet.
• RBN is given
VBB- + VBE ( sat )

R BN = ( 3.12 )
i BN

• Once iBN is fixed the storage time (ts) can be determined from the manufacturer’s data sheet.
• The storage time can be reduced by connecting a small capacitor across RBN.
The resulting base drive circuit can be realized as shown in Fig 3.9
VBB +
RBP
R1
R3
From Q
Control
circuit Optocoupler
R2 RBN
Electrical
Isolation VBB -
Fig 3.9: Typical base drive circuit of a power transistor
Power transistors have low values of dc current gain (β) compared to their signal level
counterpart. Particularly, if a low value of VCE (sat) is desired at full load current, β can be as
low as 5. With such low gain large current switching becomes difficult since the base drive
circuit is required to handle about 20% of the full load current, Monolithic, Darlington connected
transistors can solve this problem. Fig 3.10 shows the circuit connection and the vertical cross
section of a Monolithic Darlington pair. The effective current gain of a Darlington pair is given
by
β = β Mβ D + β M + β D ( 3.13)
So that even when individual β’s are small effective β can still be quite large.

C
iCD IL
B IBD iCM
QD
iED
QM
iBM
D
E
(a)
B iED E
n+ n+
iBD iBM
p sio2 p’
n- iCD n- iCM
n+ n+
C
(b)
Fig 3.10: Monolithic Darlington connected power transistor.
(a) circuit diagram, (b) schematic cross section.

In the Darlington configuration the base drive current for the main transistor is derived from the
collector biasing power supply through a drive transistor. This drive transistor should have the
same voltage rating as the main transistor but lower current rating. In a monolithic design both
are fabricated from the same crystal. The silicon protrusion through the p layer (the base region
for both transistors) isolates the two bases from each other. A discrete diode D is added (Fig 3.10
(a)) to speed up the turn off time of the main transistor.
The major quantitative difference in the operating characteristics of a Power Darlington is due to
the fact that the main transistor can not go into hard saturation. The ON state voltage drop of the
drive transistor prevents forward biasing of the C-B junction of the main transistor. Therefore,
the ON state power dissipation of the main transistor will be larger than that of an otherwise
comparable single BJT. The switching times will also be somewhat larger for the Darlington
transistor.
Exercise 3.13
A Power BJT is used to switch an inductive load carrying 20 A. The supply voltage is 200V,
switching frequency and duty cycle are 1 KHZ and 0.5 respectively. Switching times are as
follows. td = 1μs, tri = tfv1 = 8 μs, tfv2 = 0, ts = 12 μs, tfi = trv2 = 8 μs, trv1 = 0.
VCE sat = 1.0V at i c = 20 A
Calculate switching and conduction losses in the transistor.
Answer: Turn on energy loss is given by.

1
E ON = V I ( t + t ) = 32 mJ
2 CC L ri fv1
Turn off energy loss is given by
E off = 1 VCC I L ( t fi + t rv2 ) = 32mJ

2
So total energy loss per switching = EON + E0ff = 64 mJ.
∴ Switching power loss = fsw (EON + Eoff) = 64 watts.
Conducting loss per switching is given by
E COND = I L VCE sat ( D fsw - t d )

- t ri - t fv + t s = 9.9 mJ
∴ Conduction power loss = 9.9 watts.
Exercise 3.14
With reference to Fig. 3.9 determine the values of the base resistors RBP & RBN for the following
data
VBB+ = 10 volts, VBB- = -10 V, IBP = 2.5 A, IBN = 1.5 A, VBE sat = 0.7 V , VCE sat (of
drive transistors) = 0.3 V

VBB + - VBE sat - VCE
Answer: R BP = sat
= 3.6 ohms.
I BP
VBE sat - VCE sat - VBB-
R BN = = 6.93 ohms
I BN

References
1) Jacob Millman, Christos C. Halkis, “Integrated Electronics, Analog and Digital circuit
and systems”, Tata McGrow-Hill publishing Company Limited, New Delhi, 1991.
2) Ned Mohan, Tore M. Undeland, William P. Robbins, “Power Electronics, Converters,
Application and Design”. John Willey & Sons (Asia) Publishers, Third Edition, 2003.

Lesson Summary
• A Bipolar Junction Transistor is a minority carrier, current controlled unidirectional

device.
• A BJT can be of n-p-n or p-n-p type with three terminals called the collector, the base
and the emitter.
• A BJT can operate in cut-off, active or saturation regions.
• In the cut-off region the base emitter junction is reverse biased and the collector current is
almost zero.
• In the active region the ratio of collector current to base current is fairly constant. This
ratio is called the dc current gain (β).
• A transistor can be driven into saturation by increasing the base current for a given
collector current. In saturation the VCE voltage drop of a transistor is very low.
• For power application normally, n-p-n type transistor in the common emitter
configuration with the base as the control terminal is used. They operate either in the cut-
off, or saturation mode.
• For safe operation power transistors must observe maximum current, maximum voltage,
maximum power dissipation and second break down limits.
• Operating restrictions applicable to a power transistor under forward and reverse bias
conditions are represented compactly in FBSOA & RBSOA diagrams respectively.
• Power transistor output i-v characteristics exhibits a quasi saturation region not found in
their signal level counterpart. It is the direct consequence of introducing a lightly doped
n- drift region in the structure of a power transistor which enhances its forward voltage
blocking capacity.
• Switching of Power transistors from ON (saturation) to OFF (cut-off) state involves
considerable redistribution of minority carriers. Therefore, switching operation is not
instantaneous.
• Switching characteristics of a power transistor is greatly influenced by the external load
circuit and the base drive circuit.
• Energy loss takes place during each switching operation of a power transistor due to
simultaneous existence of collector current and voltage. This is called switching loss.
• Energy loss taking place during ON condition of the transistor is called the conduction
loss. Conduction loss during the OFF state of a Power transistor is negligibly small.
• Switching power loss is proportional to the switching frequency while the conduction
power loss is proportional to the duly cycle.
• BJT being a minority carrier device have low on state voltage drop and longer switching
delay times compared to some “majority” carrier “transistors”. Consequently, BJT has
higher switching loss and lower conduction loss.
• A Power transistor is suitable for large current switching at low to moderate (a few kHZ)
frequency.

• Switching aid circuits (snubbers) are used for enhancing the capacity utilization of a
power transistor. They also reduce switching loss internal to the device.
• Ordinary L-R-C-D snubber circuits may not reduce total switching loss. For that purpose
lossless (regenerative) snubber circuits are used.
• Proper design of the base drive circuit helps to reduce both conduction and switching
losses. For optimal operation, base drive voltage should be bipolar and have different
output resistance for Turn ON and Turn OFF operations.
• Power transistors have relatively small current gain (β) and hence require large base drive
current.
• Monolithic Power Darlingtons can solve the problem of low current gain. But they have
larger ON state voltage drop and longer switching times.


VCC = 200V
RL = 20Ω
RB
+
VBB = 12V
1. In the transistor switching circuit VBE sat = 0.75 V, VCE sat = 0.2 V 10 ≤ β ≤ 40 .
Find out the value of RB and Power requirement of the base source.
B
VCC = 200V
RL = 20Ω
D3
RB
+
D1 D2
VBB = 12V
2. In the transistor switching circuit shown

VBE sat = 0.75 v, VD1 = VD2 = VD3 = 0.7 v, 10 ≤ β ≤ 40
Find maximum allowable value of RB and power output of the base source. Also compare
B
conduction power loss with the circuit shown in Problem – 1.
3. The transistor of Problem -1 has the following switching time specifications.

td = 1μs, tri = tfv = 2.5 μs, ts = 5 μs, tfi = trv = 2.5 μs. The transistor is switched at a frequency
of 10 KHZ with duty ratio d = 0.5. Find out, (i) conduction power loss, (ii) switching power
loss.

VBB ∫∫
50μs 50μs
∫∫ ∫∫ t
iC ∫∫
10 A
∫∫ ∫∫ t
td t ts tfi
ri
VCE ∫∫
200v 200v
∫∫ t
tfv trv
PSW (on) PSW (off)
Ploss
PCOND
4. Figure shows practical implementation of a power transistor base drive circuit. The
comparator has an output voltage swing of ± 12 V.
Also
For QP
VBE sat = 0.7V, VCE sat = 0.2V,
For QN
VBE sat = - 0.7 V, VCE sat = - 0.2 V,
For Q
VBE sat = 0.75 V. β Min = 10. Also it is desired that negative base current should be at least
equal to positive base current. β Min of QP & QN are same. Find the values of RBP, RBN and
R1
5. Explain why the dc current gain of a Power BJT is considerably lower compared to its Signal
level counterpart. What adverse effect does it have on the switching performance of a BJT?
Suggest one solution to this problem.

6. Differentiate between the voltage ratings VSUS, VCEO & VCBO of a Power BJT. How can these
three voltage ratings of a BJT be utilized in an inductive switching circuit.
7. The pulsed FBSOA of a Power BJT is usually specified for a very low duty cycle. Then now
does it help to extend the usable voltage and current rating of a BJT?
Answer to Test Problems

200 - VCE sat
1. The load current I L = i c = ≈ 10 Amps
20
VCE sat = 0.2V, which indicates that the transistor is in hard saturation. Therefore β = βmin = 10.
ic
So required base current = = 1 amps
10
VBE sat = 0.75 volts ∴ R B = VBB - VBE sat = 11.25 Ω
Power drawn from base source is 12 × 1 = 12 watts.
2. In this case VCE = VBE sat + VD2 + VD1 - VD3 = 1.45 volts . The transistor is not in saturation
since VCB is positive. So β = βmax = 40
200 -1.45
IL = ic = = 9.93 Amps.
20
i
∴ i B = c = 0.25 Amps.
β
For maximum value of RB current through D3 will be zero
B
V -V -V -V
So R B = BB D1 D2 BE sat = 39.4 Ω
iB
Power Drawn from base source is 12 × 0.25 = 3 watts.
Conduction power lass in 1st problem was 10 × 0.2 = 2 watts
Conduction power lass in this case is 9.93 × 1.45 = 14.4 watts
Note: This circuit is known as the anti-saturation clamp or the “Baker’s clamp”.

+ 15v
+ 12v VCC
RBP
IL = 50 A
iC1
iB1
QP
10 KΩ
Rl iE1
comp 0 A
B
QP
TTL iB
iE2
Pulse
E
QN
1.5v iB2
iC2
RBN
- 12v
- 15v
3. Figure shows switching waveforms of the transistor. Major difference with clamped inductive
switching waveform is that in this case rise and fall of ic & VCE are simultaneous. In the
interval t ri ( or t fv )
t
ic = 10 = 4×106 t
t ri
VCE ≈ 200 ⎛⎜ 1- t ⎞⎟ = 200 ( 4 × 105 t ) .

⎝ t fv ⎠
where VCE sat has been neglected.
In the interval t fi ( or t rv )
i c = 10 ⎛⎜1- t ⎞⎟ = 10 (1 - 4 × 105 t )
⎝ t fi ⎠
VCE = 200 t = 80 × 10 6 t
t rv

t ri
∴ E SW ( ON ) =
∫ o
VCE i c dt
2.5×106
8×108 t (1- 4×105t ) dt
=
∫ o
= 0.83 mJ
t fi 2.5×106
8×108 t (1- 4×105 t ) dt
E SW ( OFF ) =
∫ o
VCE i c dt =
∫o
= 0.83 mJ
∴ E SW = E SW ( ON ) + E SW ( OFF ) = 1.66 mJ
∴ PSW = E SW × f SW = 1.66×10-3 × 10 × 103 = 16.6 watts.
Conduction loss occurs in the interval from the end of tri to the beginning of tfi
∴ E COND = VCE sat × I L × ( TON - td - t ri + t s )

= 0.103 mJ
∴ PCOND = E COND × f SW = 0.103 × 10 -3 × 10 × 103 = 1.03 watts.
4. For the transistor Q, β Min = 10 , & ic = 50 A.

∴required positive i BP = 50 = 5 Amps
10
Now i BP = i E1 = i c1 + i B1
12 - VAB - VBE 10.55
Now i B1 = =
R1 R1
15 - VCE sat - VBE 14.1
i C1 = =
R BP R BP
10.55 14.1
So + = 5
R1 R BP
Now iBN ≥ iBP = 5A
i BN = i E2 = i B2 + i C2
VBE - VBA + 12 12.05
i B2 = =
R1 R1
VBE - VEC2 + 15 15.55
i C2 = =
R BN R BN
12.05 15.55
So + ≥ 5
R1 R BN
Now βmin of QP & QN are same.

i C1 i
So = C2
i B1 i B2
14.1 R 1 15.55 R 1
or =
10.55 R BP 12.05 R BN
14.1 R 1 5R 1
Now 1 + =
10.55 R BP 10.55
10.55 R 1 5R 1
1+ ≥
12.05 R BN 12.05
⎛ 1 1 ⎞
∴ 0 ≥ 5R 1 ⎜ - ⎟
⎝ 12.05 10.55 ⎠
or R 1 > 0
choose R 1 = 100 Ω
∴ R BP = 2.88 Ω
R BN = 2.78 Ω
5. The main reason for comparatively lower dc current gain in a power transistor is a relatively
thicker base region (a few tens of μm compared to a fraction of a μm incase of a signal
transistor). The thicker base region is required to withstand the large blocking voltage.
Unlike a power diode the doping density of the base region cannot be made very much large
compared to the lightly doped collector drift region since it will reduce “β” by increasing
minority carrier injection into the emitter. As a result the depletion layer at the C-B junction
penetrates considerably in to the base region. The base width has to be larger than this
penetration depth. A thicker base leads to larger rate of recombination of minority carriers
injected by the emitter. Therefore, for a given collector current the required base current is
relatively high and the dc current gain is low.
A second reason for lowering of β arises from the “emitter crowding” effect where by the
collector current tends to “crowd” near specific regions of the emitter. In these localized high
current density regions β tends to fall off very sharply reducing the effective dc current gain.
Due to lower dc current gain the base current requirement of a power transistor switching
circuit increases. This requires a large base drive power supply and increased base drive
power loss.
This problem can be solved to some extent by using two power transistors connected in the
“Darlington configuration” as shown.

iCD iL
iBD
QD
βD iCM
βM QM
iED
For this configuration.
i L = i CD + i CM
But i CD = β D i BD
i CM = β M i ED = β M ( i BD + i CD )
∴ i L = β Di BD + β Mi BD + β Mβ Di BD
= (β M + β D + β Mβ D ) i BD = β eqv i BD
equivalent β (βeqv) can be increased considerably due to multiplication of βM & βD.
Power Darlington has one problem, however. The main transistor (QM) does not go into hard
saturation due to VCE drop of QD. Therefore, the conduction loss is higher.
6. The voltage rating VSUS is the maximum allowable voltage across C & E when the transistor
is in active region with iB > 0 and collector current above a minimum value.
B
With both iB and iC greater than zero, there is considerable supply of minority carriers which
B
are accelerated by the large CB junction electric field to start avalanche breakdown at a
relatively lower voltage. Therefore, the voltage rating VSUS is the lowest of the three.
The rating VCEO is the maximum allowable voltage between C & E terminals when the
transistor is in cut off region with iB = 0 or iC is less than a specified value. Under this
B
condition the supply of minority carriers at the CB junction is much less compared to the
previous case. Therefore, avalanche breakdown of the CB junction occurs at a higher voltage.
Thus VCEO > VSUS.
The rating VCBO is the maximum allowable voltage between C & E terminals when the
transistor is in cut off with iB < 0 and iC less than a specified value. With iB = 0 the EB
B B
junction is still forward biased and there is small injection of minority carriers from the
emitter to the CB junction. However, with iB < 0 base emitter junction is reverse biased and
B
there is no supply of minority carriers to the CB junction from the emitter. Thus avalanche

break down of this junction occurs at a relatively higher voltage making the rating VCBO
largest of the three. Therefore, in general for a power transistor.
VCBO > VCEO > VSUS
In an inductive switching circuit using snubber the collector voltage falls considerably before
iC builds up to any significant level. This can be utilized to increase the usable steady state
blocking voltage of the transistor up to VCEO. Since VCE will go below VSUS before iC can
build up to the level where the rating VSUS becomes applicable.
Similarly during turn off, the overshoot in the VCE voltage can be accommodated in the
difference between VCBO and VCEO. Since during turn off iB < 0 and the voltage. overshoot
B
occurs with iC = 0 the applicable voltage limit will be VCBO and not VCEO. However,
precaution must be taken such that the voltage over shoot decays before iB becomes equal to
B
zero.
However, if a snubber circuit is not used the applicable voltage limit will always be VSUS
since in this case VCE does not fall till iC rises to its full value during turn ON. Similarly
during turn off iC does not fall till VCE rises to steady state blocking voltage level.
log iC
ICM
BP Pulsed
CP
CD DC BD
O
AD AP log vCE
7. The main difference between the DC and pulsed FBOSA is in the boundary corresponding to
maximum power dissipation and second break down. With only DC FBSOA the switching
trajectory has to be restricted to something similar to AD BD CD. However, with pulsed
FBSOA applicable limits of power dissipation and second break down increases
considerably. Both these limits require simultaneous existence of nonzero VCE & iC which for
a power transistor occurs only during switching. Therefore, the increases FBSOA can be
utilized and the switching trajectory improved to AP BP CP provided total switching time is
less than the pulse period for which the increased FBSOA is applicable.

In addition pulsed FBSOA s are usually specified for a very low duty ratio. This condition
can be easily satisfied provided total turn on and turn off times of the transistor expressed as
a percentage of total “ON” and “OFF” periods of the transistor is less than this duty ratio
since during ON or OFF period the transistor remain well within DC FBSOA. In practice this
condition is satisfied by specifying a minimum ON and OFF period of the transistor.

Module
1
Power Semiconductor
Devices
Lesson
4
Thyristors and Triacs
Instructional objects
On completion the student will be able to
• Explain the operating principle of a thyristor in terms of the “two transistor analogy”.
• Draw and explain the i-v characteristics of a thyristor.
• Draw and explain the gate characteristics of a thyristor.
• Interpret data sheet rating of a thyristor.
• Draw and explain the switching characteristics of a thyristor.
• Explain the operating principle of a Triac.

4.1 Introduction
Although the large semiconductor diode was a predecessor to thyristors, the modern power
electronics area truly began with advent of thyristors. One of the first developments was the
publication of the P-N-P-N transistor switch concept in 1956 by J.L. Moll and others at Bell
Laboratories, probably for use in Bell’s Signal application. However, engineers at General
Electric quickly recognized its significance to power conversion and control and within nine
months announced the first commercial Silicon Controlled Rectifier in 1957. This had a
continuous current carrying capacity of 25A and a blocking voltage of 300V. Thyristors (also
known as the Silicon Controlled Rectifiers or SCRs) have come a long way from this modest
beginning and now high power light triggered thyristors with blocking voltage in excess of 6kv
and continuous current rating in excess of 4kA are available. They have reigned supreme for two
entire decades in the history of power electronics. Along the way a large number of other devices
with broad similarity with the basic thyristor (invented originally as a phase control type device)
have been developed. They include, inverter grade fast thyristor, Silicon Controlled Switch
(SCS), light activated SCR (LASCR), Asymmetrical Thyristor (ASCR) Reverse Conducting
Thyristor (RCT), Diac, Triac and the Gate turn off thyristor (GTO).
From the construction and operational point of view a thyristor is a four layer, three terminal,
minority carrier semi-controlled device. It can be turned on by a current signal but can not be
turned off without interrupting the main current. It can block voltage in both directions but can
conduct current only in one direction. During conduction it offers very low forward voltage drop
due to an internal latch-up mechanism. Thyristors have longer switching times (measured in tens
of μs) compared to a BJT. This, coupled with the fact that a thyristor can not be turned off using
a control input, have all but eliminated thyristors in high frequency switching applications
involving a DC input (i.e, choppers, inverters). However in power frequency ac applications
where the current naturally goes through zero, thyristor remain popular due to its low conduction
loss its reverse voltage blocking capability and very low control power requirement. In fact, in
very high power (in excess of 50 MW) AC – DC (phase controlled converters) or AC – AC
(cyclo-converters) converters, thyristors still remain the device of choice.
4.2 Constructional Features of a Thyristor

Fig 4.1 shows the circuit symbol, schematic construction and the photograph of a typical
thyristor.

A
A
p
n-
G p
K n+ n+
(a) G
(c)
K
(b)
Fig. 4.1: Constructional features of a thysistor

(a) Circuit Symbol, (b) Schematic Construction, (c) Photograph
As shown in Fig 4.1 (b) the primary crystal is of lightly doped n- type on either side of
which two p type layers with doping levels higher by two orders of magnitude are grown. As in
the case of power diodes and transistors depletion layer spreads mainly into the lightly doped n-
region. The thickness of this layer is therefore determined by the required blocking voltage of the
device. However, due to conductivity modulation by carriers from the heavily doped p regions
on both side during ON condition the “ON state” voltage drop is less. The outer n+ layers are
formed with doping levels higher then both the p type layers. The top p layer acls as the “Anode”
terminal while the bottom n+ layers acts as the “Cathode”. The “Gate” terminal connections are
made to the bottom p layer.
As it will be shown later, that for better switching performance it is required to maximize
the peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions are
finely distributed between gate contacts of the p type layer. An “Involute” structure for both the
gate and the cathode regions is a preferred design structure.
4.3 Basic operating principle of a thyristor

The underlying operating principle of a thyristor is best understood in terms of the “two
transistor analogy” as explained below.

A
A A
IA
p p Q1 (α1)
J1
iC2 iC1
- -
n n
IG
J2 (α2) Q2 G
p p n-
G J2
n+ n+ J3 p
J3 IK
n+
K
G
K
K
(a) (b) (c)
Fig. 4.2: Two transistor analogy of a thyristor construction.

(a) Schematic Construction, (b) Schematic division in component
transistor
(c) Equivalent circuit in terms of two transistors.
a) Schematic construction,
b) Schematic division in component transistor
c) Equivalent circuit in terms of two transistors.
Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode
positive with respect to the cathode and the gate terminal open. With this voltage polarity J1
& J3 are forward biased while J2 reverse biased.
Under this condition.
ic1 = ∝1 I A + I co1 ( 4.1)

ic 2 = ∝ 2 I K + I co2 ( 4.2 )
Where ∝1 & ∝2 are current gains of Q1 & Q2 respectively while Ico1 & Ico2 are reverse
saturation currents of the CB junctions of Q1 & Q2 respectively.
Now from Fig 4.2 (c).

i c1 + i c2 = I A ( 4.3)
& IA = IK ( 4.4 ) (∵ I G = 0 )
Combining Eq 4.1 & 4.4
I co1 + I co2 I co
IA = =
1- ( ∝1 + ∝ 2 ) 1- ( ∝1 + ∝ 2 )
( 4.5 )

Where I co I co1 + I co2 is the total reverse leakage current of J2
Now as long as VAK is small Ico is very low and both ∝1 & ∝2 are much lower than unity.
Therefore, total anode current IA is only slightly greater than Ico. However, as VAK is increased
up to the avalanche break down voltage of J2, Ico starts increasing rapidly due to avalanche
multiplication process. As Ico increases both ∝1 & ∝2 increase and ∝1 + ∝2 approaches unity.
Under this condition large anode current starts flowing, restricted only by the external load
resistance. However, voltage drop in the external resistance causes a collapse of voltage across
the thyristor. The CB junctions of both Q1 & Q2 become forward biased and the total voltage
drop across the device settles down to approximately equivalent to a diode drop. The thyristor is
said to be in “ON” state.
Just after turn ON if Ia is larger than a specified current called the Latching Current IL, ∝1 and
∝2 remain high enough to keep the thyristor in ON state. The only way the thyristor can be
turned OFF is by bringing IA below a specified current called the holding current (IH) where
upon ∝1 & ∝2 starts reducing. The thyristor can regain forward blocking capacity once excess
stored charge at J2 is removed by application of a reverse voltage across A & K (ie, K positive
with respect A).
It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to
cathode) without increasing the forward voltage across the device up to the forward break-over
level. With a positive gate current equation 4.4 can be written as
IK = IA + IG ( 4.6 )
∝ 2 I G + I co
Combining with Eqns. 4.1 to 4.3 I A =
1- ( ∝1 + ∝ 2 )
( 4.7 )
Obviously with sufficiently large IG the thyristor can be turned on for any value of Ico (and hence
VAK). This is called gate assisted turn on of a Thyristor. This is the usual method by which a
thyristor is turned ON.
When a reverse voltage is applied across a thyristor (i.e, cathode positive with respect to anose.)
junctions J1 and J3 are reverse biased while J2 is forward biased. Of these, the junction J3 has a
very low reverse break down voltage since both the n+ and p regions on either side of this
junction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported by
junction J1. The maximum value of the reverse voltage is restricted by
a) The maximum field strength at junction J1 (avalanche break down)

b) Punch through of the lightly doped n- layer.
Since the p layers on either side of the n- region have almost equal doping levels the avalanche
break down voltage of J1 & J2 are almost same. Therefore, the forward and the reverse break
down voltage of a thyristor are almost equal.Up to the break down voltage of J1 the reverse
current of the thyristor remains practically constant and increases sharply after this voltage.
Thus, the reverse characteristics of a thyristor is similar to that of a single diode.

If a positive gate current is applied during reverse bias condition, the junction J3 becomes
forward biased. In fact, the transistors Q1 & Q2 now work in the reverse direction with the roles
of their respective emitters and collectors interchanged. However, the reverse ∝1 & ∝2 being
significantly smaller than their forward counterparts latching of the thyristor does not occur.
However, reverse leakage current of the thyristor increases considerably increasing the OFF state
power loss of the device.
If a forward voltage is suddenly applied across a reverse biased thyristor, there will be
considerable redistribution of charges across all three junctions. The resulting current can
become large enough to satisfy the condition ∝1 + ∝2 = 1 and consequently turn on the thyristor.
This is called dv turn on of a thyristor and should be avoided.
dt
Exercise 4.1
1) Fill in the blank(s) with the appropriate word(s)
i. A thyristor is a ________________ carrier semi controlled device.

ii. A thyristor can conduct current in ________________ direction and block voltage in
________________ direction.
iii. A thyristor can be turned ON by applying a forward voltage greater than forward
________________ voltage or by injecting a positive ________________ current pulse
under forward bias condition.
iv. To turn OFF a thyristor the anode current must be brought below ________________
current and a reverse voltage must be applied for a time larger than ________________
time of the device.
v. A thyristor may turn ON due to large forward ________________.
Answers: (i) minority; (ii) one, both; (iii) break over, gate; (iv) holding, turn off;
(v) dv
dt
2. Do you expect a thyristor to turn ON if a positive gate pulse is applied under reverse bias
condition (i. e cathode positive with respect to anode)?
Answer: The two transistor analogy of thyristor shown in Fig 4.2 (c) indicates that when a
reverse voltage is applied across the device the roles of the emitters and collectors of the
constituent transistors will reverse. With a positive gate pulse applied it may appear that the
device should turn ON as in the forward direction. However, the constituent transistors have very
low current gain in the reverse direction. Therefore no reasonable value of the gate current will
satisfy the turn ON condition (i.e.∝1 + ∝2 = 1). Hence the device will not turn ON.

4.4 Steady State Characteristics of a Thyristor
4.4.1 Static output i-v characteristics of a thyristor

IA VBRF
+ VAK -
A IA K
ig Ig
ig1 ig2 ig3 ig4
VBRR VBRF
IL
Is IH
VAK
ig4 > ig3 > ig2 > ig1 > ig = 0
VH
ig4 > ig3 > ig2 > ig1 > ig = 0
Fig. 4.3: Static output characteristics of a Thyristor
The circuit symbol in the left hand side inset defines the polarity conventions of the variables
used in this figure.
With ig = 0, VAK has to increase up to forward break over voltage VBRF before significant anode
current starts flowing. However, at VBRF forward break over takes place and the voltage across
the thyristor drops to VH (holding voltage). Beyond this point voltage across the thyristor (VAK)
remains almost constant at VH (1-1.5v) while the anode current is determined by the external
load.
The magnitude of gate current has a very strong effect on the value of the break over voltage as
shown in the figure. The right hand side figure in the inset shows a typical plot of the forward
break over voltage (VBRF) as a function of the gate current (Ig)
After “Turn ON” the thyristor is no more affected by the gate current. Hence, any current pulse
(of required magnitude) which is longer than the minimum needed for “Turn ON” is sufficient to
effect control. The minimum gate pulse width is decided by the external circuit and should be
long enough to allow the anode current to rise above the latching current (IL) level.

The left hand side of Fig 4.3 shows the reverse i-v characteristics of the thyristor. Once the
thyristor is ON the only way to turn it OFF is by bringing the thyristor current below holding
current (IH). The gate terminal has no control over the turn OFF process. In ac circuits with
resistive load this happens automatically during negative zero crossing of the supply voltage.
This is called “natural commutation” or “line commutation”. However, in dc circuits some
arrangement has to be made to ensure this condition. This process is called “forced
commutation.”
During reverse blocking if ig = 0 then only reverse saturation current (Is) flows until the reverse
voltage reaches reverse break down voltage (VBRR). At this point current starts rising sharply.
Large reverse voltage and current generates excessive heat and destroys the device. If ig > 0
during reverse bias condition the reverse saturation current rises as explained in the previous
section. This can be avoided by removing the gate current while the thyristor is reverse biased.
The static output i-v characteristics of a thyristor depends strongly on the junction temperature as
shown in Fig 4.4.
VBRF IA
Tj =
150° 135° 25° 75° 125°
25° 75° 125° 150° Tj
VAK
Tj = 125° 75° 25° 135° 150°
Fig. 4.4: Effect of junction temperature (Tj) on the output

i – v characteristics of a thyristor.
4.4.2 Thyristor Gate Characteristics

The gate circuit of a thyristor behaves like a poor quality diode with high on state voltage drop
and low reverse break down voltage. This characteristic usually is not unique even within the
same family of devices and shows considerable variation from device to device. Therefore,
manufacturer’s data sheet provides the upper and lower limit of this characteristic as shown in
Fig 4.5.

Vg Vg max A
E c d
Rg
ig
• S2 E Vg
Pgav ⎜Max
Load line
Pgm K
Vg min b e
h
S1
Vng •
f
g Ig max
Ig min Ig
Fig. 4.5: Gate characteristics of a thyristor.
Each thyristor has maximum gate voltage limit (Vgmax), gate current limit (Igmax) and maximum
average gate power dissipation limit ( Pgav Max ) . These limits should not be exceeded in order to
avoid permanent damage to the gate cathode junction. There are also minimum limits of Vg
(Vgmin) and Ig (Igmin) for reliable turn on of the thyristor. A gate non triggering voltage (Vng) is
also specified by the manufacturers of thyristors. All spurious noise signals should be less than
this voltage Vng in order to prevent unwanted turn on of the thyristor. The useful gate drive area
of a thyristor is then b c d e f g h.
Referring to the gate drive circuit in the inset the equation of the load line is given by
Vg = E - Rgig
A typical load line is shown in Fig 4.5 by the line S1 S2.
The actual operating point will be some where between S1 & S2 depending on the particular
device.
For optimum utilization of the gate ratings the load line should be shifted forwards the Pgav Max
curve without violating Vg Max or IgMax ratings. Therefore, for a dc source E c f represents the
optimum load line from which optimum values of E & Rg can be determined.
It is however customary to trigger a thyristor using pulsed voltage & current. Maximum power
dissipation curves for pulsed operation (Pgm) allows higher gate current to flow which in turn
reduces the turn on time of the thyristor. The value of Pgm depends on the pulse width (TON) of
the gate current pulse. TON should be larger than the turn on time of the thyristor. For TON larger

than 100 μs, average power dissipation curve should be used. For TON less than 100 μs the
following relationship should be maintained.
δ Pgm ≤ Pgav Max ( 4.9 )

Where δ = TON f p, f p = pulse frequency.
The magnitude of the gate voltage and current required for triggering a thyristor is inversely
proportional to the junction temperature.
The gate cathode junction also has a maximum reverse (i.e, gate negative with respect to the
cathode) voltage specification. If there is a possibility of the reverse gate cathode voltage
exceeding this limit a reverse voltage protection using diode as shown in Fig 4.6 should be used.
A A
Rg
G
E E
K K
(a) (b)
Fig. 4.6: Gate Cathode reverse voltage protection circuit.
Exercise 4.2
i. Forward break over voltage of a thyristor decreases with increase in the

________________ current.
ii. Reverse ________________ voltage of a thyristor is ________________ of the gate
current.
iii. Reverse saturation current of a thyristor ________________ with gate current.
iv. In the pulsed gate current triggering of a thyristor the gate current pulse width should be
larger than the ________________ time of the device.
v. To prevent unwanted turn ON of a thyristor all spurious noise signals between the gate
and the cathode must be less than the gate ________________ voltage.

Answer: (i) gate; (ii) break down, independent; (iii) increases; (iv) Turn ON; (v) non-
trigger.
2) A thyristor has a maximum average gate power dissipation limit of 0.2 watts. It is triggered
with pulsed gate current at a pulse frequency of 10 KHZ and duly ratio of 0.4. Assuming the gate
cathode voltage drop to be 1 volt. Find out the allowable peak gate current magnitude.
Answer: On period of the gate current pulse is
0.4
TON = δ TS = δ = sec = 40 μs < 100 μs.
fs 10 4
Therefore, pulsed gate power dissipation limit Pgm can be used. From Equation 4.9
δ Pgm ≤ Pgav ( Max )

0.2
or Pgm ≤ watts = .5watts
δ
.5
But Pgm = Ig Vg; Vg = 1V ∴ I g Max = = 0.5Amps.
1
4.5 Thyristor ratings

Some useful specifications of a thyristor related to its steady state characteristics as found in a
typical “manufacturer’s data sheet” will be discussed in this section.
4.5.1 Voltage ratings

Peak Working Forward OFF state voltage (VDWM): It specifics the maximum forward (i.e,
anode positive with respect to the cathode) blocking state voltage that a thyristor can withstand
during working. It is useful for calculating the maximum RMS voltage of the ac network in
which the thyristor can be used. A margin for 10% increase in the ac network voltage should be
considered during calculation.
Peak repetitive off state forward voltage (VDRM): It refers to the peak forward transient
voltage that a thyristor can block repeatedly in the OFF state. This rating is specified at a
maximum allowable junction temperature with gate circuit open or with a specified biasing
resistance between gate and cathode. This type of repetitive transient voltage may appear across
a thyristor due to “commutation” of other thyristors or diodes in a converter circuit.
Peak non-repetitive off state forward voltage (VDSM): It refers to the allowable peak value of
the forward transient voltage that does not repeat. This type of over voltage may be caused due to
switching operation (i.e, circuit breaker opening or closing or lightning surge) in a supply
network. Its value is about 130% of VDRM. However, VDSM is less than the forward break over
voltage VBRF.

Peak working reverse voltage (VDWM): It is the maximum reverse voltage (i.e, anode negative
with respect to cathode) that a thyristor can with stand continuously. Normally, it is equal to the
peak negative value of the ac supply voltage.
Peak repetitive reverse voltage (VRRM): It specifies the peak reverse transient voltage that may
occur repeatedly during reverse bias condition of the thyristor at the maximum junction
temperature.
Peak non-repetitive reverse voltage (VRSM): It represents the peak value of the reverse
transient voltage that does not repeat. Its value is about 130% of VRRM. However, VRSM is less
than reverse break down voltage VBRR.
Fig 4.7 shows different thyristor voltage ratings on a comparative scale.

IA
VBRR VRSM VRRM VRWM
VAK
VDWM VDRM VDSM VBRF
Fig. 4.7: Voltage ratings of a thyristor.
4.5.2 Current ratings

Maximum RMS current (Irms): Heating of the resistive elements of a thyristor such as metallic
joints, leads and interfaces depends on the forward RMS current Irms. RMS current rating is used
as an upper limit for dc as well as pulsed current waveforms. This limit should not be exceeded
on a continuous basis.
Maximum average current (Iav): It is the maximum allowable average value of the forward
current such that
i. Peak junction temperature is not exceeded

ii. RMS current limit is not exceeded
Manufacturers usually provide the “forward average current derating characteristics” which
shows Iav as a function of the case temperature (Tc ) with the current conduction angle φ as a
parameter. The current wave form is assumed to be formed from a half cycle sine wave of power
frequency as shown in Fig 4.8.

Iav φ = 180°
Amps 120
φ = 120°
100
80 φ = 60° φ
60 φ = 30°
40
20
0 ∫∫
60° 80° 100° 120° 140°
TC (°C)
Fig. 4.8: Average forward current derating characteristics
Maximum Surge current (ISM): It specifies the maximum allowable non repetitive current the
device can withstand. The device is assumed to be operating under rated blocking voltage,
forward current and junction temperation before the surge current occurs. Following the surge
the device should be disconnected from the circuit and allowed to cool down. Surge currents are
assumed to be sine waves of power frequency with a minimum duration of ½ cycles.
Manufacturers provide at least three different surge current ratings for different durations.
For example
I sM = 3000 A for 1 cycle
2
I sM = 2100 A for 3 cycles
I sM = 1800 A for 5 cycles
Alternatively a plot of IsM vs. applicable cycle numbers may also be provided.
Maximum Squared Current integral (∫i2dt): This rating in terms of A2S is a measure of the
energy the device can absorb for a short time (less than one half cycle of power frequency). This
rating is used in the choice of the protective fuse connected in series with the device.
Latching Current (IL): After Turn ON the gate pulse must be maintained until the anode
current reaches this level. Otherwise, upon removal of gate pulse, the device will turn off.
Holding Current (IH): The anode current must be reduced below this value to turn off the
thyristor.
Maximum Forward voltage drop (VF): Usually specified as a function of the instantaneous
forward current at a given junction temperature.
Average power dissipation Pav): Specified as a function of the average forward current (Iav) for
different conduction angles as shown in the figure 4.9. The current wave form is assumed to be
half cycle sine wave (or square wave) for power frequency.
Pav
φ = 180°
90°
60°
30°
iF
ωt
Iav
Fig. 4.9: Average power dissipation vs average forward current in a thyristor.
In the above diagram
1 φ
I av =
2π ∫o F
i dθ ( 4.10 )
1 φ
Pav =
2π ∫o F F
v i dθ ( 4.11)
4.5.3 Gate Specifications

Gate current to trigger (IGT): Minimum value of the gate current below which reliable turn on
of the thyristor can not be guaranteed. Usually specified at a given forward break over voltage.
Gate voltage to trigger (VGT): Minimum value of the gate cathode forward voltage below
which reliable turn on of the thyristor can not be guaranteed. It is specified at the same break
over voltage as IGT.
Non triggering gate voltage (VGNT): Maximum value of the gate-cathode voltage below which
the thyristor can be guaranteed to remain OFF. All spurious noise voltage in the gate drive circuit
must be below this level.
Peak reverse gate voltage (VGRM): Maximum reverse voltage that can appear between the gate
and the cathode terminals without damaging the junction.

Average Gate Power dissipation (PGAR): Average power dissipated in the gate-cathode
junction should not exceed this value for gate current pulses wider than 100 μs.
Peak forward gate current (IGRM): The forward gate current should not exceed this limit even
on instantaneous basis.
Exercise 4.3
i. Peak non-repetitive over voltage may appear across a thyristor due to ________________
or ________________ surges in a supply network.
ii. VRSM rating of a thyristor is greater than the ________________ rating but less than the
________________ rating.
iii. Maximum average current a thristor can carry depends on the ________________ of the
thyristor and the ________________ of the current wave form.
iv. The ISM rating of a thyristor applies to current waveforms of duration ________________
than half cycle of the power frequency where as the ∫i2dt rating applies to current durations
________________ than half cycle of the power frequency.
v. The gate non-trigger voltage specification of a thyristor is useful for avoiding unwanted
turn on of the thyristor due to ________________ voltage signals at the gate.
Answer: (i) switching, lightning; (ii) VRRM, VBRR; (iii) case temperature, conduction
angle; (iv) greater, less; (v) noise
2. A thyristor has a maximum average current rating 1200 Amps for a conduction angle of 180°.
Find the corresponding rating for Φ = 60°. Assume the current waveforms to be half cycle sine
wave.
Answer: The form factor of half cycle sine waves for a conduction angle φ is given by
I
F.F = RMS =
1
2π
φ
∫ Sin θ dθ
o
2
=
(
π φ - 1 Sin 2φ
2 )
Iav 1 φ 1- Cos φ
2π ∫ Sinθ dθ
o
For φ = 180°, F.F = π

2
∴RMS current rating of the thyristor = 1200 × π = 1885 Amps.
2
For φ = 60°, F.F = 2 π ⎛⎜ π - 3 ⎞⎟ = 2.778

⎝ 3 4⎠
Since RMS current rating should not exceeded

1200 × π
Maximum Iav for φ = 60° = = 679.00 Amps.
4 π ⎛⎜ π - 3 ⎞
⎝ 3 4 ⎟⎠
4.6 Switching Characteristics of a Thyristor

During Turn on and Turn off process a thyristor is subjected to different voltages across it and
different currents through it. The time variations of the voltage across a thyristor and the current
through it during Turn on and Turn off constitute the switching characteristics of a thyristor.
4.6.1 Turn on Switching Characteristics

A forward biased thyristor is turned on by applying a positive gate voltage between the gate and
cathode as shown in Fig 4.10.
+ -
ig vAK
iA
ig
t
Vi R
iA 0.9 ION
ION
0.1 ION Firing angle
t α Vi
vAK vAK iA
0.9 VON
VON
0.1 VON Expanded scale
t
tON
td tr tp
Fig. 4.10: Turn on characteristics of a thyristor.
Fig 4.10 shows the waveforms of the gate current (ig), anode current (iA) and anode cathode
voltage (VAK) in an expanded time scale during Turn on. The reference circuit and the associated
waveforms are shown in the inset. The total switching period being much smaller compared to
the cycle time, iA and VAK before and after switching will appear flat.
As shown in Fig 4.10 there is a transition time “tON” from forward off state to forward on state.
This transition time is called the thyristor turn of time and can be divided into three separate
intervals namely, (i) delay time (td) (ii) rise time (tr) and (iii) spread time (tp). These times are
shown in Fig 4.10 for a resistive load.

Delay time (td): After switching on the gate current the thyristor will start to conduct over the
portion of the cathode which is closest to the gate. This conducting area starts spreading at a
finite speed until the entire cathode region becomes conductive. Time taken by this process
constitute the turn on delay time of a thyristor. It is measured from the instant of application of
the gate current to the instant when the anode current rises to 10% of its final value (or VAK falls
to 90% of its initial value). Typical value of “td” is a few micro seconds.
Rise time (tr): For a resistive load, “rise time” is the time taken by the anode current to rise from
10% of its final value to 90% of its final value. At the same time the voltage VAK falls from 90%
of its initial value to 10% of its initial value. However, current rise and voltage fall
characteristics are strongly influenced by the type of the load. For inductive load the voltage falls
faster than the current. While for a capacitive load VAK falls rapidly in the beginning. However,
as the current increases, rate of change of anode voltage substantially decreases.
If the anode current rises too fast it tends to remain confined in a small area. This can give rise to
local “hot spots” and damage the device. Therefore, it is necessary to limit the rate of rise of the
⎛ di ⎞
ON state current ⎜ A ⎟ by using an inductor in series with the device. Usual values of maximum
⎝ dt ⎠
allowable di A is in the range of 20-200 A/μs.
dt
Spread time (tp): It is the time taken by the anode current to rise from 90% of its final value to
100%. During this time conduction spreads over the entire cross section of the cathode of the
thyristor. The spreading interval depends on the area of the cathode and on the gate structure of
the thyristor.
4.6.2 Turn off Switching Characteristics

Once the thyristor is on, and its anode current is above the latching current level the gate loses
control. It can be turned off only by reducing the anode current below holding current. The turn
off time tq of a thyristor is defined as the time between the instant anode current becomes zero
and the instant the thyristor regains forward blocking capability. If forward voltage is applied
across the device during this period the thyristor turns on again.
During turn off time, excess minority carriers from all the four layers of the thyristor must be
removed. Accordingly tq is divided in to two intervals, the reverse recovery time (trr) and the gate
recovery time (tqr). Fig 4.11 shows the variation of anode current and anode cathode voltage with
time during turn off operation on an expanded scale.

vAK
iA
iA
di A
dt
ig
Vi
t
Qrr
Irr
vAK vi
iA
t
t
vi
Expanded
Vrr scale
trr tgr
tq
Fig. 4.11: Turn off characteristics of a thyristor.
The anode current becomes zero at time t1 and starts growing in the negative direction with the
same di A till time t2. This negative current removes excess carriers from junctions J1 & J3. At
dt
time t2 excess carriers densities at these junctions are not sufficient to maintain the reverse
current and the anode current starts decreasing. The value of the anode current at time t2 is called
the reverse recovery current (Irr). The reverse anode current reduces to the level of reverse
saturation current by t3. Total charge removed from the junctions between t1 & t3 is called the
reverse recovery charge (Qrr). Fast decaying reverse current during the interval t2 t3 coupled with
the di limiting inductor may cause a large reverse voltage spike (Vrr) to appear across the
dt
device. This voltage must be limited below the VRRM rating of the device. Up to time t2 the
voltage across the device (VAK) does not change substantially from its on state value. However,
after the reverse recovery time, the thyristor regains reverse blocking capacity and VAK starts
following supply voltage vi. At the end of the reverse recovery period (trr) trapped charges still
exist at the junction J2 which prevents the device from blocking forward voltage just after trr.
These trapped charges are removed only by the process of recombination. The time taken for this
recombination process to complete (between t3 & t4) is called the gate recovery time (tgr). The
time interval tq = trr + tgr is called “device turn off time” of the thyristor.
No forward voltage should appear across the device before the time tq to avoid its inadvertent
turn on. A circuit designer must provide a time interval tc (tc > tq) during which a reverse voltage
is applied across the device. tc is called the “circuit turn off time”.

The reverse recovery charge Qrr is a function of the peak forward current before turn off and its
di
rate of decrease A . Manufacturers usually provide plots of Qrr as a function of di A for
dt dt
different values of peak forward current. They also provide the value of the reverse recovery
current Irr for a given IA and di A . Alternatively Irr can be evaluated from the given Qrr
dt
characteristics following similar relationships as in the case of a diode.
As in the case of a diode the relative magnitudes of the time intervals t1 t2 and t2 t3 depends on
the construction of the thyristor. In normal recovery “converter grade” thyristor they are almost
equal for a specified forward current and reverse recovery current. However, in a fast recovery
“inverter grade” thyristor the interval t2 t3 is negligible compared to the interval t1 t2. This helps
reduce the total turn off time tq of the thyristor (and hence allow them to operate at higher
switching frequency). However, large voltage spike due to this “snappy recovery” will appear
across the device after the device turns off. Typical turn off times of converter and inverter
grade thyristors are in the range of 50-100 μs and 5-50 μs respectively.
As has been mentioned in the introduction thyristor is the device of choice at the very highest
power levels. At these power levels (several hundreds of megawatts) reliability of the thyristor
power converter is of prime importance. Therefore, suitable protection arrangement must be
made against possible overvoltage, overcurrent and unintended turn on for each thyristor. At the
highest power level (HVDC transmission system) thyristor converters operate from network
voltage levels in excess of several hundreds of kilo volts and conduct several tens of kilo amps
of current. They usually employ a large number of thyristors connected in series parallel
combination. For maximum utilization of the device capacity it is important that each device in
this series parallel combination share the blocking voltage and on state current equally. Special
equalizing circuits are used for this purpose.
Exercise 4.4
i. A thyristor is turned on by applying a ________________ gate current pulse when it is

________________ biased.
ii. Total turn on time of a thyristor can be divided into ________________ time
________________ time and ________________ time.
iii. During rise time the rate of rise of anode current should be limited to avoid creating local
________________.
iv. A thyristor can be turned off by bringing its anode current below ________________
current and applying a reverse voltage across the device for duration larger than the
________________ time of the device.
v. Reverse recovery charge of a thyristor depends on the ________________ of the forward
current just before turn off and its ________________.

vi. Inverter grade thyristors have ________________ turn off time compared to a converter
grade thyristor.
Answer: (i) positive, forward; (ii) delay, rise, spread; (iii) hot spots (iv) holding, turn off; (v)
magnitude, rate of decrease (vi) faster
2. With reference to Fig 4.10 find expressions for (i) turn on power loss and (ii) conduction
power loss of the thyristor as a function of the firing angle ∝. Neglect turn on delay time and
spread time and assume linear variation of voltage and current during turn on period. Also
assume constant on state voltage VH across the thyristor.
Answer: (i) For a firing angle ∝ the forward bias voltage across the thyristor just before turn on
is
VON = 2Vi Sin ∝ ; Vi = RMS value of supply voltage.
Current after the thyristor turns on for a resistive load is
VON Vi
I ON = = 2 Sin ∝
R R
Neglecting delay and spread time and assuming linear variation of voltage and current during
turn on
Vak = 2 Vi Sin ∝ ⎛⎜1 - t ⎞ . where V has been neglected.

⎟
⎝ t ON ⎠
H
2 Vi Sin ∝ t
ia =
R t ON
∴ Total switching energy loss
t ON 2Vi 2 t ON
⎛1 - t ⎞ t
E ON = ∫ v ak i a dt =Sin 2 ∝ ∫ ⎜ dt
o R o ⎝ t ON ⎟⎠ t ON
2Vi 2 t ⎛ 2⎞ Vi 2
= Sin 2 ∝ ON ⎜1 - ⎟ = Sin 2 ∝ t ON
R 2 ⎝ 3⎠ 3R
EON occurs once every cycle. If the supply frequency is f then average turn on power loss is
given by.
Vi 2
PON = E ON f = Sin 2 ∝ t ON f
3R
(ii) If the firing angle is ∝ the thyristor conducts for π-∝ angle. Instantaneous current through the
device during this period is
2 Vi Sin ωt
ia = R ∝ <ωt≤ π
R
Where tON & VH have been neglected for simplicity.
∴ total conduction energy loss over one cycle is

πω 1 π 2 Vi 2 Vi VH
E C = ∫ ∝ Vak i a dt =
ω ∫α H
V
R
Sinθ dθ =
ωR
(1 + Cos ∝ )
ω
2 Vi VH
∴ Average conduction power loss = PC = E cf =
2πR
(1 + Cos ∝ )
Fuse
i1
Vi
if
220 V
50 HZ
3. In the ideal single phase fully controlled converter T1 & T2 are fired at a firing angle ∝ after
the positive going zero crossing of Vi while T3 & T4 are fired ∝ angle after the negative going
zero crossing of Vi, If all thyristors have a turn off time of 100 μs, find out maximum allowable
value of ∝.
Answer: As T1 & T2 are fired at an angle ∝ after positive going zero crossing of Vi, T3 & T4 are
subjected to a negative voltage of –Vi. Since this voltage remain negative for a duration (π-∝)
angle (after which –Vi becomes positive) for safe commutation
( π - Max) ≥ ωt off ∴ ∝ Max = 178.2 .
0
4.7 The Triac

The Triac is a member of the thyristor family. But unlike a thyristor which conducts only in one
direction (from anode to cathode) a triac can conduct in both directions. Thus a triac is similar to
two back to back (anti parallel) connected thyristosr but with only three terminals. As in the case
of a thyristor, the conduction of a triac is initiated by injecting a current pulse into the gate
terminal. The gate looses control over conduction once the triac is turned on. The triac turns off
only when the current through the main terminals become zero. Therefore, a triac can be
categorized as a minority carrier, a bidirectional semi-controlled device. They are extensively
used in residential lamp dimmers, heater control and for speed control of small single phase
series and induction motors.
4.7.1 Construction and operating principle

Fig. 4.12 (a) and (b) show the circuit symbol and schematic cross section of a triac respective. As
the Triac can conduct in both the directions the terms “anode” and “cathode” are not used for
Triacs. The three terminals are marked as MT1 (Main Terminal 1), MT2 (Main Terminal 2) and
the gate by G. As shown in Fig 4.12 (b) the gate terminal is near MT1 and is connected to both

N3 and P2 regions by metallic contact. Similarly MT1 is connected to N2 and P2 regions while
MT2 is connected to N4 and P1 regions.
MT1
N2
MT2 N2
P2 G
P2
N3
N3 P2 N1
G P1
N1
MT1
N4 P1
(a)
(b)
MT2
Fig. 4.12: Circuit symbol and schematic construction of a Triac
(a) Circuit symbol (b) Schematic construction.
Since a Triac is a bidirectional device and can have its terminals at various combinations of
positive and negative voltages, there are four possible electrode potential combinations as given
below
1. MT2 positive with respect to MT1, G positive with respect to MT1

2. MT2 positive with respect to MT1, G negative with respect to MT1
3. MT2 negative with respect to MT1, G negative with respect to MT1
4. MT2 negative with respect to MT1, G positive with respect to MT1
The triggering sensitivity is highest with the combinations 1 and 3 and are generally used.
However, for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2
and 3 are used. Trigger mode 4 is usually averded. Fig 4.13 (a) and (b) explain the conduction
mechanism of a triac in trigger modes 1 & 3 respectively.

IG IG
G MT1
MT1
(-)
(+)
IG N2 N3 IG
P2 P2
N1
N1
P1
P1 N4
MT2 MT2
(+) (-)
(a) (b)
Fig. 4.13: Conduction mechanism of a triac in trigger modes 1
and 3
(a) Mode – 1 , (b) Mode – 3 .
In trigger mode-1 the gate current flows mainly through the P2 N2 junction like an ordinary
thyristor. When the gate current has injected sufficient charge into P2 layer the triac starts
conducting through the P1 N1 P2 N2 layers like an ordinary thyristor.
In the trigger mode-3 the gate current Ig forward biases the P2 P3 junction and a large number of
electrons are introduced in the P2 region by N3. Finally the structure P2 N1 P1 N4 turns on
completely.

4.7.2 Steady State Output Characteristics and Ratings of a Triac
I
Ig3 > Ig2 > Ig1 > Ig = 0

-VBO
VBO V
Ig = 0
-Ig3 < Ig2 < Ig1
Fig. 4.14: Steady state V – I characteristics of a Triac
From a functional point of view a triac is similar to two thyristors connected in anti parallel.
Therefore, it is expected that the V-I characteristics of Triac in the 1st and 3rd quadrant of the V-I
plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 4.14, with no
signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak
value is lower than the break over voltage (VBO) of the device. However, the turning on of the
triac can be controlled by applying the gate trigger pulse at the desired instance. Mode-1
triggering is used in the first quadrant where as Mode-3 triggering is used in the third quadrant.
As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current).
However, in a triac the two conducting paths (from MT1 to MT2 or from MT1 to MT1) interact
with each other in the structure of the triac. Therefore, the voltage, current and frequency ratings
of triacs are considerably lower than thyristors. At present triacs with voltage and current ratings
of 1200V and 300A (rms) are available. Triacs also have a larger on state voltage drop compared
to a thyristor. Manufacturers usually specify characteristics curves relating rms device current
and maximum allowable case temperature as shown in Fig 4.15. Curves relating the device
dissipation and RMS on state current are also provided for different conduction angles.

A
Bidirectional ON state current 200
150
100
(RMS)
For all conduction angles

50
0 °C
20° 40° 60° 80° 100° 120°
Maximum allowable case temperature (TC)
Fig. 4.15: RMS ON state current Vs maximum case temperature.
4.7.3 Triac Switching and gate trigger circuit

Unlike a thyristor a triac gets limited time to turn off due to bidirectional conduction. As a result
the triacs are operated only at power frequency. Switching characteristics of a triac is similar to
that of a thyristor. However, turn off of a triac is extremely sensitive to temperature variation and
may not turn off at all if the junction temperature exceeds certain limit. Problem may arise when
a triac is used to control a lagging power factor load. At the current zero instant (when the triac
turns off) a reverse voltage will appear across the triac since the supply voltage is negative at that
instant. The rate of rise of this voltage is restricted by the triac junction capacitance only. The
resulting dv may turn on the triac again. Similar problem occurs when a triac is used to
dt
control the power to a resistive element which has a very low resistance before normal working
condition is reached. If such a load (e.g. incandescent filament lamp) is switch on at full supply
voltage very large junction capacitance charging current will turn ON the device. To prevent
such condition an R-C snubber is generally used across a triac.
The triac should be triggered carefully to ensure safe operation. For phase control application,
the triac is switched on and off in synchronism with the mains supply so that only a part of each
half cycle is applied across the load. To ensure ‘clean turn ON’ the trigger signal must rise
rapidly to provide the necessary charge. A rise time of about 1 μs will be desirable. Such a triac
gate triggering circuit using a “diac” and an R-C timing network is shown in Fig 4.16.

LOAD
R1
R
D1
R2
V1
C1 C
Fig. 4.16: Triac triggering circuit using a diac.
In this circuit as Vi increases voltage across C1 increases due to current flowing through load, R1,
R2 and C1. The voltage drop across diac D1 increases until it reaches its break over point. As D1
conducts a large current pulse is injected into the gate of the triac. By varying R2 the firing can
be controlled from zero to virtually 100%.
Exercise 4.5
i. A Triac is a ________________ minority carrier device

ii. A Triac behaves like two ________________ connected thyristors.
iii. The gate sensitivity of a triac is maximum when the gate is ________________ with
respect to MT1 while MT2 is positive with respect to MT1 or the gate is
________________ with respect to MT1 while MT2 is negative with respect to MT1
iv. A Triac operates either in the ________________ or the ________________ quadrant of
the i-v characteristics.
v. In the ________________ quadrant the triac is fired with ________________ gate
current while in the ________________ quadrant the gate current should be
________________.
vi. The maximum possible voltage and current rating of a Triac is considerably
________________ compared to thyristor due to ________________ of the two current
carrying paths inside the structure of the triac.

vii. To avoid unwanted turn on of a triac due to large dv ________________ are used
dt
across triacs.
viii. For “clean turn ON” of a triac the ________________ of the gate current pulse should be
as ________________ as possible.
Answer: (i) bidirectional; (ii) anti parallel; (iii) positive, negative; (iv) first, third; (v) first,
positive, third, negative (vi) lower, interaction; (vii) R-C shubbers; (viii) rise time,
small.

References
1. Dr. P.C. Sen, “Power Electronics”; Tata McGrow Hill Publishing Company Limited;
New Delhi.
2. Dr. P.S. Bimbhra, “Power Electronics” Khanna Publishers

Lesson Summary
• Thyristor is a four layer, three terminal, minority carrier, semi-controlled device.
• The three terminals of a thyristor are called the anode, the cathode and the gate.
• A thyristor can be turned on by increasing the voltage of the anode with respect to the
cathode beyond a specified voltage called the forward break over voltage.
• A thyristor can also be turned on by injecting a current pulse into the gate terminal when
the anode voltage is positive with respect to the cathode. This is called gate triggering.
• A thyristor can block voltage of both polarity but conducts current only from anode to
cathode.
• After a thyristor turns on the gate looses control. It can be turned off only by bringing the
anode current below holding current.
• After turn on the voltage across the thyristor drops to a very low value (around 1 volt). In
the reverse direction a thyristor blocks voltage up to reverse break down voltage.
• A thyristor has a very low conduction voltage drop but large switching times. For this
reason thyristors are preferred for high power, low frequency line commutated
application.
• A thyristor is turned off by bringing the anode current below holding current and
simultaneously applying a negative voltage (cathode positive with respect to anode) for a
minimum time called “turn off time”.
• A triac is functionally equivalent to two anti parallel connected thyristors. It can block
voltages in both directions and conduct current in both directions.
• A triac has three terminals like a thyristor. It can be turned on in either half cycle by
either a positive on a negative current pulse at the gate terminal.
• Triacs are extensively used at power frequency ac load (eg heater, light, motors) control
applications.


1. Explain the effect of increasing the magnitude of the gate current and junction
temperature on (i) forward and reverse break down voltages, (ii) forward and reverse
leakage currents.
Th
15 V R
• •
N1 N2
iB
2. The thyristor Th is triggered using the pulse transformer shown in figure. The pulse
transformer operates at 10 KHZ with a duty cycle of 40%. The thyristor has maximum
average gate power dissipation limit of 0.5 watts and a maximum allow able gate voltage
limit of 10 volts. Assuming ideal pulse transformer, find out the turns ratio N1/N2 and the
value of R.
Fuse
i1
Vi
if
220 V
50 HZ
3. A thyristor full bridge converter is used to drive a dc motor as shown in the figure. The
thyristors are fired at a firing angle ∝ = 0° when motor runs at rated speed. The motor has
on armature resistance of 0.2 Ω and negligible armature inductance. Find out the peak
surge current rating of the thyristors such that they are not damaged due to sudden loss of
field excitation to the motor. The protective fuse in series with the motor is designed to
disconnect the motor within 1 cycle of fault. Find out the ∫ i 2 dt rating of the
2
thyristors.
4. Why is it necessary to maximize the peripheral contact area of the gate and the cathode
regions? A thyristor used to control the voltage applied to a load resistance from a 220v,

di a
50HZ single phase ac supply has a maximum rating of 50 A / μs. Find out the
dt
di a
value of the limiting inductor to be connected in series with the load resistance.
dt
THM
-
200V C
+ THA
20 A
200V
5. In a voltage commutated dc – dc thyristor chopper the main thyristor THM is

commutated by connecting a pre-charged capacitor directly across it through the auxiliary
thyristor THA as shown in the figure. The main thyristor THM has a turn off time off
50μs and maximum dv rating of 500v/ μs. Find out a suitable value of C for safe
dt
commutation of THM.


1.
i. Forward break down voltage reduces with increasing gate current. It increases with
junction temperature up to certain value of the junction temperature and then falls rapidly
with any further increase in temperature.
Reverse break down voltage is independent of the gate current magnitude but decreases
with increasing junction temperature.
ii. Forward leakage current is independent of the gate current magnitude but increases with
junction temperature.
Reverse leakage current increases with both the junction temperature and the magnitude
of the gate current.
THM
-
200V C
+ THA
20 A
200V
2. Figure shows the equivalent gate drive circuit of the thyristor. For this circuit one can write
E = R i g + Vg OR Vg = E - R i g
The diode D clamps the gate voltage to zero when E goes negative.
Now for ig = O, Vg = E. Since Vg Max = 10 v E = 10 v

N2 N2
But E = 15 ∴ = 15 = 1.5
N1 N1 10
Gate pulse width = 0.4 × 10-4 Sec = 40μs. <100μs.
∴ instantaneous gate power dissipation limit can be used.
Pav
0.2
∴ Vg i g Max
== = 0.5 watts
δ
Max
0.4
For maximum utilization of the gate power dissipation limit the gate load line ie Vg = E – igR =
10 – igR should be tangent to the maximum power dissipation curve Vg ig = 0.5
Let the operating Vg and ig be Vgo & igo
∴ Vgo = 10 - i go R
Vgo i go = 0.5
∴ i go 2 R - 10 i go + 0.5 = 0

Since Vg = 10 – ig R is tangent to Vg ig = 0.5 at Vgo, igo.
Slope of the tangent of Vgig = 0.5 at (Vgo, igo) = -R
dv g - vg v
∴ -R = = = - go
di g ( vgo,igo ) i g ( vgo,igo ) i go
v go v i 0.5
∴R = = go 2go = 2
i go i go i go
0.5
∴ i go 2 × - 10i go + 0.5 = 0 or 10i go = 1 or i go = 0.1
i go 2
0.5
∴ R = 0.5 2 = = 50 Ω
i go .01
Back emf.
Va
t
ia
(normal)
t
ia
(with field loss)
3. Figure shows the armature voltage (firm line) and armature current of the motor under normal
operating condition at rated speed. If there is a sudden loss of field excitation back emf will
become zero and armature current will be limited solely by the armature resistance.
220 2
The peak magnitude of the fault current will be = 1556(Amps) .
.2
It the thyristors have to survive this fault at least for 1 cycle (after which the fuse blows) IsM >
2
1556 Amps.
The fuse blows within 1 cycle of the fault occurring. Therefore the thyristors must withstand
2
the fault for at least 1 cycle.
2
2
Therefore, the i t rating of the thyristor should be

10-2
∫ i dt = ∫ (1556 Sin 100 π t )
2 2
0
(1556 )
2
10-2
=
2 ∫
0
[1 - Cos 200 π t ] dt
= 1 × 10 -2 (1556 ) = 1.21× 10 4 A 2 Sec

2
2
4. At the beginning of the turn on process the thyristor starts conducting through the area
adjacent to the gate. This area spreads at a finite speed. However, if rate of increase of anode
current is lager than the rate of increase of the current conduction are, the current density
increases with time. This may lead to thyristor failure due to excessive local heating. However, if
the contact area between the gate and the cathode is large a thyristor will be able to handle a
di
relatively large a without being damaged.
dt
di a
The maximum will occur when the thyristor is triggered at ∝ = 90°. Then
dt
di a
L = 2 × 220 Sin 90 0
dt
di a
Since = 50 × 10 6 A Sec
dt Max
2 × 220
L = = 6.22 × 10 -6 H = 6.22 μH
min
⎛ di a ⎞
⎜ dt ⎟
⎝ ⎠ Max
VC toff 200 V
vTHM
dv / dt
t
iC
20 Amps.
t

5. As soon as THA is turned on the load current transfer from THM to C. the voltage across
THM is the negative of the capacitance voltage. Figure shows the waveforms of voltage across
the capacitor (vc), voltage across the main thyristor (VTHM) and the capacitor current ic. From
dv i
figure = c
dt c
dv
Now ic = 20 Amps & = 500 v μs
dt Max
ic 20
∴ C = = 6 = 4 × 10
-8
F = 0.04 μF
Min dv 500×10
dt Max
The circuit turn off time is the time taken by the capacitor voltage to reach zero from an initial
value of 200v. This time must be greater than the turn off time of the device.
dv c
Now C = i c = 20
dt
20 × Δt
∴ Δv c = Δv = 200 - 0 = 200
c
Δt = t off
20 × 50 × 10 -6
∴ 200 =
C
20 × 50 × 10 -6
∴C = = 5 μF
200
For safe commutation of THM the higher value of C must the chosen
∴ the required value of C = 5 μF.

Module
1
Power Semiconductor
Devices
Lesson
5
Gate Turn Off Thyristor
(GTO)
Instructional objective
• Differentiate between the constructional features of a GTO and a Thyristor.

• Explain the turn off mechanism of a GTO.
• Differentiate between the steady state output and gate characteristics of a GTO and a
thyristor.
• Draw and explain the switching characteristics of a GTO.
• Draw the block diagram of a GTO gate drive unit and explain the functions of different
blocks.
• Interpret the manufacturer’s data sheet of a GTO.

Introduction
The thyristor has reigned supreme for well over two decades in the power electronics industry
and continues to do so at the very highest level of power. It, however, has always suffered from
the disadvantage of being a semi-controlled device. Although it could be turned on by applying a
gate pulse but to turn it off the main current had to be interrupted. This proved to be particularly
inconvenient in DC to AC and DC to DC conversion circuits, where the main current does not
naturally becomes zero. A bulky and expensive “commutation circuit” had to be used to ensure
proper turning off of the thyristor. The switching speed of the device was also comparatively
slow even with fast inverter grade thyristor. The development of the Gate Turn off thyristor
(GTO) has addressed these disadvantages of a thyristor to a large extent. Although it has made a
rather late entry (1973) into the thyristor family the technology has matured quickly to produce
device comparable in rating (5000V, 4000Amp) with the largest available thyristor.
Consequently it has replaced the forced commutated inverter grade thyristor in all DC to AC and
DC to DC converter circuits.
Like thyristor, the GTO is a current controlled minority carrier (i.e. bipolar) device. GTOs differ
from conventional thyristor in that, they are designed to turn off when a negative current is sent
through the gate, thereby causing a reversal of the gate current. A relatively high gate current is
need to turn off the device with typical turn off gains in the range of 4-5. During conduction, on
the other hand, the device behaves just like a thyristor with very low ON state voltage drop.
Several different varieties of GTOs have been manufactured. Devices with reverse blocking
capability equal to their forward voltage ratings are called “symmetric GTOs”. However, the
most poplar variety of the GTO available in the market today has no appreciable reverse voltage
(20-25v) blocking capacity. These are called “Asymmetric GTOs”. Reverse conducting GTOs
(RC-GTO) constitute the third family of GTOs. Here, a GTO is integrated with an anti-parallel
freewheeling diode on to the same silicon wafer. This lesson will describe the construction,
operating principle and characteristic of “Asymmetric GTOs” only.
5.2 Constructional Features of a GTO

Fig 5.1 shows the circuit symbol and two different schematic cross section of a GTO.

Anode
A Contact
p+ n+ p+ n+ p+ p+
J1 n
Anode
Short. Buffer
n Layer n-
J2
p J3 p
G
K n+ n+ n+ n+
(a) G G
C C
(b) (c)
Fig. 5.1: Circuit symbol and schematic cross section of a GTO
(a) Circuit Symbol, (b) Anode shorted GTO structure,
(c) Buffer layer GTO structure.
Like a thyristor, a GTO is also a four layer three junction p-n-p-n device. In order to obtain high
emitter efficiency at the cathode end, the n+ cathode layer is highly doped. Consequently, the
break down voltage of the function J3 is low (typically 20-40V). The p type gate region has
conflicting doping requirement. To maintain good emitter efficiency the doping level of this
layer should be low, on the other hand, from the point of view of good turn off properties,
resistively of this layer should be as low as possible requiring the doping level of this region to
be high. Therefore, the doping level of this layer is highly graded. Additionally, in order to
optimize current turn off capability, the gate cathode junction must be highly interdigitated. A
3000 Amp GTO may be composed of upto 3000 individual cathode segments which are a
accessed via a common contact. The most popular design features multiple segments arranged in
concentric rings around the device center.
The maximum forward blocking voltage of the device is determined by the doping level and the
thickness of the n type base region next. In order to block several kv of forward voltage the
doping level of this layer is kept relatively low while its thickness is made considerably higher (a
few hundred microns). Byond the maximum allowable forward voltage either the electric field at
the main junction (J2) exceeds a critical value (avalanche break down) or the n base fully
depletes, allowing its electric field to touch the anode emitter (punch through).
The junction between the n base and p+ anode (J1) is called the “anode junction”. For good turn
on properties the efficiency of this anode junction should be as high as possible requiring a
heavily doped p+ anode region. However, turn off capability of such a GTO will be poor with
very low maximum turn off current and high losses. There are two basic approaches to solve this
problem.
In the first method, heavily doped n+ layers are introduced into the p+ anode layer. They make
contact with the same anode metallic contact. Therefore, electrons traveling through the base can
directly reach the anode metal contact without causing hole injection from the p+ anode. This is
the classic “anode shorted GTO structure” as shown in Fig 5.1 (b). Due to presence of these
“anode shorts” the reverse voltage blocking capacity of GTO reduces to the reverse break down
voltage of junction J3 (20-40 volts maximum). In addition a large number of “anode shorts”
reduces the efficiency of the anode junction and degrades the turn on performance of the device.
Therefore, the density of the “anode shorts” are to be chosen by a careful compromise between
the turn on and turn off performance.
In the other method, a moderately doped n type buffer layer is juxtaposed between the n- type
base and the anode. As in the case of a power diode and BJT this relatively high density buffer
layer changes the shape of the electric field pattern in the n- base region from triangular to
trapezoidal and in the process, helps to reduce its width drastically. However, this buffer layer in
a conventional “anode shorted” GTO structure would have increased the efficiency of the anode
shorts. Therefore, in the new structure the anode shorts are altogether dispensed with and a thin
p+ type layer is introduce as the anode. The design of this layer is such that electrons have a high
probability of crossing this layer without stimulating hole injection. This is called the
“Transparent emitter structure” and is shown in Fig 5.1 (c).
Exercise 5.1
i. A GTO is a _______________ controlled _______________ carrier device.

ii. A GTO has _______________ layers and _______________ terminals.
iii. A GTO can be turned on by injecting a _______________ gate current and turned off by
injecting a _______________ gate current.
iv. The anode shorts of a GTO improves the _______________ performance but degrades
the _______________ performance.
v. The reverse voltage blocking capacity of a GTO is small due to the presence of
_______________.
Answer: (i) current, minority; (ii) four, three; (iii) positive, negative; (iv) turn off, turn on; (v)
anode shorts.
5.3 Operating principle of a GTO

GTO being a monolithic p-n-p-n structure just like a thryistor its basic operating principle can be
explained in a manner similar to that of a thyristor. In particular, the p-n-p-n structure of a GTO
can be though of consisting of one p-n-p and one n-p-n transistor connected in the regenerative
configuration as shown in Fig 5.2.

A A A
G
p IA p
αp n p
n iB n
n iC1
iC2
p p n
IG p
p αn G G
iB2 n p
Hole current n Hole current
Electron Electron
IK current C A
current G C C
(a) (b)
Fig 5.2: Current distribution in a GTO

(a) During turn on; (b) During turn off.
From the “two transistor analogy” (Fig 5.2 (a)) of the GTO structure one can write.
i C1 = ∝p I A + ICBO1 ( 5.1)
i B1 = i C 2 = ∝n I k + ICBO2 ( 5.2 )
I k = I A + IG and IA = i B1 + i C1 ( 5.3)
∝n IG + ( iCBO1 + i CBO2 )
Combining I A = ( 5.4 )
1- ( ∝n + ∝p )
With applied forward voltage VAK less than the forward break over voltage both ICBO1 and ICBO2
are small. Further if IG is zero IA is only slightly higher than (ICBO1 + ICBO2). Under this condition
both ∝n and ∝p are small and (∝p + ∝n) <<1. The device is said to be in the forward blocking
mode.
To turn the device on either the anode voltage can be raised until ICBO1 and ICBO2 increases by
avalanche multiplication process or by injecting a gate current. The current gain ∝ of silicon
transistors rises rapidly as the emitter current increases. Therefore, any mechanism which causes
a momentary increase in the emitter current can be used to turn on the device. Normally, this is
done by injecting current into the p base region via the external gate contract. As ∝n + ∝p
approaches unity the anode current tends to infinity. Physically as ∝n + ∝p nears unity the device
starts to regenerate and each transistor drives its companion into saturation. Once in saturation,
all junctions assume a forward bias and total potential drop across the device becomes
approximately equal to that of a single p-n diode. The anode current is restricted only by the
external circuit. Once the device has been turned on in this manner, the external gate current is
no longer required to maintain conduction, since the regeneration process is self-sustaining.
Reversion to the blocking mode occurs only when the anode current is brought below the
“holding current” level.

To turn off a conducting GTO the gate terminal is biased negative with respect to the cathode.
The holes injected from the anode are, therefore, extracted from the p base through the gate
metallization into the gate terminal (Fig 5.2 (b)). The resultant voltage drop in the p base above
the n emitter starts reverse biasing the junction J3 and electron injection stops here. The process
originates at the periphery of the p base and the n emitter segments and the area still injecting
electron shrinks. The anode current is crowded into higher and higher density filaments in most
remote areas from the gate contact. This is the most critical phase in the GTO turn off process
since highly localized high temperature regions can cause device failure unless these current
filaments are quickly extinguished. When the last filament disappears, electron injection stops
completely and depletion layer starts to grow on both J2 and J3. At this point the device once
again starts blocking forward voltage. However, although the cathode current has ceased the
anode to gate current continues to flow (Fig 5.2 (b)) as the n base excess carriers diffuse towards
J1. This “tail current” then decays exponentially as the n base excess carriers reduce by
recombination. Once the tail current has completely disappeared does the device regain its steady
state blocking characteristics. “Anode Shorts” (or transparent emitter) helps reduce the tail
current faster by providing an alternate path to the n base electrons to reach the anode contact
without causing appreciable hole injection from anode.
Exercise 5.2
i. After a GTO turns on the gate current can be _______________.

ii. A conducting GTO reverts back to the blocking mode when the anode current falls below
_______________ current.
iii. To turn off a conducting GTO the gate terminal is biased _______________ with respect
to the _______________.
iv. “Current filaments” produced during the turn off process of a GTO can destroy the device
by creating local _______________.
v. “Anode shorts” help to reduce the _______________ current in a GTO.
Answer: (i) removed; (ii) holding; (iii) negatively, cathode; (iv) hot spot; (v) tail.

5.4 Steady state and dynamic characteristics of a GTO
5.4.1Steady state output and gate characteristics

+ VAK -
IA - IG
IA vg
Min Max
IG +
IL
VBRR
IL
VAK
VBRF
vg
(a) (b)
Fig. 5.3: Steady state characteristics of a GTO

(a) Output characteristics; (b) Gate characteristics.
This characteristic in the first quadrant is very similar to that of a thyristor as shown in Fig. 5.3
(a). However, the latching current of a GTO is considerably higher than a thyristor of similar
rating. The forward leakage current is also considerably higher. In fact, if the gate current is not
sufficient to turn on a GTO it operates as a high voltage low gain transistor with considerable
anode current. It should be noted that a GTO can block rated forward voltage only when the gate
is negatively biased with respect to the cathode during forward blocking state. At least, a low
value resistance must be connected across the gate cathode terminal. Increasing the value of this
resistance reduces the forward blocking voltage of the GTO. Asymmetric GTOs have small (20-
30 V) reverse break down voltage. This may lead the device to operate in “reverse avalanche”
under certain conditions. This condition is not dangerous for the GTO provided the avalanche
time and current are small. The gate voltage during this period must remain negative.
Fig 5.3 (b) shows the gate characteristics of a GTO. The zone between the min and max curves
reflects parameter variation between individual GTOs. These characteristics are valid for DC and
low frequency AC gate currents. They do not give correct voltage when the GTO is turned on
dI
with high dia and G . VG in this case is much higher.
dt dt

5.4.2 Dynamic characteristics of a GTO
iA, VAK di
dt VDM Vd
VD IL
0.9VD ∫∫ VD
0.9IL RL
tON
IL
VT
Itail di/dt
0.1IL
0.1VD ∫∫ limiting
∫∫ t L
td tr
Ig Vg dig/dt ts
tf ttail ig
IGM IG
vg
∫∫ t
VgR
QgQ
IgQ
digQ
dt
Fig. 5.4: Switching characteristics of a GTO.
Fig 5.4 shows the switching characteristics of a GTO and refers to the resistive dc load switching
circuit shown on the right hand side. When the GTO is off the anode current is zero and VAK =
Vd. To turn on the GTO, a positive gate current pulse is injected through the gate terminal. A
substantial gate current ensure that all GTO cathode segments are turned on simultaneously and
within a short time. There is a delay between the application of the gate pulse and the fall of
anode voltage, called the turn on delay time td. After this time the anode voltage starts falling
while the anode current starts rising towards its steady value IL. Within a further time interval tr
they reach 10% of their initial value and 90% of their final value respectively. tr is called the
current rise time (voltage fall time). Both td and maximum permissible on state di A are very
dt
much gate current dependent. High value of I gM and dig at turn on reduces these times and
dt
di
increases maximum permissible on state A . It should be noted that large value of ig (IgM)
dt
and dig are required during td and tr only. After this time period both vg and ig settles down to
dt
their steady value. A minimum ON time period tON (min) is required for homogeneous anode
current conduction in the GTO. This time is also necessary for the GTO to be able to turn off its
rated anode current.

To turn off a GTO the gate terminal is negatively biased with respect to the cathode. With the
application of the negative bias the gate current starts growing in the negative direction.
However, the anode voltage,current or the gate voltage does not change appreciably from their
on state levels for a further time period called the storage time (ts). The storage time increases
di
with the turn off anode current and decrease with gQ . During storage time the load current at
dt
the cathode end is gradually diverted to the gate terminal. At the end of the storage time gate
current reaches its negative maximum value IgQ. At this point both the junctions J2 & J3 of the
GTO starts blocking voltage. Consequently, both the gate cathode and the anode cathode voltage
starts rising towards their final value while the anode current starts decreasing towards zero. At
the end of current fall time “tf” the anode current reaches 10% of its initial value after which both
the anode current and the gate current continues to flow in the form of a current tail for a further
duration of ttail. A GTO is normally used with a R-C turn off snubber. Therefore, VAK does not
start to rise appreciably till tf. At this point VAK starts rising rapidly and exceeds the dc voltage
Vd (VdM) (due to resonance of snubber capacitor with di limiting inductor) before setting
dt
down at its steady value Vd . A GTO should not be retriggered within a minimum off period off
(min) to avoid the risk of failure due to localized turn ON. GTOs have typically low turn off gain
in the range of 4-5.
5.4.3 GTO gate drive circuit

A GTO gate drive has to fulfill the following functions.
• Turn the GTO on by means of a high current pulse (IGM)

• Maintain conduction through provision of a continuous gate current (IG, also known as
the “back-porch current”).
• Turn the GTO off with a high negative gate current pulse.
• Reinforce the blocking state of the device by a negative gate voltage.
A typical gate drive arrangement for a large power GTO is show in Fig 5.5.

H.F.DC to H.F. AC to DC Output
AC INV. H.F TXF Rectifier Stage
A B C D
E
F
Optical
Fiber optic Control
cable Logic
Electrical
Optical -
Electrical
Converter (a)
+ A
R1 R2
C2
+ ON T1
-
G
OFF T2
- R3
-
+ K
(b)
Fig. 5.5: Gate drive circuit of a GTO.
(a) Block diagram,
(b) Circuit diagram of the output stage
In the block diagram of Fig 5.5 (a) it is assumed that there is a potential difference of several kVs
between the master control and individual gate units.
The ON and OFF pulses for a GTO is communicated to individual gate units through fiber optic
cables. These optical signals are converted to electrical signals by a optical electrical converter.
These electrical signals through the control logic then produces the ON and OFF signal for the
out put stage which in turn sends positive and negative gate current to the GTO. Depending on
the requirement the control logic may also supervise GTO conduction by monitoring the gate-
cathode voltage. Any fault is relayed back via fiber optic cable to the master control. Power
supply for the Gate drive units are derived from a common power supply through a high
frequency SMPS (Blocks A, B & C) arrangement.
Fig 5.5 (b) shows the circuit implementation of the output stage. The top switch T1 sends positive
gate pulse to the GTO gate. At the instant of turn on of T1 ,C2 acts almost as a short circuit and
the positive gate current is determined by the parallel combination of R1 and R2. However, at
steady state only R1 determines the gate current IG.
The bottom switch T2 is used for biasing the GTO gate negative with respect to the cathode.
Since, relatively large negative gate current flows during turn off, no external resistance is used
in series with T2. Instead, the ON state resistance of T2 is utilized for this purpose. In practice, a
large number of switches are connected in parallel to obtain the required current rating of T2. A
low value resistance R3 is connected between the gate and the cathode terminals of the GTO to
ensure minimum forward blocking voltage.
Exercise 5.3
i. The _______________ current and forward _______________ current of a GTO are

considerably higher compared to a thyristor.
ii. If the gate current is insufficient a GTO can operate as a low gain _______________.
iii. Reverse blocking voltage of _______________ GTO is small.
iv. To ensure that all GTO cathode segments are turned on simultaneously the magnitude of
the _______________ current should be _______________.
v. High value of gate current and dig/dt enhances the _______________ capability of a
GTO during turn on.
vi. During storage time the load current in a GTO is diverted from the _______________ to
the _______________ terminal.
vii. GTOs have low turn off _______________ gain.
viii. After the current fall time during turn off of a GTO the anode current continuous for
some more time in the form of a _______________.
ix. The gate drive unit of a GTO should provide continuous positive gate _______________
during ON period and continuous negative gate _______________ during OFF period.
x. In the gate drive unit of a GTO a low value resistance is connected between the gate and
the cathode terminals to ensure minimum _______________ voltage.
Answer: (i) latching, leakage; (ii) transistor; (iii) asymmetric; (iv) gate, high; (v) di/dt;
(vi) cathode, gate; (vii) current; (viii) current tail; (ix) current, voltage; (x)
forward blocking.

5.5 GTO Ratings
5.5.1Steady state voltage and current rating

VDRM: It is the maximum repetitive forward voltage the GTO can block in the forward
direction assuming line frequency sinusoidal voltage waveform. It is important to note that GTO
can block rated voltage only if the gate is reverse biased or at least connected to the cathode
through a low value resistance. Manufactures usually provide the forward voltage withstanding
capacity of the GTO as a functions of the gate cathode reverse voltage (and /or resistance) for a
given forward dv .
dt
VRRM: It is the maximum repetitive reverse voltage the GTO is able to withstand. For all
asymmetric GTOs this value is in the range of 20-30 V, since it is determined by the gate
cathode junction break down voltage. Due to the anode shorted structure of the GTO the anode –
base junction (J1) does not block any reverse voltage. Unlike VDRM, VRRM rating may be
exceeded for a short time without destroying the device. This “reverse avalanche” capability of
the GTO is useful in certain situations as explained in Fig 5.6.
VG1
IG1 IG1
VG1
IG1 IL VD
G1 D1 VG1
t
IL
VD ID2
VG2
VD IL
VG2 t
G2 D2 ID2 Vfr > VRRM
(a) (b)
Fig. 5.6: Reverse avalanche capability of a GTO

(a) Voltage source inverter phase leg;
(b) Voltage, current waveforms.
In the voltage source inverter phase leg shown in Fig 5.6 (a), as the GTO G1 is turned off the
current through it (IG1) starts reducing. The difference current (IL - IG1) is transferred to the
snubber capacitance of G1 and the voltage across G1 (VG1) starts increasing. When if becomes
equal to the dc link voltage VD , D2 is forward biased. However, due to the forward recovery
voltage of D2 (Vfr) the reverse voltage across G2 may exceed VRRM rating of G2 and drive it into
reverse avalanche. This condition is not dangerous for G2 provided the avalanche time and
current are small (typically within 10 μs and 1000 A respectively). However, the gate voltage
must remain negative during this time.

VDC: This is the maximum continuous DC voltage the device can withstand. Exceeding this
voltage does not immediately lead to device failure, but the probability of a cosmic radiation
failure increases progressively with the applied dc voltage.
IFAVM and IFRMS: These are maximum average and RMS on state current respectively. They are
specified at a given case temperature assuming half wave sinusoidal on state current at power
frequency.
IFSM: This is the maximum allowed peak value of a power frequency half sinusoidal non-
repetitive surge current. The pulse is assumed to be applied at an instant when the GTO is
operating at its maximum junction temperature. The voltage across the device just after the surge
should be zero.
∫ i dt : This is the limiting value of the surge current integral assuming half cycle sine wave
2
surge current. The junction temperature is assumed to be at the maximum value before the surge
and the voltage across the device following the surge is assumed to be zero. The i2t rating of a
semiconductor fuse must be less than this value in order to protect the GTO. Plots of both IFSM
and ∫ i 2 dt as functions of surge pulse width are usually provided by the manufacturer.
VF : This is the plot of the instantaneous forward voltage drop vs instantaneous forward
current at different junction temperatures.
Pav : For some frequently encountered current waveforms (e.g. sine wave, square wave) the
plot of the average on state power dissipation as a function of the average on state current is
provided by the manufacturers at a given junction temperature.
IH: This is the holding current of the GTO. This current, in case of a GTO1 , is considerably
higher compared to a similarly rated thyristor. Serious problem may arise due to anode current
variation because the GTO may “un-latch” at an in appropriate moment. This problem can be
avoided by feeding a continuous current into the gate (called the “back porch” current) during
ON period of the device. This DC gate current should be about 20% higher than the gate trigger
current (IGT) at the lowest expected junction temperature.
di
crit : This is the maximum permissible value of the rate of change of forward current during
dt
turn on. This value is very much dependent on the peak gate current magnitude and the rate of
increase of the gate current. A substantial gate current ensures that all GTO cathode segments are
turned ON simultaneously and within a short time so that no local hot spot is created.
di
The g and IgM values specified in the operating conditions should, therefore, be considered as
dt
minimum values.
5.5.2 Gate specification

Ig vs Vg: It is a plot of instantaneous gate current as a function of the gate voltage. This
characteristic is valid for DC and low frequency AC gate currents. They do not define the gate

di g
voltage when the GTO is turned on from high anode voltage with high di/dt and . Vg in this
dt
case is much higher. Generally the gate cathode impedance of a GTO is much lower than that of
a conventional thyristor.
Vgt, Igt: Igt is the gate trigger current and Vgt , the instantaneous gate cathode voltage when Igt is
flowing into the gate. Igt has a strong junction temperature dependence and increases very rapidly
with reduced junction temperature. Igt merely specifies the minimum back porch current
necessary to turn on the GTO at a low di and maintain it in conduction.
dt
Vgrm: It is the maximum repetitive reverse gate voltage, exceeding which drives the gate
cathode junction into avalanche breakdown.
Igrm: It is the peak repetitive reverse gate current at Vgrm and Tj (max).
Igqm: It is the maximum negative turn off gate current. The gate unit should be designed to
di
deliver this current under any condition. It is a function of turn off anode current, g during
dt
turn off and the junction temperature.
5.5.3 Specifications related to the switching performance

td, tr, :These are turn on delay time and anode voltage fall time respectively. Both of them can
di
be reduced with higher g and IgM for a given turn on anode voltage, current and di .
dt dt
ton (min) : This is the minimum time the GTO requires to establish homogeneous anode current.
This time is also necessary for the GTO to be able to turn off its rated anode current.
EON : It is the energy dissipated during each turn on operation. Manufacturers specify them as
functions of turn on anode current for different turn on di/dt and anode voltage EON reduces with
increased IgM .
IFgqm : It is the maximum anode current that can be repetitively turned off by a negative gate
current. It can be increased by increasing the value of the turn off snubber capacitance which
limits the dv/dt at turn off. A large negative dig/dt during turn off also helps to increase IFgqm.
ts : The storage time ts is defined as the time between the start of negative gate current and
the decrease in anode current. High value of the turn off anode current and junction temperature
increases it while a large negative dig/dt during turn off decreases it.
tf : This is the anode current fall time. It can not be influenced much by gate control.
toff(min) : This is the minimum off time before the GTO may be triggered again by a positive
gate current. If the device is re-triggered during this time, localized turn on may destroy it.

Eoff : This is the energy dissipated during each turn off operation of the GTO. Eoff increases
with increase in the turn off anode current and junction temperature while it reduces with turn off
snubber capacitance.
Exercise 5.4
i. A GTO can block rated forward voltage only when the gate is _______________ biased
with respect to the _______________.
ii. A GTO can operate in the reverse _______________ region for a short time.
iii. The holding current of a GTO is much _______________ compared to a thyristor.
iv. After a current surge the voltage across a GTO should be reduced to _______________.
v. The gate cathode impedance of a GTO is much _______________ compared to a
thyristor.
vi. The turn on di/dt capability of a GTO can be increased by in creasing the
_______________ magnitude of the gate current and _______________ during turn on.
vii. The turn on delay time and current rise time of a GTO can be reduced by increasing the
gate current _______________ and _______________ during turn ON.
viii. The maximum anode current that can be turned off repetitively can be increased by
increasing the turn off snubber _______________ and negative _______________.
Answer: (i) negatively, cathode; (ii) avalanche; (iii) larger; (iv) zero; (v) smaller; (vi)
peak, dig/dt; (vii) magnitude, dig/dt; (viii) capacitance, dig/dt.
Reference
1) “GTO and GCT product guide”, ABB semiconductors AG, 1997.
2) “GTO Thyristors” , Makoto Azuma and Mamora Kurata, Proceedings of the IEEE,
Vol.76, No. 4, April 1988, pp 419-427.
3) “Power Electronics”, P. S. Bimbhra, Khanna Publlishers, 1993.

Lesson Summary
• GTO is a four layer, three terminal current controlled minority carrier device.
• A GTO can be turned on by applying a positive gate current pulse when it is forward
biased and turned off by applying a negative gate current.
• A GTO has a “shorted anode” and highly inter-digitized gate cathode structure to
improve the gate turn off performance.
• Due to the presence of “anode shorts” a GTO can block only a small reverse voltage.
These are called “asymmetric GTOs”.
• The forward i-v characteristics of a GTO is similar to that of a thyristor. However, they
have relatively larger holding current and gate trigger current.
• The turn on di/dt capability of a GTO is significantly enhanced by using higher peak gate
current and large rate of rise of the gate current.
• Due to relatively larger holding current of a GTO a continuous low value gate current
(called the back porch current) should be injected through out the on period of the GTO.
• GTOs have relatively low turn off current gain.
• The GTO gate drive unit should be capable of injecting large positive and negative gate
currents with large rate of rise for satisfactory switching of the device.
• A GTO can block rated forward voltage only when the gate cathode junction is reverse
biased.
• A GTO can operate safely in the “reverse avalanche” region for a short time provided the
gate cathode junction is reverse biased.
• The switching delay times and energy loss of a GTO can be reduced by increasing the
gate current magnitude and its rate of rise.
• The maximum turn off anode current of a GTO can be increased by increasing the turn
off snubber capacitance.


1. What are the constructional features of a GTO that bestows it with a gate turn off
capability? How do they affect the turn on performance of the GTO?
2. What are the main differences in the steady state output characteristics of a GTO and a
thyristor? What effect do they have on the gate drive requirement of a GTO?
3. What are the desirable characteristics of the gate drive circuit of a GTO? How do they
influence the switching performance of a GTO?
4. What is the significance of the specifications IFAVM and IFRMS in relation to a GTO? Is the
specification IFgqm. Same as IFAVM / IFRMS? If not, then which current should one use in a
particular application?
5. Which paramers of the gate current waveform reduces the turn on energy loss (EON) of a
GTO? How does one reduce the turn off energy lass of a GTO?

Answers to practice problems
1. Although a GTO is a four layer (p-n-p-n) three junction devices like a thyristor it has two
important constructional differences with a thyristor which bestows it with the gate turn off
capability.
• The Gate-cathode junction of a GTO is far more inter digitized compared to a thyristor.
Thousands of cathode segments, normally arranged in concentric rings around the device
center, from the cathode structure of a GTO. This highly inter digitized structure of the
GTO cathode ensures that any “current filament” formed during the turn off process of a
GTO is quickly extinguished.
• “Anode shorts” are introduced at the p+ type anode and n type base junction of a GTO.
“Anode shorts” consists of heavily doped n+ type region introduced inside the p+ type
anodes. They make direct contact with the anode metal plate and provide an alternate path
for the electrons traveling through the n base to reach the anode metal contact without
causing bole injection from the p+ anode. This helps to reduce the “tail current” during turn
off of a GTO.
• Highly inter digitized gate-cathode structure of a GTO helps to enhance the turn on di/dt
capability of the device due to faster and more even spreading of the injected gate current
to adjacent cathodes.
• On the other hand, presence of anode shorts has adverse effect on the turn on performance
of a GTO. Referring to Fig 5.2 (a), introduction of anode shorts effectively reduces the
current gain ∝p of the top p-n-p transistor. This has the effect of increasing the latching
and holding current of a GTO compared to a thyristor. The minimum gate current required
to trigger a GTO also increases.
2. In the first quadrant of the output i-v plane the steady state output characteristics of a GTO
appears to be similar to that of a thyristor. There are some important differences however.
• Both holding and latching current of a GTO are considerably higher compared to a
similarly rated thyrisstor.
• The minimum gate current require to trigger a GTO at a given forward blocking voltage is
higher compared to a thyristor.
• The forward leakage current of a GTO is considerably higher compared to a thyristor of
equal rating. In fact, if the gate current is not sufficient to turn on a GTO it may operate as
a high voltage low gain transistor with considerable anode current.
• A GTO can block rated forward voltage only when the gate voltage is negative with respect
to the cathode or at least the gate is connected to the cathode through a low value
resistance.
• In the reverse blocking region (i.e third quadrant of the output i-v plane) an asymmetric
GTO has much lower reverse break down voltage (20-30V) compared to a thyristors.
Exceeding this reverse voltage forces the GTO to operate in the “reverse avalanche” mode.

This mode of operation does not destroy the device provided the gate is negatively biased
and the time of such operation is small.
• Since the holding current of a GTO is considerably higher than that of a thyristor anode
current variations can generate serious problem because the GTO might “unlatch” at an
inappropriate moment. To avoid this problem the gate drive unit of a GTO must feed the
gate terminal with a continuous “back porch” current during the entire on period of the
GTO. This back porch current must be larger than the gate trigger current.
• To avoid localized transistor operation during turn on from a high anode voltage with large
di/dt, the gate drive unit must inject a peak gate current considerably larger (3-10 times)
than the gate trigger current with fast rate of rise.
• To ensure that the GTO blocks rated forward voltage and operates safely in the “reverse
avalanche” mode the gate voltage must be maintained negative with respect to the cathode
for the entire off duration of the GTO.
3. The gate drive unit of a GTO should.
• Turn the GTO on with a large (3-10 times the minimum gate trigger current) positive gate
current pulse with high rate of rise.
• Maintain conduction of the GTO through out the ON period by injecting a positive “back
porch” gate current which is larger than the minimum gate trigger current.
• Turn the GTO off with a large negative gate current with high rate of fall. The peak
magnitude of the negative gate current should be at least 20-25% of the maximum anode
current during turn off.
• Reinforce the blocking state of the device by applying a negative voltage to the gate with
respect to cathode for the entire off duration of the GTO.
Both the turn on delay time (td) and the voltage fall time (tr) of a GTO can be reduced by
increasing the peak positive gate current and its rate of rise during turn on. Energy loss per
turn on (EON) also reduces.
A large negative gate current during turn off with a stiff slope considerably reduces the
storage time (ts) and enhances maximum anode current turn off (IFgqm) capability.
4. The specifications of IFAVM and IFRMS are given with reference to power frequency half
cycle sine wave anode current. If the GTO is employed in a line commutated phase
controlled converter application then these specifications give the maximum allowable
average and RMS current through the device respectively. However, in most GTO
applications the current waveform is for removed from a sinusoidal shape and the
switching losses are a considerable part of the total power losses. IFAVM / IFRMS ratings, in
such cases, does not have any practical significance except for comparison of current
carrying capacity of different devices.
On the other hand, IFgqm rating of a GTO gives the maximum anode current that can be
repetitively turned off by gate control. This rating is usually lower than IFAVM / IFRMS. In

high frequency switching application this specification gives the absolute peak value of any
desired current waveform the GTO can conduct.
5. Eon is reduced by increasing the peak magnitude of the positive gate current during turn on.
Eoff is reduced by increasing the turn off snubber capacitance across the GTO.

Module
1
Power Semiconductor
Devices
Lesson
6
Metal Oxide
Semiconductor Field
Effect Transistor
(MOSFET)
Constructional Features, operating principle and characteristics of Power Metal Oxide
Semiconductor Field Effect Transistor (MOSFET).
Instructional Objectives
• Differentiate between the conduction mechanism of a MOSFET and a BJT.

• Explain the salient constructional features of a MOSFET.
• Draw the output i-v characteristics of a MOSFET and explain it in terms of the operating
principle of the device.
• Explain the difference between the safe operating area of a MOSFET and a BJT.
• Draw the switching characteristics of a MOSFET and explain it.
• Design the gate drive circuit of a MOSFET.
• Interpret the manufacturer’s data sheet rating of a MOSFET.

6.1 Introduction
Historically, bipolar semiconductor devices (i.e, diode, transistor, thyristor, thyristor, GTO etc)
have been the front runners in the quest for an ideal power electronic switch. Ever since the
invention of the transistor, the development of solid-state switches with increased power
handling capability has been of interest for expending the application of these devices. The BJT
and the GTO thyristor have been developed over the past 30 years to serve the need of the power
electronic industry. Their primary advantage over the thyristors have been the superior switching
speed and the ability to interrupt the current without reversal of the device voltage. All bipolar
devices, however, suffer from a common set of disadvantages, namely, (i) limited switching
speed due to considerable redistribution of minority charge carriers associated with every
switching operation; (ii) relatively large control power requirement which complicates the
control circuit design. Besides, bipolar devices can not be paralleled easily.
The reliance of the power electronics industry upon bipolar devices was challenged by the
introduction of a new MOS gate controlled power device technology in the 1980s. The power
MOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. The
new device promised extremely low input power levels and no inherent limitation to the
switching speed. Thus, it opened up the possibility of increasing the operating frequency in
power electronic systems resulting in reduction in size and weight. The initial claims of infinite
current gain for the power MOSFET were, however, diluted by the need to design the gate drive
circuit to account for the pulse currents required to charge and discharge the high input
capacitance of these devices. At high frequency of operation the required gate drive power
becomes substantial. MOSFETs also have comparatively higher on state resistance per unit area
of the device cross section which increases with the blocking voltage rating of the device.
Consequently, the use of MOSFET has been restricted to low voltage (less than about 500 volts)
applications where the ON state resistance reaches acceptable values. Inherently fast switching
speed of these devices can be effectively utilized to increase the switching frequency beyond
several hundred kHz.
From the point of view of the operating principle a MOSFET is a voltage controlled
majority carrier device. As the name suggests, movement of majority carriers in a MOSFET is
controlled by the voltage applied on the control electrode (called gate) which is insulated by a
thin metal oxide layer from the bulk semiconductor body. The electric field produced by the gate
voltage modulate the conductivity of the semiconductor material in the region between the main
current carrying terminals called the Drain (D) and the Source (S). Power MOSFETs, just like
their integrated circuit counterpart, can be of two types (i) depletion type and (ii) enhancement
type. Both of these can be either n- channel type or p-channel type depending on the nature of
the bulk semiconductor. Fig 6.1 (a) shows the circuit symbol of these four types of MOSFETs
along with their drain current vs gate-source voltage characteristics (transfer characteristics).

D D
D D
ID ID
ID ID
G G
G G
S S S
S
ID ID ID ID
VGS VGS VGS VGS

n-channel depletion type p-channel depletion type n-channel enhancement p-channel enhancement
MOSFET MOSFET type MOSFET type MOSFET
(a)
(b)
Fig 6.1: Different types of power MOSFET.

(a) Circuit symbols and transfer characteristics
(b) Photograph of n-channel enhancement type MOSFET.
From Fig 6.1 (a) it can be concluded that depletion type MOSFETs are normally ON type
switches i.e, with the gate terminal open a nonzero drain current can flow in these devices. This
is not convenient in many power electronic applications. Therefore, the enhancement type
MOSFETs (particularly of the n-channel variety) is more popular for power electronics
applications. This is the type of MOSFET which will be discussed in this lesson. Fig 6.1 (b)
shows the photograph of some commercially available n-channel enhancement type Power
MOSFETs.
6.2 Constructional Features of a Power MOSFET

As mentioned in the introduction section, Power MOSFET is a device that evolved from
MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs were
by redesigning lateral MOSFET to increase their voltage blocking capacity. The resulting
technology was called lateral double deffused MOS (DMOS). However it was soon realized that
much larger breakdown voltage and current ratings could be achieved by resorting to a vertically
oriented structure. Since then, vertical DMOS (VDMOS) structure has been adapted by virtually
all manufacturers of Power MOSFET. A power MOSFET using VDMOS technology has
vertically oriented three layer structure of alternating p type and n type semiconductors as shown
in Fig 6.2 (a) which is the schematic representation of a single MOSFET cell structure. A large
number of such cells are connected in parallel (as shown in Fig 6.2 (b)) to form a complete
device.
Source
Gate conductor
FIELD OXIDE Gate oxide
n+ n+ n+ n+
p(body) p(body)
n- (drain drift)
n+
Drain
(a)
Contact to source
Source
Conductor
Field oxide
Gate
Oxide
Gate
Conductor
Single
n- MOSFET
Cell
n+ p n+ n+ p n+ n+
n-
n+
(b)
Fig. 6.2: Schematic construction of a power MOSFET
(a) Construction of a single cell.
(b) Arrangement of cells in a device.
The two n+ end layers labeled “Source” and “Drain” are heavily doped to approximately the
same level. The p type middle layer is termed the body (or substrate) and has moderate doping
level (2 to 3 orders of magnitude lower than n+ regions on both sides). The n- drain drift region
has the lowest doping density. Thickness of this region determines the breakdown voltage of the
device. The gate terminal is placed over the n- and p type regions of the cell structure and is
insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate
oxide). The source and the drain region of all cells on a wafer are connected to the same metallic
contacts to form the Source and the Drain terminals of the complete device. Similarly all gate
terminals are also connected together. The source is constructed of many (thousands) small
polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source
regions, to same extent, influences the ON state resistance of the MOSFET.
D D
S G MOSFET
Parasitic BJT
+ +
n p n
Body spreading Parasitic BJT
resistance
n- G G
n+ Body diode
S S
D
Fig. 6.3: Parasitic BJT in a MOSFET cell.
One interesting feature of the MOSFET cell is that the alternating n+ n- p n+ structure
embeds a parasitic BJT (with its base and emitter shorted by the source metallization) into
each MOSFET cell as shown in Fig 6.3. The nonzero resistance between the base and the
emitter of the parasitic npn BJT arises due to the body spreading resistance of the p type
substrate. In the design of the MOSFET cells special care is taken so that this resistance is
minimized and switching operation of the parasitic BJT is suppressed. With an effective
short circuit between the body and the source the BJT always remain in cut off and its
collector-base junction is represented as an anti parallel diode (called the body diode) in
the circuit symbol of a Power MOSFET.
6.3 Operating principle of a MOSFET

At first glance it would appear that there is no path for any current to flow between the
source and the drain terminals since at least one of the p n junctions (source – body and
body-Drain) will be reverse biased for either polarity of the applied voltage between the
source and the drain. There is no possibility of current injection from the gate terminal
either since the gate oxide is a very good insulator. However, application of a positive
voltage at the gate terminal with respect to the source will covert the silicon surface
beneath the gate oxide into an n type layer or “channel”, thus connecting the Source to the
Drain as explained next.

The gate region of a MOSFET which is composed of the gate metallization, the gate
(silicon) oxide layer and the p-body silicon forms a high quality capacitor. When a small
voltage is application to this capacitor structure with gate terminal positive with respect to
the source (note that body and source are shorted) a depletion region forms at the interface
between the SiO2 and the silicon as shown in Fig 6.4 (a).
VGS1
Gate Electrode
Source
+++ ++++++++
Electrode
Si02
n+
Ionized Depletion layer

p acceptor boundary.
n-
(a)
VGS2
VGS2 > VGS1
Gate Electrode
Source
+++ ++++++++
Electrode
Si02
n+
Depletion layer
p Ionized boundary.
acceptor Free
electron
n-
(b)

VGS3
VGS3 > VGS2 > VGS1 Gate Electrode
Source
+++ ++++++++
Electrode
Si02
Inversion layer
n+ with free electrons
Depletion layer
boundary.
p
Ionized
n- acceptor
(c)
Fig. 6.4: Gate control of MOSFET conduction.
(a) Depletion layer formation;
(b) Free electron accumulation;
(c) Formation of inversion layer.
The positive charge induced on the gate metallization repels the majority hole carriers from
the interface region between the gate oxide and the p type body. This exposes the
negatively charged acceptors and a depletion region is created.
Further increase in VGS causes the depletion layer to grow in thickness. At the same time
the electric field at the oxide-silicon interface gets larger and begins to attract free electrons
as shown in Fig 6.4 (b). The immediate source of electron is electron-hole generation by
thermal ionization. The holes are repelled into the semiconductor bulk ahead of the
depletion region. The extra holes are neutralized by electrons from the source.
As VGS increases further the density of free electrons at the interface becomes equal to the
free hole density in the bulk of the body region beyond the depletion layer. The layer of
free electrons at the interface is called the inversion layer and is shown in Fig 6.4 (c). The
inversion layer has all the properties of an n type semiconductor and is a conductive path or
“channel” between the drain and the source which permits flow of current between the
drain and the source. Since current conduction in this device takes place through an n- type
“channel” created by the electric field due to gate source voltage it is called “Enhancement
type n-channel MOSFET”.
The value of VGS at which the inversion layer is considered to have formed is called the
“Gate – Source threshold voltage VGS (th)”. As VGS is increased beyond VGS(th) the
inversion layer gets some what thicker and more conductive, since the density of free
electrons increases further with increase in VGS. The inversion layer screens the depletion
layer adjacent to it from increasing VGS. The depletion layer thickness now remains
constant.

Exercise 6.1 (after section 6.3)
1. Fill in the blank(s) with the appropriate word(s)
i. A MOSFET is a ________________ controlled ________________ carrier device.

ii. Enhancement type MOSFETs are normally ________________devices while depletion
type MOSFETs are normally ________________ devices.
iii. The Gate terminal of a MOSFET is isolated from the semiconductor by a thin layer of
________________.
iv. The MOSFET cell embeds a parasitic ________________ in its structure.
v. The gate-source voltage at which the ________________ layer in a MOSFET is formed
is called the ________________ voltage.
vi. The thickness of the ________________ layer remains constant as gate source voltage
is increased byond the ________________ voltage.
Answer: (i) voltage, majority; (ii) off, on; (iii) SiO2, (iv) BJT, (v) inversion, threshold; (vi)
depletion, threshold.
2. What are the main constructional differences between a MOSFET and a BJT? What
effect do they have on the current conduction mechanism of a MOSFET?
Answer: A MOSFET like a BJT has alternating layers of p and n type semiconductors.
However, unlike BJT the p type body region of a MOSFET does not have an external
electrical connection. The gate terminal is insulated for the semiconductor by a thin layer of
SiO2. The body itself is shorted with n+ type source by the source metallization. Thus
minority carrier injection across the source-body interface is prevented. Conduction in a
MOSFET occurs due to formation of a high density n type channel in the p type body
region due to the electric field produced by the gate-source voltage. This n type channel
connects n+ type source and drain regions. Current conduction takes place between the
drain and the source through this channel due to flow of electrons only (majority carriers).
Where as in a BJT, current conduction occurs due to minority carrier injection across the
Base-Emitter junction. Thus a MOSFET is a voltage controlled majority carrier device
while a BJT is a minority carrier bipolar device.
6.4 Steady state output i-v characteristics of a MOSFET

The MOSFET, like the BJT is a three terminal device where the voltage on the gate
terminal controls the flow of current between the output terminals, Source and Drain. The
source terminal is common between the input and the output of a MOSFET. The output
characteristics of a MOSFET is then a plot of drain current (iD) as a function of the Drain –
Source voltage (vDS) with gate source voltage (vGS) as a parameter. Fig 6.5 (a) shows such a
characteristics.

VGS – VGS (th) = VDS
Electron Drift
iD Velocity
ohmic Increasing VGS
VGS6
rDS(ON) Active
VGS5 [VGS–VGS(th)]<VDS
VGS4
VGS3
VGS2
vgs1
Cut off (VGS < VGS (th))
VDSS vDS Electric
(a) (c) Field
G
S iD
n+
Source Channel Drift
region p resistance region
resistance iD resistance
n-
Drain
n+ resistance
VGS(th) VGS
(b)
D (d)
Fig. 6.5: Output i-v characteristics of a Power MOSFET

(a) i-v characteristics;
(b) Components of ON-state resistance;
(c) Electron drift velocity vs Electric field;
(d) Transfer
With gate-source voltage (VGS) below the threshold voltage (vGS (th)) the MOSFET
operates in the cut-off mode. No drain current flows in this mode and the applied drain–
source voltage (vDS) is supported by the body-collector p-n junction. Therefore, the
maximum applied voltage should be below the avalanche break down voltage of this
junction (VDSS) to avoid destruction of the device.
When VGS is increased beyond vGS(th) drain current starts flowing. For small values of vDS
(vDS < (vGS – vGS(th)) iD is almost proportional to vDS. Consequently this mode of operation
is called “ohmic mode” of operation. In power electronic applications a MOSFET is
operated either in the cut off or in the ohmic mode. The slope of the vDS – iD characteristics
in this mode is called the ON state resistance of the MOSFET (rDS (ON)). Several physical
resistances as shown in Fig 6.5 (b) contribute to rDS (ON). Note that rDS (ON) reduces with
increase in vGS. This is mainly due to reduction of the channel resistance at higher value of

vGS. Hence, it is desirable in power electronic applications, to use as large a gate-source
voltage as possible subject to the dielectric break down limit of the gate-oxide layer.
At still higher value of vDS (vDS > (vGS – vGS (th)) the iD – vDS characteristics deviates from
the linear relationship of the ohmic region and for a given vGS, iD tends to saturate with
increase in vDS. The exact mechanism behind this is rather complex. It will suffice to state
that, at higher drain current the voltage drop across the channel resistance tends to decrease
the channel width at the drain drift layer end. In addition, at large value of the electric field,
produced by the large Drain – Source voltage, the drift velocity of free electrons in the
channel tends to saturate as shown in Fig 6.5 (c). As a result the drain current becomes
independent of VDS and determined solely by the gate – source voltage vGS. This is the
active mode of operation of a MOSFET. Simple, first order theory predicts that in the
active region the drain current is given approximately by
i D = K(vGS - vGS (th))2 (6.1)
Where K is a constant determined by the device geometry.
At the boundary between the ohmic and the active region

vDS = vGS - vGS (th) (6.2)
Therefore, i D = KvDS2 (6.3)
Equation (6.3) is shown by a dotted line in Fig 6.5 (a). The relationship of Equation (6.1)
applies reasonably well to logic level MOSFETs. However, for power MOSFETs the
transfer characteristics (iD vs vGS) is more linear as shown in Fig 6.5 (d).
At this point the similarity of the output characteristics of a MOSFET with that of a BJT
should be apparent. Both of them have three distinct modes of operation, namely, (i)cut off,
(ii) active and (iii) ohmic (saturation for BJT) modes. However, there are some important
differences as well.
• Unlike BJT a power MOSFET does not undergo second break down.
• The primary break down voltage of a MOSFET remains same in the cut off and in
the active modes. This should be contrasted with three different break down
voltages (VSUS, VCEO & VCBO) of a BJT.
• The ON state resistance of a MOSFET in the ohmic region has positive temperature
coefficient which allows paralleling of MOSFET without any special arrangement
for current sharing. On the other hand, vCE (sat) of a BJT has negative temperature
coefficient making parallel connection of BJTs more complicated.
As in the case of a BJT the operating limits of a MOSFET are compactly represented in a
Safe Operating Area (SOA) diagram as shown in Fig 6.6. As in the case of the FBSOA of a

BJT the SOA of a MOSFET is plotted on a log-log graph. On the top, the SOA is restricted
by the absolute maximum permissible value of the drain current (IDM) which should not be
exceeded even under pulsed operating condition. To the left, operating restriction arise due
to the non zero value of rDS(ON) corresponding to vGS = vGS(Max). To the right, the first
operating restriction is due to the limit on the maximum permissible junction temperature
rise which depends on the power dissipation inside the MOSFET. This limit is different for
DC (continuous) and pulsed operation of different pulse widths. As in the case of a BJT the
pulsed safe operating areas are useful for shaping the switching trajectory of a MOSFET. A
MOSFET does not undergo “second break down” and no corresponding operating limit
appears on the SOA. The final operation limit to the extreme right of the SOA arises due to
the maximum permissible drain source voltage (VDSS) which is decided by the avalanche
break down voltage of the drain -body p-n junction. This is an instantaneous limit. There is
no distinction between the forward biased and the reverse biased SOAs for the MOSFET.
They are identical.
Log (iD)
IDM
10-5sec
rDS(ON) limit 10-4sec

(VGS = VGS(max))
Max. 10-3sec
Power
Dissipation DC
Limit (Timax) Primary voltage breakdown
limit
VDSS Log (vDS)
Fig. 6.6: Safe operating area of a MOSFET.
Due to the presence of the anti parallel “body diode”, a MOSFET can not block any reverse
voltage. The body diode, however, can carry an RMS current equal to IDM. It also has a
substantial surge current carrying capacity. When reverse biased it can block a voltage
equal to VDSS.
For safe operation of a MOSFET, the maximum limit on the gate source voltage (VGS
(Max)) must be observed. Exceeding this voltage limit will cause dielectric break down of
the thin gate oxide layer and permanent failure of the device. It should be noted that even
static charge inadvertently put on the gate oxide by careless handling may destroy it. The
device user should ground himself before handling any MOSFET to avoid any static charge
related problem.
Exercise 6.2
i. A MOSFET operates in the ________________ mode when vGS < vGS(th)

ii. In the ohmic region of operation of a MOSFET vGS – vGS (th) is greater than
________________.
iii. rDS (ON) of a MOSFET ________________ with increasing vGS.
iv. In the active region of operation the drain current iD is a function of ________________
alone and is independent of ________________.
v. The primary break down voltage of MOSFET is ________________ of the drain
current.
vi. Unlike BJT a MOSFET does not undergo ________________.
vii. ________________ temperature coefficient of rDS(ON) of MOSFETs facilitates easy
________________ of the devices.
viii. In a Power MOSFET the relation ship between iD and vGS – vGS(th) is almost
________________ in the active mode of operation.
ix. The safe operating area of a MOSFET is restricted on the left hand side by the
________________ limit.
Answer: (i) Cut off; (ii) vDS; (iii) decreases; (iv) vGS, vDS; (v) independent; (vi) second
break down; (vii) Positive, paralleling; (viii) linear; (ix) rDS (ON);
6.5 Switching characteristics of a MOSFET
6.5.1 Circuit models of a MOSFET cell

Like any other power semiconductor device a MOSFET is used as a switch in all power
electronic converters. As a switch a MOSFET operates either in the cut off mode (switch
off) or in the ohmic mode (switch on). While making transition between these two states it
traverses through the active region. Being a majority carrier device the switching process in
a MOSFET does not involve any inherent delay due to redistribution of minority charge
carriers. However, formation of the conducting channel in a MOSFET and its
disappearance require charging and discharging of the gate-source capacitance which
contributes to the switching times. There are several other capacitors in a MOSFET
structure which are also involved in the switching process. Unlike bipolar devices,
however, these switching times can be controlled completely by the gate drive circuit
design.

G
S
Gate oxide
+
n CGD
CGS CGD
p Drain body CGD1 idealized
depletion
CDS layer Actual
n-
CGD2
n+
VGS – VGS (th) = VDS VDS
D
(a) (b)
D D D
CGD CGD CGD
G (cut off) G iD = f(vGS) G rDS(ON)

(Active) (Ohmic)
CGS CGS CGS
S S S
(c)
Fig. 6.7: Circuit model of a MOSFET
(a) MOSFET capacitances
(b) Variation of CGD with VDS
(c) Circuit models.
Fig 6.7 (a) shows three important capacitances inherent in a MOSFET structure. The most
prominent capacitor in a MOSFET structure is formed by the gate oxide layer between the
gate metallization and the n+ type source region. It has the largest value (a few nano farads)
and remains more or less constant for all values of vGS and vDS. The next largest capacitor
(a few hundred pico forwards) is formed by the drain – body depletion region directly
below the gate metallization in the n- drain drift region. Being a depletion layer capacitance
its value is a strong function of the drain source voltage vDS. For low values of vDS (vDS <
(vGS – vGS (th))) the value of CGD (CGD2) is considerably higher than its value for large vDS
as shown in Fig 6.7 (b). Although variation of CGD between CGD1 and CGD2 is continuous a
step change in the value of CGD at vDS = vGS – vGS(th) is assumed for simplicity. The lowest
value capacitance is formed between the drain and the source terminals due to the drain –
body depletion layer away form the gate metallization and below the source metallization.
Although this capacitance is important for some design considerations (such as snubber
design, zero voltage switching etc) it does not appreciably affect the “hard switching”
performance of a MOSFET. Consequently, it will be neglected in our discussion. From the

above discussion and the steady state characteristics of a MOSFET the circuit models of a
MOSFET in three modes of operation can be drawn as shown in Fig 6.7 (c).
6.5.2 Switching waveforms

The switching behavior of a MOSFET will be described in relation to the clamped
inductive circuit shown in Fig 6.8. For simplicity the load current is assumed to remain
constant over the small switching interval. Also the diode DF is assumed to be ideal with
no reverse recovery current. The gate is assumed to be driven by an ideal voltage source
giving a step voltage between zero and Vgg in series with an external gate resistance Rg.
VD
DF IO
if
+
iD
CGD VDS
Rg
ig -
Vgg +
-
CGS
Fig. 6.8: Clamped inductive switching circuit using a MOSFET.
To turn the MOSFET on, the gate drive voltage changes from zero to Vgg. The gate
source voltage which was initially zero starts rising towards Vgg with a time constant τ1 =
Rg (CGS + CGD1) as shown in Fig 6.9.

Vgg
∫∫ τ2
VGS
VGSI0
VGS(th) τ1
τ2 = Rg(CGS+CGD2)
∫∫ t
ig τ1 = Rg(CGS+CGD1)
Vgg
R g igI0
∫∫ t
igI0
Vgg
−
Rg
iD, if iD if
∫∫
I0 I0
if iD
∫∫ t
VDS
I0ros (ON)
∫∫ t
tdON tri tfv1 tfv2 td(off) trv2 trvi tfi
tON toff
Fig. 6.9: Switching waveforms of a clamped inductive switching circuit using MOSFET
Note that during this period the drain voltage vDS is clamped to the supply voltage VD
through the free wheeling diode DF. Therefore, CGS and CGD can be assumed to be
connected in parallel effectively. A part of the total gate current ig charges CGS while the
other part discharges CGD.
Till vGS reaches vGS (th) no drain current flows. This time period is called turn on delay
time (td(ON)). Note that td(ON) can be controlled by controlling Rg. Byond td(ON) iD
increases linearly with vGS and in a further time tri (current rise time) reaches Io. The
corresponding value of vGS and ig are marked as VGS Io and ig Io respectively in Fig 6.9.
At this point the complete load current has been transferred to the MOSFET from the free
wheeling diode DF. iD does not increase byond this point. Since in the active region iD and
vGS are linearly related, vGS also becomes clamped at the value vGSIo. The gate current ig
now discharges CGD and the drain voltage starts falling.
d d d ig V -V I
v DS = ( vGS + vGD ) = v GD = = GG GS o ( 6.4 )
dt dt dt CGD CGD R g

The fall of vDS occurs in two distinct intervals. When the MOSFET is in the active region
(vDS > (vGS – vGS (th)) CGD = CGD1.Since CGD1 << CGD2, vDS falls rapidly. This fast fall
time of vDS is marked tfv1 in Fig 6.9. However, once in the ohmic region, CGD = CGD2 >>
CGD1. Therefore, rate of fall of vDS slows down considerably (tfv2). Once vDS reaches its
on state value (rDS(ON) Io) vGS becomes unclamped and increases towards Vgg with a
time constant τ2 = Rg (CGS + CGD2). Note that all switching periods can be reduced by
increasing Vgg or / and decreasing Rg. The total turn on time is tON = td(ON) + tri + tfv1 +
tfv2.
To turn the MOSFET OFF, Vgg is reduced to zero triggering the exact reverse process of
turn on to take place. The corresponding waveforms and switching intervals are show in
Fig 6.9. The total turn off time toff = td(off) + trv1 + trv2 + tfi.
6.5.3 MOSFET Gate Drive

MOSFET, being a voltage controlled device, does not require a continuous gate current
to keep it in the ON state. However, it is required to charge and discharge the gate-source and the
gate-drain capacitors in each switching operation. The switching times of a MOSFET essentially
depends on the charging and discharging rate of these capacitors. Therefore, if fast charging and
discharging of a MOSFET is desired at fast switching frequency the gate drive power
requirement may become significant. Fig 6.10 (a) shows a typical gate drive circuit of a
MOSFET.

VGG VD R1
RG +
VGG (β1 +1)
R1
Q1
Logic level RG
gate pulse RG
Q2 VGG
Q3
(b)
(a)
VD
D
DF
IL R
RG G
D R
S
B RB
G (d)
S
(c)
Fig. 6.10: MOSFET gate drive circuit.

(a) Gate drive circuit; (b) Equivalent circuit during turn on and off;
(b) Effect of parasitic BJT; (d) Parallel connection of MOSFET’s.
To turn the MOSFET on the logic level input to the inverting buffer is set to high state so
that transistor Q3 turns off and Q1 turns on. The top circuit of Fig 6.10 (b) shows the
equivalent circuit during turn on. Note that, during turn on Q1 remains in the active
region. The effective gate resistance is RG + R1 / (β1 + 1). Where, β1 is the dc current gain
of Q1.

To turn off the MOSFET the logic level input is set to low state. Q3 and Q2 turns on
whole Q1 turns off. The corresponding equivalent circuit is given by the bottom circuit of
Fig 6.10 (b)
The switching time of the MOSFET can be adjusted by choosing a proper value of RG.
Reducing RG will incase the switching speed of the MOSFET. However, caution should
be exercised while increasing the switching speed of the MOSFET in order not to turn on
the parasitic BJT in the MOSFET structure inadvertently. The drain-source capacitance
(CDS) is actually connected to the base of the parasitic BJT at the p type body region. The
body source short has some nonzero resistance. A very fast rising drain-source voltage
will send sufficient displacement current through CDS and RB as shown in Fig 6.10 (c).
The voltage drop across RB may become sufficient to turn on the parasitic BJT. This
problem is largely avoided in a modern MOSFET design by increasing the effectiveness
of the body-source short. The devices are now capable of dvDS/dt in excess to 10,000
V/μs. Of course, this problem can also be avoided by slowing down the MOSFET
switching speed.
Since MOSFET on state resistance has positive temperature coefficient they can be
paralleled without taking any special precaution for equal current sharing. To parallel two
MOSFETs the drain and source terminals are connected together as shown in Fig 6.10
(d). However, small resistances (R) are connected to individual gates before joining them
together. This is because the gate inputs are highly capacitive with almost no losses.
Some stray inductance of wiring may however be present. This stray inductance and the
MOSFET capacitance can give rise to unwanted high frequency oscillation of the gate
voltage that can result in puncture of the gate qxide layer due to voltage increase during
oscillations. This is avoided by the damping resistance R.
Exercise 6.3
i. The Gate-Source capacitance of a MOSFET is the ________________ among all three

capacitances.
ii. The Gate-Drain transfer capacitance of a MOSFET has large value in the
________________ region and small value in the ________________ region.
iii. During the turn on delay time the MOSFET gate source voltage rises from zero to the
________________ voltage.
iv. The voltage fall time of a MOSFET is ________________ proportional to the gate
charging resistance.
v. Unlike BJT the switching delay times in a MOSFET can be controlled by proper design
of the ________________ circuit.
Answer: (i) largest; (ii) ohmic, active; (iii) threshold; (iv) inversely; (v) gate drive.

2. A Power MOSFET has the following data
CGS = 800 pF ; CGD = 150 pF; gf = 4; vGS(th) = 3V;
It is used to switch a clamped inductive load (Fig 6.8) of 20 Amps with a supply voltage VD=
200V. The gate drive voltage is vgg = 15V, and gate resistance Rg = 50Ω. Find out maximum
did dv DS
value of and during turn ON.
dt dt
Answer: During turn on

i D ≈ g f ( v gs - v gs (th) )
di D dv gs
∴ = gf
dt dt
dv V -v
But ( CGS + CGD ) gs = gg gs
dt Rg
di D dv gf
∴
dt
= g f gs =
dt R g ( CGS + CGD )
( Vgg - vgs )
di D gf g f ( Vgg - vgs (th) )
∴
dt
=
R g ( CGS + CGD )
(V
gg - vgs Min )= R g ( CGS + CGD )
Max
di D
since for vgs < vgs (th) iD = =0
dt
di D 4
-12 (
∴ = 15 - 3) = 1.01×109 A sec
dt Max 50×950×10
From equation (6.4)
dv DS Vgg - VGS , Io
=
dt CGD R g
For Io = 20 A, vgs(th) = 3V, and gf = 4

I 20
VGS , Io = o + vgs (th) = + 3 = 8 volts
gf 4
dv DS 15 -8
∴ = = 933×106 V sec.
dt 150×10-12 ×50
6.6 MOSFET Ratings

Steady state operating limits of a MOSFET are usually specified compactly as a safe
operating area (SOA) diagram. The following limits are specified.
VDSS: This is the drain-source break down voltage. Exceeding this limit will destroy the
device due to avalanche break down of the body-drain p-n junction.

IDM: This is the maximum current that should not be exceeded even under pulsed current
operating condition in order to avoid permanent damage to the bonding wires.
Continuous and Pulsed power dissipation limits: They indicate the maximum
allowable value of the VDS, iD product for the pulse durations shown against each limit.
Exceeding these limits will cause the junction temperature to rise beyond the acceptable
limit.
All safe operating area limits are specified at a given case temperature.
In addition, several important parameters regarding the dynamic performance of the

device are also specified. These are
Gate threshold voltage (VGS (th)): The MOSFET remains in the cut off region when vGS
in below this voltage. VGS (th) decreases with junction temperature.
Drain Source on state resistance (rDS (ON)): This is the slope of the iD – vDS
characteristics in the ohmic region. Its value decreases with increasing vGS and increases
with junction temperature. rDS (ON) determines the ON state power loss in the device.
Forward Transconductance (gfs): It is the ratio of iD and (vGS – vGS(th)). In a MOSFET

switching circuit it determines the clamping voltage level of the gate – source voltage and
thus influences dvDS/dt during turn on and turn off.
Gate-Source breakdown voltage: Exceeding this limit will destroy the gate structure of
the MOSFET due to dielectric break down of the gate oxide layer. It should be noted that
this limit may by exceeded even by static charge deposition. Therefore, special
precaution should be taken while handing MOSFETs.
Input, output and reverse transfer capacitances (CGS, CDS & CGD): Value of these
capacitances are specified at a given drain-source and gate-source voltage. They are
useful for designing the gate drive circuit of a MOSFET.
In addition to the main MOSFET, specifications pertaining to the “body diode” are also
provided. Specifications given are
Reverse break down voltage: This is same as VDSS

Continuous ON state current (IS): This is the RMS value of the continuous current that
can flow through the diode.
Pulsed ON state current (ISM): This is the maximum allowable RMS value of the ON
state current through the diode given as a function of the pulse duration.
Forward voltage drop (vF): Given as an instantaneous function of the diode forward
current.
Reverse recovery time (trr) and Reverse recovery current (Irr): These are specified as
functions of the diode forward current just before reverse recovery and its decreasing
slope (diF/dt).

Exercise 6.4
i. The maximum voltage a MOSFET can with stand is ________________ of drain current.
ii. The FBSOA and RBSOA of a MOSFET are ________________.
iii. The gate source threshold voltage of a MOSFET ________________ with junction
temperature while the on state resistance ________________ with junction temperature.
iv. The gate oxide of a MOSFET can be damaged by ________________ electricity.
v. The reverse break down voltage of the body diode of a MOSFET is equal to
________________ while its RMS forward current rating is equal to ________________.
Answer: (i) independent; (ii) identical; (iii) decreases, increases; (iv) static; (v) VDSS; IDM.
Reference
[1] “Evolution of MOS-Bipolar power semiconductor Technology”, B. Jayant Baliga,
Proceedings of the IEEE, VOL.76, No-4, April 1988.
[2] “Power Electronics ,Converters Application and Design” Third Edition, Mohan,
Undeland, Robbins. John Wiley & Sons Publishers 2003.
[3] GE – Power MOSFET data sheet.

Lesson Summary
• MOSFET is a voltage controlled majority carrier device.
• A Power MOSFET has a vertical structure of alternating p and n layers.
• The main current carrying terminals of an n channel enhancement mode MOSFET are
called the Drain and the Source and are made up of n+ type semiconductor.
• The control terminal is called the Gate and is isolated form the bulk semiconductor by a
thin layer of SiO2.
• p type semiconductor body separates n+ type source and drain regions.
• A conducting n type channel is produced in the p type body region when a positive voltage
greater than a threshold voltage is applied at the gate.
• Current conduction in a MOSFET occurs by flow of electron from the source to the drain
through this channel.
• When the gate source voltage is below threshold level a MOSFET remains in the “Cut Off”
region and does not conduct any current.
• With vGS > vGS (th) and vDS < (vGS – vGS (th)) the drain current in a MOSFET is
proportional to vDS. This is the “Ohmic region” of the MOSFET output characteristics.
• For larger values of vDS the drain current is a function of vGS alone and does not depend on
vDs. This is called the “active region” of the MOSFET.
• In power electronic applications a MOSFET is operated in the “Cut Off” and Ohmic
regions only.
• The on state resistance of a MOSFET (VDS (ON)) has a positive temperature coefficient.
Therefore, MOSFETs can be easily paralleled.
• A MOSFET does not undergo second break down.
• The safe operating area (SOA) of a MOSFET is similar to that of a BJT except that it does
not have a second break down limit.
• Unlike BJT the maximum forward voltage withstanding capability of a MOSFET does not
depend on the drain current.
• The safe operating area of a MOSFET does not change under Forward and Reverse bias
conditions.
• The drain – body junction in a MOSFET structure constitute an anti parallel diode
connected between the source and the drain. This is called the MOSFET “body – diode.”
• The body diode of a MOSFET has the same break down voltage and forward current rating
as the main MOSFET.
• The switching delays in a MOSFET are due to finite charging and discharging time of the
input and output capacitors.
• Switching times of a MOSFET can be controlled completely by external gate drive design.

• The input capacitor along with the gate drive resistance determine the current rise and fall
time of a MOSFET during switching.
• The transfer capacitor (Cgd) determines the drain voltage rise and fall times.
• rDS (ON) of a MOSFET determines the conduction loss during ON period.
• rDS (ON) reduces with higher vgs. Therefore, to minimize conduction power loss maximum
permissible vgs should be used subject to dielectric break down of the gate oxide layer.
• The gate oxide layer can be damaged by static charge. Therefore MOSFETs should be
handled only after discharging one self through proper grounding.
• For similar voltage rating, a MOSFET has a relatively higher conduction loss and lower
switching loss compared to a BJT. Therefore, MOSFETs are more popular for high
frequency (>50 kHz) low voltage (<100 V) circuits.


Practice Problems
1. How do you expect the gate source capacitance of a MOSFET to varry with gate source
voltage. Explain your answer.
2. The gate oxide layer of a MOSFET is 1000 Angstrom thick Assuming a break down field
strength of 5 × 106 V/cm and a safely factor of 50%, find out the maximum allowable
gate source voltage.
3. Explain why in a high voltage MOSFET switching circuit the voltage rise and fall time is
always greater than current fall and rise times.
4. A MOSFET has the following parameters
VGS(th) = 3V, gfs = 3, CGS = 800 PF, CGD = 250 PF. The MOSFET is used to switch an
inductive load of 15 Amps from 150V supply. The switching frequency is 50 kHz. The
gate drive circuit has a driving voltage of 15V and output resistance of 50Ω. Find out the
switching loss in the MOSFET.

Answer to practice problems
1. When the gate voltage is zero the thickness of the gate-source capacitance is
approximately equal to the thickness of the gate oxide layer. As the gate source voltage
increases the width of the depletion layer in the p body region also increases. Since the
depletion layer is a region of immobile charges it in effect increases the thickness of the
gate-source capacitance and hence the value of this capacitances decreases with
increasing vGS. However, as vGS is increased further free electrons generated by thermal
ionization get attracted towards the gate oxide-semiconductor interface. These free
electrons screen the depletion layer partially and the gate-source capacitance starts
increasing again. When vGS is above vgs (th) the inversion layer completely screens the
depletion layer and the effective thickness of the gate-source capacitance becomes once
again equal to the thickness of the oxide layer. There after the value of CGS remains more
or less constant.
2. From the given data the break down gate source voltage
v GS BD = E BD × t gs
where EBD = Break down field strength
tgs = thickness of the oxide layer.
So v GS BD = 5×106 ×1000×10-8 = 50V

Let vgs Max be the maximum allowable gate source voltage assuming 50% factor of
safety.
∴ 1.5 vgs Max = vGS BD = 50 V
50
∴ vgs Max = V ≈ 33 Volts.
1.5
3. We Know that for MOSFET

i D = g fs ( VGS - VGS (th) )
∴
di D d
= g fs vGS = g fs
( Vgg - vGS )
dt dt R g CGS
During current rise Vgg >> vGS
di g fs
∴ D ≈ Vgg
dt R g CGS
Io
∴ t ri = t fi ≈ R g CGS where Io = load current.
g fs Vgg
Now From equation (6.4)
d Vgg - Vg s , Io Vgg
v DS = ≈
dt R g CGD R g CGD

Since Vgg >> Vgs, Io
V
∴ t rr = t fv ≈ D R g CGD where VD = Load voltage.
Vgg
t ri t I CG S
∴ = fi = o
t rr t fr VD g fs CG D
That is current rise and fall times are much shorter than voltage rise and fall times.
4. Referring to Fig 6.9 energy loss during switching occurs during intervals tri , tfv1, tfv2, trv2,trv1,
and tfi. For simplicity it will be assumed that tfv2 = trv2 = 0. Also the rise and fall of iD and vDS
will be assumed to be linear.
During tri
i D = g fs (vgs - vgs (th))
di D d Vgg - v gs
∴ = g fs v gs = g fs
dt dt (CGS + CGD )R g
di D g fs Vgg
∴ ≈ sinceVgg >> v gs during current rise
dt (CGS + CGD )R g
Io
∴ t ri = (CGS + CGD )R g
g fs Vgg
Energy loss during tri is
1 V I2
E ON1 = t ri VD Io = D o (CGS + CGD )R g
2 2g fs Vgg
During tfv
dVDS Vgg - Vgs, Io
=
dt CGD R g
I
But Vgs , Io = o + vgs (th)
g fs
I
Vgg - v gs (th) - o
dVDS g fs
∴ =
dt R g CGD
VD
∴ t fv = R g CGD
Io
Vgg - Vgs (th) -
g fs
Energy loss during tfv is

E ON2 = 1 t fv Io VD
2
VD 2 Io
= R g CGD
2 ⎛⎜ Vgg - vgs (th) - o ⎞⎟
I
⎝ g fs ⎠
∴ Energy loss during Turn on is

VD Io R g ⎡ Io ( CGS + CGD ) VD CGD ⎤
E ON = E ON1 + E ON2 = ⎢ + ⎥
2 ⎢
⎣
g fs Vgg ( Vgg - Vgs (th) ) ⎥⎦
From the symmetry of the Turn ON and the Turn OFF operation of MOSFET (i.e. tri = tfi, tfv =
trv)
E ON = EOFF
∴ Total switching energy lass is Esw = EON + EOFF = 2 EON

⎡ ⎤
⎢ ⎥
I g ⎛ C ⎞ VD Vgg
∴ E sw = VD Io R g CGD ⎢ o fs ⎜1+ GS ⎟ + ⎥
⎢ Vgg ⎝ CGD ⎠ Vgs (th) Io g fs ⎥
⎢ - ⎥
⎣ V gg Vgg ⎦
⎡ ⎤
⎢ ⎥
⎛ C ⎞I g VD Vgg
∴ Psw E sw = VD Io R g CGD f sw ⎢⎜1+ GS ⎟ o fs + ⎥
⎢⎝ CGD ⎠ Vgg v gs (th) Io g fs ⎥
⎢ 1- - ⎥
⎣ Vgg v gg ⎦
Substituting the values given
Psw = 32 mw,

Module
1
Power Semiconductor
Devices
Lesson
7
Insulated Gate Bipolar
Transistor (IGBT)
Constructional features, operating principle and characteristics of Insulated Gate Bipolar
Transistors (IGBT)
Instructional objects
• Differentiate between the constructional features of an IGBT and a MOSFET.

• Draw the operational equivalent circuit of an IGBT and explain its operating principle in
terms of the schematic construction and the operational equivalent circuit.
• Draw and explain the steady state output and transfer characteristics of an IGBT.
• Draw the switching characteristics of an IGBT and identify its differences with that of a
MOSFET.
• Design a basic gate drive circuit for an IGBT.
• Interpret the manufacturer’s date sheet of an IGBT.

7.1 Introduction
The introduction of Power MOSFET was originally regarded as a major threat to the power
bipolar transistor. However, initial claims of infinite current gain for the power MOSFETs were
diluted by the need to design the gate drive circuit capable of supplying the charging and
discharging current of the device input capacitance. This is especially true in high frequency
circuits where the power MOSFET is particularly valuable due to its inherently high switching
speed. On the other hand, MOSFETs have a higher on state resistance per unit area and
consequently higher on state loss. This is particularly true for higher voltage devices (greater
than about 500 volts) which restricted the use of MOSFETs to low voltage high frequency
circuits (eg. SMPS).
With the discovery that power MOSFETs were not in a strong position to displace the BJT,
many researches began to look at the possibility of combining these technologies to achieve a
hybrid device which has a high input impedance and a low on state resistance. The obvious first
step was to drive an output npn BJT with an input MOSFET connected in the Darlington
configuration. However, this approach required the use of a high voltage power MOSFET with
considerable current carrying capacity (due to low current gain of the output transistor). Also,
since no path for negative base current exists for the output transistor, its turn off time also tends
to get somewhat larger. An alternative hybrid approach was investigated at GE Research center
where a MOS gate structures was used to trigger the latch up of a four layer thyristor. However,
this device was also not a true replacement of a BJT since gate control was lost once the thyristor
latched up.
After several such attempts it was concluded that for better results MOSFET and BJT
technologies are to be integrated at the cell level. This was achieved by the GE Research
Laboratory by the introduction of the device IGT and by the RCA research laboratory with the
device COMFET. The IGT device has undergone many improvement cycles to result in the
modern Insulated Gate Bipolar Transistor (IGBT). These devices have near ideal characteristics
for high voltage (> 100V) medium frequency (< 20 kHZ) applications. This device along with
the MOSFET (at low voltage high frequency applications) have the potential to replace the BJT
completely.
7.2 Constructional Features of an IGBT

Vertical cross section of a n channel IGBT cell is shown in Fig 7.1. Although p channel IGBTs
are possible n channel devices are more common and will be the one discussed in this lesson.

Gate
Emitter
SiO2 SiO2
(Gate oxide) + - (Gate oxide)
n n
p Body region
J3
Drain drift
J2 n- region
J1 n+ Buffer layer
p+ Injecting layer
Collector
Fig. 7.1: Vertical cross section of an IGBT cell.
The major difference with the corresponding MOSFET cell structure lies in the addition of a p+
injecting layer. This layer forms a pn junction with the drain layer and injects minority carriers
into it. The n type drain layer itself may have two different doping levels. The lightly doped n-
region is called the drain drift region. Doping level and width of this layer sets the forward
blocking voltage (determined by the reverse break down voltage of J2) of the device. However, it
does not affect the on state voltage drop of the device due to conductivity modulation as
discussed in connection with the power diode. This construction of the device is called “Punch
Trough” (PT) design. The Non-Punch Through (NPT) construction does not have this added n+
buffer layer. The PT construction does offer lower on state voltage drop compared to the NPT
construction particularly for lower voltage rated devices. However, it does so at the cost of lower
reverse break down voltage for the device, since the reverse break down voltage of the junction
J1 is small. The rest of the construction of the device is very similar to that of a vertical
MOSFET (Link to 6.2) including the insulated gate structure and the shorted body (p type) –
emitter (n+ type) structure. The doping level and physical geometry of the p type body region
however, is considerably different from that of a MOSFET in order to defeat the latch up action
of a parasitic thyristor embedded in the IGBT structure. A large number of basic cells as shown
in Fig 7.1 are grown on a single silicon wafer and connected in parallel to form a complete IGBT
device.
The IGBT cell has a parasitic p-n-p-n thyristor structure embedded into it as shown in Fig 7.2(a).
The constituent p-n-p transistor, n-p-n transistor and the driver MOSFET are shown by dotted
lines in this figure. Important resistances in the current flow path are also indicated.

Gate
Emitter
MOSFET n+
J3
n-p-n p
Body spreading resistance
Drift J2
resistance p-n-p n-
n+
J1
p+
Collector
(a)
Drift
region Collector Drift
resistance region Collector
resistance
Gate Body
spreading
resistance
Emitter
Gate
(c)
Emitter
(b)
Fig. 7.2: Parasitic thyristor in an IGBT cell.
(a) Schematic structure
(b) Exact equivalent circuit.
(c) Approximate equivalent circuit
Fig 7.2(b) shows the exact static equivalent circuit of the IGBT cell structure. The top p-n-p
transistor is formed by the p+ injecting layer as the emitter, the n type drain layer as the base and
the p type body layer as the collector. The lower n-p-n transistor has the n+ type source, the p
type body and the n type drain as the emitter, base and collector respectively. The base of the
lower n-p-n transistor is shorted to the emitter by the emitter metallization. However, due to
imperfect shorting, the exact equivalent circuit of the IGBT includes the body spreading
resistance between the base and the emitter of the lower n-p-n transistor. If the output current is
large enough, the voltage drop across this resistance may forward bias the lower n-p-n transistor
and initiate the latch up process of the p-n-p-n thyristor structure. Once this structure latches up
the gate control of IGBT is lost and the device is destroyed due to excessive power loss.
A major effort in the development of IGBT has been towards prevention of latch up of the
parasitic thyristor. This has been achieved by modifying the doping level and physical geometry
of the body region. The modern IGBT is latch-up proof for all practical purpose. Fig 7.3(a) and
(b) shows the circuit symbol and photograph of an IGBT.

C
E
(a) (b)
Fig. 7.3: Circuit symbol of an IGBT.

(a) Circuit symbol.
(b) Photograph.
Exercise 7.1
Fill in the blank(s) with the appropriate word(s).
i. An IGBT is a __________________ device combining the advantages of a

__________________ and a __________________.
ii. IGBT is suitable for __________________ voltage __________________ frequency
applications.
iii. In an IGBT cell structure a __________________ type injecting layer is added on top of
the drain of an n channel MOSFET.
iv. The forward blocking voltage of an IGBT is determined by the __________________
and __________________ of the drain drift layer.
v. A “punch through” IGBT has __________________ reverse break down voltage while
the “Non punch through” IGBT has __________________ voltage blocking capacity.
vi. The IGBT cell has a parasitic __________________ structure embedded into it.
vii. The parasitic __________________ structure of an IGBT cell can __________________
at large collector current due to imperfect body emitter shorting.
viii. The doping level and physical geometry of the IGBT __________________ region is
designed to be considerably different from that of a MOSFET to prevent its
__________________.
Answers:
i) hybrid, MOSFET, BJT ; ii) high, medium ; iii) p+ ; iv) thickness, doping level ; v) low,
symmetrical ; vi) thyristor; vii) thryistor, latch up ; viii) body, latch up.
7.3 Operating principle of an IGBT

Operating principle of an IGBT can be explained in terms of the schematic cell structure and
equivalent circuit of Fig 7.2(a) and (c). From the input side the IGBT behaves essentially as a

MOSFET. Therefore, when the gate emitter voltage is less then the threshold voltage no
inversion layer is formed in the p type body region and the device is in the off state. The forward
voltage applied between the collector and the emitter drops almost entirely across the junction J2.
Very small leakage current flows through the device under this condition. In terms of the
equivalent current of Fig 7.2(c), when the gate emitter voltage is lower than the threshold voltage
the driving MOSFET of the Darlington configuration remains off and hence the output p-n-p
transistor also remains off.
When the gate emitter voltage exceeds the threshold, an inversion layer forms in the p type body
region under the gate. This inversion layer (channel) shorts the emitter and the drain drift layer
and an electron current flows from the emitter through this channel to the drain drift region. This
in turn causes substantial hole injection from the p+ type collector to the drain drift region. A
portion of these holes recombine with the electrons arriving at the drain drift region through the
channel. The rest of the holes cross the drift region to reach the p type body where they are
collected by the source metallization.
From the above discussion it is clear that the n type drain drift region acts as the base of the
output p-n-p transistor. The doping level and the thickness of this layer determines the current
gain “∝” of the p-n-p transistor. This is intentionally kept low so that most of the device current
flows through the MOSFET and not the output p-n-p transistor collector. This helps to reduced
the voltage drop across the “body” spreading resistance shown in Fig 7.2 (b) and eliminate the
possibility of static latch up of the IGBT.
The total on state voltage drop across a conducting IGBT has three components. The
voltage drop across J1 follows the usual exponential law of a pn junction. The next component of
the voltage drop is due to the drain drift region resistance. This component in an IGBT is
considerably lower compared to a MOSFET due to strong conductivity modulation by the
injected minority carriers from the collector. This is the main reason for reduced voltage drop
across an IGBT compared to an equivalent MOSFET. The last component of the voltage drop
across an IGBT is due to the channel resistance and its magnitude is equal to that of a
comparable MOSFET.
7.4 Steady state characteristics of an IGBT

The i-v characteristics of an n channel IGBT is shown in Fig 7.4 (a). They appear
qualitatively similar to those of a logic level BJT except that the controlling parameter is not a
base current but the gate-emitter voltage.

VCC iC Increasing iC
Saturation V
VCC VgE6 gE
RL
Active F
ic + RL VgE5
C Load line Fault
G VcE A Load line
E VgE4
VgE - VgE3
B VgE2
gfs
VgE1
VRM C
Cut off
VCC VCES VCE VgE (th) VgE
(a) (b)
Fig. 7.4: Static characteristics of an IGBT

(a) Output characteristics; (b) Transfer characteristics
When the gate emitter voltage is below the threshold voltage only a very small leakage
current flows though the device while the collector – emitter voltage almost equals the supply
voltage (point C in Fig 7.4(a)). The device, under this condition is said to be operating in the cut
off region. The maximum forward voltage the device can withstand in this mode (marked VCES
in Fig 7.4 (a)) is determined by the avalanche break down voltage of the body – drain p-n
junction. Unlike a BJT, however, this break down voltage is independent of the collector current
as shown in Fig 7.4(a). IGBTs of Non-punch through design can block a maximum reverse
voltage (VRM) equal to VCES in the cut off mode. However, for Punch Through IGBTs VRM is
negligible (only a few tens of volts) due the presence of the heavily doped n+ drain buffer layer.
As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the
active region of operation. In this mode, the collector current ic is determined by the transfer
characteristics of the device as shown in Fig 7.4(b). This characteristic is qualitatively similar to
that of a power MOSFET and is reasonably linear over most of the collector current range. The
ratio of ic to (VgE – vgE(th)) is called the forward transconductance (gfs) of the device and is an
important parameter in the gate drive circuit design. The collector emitter voltage, on the other
hand, is determined by the external load line ABC as shown in Fig 7.4(a).
As the gate emitter voltage is increased further ic also increases and for a given load resistance
(RL) vCE decreases. At one point vCE becomes less than vgE – vgE(th). Under this condition the
driving MOSFET part of the IGBT (Fig 7.2(c)) enters into the ohmic region and drives the
output p-n-p transistor to saturation. Under this condition the device is said to be in the
saturation mode. In the saturation mode the voltage drop across the IGBT remains almost
constant reducing only slightly with increasing vgE.
In power electronic applications an IGBT is operated either in the cut off or in the saturation
region of the output characteristics. Since vCE decreases with increasing vgE, it is desirable to use
the maximum permissible value of vgE in the ON state of the device. vgE(Max) is limited by the
maximum collector current that should be permitted to flow in the IGBT as dictated by the
“latch-up” condition discussed earlier. Limiting VgE also helps to limit the fault current through

the device. If a short circuit fault occurs in the load resistance RL (shown in the inset of Fig
7.4(a)) the fault load line is given by CF. Limiting vgE to vgE6 restricts the fault current
corresponding to the operating point F. Most IGBTs are designed to with stand this fault current
for a few microseconds within which the device must be turned off to prevent destruction of the
device.
It is interesting to note that an IGBT does not exibit a BJT-like second break down failure. Since,
in an IGBT most of the collector current flows through the drive MOSFET with positive
temperature coefficient the effective temperature coefficient of vCE in an IGBT is slightly
positive. This helps to prevent second break down failure of the device and also facilitates
paralleling of IGBTs.
Exercise 7.2
i. From the input side the IGBT behaves essentially as a __________________.

ii. When the gate emitter voltage is below __________________ no __________________
layer is formed in the p type body region.
iii. Electrons arriving through the drive MOSFET causes __________________ injection
from the __________________ to the drain drift region.
iv. In an IGBT most of the collector current flows through the __________________ and not
through the __________________.
v. When the gate-emitter voltage of an IGBT is below threshold if operates in the
__________________ region.
vi. In the active region of operation the collector current of an IGBT is determined by the
__________________ characteristics which is reasonably __________________ over
most of the collector current range.
vii. For the same load resistance as the vgE of an IGBT is increased it enters
__________________ region.
viii. The forward voltage drop of an IGBT in the saturation region remains approximately
__________________.
ix. An IGBT has small __________________ temperature coefficient of on state voltage
drop.
x. An IGBT does not exhibit __________________ failure mode.
Answers:
i) MOSFET; ii) threshold, inversion; iii) hole, collector; iv) MOSFET, BJT; v) cut-off; vi)
transfer, linear; vii)saturation; viii) constant; ix) positive; x) second break down.

7.5 Switching characteristics of IGBT
Switching characteristics of the IGBT will be analyzed with respect to the clamped inductive
switching circuit shown in Fig 7.5(a). The equivalent circuit of the IGBT shown in Fig 7.5 (b)
will be used to explain the switching waveforms.
VCC
C
iL iD
DF D
iC + CGD
C VCE
Rg ig G Q1 G S
E CgE E
-
Vgg
(b)
(a)
Fig. 7.5: Inductive switching circuit using an IGBT

(a) Switching circuit; (b) Equivalent circuit of the IGBT
The switching waveforms of an IGBT is, in many respects, similar to that of a Power MOSFET.
This is expected, since the input stage of an IGBT is a MOSFET as shown in Fig 7.5(b). Also in
a modern IGBT a major portion of the total device current flows through the MOSFET.
Therefore, the switching voltage and current waveforms exhibit a strong similarity with those of
a MOSFET. However, the output p-n-p transistor does have a significant effect on the switching
characteristics of the device, particularly during turn off. Another important difference is in the
gate drive requirement. To avoid dynamic latch up, (to be discussed later) the gate emitter
voltage of an IGBT is maintained at a negative value when the device is off.

Vgg ∫∫ VgE(th)
VgE(th)
τ2 = Rg(CGS+CGD2)
VgE
VgE,IL VgE,IL
∫∫ t
τ1 = Rg(CGS+CGD1)
VCE
VCE(sat)
VCC VCC
∫∫ t
iC ∫∫
iD IL IL IL IL
∫∫ t
tdON tri tfv1 tfv2 trv1 trv2 tfi2
tfi1
Fig. 7.6: Switching waveforms of an IGBT.

The switching waveforms of an IGBT is shown in Fig 7.6. Similarity of these waveforms with
those of a MOSFET is obvious. To turn on the IGBT the gate drive voltage changes from –Vgg to
+Vgg. The gate emitter voltage vgE follows Vgg with a time constant τ1. Since the drain source
voltage of the drive MOSFET is large the gate drain capacitor assumes the lower value CGD1.
The collector current ic does not start increasing till vgE reaches the threshold voltage vgE(th).
Thereafter, ic increases following the transfer characteristics of the device till vgE reaches a value
vgEIL corresponding to ic = iL. This period is called the current rise time tri. The free wheeling
diode current falls from IL to zero during this period. After ic reaches IL, vgE becomes clamped at
vgE IL similar to a MOSFET. vCE also starts falling during this period. First vCE falls rapidly (tfv1)
and afterwards the fall of vCE slows down considerably. Two factors contribute to the slowing
down of voltage fall. First the gate-drain capacitance Cgd will increase in the MOSFET portion of
the IGBT at low drain-source voltages. Second, the pnp transistor portion of the IGBT traverses
the active region to its on state more slowly than the MOSFET portion of the IGBT. Once the
pnp transistor is fully on after tfv2, the on state voltage of the device settles down to vCE(sat). The
turn ON process ends here.
The turn off process of an IGBT follows the inverse sequence of turn ON with one major
difference. Once vgE goes below vgE(th) the drive MOSFET of the IGBT equivalent circuit turns
off. During this period (tfi1) the device current falls rapidly. However, when the drive MOSFET
turns off, some amount of current continues of flow through the output p-n-p transistor due to
stored charge in its base. Since there is no reverse voltage applied to the IGBT terminals that
could generate a negative drain current, there is no possibility for removing the stored charge by
carrier sweep-out. The only way these excess carriers can be removed is by recombination within
the IGBT. During this recombination period (tfi2) the remaining current in the IGBT decays
relatively slowly forming a current fail. A long tfi2 is undesirable, because the power dissipation

in this interval will be large due to full collector-emitter voltage. tfi2 can be reduced by
decreasing the excess carrier life time in the p-n-p transistor base. However, in the process, on
state losses will increase. Therefore, judicious design trade offs are made in a practical IGBT to
give minimum total loss.
The gate drive circuit of an IGBT should ensure fast and reliable switching of the device. In
particular, it should.
• Apply maximum permissible VgE during ON period.

• Apply a negative voltage during off period.
• Control dic dt during turn ON and turn off to avoid excessive Electro magnetic
interference (EMI).
• Control dvce dt during switching to avoid IGBT latch up.
• Minimize switching loss.

• Provide protection against short circuit fault.
Detailed discussion on IGBT gate drive circuit is beyond the scope of this lesson. References [4]
& [5] provide good discussion on this subject. Fig 7.7(a) shows a simplified IGBT gate drive
circuit.
RC +Vcc
+Vgg
Ri
Q1
- RB R G IGBT
Vi
+ Q2
(Logic level)
E
Opto isolator
Level Totem pole
Shifting -Vgg -Vcc gate drive
Comparator amplifier
(a)
RB RB
R β1 +1 R β2 +1
G G
Vgg To IGBT To IGBT
Gate -Vgg Gate
E E
Turn on equivalent circuit Turn off equivalent circuit
(b)
Fig. 7.7: IGBT gate drive circuit
(a) Gate drive
(b) Equivalent circuit of the gate drive during turn on and turn off.
The logic level gate drive signal is first opto-isolated and fed to a level shifting comparator. This
stage converts the unipolar (usually positive) out put voltage of the opto-isolator to a bipolar
(±Vgg) signal compatible to the IGBT gate drive levels. The output of the comparator feeds a
totem pole output amplifier stage which drives the IGBT. The equivalent circuit of the gate drive
during turn on and off are shown in Fig 7.7(b). If VCC > Vgg then both Q1 and Q2 will operate
in the active region and reasonably constant value of β1 & β2 of these two transistors can be used
for analysis purpose. These equivalent circuits along with the model of the IGBT input MOSFET
can be used to analyze the switching performance of the device. Conversely, for a desired
switching performance a suitable gate drive circuit can be designed.
7.6 IGBT ratings and safe operating area

Maximum collector-emitter voltage (VCES): This rating should not be exceeded even on
instantaneous basis in order to prevent avalanche break down of the drain-body p-n junction.
This is specified at a given negative gate emitter voltage or a specified resistance connected
between the gate and the emitter.
Maximum continuous collector current (IC): This is the maximum current the IGBT can
handle on a continuous basis during ON condition. It is specified at a given case temperature
with derating curves provided for other case temperatures.
Maximum pulsed collector current (ICM): This is the maximum collector current that can flow
for a specified pulse duration. This current is limited by specifying a maximum gate-emitter
voltage.
Maximum gate-emitter voltage (VgES): This is the maximum allowable magnitude of the gate-
emitter voltage (of both positive and negative polarity) in order to
• Prevent break down of the gate oxide insulation.
• Restrict collector current to ICM.
Collector leakage current (ICES): This is the leakage collector current during off state of the
device at a given junction temperature. This is usually specified at VgE = 0V and vCE = VCES.
Gate-emitter leakage current (IGES): Usually specified at vCE = 0V & vgE = vgES.
Collector emitter saturation voltage (VCE(sat)): This is specified at a given junction

temperature, gate-emitter voltage and collector current. For more detailed data the output
characteristics of the device for different vgE and expanded near the saturation zone is also
provided.
Gate-emitter threshold voltage (vgE(th)): It is specified at a low collector emitter voltage and
collector current.
Forward Transconductance (gfs): This is again specified at a low value of vCE. For more
detailed data the transfer characteristics of the device (ic vs vgE) is also provided.

Input, output and transfer capacitances (Cies, Coes & Cres): These are, gate-emitter, collector-
emitter and gate-drain capacitances of the device respectively, specified at a given collector-
emitter voltage. Variation of these parameters as functions of vCE are also supplied.
Switching times (td(ON) tri, tfv, trv, tfi): These times are specified for inductive load switching as
functions of gate charging resistance and collector current. In addition turn on and turn off
energy losses per switching operation are also specified.
Maximum total power dissipation (Ptmax): This is the maximum allowable power lass in the
device (both switching and conduction) on a continuous basis at a given case temperature.
Derating curve at other temperatures are also specified.
The IGBT has robust SOA both during turn on and turn off. Fig 7.8 (a) shows the FBSOA. On
the left side it is restricted by the forward voltage drop characteristics. Up to maximum
continuous collector current this voltage remains reasonably constant at a low value. However, at
ICM this voltage starts increasing as the IGBT starts entering active region. On the top the
FBSOA is restricted by ICM.
iC iC
ICM ICM 1000V/μS
IC 10-5sec
10-4sec
2000V/μS
10-3sec
10-2sec 3000V/μS
DC
VCES VCE VCES VCE

(a) (b)
Fig. 7.8: Safe operating area of an IGBT

(a) FBSOA; (b) RBSOA.
The other two limits are formed by the maximum power dissipation limit and the maximum
forward voltage limit. Like other devices the maximum power dissipation limit increases with
reduction in the on pulse width.
The RBSOA for low values of dvCE dt is rectangular. However, for increased dvCE dt the upper-right
hand corner is progressively cut out. The reason for this restriction on the RBSOA is to avoid
dynamic latch up. The device user can easily control dvCE dt by proper choice of Vgg and the gate
drive resistance.
Exercise 7.3
i. In a modern IGBT most of the collector current flows through the _________________
and not the _________________.

ii. To avoid _________________ the gate emitter voltage of an IGBT is maintained at a
_________________ value when the device is off.
iii. During turn on of an IGBT the rate of fall of voltage slows down towords the end since
the output p-n-p transistor traverses its _________________ region more
_________________ compared to the drive MOSFET.
iv. During turn off of an IGBT a _________________ is formed due to excess stored charge
in the _________________ region of the output p-n-p transistor.
v. The gate drive circuit of an IGBT should control dic

dt to avoid excessive
_________________.
dvCE
vi. dt of an IGBT during turn off should be controlled to prevent _________________ of
the device.
vii. A specified maximum gate emitter voltage of an IGBT helps to limit the collector current
during _________________ fault.
viii. Collector emitter saturation voltage of an IGBT _________________ with increasing

gate-emitter voltage.
ix. The FBSOA of an IGBT is similar to that of a _________________ except that the on
state voltage drop is much _________________.
x. The upper right hand corner of the IGBT RBSOA is gradually cut out with increasing
_________________ to avoid _________________ of the device.
Answer: (i) MOSFET, BJT; (ii) latch up, negative; (iii) active, slowly; (iv) current tail, base; (v)
EMI; (vi) Latch up; (vii) short circuit; (viii) decreases; (ix) MOSFET, lower; (x) dvCE dt , latch up.
Reference
[1] B. Jayanta Baliga, “Evolution of MOS Bipolar Power Semiconductor Technology”,
Proceedings of the IEEE, vol. 76, No. 4, April 1988, pp 409-418.
[2] “Power electronics, Converters, Applications and Design”, Mohan, Undeland, Robbins;
John Wiley & Sons, 2003
[3] B. Jayanta Baliga et. al, “The Insulated Gate Transistor: A new Three-Terminal MOS-
Controlled Bipolar. Power Device”, IEEE transaction on Electron Devices, vol. ED-31,
No. 6 June 1984 pp 421-828.
[4] Allen R. Hefner, “An Investigation of the drive circuit requirements for the Power
Insulated Gate Bipolar Transistor”, IEEE Transactions on Power Electronics. Vol. 6 No.
2. April 1991.

[5] Carmelo Licitra et. al, “A New Driving circuit for IGBT Devices”, IEEE Transaction on
Power Electronics, Vol. 10, No-3 may 1995.
[6] “SEMIKRON Power Electronics News 2001”, SEMIKRON International, Germany.
Lesson Summary
• IGBT is a hybrid device which combines the advantages of MOSFET and BJT.
• An IGBT is formed by adding a p+ collector layer on the drain drift layer of a Power
MOSFET.
• Punch through IGBT has a thin n+ buffer layer between the p+ collector layer and n-
drain drift layer. They have significantly lower conduction loss.
• The IGBT cell structure embeds a parasitic thyristor in it. Latching up of this thyristor is
prevented by special structuring of the body region and increasing the effectiveness of the
body shorting.
• From the operational point of view an IGBT is a voltage controlled bipolar device.
• The operational equivalent circuit of an IGBT has an n channel MOSFET driving a p-n-p
BJT.
• Like other semiconductor devices on IGBT can also operate in the cut off active and
saturation regions.
• When the gate-emitter voltage of an IGBT is below threshold it operates in the cut off
region.
• For a given load resistance the operating point of an IGBT can be moved from cut off to
saturation through the active region by increasing the gate-emitter voltage.
• In the active region, the collector current of an IGBT is determined by the gate-emitter
voltage which can be limited to a given maximum value to limit the fault current through
the device in the event of a load short circuit.
• The IGBTs have a slightly positive temperature coefficient of the on-state voltage drop
which makes paralleling of these devices simpler.
• An IGBT does not exhibit second break down phenomena as in the case of a BJT.
• The switching characteristics of an IGBT is similar to that of a MOSFET.
• To avoid dynamic latch up of the parasitic thryrstor in an IGBT, the gate emitter voltage
of the device is maintained at a negative value during it’s off period.
• During turn off, the collector current of an IGBT can exhibit “current tailing” due to
stored base change in the base region of the output p-n-p transistor.
• The forward bias SOA of an IGBT is similar to that of a MOSFET except the on state
voltage drop being much lower.
• The maximum allowable collector current in an IGBT is restricted by the static latch up
consideration.

dv
• The RBSOA of an IGBT is rectangular for low values of dtCE . For higher dvCE dt the upper
right half corner of the RBSOA is progressively cut-out to prevent “dynamic latch up of
the device”.
• The IGBT can switch at moderately high frequency (<20 kHZ) and in this range is likely
to replace the BJTs in all medium to high power applications.


Q1. What effects do the width and doping level of the drain drift region of an IGBT have on
its performance.
Q2. (a) In an IGBT a major portion of the collector current flow through the driver MOSFET
section which has a voltage rating almost same as the device. Then how does the on state
voltage drop of an IGBT remain low compared to an equivalent MOSFET?
(b) An IGBT is used to switch a resistive load of 5Ω from a DC supply of 350 volts as
shown in the inset of Fig 7.4 (a). The ON state gate voltage is vgE = 15v. For the IGBT,
vgE (th) = 4 volts and gts = 25. Find out the maximum current flowing through the IGBT
in the event of a short circuit fault across the load. Also find out the power dissipation
inside the device.
Q3. What do you under stand by “dynamic latch up” of an IGBT. How can it be prevented?
Q4. What steps are taken in the cell structure design of an IGBT to minimize the “tail current”
during turn off operation.
Q5. In the basic gate drive circuit of an IGBT shown in Fig 7.7 (a) following data are given
Vgg = 15 V, Vcc = 20 V, β1 for Q1 = 50, β2 for Q2 = 50.
RB = 2.2 KΩ, R = 30Ω, VgE (th) of IGBT = 4V, gfs = 40
CgE = 4nF, CgD = 500pF,
The IGBT is used to switch a clamed inductive load of 50 Amps from a 400 volts supply.
dvCE
Find out maximum values of dic
dt and dt during Turn on and Turn off of the IGBT.

1. The width and doping level of the drain drift layer of an IGBT affects the performance of
the IGBT in several ways.
• They determine the forward break down voltage of the IGBT.

• Referring to Fig 7.2 (b), the drain drift region constitutes the base of the upper p-n-p
transistor. The width and the doping level of this layer determines the current gain “∝” of
this transistor. This is intentionally kept low so that most of the device current flows
through the MOSFET and not the output p-n-p transistor collector. This helps to reduce
the voltage drop across the body spreading resistance between the base and emitter of the
lower p-n-p transistor. Thus the possibility of turning on this transistor and consequent
latch up of the device is minimized.
• Since the major part of the device current flows through the MOSFET which has a
positive temperature coefficient of drain source voltage drop, the collector-emitter
voltage drop across the device exhibits a slightly positive temperature coefficient. This
eliminates the possibility of second break down failure in IGBTs and simplifies
paralleling of these devices.
2. (a) The total voltage drop across a conducting IGBT has three components. The voltage
drop across the emitter-base junction of the output p-n-p transistor follows the usual
exponential low of a p-n junction. The next component of the voltage drop is due to the
drain drift region resistance. In a normal high voltage MOSFET this component of the
voltage drop is large due to lower doping level (necessary for blocking high voltage) of
this region. However, in a conducting IGBT electrons arriving at the drain drift region
through the MOSFET channel causes large minority carrier injection from the p+
collector. The consequent conductivity modulation reduces the resistance (and hence the
voltage drop) in this region. The third component of the IGBT voltage drop occurs across
the channel of the driving MOSFET and is same as that of an equivalent high voltage
MOSFET. Therefore, the reduced voltage drop across a conducting IGBT is due to
reduction of the drain drift region resistance by “conductivity modulation”.
(b) In the event of a short circuit across the load the voltage across the device will be 350
volts and the IGBT will operate in the active region. In this region
iC = gfs ( vgE - vgE (th) )
Substituting the given values
iC Max = 25 (15 - 4 ) = 275 Amps
Power dissipation inside the device will be
PD = vCE iC Max = 350 × 275 = 96.25 kW

3. Static latch up in an IGBT occurs when the continuous ON state current exceeds a critical
value. However, under dynamic conditions, when the IGBT is switching from on to off
state if may latch up at drain current less than this value. During turn off, the voltage
across the driver MOSFET increases rapidly. This voltage is blocked by the drain-body
p-n junction. To block the rapid build up of the voltage the width of the depletion region
in the drain drift layer also increases rapidly. This rapid increase in the depletion layer
width temporally increases the current gain “∝” of the output p-n-p transistor and causes
latch up of the device at a lower collector current than would have been necessary for
static latch up.
4. Punch Through and Non-punch through IGBTs solve the problem of tail current by two
different approaches. Punch through IGBT s attempt to minimize the current tailing
problem by shortening the duration of the tailing time. This is done by reducing the
excess carrier life time in the n+ buffer layer compared to the n- drain drift layer. This n+
buffer layer acts as a sink for excess holes and greatly enhances the removal rate of holes
from the drain drift layer. Thus the tail time is reduced.
Non punch through IGBTs attack the current tailing problem by minimizing the
magnitude of the current during the failing interval. This is done by designing the IGBT
so that the MOSFET section carries as much of the total current as possible. Newer NPT
IGBT designs have more than 90% of the total current carried by the MOSFET section of
the device.
5. During turn on and turn off the IGBT passes through the active region.
When vgE is greater than vgE(th) the collector current is given by
iC = gfs ( vgE - vgE (th) )
dic d
∴ = gfs vgE
dt dt
But from the equivalent circuit of the IGBT gate drive circuit during turn on
d Vgg - vgE
vgE =
dt (
( CgE + CgD ) R + βR1 +1B )
dic d gfs ( Vgg - vgE )
∴ = gfs vgE =
dt dt (
( CgE + CgD ) R + βR1 +1B )
In the active region Vgg >> vgE
Also since Vcc > Vgg, Q1 & Q2 operates in the active region.
Substituting the given values

dic 40 × 15
= = 1.82 × 109 A/Sec
dt 4500 × 10 × ( 30 + 51 )
-12 2200
dic
Since β1 = β2 , during turn off will also have the same value
dt
dic
So = 1.82 A/ns
dt
Since load current is 50 Amps and gfs = 40
IL
vge IL = vgE (th) + = 5.25 volts
gfs
dvCE V - v IL
Daring turn on CgD = ig IL = gg gERB
dt R + β+1
dvCE
∴ during turn ON is
dt
dvCE Vgg - vgE IL 15 - 5.25
= =
dt ( RB
CgD R + β +1
1
)500 × 10-12 ( 30 + 2200
51 )
= 2.67 × 108 V/Sec
Since Vgg+ =Vgg- and β1 = β2
dvCE
during turn off will be same
dt
dvCE
So = 2.67 × 108 V/Sec or 267 V/μs.
dt

Module
1
Power Semiconductor
Devices
Lesson
8
Hard and Soft Switching
of Power Semiconductors
This lesson provides the reader the following
(i) To highlight the issues related to device stresses under Hard switching;
(ii) To suggest means of reducing such stresses with external circuitry;
(iii) To propose alternative switching methods for stress reduction;
(iv) Enable the choice of the appropriate switching strategy
Soft and Hard Switching

Semiconductors utilised in Static Power Converters operate in the switching mode to
maximise efficiency. Switching frequencies vary from 50 Hz in a SCR based AC-DC Phase
Angle Controller to over 1.0 MHz in a MOSFET based power supply. The switching or dynamic
behaviour of Power Semiconductor devices thus attracts attention specially for the faster ones for
a number of reasons: optimum drive, power dissipation, EMI/RFI issues and switching-aid-
networks.
With SCRs’ 'forced commutation' and 'natural (line) commutation' usually described the type of
switching. Both refer to the turn-off mechanism of the SCR, the turn-on dynamics being
inconsequential for most purposes. A protective inductive snubber to limit the turn-on di/dt is
usually utilised. For the SCRs’ the turn-off data helps to dimension the 'commutation
components' or to set the 'margin angle'. Conduction losses account for the most significant part
of total losses.
Present day fast converters operate at much higher switching frequencies chiefly to reduce
weight and size of the filter components. As a consequence, switching losses now tend to
predominate, causing the junction temperatures to rise. Special techniques are employed to
obtain clean turn-on and turn-off of the devices. This, along with optimal control strategies and
improved evacuation of the heat generated, permit utilisation of the devices with a minimum of
deration.
This chapter first examines the switching process, estimates the device dissipation and indicates
design procedures for the cooling system.
Losses in Power Semiconductors

A converter consists of a few controlled and a few uncontrolled devices (diodes). While the first
device is driven to turn-on or off, the uncontrolled device operates mainly as a slave to the
former. Power loss in the converter is the aggregate of these losses. Occasionally the diode and
the controlled device are housed in the same module. The losses corresponding to each
contribute to the temperature rise of the integrated module.

The losses can be segregated as follows:
Total module dissipation
Controlled device losses Diode losses
conduction switching conduction switching
Turn-off Turn-on
Turn-off Turn-off
Conduction Losses
Conduction losses are caused by the forward voltage drop when the power semiconductor is on
and can be described by (with reference to an IGBT)
Fig. 3.1 Approximate forward voltage of IGBT and diode
WC = Vce (sat)(Ic).Ic
where Ic is the current carried by the device and Vce(sat)(Ic) is the current dependant forward
voltage drop. This drop may be expressed as
Vce (sat) (Ic) = V0 + R . Ic
This relation defines the forward drop of an IGBT in a similar manner to a diode. A part of the
drop is constant while another part is collector current dependent.
The given data should be used as follows: Using the numerical value is the most simple way to
determine conduction losses. The numerical value can be applied if the current in the device is
equal or close to the specified current - data sheet numerical values are specified for typical
application currents.
The graph most accurately determines conduction losses. The conditions in which the data are
used should correspond to the application. To estimate if a power semiconductor rating is
appropriate, usually the values valid for elevated temperature, close to the maximum junction
temperature TJmax , should be used to calculate power losses because this is commonly the
operating point at nominal load.

Blocking Losses
Blocking losses are generated by a low leakage current through the device with a high blocking
voltage.
WB = Vb(I).IL
Where IL is the leakage current and Vb(I) is the current dependemt blocking voltage. Data sheets
indicates leakage current at certain blocking voltage and temperature. The dependence between
leakage current and applied voltage typically is exponential; this means that using a data sheet
value given for a blocking voltage higher than applied overestimates blocking losses. However in
general, blocking losses are small and can often, but not always, be neglected.
Switching Losses
IGBTs are designed for use in switching converters and not for linear operation. This means
switching time intervals are short compared to the pulse duration at typical switching
frequencies, as can be seen from their switching times, such as rise time tr and fall time tf in the
data sheets. Switching losses occur during these switching intervals.
Fig. 3.2 Switching losses (appx)
For IGBTs they are specified as an amount of energy, Eon/off for a certain switching operation.
Eon/off are the energy dissipated at turn-on/turn-off respectively. Using the numerical value is
again the most simple way to determine switching losses. The numerical value can be applied if
the switching operations are carried out at the same or similar conditions as indicated in the data
sheet. Graphs for Eon(IC)/(RG ), Eoff (IC)/(RG) with collector current IC and gate resistance RG are
provided.
The graphs permit the most accurate determination of switching losses, given the parameters of
the converter: RG and converter current IC.

Diode
A surge voltage occurs when the free-wheel diode recovers. Consider a converter leg. The lower
device is off and that the load current is circulating through the free-wheeling diode of the upper
device. Now if the lower device turns on, the current in the free-wheel diode of the upper device
decreases during the overlap period and the load current begins to commutate to the lower
device. It becomes negative during reverse recovery of the upper free-wheel diode. When the
free-wheel diode recovers, the current in the circuit associated to the diode jumps to zero. The
parasitic line inductance Lp develops a surge voltage equal to Lp di/dt in opposition to the
decreasing current. This di/dt is dictated by the recovery characteristic of the free-wheel diode.
Fast recovery “snappy” diodes can develop very high recovery di/dt when they are hard
recovered by the rapid turn-on of a device in series with it in the same converter leg. These
diodes take a smaller time to quench the reverse recovery current compared to a soft recovery
diode.
The off-state losses of the main device and the turn-on dissipation may be neglected for most
cases. With an IGBT driven DC-DC chopper as an example, the dissipation can be estimated as:
IGBT dissipation = Conduction losses + Switching losses

= [ .Vce(sat)Ic] +[fc(Eon + Eoff)] Watts
Diode dissipation = Conduction losses + Reverse recovery losses

= [ (1 -  FVF]+ [fc Err]
where, is the conduction duty ratio, fc the switching frequency and Eon , Eoff , Err are the
respective energy losses, Fig 3.2, data for which is provided by the device manufacturer.
The values of Eon , Eoff , Err are at the rated values only and have to be adjusted to the working
values of voltage (DC bus), VCE (working) and load current, Ic.
Eon / Eoff / Err ( working ) = Eon / Eoff / Err ( working ) • ⎡⎣VCE ( working ) / VCE ( rated ) ⎤⎦
a/b/c
Eon / Eoff / Err ( working ) = Eon / Eoff / Err ⎡⎣ I C / I C ( rated ) ⎤⎦
Where, a, b and c are constants.
The power device in a converter mostly sees an inductive load. A simple circuit illustrating such
a situation is shown in Fig. 3.3. Corresponding ideal waveforms are also indicated. The free-
wheeling diode FWD, across the load is essential for clamping the induced voltages across the
inductance when the device switches off. However, its presence causes the supply voltage, Vs to
appear across the transistor whenever it carries part of the inductor current in overlap mode with
the FWD during both turn-on and turn-off modes. This causes the transistor switching dissipation
to increase.

Fig. 3.3 Typical current and voltage transients during turn-on and turn-
off of a clamped-inductive load and transitions in the V-I plane.
An RCD Switching-aid-network connected across the device reduces turn-off dissipation, Fig.
3.2. The controlled rise of the collector voltage of the transistor aids this process. However, turn-
off energy is accumulated in the SAN, which is ultimately dissipated in the resistor. The RCD
does not also help reduce turn-on dissipation when the reverse recovery current of the diode and
the SAN current add up with the load current with Vs again appearing across the device.
Example 3.1
Derive the expression for the power dissipation during turn-on and turn-off of a transistor
unassisted by a SAN. The supply voltage is Vm, peak load current Im, and tr, toff being the turn on
and turn-off times. Assume idealised waveforms.
Solution
The transition of the swichings in the VC - IC plane is rectangular. The energy dissipated in each
turn-off switching cycle is
t off 1
W = ∫ VT . I T dt = .V .I .t
T 0 2 M M f
If actual waveforms are considered the dissipation is close to about double the above figure.
The dissipation at turn-on is, similarly 1/2. VM.I M.ton.

Fig. 3.4 Current and voltage waveforms at the Main Terminals of the switch with an
R-C-D SAN, and in the associated FWD and SAN diode
Example 3.2
For a transistor carrying a collector current IM and having a turn--off time tf, find the details of a
RCD SAN to restrict the voltage rise at the end of tf to half the supply voltage. Calculate the
corresponding losses in the transistor and in the SAN.
Solution
The action of the SAN in restricting the rise of transistor voltage till the current in it is
extinguished is illustrated in Fig. 3.4.
Since the current is assumed to fall linearly during the period tf, the collector voltage rises as:
2 2
⎛ t ⎞ I .t ⎛ t ⎞
V = V0 ⎜ ⎟ = M f ⎜ ⎟
⎜t ⎟
⎝ f ⎠ 2C ⎜⎝ t f ⎟⎠
Where V0 is the voltage at the capacitor at the end of turn-off time tf.
Thus,
IM t f
V0 =
2C
⎛ t ⎞
i = I M ⎜1 − ⎟
⎜ t ⎟
⎝ f ⎠
The Transistor current can be written as:
The dissipation in the transistor is
2
tf tf I M2 .t f ⎛ t ⎞⎛ t ⎞ I M2 .t 2f 1
WT = ∫ v.idt = ∫ ⎜⎜1 − ⎟⎟ ⎜⎜ ⎟⎟ dt = . Watts
0 0 2C ⎝ t f ⎠⎝ tf ⎠ 2C 12
When the transistor switches off, the nearly constant load current linearly charges up the
capacitor till it reaches the supply voltage. Subsequently, The FWD is positively biased and there

is a short period of over-lap between the FWD and the SAN diode. During this period, the
capacitor over-charges to some extent.
If V0 is the capacitor voltage when the transistor current is extinguished,
t2 1
CV0 = ∫ i.dt = IMt f
t1 2
If this V0 is about 1/2 Vs,
IM t f
C≥
Vs
The energy dissipated in the SAN resistor which is also the energy shifted to the SAN from the
transistor during turn-off is
1
PR =
CVM2 F
2
Where F is the switching frequency. The resistance should be able to limit the transistor current
to its peak rating. Thus,
Vs
R≥
I CM − I M − I rr
Irr is the reverse recovery current of the FWD.

If the capacitor has to discharge completely during the ON time,
I M .t f
C≥
Vs − R.I M
In a Sine-PWM controlled converter with a peak value of the fundamental current equal to Icp,
the conduction losses in the IGBT would be
π ⎡2 2 ⎤
Wc = δ .T ∫ I cVce ( sat ) dθ = 12 δ .T ⎢ I cpVo + I cp2 .R ⎥
⎣ π
0
⎦
Where Vo and R are as shown in Fig 3.1. For the diode the dissipation is
WF =
1
[1 − δ ]. 2 2 I cpVod + I cp2 Rd
2 π

Soft switching
Fig. 3.5 Basic topologies for a) Hard switch, b) Zero-voltage switch

and c) for a Zero current switch
Hard switching and its consequences have been discussed above. Reduction of size and weight
of converter systems require higher operating frequencies, which would reduce sizes of inductors
and capacitors. However, stresses on devices are heavily influenced by the switching frequencies
accompanied by their switching losses. It is obvious that switching-aid-networks do not mitigate
the dissipation issues to a great extent. Turn-on snubbers though not discussed, are rarely used.
Even if used, it would not be able to prevent the energy stored in the junction capacitance to
discharge into the transistor at each turn-on. Soft switching techniques use resonant techniques to
switch ON at zero voltage and to switch OFF at zero current. There are negligible switching
losses in the devices, though there is a significant rise in conduction losses. There is no transfer
of dissipation to the resonant network which is non-dissipative. The two basic configurations are
as shown in Fig. 3.5.

Fig. 3.6 Switching loci for a Hard-Switched converter without Switching-Aid-Networks,
with the SAN and for a Soft-Switched converter operation
The switching trajectory in the voltage-current plane of a device is illustrated in Fig. 3.6
comparing the paths for that of a Hard-switched operation without any SAN, a Hard-switched
with a R-C-D Switching-Aid-Network and a resonant converter. It is indicatve of the stresses and
losses. A designer would prefer the path to be as close as possible to the origin.
A Zero Current Switch based converter is provided as illustration to the soft switching
mechanism. It is equivalent to the topology shown above. The input capacitor and the one across
the diode may be combined to arrive at this topology.
Fig. 3.7 A ZCS resonant buck converter
The ZCS converter is considered to be in stable operation with Load current Itrans flowing through
the diode and the inductor Lf. The Capacitor Cr is charged to Vs. On switching the transistor ON
the current in it ramps up from zero but the diode continues conduction till this current reaches
the load current Iout level. Subsequently, the load current and the resonating current flows
through the transistor. This current reaches a natural zero when the negative magnitude of the
resonating current equals the load current. The transistor thus switches in the Zero Current mode
for both turn on and turn off. The diode, on the other hand switches in the Zero Voltage mode
under both situations. It must be noted that the peak current stress on the transistor is high . The
peak voltage stress on the diode is also about twice the supply voltage. Both these stresses are
significantly higher than that in a comparable Hard switched buck converter. Consequently,

while switching losses are practically eliminated in this resonant converter, conduction losses
increase along with the device stresses. There is no scope of a SANs in resonant switching.
Objective type questions

Qs#1 Which component of power dissipation in a Power Semiconductor device is reduced by
an RCD Switching –Aid –Network?
a) Off state losses
b) Turn-on losses
c) Turn-off losses
d) On-state losses
Ans: c) turn-off losses
Qs#2 Does an RCD SAN reduce total switching losses?
Ans: No. It transfers the losses from the device to itself.
Qs#3 Are resonant converters superior to the hard switched converter on all counts?
Ans: No. The resonant converter reduces switching losses at the cost of higher voltage/current
stresses on the devices.

Module
2
AC to DC Converters
Lesson
9
Single Phase Uncontrolled
Rectifier
Operation and Analysis of single phase uncontrolled rectifiers
• Classify the rectifiers based on their number of phases and the type of devices used.
• Define and calculate the characteristic parameters of the voltage and current waveforms.
• Analyze the operation of single phase uncontrolled half wave and full wave rectifiers
supplying resistive, inductive, capacitive and back emf type loads.
• Calculate the characteristic parameters of the input/output voltage/current waveforms
associated with single phase uncontrolled rectifiers.

9.1 Introduction
One of the first and most widely used application of power electronic devices have been in
rectification. Rectification refers to the process of converting an ac voltage or current source to
dc voltage and current. Rectifiers specially refer to power electronic converters where the
electrical power flows from the ac side to the dc side. In many situations the same converter
circuit may carry electrical power from the dc side to the ac side where upon they are referred to
as inverters. In this lesson and subsequent ones the working principle and analysis of several
commonly used rectifier circuits supplying different types of loads (resistive, inductive,
capacitive, back emf type) will be presented. Points of interest in the analysis will be.
• Waveforms and characteristic values (average, RMS etc) of the rectified voltage and
current.
• Influence of the load type on the rectified voltage and current.
• Harmonic content in the output.
• Voltage and current ratings of the power electronic devices used in the rectifier circuit.
• Reaction of the rectifier circuit upon the ac network, reactive power requirement, power
factor, harmonics etc.
• Rectifier control aspects (for controlled rectifiers only)
In the analysis, following simplifying assumptions will be made.
• The internal impedance of the ac source is zero.

• Power electronic devices used in the rectifier are ideal switches.
The first assumption will be relaxed in a latter module. However, unless specified otherwise, the
second assumption will remain in force.
Rectifiers are used in a large variety of configurations and a method of classifying them
into certain categories (based on common characteristics) will certainly help one to gain
significant insight into their operation. Unfortunately, no consensus exists among experts
regarding the criteria to be used for such classification. For the purpose of this lesson (and
subsequent lessons) the classification shown in Fig 9.1 will be followed.

This Lesson will be concerned with single phase uncontrolled rectifiers.
9.2 Terminologies
Certain terms will be frequently used in this lesson and subsequent lessons while characterizing
different types of rectifiers. Such commonly used terms are defined in this section.
Let “f” be the instantaneous value of any voltage or current associated with a rectifier
circuit, then the following terms, characterizing the properties of “f”, can be defined.
Peak value of f ( f̂ ) : As the name suggests f̂ = f max over all time.
Average (DC) value of f(Fav) : Assuming f to be periodic over the time period T
1 T
Fav = ∫ f(t)dt ……………………………….(9.1)
T 0
RMS (effective) value of f(FRMS) : For f , periodic over the time period T,
1 T 2
T ∫0
FRMS = f (t)dt …………………………..(9.2)
Form factor of f(fFF) : Form factor of ‘f ‘ is defined as

F
f FF = RMS …………………………………. …(9.3)
Fav
Ripple factor of f(fRF) : Ripple factor of f is defined as

2 2
FRMS - Fav 2
f RF = = f FF -1 …………………….(9.4)
Fav

Ripple factor can be used as a measure of the deviation of the output voltage and current of a
rectifier from ideal dc.
( )
Peak to peak ripple of f f̂ pp : By definition
f̂ pp = f max - f min Over period T……………… …(9.5)
Fundamental component of f(F1): It is the RMS value of the sinusoidal component in the
Fourier series expression of f with frequency 1/T.
∴ F1 =
1 2
2
( 2
)
f A1 + f B1 ………………………....(9.6)
2 T
where f A1 = ∫ f ( t ) cos 2π t dt ……………………(9.7)
T 0 T
2 T
f B1 = ∫ f ( t ) sin 2π t dt …………………….(9.8)
T 0 T
Kth harmonic component of f(FK): It is the RMS value of the sinusoidal component in the
Fourier series expression of f with frequency K/T.
∴ FK =
2
(
1 2 2
)
f AK + f BK …………………………(9.9)
2 T
where f AK = ∫ f(t) cos2πK t T dt ………………...(9.10)
T 0
2 T
f BK = ∫ f(t) sin2πK t T dt …………………(9.11)
T 0
Crest factor of f(Cf) : By definition

f̂
Cf = ……………………………………(9.12)
FRMS
Distortion factor of f(DFf) : By definition

F
DFf = 1 …………………………………..(9.13)
FRMS
Total Harmonic Distortion of f(THDf): The amount of distortion in the waveform of f is

quantified by means of the index Total Harmonic Distortion (THD). By definition
2
⎛ Fk ⎞
α
THD f = ∑ ⎜ ⎟ ………………………..(9.14)
K=0 ⎝ F1 ⎠
K ≠1
From which it can be shown that

2
1- DFf
THDf = ……………………………(9.15)
DFf

Displacement Factor of a Rectifier (DPF): If vi and ii are the per phase input voltage and input
current of a rectifier respectively, then the Displacement Factor of a rectifier is defined as.
DPF = cosφi …………………………………(9.16)
Where φi is the phase angle between the fundamental components of vi and ii.
Power factor of a rectifier (PF): As for any other equipment, the definition of the power factor
of a rectifier is
Actual power input to the Rectifier
PF = ….(9.17)
Apparent power input to the Rectifier
if the per phase input voltage and current of a rectifier are vi and ii respectively then
V I cosφi
PF = i1 i1 ………………………………(9.18)
ViRMS IiRMS
If the rectifier is supplied from an ideal sinusoidal voltage source then

Vi1 = ViRMS
I
so, PF = i1 cosφi = DFi1 × DPF ………………..(9.19)
IiRMS
In terms of THDii
DPF
PF = ……………………………...(9.20)
2
1+ THDii
Majority of the rectifiers use either diodes or thyristors (or combination of both) in their
circuits. While designing these components standard manufacturer’s specifications will be
referred to. However, certain terms are used in relation to the rectifier as a system. They are
defined next.
Pulse number of a rectifier (p): Refers to the number of output voltage/current pulses in a
single time period of the input ac supply voltage. Mathematically, pulse number of a rectifier is
given by
Time period of the input supply voltage
p= .
Time period of the minium order harmonic in the output voltage/current.
Classification of rectifiers can also be done in terms of their pulse numbers. Pulse number of a
rectifier is always an integral multiple of the number of input supply phases.
Commutation in a rectifier: Refers to the process of transfer of current from one device (diode
or thyristor) to the other in a rectifier. The device from which the current is transferred is called
the “out going device” and the device to which the current is transferred is called the “incoming
device”. The incoming device turns on at the beginning of commutation while the out going
device turns off at the end of commutation.
Commutation failure: Refers to the situation where the out going device fails to turn off at the
end of commutation and continues to conduct current.
Firing angle of a rectifier (α): Used in connection with a controlled rectifier using thyristors. It
refers to the time interval from the instant a thyristor is forward biased to the instant when a gate
pulse is actually applied to it. This time interval is expressed in radians by multiplying it with

the input supply frequency in rad/sec. It should be noted that different thyristors in a rectifier
circuit may have different firing angles. However, in the steady state operation, they are usually
the same.
Extinction angle of a rectifier (γ): Also used in connection with a controlled rectifier. It refers
to the time interval from the instant when the current through an outgoing thyristor becomes zero
(and a negative voltage applied across it) to the instant when a positive voltage is reapplied. It is
expressed in radians by multiplying the time interval with the input supply frequency (ω) in
rad/sec. The extinction time (γ/ω) should be larger than the turn off time of the thyristor to avoid
commutation failure.
Overlap angle of a rectifier (μ): The commutation process in a practical rectifier is not
instantaneous. During the period of commutation, both the incoming and the outgoing devices
conduct current simultaneously. This period, expressed in radians, is called the overlap angle
“μ” of a rectifier. It is easily verified that α + μ + γ = π radian.
Exercise 9.1
i) In a rectifier, electrical power flows from the _________ side to the ________ side.
ii) Uncontrolled rectifiers employ _________ where as controlled rectifiers employ
________ in their circuits.
iii) For any waveform “Form factor” is always _______ than or equal to unity.
iv) The minimum frequency of the harmonic content in the Fourier series expression of
the output voltage of a rectifier is equal to its _________.
v) “THD” is the specification used to describe the quality of ___________ waveforms
where as “Ripple factor” serves the same purpose for _________ for waveforms.
vi) Input “power factor” of a rectifier is given by the product of the _________ factor
and the ________ factor.
vii) The sum of “firing angle”, “Extinction angle” and “overlap angle” of a controlled
rectifier is always equal to _________.
Answers: (i) ac, dc; (ii) diodes, thyristors; (iii) greater; (iv) pulse number; (v) ac, dc; (vi)
displacement, distortion; (vii) π
9.3 Single phase uncontrolled half wave rectifier

This is the simplest and probably the most widely used rectifier circuit albeit at relatively small
power levels. The output voltage and current of this rectifier are strongly influenced by the type
of the load. In this section, operation of this rectifier with resistive, inductive and capacitive
loads will be discussed.

Fig 9.2 shows the circuit diagram and the waveforms of a single phase uncontrolled half
wave rectifier. If the switch S is closed at at t = 0, the diode D becomes forward biased in the
the interval 0 < ωt ≤ π. If the diode is assumed to be ideal then
For 0 < ωt ≤ π
v0 = vi = √2 Vi sin ωt
vD = vi – v0 = 0 ………………………(9.21)
Since the load is resistive
2V0
i0 = v0 R = sinωt …………………..(9.22)
R
ii = i0
For ωt > π, vi becomes negative and D becomes reverse biased. So in the interval π < ωt ≤ 2π
ii = i0 = 0
v0 = i0R = 0………………………………...(9.23)
vD = vi – v0 = vi = √2 Vi sinωt
From these relationships
1 2π 1 π 2Vi
V0AV =
2π 0∫ v 0 dωt = ∫
2π 0
2Vi sinωtdωt =
π
……….(9.24)
1 π 2 2 V
VDRMS =
2π 0∫ 2Vi sin ωtdωt = i ……………………...(9.25)
2

It is evident from the waveforms of v0 and i0 in Fig 9.2 (b) that they contain significant amount
of harmonics in addition to the dc component. Ripple factor of v0 is given by
2 2
VDRM - VDAV 1 2
v0RF = = π - 4 ………………………… (9.26)
VDAV 2
With a resistive load ripple factor of i0 will also be same.
Because of such high ripple content in the output voltage and current this rectifier is
seldom used with a pure resistive load.
The ripple factor of output current can be reduced to same extent by connecting an
inductor in series with the load resistance as shown in Fig 9.3 (a). As in the previous case, the
diode D is forward biased when the switch S is turned on. at ωt = 0. However, due to the load
inductance i0 increases more slowly. Eventually at ωt = π, v0 becomes zero again. However, i0
is still positive at this point. Therefore, D continues to conduct beyond ωt = π while the negative
supply voltage is supported by the inductor till its current becomes zero at ωt = β. Beyond this
point, D becomes reverse biased. Both v0 and i0 remains zero till the beginning of the next cycle
where upon the same process repeats.
From the preceding discussion

For 0 ≤ ωt ≤ β
vD = 0
v0 = vi
i0 = ii…………………………………………(9.27)
for β ≤ ωt ≤ 2π

v0 = 0
i 0 = ii = 0
vD = vi – v0 = vi
1 2π 1 β
V0AV = ∫
2π 0
v0 dωt = ∫ 2Vsinωtdωt
2π 0 i ………………… (9.28)
or V0AV =
2Vi 1- cosβ
π 2 (
………………………………………... (9.29))
1 β 2 2
2π ∫0 i
V0RMS = 2V sin ωtdωt
( )
2
Vi 1 V 2β - sin2β
= β - sin2β = i ……………………..(9.30)
2π 2 2 2π
Form factor of the voltage waveform is

V 2β - sin2β
vOFF = 0RMS = π ………………………………….(9.31)
V0AV 2π(1- cosβ)
2
The ripple factor.

2 π(2β - sin2β)
v0RF = vOFF -1 = 2
- 1 ………………………………(9.32)
2(1- cosβ)
All these quantities are functions of β which can be found as follows.

For 0 ≤ ωt ≤ β
dio
vi = 2Vsinωt
i =L + Ri0 …………………………………….(9.33)
dt
i0 (ωt = 0) = i0 (ωt = β) = 0
The solution is given by

ωt
-
tanφ 2Vi
i 0 = I0 e + sin(ωt - φ) ……………………………………(9.34)
Z
ωL
where tanφ =
R
2 2 2
and Z = R + ω L ……………………………………………..(9.35)
Putting the initial conditions of (9.33)

2Vi ⎡ ⎤
ωt
-
+ sin ( ωt - φ ) ⎥⎦ ………………………………(9.36)
tanφ
i0 = ⎢⎣sinφe
Z
2Vi ⎡ ⎤
β
-
+ sin ( β - φ ) ⎦⎥ = 0
tanφ
i 0 (ωt = β) = ⎢sinφe
⎣
Z
β
-
= sin ( φ - β ) ………………………………………….(9.37)
tanφ
or sinφe
β as a function of φ can be obtained by solving equation 9.37.

It can be shown that β increases with φ. From Equation (9.29), V0AV decreases with
increasing β while V0RMS increases with β. Therefore, with increasing φ (and hence increasing
L) the form factor and the ripple factor of v0 worsens. However, the ripple factor of i0 decreases
with increasing L. Therefore, in certain applications, where a smooth dc current is of prime
importance (e.g. the field supply of a dc motor) this configuration of the rectifier is preferred.
The problem of poor form factor (ripple factor) of the output voltage can be solved to
some extent by connecting a capacitor across the load resistance of Fig 9.2 (a). This single phase
half wave rectifier supplying a capacitive load is shown in Fig 9.5 (a). Corresponding
waveforms are shown in Fig 9.5 (b).
If the capacitor was initially discharged the diode “D” is forward biased when the switch
S is turned on at ωt = 0. The output voltage follows the input voltage. The diode D carries both
the capacitor charging current and the load current. At ωt = β the sum of these two currents
becomes zero and tends to grow in the negative direction. At this point the diode becomes

reverse biased and disconnects the load (along with the capacitor) from the supply. The
capacitor then discharges with the load current. Diode D does not become forward biased till the
input supply voltage becomes equal to the capacitor voltage in the next cycle at ωt = (2π + φ).
The same process repeats thereafter.
From the preceding discussion

For 2π + φ ≤ ωt ≤ 2π + β
v0 = vi = 2V1sinωt ……………………………………..(9.38)
dv v
ii = i c + i0 = c 0 + 0
dt R
2Vi
or ii = [ ωRCcosωt + sinωt ]
R
1
2Vi ( 2 2 2 2
)
= 1+ ω R C cos(ωt - θ) ……………………..(9.39)
R
-1 1
where θ = tan
ωRC

At ωt = β+ 2π, ii = 0 so β – θ = π/2 or β = θ + π/2
π -1 1
or β = + tan ……………………………………….(9.40)
2 ωRC
Again for β ≤ ωt ≤ 2π + φ
dv v
ii = 0, C 0 + 0 = 0, v 0 ( ωt = β ) = 2Vi cosθ .
dt R
-(ωt-β) tanθ
∴ v 0 = 2Vi cosθ e …………………………………..(9.41)
at ωt = 2π + φ, v0 = 2Vsinφ
i
π
-(2π+φ- -θ) tanθ
2Vi sinϕ = 2Vi cosθ e 2
3π
-( +φ-θ) tanθ
2
or sinφ = cosθ e
⎡ -( -θ) tanθ ⎤ -φ tanθ
3π
or sinφ = ⎣ cosθ e 2 ⎦e ……………………………...(9.42)
From which φ can be solved. Peak to peak ripple in v0 is

v̂ 0pp = 2Vi (1- sinϕ) ………………………………………….(9.43)
As c → α, θ → 0 and β and φ → π/2 and v̂0pp → 0

Therefore, a very large capacitor helps to improve the ripple factor of the output voltage of this
rectifier. However, as indicated by Equation (9.39) the peak current through the diode increases
proportionately. It is also interesting to observe that unlike the previous cases the peak reverse
voltage appearing across D is given by.
v D max = 2Vi + v 0M ≈ 2 2Vi ………………………………(9.44)
This is sometimes referred to as the peak inverse voltage rating (PIV) of the diode.
Exercise 9.2
1. Fill in the blank(s) with the appropriate word(s).
i) The ripple factor of the output voltage and current waveforms of a single phase
uncontrolled half wave rectifier is ____________ than unity.
ii) With an inductive load, the ripple factor of the output __________ of the half wave
rectifier improves but that of the output __________ becomes poorer.
iii) In both single phase half wave and full wave rectifiers the form factor of the output
voltage approaches _________ with capacitive loads provided the capacitance is
________ enough.
iv) The PIV rating of the rectifier diode used in a single phase half wave rectifier
supplying a capacitive load is approximately ________ the __________ input supply
voltage.
v) The % THD of the input current of the rectifiers supplying capacitive loads is
__________.
Answers: (i) greater; (ii) current, voltage; (iii) unity, large; (iv) double, peak; (v) high.

2. An unregulated dc. power supply of average value 12 V and peak to peak ripple of 20% is to
be designed using a single phase half wave rectifier. Find out the required input voltage, the
output capacitance and the diode RMS current and PIV ratings. The equivalent load
resistance is 50 ohms.
Answer: From equation 9.43.

v̂opp = 2Vi (1- sinϕ ) = 0.2×12 = 2.4 V.
∴ Vomax = 2Vi = 12 + 2.4 2 = 13.2V ∴ Vi = 9.33V
o
∴ sin ϕ = 0.818 or ϕ = 54.9 = 0.96 rad.
Then from equation 9.42
-(3 π 2 + ϕ - θ) tanθ
0.818 = cosθ e
(5.67 - θ) tanθ
or 0.818 e = cosθ
D
From which θ ≈ 2.035
1
∴ tan θ = = 0.03553, R = 50Ω, ∴ C = 1790 μF
ωRC
PIV of the diode = 2 2Vi = 26.4V .
ii dωt = i 2 (1+ ω R C )
1 β 2 V 1 92.035 2
∫ 2π ∫54.9o
2 2 2
RMS. Diode current = cos (ωt - θ)dωt
2π ϕ R
1 ⎡β -ϕ 1 1 ⎤
= 7.432 ⎢ + sin2(β - θ) - sin2(ϕ - θ) ⎥ = 0.8564 Amps.
2π ⎣ 2 4 4 ⎦
9.4 Single phase uncontrolled full wave rectifier

Single phase uncontrolled half wave rectifiers suffer from poor output voltage and/or
input current ripple factor. In addition, the input current contains a dc component which may
cause problem (e.g. Transformer saturation etc) in the power supply system. The output dc
voltage is also relatively less. Some of these problems can be addressed using a full wave
rectifier. They use more number of diodes but provide higher average and rms output voltage.
There are two types of full wave uncontrolled rectifiers commonly in use. If a split
power supply is available (e.g. output from a split secondary transformer) only two diode will be
required to produce a full wave rectifier. These are called split secondary rectifiers and are
commonly used as the input stage of a linear dc voltage regulator. However, if no split supply is
available the bridge configuration of the full wave rectifier is used. This is the more commonly
used full wave uncontrolled rectifier configuration. Both these configurations are analyzed next.

9.4.1 Split supply single phase uncontrolled full wave rectifier.

Fig 9.6 shows the circuit diagram and waveforms of a single phase split supply,
uncontrolled full wave rectifier supplying an R – L load. The split power supply can be thought
of to have been obtained from the secondary of a center tapped ideal transformer (i.e. no internal
impedance).
When the switch is closed at the positive going zero crossing of v1 the diode D1 is
forward biased and the load is connected to v1. The currents i0 and ii1 start rising through D1.
When v1 reaches its negative going zero crossing both i0 and ii1 are positive which keeps D1 in
conduction. Therefore, the voltage across D2 is vCB = v2 - v1 . Beyond the negative going zero
crossing of vi, D2 becomes forward biased and the current i0 commutates to D2 from D1. The
load voltage v0 becomes equal to v2 and D1 starts blocking the voltage vAB = v1 - v2 . The current
i0 however continues to increase through D2 till it reaches the steady state level after several
cycles. Steady state waveforms of the variables are shown in Fig 9.6 (b) from ωt = 0 onwards. It
should be noted that the current i0, once started, always remains positive. This mode of operation
of the rectifier is called the “Continuous conduction mode” of operation. This should be
compared with the i0 waveform of Fig 9.3 (b) for the half wave rectifier where i0 remains zero
for some duration of the input supply waveform. This mode is called the “ discontinuous
conduction mode” of operation.
From the above discussion
For 0 ≤ ωt < π
v0 = v1
i0 = ii1……………………………………....(9.45)
for π ≤ ωt < 2π
v0 = v2
i0 = ii2……………………………………........(9.46)
Since v0 is periodic over an interval π

1 π 2Vi π 2 2Vi
V0AV = ∫ v 0 dωt = ∫ sinωtdωt = ……………..(9.47)
π 0 π 0 π
1 π 2 2
π ∫0 i
V0RMS = 2V sin ωt dωt = Vi ………………………........(9.48)
V π
∴ v 0FF = 0RMS = ……………………………………….(9.49)
V0AV 2 2
2
2 π -8
v 0RF = v -1 =
0FF ……………………………………..(9.50)
2 2
Both the form factor and the ripple factor shows considerable improvement over their half wave
counter parts.

The single phase full wave rectifier still does not offer a smooth dc voltage. With
resistive load, considerable ripple current will flow into the load. This problem can be solved by
connecting a capacitor across the load resistance just as in the case of a half wave rectifier.
If the capacitor was initially discharged, the diode D1 is forward biased when the switch S
is turned on at ωt = 0. The diode D2 remains reverse biased. The output voltage follows the
input voltage. D1 carries both the capacitor charging current and the load current. At ωt = β the
sum of these two currents becomes zero and tends to grow in the negative direction. At this
point the diode D1 becomes reverse biased and disconnects the load along with the capacitor
from the supply. The capacitor then discharges through the load until at ωt = π + φ, v2 becomes
greater than v0 and forward biases D2. D1 now remains reverse biased. D2 conducts up to ωt = π
+ β. The same process repeats thereafter.
From the discussion above

For π + φ ≤ ωt ≤ π + β
v0 = v2 = - 2Vsinωt i
dv v
ii2 = i c + i 0 = C 0 + 0 ………………………………………………(9.51)
dt R
2Vi
or ii2 = - [ ωRCcosωt + sinωt ]
R
1
2Vi ( ) 1
1+ ω R C cos ( π + θ - ωt ) where θ = tan
2 2 2 2 -1
= ….(9.52)
R ωRC
π π π -1 1
at ωt = π + β, ii1 = 0 so β - θ = or β = θ + or β = + tan …………(9.53)
2 2 2 ωRC
Again for β ≤ ωt ≤ π + φ
dv v
ii1 = 0 ∴ C 0 + 0 = 0 v0 ( ωt = β ) = 2Vsinβ
i = 2Vi cosθ ……….(9.54)
dt R
-( ωt-β ) tanθ
∴ v 0 = 2Vi cosθ e …………………………………………….(9.55)
at ωt = π + φ, v0 = 2sinφ
( π2 +θ-π-φ)tanθ
2Vsinφ
i = 2Vi cosθ e
- ( π2 +φ-θ )tanθ
or sinφ = cosθ e
⎡ -( -θ ) tanθ ⎤ -φtanθ
π
or sinφ = ⎣cosθ e 2 ⎦e ………………………………………(9.56)
From which φ can be solved. Peak to peak ripple in v0 is

v̂ 0pp = 2Vi (1- sinφ) ………………………………………………….(9.57)
It can be shown that for the same R and C, v̂0pp given by Equation (9.57) is smaller than that
given by Equation (9.43) for the half wave rectifier. The diode PIV ratings remain equal to
2 2Vi however.

Exercise 9.3
i) The output voltage form factor of a single phase full wave rectifier is ___________.
ii) The output voltage of a single phase full wave rectifier supplying an inductive load is
___________ of the load parameters.
iii) The peak to peak output voltage ripple of a single phase split supply full wave
rectifier supplying a capacitive load is ___________ compared to an equivalent half
wave rectifier.
Answers: (i) π ; (ii) independent ; (iii) smaller.

2 2
2. An unregulated dc power supply is built around a single phase split supply full wave rectifier
using the same input voltage and output capacitor found in the problem 2 of Exercise 9.2.
The load resistance is 50 Ω. Find out the average output voltage, the peak to peak ripple in
the output voltage and the RMS current ratings of the diodes.
Answer: From the given data C = 1790 μF, R = 50 Ω, ∴ θ = 2.035°

From equation 9.56
Sin θ = cos θ e-(π/2 + φ – θ) tan θ
-0.03553(1.5353+ϕ ) -0.03553ϕ
Or sin θ = 0.99937 e = 0.946316 e
From which φ = 65.33°
Vi = 9.33 volts.
∴ vˆ opp = 2Vi (1- sinϕ ) = 1.20 volts.
v̂ opp
V0AV = V0Max - = 2Vi - 0.6V = 13.2 - 0.6V = 12.6V .
2
∴ % ripple = 9.5%
ii dωt = i 2 (1+ ω R C )
1 π 2+θ 2 V 1 β
∫ ∫
2 2 2 2
RMS diode current = cos (ωt - θ)dωt
2π ϕ R 2π ϕ
1 ⎡β -ϕ 1 ⎤
= 7.432 ⎢ - sin2(ϕ - θ) ⎥ = 0.533 Amps.
2π ⎣ 2 4 ⎦

9.4.2 Single phase uncontrolled full bridge rectifier

The split supply full wave single phase rectifier offers as good performance as possible from a
single phase rectifier in terms of the output voltage form factor and ripple factor. They have a
few disadvantages however. These are
• They require a split power supply which is not always available.

• Each half of the split power supply carries current for only one half cycle. Hence they are
underutilized.

• The ratio of the required diode PIV to the average out put voltage is rather high.
These problems can be mitigated by using a single phase full bridge rectifier as shown in Fig 9.8
(a). This is one of the most popular rectifier configuration and are used widely for applications
requiring dc. power output from a few hundred watts to several kilo watts. Fig 9.8 (a) shows the
rectifier supplying an R-L-E type load which may represent a dc. motor or a storage battery.
These rectifiers are also very widely used with capacitive loads particularly as the front end of a
variable frequency voltage source inverter. However, in this section analysis of this rectifier
supplying an R-L-E load will be presented. Its operation with a capacitive load is very similar to
that of a split supply rectifier and is left as an exercise.
When the switch S is turned on at the positive going zero crossing of vi no current flows in the
circuit till vi crosses E at point A. Beyond this point, D1 & D2 are forward biased by vi and
current starts increasing through them till the point B. After point B, vi falls below E and io starts
decreasing. Now depending on the values of R, L & E one of the following situations may arise.
• io may become zero before the negative going zero crossing of vi at point C.
• io may continue to flow beyond C and become zero before the point D.
• io may still be non zero at point D.
It should be noted that if io >0 either D1D2 or D3D4 must conduct. Fig 9.4 (b) shows the
waveforms for the third situation.
If io >0 at point C the negative going input voltage reverse biases D1 & D2. Current io
commutates to D3 and D4 as shown in the associated “conduction Diagram” in Fig 9.8 (b). It
shows pictorially the conduction interval of different devices. The current io continues to
decrease up to the point D beyond which it again increases. It should be noted that in this mode
of conduction io always remain greater than zero. Consequently, this is called the continuous
conduction mode of operation of the rectifier. In the other two situations the mode of operation
will be discontinuous.
The steady state waveforms of the rectifier under continuous conduction mode is shown to the
right of the point ωt = 0 in Fig 9.4 (b).
From this figure and preceding discussion

For 0 < ωt ≤ π
vo = vi = 2Vi sin ωt (9.58)
ii = io
for π < ωt ≤ 2π
v o = - vi = - 2Vi sin ωt (9.59)
ii = - io
1 π 2 2
∴ VoAV = ∫
π o
2Vi 2sin ωt d ωt =
π
Vi (9.60)
1 π
π ∫o i
VoRMS = 2V 2 sin 2 ωt d ωt = Vi (9.61)

VoRMS π
∴ v OFF = =
VoAV 2 2
2 π2 - 8
v oRF = v OFF -1 = (9.62)
2 2
Finding out the characterizing quantities for ii will be difficult owing to its complicated
waveform. Considerable, simplification is achieved (without significant loss of accuracy) by
replacing the actual io waveform by its average value IoAV = VoAV / R.
Fig 9.9 shows the approximate input current wave form and its fundamental component.
From Fig 9.9

Displacement angle φi = 0
∴ Input displacement factor (DPF) = cos ϕi = 1 (9.63)
I 2 2
Distortion factor (DFil) = il = (9.64)
IoAV π
2 2
Power Factor (PF) = DPF × DFil = (9.65)
π
1 - DFii 2 π2 - 8
% TH Dii = 100 × = 100 × (9.66)
DFii 2 2 2

The exact analytical expression for io (and hence ii) can be obtained as follows.
for 0 < ωt ≤ π
Ldi o
vi = 2Vi sin ωt = Ri o + +E (9.67)
dt
io ωt=0 = io ωt=π (steady state periodic boundary cond.)
The general solution can be written as

- ωt 2Vi ⎡ sinθ ⎤
i o = Io e tanϕ + ⎢ sin ( ωt - ϕ ) - (9.68)
Z ⎣ cosϕ ⎥⎦
ωL E
where tanϕ = ; Z = R 2 + ω2 L2 ; sin θ =
R 2Vi
From the boundary condition

2Vi ⎡ sinθ ⎤ - tanπϕ 2Vi ⎡ sinθ ⎤
Io - sin ϕ + = I e + sin ϕ -
Z ⎢⎣ cosϕ ⎥⎦ o
Z ⎢⎣ cosϕ ⎥⎦
2Vi 2 sinϕ
Io = (9.69)
Z -π
1 - e tanϕ
2 Vi ⎡ 2 sinϕ ωt
- tan sinθ ⎤
∴ io = ⎢⎣1 - e tanϕ e ϕ
+ sin ( ωt - ϕ ) - (9.70)
Z - π
cosϕ ⎥⎦
From which the condition for continuous conduction can be obtained.
for continuous conduction io ≥ 0 for all 0 < ω t ≤ π

hence io Min ≥ 0 or io ωt=θ ≥ 0
∴ Condition for continuous conduction is
2 sinϕ - θ tanϕ sin θ
e = sin (ϕ - θ ) + (9.71)
1- e
-π tanϕ
cos ϕ
If the parameters of the load (i.e, R, L &E) are such that the left hand side of equation 9.71 is less
than the right hand side conduction of the rectifier becomes discontinuous i.e, the load current
becomes zero for a part of the input cycle. Discontinuous conduction mode of operation of this
rectifier is discussed next.

Fig. 9.10(b) shows the waveforms of different variables under discontinuous conduction mode of
operation. In this mode of operation D1 D2 are not forward biased till vi exceed E at ωt = θ.
Consequently, no current flows into the load till this time. After ωt = θ, the load is connected to
the input source through D1 D2 and io starts building up. Beyond ωt = π - θ, io starts decreasing
and becomes zero at ωt = β < π. D1 D2 are reverse biased at this point. D3 D4 are forward biased
at ωt = π + θ when io starts increasing again. Thus none of the diodes conduct during the interval
β < ω + ≤ π + θ and io remains zero during this period.
Form the preceding discussion

for θ < ωt ≤ β < π
vo = vi = 2Vi sin ωt (9.72)
ii = i o
for π < π + θ < ω + ≤ π + β < 2π

v o = - vi = - 2Vi sin ωt
ii = - io (9.73)
vo = E
ii = i o = 0 other wise (9.74)
1 1 ⎡ β
2Vi sin ωt + ∫ E d ωt ⎤
π+θ π+θ
VoAV =
π ∫
θ
vo d ωt = ∫
π ⎣ θ β ⎦
2Vi
OR VoAV = [ cos θ - cos β + ( π + θ - β ) sin θ ] (9.75)
π
β can be found in the following manner

for θ < ωt ≤ β
Ldi o
v = 2 sin ωt = R i o + +E (9.76)
dt
i o ωt =θ = io ωt=β = 0
The general solution is

ωt-θ
- tan 2Vi ⎡ sin θ ⎤
i o = Io e ϕ
+ ⎢ sin ( ωt - φ ) - (9.77)
Z ⎣ cos ϕ ⎥⎦
where tanϕ = ωL , Z = R 2 + ω2 L2 , sinθ = E
R 2Vi
From the initial condition io ωt=θ = 0
2Vi ⎡sin (ϕ - θ ) + sinθ ⎤
Io = (9.78)
Z ⎢⎣ cosϕ ⎥⎦
∴ io =
2Vi
Z
⎡sin ϕ - θ e- tanωt-θϕ - sinθ 1- e -ωt-θ
⎢⎣ ( )
cosϕ
tanϕ
( )
+ sin ( ωt - ϕ ) ⎤⎥
⎦
(9.79)
Putting i o ωt = β = 0 in Equation 9.79.

sinθ ⎡
1 - e tanϕ ⎤ - sin (ϕ - θ ) e
θ-β θ-β
sin ( β - ϕ ) = tanϕ
(9.80)
cosϕ ⎣⎢ ⎦⎥
Form which β can be solved.
Exercise 9.4
i) The average output voltage of a full wave bridge rectifier and a split supply full wave
rectifier are __________ provided the input voltages are ___________.

ii) For the same input voltage the bridge rectifier uses ___________ the number of
diodes used in a split supply rectifier with _________ the PIV rating.
iii) For continuous conduction, the load impedance of a bridge rectifier should be
__________.
iv) In the ___________ conduction mode the output voltage of a bridge rectifier is
__________ of load parameters.
Answers: (i) equal, equal; (ii) double, half; (iii) inductive; (iv) continuous, independent.
2. A battery is to be charged using a full bridge single phase uncontrolled rectifier. On full
discharge the battery voltage is 10.2 V. and on full charge it is 12.7 volts. The battery
internal resistance is 0.1Ω. Find out the input voltage to the rectifier so that the battery
charging current under full charge condition is 10% of the charging current under fully
discharged condition. Assume continuous conduction under all charging condition and find
out the inductance to be connected in series with the battery for this condition.
Answer: Let the rectifier input voltage be Vi and the charging current under fully discharged
condition be I.
Then assuming continuous conduction
2 2Vi 2 2
- 0.1I = 10.2 and V - 0.01I = 12.7
π π i
∴ 0.09I = 2.5 V ∴ I = 27.78 Amps and Vi = 14.415 volts.
If conduction is continuous at full charge condition it will be continuous for all other
charging conditions.
For continuous conduction
2sinϕ -θ tanϕ sinθ
e = sin(ϕ - θ) +
1- e
-π tanϕ
cosϕ
E
From given data sinθ = = 0.623, θ = 38.535°
2Vi
From which φ = 86.5°
∴ tan ϕ = ωL = 16.35 or ωL = 1.635 ohms
R
∴ L = 5.2 mH.
References
[1] P.C. Sen, “Power Electronics”, Tata McGraw –Hill Publishing Company Limited. 1995
[2] Muhammad H. Rashid, “Power Electronics, circuits, Devices and applications” Prentice –
Hall of India Private Limited, Second Edition, 1994

Module Summary
• A rectifier is a power electronic converter which converts ac voltage or current sources to
dc voltage and current.
• In a rectifier, electrical power flows from the ac input to the dc output.
• In many rectifier circuits, power can also flow from the dc side to the ac side, where
upon, the rectifier is said to be operating in the “inverter mode”.
• Rectifiers can be classified based on the type of device they use, the converter circuit
topology, number of phases and the control mechanism.
• All rectifiers produce unwanted harmonies both at the out put and the input. Performance
of a rectifier is judged by the relative magnitudes of these harmonies with respect to the
desired output.
• For a given input voltage and load, the output voltage (current) of an uncontrolled
rectifier can not be varied. However, the output voltage may vary considerably with load.
• Single phase uncontrolled half wave rectifier with resistive or inductive load have low
average output voltage, high from factor and poor ripple factor of the output voltage
waveform.
• Single phase uncontrolled full wave rectifier have higher average output voltage and
improved ripple factor compared to a half wave rectifier with resistive and inductive load.
• With highly inductive load the output voltage waveform of a full wave rectifier may be
independent of the load parameters.
• With a capacitive load the output voltage form factor approaches unity with increasing
capacitance value for both the half wave and the full wave rectifiers. However, THD of
the input current also increases.
• A full wave bridge rectifier generates higher average dc voltage compared to a split
supply full wave rectifier. However it also uses more number of diodes.


Q1. What will be the load voltage and current waveform when a single phase half wave
uncontrolled rectifier supplies a purely inductive load? Explain your answer with
waveforms.
Q2. The split supply of a single phase full wave rectifier is obtained from a single phase
transformer with a single primary and a center tapped secondary. The rectifier supplies a
purely resistive load. Assuming the transformer to be ideal find out the, displacement
factor, distortion factor and the power factor at the primary side of the transformer.
Q3. A single phase split supply full wave rectifier is designed to supply an inductive load.
The average load current is 20 A, and the ripple current is negligible. Can the same
rectifier be used with a capacitive load drawing the same 20 Amps average current?
Justify your answer.
Q4. A 200V, 15 Amps, 1500 rpm separately excited dc motor has an armature resistance of 1
Ω and inductance of 50 mH. The motor is supplied from a single phase full wave bridge
rectifier with input voltage of 230 V, 50 HZ. Neglecting all no load losses, find out the
no load speed of the machine. Also find out the torque and speed at the boundary
between continuous and discontinuous conduction.

Answer 1
Without loss of generality it can be assumed that S is turned ON at ωt = 0. Since, if it is turned

ON anytime after ωt = 0, the volt-sec. across the inductor will dictate that the current through it
becomes zero before the next positive going zero crossing of vi .
In the region 0 ≤ ωt < π

D is forward biased and v0 = vi
di
∴ L 0 = 2Vsinωt i i 0 (0) = 0
dt
di i0
or ωL 0 = 2Vsinωt =0
dωt i ωt = 0
2Vi 2Vi
∴ i 0 = I0 - cosωt I0 =
ωL ωL
2Vi
∴ i0 = (1- cosωt)
ωL
2 2Vi
at ωt = π, i0 = >0
ωL
∴ D conducts beyond ωt = π until i0 is zero again.
Let the extinction angle be ωt = β > π.
Then for 0 ≤ ωt ≤ β
2Vi
` i0 = (1- cosωt)
ωL
i0 2Vi
= (1- cosβ) for π ≤ β ≤ 2π the only solution is β = 2π
ωt = β ωL

2Vi
∴ v0 = vi for 0 ≤ ωt ≤ 2π and i0 = (1- cosωt) 0 ≤ ωt ≤ 2π
ωL
Answer 2
Figure shows the secondary voltage and current waveforms of the rectifier.
From the given data

N
vS1 = S 2VP sinωt
NP
N V
iS1 = S 2 P sinωt for 0 ≤ ωt ≤ π
NP R
iS1 = 0 otherwise.
N
vS2 = - S 2VP sinωt
NP
N V
iS2 = - S 2 P sinωt for π ≤ ωt ≤ 2π
NP R
iS2 = 0 otherwise
From the MMF balance of an ideal transformer

N Pi P - NSiS1 + NSiS2 = 0
NS 2VP
or iP = (iS1 - iS2 ) = sinωt
NP ⎛ NP ⎞
2
⎜N ⎟ R
⎝ S⎠
∴ At the input
Displacement factor = Distortion factor = Power factor = 1.0

Answer 3
If the load current is 20A with negligible ripple. The required RMS current rating of the rectifier
diode, with reference to Fig 9.6 (b) will be
I D1RMS = I D2RMS = 20 Amps .
2
However from Fig 9.7 (b) and Problem 2 of Exercise 9.3 the required RMS current for a
capacitive load will be much larger than 20 Amps. Therefore the same rectifier can not be used.
Answer 4
Since all no load losses are neglected the developed power at no load and hence the no load
torque will be zero. Therefore, the average armature current will also be zero. However, since a
diode rectifier can not conduct instantaneous negative load current, zero average current will
imply that the instantaneous value of the armature current at all time will be zero at no load.With
reference to Fig 9.10 this condition will require the rectifier diodes to remain reverse biased at all
time. Hence at no load
E ≥ 2Vi
However E will not exceed 2Vi , since once ia becomes zero when E = 2Vi there will be no
developed torque to accelerate the motor. Hence the motor speed and E will not increase any
further.
Thus at no load E = 2Vi = 325.27 volts .
Under the rated condition at 1500 rpm
Erated = 200 – 15 × 1.0 = 185 volts.
E N
Now =
E rated N rated
E 325.27
∴ N = N rated × = 1500× = 2637 rpm .
E rated 185
At the boundary between the continuous and discontinuous mode of conduction.
2sinφ -θ tanφ sinθ
e = sin(φ - θ) +
1- e
-π tanφ
cosφ
2sinφ
= [ cosϕ sin(φ - θ) + sinθ ] e
θ tanφ
or -π tanφ
1- e
-3
ωL 100π ×50×10
where tanφ = = = 15.708
R 1
cosφ = 0.0635 φ = 1.507 rad. and sin2φ = 0.1268
∴ 0.6995 = [ 0.0635 sin(1.507 - θ) + sinθ ] e

0.06366 θ
-1 E o
from which θ = sin = 38.5 ∴ E = 202.48 V
2Vi
but E at 1500 RPM = 185 volts.
∴ Speed at the junction of continuous and discontinuous condition is
202.48
1500 × = 1642 RPM.
185

⎛ 2 2Vi ⎞
Average armature current is ⎜ ⎟ R = 4.593 Amps.
⎝ π ⎠
4.593
∴ Torque = ×100 = 30.62% of rated torque.
15

Module
2
AC to DC Converters
Lesson
10
Single Phase Fully
Controlled Rectifier
Operation and Analysis of single phase fully controlled converter.
• Differentiate between the constructional and operation features of uncontrolled and

controlled converters
• Draw the waveforms and calculate their average and RMS values of different variables
associated with a single phase fully controlled half wave converter.
• Explain the operating principle of a single phase fully controlled bridge converter.
• Identify the mode of operation of the converter (continuous or discontinuous) for a given
load parameters and firing angle.
• Analyze the converter operation in both continuous and discontinuous conduction mode
and there by find out the average and RMS values of input/output, voltage/currents.
• Explain the operation of the converter in the inverter mode.

10.1 Introduction
Single phase uncontrolled rectifiers are extensively used in a number of power electronic based
converters. In most cases they are used to provide an intermediate unregulated dc voltage source
which is further processed to obtain a regulated dc or ac output. They have, in general, been
proved to be efficient and robust power stages. However, they suffer from a few disadvantages.
The main among them is their inability to control the output dc voltage / current magnitude when
the input ac voltage and load parameters remain fixed. They are also unidirectional in the sense
that they allow electrical power to flow from the ac side to the dc side only. These two
disadvantages are the direct consequences of using power diodes in these converters which can
block voltage only in one direction. As will be shown in this module, these two disadvantages
are overcome if the diodes are replaced by thyristors, the resulting converters are called fully
controlled converters.
Thyristors are semicontrolled devices which can be turned ON by applying a current pulse at its
gate terminal at a desired instance. However, they cannot be turned off from the gate terminals.
Therefore, the fully controlled converter continues to exhibit load dependent output voltage /
current waveforms as in the case of their uncontrolled counterpart. However, since the thyristor
can block forward voltage, the output voltage / current magnitude can be controlled by
controlling the turn on instants of the thyristors. Working principle of thyristors based single
phase fully controlled converters will be explained first in the case of a single thyristor halfwave
rectifier circuit supplying an R or R-L load. However, such converters are rarely used in
practice.
Full bridge is the most popular configuration used with single phase fully controlled rectifiers.
Analysis and performance of this rectifier supplying an R-L-E load (which may represent a dc
motor) will be studied in detail in this lesson.

10.2 Single phase fully controlled halfwave rectifier
10.2.1 Resistive load
Fig.10. 1(a) shows the circuit diagram of a single phase fully controlled halfwave rectifier
supplying a purely resistive load. At ωt = 0 when the input supply voltage becomes positive the
thyristor T becomes forward biased. However, unlike a diode, it does not turn ON till a gate
pulse is applied at ωt = α. During the period 0 < ωt ≤ α, the thyristor blocks the supply voltage
and the load voltage remains zero as shown in fig 10.1(b). Consequently, no load current flows
during this interval. As soon as a gate pulse is applied to the thyristor at ωt = α it turns ON. The
voltage across the thyristor collapses to almost zero and the full supply voltage appears across
the load. From this point onwards the load voltage follows the supply voltage. The load being
purely resistive the load current io is proportional to the load voltage. At ωt = π as the supply
voltage passes through the negative going zero crossing the load voltage and hence the load
current becomes zero and tries to reverse direction. In the process the thyristor undergoes reverse
recovery and starts blocking the negative supply voltage. Therefore, the load voltage and the load
current remains clamped at zero till the thyristor is fired again at ωt = 2π + α. The same process
repeats there after.
From the discussion above and Fig 10.1 (b) one can write
For α < ωt ≤ π
v 0 = vi = 2 Vi sinωt (10.1)
v0 V
i0 = = 2 i sinωt (10.2)
R R

v0 = i0 = 0 otherwise.
1 2π 1 π
2π ∫0 2π ∫α
Therefore VOAV = v 0 dωt = 2 Vi sinωt dωt (10.3)
V
Or VOAV = i (1+ cosα) (10.4)
2π
1 2π 2
2π ∫0
VORMS = v0 dωt (10.5)
1 π 2 2
2π ∫α
= 2vi sin ωtdωt
Vi2 π
=
2π ∫α
(1- cos2ωt)dωt
Vi2 ⎡ sin2α ⎤
= ⎢⎣ π - α + 2 ⎥⎦
2π
1
V
= i ⎛⎜ 1- +
α sin2α ⎞ 2
⎟
2⎝ π 2π ⎠
1
π ⎛⎜ 1- +
α sin2α ⎞ 2
VORMS ⎟
= ⎝ π
∴ 2π ⎠ (10.6)
FFVO =
VOAV (1+ cosα)
Similar calculation can be done for i0. In particulars for pure resistive loads FFio = FFvo.
10.2.2 Resistive-Inductive load

Fig 10.2 (a) and (b) shows the circuit diagram and the waveforms of a single phase fully
controlled halfwave rectifier supplying a resistive inductive load. Although this circuit is hardly
used in practice its analysis does provide useful insight into the operation of fully controlled
rectifiers which will help to appreciate the operation of single phase bridge converters to be
discussed later.

As in the case of a resistive load, the thyristor T becomes forward biased when the supply
voltage becomes positive at ωt = 0. However, it does not start conduction until a gate pulse is
applied at ωt = α. As the thyristor turns ON at ωt = α the input voltage appears across the load
and the load current starts building up. However, unlike a resistive load, the load current does
not become zero at ωt = π, instead it continues to flow through the thyristor and the negative
supply voltage appears across the load forcing the load current to decrease. Finally, at ωt = β (β
> π) the load current becomes zero and the thyristor undergoes reverse recovery. From this point
onwards the thyristor starts blocking the supply voltage and the load voltage remains zero until
the thyristor is turned ON again in the next cycle. It is to be noted that the value of β depends on
the load parameters. Therefore, unlike the resistive load the average and RMS output voltage
depends on the load parameters. Since the thyristors does not conduct over the entire input
supply cycle this mode of operation is called the “discontinuous conduction mode”.
From above discussion one can write.

For α ≤ ωt ≤ β
v 0 = vi = 2 Vi sinωt (10.7)
v0 = 0 otherwise
1 2π
2π ∫0
Therefore VOAV = v0 dωt (10.8)
1 β
2π ∫α
= 2 Vi sinωt dωt

Vi
= (cosα - cosβ)
2π
1 2π 2
2π ∫0
VORMS = v0 dωt (10.9)
1 β 2 2
2π ∫α
= 2vi sin ωt dωt
1
V β - α sin2α - sin2β ⎞ 2
= i ⎛⎜ + ⎟
2⎝ π 2π ⎠
V Vi
I OAV = OAV = (cosα - cosβ) (10.10)
R 2πR
Since the average voltage drop across the inductor is zero.
However, IORMS can not be obtained from VORMS directly. For that a closed from expression for i0
will be required. The value of β in terms of the circuit parameters can also be found from the
expression of i0.
For α ≤ ωt ≤ β
di
Rio + L o = v0 = 2Vi sinωt (10.11)
dt
The general solution of which is given by
(ωt-α)
- 2Vi
i 0 = I0 e tanϕ + sin(ωt - ϕ) (10.12)
Z
ωL
Where tanφ = and Z = R 2 + ω2 L2
R
i0 ωt =α
=0
2Vi
∴ 0 = I0 + sin(α - φ)
Z
2Vi ⎡ ( ωt-α )
⎤
∴ i0 = -
(10.13)
Z ⎢
⎣ sin(φ - α)e tanφ
+ sin(ωt - φ) ⎥⎦
i0 = 0 otherwise.
Equation (10.13) can be used to find out IORMS. To find out β it is noted that
i0 ωt=β = 0
α-β
∴ sin(φ - α)e tanφ

= sin(φ - β) (10.14)
Equation (10.14) can be solved to find out β
Exercise 10.1
Fill in the blank(s) with appropriate word(s)

i) In a single phase fully controlled converter the _________ of an uncontrolled converters
are replaced by ____________.
ii) In a fully controlled converter the load voltage is controlled by controlling the _________
of the converter.
iii) A single phase half wave controlled converter always operates in the ________
conduction mode.
iv) The voltage form factor of a single phase fully controlled half wave converter with a
resistive inductive load is _________ compared to the same converter with a resistive
load.
v) The load current form factor of a single phase fully controlled half wave converter with a
resistive inductive load is _________ compared to the same converter with a resistive
load.
Answers: (i) diodes, thyristors; (ii) firing angle; (iii) discontinuous (iv) poorer; (v) better.
2) Explain qualitatively, what will happen if a free-wheeling diode(cathode of the diode

shorted with the cathode of the thyristor) is connected across the load in Fig 10.2.(a)
Answer: Referring to Fig 10.2(b), the free wheeling diode will remain off till ωt = π since the
positive load voltage across the load will reverse bias the diode. However, beyond this point as
the load voltage tends to become negative the free wheeling diode comes into conduction. The
load voltage is clamped to zero there after. As a result
i) Average load voltage increases
ii) RMS load voltage reduces and hence the load voltage form factor reduces.
iii) Conduction angle of load current increases as does its average value. The load
current ripple factor reduces.

10.3 Single phase fully controlled bridge converter
Fig 10.3 (a) shows the circuit diagram of a single phase fully controlled bridge converter. It is
one of the most popular converter circuits and is widely used in the speed control of separately
excited dc machines. Indeed, the R–L–E load shown in this figure may represent the electrical
equivalent circuit of a separately excited dc motor.
The single phase fully controlled bridge converter is obtained by replacing all the diode
of the corresponding uncontrolled converter by thyristors. Thyristors T1 and T2 are fired together
while T3 and T4 are fired 180º after T1 and T2. From the circuit diagram of Fig 10.3(a) it is clear
that for any load current to flow at least one thyristor from the top group (T1, T3) and one
thyristor from the bottom group (T2, T4) must conduct. It can also be argued that neither T1T3
nor T2T4 can conduct simultaneously. For example whenever T3 and T4 are in the forward
blocking state and a gate pulse is applied to them, they turn ON and at the same time a negative
voltage is applied across T1 and T2 commutating them immediately. Similar argument holds for
T1 and T2.
For the same reason T1T4 or T2T3 can not conduct simultaneously. Therefore, the only
possible conduction modes when the current i0 can flow are T1T2 and T3T4. Of coarse it is
possible that at a given moment none of the thyristors conduct. This situation will typically
occur when the load current becomes zero in between the firings of T1T2 and T3T4. Once the
load current becomes zero all thyristors remain off. In this mode the load current remains zero.
Consequently the converter is said to be operating in the discontinuous conduction mode.
Fig 10.3(b) shows the voltage across different devices and the dc output voltage during
each of these conduction modes. It is to be noted that whenever T1 and T2 conducts, the voltage
across T3 and T4 becomes –vi. Therefore T3 and T4 can be fired only when vi is negative i.e, over
the negative half cycle of the input supply voltage. Similarly T1 and T2 can be fired only over
the positive half cycle of the input supply. The voltage across the devices when none of the
thyristors conduct depends on the off state impedance of each device. The values listed in Fig
10.3 (b) assume identical devices.
Under normal operating condition of the converter the load current may or may not
remain zero over some interval of the input voltage cycle. If i0 is always greater than zero then
the converter is said to be operating in the continuous conduction mode. In this mode of
operation of the converter T1T2 and T3T4 conducts for alternate half cycle of the input supply.
However, in the discontinuous conduction mode none of the thyristors conduct over some
portion of the input cycle. The load current remains zero during that period.
10.3.1 Operation in the continuous conduction mode

As has been explained earlier in the continuous conduction mode of operation i0 never becomes
zero, therefore, either T1T2 or T3T4 conducts. Fig 10.4 shows the waveforms of different
variables in the steady state. The firing angle of the converter is α. The angle θ is given by
E
sinθ = (10.15)
2V1
It is assumed that at t = 0- T3T4 was conducting. As T1T2 are fired at ωt = α they turn on
commutating T3T4 immediately. T3T4 are again fired at ωt = π + α. Till this point T1T2
conducts. The period of conduction of different thyristors are pictorially depicted in the second
waveform (also called the conduction diagram) of Fig 10.4.

The dc link voltage waveform shown next follows from this conduction diagram and the
conduction table shown in Fig 10.3(b). It is observed that the emf source E is greater than the dc
link voltage till ωt = α. Therefore, the load current i0 continues to fall till this point. However,
as T1T2 are fired at this point v0 becomes greater than E and i0 starts increasing through R-L and
E. At ωt = π – θ v0 again equals E. Depending upon the load circuit parameters io reaches its
maximum at around this point and starts falling afterwards. Continuous conduction mode will be
possible only if i0 remains greater than zero till T3T4 are fired at ωt = π + α where upon the same
process repeats. The resulting i0 waveform is shown below v0. The input ac current waveform ii
is obtained from i0 by noting that whenever T1T2 conducts ii = i0 and ii = - i0 whenever T3T4
conducts. The last waveform shows the typical voltage waveform across the thyristor T1. It is to
be noted that when the thyristor turns off at ωt = π + α a negative voltage is applied across it for a
duration of π – α. The thyristor must turn off during this interval for successful operation of the
converter.
It is noted that the dc voltage waveform is periodic over half the input cycle. Therefore,
it can be expressed in a Fourier series as follows.
α
v 0 = VOAV + ∑ [ v an cos2nωt + v bn sin2nωt ] (10.16)
n =1
1 π+α 2 2
Where VOAV =
π ∫α
v 0 dωt =
π
Vi cosα (10.17)
2 π 2 2 ⎡ cos(2n +1)α cos(2n -1)α ⎤

v an = ∫ v 0 cos2nωt dωt = Vi ⎢ - (10.18)
π 0 π ⎣ 2n +1 2n -1 ⎥⎦
2 π 2 2 ⎡ sin(2n +1)α sin(2n -1)α ⎤
v bn =
π ∫0
v 0 sin2nωt dωt =
π
Vi ⎢
⎣ 2n +1
-
2n -1 ⎥⎦
(10.19)
Therefore the RMS value of the nth harmonic

1 2
VOnRMS = v an + v 2bn (10.20)
2
RMS value of v0 can of course be completed directly from.

1 π+α 2
π ∫α
VORMS = v0 dωt = Vi (10.21)
Fourier series expression of v0 is important because it provides a simple method of estimating

individual and total RMS harmonic current injected into the load as follows:
The impedance offered by the load at nth harmonic frequency is given by

Z n = R 2 + (2nωL) 2 (10.22)
1
VonRMS ⎡ α 2 ⎤ 2
IonRMS = ; IOHRMS = ⎢ ∑ IonRMS ⎥ (10.23)
Zn ⎣ n =1 ⎦
From (10.18) – (10.23) it can be argued that in an inductive circuit IonRMS → 0 as fast as 1/n2. So
in practice it will be sufficient to consider only first few harmonics to obtain a reasonably
accurate estimate of IOHRMS form equation 10.23. This method will be useful, for example, while
calculating the required current derating of a dc motor to be used with such a converter.

However to obtain the current rating of the device to be used it is necessary to find out a
closed form expression of i0. This will also help to establish the condition under which the
converter will operate in the continuous conduction mode.
To begin with we observe that the voltage waveform and hence the current waveform is
periodic over an interval π. Therefore, finding out an expression for i0 over any interval of
length π will be sufficient. We choose the interval α ≤ ωt ≤ π + α.
In this interval
di0
L + Ri 0 + E = 2Vi sinωt (10.24)
dt
The general solution of which is given by
( )
- ωt-α ⎡ 2Vi sinθ ⎤
tanφ
i 0 = Ie ⎢sin(ωt - φ) - cosφ ⎥
+
Z
(10.25)
⎣ ⎦
ωL
Where, Z = R 2 + ω2 L2 ; tanφ = ; E = 2Vi sinθ; R = Zcosφ
R
Now at steady state i 0 ωt=α = i0 ωt =π+α since i0 is periodic over the chosen interval. Using this
boundary condition we obtain
2Vi ⎡ 2sin(φ - α) e- tanφ + sin(ωt - φ) - sinθ ⎤
( ωt-α )
i0 = ⎢ π ⎥ (10.26)
Z ⎢ - cosφ ⎥
⎣ 1- e tanφ ⎦
The input current ii is related to i0 as follows:

ii = i 0 for α ≤ ωt ≤ π + α (10.27)
ii = - i0 otherwise.
Fig 10.5 shows the waveform of ii in relation to the vi waveform.

It will be of interest to find out a Fourier series expression of ii. However, using actual
expression for ii will lead to exceedingly complex calculation. Significant simplification can be
made by replacing i0 with its average value I0. This will be justified provided the load is highly
inductive and the ripple on i0 is negligible compared to I0. Under this assumption the idealized
waveform of ii becomes a square wave with transitions at ωt = α and ωt = α + π as shown in Fig
10.5. ii1 is the fundamental component of this idealized ii.
Evidently the input current displacement factor defined as the cosine of the angle
between input voltage (vi) and the fundamental component of input current (ii1) waveforms is
cosα (lagging).
It can be shown that

2 2
Ii1RMS = I0 (10.28)
π

and IiRMS = I0 (10.29)
Ii1RMS 2 2
Therefore the input current distortion factor = = (10.30)
IiRMS π
Actual Power VI cosα
The input power factor = = i i1RMS
Apparent Power Vi IiRMS
2 2
= cosα (lagging) (10.31)
π
Therefore, the rectifier appears as a lagging power factor load to the input ac system. Larger the
‘α’ poorer is the power factor.
The input current ii also contain significant amount of harmonic current (3rd, 5th, etc) and
therefore appears as a harmonic source to the utility. Exact composition of the harmonic currents
can be obtained by Fourier series analysis of ii and is left as an exercise.
Exercise 10.2
i) A single phase fully controlled bridge converter can operate either in the _________ or
________ conduction mode.
ii) In the continuous conduction mode at least _________ thyristors conduct at all times.
iii) In the continuous conduction mode the output voltage waveform does not depend on the
________ parameters.
iv) The minimum frequency of the output voltage harmonic in a single phase fully controlled
bridge converter is _________ the input supply frequency.
v) The input displacement factor of a single phase fully controlled bridge converter in the
continuous conduction mode is equal to the cosine of the ________ angle.
Answer: (i) continuous, discontinuous; (ii) two; (iii) load; (iv) twice; (v) firing.
2. A single phase fully controlled bridge converter operates in the continuous conduction
mode from a 230V, 50HZ single phase supply with a firing angle α = 30°. The load
resistance and inductances are 10Ω and 50mH respectively. Find out the 6th harmonic
load current as a percentage of the average load current.
Answer: The average dc output voltage is

2 2
VOAV = Vi cosα = 179.33 Volts
π
V
Average output load current = OAV = 17.93 Amps
RL
From equation (10.18) Va3 = 10.25 Volts
From equation (10.19) Vb3 = 35.5 Volts
∴ V03RMS = 26.126 Volts, Z3 = R 2L + (6× 2× π×50×50×10-3 ) 2 = 94.78 ohms

V03RMS
∴ I3RMS = = 0.2756 Amps = 1.54% of I OAV .
Z3
10.3.2 Operation in the discontinuous conduction mode

So far we have assumed that the converter operates in continuous conduction mode without
paying attention to the load condition required for it. In figure 10.4 the voltage across the R and
L component of the load is negative in the region π - θ ≤ ωt ≤ π + α. Therefore i0 continues to
decrease till a new pair of thyristor is fired at ωt = π + α. Now if the value of R, L and E are such
that i0 becomes zero before ωt = π + α the conduction becomes discontinuous. Obviously then,
at the boundary between continuous and discontinuous conduction the minimum value of i0
which occurs at ωt = α and ωt = π + α will be zero. Putting this condition in (10.26) we obtain the
condition for continuous conduction as.
2sin(φ - α) sinθ
π
- sin(φ - α) - ≥0 (10.32)
-
tanφ
cosφ
1- e

Fig 10.6 shows waveforms of different variables on the boundary between continuous and
discontinuous conduction modes and in the discontinuous conduction mode. It should be stressed
that on the boundary between continuous and discontinuous conduction modes the load current is
still continuous. Therefore, all the analysis of continuous conduction mode applies to this case as
well. However in the discontinuous conduction mode i0 remains zero for certain interval. During
this interval none of the thyristors conduct. These intervals are shown by hatched lines in the
conduction diagram of Fig 10.6(b). In this conduction mode i0 starts rising from zero as T1T2 are
fired at ωt = α. The load current continues to increase till ωt = π – θ. After this, the output
voltage v0 falls below the emf E and i0 decreases till ωt = β when it becomes zero. Since the
thyristors cannot conduct current in the reverse direction i0 remains at zero till ωt = π + α when
T3 and T4 are fired. During the period β ≤ ωt ≤ π + α none of the thyristors conduct. During this
period v0 attains the value E.
Performance of the rectifier such as VOAV, VORMS, IOAV, IORMS etc can be found in terms of α, β
and θ. For example

1 π+α 1⎡ β
∫β 2Vi sinθ dωt ⎤⎥⎦ (10.33)
π+α
π ∫α π ⎢⎣ ∫α
VOAV = v 0 dωt = 2Vi sinωt dωt +
2Vi
Or VOAV = [cosα - cosβ + sinθ(π + α - β)] (10.34)
π
V - E VOAV - 2Vi sinθ
IOAV = OAV = (10.35)
R Zcosφ
2Vi
Or IOAV = [cosα - cosβ + sinθ(α - β)] (10.36)
π Zcosφ
It is observed that the performance of the converter is strongly affected by the value of β. The
value of β in terms of the load parameters (i.e, θ, φ and Z) and α can be found as follows.
In the interval α ≤ ωt ≤ β
di
L o + Rio + E = 2Vi sinωt (10.37)
dt
i 0 ωt =α = 0
From which the solution of i0 can be written as
2Vi ⎡ ( )
⎤
{ }
- ωt-α sinθ ( )
i0 = tanφ - ωt-α (10.38)
⎢ sin(φ - α)e - tanφ + sin(ωt - φ) ⎥
Z ⎣ cosφ 1- e ⎦
Now i0 ωt=β
=0
α-β
sinθ ⎡ α-β
⎤
∴ sin(φ - α)e tanφ
- tanφ + sin(β - φ) = 0 (10.39)
cosφ ⎣1- e ⎦
Given φ, α and θ, the value of β can be found by solving equation 10.39.
10.3.3 Inverter Mode of operation

The expression for average dc voltage from a single phase fully controlled converter in
continuous conduction mode was
2 2
V0 = Vi cosα (10.40)
π
For α < π/2, Vd > 0. Since the thyristors conducts current only in one direction I0 > 0 always.
Therefore power flowing to the dc side P = V0I0 > 0 for α < π/2. However for α > π/2, V0 < 0.
Hence P < 0. This may be interpreted as the load side giving power back to the ac side and the
converter in this case operate as a line commutated current source inverter. So it may be
tempting to conclude that the same converter circuit may be operated as an inverter by just
increasing α beyond π/2. This might have been true had it been possible to maintain continuous
conduction for α < π/2 without making any modification to the converter or load connection. To
supply power, the load EMF source can be utilized. However the connection of this source in
Fig 10.3 is such that it can only absorb power but can not supply it. In fact, if an attempt is made
to supply power to the ac side (by making α > π/2) the energy stored in the load inductor will be
exhausted and the current will become discontinuous as shown in Fig 10.7 (a).

Therefore for sustained inverter mode of operation the connection of E must be reversed as
shown in Fig 10.7(b).
Fig 10.8 (a) and (b) below shows the waveforms of the inverter operating in continuous
conduction mode and discontinuous conduction mode respectively. Analysis of the converter
remains unaltered from the rectifier mode of operation provided θ is defined as shown.

Exercise 10.3
i) In the discontinuous conduction mode the load current remains __________ for a
part of the input cycle.
ii) For the same firing angle the load voltage in the discontinuous conduction mode
is __________ compared to the continuous conduction mode of operation.
iii) The load current ripple factor in the continuous conduction mode is _______
compared to the discontinuous conduction mode.

iv) In the inverter mode of operation electrical power flows from the ________ side
to the __________side.
v) In the continuous conduction mode if the firing angle of the converter is increased
beyond _________ degrees the converter operates in the _______ mode.
Answers: (i) zero; (ii) higher; (iii) lower; (iv) dc, ac; (v) 90, inverter.
2. A 220 V, 20A, 1500 RPM separately excited dc motor has an armature resistance of
0.75Ω and inductance of 50mH. The motor is supplied from a 230V, 50Hz, single phase
supply through a fully controlled bridge converter. Find the no load speed of the motor
and the speed of the motor at the boundary between continuous and discontinuous modes
when α = 25°.
Answer: At no load the average motor torque and hence the average motor armature current is
zero. However, since a converter carries only unidirectional current, zero average armature
current implies that the armature current is zero at all time. From Fig 10.6(b) this situation can
occur only when θ = π/2, i.e the back emf is equal to the peak of the supply voltage. Therefore,
E b no load = 2 × 230 V = 325.27 V, Under rated condition E b 1500 = 205 V
325.27
∴ N no load = ×1500 = 2380 RPM
205
At the boundary between continuous and discontinuous conduction modes from equation 10.32
1+ e -π/tanφ
sinθ = cosφsin(φ - α)
1- e-π/tanφ
From the given data φ = 87.27°, α = 25°
∴ sinθ = 0.5632
∴ E b = 2Vi sinθ = 183.18 Volts
183.18
∴ Motor speed N = ×1500 = 1340 RPM .
205
Summary
• Single phase fully controlled converters are obtained by replacing the diodes of an
uncontrolled converter with thyristors.
• In a fully controlled converter the output voltage can be controlled by controlling the
firing delay angle (α) of the thyristors.
• Single phase fully controlled half wave converters always operate in the discontinuous
conduction mode.
• Half wave controlled converters usually have poorer output voltage form factor compared
to uncontrolled converter.
• Single phase fully controlled bridge converters are extensively used for small dc motor
drives.

• Depending on the load condition and the firing angle a fully controlled bridge converter
can operate either in the continuous conduction mode or in the discontinuous conduction
mode.
• In the continuous conduction mode the load voltage depends only on the firing angle and
not on load parameters.
• In the discontinuous conduction mode the output voltage decreases with increasing load
current. However the output voltage is always greater than that in the continuous
conduction mode for the same firing angle.
• The fully controlled bridge converter can operate as an inverter provided (i) α > π 2 , (ii) a
dc power source of suitable polarity exists on the load side.
References
1) “Power Electronics” P.C.Sen; Tata McGraw-Hill 1995
2) “Power Electronics; Circuits, Devices and Applications”, Second Edition, Muhammad

H.Rashid; Prentice-Hall of India; 1994.
3) “Power Electronics; Converters, Applications and Design” Third Edition, Mohan,

Undeland, Robbins, John Wileys and Sons Inc, 2003.

Q1. Is it possible to operate a single phase fully controlled half wave converter in the
inverting mode? Explain.
Q2. A 220V, 20A 1500 RPM separately excited dc motor has an armature resistance of 0.75Ω
and inductance of 50 mH. The motor is supplied from a single phase fully controlled
converter operating from a 230 V, 50 Hz, single phase supply with a firing angle of α =
30°. At what speed the motor will supply full load torque. Will the conduction be
continuous under this condition?
Q3. The speed of the dc motor in question Q2 is controlled by varying the firing angle of the
converter while the load torque is maintained constant at the rated value. Find the
“power factor” of the converter as a function of the motor speed. Assume continuous
conduction and ripple free armature current.
Q4. Find the load torque at which the dc motor of Q2 will operate at 2000 RPM with the field
current and α remaining same.
Q5. A separately excited dc motor is being braked by a single phase fully controlled bridge
converter operating in the inverter mode as shown in Fig 10.7 (b). Explain what will
happen if a commutation failure occurs in any one of the thyristors.

Answers
1. As explained in section 10.3.3, the load circuit must contain a voltage source of proper
polarity. Such a load circuit and the associated waveforms are shown in the figure next.
Figure shows that it is indeed possible for the half wave converter to operate in the inverting
mode for some values of the firing angle. However, care should be taken such that i0 becomes
zero before vi exceeds E in the negative half cycle. Otherwise i0 will start increasing again and
the thyristor T will fail to commutate.
2. For the machine to deliver full load torque with rated field the armature current should be
20 Amps.
2 2 × 230
Assuming continuous conduction v 0 = cos30o = 179.33 volts.
π
For 20 Amps armature current to flow the back emf will be
Eb = Va – IaRa = 179.33 – 20 × 0.75 = 164.33 volts
E
∴ sinθ = b = 0.505 .
2Vi

ωL a
For the given machine, tanφ = = 20.944, φ = 87.266o .
Ra
Now from equation (10.32)
2sin(φ - α)
- sin(φ - α) = 11.2369.
1- e-π/tanφ
sinθ
and = 10.589
cosφ
∴ the conduction is continuous.
At 1500 RPM the back emf is 220 – 20 × 0.75 = 205 volts.

∴The speed at which the machine delivers rated torques
164.33
is N r = ×1500 = 1202 RPM .
205
3. To maintain constant load torque equal to the rated value the armature voltage should be
N
Va = ra I a rated + E b rated
N rated
N
= 0.75 × 20 + 205 × = 0.137 N + 15 V
1500
In a fully controlled converter operating in the continuous conduction mode

2 2
Va = Vi cosα = 207.073 cosα
π
∴ cosα = 6.616 × 10- 4 N + 0.0724
Now the power factor from equation 10.31 is

2 2
pf = cosα = 5.9565 × 10- 4 N + 0.0652
π
This gives the input power factor as a function of speed.
2000
4. At 2000 RPM, E b = × 205 = 273.33 volts
1500
Eb
∴ sinθ = = 0.84, φ = 87.266o , α = 30o
2Vi
From equation 10.32 it can be shown that the conduction will be discontinuous.
Now from equation 10.39

α -β
⎡ sinθ ⎤ sinθ
⎢ cosφ + sin ( φ - α ) ⎥ = cosφ
sin ⎡⎣( α - φ ) - ( α - β ) ⎤⎦ + e tanφ
⎣ ⎦
or e.0477(α - β)
[17.61+ .8412] - sin ⎡⎣57.266 + ( α - β ) ⎤⎦ = 17.61
o
18.4515 e.0477(α - β) - sin ⎡⎣( α - β ) + 57.266o ⎤⎦ = 17.61

Solving which β ≈ 140°

∴ from equation 10.36
2Vi
Ioav = [cosα - cosβ + sinθ(α - β)] = 2.676 Amps
πZcosφ
2.676
∴ the load torque should be ×100 = 13.38% of the full load torque.
20
5. Referring to Fig 10.8 (a) let there be a commutation failure of T1 at ωt = α. In that case
the conduction mode will be T3 T2 instead of T1 T2 and v0 will be zero during that period.
As a result average value of V0 will be less negative and the average armature current
will increase. However the converter will continue to operate in the inverter mode and
the motor will be braked.

Module
2
AC to DC Converters
Lesson
11
Single Phase Half
Controlled Bridge
Converter
Operation and analysis of single phase half controlled converters
• Draw different topologies of single phase half controlled converter.

• Identify the design implications of each topology.
• Construct the conduction table and thereby draw the waveforms of different system
variables in the continuous conduction mode of operation of the converter.
• Analyze the operation of the converter in the continuous conduction mode to find out the
average and RMS values of different system variables.
• Find out an analytical condition for continuous conduction relating the load parameters
with the firing angle.
• Analyze the operation of the converter in the discontinuous conduction mode of
operation.

11.1 Introduction
Single phase fully controlled bridge converters are widely used in many industrial applications.
They can supply unidirectional current with both positive and negative voltage polarity. Thus
they can operate either as a controlled rectifier or an inverter. However, many of the industrial
application do not utilize the inverter mode operation capability of the fully controlled converter.
In such situations a fully controlled converter with four thyristors and their associated control
and gate drive circuit is definitely a more complex and expensive proposition. Single phase fully
controlled converters have other disadvantages as well such as relatively poor output voltage
(and current for lightly inductive load) form factor and input power factor.
The inverter mode of operation of a single phase fully controlled converter is made
possible by the forward voltage blocking capability of the thyristors which allows the output
voltage to go negative. The disadvantages of the single phase fully controlled converter are also
related to the same capability. In order to improve the output voltage and current form factor the
negative excursion of the output voltage may be prevented by connecting a diode across the
output as shown in Fig 11.1(a). Here as the output voltage tries to go negative the diode across
the load becomes forward bias and clamp the load voltage to zero. Of course this circuit will not
be able to operate in the inverter mode. The complexity of the circuit is not reduced, however.
For that, two of the thyristors of a single phase fully controlled converter has to be replaced by
two diodes as shown in Fig 11.1 (b) and (c). The resulting converters are called single phase half
controlled converters. As in the case of fully controlled converters, the devices T1 and D2
conducts in the positive input voltage half cycle after T1 is turned on. As the input voltage
passes through negative going zero crossing D4 comes into conduction commutating D2 in Fig
11.1 (b) or T1 in Fig 11.1 (c). The load voltage is thus clamped to zero until T3 is fired in the
negative half cycle. As far as the input and output behavior of the circuit is concerned the
circuits in Fig 11.1 (b) and (c) are identical although the device designs differs. In Fig 11.1 (c)
the diodes carry current for a considerably longer duration than the thyristors. However, in Fig
11.1 (b) both the thyristors and the diodes carry current for half the input cycle. In this lesson the
operating principle and characteristics of a single phase half controlled converter will be
presented with reference to the circuit in Fig 11.1 (b).

11.2 Operating principle of a single phase half controlled bridge
converter
With reference of Fig 11.1 (b), it can be stated that for any load current to flow one device from
the top group (T1 or T3) and one device from the bottom group must conduct. However, T1 T3 or
D2 D4 cannot conduct simultaneously. On the other hand T1 D4 and T3 D2 conducts
simultaneously whenever T1 or T3 are on and the output voltage tends to go negative. Therefore,
there are four operating modes of this converter when current flows through the load. Of course
it is always possible that none of the four devices conduct. The load current during such periods
will be zero. The operating modes of this converter and the voltage across different devices
during these operating modes are shown in the conduction table of Fig 11.2. This table has been
prepared with reference to Fig 11.1 (b).

It is observed that whenever D2 conducts the voltage across D4 is -vi and whenever D4 conducts
the voltage across D2 is vi. Since diodes can block only negative voltage it can be concluded that
D2 and D4 conducts in the positive and the negative half cycle of the input supply respectively.
Similar conclusions can be drawn regarding the conduction of T1 and T3. The operation of the
converter can be explained as follows when T1 is fired in the positive half cycle of the input
voltage. Load current flows through T1 and D2. If at the negative going zero crossing of the
input voltage load current is still positive it commutates from D2 to D4 and the load voltage
becomes zero. If the load current further continuous till T3 is fired current commutates from T1
to T3. This mode of conduction when the load current always remains above zero is called the
continuous conduction mode. Otherwise the mode of conduction becomes discontinuous.
Exercise 11.1
Fill in the blanks(s) with the appropriate word(s)
i. In a half controlled converter two ___________________ of a fully controlled converter

are replaced by two ___________________.
ii. Depending on the positions of the ___________________ the half controlled converter
can have ___________________ different circuit topologies.
iii. The input/output waveforms of the two different circuit topologies of a half controlled
converter are ___________________ while the device ratings are
___________________.
iv. A half controlled converter has better output voltage ___________________ compared to
a fully controlled converter.
v. A half controlled converter has improved input ___________________ compared to a
fully controlled converter.
Answer: (i) thyristors, diodes; (ii) diodes, two; (iii) same, different; (iv) form factor; (v) power
factor.

2. Find out an expression of the ration of the thyristor to diode RMS current ratings in the single
phase half controlled converter topologies of Fig. 11.1(b) & (c). Assume ripple free continuous
output current.
Answer
In the first conduction diagram the diodes and the thyristors conduct for equal periods, since the
load current is constant. The ration of the thyristors to the diode RMS current ratings will be
unity for the circuit of Fig 11.1 (b).
From the second conduction diagram the thyristors conduct for π - α radians while the diodes
conduct for π + α radians. Since the load current is constant.
Thyristor RMS current rating 1− α / π
=
Diode RMS current rating 1+ α / π
in this case
11.2.1 Single phase half controlled converter in the continuous

conduction mode
From the conduction table and the discussion in the previous section it can be concluded that the
diode D2 and D4 conducts for the positive and negative half cycle of the input voltage waveform
respectively. On the other hand T1 starts conduction when it is fired in the positive half cycle of
the input voltage waveform and continuous conduction till T3 is fired in the negative half cycle.
Fig. 11.3 shows the circuit diagram and the waveforms of a single phase half controlled
converter supplying an R – L – E load.

Referring to Fig 11.3 (b) T1 D2 starts conduction at ωt = α. Output voltage during this period
becomes equal to vi. At ωt = π as vi tends to go negative D4 is forward biased and the load
current commutates from D2 to D4 and freewheels through D4 and T1. The output voltage
remains clamped to zero till T3 is fired at ωt = π + α. The T3 D4 conduction mode continues upto
ωt = 2π. Where upon load current again free wheels through T3 and D2 while the load voltage is
clamped to zero.
From the discussion in the previous paragraph it can be concluded that the output voltage (hence
the output current) is periodic over half the input cycle. Hence
1 π 1 π 2Vi
Voav =
π ∫o
vo dωt = ∫ 2Vi sin ωt dωt =
π α π
(1+ cosα) (11.1)
V -E 2Vi
Iov = oav = (1+ cosα - π sinθ) (11.2)
R πR

Clearly in addition to the average component, the output voltage (and current) contains a large
number of harmonic components. The minimum harmonic voltage frequency is twice the input
supply frequency. Magnitude of the harmonic voltages can be found by Fourier series analysis of
the load voltage and is left as an exercise.
The Fourier series representation of the load current can be obtained from the load voltage by
applying superposition principle in the same way as in the case of a fully controlled converter.
However, the closed form expression of io can be found as explained next.
In the period α ≤ ωt ≤ π
dio
L + Rio + E = 2Vi sin ωt (11.3)
dt
(ωt-α)
- 2Vi ⎡ sinθ ⎤
io = I1e tanφ + ⎢ sin(ωt - φ) - (11.4)
Z ⎣ cosφ ⎥⎦
E ωL
Where sinθ = ; Z = R2 + ω2 L2 ; tanφ =
2Vi R
2Vi ⎡ sinθ ⎤
io α = I1 + ⎢sin(α - φ) - cosφ ⎥ (11.5)
Z ⎣ ⎦
(π - α) 2Vi ⎡ sinθ ⎤
io = I1 - + ⎢ sinφ - (11.6)
π
tanφ Z ⎣ cosφ ⎥⎦
In the period π ≤ ωt ≤ π + α
dio
L + Rio + E = 0 (11.7)
dt
2Vi sinθ ⎡ - tanφ ⎤
(ωt-π) (ωt-π)
-
tanφ
io = io π e - ⎢1- e ⎥ (11.8)
Z cosφ ⎢⎣ ⎥⎦
2Vi ⎡ sinθ ⎤
(ωt-α) (ωt-π)
- -
∴ io = I1 e tanφ
+ ⎢sinφ e
tanφ
- ⎥ (11.9)
Z ⎣⎢ cosφ ⎦⎥
-
π
2Vi ⎡ -
α
sinθ ⎤
∴ io π+α
= I1e tanφ
+ ⎢sinφ e
tanφ
- ⎥ (11.10)
Z ⎣⎢ cosφ ⎦⎥
Due to periodic operation

io α = io π+α
α
-
tanφ
2Vi sin(φ - α) + sinφ e
∴ I1 = π
(11.11)
Z -
tanφ
1- e
∴ For α ≤ ωt ≤ π
⎧ -
(ωt-α)
⎫
2Vi ⎪ ⎡ -
α
tanφ
⎤ e tanφ sinθ ⎪
io = ⎨ ⎢sin(φ - α) + sinφe ⎥ π
+ sin(ωt - φ) - ⎬ (11.12)
Z ⎪ ⎣⎢ ⎦⎥ 1- e tanφ
- cosφ ⎪
⎩ ⎭
For π ≤ ωt ≤ π + α
⎧ -
(ωt-α)
⎫
2Vi ⎪ ⎡ -
α
tanφ
⎤ e tanφ -
(ωt-π)
tanφ sinθ ⎪
io = ⎨ ⎢sin(φ - α) + sinφe ⎥ π
+ sinφ e - ⎬ (11.13)
Z ⎪ ⎣⎢ ⎦⎥ 1- e tanφ
- cosφ ⎪
⎩ ⎭
The input current ii is given by
ii = i0 for α ≤ ωt ≤ π
ii = - i0 for π + α ≤ ωt ≤ 2π
ii = 0 otherwise (11.14)
However, it will be very difficult to find out the characteristic parameters of ii using equation
11.14 since the expression of i0 is considerably complex. Considerable simplification can
however be obtained if the actual ii waveform is replaced by a quasisquare wave current
waveform with an amplitude of Ioav as shown in Fig 11.5.

From Fig 11.5
IiRMS = 1- α/π Ioav (11.15)
The displacement factor = cos α/2 (11.16)
2Vi
∴ Vi Ii1 cos α = Vo I oav = (1+ cosα)I OAV (11.17)
2 π
2 2
∴ Ii1 = IOAV cos α (11.18)
π 2
Ii1 2
∴ Distortion factor = =2 cos α (11.19)
IiRMS π(π - α) 2
∴ Power factor = displacement factor × distortion factor

2
= (1+ cosα) (11.20)
π(π - α)
Exercise 11.2
i. In a half controlled converter the output voltage can not become ___________________
and hence it can not operate in the ___________________ mode.
ii. For the same firing angle and input voltage the half controlled converter gives
___________________ output voltage form factor compared to a fully controlled
converter.
iii. For ripple-free continuous output current the input current displacement factor of a half
controlled converter is given by ___________________.
iv. For the same supply and load parameters the output current form factor of a half
controlled converter is ___________________ compared to a fully controlled converter.

v. The free wheeling operating mode of a half controlled converter helps to make the output
current ___________________.
π
Answer: (i) negative, inverter; (ii) lower; (iii) cos ; (iv) lower; (v) continuous.
2
2. A single phase half controlled converter is used to supply the field winding of a separately
excited dc machine. With the rated armature voltage the motor operates at the rated no load
speed for a fining angle α =0°. Find the value of α which will increase the motor no load speed
by 30%. Neglect lasses and saturation. Assume continuous conduction.
Answer:
1
N NO load α 1 or φf α
φf N NO load
In order to increase Nno load by 30% φf should be reduced by 23%. Therefore the applied field
voltage must by 23%.
Now by (11.1)
1 + cos α
Vf ( α ) = Vf ( α = 0 )
2
1 + cos α 1 − cos α
∴ 1− = = 0.23
2 2
∴ α = 57.4o
11.2.2 Single phase half controlled converter in the discontinuous

conduction mode.
So far we have discussed the operating characteristics of a single phase half controlled converter
in the continuous conduction mode without identifying the condition required to achieve it. Such
a condition exists however and can be found by carefully examining the way this converter
works.
Referring to Fig 11.3 (b), when T1 is fired at ωt = α the output voltage (instantaneous value) is
larger than the back emf. Therefore, the load current increases till vo becomes equal to E again at
ωt = π – θ. There, onwards the load current starts decreasing. Now if io becomes zero before T3
is fired at ωt = π + α the conduction becomes discontinuous. So clearly the condition for
continuous conduction will be
io ωt
=α≥0 (11.21)
Which in conjunction with the equation (11.12) gives
α
-
tanφ
sin(φ - α) + sinφ e sinθ
π
- sin(φ - α) ≥
-
tanφ
cosφ
1- e

π α
- -
tanφ tanφ
sin(φ - α)e + sinφ e sinθ
or π
≥ (11.22)
-
tanφ
cosφ
1- e
If the condition in Eq. 11.22 is violated the conduction will become discontinuous. Clearly, two
possibilities exist. In the first case the load current becomes zero before ωt = π. In the second
case io continuous beyond ωt = π but becomes zero before ωt = π + α. In both cases however, io
starts from zero at ωt = α.
Fig. 11.6 shows the wave forms in these two cases.
Of these two cases the second one will be analyzed in detail here. The analysis of the first case
is left as an exercise.
For this case

vo = vi for α ≤ ωt ≤ π
vo = 0 for π ≤ ωt ≤ β (11.23)
vo = E for β ≤ ωt ≤ π + α

1 π+α
π ∫α
Therefore VOAV = v o dωt
1 π
= ⎡ ∫ 2vi sinωt dωt + ∫ 2vi sinθ dωt ⎤
π+α
π ⎢
⎣ α β ⎦⎥
2Vi
= [1+ cosα + (π + α - β)sinθ ] (11.24)
π
VOAV - E 2Vi
IOAV = = [1+ cosα + (α - β)sinθ] (11.25)
R π Z cosφ
1 π+α 2
π ∫α
VORMS = vo dωt
1
1 π
= ⎡ ∫ 2vi2 sin 2 ωt dωt + ∫ 2vi2 sin 2θ dωt ⎤
π+α 2
π ⎢
⎣ α β ⎥
⎦
1
2Vi ⎡ π - α 1 ⎤2
= ⎢ + (π + α - β) sin 2θ + sin 2α ⎥ (11.26)
π ⎣ 2 4 ⎦
However IORMS cannot be computed directly from VORMS. For this the closed form expression for
io has to be obtained. This will also help to find out an expression for the conduction angle β.
For α ≤ ωt ≤ π
di o
2Vi sin ωt = Ri o + L +E (11.27)
dt
The general solution is given by
(ωt-α)
- 2Vi
tanφ 2Vi sinθ
io = Io e +
sin(ωt - φ) - (11.28)
Z Z cosφ
Where Z = R 2 + ω2 L2 ; tanφ = ωL ; E = 2Vi sinθ
R
At ωt = α, io = 0
2Vi ⎡ sinθ ⎤
∴ Io = ⎢ + sin(φ - α) ⎥ (11.29)
Z ⎣ cosφ ⎦
2Vi ⎧⎪ ⎡ sinθ sinθ ⎫⎪
ωt-α
⎤ - tanφ
∴ io = ⎨ + sin(φ - α) e + sin(ωt - φ) - ⎬ (11.30)
Z ⎪⎩ ⎢⎣ cosφ ⎥
⎦ cosφ ⎪⎭

α-π
⎤ tanφ
io at ωt = π = ⎨⎢ + sin(φ - α) ⎥ e + sinφ - ⎬ (11.31)
Z ⎩⎪ ⎣ cosφ ⎦ cosφ ⎭⎪
For π ≤ ωt ≤ β
di o
O = Ri o + L +E (11.32)
dt

ωt-π
- 2Vi sinθ
∴ io = I1 e tanφ
- (11.33)
Z cosφ
2Vi sinθ
io ωt = π
= I1 -
Z cosφ
⎧⎪ ⎡ sinθ
2Vi
α-π
⎤ tanφ sinθ ⎫⎪
= ⎨⎢ + sin(φ - α) ⎥ e + sinφ - ⎬ (11.34)
Z ⎩⎪ ⎣ cosφ ⎦ cosφ ⎪⎭
2Vi ⎧⎪ ⎡ sinθ ⎪⎫
α-π
⎤ tanφ
∴ I1 = ⎨ + sin(φ - α) e + sinφ ⎬ (11.35)
Z ⎪⎩ ⎢⎣ cosφ ⎥
⎦ ⎪⎭
ωt-α ωt-π
⎤ - tanφ -
∴ io = ⎨⎢ + sin(φ - α) ⎥ e + sinφe tanφ - ⎬ (11.36)
Z ⎩⎪ ⎣ cosφ ⎦ cosφ ⎭⎪
Equations (11.30) and (11.36) gives closed from expression of io in this conduction mode. To
find out β we note that at ωt = β, io = 0. So from equation (11.36)
α-β π-β
⎡ sinθ ⎤ tanφ sinθ
⎢ cosφ + sin(φ - α) ⎥ e + sinφ e tanφ - =0 (11.37)
⎣ ⎦ cosφ
β π α α
sinθ tanφ sinθ tanφ
or e = sinφ e tanφ + sin(φ - α) e tanφ + e (11.38)
cosφ cosφ
Given the values of ϕ, θ and α the value of β can be obtained from equation 11.38.
Exercise 11.3 (After section 11.2.2)
i. At the boundary between continuous and discontinuous conduction the value of the
output current at ωt = α is ___________________.
ii. The output voltage and current waveform of a single phase fully controlled and half
controlled converter will be same provided the extinction angle β is less than
___________________.
iii. For the same value of the firing angle the average output voltage of a single phase half
controlled converter is ___________________ in the discontinuous conduction mode
compared to the continuous conduction mode.
iv. Single phase half controlled converters are most suitable for loads requiring
___________________ voltage and current.
Answer: (i) zero; (ii) π; (iii) higher; (iv) unidirectional.
2. A single phase half controlled converter charges a 48v 50Ah battery from a 50v, 50Hz single
phase supply through a 50mH line inductor. The battery has on interval resistance of 0.1Ω. The
firing angle of the converter is adjusted such that the battery is charged at C/5 rate when it is
fully discharged at 42 volts. Find out whether the conduction will be continuous or discontinuous
at this condition. Up to what battery voltage will the conduction remain continuous? If the
charging current of the battery is to become zero when it is fully charged at 52 volts what should
be the value of the firing angle.
Answer: From the given data assuming continuous conduction the output voltage of the
converter to charge the battery at C/5 (10 Amps) rate will be
Vo = E + Ib rb = 42 + 0.1×10 = 43volts
∴ α = 24.43o
ωL
φ = tan −1 = 89.63o , tan φ = 157.08, sin φ = 0.99998 cos φ = 6.3 × 10−3
R
Putting these values in equation (11.22) one finds that the conduction will be continuous.
The conduction will remain continuous till
1 −α
cos φ sin ( φ − α ) e
− π tan φ tan φ
+ sin 2φ e
E 2
sin θ = = −π
2vi 1− e
tan φ
From the given value this gives.
E = 2 × 50 × 0.606 = 42.8V
At E = 52 volts io is zero. Therefore
2Vi sin α = E = 52
sin 52
∴ α = 180o − = 132.66o
2 × 50
References
[1] “Power Electronics”; P.C. Sen; Tata McGraw Hill Publishing Company Limited 1995.
[2] “Power Electronics, circuits, devices and applications”; Second Edition; Muhammad H.
Rashid; Prentice – Hall of India; 1994.
[3] “Power Electronics, converters, applications and design”; Third Edition; Mohan,
Undeland, Robbins; John Wiley and Sons Inc., 2003.

Lesson Summary
• Single phase half controlled converters are obtained from fully controlled converters by
replacing two thyristors by two diodes.
• Two thyristors of one phase leg or one group (top or bottom) can be replaced resulting in
two different topologies of the half controlled converter. From the operational point of
view these two topologies are identical.
• In a half controlled converter the output voltage does not become negative and hence the
converter cannot operate in the inverter mode.
• For the same firing angle and input voltage the half controlled converter in the continuous
conduction mode gives higher output voltage compared to a fully controlled converter.
• For the same input voltage, firing angle and load parameters the half controlled converter
has better output voltage and current form factor compared to a fully controlled
converter.
• For the same firing angle and load current the half controlled converter in the continuous
conduction mode has better input power factor compared to a fully controlled converter.
• Half controlled converters are most favored in applications requiring unidirectional
output voltage and current.

Q1. The thyristor T3 of Fig 1.1(b) fails to turn on at the desired instant. Describe how this
circuit will work in the presence of the fault.
Q2. A single phase half controlled converter is used to boost the no load speed of a
separately excited dc machine by weakening its field supply. At α = 0° the half
controlled converter produces the rated field voltage. If the field inductance is large enough
to make the field current almost ripple face what will be the input power factor when the dc
motor no load speed is bossed to 150%?
Q3. A single phase half controlled converter supplies a 220V, 1500rpm, 20A dc motor from a
230V 50HZ single phase supply. The motor has a armature resistance of 1.0Ω and
inductance of 50mH. What will be the operating modes and torques for α = 30°; and
speed of 1400 RPM.

Answer to practice problems
Figure above explains the operation of the circuit following the fault. T1 is tired at ωt = α and the
load current commutates from T3 to T1. The conduction periods T1 D2 & T1 D4 commences as
usual. However at ωt = π + α when T3 is fired it fails to turn ON and as a consequences T1 does
not commutate. Now if the load is highly inductive T1 D4 will continue to conduct till ωt = 2π
and the load voltage will be clamped to zero during this period.
However, since T1 does not stop conduction fining angle control on it is lost after words. Hence
T1 D2 conduction period starts right after ωt = 2π instead of at ωt = 2π + α. Thus the full positive
half cycle of supply voltage is applied across the load followed by a entire half cycle of zero
voltage. Thus the load voltage becomes a half wave rectified sine wave and voltage control
through fining angle is last. This is the effect of the fault.
[Note: This phenomenon is known as “half cycle brusting”. It can be easily verified that this
possibility does not existion the circuit shown in Fig 11.1 (c)]
2. For a separately excited dc motor
1 1
ωNO load α α
φf Vf
Vf rated
∴ Vf = for boosting no load speed by 150%
1.5
Vf 1 + cos α 1
but = =
Vf rated 2 1.5
∴ α = 70.53o
using equation 11.20 the power factor will be 0.77.

ωL
3. From the given data, tanφ = = 15.7, φ = 86.36o
R
E 14 220 − 20 × 1.0
sinθ = = × = 0.578 substituting these values in equation 11.22 it can be
2Vi 15 2 × 230
conducted that the conduction is continuous
∴ Va = 193.2V, E = 186.7V
V −E
∴ Ia = a = 6.53A
ra
6.53
∴ Motor torque will be ×100 = 32.67% of full load torque.
20

Module
2
AC to DC Converters
Lesson
12
Single Phase Uncontrolled
Rectifier
Operation and Analysis of three phase uncontrolled rectifier.
• Draw the conduction table and waveforms of a three phase half wave uncontrolled
converter supplying resistive and resistive inductive loads.
• Calculate the average and RMS values of the input / output current and voltage
waveforms of a three phase uncontrolled half wave converter.
• Analyze the operation of a three phase full wave uncontrolled converter to find out the
input / output current and voltage waveforms along with their RMS and Average values.
• Find out the harmonic components in the input / output voltage and current waveforms of
a three phase uncontrolled full wave converter.
• Analyze the operation of a three phase full wave uncontrolled converter supplying a
Capacitive – Resistive load.

12.1 Introduction
Single phase rectifiers, as already discussed, are extensively used in low power applications
particularly for power supplies to electronic circuits. They are also found useful for supplying
small dc loads rarely exceeding 5 KW. Above this power level three phase ac – dc power
supplies are usually employed. Single phase ac – dc converters have several disadvantages such
as
• Large output voltage and current form factor.

• Large low frequency harmonic ripple current causing harmonic power loss and reduced
efficiency.
• Very large filter capacitor for obtaining smooth output dc voltage.
• Low frequency harmonic current is injected in the input ac line which is difficult to filter.
The situation becomes worse with capacitive loads.
Many of these disadvantages are mitigated to a large extent by using three phase ac – dc
converters. In a way it is also natural that bulk loads are supplied by three phase converters since
bulk electrical power is always transmitted and distributed in three phases and high power should
load three phases symmetrically. Polyphase rectifiers produce less ripple output voltage and
current compared to single phase rectifiers. The efficiency of polyphase rectifier is also higher
while the associated equipments are smaller.
A three phase supply gives the choice of a number of circuits. These can be placed in one of two
groups according to whether three or six diodes are used. These topologies will be analyzed in
detail in this section.
12.2 Operating principle of three phase half wave uncontrolled

rectifier
The half wave uncontrolled converter is the simplest of all three phase rectifier
topologies. Although not much used in practice it does provide useful insight into the operation
of three phase converters. Fig. 12.1 shows the circuit diagram, conduction table and wave forms
of a three phase half wave uncontrolled converter supplying a resistive inductive load.

For simplicity the load current (io) has been assumed to be ripple free. As shown in Fig.
12.1 (a), in a three phase half wave uncontrolled converter the anode of a diode is connected to
each phase voltage source. The cathodes of all three diodes are connected together to form the
positive load terminal. The negative terminal of the load is connected to the supply neutral.
Fig. 12.1 (b) shows the conduction table of the converter. It should be noted that for the
type of load chosen the converter always operates in the continuous conduction mode. The
conduction diagram for the diodes (as shown in Fig. 12.1 (c) second waveform) can be drawn
easily from the conduction diagram. Since the diodes can block only negative voltage it follows
from the conduction table that a phase diode conducts only when that phase voltage is maximum

of the three. (In signal electronics the circuit of Fig. 12.1 (a) is also known as the “maximum
value” circuit). Once the conduction diagram is drawn other waveforms of Fig. 12.1 (c) are
easily obtained from the supply voltage waveforms in conjunction with the conduction table.
The phase current waveforms of Fig. 12.1 (c) deserve special mention. All of them have a
dc component which flows through the ac source. This may cause “dc saturation” in the ac side
transformer. This is one reason for which the converter configuration is not preferred very much
in practice.
From the waveforms of Fig. 12.1 (c)
3 5π/6
2π ∫π/6
VOAV = 2Vi sin ωt d(ωt)
3 6
= Vi (12.1)
2π
1
⎡ 3 5π/6 ⎤2
VORMS = ⎢ ∫ 2Vi2 sin 2 ωt d(ωt) ⎥
⎣ 2π π/6 ⎦
1
⎡ 3 3 ⎤2
= ⎢1 + ⎥ Vi (12.2)
⎣ 4π ⎦
VORMS
∴ The output voltage form factor = = 1.01 (12.3)
VOAV
VOAV
IO av = ,
R
IO
Ii RMS = I a RMS = I b RMS = I c RMS = (12.4)
3
3 6
VO av IO Vi IO
3
∴ Input power factor = AV
= 2π = (12.5)
3Vi Ii RMS IO 2π
3Vi
3
The harmonics present in vo and ii can be found by Fourier series analysis of the
corresponding waveforms of Fig. 12.1 (c) and is left as an exercise.
Exercise 12.1
i) Three phase half wave uncontrolled rectifier uses ________ diodes.

ii) Three phase half wave uncontrolled rectifier requires ________ phase ______ wire
power supply.

iii) In a three phase half wave uncontrolled rectifier each diode conduct for _________
radians.
iv) The minimum frequency of the output voltage ripple in a three phase half wave
uncontrolled rectifier is _________ times the input voltage frequency.
v) The input line current of a three phase half wave uncontrolled rectifier contain ________
component.
Answers: (i) three; (ii) three, four; (iii) 2π/3; (iv) three; (v) dc.
2. Assuming ripple free output current, find out the, displacement factor, distortion factor
and power factor of a three phase half wave rectifier supplying an R – L load.
With reference to Fig 12.1 the expression for phase current ia can be written as
π 5π
i a = Id ≤ ωt ≤
6 6
ia = 0 otherwise.
Fundamental component of ia can be written as
i a1 = 2 Ia1 sin(ωt + φ)
A1
where 2 Ia1 = A12 + B12 and φ = tan -1
B1
1 2π
π ∫0
A1 = i a cosωt dωt
1 2π
B1 = ∫ i a sinωt dωt
π 0
5π
1
∴ A1 = ∫π6 Id cosωt dωt = 0
π 6
5π
1 6 3
B1 = ∫
π 6
π I d sinωt dωt =
π
Id
3 3 Id
∴ 2I a1 = B1 = Id ∴ Ia1 =
π 2 π
φ = 0 ∴ Displacement factor = cosφ = 1.
Id
R.M.S value of ia = Ia =
3
Ia1 3
∴ Distortion factor = =
Ia 2π
3
Power Factor = Disp. Factor × Dist. Factor =
2π

12.3 Three phase full wave uncontrolled converter
As has been explained earlier three phase half wave converter suffers from several
disadvantages. Chief among them are dc component in the input ac current, requirement of
neutral connection and comparatively lower output voltage. In addition the input and output
waveforms contain lower order harmonics which require heavy filtering.
Most of these disadvantages can be mitigated by using a three phase full wave bridge rectifier.
This is probably the most extensively used rectifier topology from low (>5 KW) to moderately
high power (> 100 KW) applications. In this section the operation of a three phase full wave
uncontrolled bridge rectifier with two different types of loads namely the R – L – E type load and
the capacitive load will be described.
12.3.1 Operation of a 3 phase full wave uncontrolled bridge

rectifier supplying an R – L – E load
This type of load may represent a dc motor or a battery. Usually for driving these loads a
variable output voltage is required. This requirement has to be met by using a variable ac source
(e.g a 3 phase variable) since the average output voltage of an uncontrolled rectifier is constant
for a given ac voltage.
It will also be assumed in the following analysis that the load side inductance is large enough to
keep the load current continuous. The relevant condition for continuous conduction will be
derived but analysis of discontinuous conduction mode will not be attempted. Compared to
single phase converters the cases of discontinuous conduction in 3 phase bridge converter are
negligible.

Since the load current is assumed to be continuous at least one diode from the top group
(D1, D3 and D5) and one diode from the bottom group (D2, D4 and D6) must conduct at all time.
It can be easily verified that only one diode from each group (either top or bottom) conducts at a
time and two diodes from the same phase leg never conducts simultaneously. Thus the converter

has six different diode conduction modes. These are D1D2, D2D3, D3D4, D4D5, D5D6 and D6D1.
Each conduction mode lasts for π/3 rad and each diode conducts for 120º.
Fig. 12.2 (b) shows voltages across different diodes and the output voltage in each of
these conduction modes. The time interval during which a particular conduction mode will be
effective can be ascertained from this table. For example the D1D2 conduction mode will occur
when the voltage across all other diodes (i.e. vba, vca and vcb) are negative. This implies that
D1D2 conducts in the interval 0 ≤ ωt ≤ π/3 as shown in Fig. 12.2 (c). The diodes have been
numbered such that the conduction sequence is D1 → D2 → D3 → D4 → D5 → D6 → D1---.
When a diode stops conduction its current is commutated to another diode in the same group (top
or bottom). This way the sequence of conduction modes become, D1D2 → D2D3 → D3D4 →
D4D5 → D5D6 → D6D1 → D1D2 ---. The conduction diagram in Fig. 12.2 (c) is constructed
accordingly.
The output dc voltage can be constructed from this conduction diagram using appropriate
line voltage segments as specified in the conduction table.
The input ac line currents can be constructed from the conduction diagram and the output
current. For example
ia = io for 0 ≤ ωt ≤ π/3 and 5π/3 ≤ ωt ≤ 2π
ia = - io for 2π/3 ≤ ωt ≤ 4π/3
ia = 0 otherwise. (12.6)
The line current wave forms and their fundamental components are shown in Fig. 12.2 (c).
It is clear from Fig 12.2 (c) that the dc voltage output is periodic over one sixth of the input ac
cycle.
For π/3 ≤ ωt ≤ 2π/3

v o = 2VL sin ωt (12.7)
3 2π/3 3 2
VOAV =
π ∫π/3
2VL sin ωt dωt =
π
VL (12.8)
3 2π/3 2
VORMS =
π ∫π/3
2VL sin 2 ωt dωt
⎛ 3 3⎞
= ⎜⎜ 1 + ⎟VL (12.9)
⎝ 2π ⎟⎠
2 VOAV − E
Ii RMS = IOAV ; IOAV = (12.10)
3 R
Ii1 RMS can be found as follows

3 VL Ii 1 = VOAV IOAV (12.11)

Since input displacement factor is unity
VOAV 6
∴ Ii1 = IOAV = IOAV (12.12)
3VL π
3 Ii1
∴ Power factor = distortion factor = = (12.13)
Ii RMS π
A closed form expression for io can be found as follows
for π/3 ≤ ωt ≤ 2π/3

di o
L + Ri o + E = v o = 2VLsinωt (12.14)
dt
The general solution is given by
ωt - π/3
-
tanφ 2VL ⎡ sinθ ⎤
io = I1e + ⎢ sin(ωt - φ) - (12.15)
Z ⎣ cosφ ⎥⎦
ωL E
Where tanφ = ; sinθ = ; Z = R 2 + ω2 L2
R 2VL
Now since the current waveform is periodic over one sixth of the input ac cycle
⎛ π⎞ ⎛ 2π ⎞
i o ⎜ ωt = ⎟ = i o ⎜ ωt = ⎟ (12.16)
⎝ 3⎠ ⎝ 3 ⎠
π
2VL ⎡ ⎛ π ⎞ sinθ ⎤ - 2VL ⎡ ⎛ 2π ⎞ sinθ ⎤
∴ I1 + sin - φ - =
⎢ ⎜ 3 ⎟ cosφ ⎥ 1 I e 3tanφ
+ sin ⎜ - φ ⎟ - (12.17)
Z ⎣ ⎝ ⎠ ⎦ Z ⎢⎣ ⎝ 3 ⎥
⎠ cosφ ⎦
2VL sinφ
∴ I1 = π
(12.18)
Z -
3tanφ
1- e
⎡ ωt - π/3 ⎤
2VL ⎢ sinφ - 3tanφ sinθ ⎥
∴ io = e + sin ( ωt - φ ) - (12.19)
Z ⎢ - 3tanφ
π
cosφ ⎥
⎣1- e ⎦
Exercise 12.2
i) Three phase full wave uncontrolled rectifier uses _________ diodes.

ii) Three phase full wave uncontrolled rectifier does not require ________ wire connection.
iii) In a three phase full wave uncontrolled rectifier each diode conducts for _______ radians.
iv) The minimum frequency of the output voltage ripple in a three phase full wave rectifier is
_________ times the input voltage frequency.
v) The input ac line current of a three phase full wave uncontrolled rectifiers supplying an R
– L – E load contain only ________ harmonics but no ________ harmonic or
__________ component.
vi) A three phase full wave uncontrolled rectifier supplying an R – L – E load normally
operates in the ________ conduction mode.
Answers: (i) six; (ii) neutral; (iii) 2π/3; (iv) six; (v) odd, tripler, dc; (vi) continuous.
2. A 220 V, 1500 rpm 20 A separately excited dc motor has armature resistance of 1Ω and
negligible armature inductance. The motor is supplied from a three phase full wave
uncontrolled rectifier connected to a 220 V, 3 phase, 50 Hz supply through a Δ/Y
transformer. Find out the transformer turns ratio so that the converter applies rated
voltage to the motor. What is the maximum torque as a percentage of the rated torque the
motor will be able to supply without over heating. Assume ideal transformer and
continuous conduction.
Answer: Average output voltage of the converter is
3 2
V0 = VL = 220V
π
∴ VL = 163 Volts. This is the line voltage of the secondary side of the transformer.
The secondary is star connected. So
163
Secondary phase voltage = = 94 volts .
3
Primary side is delta connected. So
Primary phase voltage = 220 V.
220
∴ The required turns ratio = = 2.34 :1
94
Output voltage can be written as

α
v 0 = V0 + ∑ v hn Where vhn = nth harmonic voltage magnitude.
n =1
V0 - E α v hn
∴ i0 = +∑
r n =1 r
Where E = back emf and r = armature resistance

2 2
⎛ V -E⎞ α
⎛ Vhn ⎞
∴ ⎟ ∑⎜
2
I 0RMS =⎜ 0 + ⎟
⎝ r ⎠ n=1 ⎝ r ⎠
2 2 2
V0AV V0AV α
⎛ Vhn ⎞
2
= I0AV -
r 2
+
r 2
+ ∑ ⎜
n=1 ⎝ r ⎠
⎟
2 V2 2
V0RMS
= I 0AV - 0AV +
r2 r2

2
V0AV
2
= I 0AV +
r2
( FF2 -1)
To prevent over heating I0RMS = 20 A
2
2 ⎛ V0RMS ⎞
For the given converter FF = ⎜ ⎟ = 1.00176
⎝ V0AV ⎠
2202
∴ 202 = I 0AV
2
+ (1.00176 -1)
1
∴ 2
I 0AV = 314.816 ∴ I0AV = 17.743 Amps.
In a separately excited dc machine Te ∝ I0AV
17.743
∴ Maximum allowable torque = ×100 = 88.715 % of full load torque.
20
12.3.2 Operation of a three phase uncontrolled bridge rectifier

supplying a capacitive load
A three phase uncontrolled bridge rectifier supplying a capacitive load is a very popular
power electronic converter. It is very widely used as the front end of a variable voltage variable
frequency dc – ac inverter. Fig. 12.3 (a) shows the power circuit diagram of such a converter.
Operation of the converter can be explained as follows. The top group diodes (D1, D3, D5) form
a “Maximum value circuit” and therefore the maximum of the phase voltages van, vbn, vcn appears
at the positive dc bus. On the other hand, the bottom group diodes (D2, D4, D6) form a
“Minimum value circuit”. Therefore the minimum of the phase voltages van, vbn and vcn appears
at the negative dc bus. Therefore, the output voltage waveform at any instant is equal to the
maximum of the six line voltages vab, vbc, vca, vba, vcb and vac provided at least one diode from the
top group and one from the bottom group conducts at that instant. None of the diodes will
conducts, however if the output capacitor voltage is larger than the maximum line voltage. All
the six operating modes of a 3 phase bridge rectifier namely, D1D2, D2D3, D3D4, D4D5, D5D6 and
D6D1 appear in that order. In addition an additional operating mode in which none of the diodes
conduct appears in the conduction diagram as shown in Fig. 12.3 (b). During these periods the
output capacitor discharges through the load. As the capacitor voltage decreases its voltage
becomes equal to the incoming line voltage. At this instant the appropriate diodes from both the
top and the bottom group starts conducting and continuous to do so till the sum of the capacitor
charging current and the load current becomes zero.

From Fig. 12.3 (b)
In the interval α ≤ ωt ≤ β
v o = 2VL sin ωt (12.20)
dvo
∴ ic = c = 2VL ωc cos ωt (12.21)
dt
v V
i o = o = 2 L sin ωt (12.22)
R R
VL
∴ ii = i o + i c = 2 [ ωRC cos ωt + sin ωt ]
R
V
= 2 L 1+ ω2 R 2 C2 cos (ωt - φ) (12.23)
R
1
Where tanφ =
ωRC
At ωt = β, ii = 0
π
∴ cos (β - φ) = 0 or β = +φ (12.24)
2
in the interval
β ≤ ωt ≤ α + π/3
dvo v o
c + =0
dt R
ωRC
v o β = 2VL sinβ = 2VL cosφ = 2VL (12.25)
1+ ω 2 R 2 C 2
(ωt - β) (ωt - β)
- ωRC -
∴ vo = vo β e ωRC
= 2VL e ωRC
(12.26)
1+ ω2 R 2 C 2
at ωt = α + π/3
π/6 - α + φ
ωRC
v o = 2VL e ωRC
(12.27)
1+ ω2 R 2 C 2
Also at ωt = α + π/3
⎛ π⎞
v o = 2VL sin ⎜ ωt - ⎟
⎝ 3 ⎠ ωt = α + π
3
= 2VL sin α

π/6 - α + tan -1 ωRC
1
ωRC
∴ sinα = e ωRC
(12.28)
2 2 2
1+ ω R C
From which the value of α can be found. Equation 12.23 gives the expression of the
output current ii of the rectifier.
It is observed that ii is discontinuous and contains large ripple. This is a major

disadvantage of this converter. This ripple is also reflected in the input current of the rectifier as
shown in Fig 12.3 (b). However, the displacement factor of the converter still remains unity.
The current ii can be made continuous by connecting an inductor of appropriate value

between the rectifier and the capacitor. Analysis of such a converter is similar to a converter
V
supplying an R – L – E load where the value of E is 3 2 L .
π
Exercise 12.3
i) A three phase full wave uncontrolled rectifier supplying a capacitive load can operate in
the _________ conduction mode.
ii) The output _________ ripple factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is very low.
iii) The output _________ ripple factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is very high.
iv) The input current displacement factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is ___________.
v) The input current distortion factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is very ________.
Answers: (i) discontinuous; (ii) voltage; (iii) current; (iv) unity; (v) high.
2. A three phase full wave rectifier operates from 220 volts, three phase 50 Hz supply and
supplies a capacitive resistive load of 20 Amps. An inductor of negligible resistance is
inserted between the rectifier and the capacitor. Assuming the capacitor to be large
enough so that the output voltage is almost ripple free. Calculate the value of the
inductor so that the rectifier output current is continuous.
Answers: The following figure shows the circuit arrangement and the corresponding waveforms.

Since the conduction is continuous
3 2 V0 3
V0 = VL and sinθ = = or θ = 72.73º
π 2VL π
π 2π
In the interval ≤ ωt ≤
3 3
di
v0 + L L = 2VL sinωt
dt
3 2
Since v0 is almost ripple free v0 = V0 = VL
π
3 2 di
∴ VL + ωL L = 2VL sinωt
π dωt
2VL 3 2
i L = I0 - cosωt - VL ωt
ωL πωL
Now i L av = 20A

3 2 1 π2 3 3VL
∴ I0 - VL × × × = 20A or I 0 = 20 +
πωL 2 3 π 2ωL
2VL ⎡ 3 3 ⎤
∴ i L = 20 + ⎢ - cosωt - ωt ⎥
ωL ⎣ 2 π ⎦
For just continuous conduction iL = 0 at ωt = θ
2VL ⎡ 3 3 ⎤
∴ 0 = 20 + ⎢ - cosθ - θ ⎥
ωL ⎣ 2 π ⎦
or ωL = 1.0306 Ω or L = 3.28 mH.
References
[1] “Power Electronics”, P.C. Sen; Tata MC Grawhill publishing company limited; 1995.
[2] “Power Electronics, Converters, Applications and Design”; Mohan, Undeland, Robbins;
John Willey and Sons Ine, Third Edition, 2003.
Lesson Summary
• Three phase uncontrolled rectifiers are available in half wave and full wave
configuration.
• Three phase uncontrolled half wave rectifier require three phase four wire power supply.
• The input ac line current in a three phase uncontrolled half wave rectifier contain dc
component which may cause “dc saturation” of input transformer.
• Three phase full wave uncontrolled rectifier is most widely used in the medium power
applications particularly as the input stage of the dc link inverter.
• Three phase full wave uncontrolled rectifier uses six diodes instead of three of the half
wave rectifier.
• Full bridge rectifier does not require neutral connection.
• The output voltage of a three phase full bridge rectifier contains multiplies of 6th
harmonic of input cycle.
• The input ac current of a three phase full bridge rectifier contain only odd harmonics but
no dc component or triplen harmonics.
• The input displacement factor of the three phase bridge rectifier is always unity.
• Three phase full bridge converter supplying an R – L – E load usually operate in the
continuous conduction mode.
• Compared to single phase rectifiers, three phase bridge converter require smaller inductor
to obtain the same output current ripple factor.

• Three phase bridge rectifier supplying a capacitive load has very good output voltage
form factor but very poor input current THD.
• Compared to single phase converters three phase bridge rectifier require smaller capacitor
to obtain a given output voltage form factor.

Q1. A three phase half wave rectifier operates from a three phase 220 V, 50 Hz supply and
supplies a resistive load rated at 200 Volts 1 KW through an inductance large enough to
make the load current ripple free. Find out the power consumed by the load? What will
be the load power if the inductor is shorted?
Q2. A three phase full wave rectifier operates from a three phase 220 V 50 Hz supply through
a three phase Δ/Y transformer and supplies a 200 V 1500 R.P.M, 50 Amps separately
excited dc motor. Find out the turns ratio of the transformer so that the motor operates at
rated speed at full load. If the motor armature resistance is 0.5 Ω find out the inductance
to be connected in series with the motor such that the rectifier operates in the continuous
conduction mode at 50 % of the full load torque.
Q3. A three phase full wave rectifier supplies a resistive capacitive load of 50 Amps from a
220 V. 3 phase 50 Hz supply. Find out the value of the load capacitance such that the
load voltage ripple is less than 5 %.
Answers to practice problems

1. Since the load current is ripple free the power consumed by the load will be
2
2 V0AV
PL = I 0AV R LOAD =
R LOAD
3 2VL 3 2 × 220
Now V0AV = = = 148.55 volts
2π 2π
2 2
V0AV ⎛ 148.55 ⎞
∴ PL = =⎜ ⎟ ×1 KW = 551.7 watts
R LOAD ⎝ 200 ⎠
When the inductor is shorted

2
V0RMS
PL =
R LOAD
1 3
Now from Equ. (12.2) V0RMS = + VL = 151.01 volts
3 4π

2 2
V0RMS ⎛ 151.01 ⎞
∴ PL = =⎜ ⎟ ×1 KW = 570 watts
R LOAD ⎝ 200 ⎠
2. To run at rated speed at full load the motor terminal voltage must be 200 volts.
3 2
∴ V0AL = VL = 200 volts, ∴ VL = 148.1 volts
π
Where VL is the secondary line voltage. Secondary is star connected. So secondary
phase voltage
VL
V2 = = 85.5 volts
3
Primary is delta connected. So primary phase voltage

V1 = 220 V
V
∴ Required turns ratio = 1 = 1: 0.38865
2
At 50% of the full load torque motor current is 25 Amps
∴ back Emf = 200 – 0.5 × 25 = 187.5 Volts.

187.5
∴ speed at 50% of full load torque = ×1500 = 1607 RPM .
200 - 0.5×50
At 50% of full load torque the motor operates in the continuous conduction mode,
with reference to Fig. 12.2 and equation 12.19.
⎡ ωt-π/3 ⎤
2VL ⎢ sinφ - tanφ sinθ ⎥
i0 = e + sin(ωt - φ) -
z ⎢ -
π
cosφ ⎥
⎣1- e 3tanφ
⎦
E 187.5
Where sinθ = = = 0.9375
2VL 200
θ = 69.64º = 1.2154 rad.
At the junction of continuous and discontinuous conduction
i 0 Min = i 0 ωt = θ = 0
( θ-π/3)
sinφ - sinθ
∴ π
e tanφ
+ sin(θ - φ) - =0
-
3tanφ
cosφ
1- e
( π/3 - θ )
1 sin2φe tanφ 1 1
OR π
+ sinθ - sin(θ - 2φ) = sinθ
2 - 2 2
1- e 3tanφ

( π/3 - θ )
tanφ
e
OR sin2φ π
- sin(θ - 2φ) = sinθ
-
3tanφ
1- e
Solving which φ = 34.65º.
ωL
∴ = tanφ = 0.6911
R
∴ ωL = 0.3456 Ω or L = 1.1 mH.
3. Assuming linear ripple
V0Max + V0Min
V0AV =
2
V̂0pp = V0Max - V0Min
2 ( V0Max + V0Min ) V̂0pp
∴ = = 0.05
V0Max + V0Min V0AV
1- V0Min /V0Max
∴ = 0.025
1+ V0Min /V0Max
∴ V0Min /V0Max = 0.9512 .
From Fig. 12.3, V0Max = 2VL = 2 × 220 V = 311 volts

∴ V0Min = 295.943 Volts ∴ V0AV = 303.47 V.
I0AV = 50 Amps ∴ R = 6.0694 Ω.
From Fig. 12.3. V0Min occurs at ωt = α

∴ V0Min = 2VLsinα = 295.943
∴ sin α = 0.9512 or α = 72º
But from Equation (12.28)

⎛π ⎞
tanφ ⎜ - α+φ ⎟
sinα = cosφ e ⎝ 6 ⎠
1
where tanφ =
ωRC
from which φ = 3.5º ∴ tanφ = 0.06116
1
∴ ωRC = = 16.35 , R = 6.0694 Ω
tanφ
∴ ωC = 2.6938, ∴ C = 8575 μF.

Module
2
AC to DC Converters
Lesson
13
Operation and Analysis of
the Three Phase Fully
Controlled Bridge
Converter
• Draw the circuit diagram and waveforms associated with a three phase fully controlled
bridge converter.
• Find out the average, RMS valves and the harmonic spectrum of the output voltage /
current waveforms of the converter.
• Find out the closed form expression of the output current and hence the condition for
• Find out the displacement factor, distortion factor and the power factor of the input
current as well as its harmonic spectrum.
• Analyze the operation of higher pulse number converters and dual converter.
• Design the triggering circuit of the three phase fully controlled bridge converter.

13.1 Introduction
The three phase fully controlled bridge converter has been probably the most widely used power
electronic converter in the medium to high power applications. Three phase circuits are
preferable when large power is involved. The controlled rectifier can provide controllable out
put dc voltage in a single unit instead of a three phase autotransformer and a diode bridge
rectifier. The controlled rectifier is obtained by replacing the diodes of the uncontrolled rectifier
with thyristors. Control over the output dc voltage is obtained by controlling the conduction
interval of each thyristor. This method is known as phase control and converters are also called
“phase controlled converters”. Since thyristors can block voltage in both directions it is possible
to reverse the polarity of the output dc voltage and hence feed power back to the ac supply from
the dc side. Under such condition the converter is said to be operating in the “inverting mode”.
The thyristors in the converter circuit are commutated with the help of the supply voltage in the
rectifying mode of operation and are known as “Line commutated converter”. The same circuit
while operating in the inverter mode requires load side counter emf. for commutation and are
referred to as the “Load commutated inverter”.
In phase controlled rectifiers though the output voltage can be varied continuously the load
harmonic voltage increases considerably as the average value goes down. Of course the
magnitude of harmonic voltage is lower in three phase converter compared to the single phase
circuit. Since the frequency of the harmonic voltage is higher smaller load inductance leads to
continuous conduction. Input current wave shape become rectangular and contain 5th and higher
order odd harmonics. The displacement angle of the input current increases with firing angle.
The frequency of the harmonic voltage and current can be increased by increasing the pulse
number of the converter which can be achieved by series and parallel connection of basic 6 pulse
converters. The control circuit become considerably complicated and the use of coupling
transformer and / or interphase reactors become mandatory.
With the introduction of high power IGBTs the three phase bridge converter has all but been
replaced by dc link voltage source converters in the medium to moderately high power range.
However in very high power application (such as HV dc transmission system, cycloconverter
drives, load commutated inverter synchronous motor drives, static scherbius drives etc.) the basic
B phase bridge converter block is still used. In this lesson the operating principle and
characteristic of this very important converter topology will be discussed in source depth.
13.2 Operating principle of 3 phase fully controlled bridge

converter
A three phase fully controlled converter is obtained by replacing all the six diodes of an
uncontrolled converter by six thyristors as shown in Fig. 13.1 (a)

For any current to flow in the load at least one device from the top group (T1, T3, T5) and one
from the bottom group (T2, T4, T6) must conduct. It can be argued as in the case of an
uncontrolled converter only one device from these two groups will conduct.
Then from symmetry consideration it can be argued that each thyristor conducts for 120° of the
input cycle. Now the thyristors are fired in the sequence T1 → T2 → T3 → T4 → T5 → T6 → T1
with 60° interval between each firing. Therefore thyristors on the same phase leg are fired at an
interval of 180° and hence can not conduct simultaneously. This leaves only six possible
conduction mode for the converter in the continuous conduction mode of operation. These are
T1T2, T2T3, T3T4, T4T5, T5T6, T6T1. Each conduction mode is of 60° duration and appears in the
sequence mentioned. The conduction table of Fig. 13.1 (b) shows voltage across different
devices and the dc output voltage for each conduction interval. The phasor diagram of the line
voltages appear in Fig. 13.1 (c). Each of these line voltages can be associated with the firing of a
thyristor with the help of the conduction table-1. For example the thyristor T1 is fired at the end
of T5T6 conduction interval. During this period the voltage across T1 was vac. Therefore T1 is
fired α angle after the positive going zero crossing of vac. Similar observation can be made about
other thyristors. The phasor diagram of Fig. 13.1 (c) also confirms that all the thyristors are fired
in the correct sequence with 60° interval between each firing.
Fig. 13.2 shows the waveforms of different variables (shown in Fig. 13.1 (a)). To arrive at the
waveforms it is necessary to draw the conduction diagram which shows the interval of
conduction for each thyristor and can be drawn with the help of the phasor diagram of fig. 13.1
(c). If the converter firing angle is α each thyristor is fired “α” angle after the positive going zero
crossing of the line voltage with which it’s firing is associated. Once the conduction diagram is
drawn all other voltage waveforms can be drawn from the line voltage waveforms and from the
conduction table of fig. 13.1 (b). Similarly line currents can be drawn from the output current
and the conduction diagram. It is clear from the waveforms that output voltage and current
waveforms are periodic over one sixth of the input cycle. Therefore this converter is also called
the “six pulse” converter. The input current on the other hand contains only odds harmonics of
the input frequency other than the triplex (3rd, 9th etc.) harmonics. The next section will analyze
the operation of this converter in more details.

Exercise 13.1
i) The three phase fully controlled bridge converter is obtained by replacing six
_________ of an uncontrolled converter by six __________.

ii) The pulse number of a three phase fully controlled bridge converter is _________.
iii) In a three phase fully controlled converter each device conducts for an interval of
__________ degrees.
iv) In a three phase fully controlled converter operating in continuous conduction there
are ________ different conduction modes.
v) The output voltage of a three phase fully controlled converter operating in the
continuous conduction mode consists of segments of the input ac ________ voltage.
vi) The peak voltage appearing across any device of a three phase fully controlled
converter is equal to the ________ input ac ________ voltage.
vii) The input ac current of a three phase fully controlled converter has a ________ step
waveform.
viii) The input ac current of a three phase fully controlled converter contains only
_________ harmonics but no _________ harmonic.
ix) A three phase fully controlled converter can also operate in the _________ mode.
x) Discontinuous conduction in a three phase fully controlled converter is _________.
Answers: (i) diodes, thyristors; (ii) six; (iii) 120; (iv) six; (v) line; (vi) peak, line; (vii) six; (viii)
odd, tripler; (ix) inverting; (x) rare.
13.2.1 Analysis of the converter in the rectifier mode

The output voltage waveform can be written as
α α
v0 = V0 + ∑V
K=1,2
AK cos 6 Kωt + ∑V
K=1,2
BK sin 6 Kωt (13.1)
3 α+ π3 3 2 α+
π
⎛ π⎞
V0 = ∫
π α
v 0 dωt =
π
VL ∫α
3
sin ⎜ ωt + ⎟ dωt
⎝ 3⎠
3 2
= VL cosα (13.2)
π
6 α+ π3
VAK = ∫ v0 cos6 Kωt dωt
π α
6 α+ π ⎛ π⎞
= ∫ 3 2 VLsin ⎜ ωt + ⎟ cos6 ωt dωt
π α ⎝ 3⎠
3 2 ⎡ cos(6K +1)α cos(6K -1)α ⎤
= VL ⎢ - (13.3)
π ⎣ 6K +1 6K -1 ⎥⎦

6 α+ π3
π ∫α
VBK = v 0 sin6 Kωt dωt
6 α+ π3 ⎛ π⎞
= ∫ 2 VLsin ⎜ ωt + ⎟ sin6 ωt dωt
π α
⎝ 3⎠
3 2 ⎡ sin(6K +1)α sin(6K -1)α ⎤
= VL ⎢ - (13.4)
π ⎣ 6K +1 6K -1 ⎥⎦
1
3 α+
π
⎡ 3 3 ⎤2
π ∫α
V0RMS = 3
v02 dωt = VL ⎢1+ cos2α ⎥
⎣ 4π ⎦
The input phase current ia is expressed as
π
ia = i0 α ≤ ωt ≤ α +
3
2π 4π
ia = - i0 α+ ≤ ωt ≤ α +
3 3
5π
ia = i0 α+ ≤ ωt ≤ α + 2π
3
ia = 0 otherwise
From Fig. 13.2 it can be observed that i0 itself has a ripple at a frequency six times the input
frequency. The closed from expression of i0, as will be seen later is some what complicated.
However, considerable simplification in the expression of ia can be obtained if i0 is replaced by
its average value I0. This approximation will be valid provided the ripple on i0 is small, i.e, the
load is highly inductive. The modified input current waveform will then be ia which can be
expressed in terms of a fourier series as
I A0 α α
ˆ
i a ≈ ia = + ∑ I An cos nωt + ∑ I Bn sin nωt (13.5)
2 n=1 n=1
Where
1 α+2π
2π ∫α
I A0 = i a dωt = 0 (13.6)
1 α+2π
I An = ∫ i a cos nωt n≠0
π α
4I nπ nπ
= 0 cos sin cos nα (13.7)
nπ 6 2
2 3I 0 ⎛ π⎞
I An = ( -1) sin ⎜ Kπ ± ⎟ cos ( 6K ±1) α
K
∴
( 6K ±1) π ⎝ 2⎠ (13.8)
for n = 6K ±1, K = 0, 1, 2, 3 ....
IAn = 0 otherwise.

1 α+2π
π ∫α
I Bn = i a sin nωt dωt
4I nπ nπ
= 0 cos sin nα sin (13.9)
nπ 6 2
2 3I 0 ⎛ π⎞
I Bn = ( -1) sin ⎜ Kπ ± ⎟ sin ( 6K ±1) α
K
∴
( 6K ±1) π ⎝ 2⎠ (13.10)
for n = 6K ±1, K = 0, 1, 2, ....
IBn = 0 otherwise.
( -1) 2 3I0 sin ⎛ Kπ ± π ⎞ cos ⎡ 6K ±1 ωt - α ⎤

K
α
∴ ia = ∑ ⎜ ⎟ ⎣( )( )⎦ (13.11)
K =0 ( 6K ±1) π ⎝ 2⎠
in particular ia1 = fundamental component of ia
2 3
= I0 cos ( ωt - α ) (13.12)
π
2VL
From Fig. 13.2 v an = cos ωt (13.13)
3
∴ displacement angle φ = α. ∴ displacement factor = cosα (13.14)
I0
I ⎛ 6⎞ 2 3
distortion factor = a1 = ⎜ ⎟ I0 = (13.15)
Ia ⎝ π ⎠ 3 π
3
∴ Power factor = Displacement factor × Distortion factor = cosα (13.16)
π
π
The closed form expression for i0 in the interval α ≤ ωt ≤ α + can be found as follows
3
in this interval
di ⎛ π⎞
Ri 0 + L 0 + E = v0 = 2VLsin ⎜ ωt + ⎟ (13.17)
dt ⎝ 3⎠
( ωt - α )
- 2VLtanφ ⎛ π ⎞ E
i 0 = I1e +
sin ⎜ ωt + - φ ⎟ - (13.18)
Z ⎝ 3 ⎠ R
ωL
Where Z = R 2 + ω2 L2 , tanφ =
R
∴ R = Zcosφ, E = 2VLsinθ (from Fig. 13.2) (13.19)

( ωt - α )
- 2VL ⎡ ⎛ π ⎞ sinθ ⎤
∴ i 0 = I1e tanφ
+ ⎢sin ⎜ ωt + 3 - φ ⎟ - cosφ ⎥ (13.20)
Z ⎣ ⎝ ⎠ ⎦
Since i0 is periodic over π/3
i 0 ωt=α = i 0 ωt =α+ π (13.21)

3
2VL ⎡ ⎛ π ⎞ sinθ ⎤
∴ I1 + ⎢sin ⎜ α + 3 - φ ⎟ - cosφ ⎥
Z ⎣ ⎝ ⎠ ⎦
π
-
3tanφ 2VL ⎡ ⎛ 2π ⎞ sinθ ⎤
= I1e + ⎢sin ⎜ α + 3 - φ ⎟ - cosφ ⎥
Z ⎣ ⎝ ⎠ ⎦
2VL sin ( φ - α )
OR I1 = π
(13.22)
Z -
1- e 3tanφ
⎡ (ω t - α ) ⎤
2VL ⎢ sin ( φ - α ) - tanφ ⎛ π ⎞ sinθ ⎥
∴ i0 = e + sin ⎜ ω t + - φ ⎟ - (13.23)
Z ⎢ -
π
⎝ 3 ⎠ cosφ ⎥
⎣ 1- e 3tanφ
⎦
To find out the condition for continuous conduction it is noted that in the limiting case of
π
i 0 min=0 , Now if θ ≤ α + then i0 is minimum at ωt = α. ∴ Condition
3
for continuous conduction is i0 ωt=α ≥ 0 . However discontinuous conduction is rare in these
conversions and will not be discussed any further.
13.2.2 Analysis of the converter in the inverting mode.

In all the analysis presented so far it has been assumed that α < 90°. It follows from equation
13.2 that the output dc voltage will be positive in this case and power will be flowing from the
three phase ac side to the dc side. This is the rectifier mode of operation of the converter.
However if α is made larger than 90° the direction of power flow through the converter will
reverse provided there exists a power source in the dc side of suitable polarity. The converter in
that case is said to be operating in the inverter mode. It has been explained in connection with
single phase converters that the polarity of EMF source on the dc side [Fig. 13.1(a)] would have
to be reversed for inverter mode of operator. Fig. 13.3 shows the circuit connection and wave
forms in the inverting mode of operation where the load current has been assumed to be
continuous and ripple free.

Analysis of the converter in the inverting mode is similar to its rectifier mode of operation. The
same expressions hold for the dc and harmonic compounds in the output voltage and current.
The input supply current Fourier series is also identical to Equation 13.8. In particular
3 2
V0 = VL cosα (13.24)
π
2 3
i a1 = I0 cos(ωt - α) (13.25)
π

For values of α in the range 90° < α < 180° it is observed from Fig. 13.3(b) that the average dc
voltage is negative and the displacement angle φ of the fundamental component of the input ac
line current is equal to α > 90°. Therefore, power in the ac side flows from the converter to the
source.
It is observed form Fig. 13.3(b) that an outgoing thyristor (thyristor T6 in Fig. 13.3(b)) after
commutation is impressed with a negative voltage of duration β = π – α. For successful
commutation of the outgoing thyristor it is essential that this interval is larger than the turn off
time of the thyristor i.e,
β ≥ ωtq , tq is the thyristor turn off time
Therefore π - α ≥ ωtq or α ≤ π - ωtq .
Which imposes an upper limit on the value of α. In practice this upper value of α is further
reduced due to commutation overlap.
Exercise 13.2
1. A three phase fully controlled bridge converter operating from a 3 phase 220 V, 50 Hz
supply is used to charge a battery bank with nominal voltage of 240 V. The battery bank
has an internal resistance of 0.01 Ω and the battery bank voltage varies by ± 10% around
its nominal value between fully charged and uncharged condition. Assuming continuous
conduction find out.
(i) The range of firing angle of the converter.

(ii) The range of ac input power factor.
(iii) The range of charging efficiency.
When the battery bank is charged with a constant average charging current of 100 Amps through
a 250 mH lossless inductor.
Answer: The maximum and minimum battery voltages are, VB Min = 0.9 × VB Nom = 216 volts
and VB Max = 1.1 × VB Nom = 264 volts respectively.
Since the average charging current is constant at 100 A.
V0 Max = VB Max + 100 × RB = 264 + 100 × 0.01 = 265 volts

V0 Min = VB Min + 100 × RB = 216 + 100 × 0.01 = 217 volts.
(i) But V0 Max = 3 2 VL cos α Min ∴ α Min = 26.88º

π
V0 Min = 3 2 VL cos α Max ∴ α Max = 43.08º
π
(ii) Input power factor is maximum at minimum α and vice versa

∴ p.f. max = Distortion factor × Displacement factor Max = 3 × cos α min = 0.85
π
p.f. Min = 3 × cos α Max = 0.697
π
2
(iii) Power loss during charging = I0RMs RB
2 2
VK VAK + VBK
But I 2
0RMs = I + I + I + ........ and I K ≈
2
0
2
1
2
2 =
6KωL 6 2KωL
For α = α Min
VA1 = 0.439 V, VB1 = 48.48 V, I1 = 0.073 Amps
VA2 = 10.76, VB2 = 20.15 V, I2 = 0.017 Amps.
∴ 2
J 0RMs ≈ 1002 + (0.073) 2 + (0.017) 2 = 10000.00562
∴ Ploss = 100 watts.
At α Min, P0 = I0 × VB Max = 26400 watts.
∴ Charging efficiency = 26400 = 99.6%

26400 + 100
Similarly for α Max, 2

I0RMs ≈ I 02
∴ Ploss = 100 watts
P0 = I0 × VB Min = 21600 watts.
∴ Charging efficiency = 21600 = 99.54%

21600 + 100
2. A three phase fully controlled converter operates from a 3 phase 230 V, 50 Hz supply
through a Y/Δ transformer to supply a 220 V, 600 rpm, 500 A separately excited dc
motor. The motor has an armature resistance of 0.02 Ω. What should be the transformer
turns ratio such that the converter produces rated motor terminal voltage at 0º firing
angle. Assume continuous conduction. The same converter is now used to brake the
motor regeneratively in the reverse direction. If the thyristors are to be provided with a
minimum turn off time of 100 μs, what is the maximum reverse speed at which rated
braking torque can be produced.
Answer: From the given question

3 2 V = 220 ∴ VL = 162.9 V
π L
Where VL is the secondary side line and also the phase voltage since the secondary
side is Δ connected.

Primary side phase voltage = 230 V = 132.79 V
3
∴ Turns ratio = 132.79 = 1:1.2267 .
162.9
During regenerative braking in the reverse direction the converter operates in the
inverting mode.
tq Min = 100μS ∴ β Min = ωtq Min = 1.8o

∴ α Max = 180 – β Min = 178.2º
∴ Maximum negative voltage that can be generated by the converter is
3 2 V cos 178.2o = - 219.89 V

π L
For rated braking torque Ia = 500 A
∴ Eb = Va – Iara = - 229.89 V.
At 600 RPM Eb = 220 – 500 × 0.02 = 210 V.
∴ Max reverse speed is 229.89 × 600 = 656.83 RPM .

210
13.3 Higher pulse number converters and dual converter

The three phase fully controlled converter is widely used in the medium to moderately high power
applications. However in very large power applications (such as HV DC transmission systems)
the device ratings become impractically large. Also the relatively low frequency (6th in the dc
side, 5th and 7th in the ac side) harmonic voltages and currents produced by this converter become
unacceptable. Therefore several such converters are connected in series parallel combination in
order to increase the voltage / current rating of the resulting converter. Furthermore if the
component converters are controlled properly some lower order harmonics can be eliminated both
from the input and output resulting in a higher pulse converter.

Fig. 13.4(a) schematically represents series connection of two six pulse converters where as Fig.
13.4(b) can be considered to be a parallel connection. The inductance in between the converters
has been included to limit circulating harmonic current. In both these figures CONV – I and
CONV – II have identical construction and are also fired at the same firing angle α. Their input
supplies also have same magnitude but displaced in phase by an angle φ. Then one can write
∞ α
3 2
v 01 = VL cosα + ∑ VAK cos 6 Kωt + ∑ VBK sin 6 Kωt (13.26)
π K=1 K=1

α α
3 2
v02 = VL cosα + ∑ VAK cos 6 K ( ωt - φ ) + ∑ VBK sin 6 K ( ωt - φ ) (13.27)
π K=1 K=1
Therefore for Fig 13.4(a)
6 2
v 0 = v01 + v02 = VL cosα +
π
α
(13.28)
2∑ cos3Kφ ⎡⎣ VAK cos3K ( 2ωt - φ ) + VBK sin3K ( 2ωt - φ ) ⎤⎦
K=1
Now if cos 3Kφ = 0 for some K then the corresponding harmonic disappear from the fourier
series expression of v0.
In particular if φ = 30° then cos 3Kφ = 0 for K = 1, 2, 3, 5…….

This phase difference can be obtained by the arrangement shown in Fig. 13.4(c).
Then
α
6 2
v0 = VL cosα + 2∑ [ VAm cos 12mωt + VBm sin 12mωt ] (13.29)
π m=1
It can be seen that the frequency of the harmonics present in the output voltage has the form
12ω, 24ω, 36ω ………..
Similarly it can be shown that the input side line current iABC have harmonic frequency of the
form
11ω, 13ω, 23ω, 25ω, 35ω, 37ω, ………….
Which is the characteristic of a 12 pulse converter.
In a similar manner more number of 3 phase 6 pulse converters can be connected in series /
parallel and the φ angle can be adjusted to obtain 18 and 24 pulse converters.
One of the shortcomings of a three phase fully controlled converter is that although it can
produce both positive and negative voltage it can not supply current in both directions.
However, some applications such as a four quadrant dc motor drive require this capability from
the dc source. This problem is easily mitigated by connecting another three phase fully
controlled converter in anti parallel as shown in Fig. 13.5 (a). In this figure converter-I supplies
positive load current while converter-II supplies negative load current. In other words converter-
I operates in the first and fourth quadrant of the output v – i plane whereas converter-II operates
in the third and fourth quadrant. Thus the two converters taken together can operate in all four
quadrants and is capable of supplying a four quadrant dc motor drive. The combined converter is
called the Dual converter.

Obviously since converter-I and converter-II are connected in antiparallel they must produce the
same dc voltage. This requires that the firing angles of these two converters be related as
α2 = π – α 1 (13.30)

Although Equations 13.30 ensures that the dc voltages produced by these converters are equal
the output voltages do not match on an instantaneous basis. Therefore to avoid a direct short
circuit between two different supply lines the two converters must never be gated
simultaneously. Converter-I receives gate pulses when the load current is positive. Gate pulses
to converter-II are blocked at that time. For negative load current converter-II thyristors are fired
while converter-I gate pulses are blocked. Thus there is no circulating current flowing through
the converters and therefore it is called the non-circulating current type dual converter. It
requires precise sensing of the zero crossing of the output current which may pose a problem
particularly at light load due to possible discontinuous conduction. To overcome this problem an
interphase reactor may be incorporated between the two converters. With the interphase reactor
in place both the converters can be gated simultaneously with α2 = π – α1. The resulting
converter is called the circulating current type dual converter.
13.4 Gate Drive circuit for three phase fully controlled converter
Several schemes exist to generate gate drive pulses for single phase or three phase converters. In
many application it is required that the output of the converter be proportional to a control
voltage. This can be achieved as follows.
In either single or three phase converters

V0 ∝ cosα or α = cos-1 V0 K1 (13.31)
To get V0 ∝ v c α = cos -1 Vc K (13.32)
The following circuit can be used to generate “α” according to equation 13.32.

In the circuit of Fig. 13.6(a) a phase shift network is used to obtain a waveform leading vi by 90º.
The phasor diagram of the phase shift circuit is shown in Fig. 13.6(b). The output of the phase
shift waveform (and its inverse) is compared with vc. The firing pulse is generated at the point
when these two waveforms are equal. Obviously at-this instant
vc ∝ Vs cosα or α = cos-1 vc Vs (13.33)
Therefore this method of generation of converter firing pulses is called “inverse cosine” control.
The output of the phase shift network is called carrier waveform.
Similar technique can be used for three phase converters. However the phase shift network here
consists of a three phase signal transformer with special connections as shown in Fig. 13.7.

The signal transformer uses three single phase transformer each of which has two secondary
windings. The primary windings are connected in delta while the secondary windings are
connected in zigzag. From Fig. 13.1 (c) T2 is fired α angle after the positive going zero crossing
of vbc. Therefore, to implement inverse cosine the carrier wave for T2 must lead vbc by 90º. This
waveform is obtained from zigzag connection of the winding segments a1a2 and c1c2 as shown in
Fig. 13.7(a). The same figure also shows the zigzag connection for other phase. The voltage
across each zigzag phase can be used to fire two thyristors belonging to the same phase leg using
a circuit similar to Fig. 13.6 (a). The phase shift network will not be required in this case.

Exercise 13.3
i) Higher pulse number converters can be realized by __________ and _______

connection of six pulse converters.
ii) Constituent six pulse converters of a 12 pulse converter have _________ firing
angles.
iii) The input supply voltages to the converters of a 12 pulse converter have ________
magnitudes and are phase shifted from one another by _________ degrees.
iv) The input supply to a 12 pulse converter can be obtained through a _________
connected transformer.
v) Dual converters are used for supplying ________ quadrant dc motor drives.
vi) In a dual converter if one converter is fired at an angle ‘α’ the other has to be fired
at _________.
vii) In ___________ current dual converter only one converter conducts at any time.
viii) In a circulating current type dual converter an __________ is used between the
converters to limit the circulating current.
ix) To obtain a linear control relation between the control voltage and the output dc
voltage of a converter ___________ control logic is used.
x) In a three phase fully controlled converter the carrier waves for firing pulse
generation are obtained using three ___________ connected single phase
transformers.
Answers: (i) Series, parallel; (ii) same, (iii) equal, 30, (iv) star – star – delta; (v) four; (vi) π - α,
(vii) non-circulating ; (viii) inductor, (ix) inverse-cosine; (x) delta-zigzag.
2. A 220V, 750 RPM, 200A separately excited dc motor has an armature resistance of 0.05
Ω. The armature is fed from a three phase non circulating current dual converter. If the
forward converter operates at a firing angle of 70º
i) At what speed will the motor deliver rated torque.

ii) What should be the firing angle in the regenerative braking mode when the motor
delivers half the rated torque at 600 rpm.
Assume continuous conduction. Supply voltage is 400 V.
Answer:
i) The output voltage = 3 2 × 400 cos 70o = 184.7 V
π

∴ Eb = Va – Iara = 184.7 – 200 × 0.05 = 174.75 V.
∴ Operating speed = 174.75 × 750 = 624 RPM .

220 - 0.05 × 200
ii) E b 600RPM = - 600 × 210 = -168V1 Ia = 100A

750
∴ Va = - Eb + Iara = – 173 r.
Va = - 173 = 3 2 400 cos α ∴ α = 108.67º

π
3. What will happen if the signal transformers generating the carrier wave have delta –
double star connection instead of delta-zigzag connection.
Answer: With delta-double star connection of the signal transformers the carrier wave forms
will be in phase with the line voltage waveforms. Therefore, without a phase shift
network it will not be possible to generate carrier waveforms which are in quadrature
with the line voltages. Hence inverse casine control law cannot be implemented.
References
1. “Power Electronics”; P.C. Sen; Tata-McGrawhill publishing company limited; 1995.
2. “Power Electronics, Converters, Applications and Design”, Mohan, Undeland, Robbins;
John Willey and Sons Inc; Third Edition, 2003.

Lesson Summary
• A three phase fully controlled converter is realized by replacing the diodes of an
uncontrolled converter with thyristors.
• A three phase fully controlled converter can operate either as a rectifier or as an inverter.
• The output voltage of a three phase fully controlled converter contains multiple of sixth
harmonic of the input frequency in addition to the dc component.
• The input current of a three phase fully controlled converter contains only odd harmonics
other than tripler harmonics.
• The input current displacement factor of a three phase fully controlled converter is cos α.
α being the firing angle.
• In the continuous conduction mode a three phase fully controlled converter may operate
in the inverting mode by increasing α beyond 90º.
• In the inverting mode the firing angle should be less than 180º for safe commutation of
the thyristors.
• Several units of three phase fully controlled converters can be connected in series parallel
to form higher pulse number (12, 18, 24 etc) converters.
• In higher pulse number converters all component converters are fired at the same firing
angle while their input supplies are phase shifted from one another by a predetermined
angle.
• Two three phase fully controlled converter can be connected in anti parallel to form a
dual converter which can operate in all four quadrants of the V-I plane.
• Dual converters can be of circulating and non circulating current type.
• Fully controlled converters employ “inverse casine control” strategy for generating firing
pulses which gives linear relationship between the output voltage and the control voltage.
In a three phase fully controlled converter, a three phase delta/zig-zag connected signal
transformer is used to generate the required carrier waves for this purpose.

Practice problems and answers
1. A three phase fully controlled converter operates from a 3 phase 230 V, 50 Hz supply and
supplies a resistive load of 25 Ω at a firing angle 90º. Find out the power supplied to the
load.
2. A three phase fully controlled converter supplies a 220 V 1500 RPM, 50 A separately
excited dc motor from a 230 V, 3 phase, 50 Hz supply. The motor holds an overhauling
load at 1000 RPM while producing full load torque. The motor has an armature
resistance of 0.2 Ω. What should be the firing angle? Assume continuous conduction.
3. What precaution should be taken in the gate drive circuit so that a three phase fully
controlled converter can continue to operate even when the load current becomes
discontinuous.
Answers
1.
The figure above shows the output voltage with α = 90º and a resistive load. Since the load is
resistive the load current becomes zero when the voltage becomes zero. Both the voltage and
amount remains zero thereafter till the next thyristor is fired.
Therefore for 5π ≤ ωt ≤ π
6
v0 = Vbc = 2VL sinωt
π ≤ ωt ≤ 7π
6
v0 = 0
∴ V0 RMS = 3 ∫5π 2VL2 sin 2 ωt dωt
π
π 6
= VL 3 ∫5π (1 - cos2ωt ) dωt

π
π 6
2
V0
= VL 1 − 3 ∫5π cos2ωt dωt
RMS π
∴ P0 =
R 2 π 6
= 183 Watts
= VL 1 − 3 3
2 4π
= 67.65 V
2. To hold the overhauling load the motor must operate in the regenerative braking mode.
At 1000 RPM Eb = 220 - 50× 0.2 ×1000 = 140 volts
1500
To supply full load torque, the motor armature current = 50 A.
∴ Supply voltage = Va = Eb + Iara = 140 + 50 × 0.2 = 150 V in the reverse direction.
∴ 3 2 VL cosα = - 150V ∴ α = 118.9º.

π
3. With reference to the conduction diagram of problem – 1 it can be seen that the load
current becomes zero 30º after a new thyristor is fired (for example, T2). Therefore, both
the conducting thyristor (T1 and T2 in this case) turns off. However, when T3 is fired the
converter will be unable to resume operation from T2T3 mode unless T2 is fired
simultaneously. Similar explanation holds for all other thyristor firing. Therefore, to
ensure that the converter operates properly even under discontinuous load current
condition the final gate pulse for a particular thyristors must be generated by logically
“ANDing” the outputs of its own firing circuit with the output of the firing circuit of the
thyristor in the commutation sequence as shown in the table next below
To generate the
gate pulse of : T1 T2 T3 T4 T5 T6
AND the outputs of : T1 & T2 T2 & T3 T3 & T4 T4 & T5 T5 & T6 T6 & T1

Module
2
AC to DC Converters
Lesson
14
Operation and Analysis of
Three Phase Half
Controlled Converter
• Draw the circuit diagram and waveforms of different variables associated with a three
phase half controlled converter.
• Identify the constructional and operational difference between a three phase fully
controlled and half controlled converter.
• Calculate the average and RMS value of the output dc voltage.
• Calculate the displacement factor, distortion factor and power factor of the input ac line
current.
• Calculate the Fourier series components of the output voltage and input current
waveforms.
• Derive the closed form expression for output dc current and hence identify continuous or
discontinuous conduction mode of the converter.

14.1 Introduction
Three phase fully controlled converters are very popular in many industrial applications
particularly in situations where power regeneration from the dc side is essential. It can handle
reasonably high power and has acceptable input and output harmonic distortion. The
configuration also lends itself to easy series and parallel connection for increasing voltage and
current rating or improvement in harmonic behavior. However, this versatility of a three phase
fully controlled converters are obtained at the cost of increased circuit complexity due to the use
of six thyristors and their associated control circuit. This complexity can be considerably reduced
in applications where power regeneration is not necessary. In that case three thyristors of the top
group or the bottom group of a three phase fully controlled converter can be replaced by three
diodes. The resulting converter is called a three phase half controlled converter. Replacing three
thyristors by three diodes reduces circuit complexity but at the same time prevents negative
voltage appearing at the output at any time. Therefore the converter cannot operate in the
inverting mode.
The three phase half controlled converter has several other advantages over a three phase
fully controlled converter. For the same firing angle it has lower input side displacement factor
compared to a fully controlled converter. It also extends the range of continuous conduction of
the converter. It has one serious disadvantage however. The output voltage is periodic over one
third of the input cycle rather than one sixth as is the case with fully controlled converters. This
implies both input and output harmonics are of lower frequency and require heavier filtering.
For this reason half controlled three phase converters are not as popular as their fully controlled
counterpart.
Although, from the point of view of construction and circuit complexity the half controlled
converter is simpler compared to the fully controlled converter, its analysis is considerably more
difficult. In this lesson the operating principle and analysis of a three phase half controlled
converter operating in the continuous conduction mode will be presented.
14.2 Operating principle of three phase half controlled converter

Fig. 14.1(a) shows the circuit diagram of three phase half controlled converter supplying an R-L-
E load. In the continuous conduction mode only one thyristor from top group and only one diode
from the bottom group conduct at a time. However, unlike fully controlled converter here both
devices from the same phase leg can conduct at the same time. Hence, there are nine conducting
modes as shown in Fig. 14.1(b).

Now consider the conducting and blocking state of D2. In the blocking state the voltage across
D2 is either vac or vbc. Hence, D2 can block only when these voltages are negative. Taking vbc as
the reference phasor (i.e., v bc = 2VL sinωt ) D2 will block during 2π/3 ≤ ωt ≤ 2π and will
conduct in the interval 0 ≤ ωt ≤ 2π/3 . Similarly it can be shown that D4 and D6 will conduct
during 2π/3 ≤ ωt ≤ 4π/3 and 4π/3 ≤ ωt ≤ 2π respectively.
Next consider conduction of T1. The firing sequence of the thyristor is T1 → T3 → T5.
Therefore before T1 comes into conduction T5 conducts and voltage across T1 is
v ac = 2VL sin (ωt + π/3) . If the firing angle of T1 is α then T1 starts conduction at
ωt = α - π/3 and conducts upto α + π/3 . Similarly T3 and T5 conducts during α + π/3 ≤ ωt ≤ α + π
and α + π ≤ ωt ≤ 2π + α - π/3 . From this discussion the following conduction diagrams can be
drawn for continuous conduction mode.

Exercise 14.1
Fill in the blanks(s) with appropriate word(s).
i. A three phase half controlled converter has ________________ thyristors and

________________ diodes.
ii. A three phase half controlled converter has ________________ conduction modes as
compared to ________________ of a fully controlled converter.
iii. A three phase half controlled converter can not operate in the ________________ mode.
iv. Unlike a three phase fully controlled converter the devices in the ________________ phase
leg of a half controlled converter can conduct at a given time. These conduction modes are
called ________________ modes.
v. In a three phase half controlled converter only ________________ conduction modes
appear at the same time.

vi. ________________ modes appear only when the firing angle of the converter is greater
than ________________ degrees.
vii. In a three phase half controlled converter the diodes conduct in a manner similar to a
________________ converter where as the thyristors conducts similar to a
________________ converter.
viii. The input current of a three phase half controlled converter does not have
________________ cycle symmetry.
Answer: (i) three, three; (ii) nine, six; (iii) inverter; (iv) same, free wheeling; (v) six; (vi) free
wheeling, 60; (vii) uncontrolled, controlled; (viii) quarter.
14.3 Analysis of three phase half controlled converters

Fig. 14.2 (a) and (b) also shows the waveforms of v0 and i0 (for α < π/3 and α > π/3 ) both of
which are periodic over one third of the input voltage time period. Therefore examining v0 for
the conduction period of any one thyristor (for example T1) will be sufficient to deduce
information regarding output voltage. For example the average value of v0 can be found as
follows.
With T1 conducting there can be three conduction modes namely, T1D6, T1D2 and T1D4.
Now T1 conducts in the interval α - π ≤ ω t ≤ α + π

3 3
D2 conducts in the interval 0 ≤ ωt ≤ 2 π
3
D4 conducts in the interval 2 π ≤ ωt ≤ 4 π
3 3
D6 conducts in the interval 4 π ≤ ωt ≤ 2π
3
∴Conduction interval T1D6 exists only if α ≤ π

3
Conduction interval T1D4 exists only if α > π
3
So for α ≤ π
3
In the interval α - π ≤ ωt ≤ 0
3
(
v0 = vab = 2VL sin ωt + 2π
3 ) (14.1)
0 ≤ ωt ≤ α + π
3
(
v0 = vac = 2VL sin ωt + π
3) (14.2)
3 2VL ⎡ 0 ⎛ π⎞ α+
π
⎛ π⎞ ⎤
V0 = ⎢ ∫α - π ⎜
sin ωt + 2 dωt+ ∫0 sin ωt + dωt
3
⎟ ⎜ ⎟ ⎥
2π ⎣ 3 ⎝ 3⎠ ⎝ 3⎠ ⎦

=
3 2VL ⎡
2π ⎢⎣ ( 3 ) 3 3 (
cos α + π - cos 2π + cos π - cos α + 2π ⎤)
3 ⎥⎦
(14.3)
3 2
or, V0 = VL (1 + cosα) (14.4)
2π
For α> π, In the interval α - π ≤ ωt ≤ 2π
3 3 3
(
v0 = vac = 2VL sin ωt + π
3 ) (14.5)
for 2π ≤ ωt ≤ α + π
3 3
v0 = 0 (14.6)
3 2VL ⎡ 2π ⎛ π⎞ ⎤
∴ V0 = ⎢ ∫ π sin ⎜ ωt +
2π ⎣ α - 3 ⎝
⎟
3⎠
dωt ⎥
⎦
3 2
= VL (1 + cosα)
2π
RMS value of v0 can be found in a similar manner and is left as an exercise.
From the waveforms of Fig. 14.2, v0 is periodic over one third of the input cycle. Therefore one
can write
α
v 0 = V0 + ∑ [ VAn cos 3nωt + VBn sin 3nωt ] (14.8)
n=1
π
3α+
π∫
VAn = π
3
v0 cos 3nωt dωt (14.9)
α-
3
π
3α+
π∫
VBn = 3
π v0 sin 3nωt dωt (14.10)
α-
3
For α ≤ π From equations 14.1 and 14.2

3
3⎡ 0 ⎛ π⎞ α+
π
⎛ π⎞ ⎤
VAn = ⎢ 2VL ∫ π sin ⎜ ωt + 2 ⎟ cos3nωtdωt + 2VL ∫ 3 sin ⎜ ωt + ⎟ cos3nωtdωt ⎥
π⎣ α -
3 ⎝ 3⎠ 0
⎝ 3⎠ ⎦
⎡ 0 ⎧ ⎛ π⎞ ⎛ π⎞ ⎫⎤
⎢ ∫α - π ⎨sin ⎜ (3n + 1)ωt + 2 ⎟ + sin ⎜ (1 - 3n)ωt + 2 ⎟ dωt ⎬⎥
3 2VL ⎢ 3 ⎩ ⎝ 3⎠ ⎝ 3⎠ ⎭⎥
=
2π ⎢ α + 3 ⎧ ⎛ π
π⎞ ⎛ π⎞ ⎫ ⎥
⎢+ ∫ ⎨sin ⎜ (3n + 1)ωt + ⎟ - sin ⎜ (3n -1)ωt - ⎟ dωt ⎬ ⎥
⎢⎣ 0 ⎩ ⎝ 3⎠ ⎝ 3⎠ ⎭ ⎥⎦

⎡ π
⎤
{ } cos {(3n - 1)ωt - 2π/3}
α- 0
⎢ cos (3n + 1)ωt + 2π/3 3
⎥
+
⎢ 3n + 1 3n - 1 π ⎥
3 2VL ⎢ 0 α-
3 ⎥
= ⎢ π⎥
(14.11)
2π
⎢ cos {(3n + 1)ωt + π/3} cos {(3n - 1)ωt - π/3} 3 ⎥
0 α+
⎢+ + ⎥
⎢⎣ 3n + 1 α+
π 3n - 1 0 ⎥⎦
3
Therefore
⎡1 + cos [ (3n + 1)(α - π/3) + 2π/3] - cos [ (3n + 1)(α + π/3) + π/3] ⎤
3 2VL ⎢ 3n + 1
⎥
VAn = ⎢ ⎥
2π ⎢ cos [ (3n - 1)(α + π/3) - π/3] - cos [ (3n - 1)(α - π/3) - 2π/3] -1 ⎥
⎢+ ⎥
⎣ 3n - 1 ⎦
⎡1 - 2sin [ (3n + 1)α + π/2] sin [ π/6 - (3n + 1) π/3] ⎤
3 2VL ⎢ 3n + 1
⎥
= ⎢ ⎥
2π ⎢ 1 + 2sin [ (3n - 1)α - π/2] sin [ π/6 + (3n - 1) π/3] ⎥
⎢- ⎥
⎣ 3n - 1 ⎦
3 2VL ⎡1+ 2sin(6n + 1)π/6 cos(3n + 1)α 1- 2sin(6n - 1)π/6 cos(3n - 1)α ⎤
= -
2π ⎢⎣ 3n + 1 3n - 1 ⎥⎦
3 2VL ⎡1+ (-1) n cos(3n + 1)α 1+ (-1) n cos(3n - 1)α ⎤
= - (14.12)
2π ⎢⎣ 3n + 1 3n - 1 ⎥
⎦
Similarly,
3 2VL ⎡ 0 ⎛ π⎞ α+
π
⎛ π⎞ ⎤
VBn = ⎢ ∫α - π ⎜
sin ωt + 2 sin3nωtdωt + ∫ sin ⎜ ωt + ⎟ sin3nωtdωt ⎥ (14.13)
3
⎟
π ⎣ 3 ⎝ 3⎠ 0
⎝ 3⎠ ⎦
⎡ 0 ⎧ ⎡ π⎤ ⎡ π ⎤⎫ ⎤
⎢ ∫α - π ⎨cos ⎢ (3n - 1)ωt - 2 ⎥ - cos ⎢ (3n + 1)ωt + 2 ⎥ ⎬ dωt ⎥
3 2VL ⎢ 3 ⎩ ⎣ 3⎦ ⎣ 3 ⎦⎭ ⎥
or, VBn =
2π ⎢ α + 3 ⎧ ⎡π
π⎤ ⎡ π ⎤⎫ ⎥
⎢+ ∫ ⎨ cos ⎢ (3n - 1)ωt - ⎥ - cos ⎢ (3n + 1)ωt + ⎥ ⎬ dωt ⎥
⎣⎢ ⎩ ⎣ 3⎦ ⎣ 3 ⎦⎭ ⎦⎥
0
⎡ sin {(3n - 1)ωt - 2π/3} 0 sin {(3n + 1)ωt + 2π/3}

0
⎤
⎢ - ⎥
⎢ 3n - 1 π 3n + 1 π ⎥
3 2VL ⎢ α-
3
α-
3
⎥
=
2π ⎢ π
α+ ⎥
π
⎢ + sin {(3n - 1)ωt - π/3} 3 - sin {(3n + 1)ωt + π/3} 3 ⎥

α+
⎢ 3n - 1 3n + 1 ⎥
⎣ 0 0 ⎦

⎡ sin [ (3n - 1)(α + π/3) - π/3] - sin [ (3n - 1)(α - π/3) - 2π/3] ⎤
3 2VL ⎢ ⎥
⎢ 3n - 1 ⎥
=
2π ⎢ sin [ (3n + 1)(α + π/3) + π/3] - sin [ (3n + 1)(α - π/3) + 2π/3] ⎥
⎢- ⎥
⎣ 3n + 1 ⎦
⎡ cos [ (3n - 1)α - π/2] sin [ π/6 + (3n - 1) π/6] ⎤

3 2VL ⎢ 3n - 1
⎥
= ⎢ ⎥
π ⎢ cos [ (3n + 1)α + π/2] sin [ (3n + 1)π/6 - π/6] ⎥
⎢- ⎥
⎣ 3n + 1 ⎦
3 2VL ⎡ sin(3n + 1)α sin(3n - 1)α ⎤ nπ
= ⎢ + ⎥ sin
π ⎣ 3n + 1 3n - 1 ⎦ 2
3 2 nπ ⎡ sin(3n + 1)α sin(3n - 1)α ⎤

∴ VBn = VL sin ⎢ + (14.14)
π 2 ⎣ 3n + 1 3n - 1 ⎥⎦
Similar analysis can be done for α > π

3
To find out the Fourier series of the input ac line current the load may be replaced by a constant
current source having the same value as the average load current. This approximation will be
valid provided the load current ripple is relatively small. With this assumption the last waveform
of Fig. 14.2(b) can be redrawn as follows.
∴ α - π ≤ ωt ≤ 2π ia = I0
3 3
α + π ≤ ωt ≤ 4π ia = - I0
3 3
otherwise ia = 0

α
i a = ∑ [ I an cos nωt + I bn sin nωt ] (14.15)
n=1
I an = 1 ∫ i a cos nωt dωt

2π
π 0
⎡ 2π 4π ⎤
= 1 ⎢ ∫ 3 π I 0 cos nωt dωt - ∫
I0 cos nωt dωt ⎥
3
π ⎣ α- 3 α+ π
3 ⎦
I0 ⎡ sin nωt 2 3 ⎤
π 4π
= ⎢ - sin nωt 3
⎥
π ⎢ n α- π n α+ π ⎥
⎣ 3 3 ⎦
=
I0 ⎡ 2nπ
nπ ⎢⎣
sin
3 3 ( ) 3 (
- sin n α - π + sin n α + π - sin 4nπ ⎤
3 ⎥⎦ )
2I
= 0 ⎡sin 2nπ + cos nα sin nπ ⎤
nπ ⎢⎣ 3 3 ⎥⎦
2I0
or, Ian = ⎡⎣cos nα - (- 1) n ⎤⎦ sin nπ (14.16)
nπ 3
I bn = 1 ∫ i a sin nωt dωt

2π
π 0
⎡ 2π 4π ⎤
= 1 ⎢ ∫ 3 π I 0 sin nωt dωt - ∫
I0 sin nωt dωt ⎥
3
π ⎣ α- 3 α+ π
3 ⎦
I ⎡ α- π 4π ⎤
= 0 ⎢ cos nωt π 3 + cos nωt 3 π ⎥
nπ ⎣ 2
3
α +
3⎦
I
nπ ⎣ 3 3 3 ( )
= 0 ⎡⎢sin 4nπ - cos 2nπ + cos n α - π - cos n α + π ⎤⎥
3 ⎦ ( )
2I
= 0 sin nα sin nπ (14.17)
nπ 3
For the fundamental component n = 1
3I 0
i a1 =
π
[ cosωt + cosα cosωt + sinα sinωt ]
3I0
=
π
[cosωt + cos(ωt - α)]
=
2 3I0
π
cos α cos ωt - α
2 2 ( ) (14.18)
∴ Displacement factor = cos α (14.19)

2
6 I cos α
I 6
Distortion factor = a1 = π 0 2= cos α (14.20)
Ia π (π - α) 2
I0 π - α
π

∴ Power factor = Distortion factor × Displacement factor
6 3
cos 2 α = (1 + cosα) (14.21)
π (π - α) 2 2(π - α) π
A closed form expression for i0 can be found as follows
In the interval 0 < ωt ≤ α + π v0 = vac

3
di
∴ L 0 + Ri0 + E = vac = 2VL sin ωt +
dt
π
3 ( ) (14.22)
( )
ωt
2VL ⎡ ⎤
sin ωt + π - φ - sinθ ⎥
-
∴ i 0 = Ie tanφ + ⎢ (14.23)
Z ⎣ 3 cosφ ⎦
Where tanφ = ωL , Z = R 2 + ω 2 L2 and E = 2VL sinθ (14.24)
R
At ωt = α + π
3
( )
( α + π/3)
2VL ⎡ ⎤
sin α - φ + 2π - sinθ ⎥
-
i 0 = I1 = Ie tanφ + ⎢ (14.25)
Z ⎣ 3 cosφ ⎦
In the interval α + π ≤ ωt ≤ 2π v0 = vbc

3 3
di 0
∴ L + Ri 0 + E = v bc = 2VL sinωt (14.26)
dt
( ωt - α - π/3)
2VL ⎡ ⎤
sin ( ωt - φ ) - sinθ ⎥
-
∴ i 0 = I 2 e tanφ + (14.27)
Z ⎢⎣ cosφ ⎦
At ωt = α + π
3
i0 = I2 +
2VL ⎡
Z ⎣ ⎢ 3 (⎤
sin α + π - φ - sinθ ⎥ = I1
cosφ ⎦ ) (14.28)
( α + π/3)
- 2VL
∴ I2 = Ie tanφ
sin ( α - φ )
- (14.29)
Z
( ωt ) ( ωt - α - π/3)
- 2VL ⎡ -
sinθ ⎤
∴ i 0 = Ie tanφ
+ ⎢sin ( φ - α ) e tanφ + sin ( ωt - φ ) - ⎥ (14.30)
Z ⎢ cosφ ⎥
⎣ ⎦
( )
2π ⎡ ( α - π/3) ⎤
2VL
) tanφ - sin φ - 2π - sinθ ⎥
-
i0 ωt = 2π
= Ie 3tanφ
+ ⎢ (sin φ - α e (14.31)
Z ⎢⎣ 3 cosφ ⎥
3
⎦
i0 ωt =
2π
3
= i0 ωt = 0
= I+
2VL ⎡
Z ⎢⎣ (
sin π - φ - sinθ ⎥
3 ) ⎤
cosφ ⎦
(14.32)

( α - π/3)
⎛ - 2π ⎞ 2VL ⎡ ⎤
∴ I ⎜1 - e 3tanφ ⎟ = ⎢sin ( φ - α ) e tanφ + sinφ ⎥
⎝ ⎠ Z ⎢ ⎥⎦
⎣
∴ for 0 < ωt ≤ α + π
3
⎡ ( ωt - α - π/3) - ωt ⎤
( )
-
2VL ⎢ e tanφ sinφ e tanφ π sinθ ⎥
i0 = sin ( φ - α ) + + sin ωt + - φ -
Z ⎢ - 2π - 2π 3 cosφ ⎥
⎢⎣ 1- e 3tanφ 1- e 3tanφ ⎥⎦
(14.33)
for α + π ≤ ωt ≤ 2π
3 3
⎡ ⎧ - ( ωt - α - π/3) α - π/3 - ωt
⎫ - ωt ⎤
2VL ⎢ ⎪ e tanφ ⎪ sinφ e tanφ s inθ ⎥
i0 = sin ( φ - α ) ⎨e tanφ
+ ⎬+ + sin ( ωt - φ ) -
Z ⎢ ⎪ - 2π
⎪⎭ - 2π cos φ ⎥
⎣⎢ ⎩ 1- e 3tanφ 1- e 3tanφ ⎦⎥
(14.34)
Exercise 14.2
i. In a three phase half controlled converter each thyristor and diode conduct for
________________ degrees.
ii. The output voltage waveform of a three phase half controlled converter is periodic over
________________ of the input voltage cycle.
iii. The output voltage waveform of a three phase half controlled converter operating with α >
π/3 and α ≤ π/3 are ________________ and have ________________ formula for the
average voltage.
iv. The output voltage and current of a three phase half controlled converter contain
________________ harmonics of the input ac frequency.
v. The ac input current of a half controlled three phase converter can be zero for larger than
________________ of the input ac cycle provided the value of α is ________________
than 60°.
vi. The input ac current of a three phase half controlled converter contain ________________
harmonics but no ________________ harmonics.
vii. For the same output load current and firing angle the three phase half controlled converter
has better ________________ factor but poorer ________________ factor compared to a
Answer: (i) 120°; (ii) one third; (iii) different, same; (iv) triplen; (v) one third, greater; (vi) even,
triplen; (vii) displacement, distortion.

2. A 200V, 1450 RPM, 100A separately excited dc machine has an armature resistance of
0.04Ω. The machine is driven by a three phase half controlled converter operating from a
three phase 220V, 50Hz supply. The motor operates at the rated speed and rated load torque.
Assuming continuous conduction find out (i) the firing angle of the converter; (ii) RMS
fundamental component of the input current, (iii) Input current displacement factor and
distortion factors.
Answer:
(i) Under rated operating condition the motor must be supplied with rated voltage.
3 2
Therefore Vo = VL (1+ cosα ) = 200V
2π
Where VL = 230V
∴ α ≈ 70o
(ii) Io = 100A
From equation (14.18)
6
Ii1 = I o cos α = 63.87 amps
π 2
(iii) From equation (14.19)
Input displacement factor = cos α = 0.819

2
From equation (14.20)
6
Input distortion factor = cos α = 0.712
π(π − α) 2
References
1. “Power Electronics”’ P.C. Sen, Tata McGrawhill publishing company limited, 1995.
2. “Power Electronics, Converters, Applications and Design”; Mohan, Undeland, Robins;
John Willey and Sons Inc, Third Edition, 2003.

Lesson Summary
• Three phase half controlled converters are obtained by replacing three thyristors of either
the top group or the bottom group of fully controlled converters by three diodes.
• Three phase half controlled converters can not operate in the inverting mode.
• Three phase half controlled converters have nine operating modes as compared to six of a
• The three free wheeling modes of a half controlled converters appears only when the
firing angle is larger than 60º.
• The output voltage and current waveforms of a three phase half controlled converter
consist of a dc component and triplen harmonics of the input voltage frequency.
• For the same input ac voltage and firing angle a half controlled converter has higher
output average dc voltage compared to a fully controlled converter.
• The input ac line current of a three phase half controlled converter contains harmonics of
all (odd and even) order except triplen harmonics.
• For the same average dc load current and firing angle the half controlled converter has
better input current displacement factor but poorer distortion factor compared to a fully
controlled converter.
• The triggering circuit of a three phase half controlled converter is similar to that of a fully
controlled converter. However, only three are required.

1. If a free wheeling diode is connected across the output terminals of a three phase fully
controlled converter will the performance of converter will be similar to a half controlled
converter? Justify your answer.
2. A 220V, 1500 rpm, 50A, separately excited dc motor with armature resistance of 0.5Ω if
fed from a 3 phase half controlled rectifier. The available ac source is 440V, 50Hz. A star
delta connected transformer is used to feed the armature so that the motor terminal
voltage equals rated voltage when converter firing angle is zero.
(i) Calculate the transformer turns ratio
(ii) Firing angle when (a) motor is running at 1200 rpm and rated torque; (b) 1500 rpm
and half the rated torque.
3. A battery with a nominal voltage of 200V and internal resistance of 10mΩ has to be
charged at a constant current of 20 amps from a 3 phase 220V 50 Hz power supply.
Which of the following converters will give better performance with respect to input
current displacement factor, distortion factor and power factor?
(i) 3 phase fully controlled converter; (ii) 3 phase half controlled converter.

1) Connecting a diode at the output of a three phase fully controlled converter will not make
it performs as a half controlled converter. For example
i) When α ≤ π/3 the free wheeling diode will not come into conduction and therefore,
the converter will continue to perform like a fully controlled converter which is very
different from that of a half controlled converter for this range of α.
ii) For α > π/3 the output voltage will be clamped to zero for certain part of the input
cycle. However, the output voltage will still have “six pulse” characteristics unlike a
half controlled converter. Similarly the input current waveform will retain its quarter
cycle symmetry which is not the case with a half controlled converter.
2) For a half controlled converter
3 2
i) V0 = VL (1 + cosα)
2π
at α = 0, V0 = 220 V, ∴ VL = 163 V,
supply voltage = 440 V, ∴ Primary phase voltage = 254 V
∴ Turns ratio = 1 : 0.64.
ii) (a) E b 1500 = 220 - 0.5 × 50 = 195V
∴ E b 1200 = 195 ×
12 = 156 V
15
Torque is rated, ∴ Ia = 50 A, V1200 = 156 + 0.5 × 50 = 181 volts
∴ 181 = 3 2 × 163(1 + cosα) ∴ α = 49.87º
2π
(b) V1500 at half rated torque = 195 + 0.5 × 25 = 207.5V

207.5 = 3 2 × 163(1 + cosα) ∴ α = 27.7º
2π
3) The output voltage of the converter should be
V0 = 200 + 20 × 10 × 10-3 = 200.2 V
(i) with a fully controlled converter
200.2 = 3 2 × 220 cosα ∴ α = 47.64º

π
∴ Displacement factor = cos α = 0.674
Distortion factor = 3 = 0.955
π
∴ Power factor = Displacement factor × Distortion factor = 0.6436

(ii) with a half controlled converter
200.2 = 3 2 × 220 (1 + cosα) ∴ α = 69.65º

2π
∴ Displacement factor = cos α = 0.82
2
Distortion factor = 6 cos α = 0.8166
π(π-α) 2
∴ Power factor = 0.6695
∴ Displacement factor and power factor of a half controlled converter are better
compared to a fully controlled converter while the distortion factor is poorer.

Module
2
AC to DC Converters
Lesson
15
Effect of Source
Inductance on the
Performance of AC to DC
Converters
• Draw the voltage and current waveforms associated with a converter taking into account
the effect of source inductance.
• Find the average output voltage of the converter as a function of the firing angle and
overlap angle.
• Estimate overlap angles under a given operating condition and hence determine the turn
off time available for the thyristors.
• Draw the dc equivalent circuit of a converter and parameterize it.
• Find out the voltage stress on the thyristors due to commutation overlap.

15.1 Introduction
In the previous lessons the input ac power sources supplying an ac to dc power converter have
been assumed to be ideal with no source impedance. Although this assumption simplifies the
analysis of the converters, in most practical situations, they are not fully justified. Most ac dc
converters are supplied from transformers. The series impedance of the transformer can not
always be neglected. Even if no transformer is used, the impedance of the feeder line comes in
series with the source. In most cases this impedance is predominantly inductive with negligible
resistive component. The presence of source inductance does have significant effect on the
performance of the converter. With source inductance present the output voltage of a converter
does not remain constant for a given firing angle. Instead it drops gradually with load current.
The converter output voltage and input current waveforms also change significantly. In this
lesson a quantitative analysis of these effects will be taken up in some detail.
15.2 Single phase fully controlled converter with source

inductance
Fig. 15.1(a) shows a single phase fully controlled converter with source inductance. For
simplicity it has been assumed that the converter operates in the continuous conduction mode.
Further, it has been assumed that the load current ripple is negligible and the load can be
replaced by a dc current source the magnitude of which equals the average load current. Fig.
15.1(b) shows the corresponding waveforms. It is assumed that the thyristors T3 and T4 were
conducting at t = 0. T1 and T2 are fired at ωt = α. If there were no source inductance T3 and T4
would have commutated as soon as T1 and T2 are turned ON. The input current polarity would
have changed instantaneously. However, if a source inductance is present the commutation and
change of input current polarity can not be instantaneous. Therefore, when T1 and T2 are turned
ON T3 T4 does not commutate immediately. Instead, for some interval all four thyristors
continue to conduct as shown in Fig. 15.1(b). This interval is called “overlap” interval.

During this period the load current freewheels through the thyristors and the output voltage is
clamped to zero. On the other hand, the input current starts changing polarity as the current
through T1 and T2 increases and T3 T4 current decreases. At the end of the overlap interval the
current through T3 and T4 becomes zero and they commutate, T1 and T2 starts conducting the full
load current. The same process repeats during commutation from T1 T2 to T3T4 at ωt = π + α.

From Fig. 15.1(b) it is clear that, commutation overlap not only reduces average output dc
voltage but also reduces the extinction angle γ which may cause commutation failure in the
inverting mode of operation if α is very close to 180º. In the following analysis an expression of
the overlap angle “μ” will be determined.
From the equivalent circuit of the converter during overlap period
dii
L = vi for α ≤ ωt ≤ α + μ (15.1)
dt
ii(ωt = α) = - I0 (15.2)
2Vi
∴ ii = I - cosωt (15.3)
ωL
2Vi
ii =I- cosα = - I0 (15.4)
ωt = α ωL
2Vi
∴ I= cosα - I0 (15.5)
ωL
2Vi
∴ ii = (cosα - cosωt) - I0 (15.6)
ωL
at ωt = α + μ ii = I0
2Vi
∴ I0 = (cosα - cos(α + μ)) - I0 (15.7)
ωL
∴ cosα - cos(α + μ) = 2ωL I (15.8)

Vi 0
V0 = I
α+π
π ∫ α
vi dωt (15.9)
V0 = I
α+π
or
π ∫α+μ
2vi sinωt dωt
2vi
=
π
[cos(α + μ) − cos(π + α)]
2vi
=
π
[cosα + cos(α + μ)] (15.10)
vi 2vi
∴ V0 = 2 2
π
cosα -
π
[ cosα − cos(α + μ)]
= 2 2 vi cosα - 2 ωL I0 (15.11)
π π

Equation 15.11 can be represented by the following equivalent circuit
The simple equivalent circuit of Fig. 15.3 represents the single phase fully controlled converter
with source inductance as a practical dc source as far as its average behaviour is concerned. The
open circuit voltage of this practical source equals the average dc output voltage of an ideal
converter (without source inductance) operating at a firing angle of α. The voltage drop across
the internal resistance “RC” represents the voltage lost due to overlap shown in Fig. 15.1(b) by
the hatched portion of the v0 waveform. Therefore, this is called the “Commutation resistance”.
Although this resistance accounts for the voltage drop correctly there is no power loss associated
with this resistance since the physical process of overlap does not involve any power loss.
Therefore this resistance should be used carefully where power calculation is involved.
15.3 Three phase fully controlled converter with source

inductance
In lesson 13 the three phase fully controlled converter was analyzed with ideal source with no
internal impedance. When the source inductance is taken into account, the qualitative effects on
the performance of the converter is similar to that in the case of a single phase converter. Fig.
15.4(a) shows such a converter. As in the case of a single phase converter the load is assumed to
be highly inductive such that the load can be replaced by a current source.

As in the case of a single phase converter, commutations are not instantaneous due to the
presence of source inductances. It takes place over an overlap period of “μ1” instead. During the
overlap period three thyristors instead of two conducts. Current in the outgoing thyristor
gradually decreases to zero while the incoming thyristor current increases and equals the total
load current at the end of the overlap period. If the duration of the overlap period is greater than
60º four thyristors may also conduct clamping the output voltage to zero for sometime. However,
this situation is not very common and will not be discussed any further in this lesson. Due to the
conduction of two devices during commutation either from the top group or the bottom group the
instantaneous output voltage during the overlap period drops (shown by the hatched portion of
Fig. 15.4 (b)) resulting in reduced average voltage. The exact amount of this reduction can be
calculated as follows.
In the time interval α < ωt ≤ α + μ, T6 and T2 from the bottom group and T1 from the top group
conducts. The equivalent circuit of the converter during this period is given by the circuit
diagram of Fig. 15.5.

Therefore, in the interval α < ωt ≤ α + μ
di b di
vb = L - L c + vc (15.12)
dt dt
or, d
v bc = L (i b - ic ) (15.13)
dt
di b di
but ib + ic + Io = 0 ∴ =- c (15.14)
dt dt
∴ 2L d i b = vbc = 2VL sinωt (15.15)
dt
2VL
∴ ib = C - cosωt (15.16)
2ωL
2VL
at ωt = α, ib = - I0 ∴ C= cosα - I0 (15.17)
2ωL
2VL
∴ ib = (cosα - cosωt) - I0 (15.18)
2ωL
at ωt = α + μ, ib = 0
2VL
∴ (cosα - cos(α + μ)) = I0 (15.19)
2ωL
Or, cosα - cos(α + μ) = 2ωL I (15.20)
VL 0
Equation 15.20 holds for μ ≤ 60º. It can be shown that for this condition to be satisfied
I0 ≤
VL
2ωL
(
cos α - π
3 ) (15.21)
To calculate the dc voltage

For α ≤ ωt ≤ α + μ
di b
v0 = va - v b + L = 3 va (15.22)
dt 2
for α + μ ≤ ωt ≤ α + π v0 = vac
3
⎡ α+μ π
⎤
V0 = 3 ⎢ ∫ 3 va dωt +
α+
∴
π⎣ α 2 ∫
α+μ
3
vac dωt ⎥
⎦

⎡ α+μ
( ) ⎤
π
= 3 ⎢∫ vac + 3 va - vac + ∫ 3 vac dωt ⎥
α+
π⎣ α 2 α+μ
⎦
⎡ α+ π
α+μ ⎛ v ⎞ ⎤
= 3 ⎢ ∫ 3 vac dωt + ∫ ⎜ a + vc ⎟ dωt ⎥
π⎣ α α
⎝ 2 ⎠ ⎦
= 3 2 VL cosα - 3 ∫ v bc dωt
α+μ
(15.23)
π 2π α
3 2VL
V0 = 3 2 VL cosα -
α+μ
or
π 2π ∫α sinωt dωt
3 2VL
= 3 2 VL cosα - [cosα - cos(α + μ)] (15.24)
π 2π
Substituting Equation 15.20 into 15.24
V0 = 3 2 VL cosα - 3 ωL I0 (15.25)
π π
Equation 15.25 suggests the same dc equivalent circuit for the three phase converter with source
inductance as shown in Fig. 15.3 with
VOC = 3 2 VL cosα and commutation resistance R C = 3 ωL .

π π
It should be noted that RC is a “loss less” resistance, since the overlap process does not involve
any active power loss.
Exercise 15.1
1. Fill in the blank(s) with appropriate word(s)
i. The internal impedance of an ac source supplying a converter is largely ______________

in nature.
ii. Due to the presence of source ______________ commutation in a converter is not
______________.
iii. The period over which the commutation process continues is called the ______________
period.
iv. Length of the overlap period depends on the valve of the source inductance and load
______________.
v. In a single phase converter ______________ thyristors conduct during the overlap
period.
vi. In a three phase converter ______________ thryistors conduct during the overlap period
provided the overlap angle is less than ______________ degrees.
vii. The average output voltage of a ac-dc converter ______________ as a result of
commutation overlap.

viii. In the dc equivalent circuit of a converter the input ac source inductor appears as a loss
less resistance called the ______________ resistance.
ix. Commutation overlap decreases the ______________ angle of a converter and may cause
commutation failure during ______________ mode of operation.
x. Commutation overlap introduces ______________ in the supply voltage waveform.
Answer: (i) inductive; (ii) inductance, instantaneous; (iii) overlap; (iv) current ; (v) four; (vi)
three, sixty; (vii) decreases; (viii) commutation; (ix) inverter, (x) notches.
2. A 220V, 1450 RPM, 100A separately excited dc motor has an armature resistance to
0.1Ω. It is supplied from a 3 phase fully controlled converter connected to a 3 phase 50
Hz ac source. The ac source has an inductive reactance of 0.5Ω at 50 Hz. The line voltage
is adjusted such that at α = 0; the motor operates at rated speed and torque. The motor is
to be braked regeneratively in the reverse direction at rated speed using the converter.
What is the maximum braking torque the motor will be able to produce under this
condition without causing commutation failure?
Answer: Under rated operating condition, the motor terminal voltage is 220V and it draws 100
Amps current. Therefore from eqn. 15.25.
3 2 3
220 = VL - × .5×100
π π
or VL = 198 volts Eb rated speed = 220 − 100 × 0.1 = 210V
Under regenerative braking in the reverse direction at rated speed

3 2 ⎛3 ⎞
×198cos α − ⎜ × 0.5 + 0.1⎟ Io = −210V
π ⎝π ⎠
Also from equation 15.20
2 × 0.5 Io
cos α − cos ( α + μ ) =
198
At the limiting condition of commutation failure
α + μ ≈ 180o
Io
∴ cos α = −1
198 2
3 3 2 ⎛3 ⎞
∴ Io − × 198 − ⎜ × 0.5 + 0.1⎟ I o = −210
π π ⎝π ⎠
or 0.377 Io = 57.4 ∴ Io = 152.24 Amps
∴ Maximum braking torque will be approximately 150% of the rated motor torque.

References
1. Muhammad H. Rashid; “Power Electronics, Circuits, Devices and Applications” Second
Edition, Prentice – Hall of India, New Delhi, 1994.
2. P.C. Sen; “Power Electronics”, Tata McGrawhill publishing company limited, 1995.
3. “Power Electronics, Converters, Applications and Design”; Mohan, Undeland, Robbins;
John Willey and Sons Inc, Third Edition, 2003.
Lesson Summary
• Ac power sources supplying an ac-dc converter have internal impedances which are not
always negligible.
• The internal impedance of an ac source is predominantly inductive with negligible
resistive component.
• Due to the presence of the source inductance in the ac line the thyristors in a ac-dc
converter can not commutate instantaneously.
• The period over which the commutation process continuous is called the overlap period.
• The length of the overlap period increases with increasing source inductance and load
current.
• In a single phase converter all four thyristors conduct during the overlap period.
• In a three phase converter, three thyristors conduct during the overlap period provided it
is less than 60º.
• The average output voltage of a converter decreases as a result of commutation overlap.
• The voltage drop due to commutation overlap can be represented as a drop across a
commutation resistance the value of which is proportional to the ac line reactance per
phase.
• The commutation resistance is “loss less” since the actual process of overlap does not
involve any real power loss.
• Commutation overlap reduces the margin angle (γ) of a converter and may cause
commutation failure.
• Commutation overlap introduces “notches” in the ac supply voltage waveform which
may affect other equipment connect to the same power source.

Module
2
AC to DC Converters
Lesson
16
Power Factor
Improvement, Harmonic
Reduction, Filter
Study of the following:
• Schemes for the improvement of power factor in AC-DC converters.
• Methods for harmonic reduction in the current waveforms of the converters.
• Types of filters used to obtain ripple free (dc) output voltage and currents, reducing the
harmonics.
2.8.1 Introduction
After the discussion of various types of ac to dc converters (rectifiers), both single- and three-
phase, in the lessons (#2.1-2.6) of this module (# 2), the drop in the output voltage due to the
commutation overlap in the converter, was presented, the inductance on the source (ac) side
being taken into account, in the previous lesson (#2.7).
In this (last) lesson (#2.8), three important points – power factor improvement, harmonic
reduction, and filters, as applicable to converters, are described. The three schemes for power
factor improvement are discussed. Then, the use of various filters to reduce the harmonics in the
output voltage and current waveforms, are presented. Lastly, the harmonic reduction techniques
are taken up, in brief. In all these cases, the circuit of a single phase full wave half (semi)
controlled bridge converter (ac-dc) is used mostly as an example.
Power Factor Improvement
For phase-controlled operation in both single phase full wave half and full controlled bridge
converters as discussed in this module (#2), the displacement factor (or power factor, which is
lagging) decreases, as the average value of output voltage (Vdc) decreases, with the increase in
firing angle delay, α. This is also applicable for both three phase half wave and full wave
(bridge) converters. The three schemes used for power factor (pf) improvement are:
• Extinction angle control

• Symmetrical angle control
• Pulse width modulation (PWM) control
Extinction Angle Control

The circuit diagram of a single phase full wave half-controlled (semi) force-commutated
bridge converter is shown in Fig. 16.1(a). The thyristors, T1 & T2, are replaced by the switches,
self-commutated devices, such as power transistor or equivalent. The power transistor is turned
on by applying a signal at the base, and turned off by withdrawing the signal at the base. A gate
turn-off thyristor (GTO) also may be used, in which case, it may be turned off by applying a
short negative pulse to its gate, but is turned on by a short positive pulse, like a thyristor.
In extinction angle control, switch, S1 is turned on at ωt = 0 , and then turned off by forced
commutation at ωt = ( π − β ) . The switch, S2 is turned on at ωt = π , and then turned off at
ωt = ( 2π − β ) . The output voltage is controlled by varying the extinction angle, β. Fig. 16.1(b)
shows the waveforms for input voltage, output voltage, input current, and the current through
thyristor switches. The fundamental component of input current leads the input voltage, and the

displacement factor (and power factor) is leading. This feature may be desirable to simulate a
capacitive load, thus compensating the line voltage drops.
iT1
+
S1 S2 i 0 = Ia
v0
+ is iT2
DF L
vs O
- A
D
D2 D1
iDF
-
(a) Circuit

vs
vs = Vmsinωt
Vm
π ωt
0
2π
v0
β
0 ωt
π-β π 2π - β 2π
iT1
Ia
0 ωt
π-β π 2π 3π - β
Ia iT2
0 ωt
π 2π - β
iDF Ia
ωt
0 π-β π 2π - β 2π
is
is1
Ia
2π - β
0 ωt
π-β π 2π 3π - β
- Ia
io
Ia Load current
ωt
0
(b) Waveforms for extinction angle control
Fig. 16.1 Single-phase forced-commutated semi-converter.
The average output voltage is

2 π-β 2
Vdc = ∫ 2Vsin ωt d ( ωt ) = ⋅ V (1 + cos β )
2π 0 π
The value of Vdc is varied from (2 2 / π)V to 0, as β varies from 0 to π .
The rms value of output voltage is
1 1
⎡ 2 π-β ⎤ ⎡1 ⎛ 1 ⎞⎤
2 2
Vo = ⎢ ∫ 2V 2 sin 2 ωt d ( ωt ) ⎥ = V ⎢ ⎜ ( π − β ) + sin 2β ⎟ ⎥
⎣ 2π 0 ⎦ ⎣π ⎝ 2 ⎠⎦
Here also, Vo varies from V to 0.
This scheme of extinction angle control can also be used for single phase full wave full
controlled bridge converter with four switches, instead of two needed in the earlier case. The
students are requested-to study this matter form text books, but details are not included here.

Symmetrical Angle Control
This control can be applied for the same half-controlled force commutated bridge converter
with two switches, S1 and S2 as shown in Fig. 16.1(a). The switch, S1 is turned on at
ωt = ( π − β ) 2 and then turned off at ωt = ( π + β ) 2 . The other switch, S2 is turned on at
ωt = ( 3π − β ) 2 and then turned off at ωt = ( 3π + β ) 2 . The output voltage is varied by varying
conduction angle, β. The gate signals are generated by comparing half-sine waves with a dc
signal as shown in Fig. 16.2(b). The half-sine waves can be obtained using a full wave diode
(uncontrolled) bridge converter. The gate signals can also be generated by comparing triangular
waves with a dc signal as shown in Fig. 16.2(c). In the second case, the conduction angle varies
linearly with the dc signals, but in inverse ratio, i.e., when the dc signal is zero, full conduction
(β = π ) takes place, and the dc signal being same as the peak of the triangular reference signal,
no conduction ( β = 0 ) takes place. Fig. 16.2(a) shows the waveforms for input voltage, output
voltage, input current and the current through the switches. The fundamental component of input
current is in phase with input voltage, and the displacement factor is unity (1.0). Therefore, the
power factor is improved.

vs
Vm vs = Vmsinωt
π
0
ωt
v0
Vm
β
0
is1 π 2π 3π ωt
Ia
0
is2 π /2 π 2π 5π /2 ωt
Ia
0 ωt
is π 3π /2 2π
Ia is1
π
0
π-β π+β 2π ωt
- Ia 2 2
i0
Ia
Load current
0
ωt
(a)
v
vr
vc
Ar
-Ar
0 π 2π 3π ωt
S1 S2 S1
vg
β
0 π 2π 3π ωt
(b)
Fig. 16.2 Symmetrical angle control.

The average output voltage is
2 ( π+β ) / 2 ⎛2 2 ⎛ β ⎞⎞
Vdc = ∫ 2V sin ωt d ( ωt ) = ⎜⎜ V sin ⎜ ⎟ ⎟⎟
π ( π−β ) / 2 ⎝ π ⎝ 2 ⎠⎠
( )
The value of Vdc varies from 2 2π V to 0 as β varies from π to 0.
The rms value of output voltage is
1 1
⎡ 2 ( π+β ) / 2 2 2 ⎤ ⎡1 ⎤
2 2
Vo = ⎢ ∫ 2V sin ( ωt ) d ( ωt ) ⎥ = V ⎢ ( β + sin β ) ⎥
⎣ 2π ( π-β ) / 2
⎦ ⎣π ⎦
Pulse Width Modulation (PWM) Control

If the output voltage of single phase half-controlled converter is controlled by delay angle,
extinction angle or symmetrical, there is only one pulse per half cycle in the input current of the
converter, and as a result, the lowest order harmonic is third. It is difficult to filter out the lower
order harmonic current. In Pulse Width Modulation (PWM) control, the converter switches are
turned on and off several times during a half cycle, and the output voltage is controlled by
varying the width of pulses. The gate signals are generated by comparing a triangular wave with
a dc signal as shown in Fig. 16.3c. In this case, all the pulse widths obtained are equal. Fig. 16.3a
shows the input voltage, output voltage, and input current. The lowest order harmonic can be
eliminated or reduced by selecting the number of pulses per half cycle. However, increasing the
number of pulses would also increase the magnitude of higher order harmonics, which could
easily be filtered out. The earlier case of symmetrical angle control can be considered as single
pulse PWM. For more details of PWM methods used, the students are requested to study the two
lessons (#5.4-5.5) in module 5 (DC-AC converter, or inverter).

v
0
π 2π 3π ωt
v0
δm
0
αm π 2π 3π ωt
is1
Ia
δm
δm
0
is3 π 2π 3π ωt
Ia
0
π π + αm 2π 3π ωt
is
Ia
δm
π + αm
0
αm π 2π 3π ωt
i0
- Ia
Ia
Load current
0
ωt
(a)
v
vr
Ar
vc
-Ac
0 π
vg2 S1 S1 S1
δm δm
α1 αm ωt π
(b)

v
vr
vc
Ar
-Ac
π ωt
vg2
S1 S1 S1
δm
0 αm π ωt
(c)
Fig. 16.3 Pulse-width-modulation control.
The details of output voltage and current waveforms of the converter are given. The output
voltage (i.e., performance parameters) can be obtained in two steps: (i) by considering only one
pair of pulses such that, if one pulse starts at ωt = α1 , and ends at ωt = α1 + δ1 , the other pulse
starts at ωt = π + α1 , and ends at ωt = ( π + α1 + δ1 ) , and (2) then by combining the effects of all
pairs of pulse.
If mth pulse starts at ωt = α m and its width is δm , the average output voltage due to p number
of pulses is found as
p
⎡ 2 α m +δm ⎤ 2V p
Vdc = ∑ ⎢ ∫
m =1 ⎣ π
αm
2V sin ωt d ( ωt ) ⎥ =
⎦
∑ ⎡cos α m − cos ( α m + δm )⎤⎦
π m =1 ⎣
If the load current with an average value of Ia is continuous and has negligible ripple, the
instantaneous input current is expressed in a Fourier series as
α
is ( t ) = Idc + ∑ (a
n =1,3,5,...
n cos nωt + b n sin nωt )
Due to symmetry of the input current waveform, even harmonics are absent, and Idc is zero. The
Fourier coefficients are obtained as
1 2π
a n = ∫ is ( t ) cos nωt d ( ωt )
π 0
p
⎡ 1 α m +δm 1 π+αm +δm ⎤
= ∑⎢ ∫ I a cos nωt d ( ωt ) − ∫ I a cos nωt d ( ωt ) ⎥ = 0
m =1 ⎣ π π ⎦
α m π+α m
1 2π
is ( t ) sin nωt d ( ωt )
π ∫0
bn =
p
⎡ 1 α m +δm 1 π+α m +δm ⎤
= ∑⎢ ∫ Ia sin nωt d ( ωt ) − ∫ I a sin nωt d ( ωt ) ⎥
m =1 ⎣ π π ⎦
α m π+α m
p
2I
= a ∑ ⎡⎣ cos nα m − cos n ( α m + δ m ) ⎤⎦
nπ m =1

So, the equation for is(t) is written as
α
is ( t ) = ∑
n =1,3,...
2 I n sin ( nωt + φn )
where φn = tan −1 ( a n b n ) = 0 , and I n = ( a 2n + b 2n )

1
2 = bn
2
2
Sinusoidal Pulse Width Modulation (SPWM) Control

Various types of modifications in PWM techniques have been proposed. One important
method is sinusoidal pulse width modulation (SPWM) control, the pulse widths are generated by
comparing a triangular reference voltage vr of amplitude Ar and frequency fr, with a carrier half
sinusoidal voltage vc of variable amplitude Ac and frequency 2fs. The sinusoidal voltage vc is in
phase with the input phase voltage vs and has twice the supply frequency fs. The widths of the
pulses (and the output voltage) are varied by changing the amplitude Ar or the modulation index
M from 0 to 1. The modulation index, M is Ac/Ar. It may be noted that the width of the pulses
obtained are variable. The width are smaller at the centre of the carrier signal (sinusoidal), and
increases as one goes to the start and end of the above signal. Fig. 16.4 shows the various
waveforms, including the currents through thyristors and the input current and load current
(assumed to be continuous). It may be noted that, in the earlier case (multiple PWM control), the
pulse widths are uniform (equal). In this type of control, the displacement factor is unity, and the
power factor is improved. The lower order harmonics one eliminated or reduced. For example,
width four pulses per half cycle, the lowest order harmonic is the fifth, and so on.
Different modifications have been suggested to take one such example, as the pulse width
one small in the centre as shown in Fig. 16.4, the carrier signal is modified to care of this. The
triangular waveforms are kept same, upto some point from the start and end of the cycle, and
then the pulse widths can be made uniform. For more on the matter as given earlier, the students
can, either study lesson #5.5 (module 5), or text books on various PWM methods applied for
inverters (dc-ac converters).
So, the power factor is improved with various control methods discussed. For different PWM
methods used, the harmonic components of the voltage waveforms are also decreased or
eliminated.

v Reference signal Carrier signal
Ar
vr
Ac
vc
0 ωt
iT1
+Ia
0 ωt
αm π 2π 3π
δm
iT2
+Ia
0 ωt
π π + αm 2π 3π
is δm
+Ia π + αm
π + αm + δ m
0 ωt
αm π 2π 3π
- Ia
io
Ia
Load current
0 ωt
Fig. 16.4 Sinusoidal pulse-width modulation control.
Filters
It is known that the output voltage waveform of a single phase full wave diode (uncontrolled)
bridge converter (rectifier) fed from f = 50 Hz (fundamental) supply, contains harmonics of 2f =
100 Hz. So, it is necessary to filter out this and other harmonics from the output voltage to obtain
dc component only. The harmonic frequency present in the output voltage waveforms of three-
phase half-wave and full wave (bridge) diode converters, are 150 Hz (3f) and 300 Hz (6f)
respectively. The higher the harmonic frequency, it is easier to filter it. For phase-controlled
thyristor converters, the harmonic frequency remains same, but magnitudes vary, as the firing
angle delay, α is changed. It may also be noted that the harmonics present in the output current
waveforms of the converters with resistive (R) load, remain same. .
For simple filter, a capacitor (C) is connected in parallel across the output of the diode
converters with resistive (R) load. The reactance of the capacitor should be low, such that
harmonics currents pass through it. So, the harmonics in the output voltage decrease. The value
of the capacitor chosen varies with the predominant harmonic frequency present. Thus, the
capacitor of higher value is needed to filter lower harmonic frequency, say 100 Hz, whereas a
lower value of C could be chosen for say, three phase converters. The function of the capacitor

may also be explained in the following way. The voltage across the capacitor changes as per the
input voltage, which is the output voltage of the converter, fed to it, and the capacitor voltage
tries to stabilize at the overage value of the output voltage, as the capacitor voltage decreases,
load resistance being connected across it.
Same is the case with the filter used to reduce the harmonic content of the output current
waveform for the above converters with resistive (R) load. Instead of a capacitor in parallel, an
inductor (L) is connected in series with the load. The reactance of the inductor increases, thus
reducing the harmonic component in the current waveform. Here, a smaller value of the inductor
is needed to filter higher harmonics, for example a three-phase bridge converter. These are all
simple cases, known to those, who have studied the circuit (network) theory. Also, by Faraday’s
laws, induced voltage (emf) appears across the inductor, L, when the current through it changes,
and the sign of it opposes the cause, thus opposing the changes in current. So, the current is not
allowed to change much, as an inductor is placed in series with the load. In actual practice, a
combination of L, C & R is needed to get an optimum filter needed to reduce or eliminate the
harmonics in both output voltage and current waveforms.
Low Pass (L-C) Filter
A passive low pass filter is the ideal choice. But two problems arise; one is the voltage level,
the other is the power or current level. All the elements used, L C or R must be properly rated for
the voltage or current level as needed. A single stage filter (L-C) is used to reduce the harmonic
components in both voltage and current waveforms of a single phase full wave diode bridge
converter with resistive (RL) load as shown in Fig. 16.5(a). It may be noted that, for the lowest
harmonic frequency of 100 Hz, the value of the inductor needed is high, needing an iron-cored
coil. The size also may be large, if the power or current level is high. As stated earlier, such that
nth harmonic ripple content passes through the filter capacitor (C), the impedance of the series
path must be much greater than that of the capacitance, i.e.,
1
ZL = ( R L ) + ( n ω L ) >>
2 2
n ωC
The condition to be satisfied is
10
ZL = or ZL 10 = 1 ( n ω C )
n ωC
and the effect of load is negligible. As shown, the capacitive reactance chosen is total load
impedance divided by a factor of 10
The advantages are small ripple factor with just a single stage (L-C) used, with higher dc
output voltage. The main advantage is poor voltage regulation, also resulting in higher peak
anode current and peak inverse voltage rating.

iL
+ A D
D1 D2
1-φ +
Supply L
G O
(50Hz) A RL
- C
is D
H
D4 D3
- B
(a)
A E
+
R RL, L
L
O
C1 C2 A
D
-
B
(b)
Fig. 16.5 (a) Low pass (L-C) filter, (b) Two-stage filter
Two Stage Filter

A two-stage filter (Fig. 16.5(b)) may be used, instead of a single stage one given earlier. In
this case, the first one is only capacitive (C1) to reduce the harmonic content in voltage
waveform, followed by second stage (R-C), instead of L-C. The size may be reduced as the size
of R is smaller than that of L, as given earlier. This circuit offers satisfactory operation at light
loads, but considerably poor voltage regulation due to drop in R, resulting in higher ripple
content, at heavy load.
If a single capacitor (C1) is used as a single stage one, the ripple factor (RF) is
RF = 1 ⎡⎣ 2 ( 4fR L C1 − 1) ⎤⎦
For a chosen ripple factor, the value of C1 may be computed, if the values of rated output voltage
and current for the converter are known or given.
These filters may also be used at the output of the dc-dc converter circuits described in
module 3 (lessons $3.1-3.2). Only a single stage (L-C) filter may be used, as the frequency in the
output voltage in thus case is much higher than the harmonic frequency (100 Hz) for the single
phase full wave ac-dc converter (rectifier) circuit described here.

Harmonic Reduction
The harmonic reduction schemes are presented in brief. The important point to be noted is
that, recently due to increasing use of power electronic units, utility or electricity supply agencies
(boards), have restricted that the power is drawn by the consumers, so as to decrease the
harmonic content in the input current, or make it sinusoidal, and at the same time, improved load
power factor is achieved. Two schemes – (a) passive (filter) circuits and (b) Active shaping of
input line current, are presented, in brief.
Low pass (L-C) filter circuit on ac side

Before going into the aspect, let us take a rebook at the input current drawn in the circuit
shown in Fig. 16.5a. Assuming that output (load) current is constant (dc) without any ripple, the
ac input (source) current is square wave in nature (Fig. 16.6a), as this current changes sign, when
the input voltage changes sign. If a Fourier analysis of the above current is done, there are
harmonic components present in it. Just as filters have been used on the output (dc) side, a low
pass (L-C) filter (Fig. 16.6b) is used on the input (source) side to reduce the harmonic
components in the input current. The inductors used tend both to improve the power factor and
also reduce harmonics as given earlier. The overall energy efficiency remains the same, though
additional losses occur in the inductors, but conduction losses in the diodes are reduced.
iL
Ia
is
Ia
0
π(T/2) 2π(T) ωt
-Ia
Fig. 16.6(a) Output and input currents.

+
A
iS L1 L2
+ G
C H
-
B
-
Fig. 16.6 (b) Low pass (L-C) filter on source (AC) side
Active Shaping of Input (line) Current

By using a power electronic converter for current shaping, as shown in Fig. 16.7a, it is
possible to shape the input current drawn by the single phase bridge converter (rectifier) to be
sinusoidal and also in phase with the input voltage. The choice of the power electronic converter
is based on the following considerations:
• No need for electrical isolation between the input (dc) and output (dc) sides
• the power flow is always unidirectional from the utility side to the equipment
• the cost, power losses and size of the circuit used should be small.
Based on the above, a step-up (boost) dc-dc converter as described in next module (#3),
lesson 3.1, is used as the current shaping circuit. The basic principle of operation is as follows.
At the input side, the current, is, is desired to be sinusoidal, and also in phase with the voltage, vs,
as shown in Fig. 16.7b. Therefore, at the full wave bridge converter output, iL and vs have the
same waveform as shown in Fig. 16.7c.

Step-up
converter
iL id Iload
+ Ld +
ic
+
vs │vs│ vd (Vd > Vˆ s )
Cd
-
- -
(a)
vs
is
0 ωt
(b)
│vs│
iL
0 ωt
(c)
Fig. 16.7 Active harmonic filtering: (a) step-up converter for current
shaping; (b) line waveforms; (c) │vs│ and iL.
The control used is constant tolerance-band one. Here, the current. iL, is controlled, such that
peak-to-peak ripple Irip in iL remains constant. The reference input, i*L , is made sinusoidal having
same (line) frequency. With a pre-selected value of Irip, iL is forced to be in tolerance band (iL +
Irip/2) and (iL – Irip/2) by controlling the status of the switch, S. So, the input current, iL, follows
the reference input, i*L , which is sinusoidal. As described later (module #3), the switch, S may be
a self-commutated switching device, power transistor or MOSFET. For detail, any text book may
be used by the student, as only a brief discussion is presented here.
In this lesson, last one in this module, three important points – power factor (pf)
improvement, harmonic reduction and filters, are presented. Firstly, three methods, viz extinction
angle control, symmetrical angle control and pulse width modulation (PWM) control, are
described in detail with relevant waveforms. Then, various types of filters (C, L-C & R-C) used
for the reduction in harmonic content of output voltage and current waveforms of the ac-dc

converters, are discussed, with the equations for the value of the filter components needed.
Lastly, in brief, harmonic reduction aspect is taken up. In this module of ac-dc converter
consisting of eight lessons, all types of single-phase and three-phase converters, with other
relevant points, have been thoroughly discussed.

Module
3
DC to DC Converters
Lesson
17
Types of Basic DC-DC
Converters
• Three basic types of dc-dc converter circuits − buck, boost and buck-boost
• The expressions for the output voltage in the above circuits, with inductive (R-L) and battery
(or back emf = E) load
Introduction
In the last module (#2) consisting of eight lessons, the various types of circuits used in both
single-phase and three-phase ac-dc converters, were discussed in detail. This includes half-wave
and full-wave, and also half-controlled and full-controlled ones.
In this lesson − the first one in this module (#3), firstly, three basic types of dc-dc converter
circuits − buck, boost and buck-boost, are presented. Then, the expressions for the output voltage
in the above circuits, with inductive (R-L) and battery (or back emf = E), i.e., R-L-E, load, are
derived, assuming continuous conduction. The different control strategies employed are briefly
described.
Keywords: DC-DC converter circuits, Thyristor choppers, Buck, boost and buck-boost
converters (dc-dc), Step-down (buck) and step-up (boost) choppers, Output voltage and current.
DC-DC Converters
There are three basic types of dc-dc converter circuits, termed as buck, boost and buck-boost.
In all of these circuits, a power device is used as a switch. This device earlier used was a
thyristor, which is turned on by a pulse fed at its gate. In all these circuits, the thyristor is
connected in series with load to a dc supply, or a positive (forward) voltage is applied between
anode and cathode terminals. The thyristor turns off, when the current decreases below the
holding current, or a reverse (negative) voltage is applied between anode and cathode terminals.
So, a thyristor is to be force-commutated, for which additional circuit is to be used, where
another thyristor is often used. Later, GTO’s came into the market, which can also be turned off
by a negative current fed at its gate, unlike thyristors, requiring proper control circuit. The turn-
on and turn-off times of GTOs are lower than those of thyristors. So, the frequency used in GTO-
based choppers can be increased, thus reducing the size of filters. Earlier, dc-dc converters were
called ‘choppers’, where thyristors or GTOs are used. It may be noted here that buck converter
(dc-dc) is called as ‘step-down chopper’, whereas boost converter (dc-dc) is a ‘step-up chopper’.
In the case of chopper, no buck-boost type was used.
With the advent of bipolar junction transistor (BJT), which is termed as self-commutated
device, it is used as a switch, instead of thyristor, in dc-dc converters. This device (NPN
transistor) is switched on by a positive current through the base and emitter, and then switched
off by withdrawing the above signal. The collector is connected to a positive voltage. Now-a-
days, MOSFETs are used as a switching device in low voltage and high current applications. It
may be noted that, as the turn-on and turn-off time of MOSFETs are lower as compared to other
switching devices, the frequency used for the dc-dc converters using it (MOSFET) is high, thus,
reducing the size of filters as stated earlier. These converters are now being used for applications,
one of the most important being Switched Mode Power Supply (SMPS). Similarly, when
application requires high voltage, Insulated Gate Bi-polar Transistors (IGBT) are preferred over

BJTs, as the turn-on and turn-off times of IGBTs are lower than those of power transistors (BJT),
thus the frequency can be increased in the converters using them. So, mostly self-commutated
devices of transistor family as described are being increasingly used in dc-dc converters.
Buck Converters (dc-dc)
A buck converter (dc-dc) is shown in Fig. 17.1a. Only a switch is shown, for which a device
as described earlier belonging to transistor family is used. Also a diode (termed as free wheeling)
is used to allow the load current to flow through it, when the switch (i.e., a device) is turned off.
The load is inductive (R-L) one. In some cases, a battery (or back emf) is connected in series
with the load (inductive). Due to the load inductance, the load current must be allowed a path,
which is provided by the diode; otherwise, i.e., in the absence of the above diode, the high
induced emf of the inductance, as the load current tends to decrease, may cause damage to the
switching device. If the switching device used is a thyristor, this circuit is called as a step-down
chopper, as the output voltage is normally lower than the input voltage. Similarly, this dc-dc
converter is termed as buck one, due to reason given later.
S Switch L
+
+ I0
L
Vs V0 O
DF A
D
-
-
Fig. 17.1(a): Buck converter (dc-dc)
v0 Vs
V0
TON
t
T TOFF
i0
t
Fig. 17.1(b): Output voltage and current waveforms
The output voltage and current waveforms of the circuit (Fig. 17.1a) are shown in Fig. 17.1b.
The output voltage is same as the input voltage, i.e., v0 = Vs , when the switch is ON, during the
period, TON ≥ t ≥ 0 . The switch is turned on at t = 0 , and then turned off at t = TON . This is

called ON period. During the next time interval, T ≥ t ≥ TON , the output voltage is zero, i.e.,
v0 = 0 , as the diode, D F now conducts. The OFF period is TOFF = T − TON , with the time period
being T = TON + TOFF . The frequency is f = 1 / T . With T kept as constant, the average value of
the output voltage is,
TON
⎛T ⎞
T
1 1
V0 = ∫
T 0
v0 dt =
T ∫V 0
s dt = Vs ⎜ ON ⎟ = k Vs
⎝ T ⎠
The duty ratio is k = (TON / T ) = [TON / (TON + TOFF )] , its range being 1.0 ≥ k ≥ 0.0 . Normally, due
to turn-on delay of the device used, the duty ratio (k) is not zero, but has some positive value.
Similarly, due to requirement of turn-off time of the device, the duty ratio (k) is less than 1.0. So,
the range of duty ratio is reduced. It may be noted that the output voltage is lower than the input
voltage. Also, the average output voltage increases, as the duty ratio is increased. So, a variable
dc output voltage is obtained from a constant dc input voltage. The load current is assumed to be
continuous as shown in Fig. 17.1b. The load current increases in the ON period, as the input
voltage appears across the load, and it (load current) decreases in the OFF period, as it flows in
the diode, but is positive at the end of the time period, T.
Boost Converters (dc-dc)
A boost converter (dc-dc) is shown in Fig. 17.2a. Only a switch is shown, for which a device
belonging to transistor family is generally used. Also, a diode is used in series with the load. The
load is of the same type as given earlier. The inductance of the load is small. An inductance, L is
assumed in series with the input supply. The position of the switch and diode in this circuit may
be noted, as compared to their position in the buck converter (Fig. 17.1a).
Is L D I0
+ +
L
S
Vs V0 O
A
D
Switch
- -
Fig. 17.2(a): Boost converter (dc-dc)
I2
I1
0 TON T 2T
TOFF
Fig. 17.2(b): Waveforms of source current (iS)

The operation of the circuit is explained. Firstly, the switch, S (i.e., the device) is put ON
(or turned ON) during the period, TON ≥ t ≥ 0 , the ON period being TON . The output voltage is
zero ( v0 = 0 ), if no battery (back emf) is connected in series with the load, and also as stated
earlier, the load inductance is small. The current from the source ( i s ) flows in the inductance L.
The value of current increases linearly with time in this interval, with ( d i d t ) being positive. As
the current through L increases, the polarity of the induced emf is taken as say, positive, the left
hand side of L being +ve. The equation for the circuit is,
di d i s Vs
Vs = L s or, =
dt dt L
The switch, S is put OFF during the period, T ≥ t ≥ TON , the OFF period being
TOFF = T − TON . ( T = TON + TOFF ) is the time period. As the current through L decreases, with its
direction being in the same direction as shown (same as in the earlier case), the induced emf
reverses, the left hand side of L being -ve. So, the induced emf (taken as –ve in the equation
given later) is added with the supply voltage, being of the same polarity, thus, keeping the
current ( is = i0 ) in the same direction. The current ( is = i0 ) decreases linearly in the time interval,
TOFF , as the output voltage is assumed to be nearly constant at v0 ≈ V0 , with ( d i s d t ) being
negative, as Vs < V0 , which is derived later.
The equation for the circuit is,
di d i s (Vs − V0 )
Vs = V0 + L s or, =
dt dt L
The source current waveform is shown in Fig. 17.2b. As stated earlier, the current varies
linearly from I 1 ( I min ) to I 2 ( I max ) during the time interval, TON .
So, using the expression for d i s d t during this time interval,
I 2 − I 1 = I max − I min = (Vs / L ) TON .
Similarly, the current varies linearly from I 2 ( I max ) to I 1 ( I min ) during the time interval, TOFF .
So, using the expression for d i s d t during this time interval,
I 2 − I1 = I max − I min = [(V0 − Vs ) / L] TOFF .
Equating the two equations, (V s / L ) T ON = [(V 0 − V s ) / L ] T OFF , from which the average
value of the output voltage is,
⎛ T ⎞ ⎛ T ⎞ ⎛ ⎞
⎟⎟ = Vs ⎛⎜
1 1 ⎞
V0 = Vs ⎜⎜ ⎟⎟ = Vs ⎜⎜ ⎟⎟ = Vs ⎜⎜ ⎟
⎝ TOFF ⎠ ⎝ T − TON ⎠ ⎝ 1 − (TON / T ) ⎠ ⎝1− k ⎠
The time period is T = TON + TOFF , and the duty ratio is,
k = (TON / T ) = [TON / (TON + TOFF )] , with its range as 1.0 ≥ k ≥ 0.0 . The ON time interval is
TON = k T . As stated in the previous case, the range of k is reduced. This is, because the
minimum value is higher than the minimum (0.0), and the maximum value is lower than the
maximum (1.0), for reasons given there, which are also valid here. As shown, the source current
is assumed to be continuous. The expression for the output voltage can be obtained by using
other procedures.
In this case, the output voltage is higher than the input voltage, as contrasted with the
previous case of buck converter (dc-dc). So, this is called boost converter (dc-dc), when a self-
commutated device is used as a switch. Instead, if thyristor is used in its place, this is termed as
step-up chopper. The variation (range) of the output voltage can be easily computed.
Buck-Boost Converters (dc-dc)
A buck-boost converter (dc-dc) is shown in Fig. 17.3. Only a switch is shown, for which a
device belonging to transistor family is generally used. Also, a diode is used in series with the
load. The connection of the diode may be noted, as compared with its connection in a boost
converter (Fig. 17.2a). The inductor, L is connected in parallel after the switch and before the
diode. The load is of the same type as given earlier. A capacitor, C is connected in parallel with
the load. The polarity of the output voltage is opposite to that of input voltage here.
When the switch, S is put ON, the supply current ( is ) flows through the path, Vs , S and L,
during the time interval, TON . The currents through both source and inductor ( i L ) increase and
are same, with ( d i L d t ) being positive. The polarity of the induced voltage is same as that of
the input voltage. The equation for the circuit is,
di d i L Vs
Vs = L L or, =
dt dt L
Is Switch I0
+ S -
L
Vs L O V0
IL A C
D
- +
Fig. 17.3(a): Buck-boost converter (dc-dc)
IL2
IL1
TON T 2T
TOFF
Fig. 17.3(b): Inductor current (iL) waveform
Then, the switch, S is put OFF. The inductor current tends to decrease, with the polarity of
the induced emf reversing. ( d i L d t ) is negative now, the polarity of the output voltage, V0
being opposite to that of the input voltage, Vs . The path of the current is through L, parallel
combination of load & C, and diode D, during the time interval, TOFF . The output voltage
remains nearly constant, as the capacitor is connected across the load.

The equation for the circuit is,
di d i L V0
L L = V0 or, =
dt dt L
The inductor current waveform is shown in Fig. 17.3b. As stated earlier, the current varies
linearly from I L1 to I L 2 during the time interval, TON . Note that I L1 and I L 2 are the minimum
and maximum values of the inductor current respectively. So, using the expression for d i L d t
during this time interval, I L 2 − I L1 = (Vs / L ) TON .
Similarly, the current varies linearly from I L 2 to I L1 during the time interval, TOFF . So, using
the expression for d i L d t during this time interval, I L 2 − I L1 = (V0 / L ) TOFF .
Equating the two equations, (V s / L ) T ON = (V 0 / L ) T OFF , from which the average value of
the output voltage is,
⎛T ⎞ ⎛ T ⎞ ⎛ (TON / T ) ⎞
⎟⎟ = Vs ⎛⎜
k ⎞
V0 = Vs ⎜⎜ ON ⎟⎟ = Vs ⎜⎜ ON ⎟⎟ = Vs ⎜⎜ ⎟
⎝ TOFF ⎠ ⎝ T − TON ⎠ ⎝ 1 − (TON / T ) ⎠ ⎝1− k ⎠
The time period is T = TON + TOFF , and the duty ratio is,
k = (TON / T ) = [TON / (TON + TOFF )] . The ON time interval is TON = k T . It may be observed that,
for the range 0 ≥ k > 0.5 , the output voltage is lower than the input voltage, thus, making it a
buck converter (dc-dc). For the range 0.5 > k ≥ 1.0 , the output voltage is higher than the input
voltage, thus, making it a boost converter (dc-dc). For k = 0.5 , the output voltage is equal to the
input voltage. So, this circuit can be termed as a buck-boost converter. Also it may be called as
step-up/down chopper. It may be noted that the inductor current is assumed to be continuous.
The range of k is somewhat reduced due to the reasons given earlier. The expression for the
output voltage can be obtained by using other procedures.
Control Strategies
In all cases, it is shown that the average value of the output voltage can be varied. The two
types of control strategies (schemes) are employed in all cases. These are:
(a) Time-ratio control, and (b) Current limit control.
Time-ratio Control
In the time ratio control the value of the duty ratio, k = TON / T is varied. There are two ways,
which are constant frequency operation, and variable frequency operation.
Constant Frequency Operation
In this control strategy, the ON time, TON is varied, keeping the frequency ( f = 1 / T ), or
time period T constant. This is also called as pulse width modulation control (PWM). Two cases
with duty ratios, k as (a) 0.25 (25%), and (b) 0.75 (75%) are shown in Fig. 17.4. Hence, the
output voltage can be varied by varying ON time, TON .

Load-voltage
v0
TON
TOFF
V0 k = 0.25
T t
V0
v0
k = 0.75
TON TOFF
T t
Fig. 17.4: Pulse-width modulation control (constant frequency)
Variable Frequency Operation

In this control strategy, the frequency ( f = 1 / T ), or time period T is varied, keeping either
(a) the ON time, TON constant, or (b) the OFF time, TOFF constant. This is also called as
frequency modulation control. Two cases with (a) the ON time, TON constant, and (b) the OFF
time, TOFF constant, with variable frequency or time period ( T ), are shown in Fig. 17.5. The
output voltage can be varied in both cases, with the change in duty ratio, k = TON / T .

v0
TON k = 0.25
t
v0
k = 0.75
TON TOFF
T t
(a) Constant TON
v0
TOFF TON k = 0.25
T t
v0 Load voltage
TOFF
TON k = 0.75
T t
(b) Constant TOFF

Fig. 17.5: Output voltage waveforms for variable frequency system
There are major disadvantages in this control strategy. These are:

(a) The frequency has to be varied over a wide range for the control of output voltage in
frequency modulation. Filter design for such wide frequency variation is, therefore, quite
difficult.
(b) For the control of a duty ratio, frequency variation would be wide. As such, there is a
possibly of interference with systems using certain frequencies, such as signaling and
telephone line, in frequency modulation technique.
(c) The large OFF time in frequency modulation technique, may make the load current
discontinuous, which is undesirable.
Thus, the constant frequency system using PWM is the preferred scheme for dc-dc converters
(choppers).

Current Limit Control
As can be observed from the current waveforms for the types of dc-dc converters described
earlier, the current changes between the maximum and minimum values, if it (current) is
continuous. In the current limit control strategy, the switch in dc-dc converter (chopper) is turned
ON and OFF, so that the current is maintained between two (upper and lower) limits. When the
current exceed upper (maximum) limit, the switch is turned OFF. During OFF period, the current
freewheels in say, buck converter (dc-dc) through the diode, D F , and decreases exponentially.
When it reaches lower (minimum) limit, the switch is turned ON. This type of control is
possible, either with constant frequency, or constant ON time, TON . This is used only, when the
load has energy storage elements, i.e. inductance, L. The reference values are load current or
load voltage. This is shown in Fig. 17.6. In this case, the current is continuous, varying between
I max and I min , which decides the frequency used for switching. The ripple in the load current can
be reduced, if the difference between the upper and lower limits is reduced, thereby making it
minimum. This in turn increases the frequency, thereby increasing the switching losses.
I max
i0 I min
v0
TON TOFF
t
T
Fig. 17.6: Current limit control
In this lesson, first one in this module (#3), the three basic circuits − buck, boost and buck-
boost, of dc-dc converters (choppers) are presented, along with the operation and the derivation
of the expressions for the output voltage in each case, assuming continuous conduction. The
different strategies employed for their control are discussed. In the next lesson − second one, the
expression for the maximum and currents for continuous conduction in buck dc-dc converter will
be derived.

Module
3
DC to DC Converters
Lesson
18
Analysis of Buck
Converter (DC-DC) Circuit
Study of the following in respect of the buck converter (dc-dc) circuit, with inductive (R-L) and
battery (or back emf = E) load, assuming continuous conduction
• Derivation of the expressions for the maximum and minimum load currents
• Calculation of the following:
(a) the duty ratio for the limit for continuous conduction
(b) the average value and the ripple factor of the load current
(c) the harmonic components of the output voltage waveform
Introduction
In the last lesson − first one in the module (#3), firstly the circuits of the various types of dc-
dc converters (choppers), such as buck, boost and buck-boost, were presented. Then, the
operation and the derivation of the expressions for the output voltage for the above dc-dc
converters, including current waveforms, were described in detail. Lastly, the different control
strategies used were briefly discussed.
In this lesson − the second one in this module, the analysis of the buck converter (dc-dc) or
step-down chopper circuit, using thyristor as a switching device, with inductive (R-L) and
battery (or back emf = E) load, is presented in detail. Starting with the derivation of the
expressions for the maximum and minimum load currents, assuming continuous conduction, the
procedure for the calculation of following expressions ─ the duty ratio for the limit of continuous
conduction, the average value and the ripple factor, of the output (load) current, and the
harmonic components of the output voltage waveform, are described in detail.
Keywords: Buck converter (dc-dc), Step-down chopper, Output (load) current – maximum and
minimum values, average value, ripple factor, harmonic analysis.
Buck Converter (DC-DC)

The circuit of the buck converter (dc-dc) or step-down chopper using thyristor, with
inductive (R-L) and battery (or back emf = E) load, is shown in Fig. 18.1. The switch in Fig.
17.1a is replaced by a thyristor here, where the components of the load, such as R, L & E, are
also shown. The output (load) voltage and current waveforms for both
(a) discontinuous, and (b) continuous conduction are shown in Fig. 18.2.
i0 LOAD
A K Switch R
+
+
G
L
Vs V0 +
DF E
-
-
-
Fig. 18.1: Step-down chopper circuit using thyristor.
Ig
0
t
io
0
v0 t
VS
E
0
TON TOFF t
T
(a) Discontinuous load current
Ig
0
t
io
Imax
Imin
0
iT iD t
v0
VS
V0
0
TON TOFF t
(b) Continuous load current

Fig. 18.2: Two modes operation of the chopper.

Maximum and Minimum Values of the Load Current
The procedure for finding the maximum and minimum of the load current, assuming
continuous conduction, is described. The operation of the chopper circuit has been discussed in
the earlier lesson. There are two modes of operation. Mode 1 starts at t = 0 , when the thyristor is
turned ON, with the diode, D F being OFF at that time, and continues till t = TON . During this
time period, the load current increases. The induced emf in the load inductance L, is positive,
i.e., having the same polarity as that of the input voltage, opposing it. Mode 2 starts at t = TON ,
when the thyristor is turned OFF by auxiliary circuit (not shown in Fig. 18.1), and the diode, D F
turns ON at that time, as the load current starts decreasing, and the induced emf in the load
inductance, L changes polarity, with the voltage across the diode now being positive. This
continues till t = T , end of the time period. Then the cycle repeats.
Mode 1: The equation for the load (output) current in the circuit during this time interval,
0 ≤ t ≤ TON is,
d i0 di
V S = R i0 + L +E or, VS − E = R i0 + L 0
dt dt
The current is the load current, same as the source current during this time interval. The values of
the load current ( i0 ) at t = 0 and t = TON , are I min and I max respectively. The expression for the
load current is, i0 = A e − t / τ + B
where A and B are constants, and time constant is, τ = L / R .
At t = 0 , i0 = A + B = I min
At t = ∞ , i0 = B = [(Vs − E ) / R]
So, A = I min − [(Vs − E ) / R]
Substituting the values of A & B, the expression for the load current is,
⎡ (V − E ) ⎤
i0 = ⎢ s ⎥( )
1 − e −t / τ + I min e −t / τ
⎣ R ⎦
At t = TON , i0 = I max . So,
⎡ (V − E ) ⎤
I max = ⎢ s (
⎥ 1− e )
−TON / τ
+ I min e −TON / τ
⎣ R ⎦
⎡ (V − E ) ⎤
or, I max − I min e −TON / τ = ⎢ s ( ⎥ )
1 − e −TON / τ
⎣ R ⎦
This is the first expression obtained for mode 1 between I max and I min . Similarly, the second one
will be derived for mode 2.
Mode 2: The equation for the load (output) current in the circuit during this time interval,
0 ≤ t ≤ TOFF is,
di di
0 = R i0 + L 0 + E or, − E = R i0 + L 0
dt dt
It may be noted here that the time ( t = 0 ) is taken here from the start of mode 2, i.e., the end of
mode 1. The current is the load current, and the current through the diode, D F during this time
interval. The values of the load current ( i0 ) at t = 0 and t = TOFF , are I max and I min respectively.
The expression for the load current is, i0 = A e − t / τ + B .

At t = 0 , i0 = A + B = I max
At t = ∞ , i0 = B = −(E / R )
So, A = I max + (E / R )
Substituting the values of A & B, the expression for the load current is,
⎛E⎞
( )
i0 = −⎜ ⎟ 1 − e −t / τ + I min e −t / τ
⎝R⎠
At t = TOFF , i0 = I min . So,
⎛E⎞
( )
I min = − ⎜ ⎟ 1 − e −TOFF / τ + I max e −TOFF / τ
⎝R⎠
⎛E⎞
(
or, I max e −TOFF /τ − I min = −⎜ ⎟ 1 − e −TOFF / τ )
⎝ R⎠
This is the second expression obtained for mode 2 between I max and I min .
From these two expressions, the currents, I max and I min are derived as,
−T / τ
⎛ V ⎞ ⎡1 − e ON ⎤ ⎛ E ⎞ ⎛ V ⎞ ⎡1 − e ON ⎤ ⎛ E ⎞
− RT / L
I max = ⎜ s ⎟ ⎢ −T / τ ⎥
−⎜ ⎟ or, I max = ⎜ s ⎟ ⎢ −R T / L ⎥
− ⎜ ⎟ , and
⎝ R ⎠ ⎣ 1− e ⎦ ⎝R⎠ ⎝ R ⎠ ⎣ 1− e ⎦ ⎝R⎠
T /τ
⎛ Vs ⎞ ⎡ e ON − 1⎤ ⎛ E ⎞ ⎛ Vs ⎞ ⎡ e ON − 1⎤ ⎛ E ⎞
RT / L
I min = ⎜ ⎟ ⎢ T / τ ⎥−⎜ ⎟ or, I min = ⎜ ⎟ ⎢ R T / L ⎥−⎜ ⎟
⎝ R ⎠ ⎣ e −1 ⎦ ⎝ R ⎠ ⎝R⎠ ⎣ e −1 ⎦ ⎝ R ⎠
Ripple content in the Load Current
As given earlier, the load (output) current varies between the maximum and minimum values
( I max and I min ). Therefore, the ripple content of the current is,
(
−T / τ
⎛ V ⎞ ⎡ 1 − e ON 1 − e
I max − I min = ⎜ s ⎟ ⎢
)(
− (T −TON ) / τ
) ( )(
⎤ ⎛ Vs ⎞ ⎡ 1 − e −TON / τ 1 − e −TOFF / τ ⎤ )
⎥=⎜ ⎟ ⎢
⎝R⎠ ⎣ 1 − e −T / τ( ) ⎦ ⎝R⎠⎣ 1 − e −T / τ ( ⎥
⎦ )
The above expression for ripple content is independent of battery voltage or back emf (E). Using
the duty ratio, k = TON / T , the expression becomes,
⎛ Vs ⎞ ⎡ 1 − e
I max − I min = ⎜ ⎟ ⎢
( − k T /τ
)(
1 − e − (1−k ) T / τ ⎤ )
(
1 − e −T / τ ) ⎥,
⎝R⎠ ⎣ ⎦
its per unit value being,
( )(
(I max − I min ) = ⎡ 1 − e − k T /τ 1 − e − (1−k ) T / τ ⎤ )
(Vs / R ) ⎢⎣ (
1 − e −T / τ ) ⎥
⎦
The current ( Vs / R ) is taken as 1.0 pu (100%).
The Duty Ratio (k) for the Limit of Continuous Conduction

The current waveforms for both continuous and discontinuous conduction are shown in Fig.
18.2. From the waveforms, it is observed that, for a low value of TON , or duty ratio, k , time
period, T being kept constant, the turn-off time, TOFF is large. The output current, i0 may go to
zero during this interval, depending on the circuit parameters. Therefore, the limit of continuous
conduction is reached, when the minimum current, I min goes to zero. So,

T /τ
⎛ V ⎞ ⎡ e ON − 1⎤ ⎛ E ⎞ eTON / τ − 1 ⎛ E ⎞
I min = ⎜ s ⎟ ⎢ T / τ −
⎥ ⎜ ⎟ = 0 or, =⎜ ⎟= g
⎝ R ⎠ ⎣ e −1 ⎦ ⎝ R ⎠ eT / τ − 1 ⎜⎝ Vs ⎟⎠
where g = (E / Vs )
So, the duty ratio for limit of continuous conduction is,
[ (
k ′ = (TON / T ) = (τ / T ) log e 1 + g eT / τ − 1)]
The output (load) current is continuous, if the actual duty ratio, k is more than the above duty
ratio, k ′ , and it becomes discontinuous, if k is lower than the above duty ratio, k ′ .
The Average Value of the Output Current
The average value of the output (load) current for continuous conduction (Fig. 18.2b) is
obtained as I av = (k Vs − E ) / R , as the average value of the output voltage is k Vs . This is,
because the average value of L (di / dt ) over the time period, T is zero.
This value can also be written as,
⎛ 1 ⎞⎡ ⎤ ⎛ 1 ⎞ ⎡TON ⎤ ⎛ 1 ⎞ ⎡TOFF ⎤
TON TOFF
I av = ⎜ ⎟ ⎢ ∫ i01 (t ) dt + ∫ i02 (t ) dt ⎥ = ⎜ ⎟ ⎢ ∫ i01 (t ) dt ⎥ + ⎜ ⎟ ⎢ ∫ i02 (t ) dt ⎥ = ( I T ) av + ( I D ) av ,

⎝ T ⎠ ⎢⎣ 0 0 ⎥⎦ ⎝ T ⎠ ⎢⎣ 0 ⎥⎦ ⎝ T ⎠ ⎢⎣ 0 ⎥⎦
where i01 and i02 are the output (load) currents in the time intervals, TON < t < 0 and TOFF < t < 0
(the time ( t = 0 ) is taken as the beginning of OFF period (mode 2)) respectively. If the
expression is derived by substituting the currents, i01 & i02 , its value comes out to be the same as
given earlier. The average values of the currents in the thyristor (I T )av and diode (I D )av , can also
be computed by using the expressions for the currents separately. These two expressions are not
included here, but are available in text book. All these values of the currents can also be obtained
by using other procedure.
Fourier Analysis of the Output Voltage Waveform
The output (load) voltage waveform for continuous conduction is shown in Fig. 18.2.b. This
voltage is periodic in nature and also independent of the parameters of the load. The symbols,
including some described earlier, are given here.
v0 = Instantaneous value of the output (load) voltage
Vs = Source (input) voltage (constant)
V0 = Average value of the output voltage
T = TON + TOFF = Time period of the thyristor chopper (step-down)*
TON = Time interval for which the thyristor is ON*
TOFF = T − TON = Time interval for which the thyristor is OFF*
f = 1 / T = Frequency (Hz) for the thyristor chopper (step-down)*
ω = 2 π f = Angular frequency (rad/s)
θ = ω t = Angle (rad)
ω T = 2 π = Angle (rad) for time period, T
a n & bn are the maximum values of the sine and cosine components of the harmonics of order n,
present in the output voltage waveform respectively.

cn & θ n are the maximum value (amplitude), and phase angle, of nth harmonic component
respectively.
The relationships are cn = a n2 + bn2 , and θ n = tan −1 (bn / an ) ,
and the other relationships are an = cn cos θ n and bn = cn sin θ n .
The rms value of nth harmonic component = cn / 2
* It may be noted that, when the thyristor (device) in the step-down chopper (Fig. 18.1), or buck
converter (dc-dc), is ON, or conducting, the diode, D F is not conducting (OFF), and vice versa,
i.e., when the thyristor (device) is OFF, or not conducting, the diode, D F is conducting (ON).
The output (load) voltage waveform for one time period T , is,
v0 = Vs for TON < t < 0 ; v0 = 0 for T < t < TON
In terms of the Fourier components, the expression is,
∞ ∞
v0 = V0 + ∑ (an sin nθ + bn cos nθ ) = V0 + ∑ cn sin (nθ + θ n )
n =1 n =1
where,
ωT ωT
1 1 ON ⎛V ⎞
an = ∫ v0 sin (n θ ) dθ = ∫ Vs sin (n θ ) dθ = ⎜⎜ s ⎟⎟ cos n θ 0
2π k
π 0 π 0 ⎝ nπ ⎠
⎛V ⎞ ⎛ 2V ⎞
= ⎜⎜ s ⎟⎟ (1 − cos 2 π n k ) = ⎜⎜ s ⎟⎟ ( sin 2 ( π n k ) )
⎝ nπ ⎠ ⎝ nπ ⎠
ωT ω TON
1 1 ⎛V ⎞ ⎛V ⎞
bn = ∫v cos (n θ ) dθ = ∫ Vs cos (n θ ) dθ = ⎜⎜ s ⎟⎟ sin n θ 2π k
=⎜⎜ s ⎟⎟ (sin 2 π k )
π π ⎝ nπ ⎠ ⎝ nπ
0 0
0 0 ⎠
⎛V ⎞ ⎛ 2V ⎞
= ⎜⎜ s ⎟⎟ (sin 2 π n k ) = ⎜⎜ s ⎟⎟ (sin π n k ) (cos π n k )
⎝ nπ ⎠ ⎝ nπ ⎠
⎛ 2V ⎞
cn = ⎜⎜ s ⎟⎟ (sin π n k )
⎝ nπ ⎠
θ n = tan −1 (cot π n k ) = (π 2) − (π n k )
The average value (dc) is V0 = k Vs , which has been derived in lesson #17 (module 3).
Substituting the above values of cn & θ n ,
∞
⎛ 2V ⎞
v0 = V0 + ∑ ⎜⎜ s ⎟⎟ (sin π n k ) (sin (nθ + (π 2) − (π n k )) )
n =1 ⎝ n π ⎠
∞
⎛ 2V ⎞ ∞
⎛ 2V ⎞
= V0 + ∑ ⎜ s ⎟ (sin π n k ) ( cos [ nθ − (n π k ) ]) = V0 + ∑ ⎜ s ⎟ (sin π n k ) ( cos[n (θ − π k )]) The
n =1 ⎝ n π ⎠ n =1 ⎝ n π ⎠
maximum value of the fundamental component is, c1 = ((2Vs ) π ) (sin π k ) ,

and its phase angle (rad) is, θ1 = (π 2) − (π k ) .
The magnitude of the maximum (or rms) value of the harmonic components decreases as its
order (n) increases.
∞ ∞
The rms value of the waveform is, Vor = (V0 ) 2 + ∑ (cn / 2 ) 2 = (V0 ) 2 + ( 12 ) ∑ (cn ) 2
n =1 n =1
The rms value is computed as,

T
⎛1⎞
ON
T
V0 r = ⎜ ⎟ ∫ (Vs ) 2 dt = ON Vs = k Vs
⎝T ⎠ 0 T
It can be observed that the amplitude of the harmonic component depends on the order of the
harmonic, n and also on the duty ratio, k. The maximum value of the nth harmonic component
occurs, when sin (π n k ) = 1 , and its value (V) is,
2 Vs 0.637 Vs 2 Vs 0.45 Vs
= , with its rms value (V) as =
nπ n nπ n
The value of the angle for the above condition, i.e., at which the maximum value of the
magnitude of the nth harmonic component of the output voltage occurs, is,
π n k = (4m + 1) (π / 2) = 2 π m + (π / 2) , or n k = (4m + 1) / 2 = 2 m + 12 or, ( 2 m + 0.5 )
Firstly, the average value or dc component and the rms values of all harmonic components,
of the output (load) voltage, are computed as per the formula given earlier. It may be noted that,
the rms values of only a few harmonic components need be computed, because the rms values
decrease, as the order of harmonic increases (having an inverse relationship with it), as given
earlier. Then, using the expression for the rms value, it (rms value) is computed. Finally, it can
be checked from the expression for the rms value given earlier.
As first example, the case of fundamental frequency ( n = 1 ) is taken up. The value of duty
ratio is ( k = 0.5( 12 ) ) as ( k < 1.0 ), at which the magnitude of the output voltage is maximum at
the above frequency. If the third harmonic ( n = 3 ) is chosen as another example, more than one
value, in this case, three values of the duty ratio – ( k = 0.167 ( 16 ) & 0.833( 65 ) ), and also the
previous value of ( k = 0.5( 12 ) ), as k < 1.0 , are obtained. If first two values of k are substituted,
the results obtained, using the ascending order, are sin (π / 2) = 1 and
sin (5 π / 2) = sin (π / 2) = 1 . But, if the value, ( k = 0.5( 12 ) ) is substituted, the results obtained is
cn = sin (3π / 2) = − sin (π / 2) = sin (−π / 2) = −1 . For this value in this case, 3π k = (3π / 2) or
(− π / 2) . So, the set of values would be 3π k = (2 m π + (3π / 2)) or (2 m π − ( π / 2)) . Earlier, the
value of cn is chosen as positive only, assuming that its angle would take care of the sign, i.e.,
for cn = +1 , θ n = 0° , and for cn = −1 , θ n = 180° (π ) . The angle ( θ n ) can be obtained by using the
sign of two components, an & bn . But if a close look at the formula of cn is taken, it can have
both +ve and –ve values, i.e., cn = sin (π n k ) = ±1 , being square root of a +ve quantity. The
value would now be, n k = (4m ± 1) / 2 = 2 m ± 12 or, ( 2 m ± 0.5 ). So, for ( n = 3 ), three values of
duty ratio, k as given earlier, are obtained. Similarly, for any other odd harmonic ( n = 2 m + 1 ),
the duty ratios can be computed. It may also be observed that, for the duty ratio of ( k = 0.5( 12 ) ),
the magnitudes of the output voltage at all odd harmonics are maximum.
Now, for even harmonics ( n = 2 m ), the duty ratios for which the magnitude of the
component of output voltage is maximum, are obtained. For second harmonic ( n = 2 ), two
values of duty ratio obtained using the formula ( 2 k = 2 m ± 12 ) are,
k = 0.25( 14 ) & 0.75( 34 ) , as k < 1.0 . If these two values of k are substituted, the results obtained,
using the ascending order, are sin (π / 2) = 1 and
sin (3π / 2) = − sin (π / 2) = −1 . For fourth harmonic ( n = 4 ), the duty ratios obtained are,

k = 0.125( 18 ), 0.375( 83 ),0.625( 85 ) & 0.875( 78 ) , as k < 1.0 . Similarly, for the rms value of any other
even harmonic to be maximum (highest), the duty ratios can be computed. To obtain the
maximum value of average or dc component as per formula given earlier, the duty ratio is
( k = 1.0 ), it being an ideal one. In this case, the switch or the device is always ON in the time
period ( 0 − T ), with the output voltage being constant, and also same as the average value, which
is equal to the input (source) voltage. In the ideal case, no harmonic component, including
fundamental one, is present in the output voltage. But the duty ratio in normal case, for buck
converter (dc-dc) or step-down chopper (thyristor) circuit is ( k ≈ 1.0 ), due to the turn-off time
requirement of the switching device used. For this case, the rms and average values are nearly
equal, but the rms value is slightly higher than the average value. Both the above values are also
nearly maximum. The ripple content is very low, with the rms values of the harmonic
components, starting from fundamental, also being very low. All these can be checked from the
formula.
To eliminate a given harmonic or a set of harmonics in the output voltage waveform, the
condition to be satisfied is, sin π n k = 0 , for which the value of the angle is π n k = m π , or
n k = m . The case of even ( n = 2 m ) harmonics, starting from second ( n = 2 ), is taken up first.
The duty ratio required is k = 0.5 , as k < 1.0 , for the elimination of second harmonic
component. To eliminate fourth ( n = 4 ) harmonic component, two more values of duty ratio
( k = 0.25( 14 ) & 0.75( 34 ) ), including the earlier one ( k = 0.5 ), as k < 1.0 , are required. It may be
noted that, with the duty ratio (k = 0.5) , all even harmonic components are eliminated. To make
the average value or dc component zero (0), the duty ratio required is ( k = 0.0 ). But this is an
ideal case, in which the switch or the device is OFF. In normal case, duty ratio required is very
small ( k ≈ 0.0 ), due to requirement of both turn-on and turn-off times of the switching device
used. For this case, the rms and average values are nearly equal, but the rms value is slightly
higher than the average value. Both the above values are also nearly minimum. The ripple
content is very low, with the rms values of the harmonic components, starting from fundamental,
also being very low. All these can be checked from the formula. Now, the case of the elimination
of odd ( n = 2 m + 1 ) harmonic components is described. If third ( n = 3 ) harmonic is to be
eliminated, two values of duty ratios required are ( k = 0.333( 13 ) & 0.667 ( 23 ) ), as k < 1.0 .
Similarly, for any other (odd or even) harmonic component to be eliminated, the duty ratios can
be computed.
The rms value of the nth harmonic component of the output (load) current is,
(
In = n
c / 2 ) , where the load impedance for nth harmonic is Z n = R 2 + ( n ω L) 2 .
Zn
As stated earlier, the rms value of the harmonic components of the output voltage decreases and
also is inversely proportional to n, as the order of the harmonic (n) is increased. The impedance
at the harmonic frequency ( n f ) increases, and also is nearly proportional to n, if the load
resistance (R) is assumed to be much smaller than the inductive reactance ( 2 π n f L ), as the
order of the harmonic is increased. So, the rms value of the nth harmonic component of the output
current decreases at a faster rate, and also can be stated as being inversely proportional (nearly)
to n 2 , with the increase in the order of the harmonic. If R is very small, and can be neglected, as
compared to the inductive reactance, the rms value of the nth harmonic component of the output
current is inversely proportional to n 2 , i.e. proportional to ( 1 / n 2 ).

The harmonic content of the output voltage waveform is the ac ripple voltage ( V r ), which
can be easily computed as shown here, without computing the harmonic components. Its rms
value is defined as Vr = (V0 r ) 2 − (V0 ) 2 , the other symbols having been defined earlier. The
average value of the output voltage ( V0 ) is shown in Fig. 18.2b. If the X-axis is shifted to the
average value, the remaining part is the ac ripple voltage, having both positive and negative
values in a cycle. The expression for ac ripple voltage is obtained as, after substituting the
expressions of two voltages given earlier,
Vr = k (V s ) 2 − k 2 (Vs ) 2 = V s k − k 2
The ripple factor (RF) is defined as the ratio of ac ripple voltage to the average value, and is
obtained as,
V 1− k
RF = r =
V0 k
It may be noted that the ac ripple voltage, in terms of rms values of all harmonic components,
may also be computed as,
∞ ∞
Vr = ∑ (c n / 2 ) 2 = ( 12 ) ∑ (c n ) 2
n =1 n =1
This value is same as computed by the expression given earlier.
In this lesson ─ the second one in this module, the analysis of the analysis of the buck
converter (dc-dc) or step-down chopper circuit, using thyristor as a switching device, with
inductive (R-L) and battery (or back emf = E) load, is presented in detail The procedure for the
derivation of following expressions ─ the maximum and minimum output (load) currents,
assuming continuous conduction, the duty ratio for the limit of continuous conduction, the
average value and the ripple factor, of the output current, and the harmonic components of the
output voltage waveform, are described in detail. Starting with the next lesson ─ the third one in
this module, the operation of the additional circuits needed for commutation in thyristor-based
choppers, with relevant waveforms, will be taken up in detail.

Module
3
DC to DC Converters
Lesson
19
Commutation of
Thyristor-Based Circuits
Part-I
(i) Requirements to be satisfied for the successful turn-off of a SCR

(ii) The turn-off groups as per the General Electric classification
(iii) The operation of the turn-off circuits
(iv) Design of a SCR commutation circuit
A thyristor can be turned ON by applying a positive voltage of about a volt or a current of a

few tens of milliamps at the gate-cathode terminals. However, the amplifying gain of this
regenerative device being in the order of the 108, the SCR cannot be turned OFF via the gate
terminal. It will turn-off only after the anode current is annulled either naturally or using forced
commutation techniques. These methods of turn-off do not refer to those cases where the anode
current is gradually reduced below Holding Current level manually or through a slow process.
Once the SCR is turned ON, it remains ON even after removal of the gate signal, as long as a
minimum current, the Holding Current, Ih, is maintained in the main or rectifier circuit.
Fig. 3.1 Turn-off dynamics of the SCR
In all practical cases, a negative current flows through the device. This current returns to zero
only after the reverse recovery time trr, when the SCR is said to have regained its reverse
blocking capability. The device can block a forward voltage only after a further tfr, the forward
recovery time has elapsed. Consequently, the SCR must continue to be reverse-biased for a
minimum of tfr + trr = tq, the rated turn-off time of the device. The external circuit must therefore
reverse bias the SCR for a time toff > tq. Subsequently, the reapplied forward biasing voltage must
rise at a dv/dt < dv/dt (reapplied) rated. This dv/dt is less than the static counterpart. General
Electric has suggested six classification methods for the turn-off techniques generally adopted
for the SCR. Others have chosen different classification rules.
SCRs have turn-off times rated between 8 - 50 μsecs. The faster ones are popularly
known as 'Inverter grade' and the slower ones as 'Converter grade' SCRs. The latter are available
at higher current levels while the faster ones are expectedly costlier.
Classification of forced commutation methods

The six distinct classes by which the SCR can be turned off are:
Class A Self commutated by a resonating load
Class B Self commutated by an L-C circuit
Class C C or L-C switched by another load carrying SCR
Class D C or L-C switched by an auxiliary SCR
Class E An external pulse source for commutation
Class F AC line commutation
These examples show the classes as choppers. The commutation classes may be used in practice
in configurations other than choppers.
Class A, Self commutated by resonating the load
Fig. 3.2 A resonant load commutated SCR and the corresponding waveforms
When the SCR is triggered, anode current flows and charges up C with the dot as positive. The
L-C-R form a second order under-damped circuit. The current through the SCR builds up and
completes a half cycle. The inductor current will then attempt to flow through the SCR in the
reverse direction and the SCR will be turned off.
The current may be expressed as

1 1 + RCs
I ( s) = V =V
s ( Ls + R ) LRCs 3 + Ls 2 + Rs
1 + RCs
The solution of the above equation is of the form

V⎡ 1 ω n2 −t RC ⎤
i (t ) = ⎢1 + e sin( wt + φ )⎥
R⎢
⎣ 1−ξ 2 ξ ⎥⎦
where,
1 L
ξ= , ω n = L , ω = ω n 1 − ξ 2 , φ = tan −1 2 RCω
C
2R C
and
⎡ ω2 ⎤
v(t ) = V ⎢ n
e −t 2 RC sin(ωt ) + 1⎥
⎢⎣ 1 − ξ 2 ⎥⎦
The capacitor voltage is at its peak when the SCR turns off and the capacitor discharges into
the resistance in an exponential manner. The SCR is reverse-biased till the capacitor voltages
returns to the level of the supply voltage V.
Class B, Self commutated by an L-C circuit

The Capacitor C charges up in the dot as positive before a gate pulse is applied to the
SCR. When SCR is triggered, the resulting current has two components.
The constant load current Iload flows through R - L load. This is ensured by the large
reactance in series with the load and the freewheeling diode clamping it. A sinusoidal current
flows through the resonant L-C circuit to charge-up C with the dot as negative at the end of the
half cycle. This current will then reverse and flow through the SCR in opposition to the load
current for a small fraction of the negative swing till the total current through the SCR becomes
zero. The SCR will turn off when the resonant–circuit (reverse) current is just greater than the
load current.
The SCR is turned off if the SCR remains reversed biased for tq > toff, and the rate of rise
of the reapplied voltage < the rated value.
Fig. 3.3 Class B, L-C turn-off

Problem #1
A Class B turn-off circuit commutates an SCR. The load current is constant at 10 Amps.
Dimension the commutating components L and C. The supply voltage is 100VDC.
Soln # 1
The commutating capacitor is charged to the supply voltage = 100 V
The peak resonant current is,
i peak = V C
L
Assuming, i peak ~1.5.I load

C = (15 ) 2 = 0.0225
L 100
The SCR commutates when the total current through it reaches zero.This corresponds to 0.73
rads after the zero crossing of the resonant current. The capacitor voltage at that instant is 75
volts. After the SCR turns off, the capacitor is charged linearly by the load current.
If the SCR is to commutate at twice this load current, for a rated "Inverter grade' SCR turn-
off time of 20 μsecs,
(2.I load ).t = 75.C
20.20 μF
C=
75
= 15.33 ≈ 15 μF
C
L= = 667 ≈ 700
0.0225 μH
20
The reapplied forward voltage has a dV = = 1.33 volts/sec rise.
dt 15
It can be observed that if the peak of the commutating current is just equal to the load
current, the turn-off time would be zero as the capacitor would not be able to impress any
negative voltage on the SCR.
Class C, C or L-C switched by another load–carrying SCR

This configuration has two SCRs. One of them may be the main SCR and the other auxiliary.
Both may be load current carrying main SCRs. The configuration may have four SCRs with the
load across the capacitor, with the integral converter supplied from a current source. Assume
SCR2 is conducting. C then charges up in the polarity shown. When SCR1 is triggered, C is
switched across SCR2 via SCR1 and the discharge current of C opposes the flow of load current
in SCR2.
Fig. 3.4 Class C turn-off, SCR switched off by another load-carring SCR

Class D, L-C or C switched by an auxiliary SCR
Example 1
The circuit shown in Figure 3.3 (Class C) can be converted to Class D if the load current is
carried by only one of the SCR’s, the other acting as an auxiliary turn-off SCR. The auxiliary
SCR would have a resistor in its anode lead of say ten times the load resistance.
Fig. 3.5 Class D turn-off. Class D commutation by a C (or LC) switched by an

Auxiliary SCR.
Example 2
SCRA must be triggered first in order to charge the upper terminal of the capacitor as
positive. As soon as C is charged to the supply voltage, SCRA will turn off. If there is substantial
inductance in the input lines, the capacitor may charge to voltages in excess of the supply
voltage. This extra voltage would discharge through the diode-inductor-load circuit.
When SCRM is triggered the current flows in two paths: Load current flows through the
load and the commutating current flows through C- SCRM -L-D network. The charge on C is
reversed and held at that level by the diode D. When SCRA is re-triggered, the voltage across C
appears across SCRM via SCRA and SCRM is turned off. If the load carries a constant current as
in Fig. 3.4, the capacitor again charges linearly to the dot as positive.
Problem # 2
A Class D turn-off circuit has a commutating capacitor of 10 μF. The load consists of a clamped
inductive load such that the load current is reasonably constant at 25 amperes. The 'Inverter
grade' SCR has a turn-off time of 12 μsecs. Determine whether the SCR will be satisfactorily
commutated. Also dimension the commutating inductor. The supply voltage is 220 VDC.

Soln # 2
The capacitor is initially charged to the supply voltage 220 V at the end of the conduction period
of SCRA.
When SCRM is triggered, the 25 Amps load current and the L-C ringing current flows
through it. Peak current through SCR is
i peak = 25 + 220 C Amps

L
Selecting L such that ipeak ~ 1.5 . load current,
25
C = = 0.0568
L 2.220
L = 3.1 mH
Assuming that the capacitor charges to 70% of its original charge because of losses in the
C- SCRM -L-D network, and it charges linearly when SCRA is again triggered,
I load .t q = 10(0.7.220)10 −6 = 1540.10 −6

tq = 1540 / 25 = 61.6 μ sec s
The SCR can therefore be successfully commutated.
The maximum current that can be commutated with the given Capacitor at the 220 V
supply voltage is
I load = 1540 / 12 = 128 Amps
For the 25 Amps load current the capacitor just enough would have a rating of
C = I load .t q /(0.7.220) = (25.12) / 154 = 1.95 ≈ 2.0 μF

If the supply voltage is reduced by a factor K, the required capacitor rating
increases by the same factor K for the same load current.
Class E – External pulse source for commutation

The transformer is designed with sufficient iron and air gap so as not to saturate. It is capable of
carrying the load current with a small voltage drop compared with the supply voltage.
When SCR1 is triggered, current flows through the load and pulse transformer. To turn SCR1 off
a positive pulse is applied to the cathode of the SCR from an external pulse generator via the
pulse transformer. The capacitor C is only charged to about 1 volt and for the duration of the
turn-off pulse it can be considered to have zero impedance. Thus the pulse from the transformer
reverses the voltage across the SCR, and it supplies the reverse recovery current and holds the
voltage negative for the required turn-off time.

SCR
LOAD
Fig. 3.6 Class E, External pulse commutation

Class F, AC line commutated
If the supply is an alternating voltage, load current will flow during the positive half
cycle. With a highly inductive load, the current may remain continuous for some time till the
Fig. 3.7 Class F, natural commutation by supply voltage
energy trapped in the load inductance is dissipated. During the negative half cycle, therefore, the
SCR will turn off when the load current becomes zero 'naturally'. The negative polarity of the
voltage appearing across the outgoing SCR turns it off if the voltage persists for the rated turn-
off period of the device. The duration of the half cycle must be definitely longer than the turn-
off time of the SCR.
The rectifier in Fig.3.6 is supplied from an single phase AC supply. The commutation
process involved here is representative of that in a three phase converter. The converter has an
input inductance Ls arising manly out of the leakage reactance of the supply transformer.
Initially, SCRs Th1 and Th1' are considered to be conducting. The triggering angle for the
converter is around 600. The converter is operating in the continuous conduction mode aided by
the highly-inductive load.
When the incoming SCRs, Th2 and Th2' are triggered, the current through the incoming
devices cannot rise instantaneously to the load current level. A circulating current Isc builds up in
the short-circuited path including the supply voltage, Vs-Ls-Th1'- Th2 and Vs- Ls-Th2'-Th1 paths.
This current can be described by:
Vs sin(ωt − 90 0 ) Vs V cos(ωt ) Vs
I sc = + cos α = s + cos α
ωL s ωLs ωLs ωL s
where α the triggering angle and Isc and Vs as shown in Fig. 3.6.
This expression is obtained with the simplifying assumption that the input inductance
contains no resistances. When the current rises in the incoming SCRs, which in the outgoing
ones fall such that the total current remains constant at the load current level. When the current in
the incoming ones reach load current level, the turn-off process of the outgoing ones is initiated.
The reverse biasing voltage of these SCRs must continue till they reach their forward blocking
state. As is evident from the above expression, the overlap period is a function of the triggering
angle. It is lowest when α ~ 900. These SCRs being 'Converter grade', they have a larger turn-off
time requirement of about 30-50 μsecs.
The period when both the devices conduct is known as the 'overlap period'. Since all
SCRs are in conduction, the output voltage for this period is zero. If the 'fully-controlled'
converter in Fig. 3.7 is used as an inverter with triggering angles > 900, the converter triggering
can be delayed till the 'margin angle' which includes the overlap angle and the turn-off time of
the SCR - both dependent on the supply voltages.
Rate of rise of forward voltage, dv/dt

The junctions of any semiconductor exhibit some unavoidable capacitance. A changing
voltage impressed on this junction capacitance results in a current, I = C dv/dt. If this current is
sufficiently large a regenerative action may occur causing the SCR to switch to the on state. This
regenerative action is similar to that which occurs when gate current is injected. The critical rate
of rise of off-state voltage is defined as the maximum value of rate of rise of forward voltage
which may cause switching from the off-state to the on-state.
Since dv/dt turn-on is non-destructive, this phenomenon creates no problem in applications in

which occasional false turn-on does not result in a harmful affect at the load. Heater application
is one such case. However, at large currents where dv/dt turn-on is accompanied by partial turn-
on of the device area a high di/dt occurs which then may be destructive.
The majority of inverter applications, however, would result in circuit malfunction due to
dv/dt turn-on. One solution to this problem is to reduce the dv/dt imposed by the circuit to a
value less than the critical dv/dt of the SCR being used. This is accomplished by the use of a
circuit similar to those in Figure 3.8 to suppress excessive rate of rise of anode voltage. Z
represents load impedance and circuit impedance. Variations of the basic circuit is also shown
where the section of the network shown replaces the SCR and the R-C basic snubber.
Since circuit impedances are not usually well defined for a particular application, the values
of R and C are often determined by experimental optimization. A technique can be used to
simplify snubber circuit design by the use of nomographs which enable the circuit designer to
select an optimized R-C snubber for a particular set of circuit operating conditions.
Another solution to the dv/dt turn-on problem is to use an SCR with higher dv/dt turn-on
problem is to use an SCR with higher dv/dt capability. This can be done by selecting an SCR
designed specially for high dv/dt applications, as indicated by the specification sheet. Emitter
shorting is a manufacturing technique used to accomplish high dv/dt capability.

Fig. 3.8 dv/dt supression circuits
Questions
#1 For a Class D turn-off SCR, the load consists of a resistance only. If the supply voltage and
SCR turn-off ratings are as in Problem # 1 calculate the required value of the commutating
capacitor.
Ans: (Hints): The capacitor would now charge in an exponential manner. The time it takes to
discharge from its reverse charged state once SCRA is triggered is the circuit turn-off time which
must be in excess of the rated 12 μsecs.
#2 For a Class F converter, will the overlap period rise with the leakage inductance of the
converter? What happens to the output voltage?
Ans: Yes. The overlap time is directly related to the commutating inductance. The output
voltage decreases. In fact, this inductor limits the maximum output current of the converter. The
input current maximum would be as for a shorted network with the leakage inductance only
present.
#3 Can the output DC voltage be controlled in the above circuits?
Ans: Yes. Most of the above circuits are also called 'forced commutated' DC-DC chopper
circuits.

Module
3
DC to DC Converters
Lesson
20
Commutation of
Thyristor-Based Circuits
Part-II
(i) Practical significance of commutation

(ii) Limitations of line commutation
(iii) Ability to determine commutation interval
(iv) Insight to different methods of commutation
(v) Consequences of the commutating methods on device stresses
20.1 Introduction
The commutation process plays an important role in the operation and control of both
naturally commutated (or line commutated) and forced commutated SCR based converters.
These converters may be either AC-DC, DC-DC or DC-AC converters. The AC-DC Phase
Fig. 20.1 Top: A three-phase Phase Angle Converter; bottom: The input
three-phase voltage waveforms
Angle Converter, (PAC) continues to be used in much high power and very high power
converters where the application is non-critical or the non-state-of-the-art is preferred for
operational advantages. The following section discusses commutation with respect to this
application.

20.2 Commutation in PAC
A three phase PAC is shown in Fig. 20.1. Nominally balanced three phase voltages VR,
VY and VB are connected to the three legs of the converter via three inductances LS, which can
be considered to represent the leakage reactance of the supply transformer. At any instant, two
devices are conducting, say SCR1 and SCR6 at the time instant indicated by the dashed line in
Fig, 20.1, bottom. At that instant, phase voltage VR is most positive and VB most negative.
Fig. 20.2 Significant voltage and current waveforms of a single phase converter
highlighting the overlap instants and the corresponding converter terminal and
output voltages
Subsequently, at the crossover point, VY becomes most negative and SCR2 is more forward
biased with respect to SCR6. The incoming SCR does not take the full load current IL, nor does
the outgoing SCR turn-off immediately. There ensues an ‘overlap’ period when three SCRs
conduct for a transient period. It is evident that with the simultaneous conduction of SCR2 and
SCR6 there is a short circuit at the converter terminals with the short circuit current ISC being
limited by the per-phase series inductances LS. Line voltage VYB drives this current. With no
delay in triggering (as if the SCRs are all replaced by diodes) the SCRs, they would be triggered
600 after the zero crossing of the corresponding line voltage. The triggering on this line voltage is
delayed by the trigger angle αfrom this 600 point.
There are a few significant effects of the commutation process when three devices
conduct. The voltage waveforms at the output and at the converter input terminals reflect the
commutation process. All-SCR (fully-controlled) converters, which are capable of operating with
trigger angles α between 00 to 1800 ideally, are restricted in the inverter mode to operate within
the ‘margin-angle’. This angle is of the order of 1600 and the output voltage is limited.

20.3 Input voltage waveform distortion
A single-phase converter, Fig 20.2 is considered to illustrate this. A four-SCR fully-controlled
converter operates into a load, which draws a constant current. The AC source includes the series
(leakage) inductance LS. Waveforms are shown for (i) no overlap case (when LS = 0) and (ii) for
a finite value of LS causing an overlap. It is evident from waveforms of ISCR 1,1’ ISCR 2,2’ that they
take a finite time to rise and fall. In the intervening period all four SCRs are ON. The current in
the incoming device rises till it equals the load current IL while that in the out going one falls to
zero. All conducting SCRs can be considered to be short circuits and consequently the output
voltage and thus also the input voltage is zero during this period. The output voltage is
diminished and a ‘notch’ appears across the input. The input distortion affects other equipment
connected to the same bus and protection must be provided against this cross-talk between two
converters through this type of line distortion. The input voltage exhibits two notches in a single-
phase converter both of which are identical and reach down to zero.
Fig. 20.3 Short circuit currents between incoming and out going
SCRs for various trigger angles
Example 20.1
A single-phase converter, Fig. 20.2 operates with an input inductance LS = 0.04 mH. Indicate the
current waveforms of the outgoing and incoming phase for trigger angles
α = 450, 900, 1600.Calculate the overlap times for each case and sketch the current waveform in
the incoming SCR pair. The input voltage is 230 V, 50 Hz and the level load current is 15 Amps.
Solution 20.1
The commutating voltage for a single phase converter is the supply voltage itself, 230 V.
When the incoming SCRs (say 2 and 2’) are triggered, the SCR pairs 1, 1’ and 2, 2’ are all
conducting. A short circuit of the supply voltage takes place via the SCRs. A short-circuiting
current, ISC flows through the SCRs, in the forward mode in 2, 2’ and reverse mode, opposing
the load current, IL in 1, 1’. Current, ISC is initially zero and rises ultimately to load current level
when SCRs 1, 1’ turn off and the overlap time is complete.

For all trigger angles, current, ISC can be separated into two components – the steady state
part and the transient part. The steady state component is for all cases the current that occurs
when the voltage is applied to a pure inductance (LS).
VS = 230∠0 0 Volts
Forα = 45 , 90 and 160 0
0 0
Steady − state component of short circuiting current is

I SS = 230∠0
0
= 73.21∠ − 90 0 Amps
2.π 50.0.01
The transient current is a level current
= − ( the magnitude of I SS at the instant of triggering )
(A current flowing in a short-circuited pure inductor does not decay – it is level)
Forα = 45 0 ,
Transient component = 73.21sin(90 0 − 45 0 ) = 51.77 Amps
Forα = 90 0 ,
Transient component = 73.21sin(90 0 − 90 0 ) = 0.00 Amps
Forα = 160 0 ,
Transient component = 73.21sin(90 0 − 160 0 ) = −68.80 Amps
In each case the transient current adds up with the steady-state component to give the net
current. Since the transients are all level currents, the steady state component can be considered
to just being shifted up or down by an amount equal to the transient component. Thus for
α = 450, the shift is by +51.77, there is no transient for α = 900, and forα = 1600 the shift is by –
68.80. Note the shape of the relevant portions of the current waveform lying between 0 to IL in
each case. The expressions for each delay angle α is:
I SC1 = 73.21sin(2.π .50 − 90) + 51.77

I SC2 = 73.21sin( 2.π .50 − 90)
I SC3 = 73.21sin( 2.π .50 − 90) − 68.80
The overlap angle is the period over which the current in each case builds up from zero to the
load current IL level. So equating each current expression to 15 Amps,
μ1 = − cos −1 (− 36.77 73.21) + cos −1 (− 51.77 73.21)
= 14.85 0
μ 2 = − cos −1 (15 73.21) + 90 0
= 11.82 0
μ 3 = − cos −1 (− 83.80 73.21) + cos −1 (68.80 73.21)
so commutation is not possible for α = 160 0
It may be noted that the overlap time decreases and comes to a minimum when the trigger
angle reaches 900, but again increases when the delay angle goes beyond 900. Two other overlap
angles are also of interest. First the overlap angle for α = 00 and when the delay angle just
permits the overlap to be over before the commutating voltage reaches 1800. The peak of ISC
occurs at this instant. This angle plus the time period required by the SCRs to complete their
turn-off process (refer: turn-off dynamics of SCR) is called the Margin Angle. Assuming zero
turn-off time,
μ m arg in − angle = − cos −1 (− 58.21 73.21) + 180 0

= 37.330
I SC 0 = 73.21sin( 2.π .50 − 90) + 73.21

0
μ 0 = cos −1 (58.21 73.21) + cos −1 (− 73.21 73.21)

0
= 37.33 0
The two angles are numerically equal as is evident from Fig. Example 20.1.
20.4 Three-phase converters

In a three phase six-pulse converter, the notches in the line voltage waveform are as shown in Fig
20.4. The triggering angle is α = 00 for the case illustrated. There are six notches per cycle.
While two of the notches reach down to zero volts, the four other have different magnitudes.
The three-phase converter, Fig. 20.1, has three inductances LS, each in series with each of
the three phases. They are the leakage inductances of the transformer, which may supply other
equipment of the plant too.
Fig. 20.4
The overlap time is dependent on the load current existing during the commutation period and
also the voltage behind the short circuit current. This commutating voltage magnitude is dictated
by the trigger angle. Thus for α = 00 this voltage is minimum. At α = 1800 too it would have
been very low if successful commutation had been possible. However, without any allowance for
an overlap time, the SCR current would just start to fall before it rises again. Note at α = 1800 the
converter operates in the ‘inverter’ mode and if the out going SCR fails to turn off it is
effectively triggered at α = 00 which pushes the converter from peak inversion to peak
rectification mode. The resulting ‘commutation failure’ can cause severe short circuits. Thus the
trigger angle must be restricted to values, which permit successful commutation of the SCRs.
20.5 Commutation in DC-DC Choppers

DC-DC Choppers have also been categorised on the basis of their commutation process. Three
types of commutation are identified: i) Voltage commutation, ii) Current commutation and iii)
Load commutation.
20.5.1 Voltage Commutation

In a voltage commutated thyristor circuit a voltage source is impressed across the SCR to
be turned off, mostly by an auxiliary SCR. This voltage is comparable in magnitude to the
operating voltages. The current in the conducting SCR is immediately quenched, however the
reverse-biasing voltage must be maintained for a period greater than that required for the device
to turn-off. With a large reverse voltage turning it off, the device offers the fastest turn-off time
obtainable from that particular device. It is an exposition of ‘hard’ turn-off where the reverse
biasing stress is maximum.
Fig. 20.5 A voltage commutated DC-DC Chopper and most significant

waveforms

Fig. 20.5 illustrates voltage commutation. ThM is the main SCR and ThAux is the
Auxiliary. As a consequence of the previous cycle, Capacitor C is charged with the dot as
positive. When the Main SCR is triggered, it carries the load current, which is held practically
level by the large filter inductance, LF and the Free-wheeling diode. Additionally, the charged
Capacitor swings half a cycle through ThM, L and D ending with a negative at the dot. The
reverse voltage may be less than its positive value as some energy is lost in the various
components in the path. The half cycle capacitor current adds to the load current and is taken by
the Main SCR.
With the negative at the dot C-ThAux is enabled to commutate ThM. When ThAux is
triggered the negative charge of the capacitor is impressed onto ThM and it immediately turns off.
The SCR does take the reverse recovery current in the process. Thereafter, the level load current
charges the capacitor linearly to the supply voltage with the dot again as positive.
The Load voltage peaks by the addition of the capacitor voltage to the supply when ThAux
is triggered. The voltage falls as the capacitor discharges both changes being linear because of
the level load current. When the Capacitor voltage returns to zero, the load voltage equals supply
voltage. The turn-off time offered by the commutation circuit to the SCR lasts till this stage
starting from the triggering of ThAux. Now the capacitor is progressively positively charged and
the load voltage is equally diminished from the supply voltage. ThAux is naturally commutated
when the capacitor is fully charged and a small excess voltage switches on the free wheeling
diode. With the positive at the dot the capacitor is again ready for the next cycle. Here ThAux
must be switched before ThM to charge C to desired polarity.
Voltage commutation may be chosen for comparatively fast switching and it can be
identified from the steep fall of the SCR current. There is no overlapping operation between the
incoming and the outgoing devices and both currents fall and rise sharply. Stresses on all the
three semiconductors can be expected to be high here.
20.5.2 Current commutation

The circuit of Fig. 20.6 can be converted into a current commuted one just by
interchanging the positions of the diode and the capacitor. Here the Capacitor is automatically
charged through D-L-LF-Load with the dot as positive. Any of the SCRs can thus be switched on
first.

If ThM is triggered first, it immediately takes the load current turning off DF. When ThAux is
triggered, it takes a half cycle of the ringing current in the L-C circuit and the polarity of the
charge across the capacitor reverses. As it swings back, ThAux is turned off and the path through
D-C-L shares the load current which may again be considered to be reasonably level. The
Current-share of THM is thus reduced in a sinusoidal (damped) manner. Turn-off process is
consequently accompanied by an overlap between ThM and the diode D in the D-C-L path. Once
the main SCR is turned off, the capacitor current becomes level and the voltage decreases
Fig. 20.7 A current commutated DC-DC Chopper and most significant waveforms
linearly. A voltage spike appears across the load when the voltage across the commutating
inductance collapses and the capacitance voltage adds to the supply voltage.
The free-wheeling diode also turns on through a overlap with D when the capacitor
voltage just exceeds the supply voltage and this extra voltage drives the commutating current
through the path D-Supply-DF-L. Thus there is soft switching of all devices during this period.
Further an additional diode may be connected across the main SCR. It ensures ‘soft’ turn-
off by conducting the excess current in the ringing L-C circuit. The low forward voltage
appearing across the SCR causes it to turn-off slowly. Consequently switching frequencies have
to be low. Note that such a diode cannot be connected across the Main SCR in the voltage-
commutated circuit.

20.5.3 Load Commutation
The circuit in Fig 20.7 is called a load-commutated chopper. Conduction paths are alternately
through the diagonal SCR pairs. Conduction patterns of these two groups are symmetrical. Each
pair of SCRs conduct with the capacitor in series. The current thus automatically is extinguished
when the capacitor achieves supply voltage level and the free-wheeling diode is turned on. Any
value of capacitor will suffice for commutation. In fact it is chosen to satisfy the load current
requirement. This commutation method permits fastest switching of the SCRs. Currents through
Fig. 20.7 A load-commutated DC-DC Chopper and most significant waveforms

the SCRs rise and fall sharply without any inductance regulating it. The free wheeling diode
current also behaves similarly and all devices are stressed by sharp di/dt. The load voltage is of
triangular shape with a peak equal to double the supply voltage (average equal to supply voltage
for the conduction interval). The capacitor has a symmetric trapezoidal voltage across itself.

20.7 Practice Problems with Answers and Questions
Q1 SCRs having turn-off times of 8 μsecs is connected in a load-commutated chopper. The
load current is 10 amperes, level. What is the minimum value of commutating capacitor
necessary for successful commutation and what is the corresponding switching frequency?
Supply voltage is 20 V DC.
A1 The capacitor charges linearly, and the forward biasing ends when the capacitor discharges
to zero. This time should be a greater than or equal to the rated turn-off time of the SCR
dv c
C = 10
dt
dt = (C / 10 ).200
= 8.10 −6 sec s
Therefore
C = 0.4μF
Each time the capacitor conducts a current it requires 2*8 μsecs to reverse charge.
Switching period is thus 4*8 = 32 μsecs. The corresponding frequency is 31 KHz. The apparent
frequency is 62 as the conduction of the SCR pairs is symmetrical.

Q2 For the current commutated circuit with a diode connected anti-parallel to the Main SCR
estimate the turn-off time permitted as a function of the commutating capacitor and
inductor. Sketch important waveforms specially the current through the Main SCR and its
ant-parallel diode.

Module
3
DC to DC Converters
Lesson
21
Introduction to Switched-
Mode Power Supply
(SMPS) Circuits
After completion of this lesson the reader will be able to:
(i) Identify the basic elements in a regulated power supply

(ii) Explain the basic principle of operation of linear and switched mode power supplies
(iii) Compare the merits and demerits of SMPS vis-à-vis linear power supplies
(iv) Interpret Power supply specifications
21.1 Introduction to regulated dc power supplies

Power supply is a broad term but this lesson is restricted to discussion of circuits that generate a
fixed or controllable magnitude dc voltage from the available form of input voltage. Integrated-
circuit (IC) chips used in the electronic circuits need standard dc voltage of fixed magnitude.
Many of these circuits need well-regulated dc supply for their proper operation. In majority of
the cases the required voltages are of magnitudes varying between -18 to +18 volts. Some
equipment may need multiple output power supplies. For example, in a Personal Computer one
may need 3.3 volt, ±5 volt and ±12 volt power supplies. The digital ICs may need 3.3volt supply
and the hard disk driver or the floppy driver may need ±5 and ±12 volts supplies. The individual
output voltages from the multiple output power supply may have different current ratings and
different voltage regulation requirements. Almost invariably these outputs are isolated dc
voltages where the dc output is ohmically isolated from the input supply. In case of multiple
output supplies ohmic isolation between two or more outputs may be desired. The input
connection to these power supplies is often taken from the standard utility power plug point (ac
voltage of 115V / 60Hz or 230V / 50Hz). It may not be unusual, though, to have a power supply
working from any other voltage level which could be of either ac or dc type.
There are two broad categories of power supplies: Linear regulated power supply and
switched mode power supply (SMPS). In some cases one may use a combination of switched
mode and linear power supplies to gain some desired advantages of both the types.
21.2 Linear regulated power supply

Fig. 21.1 shows the basic block for a linear power supply operating from an unregulated dc
input. This kind of unregulated dc voltage is most often derived from the utility ac source. The
utility ac voltage is first stepped down using a utility frequency transformer, then it is rectified
using diode rectifier and filtered by placing a capacitor across the rectifier output. The voltage
across the capacitor is still fairly unregulated and is load dependent. The ripple in the capacitor
voltage is not only dependent on the capacitance magnitude but also depends on load and supply
voltage variations. The unregulated capacitor voltage becomes the input to the linear type power
supply circuit. The filter capacitor size is chosen to optimize the overall cost and volume.
However, unless the capacitor is sufficiently large the capacitor voltage may have unacceptably
large ripple. The representative rectifier and capacitor voltage waveforms, where a 100 volts
(peak), 50 Hz ac voltage is rectified and filtered using a capacitor of 1000 micro-farad and fed to
a load of 100 ohms is shown in Fig.21.2. For proper operation of the voltage regulator, the
instantaneous value of unregulated input voltage must always be few volts more than the desired
regulated voltage at the output. Thus the ripple across the capacitor voltage (difference between
the maximum and minimum instantaneous magnitudes) must not be large or else the minimum
voltage level may fall below the required level for output voltage regulation. The magnitude of
voltage-ripple across the input capacitor increases with increase in load connected at the output.

The step down transformer talked above should be chosen such that the peak value of rectified
voltage is always larger than the sum of bare minimum voltage required at the input of the
regulator and the worst-case ripple in the capacitor voltage. Thus the transformer turns ratio is
chosen on the basis of minimum specified supply voltage magnitude. The end user of the power
supply will like to have a regulated output voltage (with voltage ripple within some specified
range) while the load and supply voltage fluctuations remain within the allowable limit. To
achieve this the unregulated dc voltage is fed to a voltage regulator circuit. The circuit in
Fig.21.1 shows, schematically, a linear regulator circuit where a transistor is placed in between
the unregulated dc voltage and the desired regulated dc output. Difference between the
instantaneous input voltage and the regulated output voltage is blocked across the collector -
emitter terminals of the transistor. As discussed previously, in such circuits the lowest
instantaneous magnitude of the unregulated dc voltage must be slightly greater than the desired
output voltage (to allow some voltage for transistor biasing circuit). The power dissipation in the
transistor and the useful output power will be in the ratio of voltage drops across the transistor
and the load (here the control power dissipated in the base drive circuit of the transistor is
assumed to be relatively small and is neglected). The worst-case series voltage drop across the
transistor may be quite large if the allowed variation in supply magnitude is large. Worst-case
power dissipation in the transistor will correspond to maximum supply voltage and maximum
load condition (load voltage is assumed to be well regulated). Efficiency of linear voltage
regulator circuits will be quite low when supply voltage is on the higher side of the nominal
voltage.
Series pass
elements
Unregulated
DC voltage
Regulated Output
Fig.21.1: Schematic linear voltage regulator

Power- electronic switch
Unregulated Duty ratio

DC source control +
Load
Output voltage
-
feedback
Fig. 21.3: A schematic switched mode dc to dc chopper circuit

Problem 1
An 18V (rms), 50 Hz supply is rectified using a full bridge diode rectifier and is followed by a
capacitor filter. The load connected across the capacitor is a simple resistor of 30 ohm. What
should be the value of filter capacitor to get only 5 volts peak to peak ripple across the load
voltage? Neglect voltage drop across conducting diode.
[Hint: The exact solution will involve use of numerical technique or trial and error method.
However with some simplifying assumptions, fairly accurate value of capacitance may be found
out. It may be assumed that in each half cycle the capacitor charges to the peak of supply voltage
(= 18*1.414 =25.456 volts). The ripple in the capacitor voltage may be neglected to calculate
load current. Thus capacitor may be assumed to discharge under the influence of 25.456/30 amp.
1 ⎧ − ⎛ 25.456 − 5 ⎞ ⎫
( I ) for a time duration (Δt) equal to ⎨π − Cos ⎜ ⎟⎬ . Next, use the equality
2π ( freq.) ⎩ ⎝ 25.456 ⎠⎭
C ΔV = I Δt and find C.
Answer: C = approx. 1350 microfarad.]

Problem 2
It is desired to get a regulated 15 volts supply from the utility ac voltage of 50 Hz using a linear
regulator circuit. The input ac voltage (rms magnitude) varies from 190 volts to 260volts. The
utility voltage is first stepped down using a transformer. The stepped down voltage is rectified
using a diode bridge and filtered by placing a capacitor after the rectified output. Assuming peak-
to-peak ripple in the capacitor voltage to be 10% of the capacitor’s crest voltage, find the turns
ratio of the step down transformer. For proper operation of the linear regulator circuit the input
voltage applied to it must always be 2 volts more than the desired output voltage (neglect diode
drops).
[Answer: Turns ratio = L.V. turns/ H.V. turns = {1.11 (15+2) } / (190* 1.414) = 1 : 14]
21.3 Switched Mode Power Supply (SMPS)

Like a linear power supply, the switched mode power supply too converts the available
unregulated ac or dc input voltage to a regulated dc output voltage. However in case of SMPS
with input supply drawn from the ac mains, the input voltage is first rectified and filtered using a
capacitor at the rectifier output. The unregulated dc voltage across the capacitor is then fed to a
high frequency dc-to-dc converter. Most of the dc-to-dc converters used in SMPS circuits have
an intermediate high frequency ac conversion stage to facilitate the use of a high frequency
transformer for voltage scaling and isolation. In contrast, in linear power supplies with input
voltage drawn from ac mains, the mains voltage is first stepped down (and isolated) to the
desired magnitude using a mains frequency transformer, followed by rectification and filtering.
The high frequency transformer used in a SMPS circuit is much smaller in size and weight
compared to the low frequency transformer of the linear power supply circuit.
The ‘Switched Mode Power Supply’ owes its name to the dc-to-dc switching converter for
conversion from unregulated dc input voltage to regulated dc output voltage. The switch
employed is turned ‘ON’ and ‘OFF’ (referred as switching) at a high frequency. During ‘ON’
mode the switch is in saturation mode with negligible voltage drop across the collector and
emitter terminals of the switch where as in ‘OFF’ mode the switch is in cut-off mode with
negligible current through the collector and emitter terminals. On the contrary the voltage-
regulating switch, in a linear regulator circuit, always remains in the active region.
Details of some popular SMPS circuits, with provisions for incorporating high frequency
transformer for voltage scaling and isolation, have been discussed in next few lessons. In this
lesson a simplified schematic switching arrangement is described that omits the transformer
action. In fact there are several other switched mode dc-to-dc converter circuits that do not use a
high frequency transformer. In such SMPS circuits the unregulated input dc voltage is fed to a
high frequency voltage chopping circuit such that when the chopping circuit (often called dc to
dc chopper) is in ON state, the unregulated voltage is applied to the output circuit that includes
the load and some filtering circuit. When the chopper is in OFF state, zero magnitude of voltage
is applied to the output side. The ON and OFF durations are suitably controlled such that the
average dc voltage applied to the output circuit equals the desired magnitude of output voltage.
The ratio of ON time to cycle time (ON + OFF time) is known as duty ratio of the chopper
circuit. A high switching frequency (of the order of 100 KHz) and a fast control over the duty
ratio results in application of the desired mean voltage along with ripple voltage of a very high
frequency to the output side, consisting of a low pass filter circuit followed by the load. The high

frequency ripple in voltage is effectively filtered using small values of filter capacitors and
inductors. A schematic chopper circuit along with the output filter is shown in Fig.21.3. Some
other switched mode power supply circuits work in a slightly different manner than the dc-to-dc
chopper circuit discussed above. Details of some of these circuits have been discussed in
following lessons.
21.4 SMPS versus linear power supply

As discussed above, in a linear regulator circuit the excess voltage from the unregulated dc input
supply drops across a series element (and hence there is power loss in proportion to this voltage
drop) whereas in switched mode circuit the unregulated portion of the voltage is removed by
modulating the switch duty ratio. The switching losses in modern switches (like: MOSFETs) are
much less compared to the loss in the linear element.
In most of the switched mode power supplies it is possible to insert a high frequency transformer
to isolate the output and to scale the output voltage magnitude. In linear power supply the
isolation and voltage-scaling transformer can be put only across the low frequency utility supply.
The low frequency transformer is very heavy and bulky in comparison to the high frequency
transformer of similar VA rating. Similarly the output voltage filtering circuit, in case of low
frequency ripples is much bulkier than if the ripple is of high frequency. The switched mode
circuit produces ripple of high frequency that can be filtered easily using smaller volume of
filtering elements.
Linear power supply though more bulky and less efficient has some advantages too when
compared with the switched mode power supply. Generally the control of the linear power
supply circuit is much simpler than that of SMPS circuit. Since there is no high frequency
switching, the switching related electro-magnetic interference (EMI) is practically absent in
linear power supplies but is of some concern in SMPS circuits. Also, as far as output voltage
regulation is concerned the linear power supplies are superior to SMPS. One can more easily
meet tighter specifications on output voltage ripples by using linear power supplies.
Problem 3
Estimate and compare the size (window area X core area) of the following two transformers: (i) a
50 VA, 50Hz, 15V low frequency transformer and (ii) a 50 VA, 100 kHz, 15V high frequency
transformer. Assume sinusoidal voltages. Assume the peak flux density in low frequency
transformer to be 1.5 tesla and in high frequency transformer to be 0.3 tesla. Take identical
values for window utilization factor and copper current density.
[Hint: VA ratng for a single phase transformer = 2.22 f BmaxAC AW δ KW , where f is supply
frequency, Bmax is the peak flux density, AC : core area, AW : window area, δ : current density in
copper and KW is the window utilization factor.]
Answer: Volume (size) of Low frequency transformer will be 400 times higher than that of high
frequency transformer.

21.5 Hybrid (SMPS followed by linear) power supply
A comparison of linear and switched mode power supplies tells about the advantages and
disadvantages of the two. Linear power supply is highly inefficient if it has to work over large
variations in input voltage, is more bulky because of the use of low frequency transformer and
filter elements (inductors and capacitors). On the other hand linear power supplies give better
output voltage regulation. It may sometimes be required to have output voltage regulation similar
to the one provided by linear supplies and compactness and better efficiency of a switched mode
supply. For this, the linear power supply may be put in tandem with a switched mode supply. Let
us consider a case where one needs an isolated and well-regulated 5 volts output while input
power is drawn from utility supply that has large voltage fluctuation. In such a situation one may
generate an isolated 7.5 volts from an SMPS and follow it by a 5 volts linear power supply set to
work with 7.5 volts input. The input to linear power supply must be few volts more than the
required output (for proper biasing of the switches) and hence SMPS tries to maintain around 7.5
volts input. It can be seen that the linear power supply now does not have large input voltage
variation in spite of large variations in the utility rms voltage. The SMPS portion of the power
supply efficiently performs the job of voltage isolation and conversion from widely varying
utility voltage to fairly regulated 7.5 volts dc. Under the given condition it may not be difficult
to see that the overall efficiency of this hybrid power supply will lie between that of a SMPS and
a linear supply. The overall cost may or may not increase even though two supplies in tandem
are used. It is to be kept in mind that to achieve the same output voltage specification by an
SMPS circuit alone, the control and filtering circuit may become more costly and complex (than
the one used in the hybrid power supply unit). Similarly if the linear supply has to be designed
for larger fluctuation in input voltage the component ratings, including heat-sink ratings, will be
higher and may cost as much as the hybrid unit.
21.6 Multiple output SMPS

A single power supply unit may need to output several different voltages. The individual output
voltages may have different ratings in terms of output current, voltage regulation and ripple
voltages. These outputs may need isolation between them. Generally a common high frequency
transformer links the input and output windings and in spite of output voltage feedback all the
outputs can not have same regulation because of different loads connected to different outputs
and hence different ohmic (resistive) drops in the output windings (loads are generally variable
and user dependent). Also the coupling between the different secondary windings and the
primary winding may not be same causing different voltage drops across the respective leakage
inductances. Barring this mismatch in the voltage drops across the resistances and leakage
inductances of the secondary windings their output voltages are in proportional to their turns
ratios. The turns ratios are properly chosen to give fairly regulated individual output voltages
(even if only one output voltage feedback is used for SMPS switch control). The output that
needs to have tighter voltage regulation may be used for output voltage feedback. In case another
output needs to have similarly tight regulation then that particular output may be passed through
an additional linear regulator circuit as in the case of hybrid power supply circuit discussed in the
previous section (Sec. 21.5).

21.7 Resonant Mode Power Supplies
Resonant mode power supplies are a variation over SMPS circuits where the switching losses are
significantly reduced by adapting zero-voltage or zero-current switching techniques. In non-
resonant mode SMPS circuits the switches are subjected to hard switching (during hard-
switching, both the voltage and current in the switch are of considerable magnitude resulting in
large instantaneous switching power loss). Efficiency of resonant mode power supplies is
generally higher than non-resonant mode supplies.
21.8 Power supply specifications

Power supplies may have several specifications to be met, including their voltage and current
ratings. There may be short time ratings of higher magnitudes of current and continuous ratings
of somewhat lower magnitudes. One needs to specify the tolerable limits on the ripple voltages,
short-circuit protection level of current (if any) and the nature of output volt-current curve during
over-current or short circuit (the output voltage magnitude should reduce or fold back towards
zero, gradually, depending on the severity of over-current). The fuse requirement (if any) on the
input and the output side may need to be specified. One needs to specify the type of input supply
(whether ac or dc) or whether the power supply can work both from ac or dc input voltages.
Acceptable range of variation in input voltage magnitude, supply frequency (in case of ac input)
are also to be specified. Efficiency, weight and volume are some other important specifications.
Some applications require the electro-magnetic compatibility standards to be met. By
electromagnetic compatibility it is meant that the level of EMI generation by power supply
should be within tolerable limits and at the same time the power supply should have the ability to
work satisfactorily in a limited noisy environment. It is quite common to have output voltage
isolation and it is specified in terms of isolation breakdown voltage. In case of multiple power
supplies it needs to be specified whether all the outputs need to be isolated or not and what
should be the acceptable ripple voltage range for each.
In majority of the cases the available source of input power is the alternating type utility voltage
of 50 or 60 Hz. The voltage levels commonly used are 115V (common in countries like, USA)
and 230 volts (common in India and many of the European countries). Most utility (mains)
power supplies are expected to have ± 10% voltage regulation but for additional precaution the
SMPS circuits must work even if input voltages have ± 20% variation. Now-a-days universal
power supplies that work satisfactorily and efficiently both on 115 V and 230 V input are quite
popular. These power supplies are very convenient for international travelers who can simply
plug-on their equipments, like laptop computer and shaving machine, without having to pay
much attention on the exact voltage and frequency levels of the utility supply. In contrast some
of the other power supplies have a selector switch and the user is required to adjust the switch
position to match the utility voltage. In case user forgets to keep the selector switch at correct
position, the equipment attached may get damaged.
21.9 Some common types of SMPS circuits

There are several different topologies for the switched mode power supply circuits. Some
popular ones are: fly-back, forward, push-pull, C’uk, Sepic, half bridge and H-bridge circuits.
Some of these configurations will be discussed in the coming lessons. A particular topology may
be more suitable than others on the basis of one or more performance criterions like cost,

efficiency, overall weight and size, output power, output regulation, voltage ripple etc. All the
topologies listed above are capable of providing isolated voltages by incorporating a high
frequency transformer in the circuit. There are many commercially available power supply
controller ICs that can readily be used to control the duty ratio of the SMPS switches so that the
final output is well regulated. Most of these ICs are capable of driving MOSFET type of
switches. They also provide features like under voltage lock-out, output over-current protection
etc.
Problem 4
Which among the following power supplies will be most energy-efficient if operated under wide
input voltage variation and at full load:
(i) Linear power supply
(ii) Switched mode power supply
(iii) Switched mode followed by linear power supply
(iv) Linear followed by switched mode power supply
Answer: (ii)
More Quiz problems on Chapter-21

(1) A regulated power supply should be able to maintain output voltage within specified limits
in spite of
(a) Unlimited variation in supply voltage
(b) Unlimited variation in load at the output
(c) Both (a) and (b)
(d) Only for load and supply parameter- variations in the specified range
(2) Linear isolated power supplies will generally be superior to switched-mode power supplies
(outputting isolated voltage) in respect to the following
(a) Higher efficiency in the entire range of load and supply variations
(b) Better dynamic regulation of output voltage against supply variations
(c) Less volume and weight for identical input and output ratings
(d) All the above
(3) High frequency transformers are used for output voltage isolation and scaling in the
following type of power supplies:-
(a) Switched mode power supplies
(b) Linear power supplies
(c) Hybrid power supplies
(d) Both (a) and (c)
(4) A 60watt, 15V ± 0.2V, power supply specified to deliver regulated output for input supply
(50Hz) variation from 180 volts to 270 volts will be different from another power supply
with identical output rating but capable of outputting regulated voltage over input range of
90 volts to 270 volts in respect of:-
(a) Less cost
(b) More bulky and more costly
(c) Higher current rating of power-switch
(d) None of the above
Answers: (1-d), (2-b), (3-d), (4-a)
Module
3
DC to DC Converters
Lesson
22
Fly-Back Type Switched
Mode Power Supply
(i) Identify the topology of a fly-back type switched mode power supply circuit.
(ii) Explain the principle of operation of fly-back SMPS circuit.
(iii) Calculate the ratings of devices and components used in fly-back converter for the
specified input and output voltages and for the required output power.
(iv) Design a simple fly-back converter circuit.
22.1 Introduction
Fly-back converter is the most commonly used SMPS circuit for low output power applications
where the output voltage needs to be isolated from the input main supply. The output power of
fly-back type SMPS circuits may vary from few watts to less than 100 watts. The overall circuit
topology of this converter is considerably simpler than other SMPS circuits. Input to the circuit
is generally unregulated dc voltage obtained by rectifying the utility ac voltage followed by a
simple capacitor filter. The circuit can offer single or multiple isolated output voltages and can
operate over wide range of input voltage variation. In respect of energy-efficiency, fly-back
power supplies are inferior to many other SMPS circuits but its simple topology and low cost
makes it popular in low output power range.
The commonly used fly-back converter requires a single controllable switch like,
MOSFET and the usual switching frequency is in the range of 100 kHz. A two-
switch topology exists that offers better energy efficiency and less voltage stress
across the switches but costs more and the circuit complexity also increases
slightly. The present lesson is limited to the study of fly-back circuit of single
switch topology.
22.2 Basic Topology of Fly-Back Converter

Fig.22.1 shows the basic topology of a fly-back circuit. Input to the circuit may be unregulated
dc voltage derived from the utility ac supply after rectification and some filtering. The ripple in
dc voltage waveform is generally of low frequency and the overall ripple voltage waveform
repeats at twice the ac mains frequency. Since the SMPS circuit is operated at much higher
frequency (in the range of 100 kHz) the input voltage, in spite of being unregulated, may be
considered to have a constant magnitude during any high frequency cycle. A fast switching
device (‘S’), like a MOSFET, is used with fast dynamic control over switch duty ratio (ratio of
ON time to switching time-period) to maintain the desired output voltage. The transformer, in
Fig.22.1, is used for voltage isolation as well as for better matching between input and output
voltage and current requirements. Primary and secondary windings of the transformer are wound
to have good coupling so that they are linked by nearly same magnetic flux. As will be shown in
the next section the primary and secondary windings of the fly-back transformer don’t carry
current simultaneously and in this sense fly-back transformer works differently from a
normal transformer. In a normal transformer, under load, primary and secondary windings
conduct simultaneously such that the ampere turns of primary winding is nearly balanced by the
opposing ampere-turns of the secondary winding (the small difference in ampere-turns is
required to establish flux in the non-ideal core). Since primary and

N1:N2 D
Edc
C Load
Primary Side VO
Switch S
Gate pulses
Fig. 22.1 Fly Back Converter
secondary windings of the fly-back transformer don’t conduct simultaneously they are more like
two magnetically coupled inductors and it may be more appropriate to call the fly-back
transformer as inductor-transformer. Accordingly the magnetic circuit design of a fly-back
transformer is done like that for an inductor. The details of the inductor-transformer design are
dealt with separately in some later lesson. The output section of the fly-back transformer, which
consists of voltage rectification and filtering, is considerably simpler than in most other switched
mode power supply circuits. As can be seen from the circuit (Fig.22.1), the secondary winding
voltage is rectified and filtered using just a diode and a capacitor. Voltage across this filter
capacitor is the SMPS output voltage.
It may be noted here that the circuit shown in Fig.22.1 is rather schematic in nature. A more
practical circuit will have provisions for output voltage and current feedback and a controller for
modulating the duty ratio of the switch. It is quite common to have multiple secondary windings
for generating multiple isolated voltages. One of the secondary outputs may be dedicated for
estimating the load voltage as well as for supplying the control power to the circuit. Further, as
will be discussed later, a snubber circuit will be required to dissipate the energy stored in the
leakage inductance of the primary winding when switch ‘S’ is turned off.
Under this lesson, for ease of understanding, some simplifying assumptions are made. The
magnetic circuit is assumed to be linear and coupling between primary and secondary windings
is assumed to be ideal. Thus the circuit operation is explained without consideration of winding
leakage inductances. ON state voltage drops of switches and diodes are neglected. The windings,
the transformer core, capacitors etc. are assumed loss-less. The input dc supply is also assumed
to be ripple-free.
[A brief idea of a more practical fly-back converter will be given towards the end of this
lesson.]

22.3 Principle of Operation
During its operation fly-back converter assumes different circuit-configurations. Each of these
circuit configurations have been referred here as modes of circuit operation. The complete
operation of the power supply circuit is explained with the help of functionally equivalent
circuits in these different modes.
As may be seen from the circuit diagram of Fig.22.1, when switch ‘S’ is on, the primary winding
of the transformer gets connected to the input supply with its dotted end connected to the positive
side. At this time the diode ‘D’ connected in series with the secondary winding gets reverse
biased due to the induced voltage in the secondary (dotted end potential being higher). Thus with
the turning on of switch ‘S’, primary winding is able to carry current but current in the secondary
winding is blocked due to the reverse biased diode. The flux established in the transformer core
and linking the windings is entirely due to the primary winding current. This mode of circuit has
been described here as Mode-1 of circuit operation. Fig. 22.2(a) shows (in bold line) the current
carrying part of the circuit and Fig. 22.2(b) shows the circuit that is functionally equivalent to the
fly-back circuit during mode-1. In the equivalent circuit shown, the conducting switch or diode is
taken as a shorted switch and the device that is not conducting is taken as an open switch. This
representation of switch is in line with our assumption where the switches and diodes are
assumed to have ideal nature, having zero voltage drop during conduction and zero leakage
current during off state.
Vpri = Edc , Vsec = Edc*N2/N1

+
Edc VO + Vpri Vsec VO
Edc
N1 : N2
Fig.22.2(a): Current path during Mode-1 of

circuit operation Fig.22.2(b): Equivalent circuit in Mode-1
Under Mode-1, the input supply voltage appears across the primary winding inductance and the
primary current rises linearly. The following mathematical relation gives an expression for
current rise through the primary winding:
d
EDC = LPr i × iPr i ------------------------------------------------------------(22.1),
dt
where EDC is the input dc voltage, LPr i is inductance of the primary winding and iPri is
the instantaneous current through primary winding.
Linear rise of primary winding current during mode-1 is shown in Fig.22.5(a) and Fig.22.5(b).
As described later, the fly-back circuit may have continuous flux operation or discontinuous flux
operation. The waveforms in Fig.22.5(a) and Fig.22.5(b) correspond to circuit operations in
continuous and discontinuous flux respectively. In case the circuit works in continuous flux
mode, the magnetic flux in the transformer core is not reset to zero before the next cyclic turning
ON of switch ‘S’. Since some flux is already present before ‘S’ is turned on, the primary winding
current in Fig. 22.3(a) abruptly rises to a finite value as the switch is turned on. Magnitude of the
current-step corresponds to the primary winding current required to maintain the previous flux in
the core.
At the end of switch-conduction (i.e., end of Mode-1), the energy stored in the magnetic field of
the fly back inductor-transformer is equal to LPr i I P2 2 , where I P denotes the magnitude of
primary current at the end of conduction period. Even though the secondary winding does not
conduct during this mode, the load connected to the output capacitor gets uninterrupted current
due to the previously stored charge on the capacitor. During mode-1, assuming a large capacitor,
the secondary winding voltage remains almost constant and equals to VSec = EDC × N 2 / N1 .
During mode-1, dotted end of secondary winding remains at higher potential than the other end.
Under this condition, voltage stress across the diode connected to secondary winding (which is
now reverse biased) is the sum of the induced voltage in secondary and the output voltage
( Vdiode = VO + EDC × N 2 / N1 ).
Mode-2 of circuit operation starts when switch ‘S’ is turned off after conducting for some time.
The primary winding current path is broken and according to laws of magnetic induction, the
voltage polarities across the windings reverse. Reversal of voltage polarities makes the diode in
the secondary circuit forward biased. Fig. 22.3(a) shows the current path (in bold line) during
mode-2 of circuit operation while Fig. 22.3(b) shows the functional equivalent of the circuit
during this mode.
Vpri = VO*N1/N2 , Vsec= VO

+ VO
Edc +
Edc Vpri Vsec VO
N1: N2
Fig:22.3(a) : Current path during Mode-2 of

circuit operation Fig.22.3(b): Equivalent circuit in Mode-2
In mode-2, though primary winding current is interrupted due to turning off of the switch ‘S’, the
secondary winding immediately starts conducting such that the net mmf produced by the
windings do not change abruptly. (mmf is magneto motive force that is responsible for flux
production in the core. Mmf, in this case, is the algebraic sum of the ampere-turns of the
two windings. Current entering the dotted ends of the windings may be assumed to
produce positive mmf and accordingly current entering the opposite end will produce
negative mmf.) Continuity of mmf, in magnitude and direction, is automatically ensured as
sudden change in mmf is not supported by a practical circuit for reasons briefly given below.
[mmf is proportional to the flux produced and flux, in turn, decides the energy stored in
the magnetic field (energy per unit volume being equal to B 2 2μ , B being flux per unit
area and μ is the permeability of the medium). Sudden change in flux will mean sudden

change in the magnetic field energy and this in turn will mean infinite magnitude of
instantaneous power, some thing that a practical system cannot support.]
For the idealized circuit considered here, the secondary winding current abruptly rises from zero
to I P N1 N 2 as soon as the switch ‘S’ turns off. N 1 and N 2 denote the number of turns in the
primary and secondary windings respectively. The sudden rise of secondary winding current is
shown in Fig. 22.5(a) and Fig. 22.5(b). The diode connected in the secondary circuit, as shown in
Fig.22.1, allows only the current that enters through the dotted end. It can be seen that the
magnitude and current direction in the secondary winding is such that the mmf produced by the
two windings does not have any abrupt change. The secondary winding current charges the
output capacitor. The + marked end of the capacitor will have positive voltage. The output
capacitor is usually sufficiently large such that its voltage doesn’t change appreciably in a single
switching cycle but over a period of several cycles the capacitor voltage builds up to its steady
state value.
The steady-state magnitude of output capacitor voltage depends on various factors, like,
input dc supply, fly-back transformer parameters, switching frequency, switch duty ratio
and the load at the output. Capacitor voltage magnitude will stabilize if during each switching
cycle, the energy output by the secondary winding equals the energy delivered to the load.
As can be seen from the steady state waveforms of Figs.22.5(a) and 22.5(b), the secondary
winding current decays linearly as it flows against the constant output voltage (VO). The linear
d
decay of the secondary current can be expressed as follows: LSec × iSec = −VO ---------- (22.2),
dt
Where, LSec and iSec are secondary winding inductance and current respectively.
VO is the stabilized magnitude of output voltage.
Under steady-state and under the assumption of zero on-state voltage drop across diode, the
secondary winding voltage during this mode equals VO and the primary winding voltage =
VON1/N2 (dotted ends of both windings being at lower potential). Under this condition, voltage
stress across switch ‘S’ is the sum total of the induced emf in the primary winding and the dc
supply voltage (Vswitch = EDC + VON1/N2).
The secondary winding, while charging the output capacitor (and feeding the load), starts
transferring energy from the magnetic field of the fly back transformer to the power supply
output in electrical form. If the off period of the switch is kept large, the secondary current gets
sufficient time to decay to zero and magnetic field energy is completely transferred to the output
capacitor and load. Flux linked by the windings remain zero until the next turn-on of the switch,
and the circuit is under discontinuous flux mode of operation. Alternately, if the off period of the
switch is small, the next turn on takes place before the secondary current decays to zero. The
circuit is then under continuous flux mode of operation.
During discontinuous mode, after complete transfer of the magnetic field energy to the output,
the secondary winding emf as well as current fall to zero and the diode in series with the winding
stops conducting. The output capacitor however continues to supply uninterrupted voltage to the
load. This part of the circuit operation has been referred to as Mode-3 of the circuit operation.

Mode-3 ends with turn ON of switch ‘S’ and then the circuit again goes to Mode-1 and the
sequence repeats.
+ +
Edc VO
Edc VO
Fig:22.4 (a) : Current flow path during Mode-

3 of circuit operation Fig.22.4(b): Equivalent circuit in Mode-3
Figs.22.4(a) and 22.4(b) respectively show the current path and the equivalent circuit during
mode-3 of circuit operation. Figs.22.5(a) and 22.5(b) show, the voltage and current waveforms of
the winding over a complete cycle. It may be noted here that even though the two windings of
the fly-back transformer don’t conduct simultaneously they are still coupled magnetically
(linking the same flux) and hence the induced voltages across the windings are proportional to
their number of turns.

IP
Io
I pri
0 tON T
IP X N1 / N2 Time
Io X N1 / N2
I sec
0 tON T Time
EDC
V pri VO X N1 / N2
0 tON T Time
MODE-1 MODE-1
MODE-2
V load VO
Time
Fig.22.5(a): Fly-back circuit waveforms under continuous magnetic flux

22.4 Circuit Equations Under Continuous-Flux Operation
The waveforms in Fig.22.5(a) correspond to steady state operation under continuous magnetic
flux. ‘tON’ denotes the time for which the fly-back switch is ON during each switching cycle. ‘T’
stands for the time period of the switching cycle. The ratio ( tON /T) is known as the duty cycle
(δ) of the switch. As can be seen from Fig.22.5(a), the primary winding current rises from I0 to IP
in ‘δT’ time. In terms of input supply voltage (Edc) and the primary winding inductance ( LPr i )
the following relation holds:
(IP - I0) = (Edc / LPr i ) δT ------------------------------------------(22.3),
Under steady state the energy input to primary winding during each ON duration equals: 0.5Edc
(IP + I0) δT and similarly the output energy in each cycle equals V0 ILoad T, where V0 is the
output voltage magnitude and ILoad denotes the load current. Equating energy input and energy
output of the converter (the converter was assumed loss-less) in each supply cycle, one gets:
0.5Edc (IP + I0) δ = V0 ILoad ------------------------------------------(22.4),
The mean (dc) voltage across both primary and secondary windings must be zero under every
steady state. When the switch is ON, the primary winding voltage equals input supply voltage
and when the switch is OFF the reflected secondary voltage appears across the primary winding.
Under the assumption of ideal switch and diode,
Edc δ = (N1 / N2) V0 (1-δ) ------------------------------------------(22.5),
where N1 and N2 are the number of turns in primary and secondary windings and (N1/N2)V0 is
the reflected secondary voltage across the primary winding (dotted end of the windings at lower
potential) during mode-2 of circuit operation.
One needs to know the required ratings for the switch and the diode used in the converter. When
the switch is OFF, it has to block a voltage (Vswitch) that equals to the sum of input voltage and
the reflected secondary voltage during mode-2.
Thus, Vswitch = Edc + (N1 / N2) V0 -----------------------------------(22.6),
When the switch in ON, the diode has to block a voltage (Vdiode) that equals to the sum of output
voltage and reflected primary voltage during mode-1, i.e.,
Vdiode = V0 + Edc (N2 / N1) -----------------------------------(22.6a)
Since the intended switching frequency for SMPS circuits is generally in the range of 100kHz,
the switch and the diode used in the fly-back circuit must be capable of operating at high
frequency. The switch and the transformer primary winding must be rated to carry a repetitive
peak current equal to IP (related to maximum output power as given by Eqns. 22.3 to 22.5).
Similarly the secondary winding and the diode put in the secondary circuit must be rated to carry
a repetitive peak current equal to the maximum expected load current. The magnetic core of the
high frequency inductor-transformer must be chosen properly such that the core does not saturate
even when the primary winding carries the maximum expected current. Also, the transformer

core (made of ferrite material) must have low hysteresis loss even at high frequency operation.
Since the ferrite cores have very low conductivity, the eddy current related loss in the core is
generally insignificant.
22.5 Circuit Equations Under Discontinuous-Flux Mode

Fig. 22.5(b) shows some of the important voltage and current waveforms of the fly-back circuit
when it is operating in the discontinuous flux mode. During mode-3 of the circuit operation,
primary and secondary winding currents as well as voltages are zero. The load, however,
continues to get a reasonably steady voltage due to the relatively large output filter capacitor.
IP
I pri
0 tON T
Time
IP X N1 / N2
I sec
0 tON T Time
EDC
V pri VO X N1 / N2
0
tON T Time
MODE-1
MODE-2 MODE-3
MODE-1
V load 0 VO
Time
Fig.22.5(b): Fly-back circuit waveforms under discontinuous flux
With the turning ON of the switch, the primary winding current starts building up linearly from
zero and at the end of mode-1 the magnetic field energy due to primary winding current rises to
1
L pri I P2 . This entire energy is transferred to the output at the end of mode-2 of circuit operation.
2
Under the assumption of loss-less operation the output power (Po) can be expressed as:
1
Po = L pri I P2 fswitch -----------------------------------(22.7),
2

where fswitch (=1/T) is the switching frequency of the converter.
It may be noted that output power Po is same as ‘V0 ILoad’ used in Eqn.(22.4). The volt-time area
equation as given in Eqn.(22.5) gets modified under discontinuous flux mode of operation as
follows:
Edc δ ≤ (N1 / N2) V0 (1-δ) ------------------------------------------(22.8)
Average voltage across windings over a switching cycle is still zero. The inequality sign of
Eqn.22.8 is due to the fact that during part of the OFF period of the switch [= (1-δ)T], the
winding voltages are zero. This zero voltage duration had been identified earlier as mode-3 of the
circuit operation. The equality sign in Eqn.(22.8) will correspond to just-continuous case, which
is the boundary between continuous and discontinuous mode of operation. The expression for
Vswitch and Vdiode, as given in Eqns.(22.6) and (22.6a), will hold good in discontinuous mode also.
22.6 Continuous Versus Discontinuous Flux Mode of Operation

A practical fly-back type SMPS circuit will have a closed loop control circuit for output voltage
regulation. The controller modulates the duty ratio of the switch to maintain the output voltage
within a small tolerable ripple voltage band around the desired output value. If the load is very
light, very small amount of energy needs to be input to the circuit in each switching cycle. This is
achieved by keeping the ON duration of the switch low, resulting in low duty ratio (δ). Within
this small ON time only a small amount of current builds up in the primary winding. The off
duration of the switch, which is (1-δ) fraction of the switching time period, is relatively large.
Mode-2 duration of the circuit operation is also small as the magnetic field energy is quickly
discharged into the output capacitor. Thus, at light load, the circuit is in mode-3 for significant
duration. As the load increases the mode-3 duration, during which there is zero winding currents
and zero flux through the core, reduces and the circuit is driven towards continuous flux mode.
The circuit operation changes from discontinuous to continuous flux mode if the output power
from the circuit increases beyond certain value. Similarly if the applied input voltage decreases,
keeping the load power and switching frequency constant, the circuit tends to go in continuous
flux mode of operation.
For better control over output voltage, discontinuous flux mode of operation is preferred.
However, for the given transformer and switch ratings etc., more output power can be transferred
during continuous flux mode. A common design thumb rule is to design the circuit for operation
at just-continuous flux mode at the minimum expected input voltage and at the maximum (rated)
output power.
22.7 A Practical Fly-Back Converter

The fly-back converter discussed in the previous sections neglects some of the practical aspects
of the circuit. The simplified and idealized circuit considered above essentially conveys the basic
idea behind the converter. However a practical converter will have device voltage drops and
losses, the transformer shown will also have some losses. The coupling between the primary and
secondary windings will not be ideal. The loss part of the circuit is to be kept in mind while
designing for rated power. The designed input power (Pin) should be equal to Po/η, where Po is
the required output power and η is the efficiency of the circuit. A typical figure for η may be

taken close to 0.6 for first design iteration. Similarly one needs to counter the effects of the non-
ideal coupling between the windings. Due to the non-ideal coupling between the primary and
secondary windings when the primary side switch is turned-off some energy is trapped in the
leakage inductance of the winding. The flux associated with the primary winding leakage
inductance will not link the secondary winding and hence the energy associated with the leakage
flux needs to be dissipated in an external circuit (known as snubber). Unless this energy finds a
path, there will be a large voltage spike across the windings which may destroy the circuit.
Fig.22.6 shows a practical fly-back converter. The snubber circuit consists of a fast recovery
diode in series with a parallel combination of a snubber capacitor and a resistor. The leakage-
inductance current of the primary winding finds a low impedance path through the snubber diode
to the snubber capacitor. It can be seen that the diode end of the snubber capacitor will be at
higher potential. To check the excessive voltage build up across the snubber capacitor a resistor
is put across it. Under steady state this resistor is meant to dissipate the leakage flux energy. The
power lost in the snubber circuit reduces the overall efficiency of the fly-back type SMPS circuit.
A typical figure for efficiency of a fly-back circuit is around 65% to 75%. In order that snubber
capacitor does not take away any portion of energy stored in the mutual flux of the windings, the
minimum steady state snubber capacitor voltage should be greater than the reflected secondary
voltage on the primary side. This can be achieved by proper choice of the snubber-resistor and
by keeping the RC time constant of the snubber circuit significantly higher than the switching
time period. Since the snubber capacitor voltage is kept higher than the reflected secondary
voltage, the worst-case switch voltage stress will be the sum of input voltage and the peak
magnitude of the snubber capacitor voltage.
S
N N1:N2 D
RS U
Edc B
B C Load V (o/p)
E
R
N3
PWM
Control
Block
Current Feedback
Fig. 22.6 A Practical Fly Back Converter
The circuit in Fig.22.6 also shows, in block diagram, a Pulse Width Modulation (PWM) control
circuit to control the duty ratio of the switch. In practical fly-back circuits, for closed loop output
voltage regulation, one needs to feed output voltage magnitude to the PWM controller. In order
to maintain ohmic isolation between the output voltage and the input switching circuit the output
voltage signal needs to be isolated before feeding back. A popular way of feeding the isolated
voltage information is to use a tertiary winding. The tertiary winding voltage is rectified in a way
similar to the rectification done for the secondary winding. The rectified tertiary voltage will be
nearly proportional to the secondary voltage multiplied by the turns-ratio between the windings.
The rectified tertiary winding voltage also doubles up as control power supply for the PWM
controller. For initial powering up of the circuit the control power is drawn directly from the
input supply through a resistor (shown as RS in Fig.22.6) connected between the input supply
and the capacitor of the tertiary circuit rectifier. The resistor ‘RS’ is of high magnitude and causes
only small continuous power loss.
In case, multiple isolated output voltages are required, the fly-back transformer will need to have
multiple secondary windings. Each of these secondary winding voltages are rectified and filtered
separately. Each rectifier and filter circuit uses the simple diode and capacitor as shown earlier
for a single secondary winding. In the practical circuit shown above, where a tertiary winding is
used for voltage feedback, it may not be possible to compensate exactly for the secondary
winding resistance drop as the tertiary winding is unaware of the actual load supplied by the
secondary winding. However for most applications the small voltage drop in the winding
resistance may be tolerable. Else, one needs to improve the voltage regulation by adding a linear
regulator stage in tandem (as mentioned in Chapter-21) or by giving a direct output voltage
feedback to the control circuit.
Quiz Problems
(i) What kind of output rectifier and filter circuit is used in a fly back converter?
(a) a four-diode bridge rectifier followed by a capacitor
(b) a single diode followed by an inductor-capacitor filter
(c) a single diode followed by a capacitor
(d) will require a center-tapped secondary winding followed by a full wave rectifier and
a output filter capacitor.
(ii) A fly-back converter operates in discontinuous conduction mode with fixed ON duration of
the switch in each switching cycle. Assuming input voltage and the resistive load at the
output to remain constant, how will the output voltage change with change in switching
frequency? (Assume discontinuous conduction through out and neglect circuit losses.)
(a) Output voltage varies directly with switching frequency.

(b) Output voltage varies inversely with switching frequency.
(c) Output voltage varies directly with square root of switching frequency.
(d) Output voltage is independent of switching frequency.
(iii) A fly-back converter has primary to secondary turns ratio of 15:1. The input voltage is
constant at 200 volts and the output voltage is maintained at 18 volts. What should be the
snubber capacitor voltage under steady state?
(a) More than 270 volts.

(b) More than 200 volts but less than 270 volts.
(c) Less than 18 volts.
(d) Not related to input or output voltage.

(iv) A fly-back converter is to be designed to operate in just-continuous conduction mode when
the input dc is at its minimum expected voltage of 200 volts and when the load draws
maximum power. The load voltage is regulated at 16 volts. What should be the primary to
secondary turns ratio of the transformer if the switch duty ratio is limited to 80%. Neglect
ON-state voltage drop across switch and diodes.
(a) 20 :1
(b) 30 :1
(c) 25 :2
(d) 50 :1
Answers to quiz problems: (i-c), (ii-c), (iii-a), (iv-d).

Module
3
DC to DC Converters
Lesson
23
Forward Type Switched
Mode Power Supply
(i) Identify the topology of a forward type switched mode power supply circuit.
(ii) Explain the principle of operation of a forward dc-to-dc power supply.
(iii) Calculate the ratings of devices, components, transformer turns ratio for the given
input and output voltages and the required output power.
(iv) Design a simple forward type switched mode power supply circuit.
23.1 Introduction
Forward converter is another popular switched mode power supply (SMPS) circuit that is used
for producing isolated and controlled dc voltage from the unregulated dc input supply. As in
the case of fly-back converter (lesson-22) the input dc supply is often derived after rectifying
(and little filtering) of the utility ac voltage. The forward converter, when compared with the
fly-back circuit, is generally more energy efficient and is used for applications requiring little
higher power output (in the range of 100 watts to 200 watts). However the circuit topology,
especially the output filtering circuit is not as simple as in the fly-back converter.
Fig. 23.1 shows the basic topology of the forward converter. It consists of a fast switching
device ‘S’ along with its control circuitry, a transformer with its primary winding connected in
series with switch ‘S’ to the input supply and a rectification and filtering circuit for the
transformer secondary winding. The load is connected across the rectified output of the
transformer-secondary.
NP : NS
L
D1
Edc V (o/p)
Load
D2 C
Control Switch S
Circuit
Fig. 23.1: Basic Topology of a Forward Converter

The transformer used in the forward converter is desired to be an ideal transformer with no
leakage fluxes, zero magnetizing current and no losses. The basic operation of the circuit is
explained here assuming ideal circuit elements and later the non-ideal characteristics of the
devices are taken care of by suitable modification in the circuit design. In fact, due to the
presence of finite magnetizing current in a practical transformer, a tertiary winding
needs to be introduced in the transformer and the circuit topology changes slightly. A

more practical type forward converter circuit is discussed in later sections.
23.2 Principle of Operation

The circuit of Fig. 23.1 is basically a dc-to-dc buck converter with the addition of a transformer
for output voltage isolation and scaling. When switch ‘S’ is turned on, input dc gets applied to the
primary winding and simultaneously a scaled voltage appears across the transformer secondary.
Dotted sides of both the windings are now having positive polarity. Diode ‘D1’, connected in
series with the secondary winding gets forward biased and the scaled input voltage is applied to
the low pass filter circuit preceding the load. The primary winding current enters through its
dotted end while the secondary current comes out of the dotted side and their magnitudes are
inversely proportional to their turns-ratio. Thus, as per the assumption of an ideal transformer, the
net magnetizing ampere-turns of the transformer is zero and there is no energy stored in the
transformer core. When switch ‘S’ is turned off, the primary as well as the secondary winding
currents are suddenly brought down to zero. Current through the filter inductor and the load
continues without any abrupt change. Diode ‘D2’ provides the freewheeling path for this current.
The required emf to maintain continuity in filter-inductor current and to maintain the forward bias
voltage across D2 comes from the filter inductor ‘L’ itself. During freewheeling the filter inductor
current will be decaying as it flows against the output voltage (Vop), but the presence of relatively
large filter capacitor ‘C’ still maintains the output voltage nearly constant. The ripple in the output
voltage must be within the acceptable limits. The supply switching frequency is generally kept
sufficiently high such that the next turn-on of the switch takes place before the filter inductor
current decays significantly. Needless to say, that the magnitudes of filter inductor and capacitor
are to be chosen appropriately.
The idea behind keeping filter inductor current nearly constant is to relieve the output capacitor
from supplying large ripple current. [As per the circuit topology of Fig.23.1, the inductor and
the capacitor together share the load-current drawn from the output. Under steady state
condition, mean dc current supplied by the capacitor is zero but capacitor still supplies
ripple current. For maintaining constant load current, the inductor and capacitor current-
ripples must be equal in magnitude but opposite in sense. Capacitors with higher ripple
current rating are required to have much less equivalent series resistor (ESR) and
equivalent series inductor (ESL) and as such they are bulkier and costlier. Also, the ESR
and ESL of a practical capacitor causes ripple in its dc output voltage due to flow of ripple
current through these series impedances. Since the output voltage is drawn from capacitor
terminal the ripple in output voltage will be less if the capacitor is made to carry less ripple
current.]
For better understanding of the steady-state behavior of the converter, the circuit’s operation is
divided in two different modes, mode-1 and mode-2. Mode-1 corresponds to the ‘on’ duration of
the switch and mode-2 corresponds to its ‘off’ duration.
The following simplifying assumptions are made before proceeding to the detailed mode-
wise analysis of the circuit:
• ON state voltage drops of switches and diodes are neglected. Similarly, leakage currents
through the off state devices is assumed zero. The switching-on and switching-off times
of the switch and diodes are neglected.

• The transformer used in the circuit is assumed to be ideal requiring no magnetizing
current, having no leakage inductance and no losses.
• The filter circuit elements like, inductors and capacitors are assumed loss-less.
• For the simplified steady-state analysis of the circuit the switch duty ratio (δ), as defined
in the previous chapters is assumed constant.
• The input and output dc voltages are assumed to be constant and ripple-free. Current
through the filter inductor (L) is assumed to be continuous.
Mode-1 of Circuit Operation

Mode-1 of circuit starts after switch ‘S’ (as shown in Fig.23.1) is turned ON. This connects the
input voltage, Edc, to the primary winding. Both primary and secondary windings start
conducting simultaneously with the turning on of the switch. The primary and secondary
winding currents and voltages are related to their turns-ratio (NP / NS), as in an ideal transformer.
Fig.23.2 (a) shows, in bold lines, the current carrying path of the circuit and Fig.23.2 (b) shows
the functional equivalent circuit of mode-1. As switch ‘S’ closes, diode D1 in the secondary circuit
gets forward biased and the input voltage, scaled by the transformer turns ratio, gets applied to the
secondary circuit. Diode D2 does not conduct during mode-1, as it remains reverse biased.
NP: NS
D1 L
Edc L
C Load P
D2 NS
Edc C Load
NP VO
Switch ‘S’ N
S and D1 ON,
D2 Off.
Fig.23.2(b): Equivalent circuit in
Fig. 23.2(a): Current path during Mode-1 Mode-1
As can be seen, the output circuit consisting of L-C filter and the load gets a voltage equal
N
to S Edc during mode-1. This voltage is shown across points ‘P’ and ‘N’ in Fig. 23.2(b) and it is
NP
the maximum achievable dc voltage across the load, corresponding to δ = 1. Mode-1 can be called
as powering mode during which input power is transferred to the load. Mode-2, to be called as
freewheeling mode, starts with turning off of the switch ‘S’.
Mode-2 of Circuit Operation

As soon as switch ‘S’ is turned off, the primary and the secondary winding currents of the
transformer fall to zero. However, the secondary side filter inductor maintains a continuous
current through the freewheeling diode ‘D2’. Diode ‘D1’ remains off during this mode and isolates
the output section of the circuit from the transformer and the input.

NP: NS
D1 L
Edc L
C Load P
D2
C Load VO
Switch ‘S’ N
S and D1 Off,
D2 ON.
Fig.23.2(b): Equivalent circuit in
Fig. 23.3(a): Current path during Mode-2 Mode-2
Fig. 23.3(a) shows the current carrying portion of the circuit in bold line and Fig. 23.3(b) shows
the equivalent circuit active during mode-2. Points ‘P’ and ‘N’ of the equivalent circuit are
effectively shorted due to conduction of diode ‘D2’. The inductor current continues to flow
through the parallel combination of the load and the output capacitor. During mode-2, there is no
power flow from source to load but still the load voltage is maintained nearly constant by the large
output capacitor ‘C’. The charged capacitor and the inductor provide continuity in load voltage.
However since there is no input power during mode-2, the stored energy of the filter inductor and
capacitor will be slowly dissipating in the load and hence during this mode the magnitudes of
inductor current and the capacitor voltage will be falling slightly. In order to keep the load voltage
magnitude within required tolerance band, the converter-switch ‘S’ is turned on again to end the
freewheeling mode and start the next powering mode (mode-1). Under steady state, loss in
inductor current and capacitor voltage in mode-2 is exactly made up in mode-1. It may not be
difficult to see that to maintain load voltage within the desired tolerance band the filter inductor
and capacitor magnitudes should be sufficiently large. However, in order to keep the filter cost
and its physical size small these elements should not be unnecessarily too large. Also, for faster
dynamic control over the output voltage the filter elements should not be too large. [It may be
pointed out here that the filter inductor, capacitor, transformer and the heat sinks for the
switching devices together account for nearly 90% of the power supply weight and volume.]
One important factor that directly influences the size of the filter circuit elements and the
transformer is the converter’s switching frequency. High frequency operation of switch ‘S’ will
help in keeping the filter and transformer size small. The switching frequency of a typical forward
converter may thus be in the range of 100 kHz or more. The higher end limit on the switching
frequency comes mainly due to the finite switching time and finite switching losses of a practical
switch.
Switch limitations have been ignored in the simplified analysis presented here. As mentioned
earlier, the switch and the diodes have been assumed to be ideal, with no losses and zero
switching time. Control over switch duty ratio, which is the ratio of ON time to (ON + OFF)
time, provides the control over the output voltage ‘VO’.
Relation Between Input and Output Voltage

The equivalent circuits of mode-1 and mode-2 can be used to derive a steady state relation
between the input voltage, switch duty ratio (δ) and the output voltage. With the assumption of

constant input and output voltage, the instantaneous value of inductor voltage (eL) during mode-1
can be written as:
N
eL (t) = S Edc - VO ; for 0 ≤ t ≤ δT, -------------------------------- (23.1)
NP
Where t = 0 is the time instant when mode-1 of any steady state switching cycle starts, T is the
switching time period that may be assumed to be constant and δ is the duty ratio of the switch. It
can be seen that δT is the time duration of mode-1 and (1-δ) T is the time duration of mode-2. The
inductor voltage during mode-2 may similarly be written as:
eL (t) = - VO ; for δT ≤ t ≤ T, -------------------------------- (23.2)
Now since voltage across an inductor, averaged over a steady state cycle time, must always be
zero, one gets:
N
[ S Edc - VO ] δ + [- VO ] (1-δ) = 0,
NP
N
Or, VO = δ S Edc ------------------------------- (23.3)
NP
Thus according to Eqn. (23.3), the forward converter output voltage is directly proportional to the
switch duty ratio. It may be noticed that except for transformer scaling factor the output voltage
relation is same as in a simple dc-to-dc buck converter. It is to be noted that the output voltage
relation given by Eqn. (23.3) is valid only under the assumption of continuous inductor
current. For an improperly designed circuit or for very light load at the converter output, the
inductor current may decay to zero in the midst of mode-2 resulting into discontinuous inductor
current. Once the inductor current becomes zero, diode ‘D2’ in Fig. 23.3(a) no longer conducts
and the points ‘P’ and ‘N’ of the equivalent circuit in Fig. 23.3(b) are no longer shorted. In fact,
the output voltage ‘VO’ will appear across ‘P’ and ‘N’. Thus equation (23.2) remains valid only
for a part of (1-δ) T period. In case of discontinuous inductor current, the output voltage, which is
the average of voltage across points ‘P’ and ‘N’ will have a higher magnitude than the one given
by Eqn. (23.3). Under discontinuous inductor current the relation between output voltage
and switch duty ratio becomes non-linear and is load dependent. For better control over
output voltage discontinuous inductor current mode is generally avoided. With prior knowledge of
the load-range and for the desired switching frequency the filter inductor may be suitably chosen
to keep the inductor current continuous and preferably with less ripple.
23.3 Practical Topology of A Forward Converter Circuit

Fig. 23.4 shows the circuit topology of a practical forward converter. It takes into account the non-
ideal nature of a practical transformer. Other non-idealities of the circuit elements like that of
switch, diodes, inductor and capacitor are taken care of by modifying the circuit parameters
chosen on the basis of ideal circuit assumption. Most common consequence of non-ideal nature of
circuit elements is increase in looses and hence reduction in efficiency of the power supply. A
practical way to get around the consequence of circuit losses is to over-design the power supply.
P
The design should aim to achieve an output power of o , where ‘ Po ’ is the required output power
η
and ‘ η ’ is the efficiency of the converter. As a first order approximation, a typical efficiency
figure of around 80% may be assumed for the forward converter. Once the efficiency figure has
been considered the circuit may still be designed based on the simplified analysis presented here,

which neglects many of the non-idealities. Another common non-ideality is the low frequency
ripple and fluctuation in input dc supply voltage. In the simplified analysis input supply has been
assumed to be of constant magnitude. In a practical circuit, the variation in input supply is taken
care of by modulating the switch duty ratio in such a manner that it offsets the effect of supply
voltage fluctuation and continues to give the required quality of output voltage.
The non-ideality of the transformer, however, cannot simply be overcome by changing the circuit
parameters of the simplified circuit shown in Fig. 23.1. A practical transformer will have finite
magnetization current and finite energy associated with this magnetization current. Similarly there
will be some leakage inductance of the windings. However, windings of the forward-converter
transformer will have much smaller leakage inductances than those of fly-back converter
transformer. In fly-back transformer’s flux path some air-gap is deliberately introduced by
creating a gap in the transformer core (refer to lesson-22). Introduction of air gap in the mutual
flux path increases the magnitude of leakage inductances. Transformer of a forward converter
should have no air-gap in its flux path.
The forward-converter transformer works like a normal power transformer where both primary
and secondary windings conduct simultaneously with opposing magneto motive force (mmf)
along the mutual flux path. The difference of the mmfs is responsible for maintaining the
magnetizing flux in the core. When primary winding current is interrupted by switching off ‘S’,
the dotted ends of the windings develop negative potential to oppose the interruption of current (in
accordance with Lenz’s law). Negative potential of the dotted end of secondary winding makes
diode ‘D1’ reverse biased and hence it also stops conducting. This results in simultaneous opening
of both primary and secondary windings of the transformer. In case the basic circuit of Fig. 23.1 is
used along with a practical transformer, turning off of switch ‘S’ will result in sudden
demagnetization of the core from its previously magnetized state. As discussed in Lesson-22, a
practical circuit cannot support sudden change in flux. Any attempt to change flux suddenly
results in generation of infinitely large magnitude of voltage (in accordance with Lenz’s law).
Such a large voltage in the circuit will have a destructive effect and that should be avoided. Thus,
after switch ‘S’ is turned off, there must exist a convenient path for the trapped energy in the
primary due to magnetizing current. One solution could be a snubber circuit across the primary
winding, similar to the one shown in Fig.22.6 for a fly-back circuit (refer to lesson-22). Each time
the switch ‘S’ is turned off the snubber circuit will dissipate the energy associated with the
magnetizing flux. This, as has been seen in connection with fly-back converter, reduces the
power-supply efficiency considerably. A more preferred solution is to recover this energy. For this
reason the practical forward converter uses an extra tertiary winding with a series diode, as shown
in Fig. 23.4. When both switch ‘S’ and ‘D1’ turn-off together, as discussed above, the
magnetization energy will cause a current flow through the closely coupled tertiary winding and
the diode ‘D3’. The dot markings on the windings are to be observed. Current entering the dot
through any of the magnetically coupled windings will produce magnetic flux in the same sense.
As soon as switch ‘S’ is turned off, the dotted end voltages of the windings will become negative
in accordance with Lenz’s law. The sudden rise in magnitude of negative potential across the
windings is checked only by the conduction of current through the tertiary winding. As discussed
earlier unless the continuity in transformer flux is maintained the voltages in the windings will
theoretically reach infinite value. Thus turning off of switch ‘S’ and turn-on of diode ‘D3’ need to
be simultaneous. Similarly fall in magnetizing current through primary winding must be coupled
with simultaneous rise of magnetization current through the tertiary winding. In order that the
entire flux linking the primary winding gets transferred to the tertiary, the magnetic coupling
between these two windings must be very good. For this the primary and tertiary winding turns
are wound together, known as bifilar windings. The wires used for bifilar windings of the primary
and the tertiary need to withstand large electrical voltage stress and are costlier than ordinary
transformer wires.
NT : NP : NS
L
D1
Edc
Load
D2 C V (o/p)
D3
Switch S
Fig. 23.4: Circuit topology of a practical forward converter
Fig. 23.5 shows some of the typical current and voltage waveforms of the forward converter
shown in Fig. 23.4. For these waveforms, once again, many of the ideal circuit assumptions have
been made.
In Fig. 23.5, Vload is the converter output voltage that is maintained constant at VO. ‘IL’ is the
current through filter inductor ‘L’. The inductor current rises linearly during mode-1 as its voltage
is maintained constant as per Eqn.23.1. Similarly the inductor current decays at a constant rate in
mode-2 as it flows against the constant output voltage. Average magnitude of inductor current
equals the load current. ISW and VSW are respectively the switch current and switch voltage. VD3 is
the voltage across diode ‘D3’. Switch conducts only during mode-1 and carries the primary
winding current (IPr) of the transformer. The transformer magnetization current is assumed to be
negligibly small and hence the primary winding essentially carries the reflected inductor current.
As switch ‘S’ turns on, primary winding gets input dc voltage (with its dotted end positive). The
induced voltages in other windings are in proportion to their turns ratios. Diode ‘D3’ of the tertiary
N
winding is reverse biased and is subjected to a voltage − Edc (1 + T ) .
NP
As soon as switch ‘S’ is turned-off, primary and secondary winding currents fall to zero but diode
‘D3’ gets forward biased and the tertiary winding starts conducting to maintain a path for the
magnetizing current. While ‘D3’ conducts the tertiary winding voltage is clamped to input dc
voltage with its dotted end negative. Primary and secondary windings have induced voltages due
N
to transformer action. Primary winding voltage equals to Edc P , with dotted end at negative
NT
potential.
In Fig. 23.5, ‘VPr’ denotes the primary winding voltage. The net volt-time area of the primary

winding voltage must be zero under steady state. Voltage across switch ‘S’ can be seen to be the
N
sum of primary winding voltage and the input voltage and equals Edc (1 + P ) .
NT
As the tertiary winding current flows against the input dc supply, the magnetization current decays
linearly given by the following relation:
d Φm
NT = − Edc -------------------------------- (23.4)
dt
Where, Φ m = flux through the transformer core.

When the transformer is completely demagnetized, diode ‘D3’ turns off and voltage across
transformer windings fall to zero. The transformer remains de-magnetized for the remaining
duration of Mode-2.
When switch ‘S’ is again turned on, in the next switching cycle, the transformer flux builds up
d Φm
linearly given by the relation: N P = Edc , ----------------------------- (23.5)
dt
Under steady-state the increase in flux during conduction of switch ‘S’ must be equal to fall in
flux during conduction of tertiary winding and hence Eqns. 23.4 and 23.5 may be combined to
t t
show that T = P , where tT and tP are the time durations for which tertiary and primary
NT N P
windings conduct during each switching cycle. Now, tP = δT = on-duration of switch ‘S’ and the
tertiary winding conducts only during off duration of switch (during mode-2). Hence, (1-δ) T ≥
tT . As a result,
δ N NP
≤ P , or δ ≤ ------------------------------- (23.6)
1 − δ NT ( N P + NT )
Thus if N P = NT , the duty ratio must be less than or equal to 50% or else the transformer
magnetic circuit will not get time to reset fully during mode-2 and will saturate. Less duty ratio
means less duration of powering mode (mode-1) and hence less transfer of power to the output
N
circuit. On the other hand, as described above, if P is increased for higher duty ratio, the switch
NT
voltage stress increases.

V load VO
0
Imax Time
IL Imin
0 tON T
Time
Imax (NS / NP)
I Pr
0 tON T Time
Edc
V Pr
0 NP Time
− Edc
NT
0 Time
V D3 − Edc
NP
Edc (1 + )
NT NT
− Edc (1 + )
NP Edc
V sw 0
tON = δ T T Time
MODE-1 MODE-2 MODE-1
Fig.23.5: Some Typical waveforms of a practical Forward converter circuit
23.4 Selection of Transformer Turns Ratio

The transformer-winding turns ratio is a crucial design factor. The primary to secondary turns
ratio of the transformer is decided in accordance with Eqn. 23.3. For the required output voltage
N
(VO), the turns ratio S is found after considering the minimum magnitude of input supply
NP

voltage ( Edc ) and the maximum allowable duty ratio (δ). The maximum duty ratio of the
converter, as discussed above, is constrained by the primary to tertiary winding turns ratio (given
by Eqn. 23.6) but the choice of primary to tertiary winding turns ratio is often governed by the
voltage stress that the switch must withstand. Higher voltage stress will mean higher cost of
switch. If the tertiary winding turns is kept very high, the switch voltage stress reduces but
allowable duty ratio of switch and the power output of the converter becomes low and diode ‘D3’
voltage rating increases. Thus an optimum design needs to be arrived at to maximize the
performance of the converter.
23.5 Selection of Filter Circuit Inductor and Capacitor

The transformer’s secondary voltage is rectified and filtered suitably to get the desired quality of
output voltage waveform. The filter inductor and capacitor values need to be chosen optimally to
arrive at a cost-effective, less bulky power supply. In this section, some simple guidelines have
been developed to arrive at the required filter size.
Inductor current waveform during a typical switching cycle has been shown in Fig. 23.5. As
described earlier, mean (dc) value of inductor current equals the load current. The filter capacitor
merely supplies the ripple (ac) current of switching frequency. It has also been mentioned earlier
that for linear relation between the output voltage and the switch duty ratio, the inductor current is
desired to be continuous (refer to Eqn.23.3). In case the inductor current becomes discontinuous
the linearity between switch duty ratio and output voltage is lost and the output-voltage controller
circuit, which is often designed using linear control theory, is not able to maintain the desired
quality of output voltage. Hence filter inductor should be chosen to be sufficiently large such that
under expected range of load current variation, the inductor current remains continuous. In many
cases the minimum value of load current may not be specified or may be too low. If the load
connected to the output is very light or if there is no load, the inductor current will not remain
continuous. Hence, as a thumb rule, the filter inductor size may be chosen such that the inductor
current remains continuous for more than 10% of the rated load current. At 10% of the load, the
inductor current may be assumed to be just continuous. This gives a basis for choosing the
inductor value as detailed below:
With reference to the waveforms in Fig. 23.5, under just continuous inductor current, Imin = 0 and
Iload = 0.5 (Imin + Imax) = 0.5 Imax = 0.1 Irated, where Irated is the rated load current.
N
Again, using Eqn.23.1, (Imax - Imin) = δT ( S Edc - VO)/L ------------------- (23.7)
NP
Thus for Imin = 0 and Imax = 0.2 Irated,

N
L = δT ( S Edc - VO)/ (0.2 Irated) -------------------------- (23.8)
NP
where VO, the output voltage, is assumed to have a fixed magnitude. Input supply voltage, Edc ,
may itself be varying and the duty ratio is adjusted to keep VO constant in accordance with
N
Eqn.23.3. Thus even though ‘ Edc ’ and ‘δ’ are varying, their product (δ S Edc ) will be constant
NP

and equal to VO. [As mentioned earlier, only low frequency variation in supply voltage has
been considered. Switching frequency and the switch control dynamics are assumed to be
much faster.]
Hence, the inductor ‘L’ magnitude should correspond to minimum value of duty ratio and may be
5VO
written as L = (1 − δ min ) -------------------------------- (23.9)
I rated f SW
,where δ min is the minimum magnitude of duty ratio and f SW is the constant switching
frequency of the converter switch. Now in accordance with Eqn.(23.6) the maximum value of
NP
duty ratio may be taken as δ max = . Again to maintain constant output voltage
( N P + NT )
δ max Edc ,max
= . -------------------------------- (23.10)
δ min Edc ,min
, where Edc ,max and Edc ,min are maximum and minimum magnitudes of input dc voltage
respectively.
Edc ,min NP
Thus δ min = and
Edc ,max ( N P + NT )
5VO ⎡ Edc ,min NP ⎤
L= ⎢1 − ⎥ -------------------------------- (23.11)
I rated f SW ⎣⎢ Edc ,max ( N P + NT ) ⎦⎥
The inductor magnitude given by Eqn.(23.11) will limit the worst case peak to peak current ripple
in the filter inductor (= Imax - Imin) to 20% of rated current. [refer to Eqns.(23.7) and (23.8). It
may be noted here that as long as inductor current is continuous the peak-to-peak ripple in
the inductor current is not affected by the dc value of load current. For constant output
voltage and constant current through load, the inductor current ripple depends only on the
duty ratio, which in turn depends on the magnitude of input dc voltage]
Once inductor magnitude is chosen in accordance with Eqn.(23.11), peak to peak ripple in the
capacitor current will also be 20% of the rated current. This is so because the load, under steady
state, has been assumed to draw a constant magnitude of current.
Even though the output capacitor voltage has been assumed constant in our analysis so far,
there will be a minor ripple in capacitor voltage too which however will have only negligible
effect on the analysis carried out earlier. The worst case, peak to peak ripple in capacitor voltage
I
( vO , p − p ) can be given as: vO , p − p = rated -------------------------------- (23.12)
20Cf SW
, where ‘C’ is the output capacitance in farad. Capacitance value should be chosen, in
accordance with the above equation, based on the allowed ripple in the output voltage.
Quiz
1). If the turns ratio of the primary and tertiary windings of the forward transformer are in the
ratio of 1:2, what is the maximum duty ratio at which the converter can be operated?
Corresponding to this duty ratio, what should be the minimum ratio of secondary to primary

turns if the input dc supply is 400 volts and the required output voltage is 15 volts? Neglect
switch and diode conduction voltage drops.
[Answer: 1/3 and 9/80]
2) Find maximum voltage stress of the switch in the primary winding and diode in the tertiary
winding if the converter-transformer has 10 primary turns and 15 tertiary turns and the maximum
input dc voltage is 300 volts.
[Answer: Switch voltage stress = 500V, diode voltage stress = 750V]
3) Calculate the filter inductor and capacitor values for the forward converter described below:
Maximum duty ratio = 0.5, Input dc remains constant at 200 volts, output dc (under steady state)
= 10 volts ± 0.1 volt, primary to secondary turns = 10:1. The load current is expected to vary
between 0.5 and 5 amps. Assume just continuous conduction of inductor current at 0.5 amp load
current. Take switching frequency = 100 kHz.
[Answer: L = 50 micro Henry and C = 12.5 micro Farad]
(4) What function does the diode ‘D1’ of circuit in Fig.(23.4) have?
(i) rectifies secondary voltage
(ii) blocks back propagation of secondary voltage to transformer
(iii) both (i) and (ii)
(iv) protects diode ‘D2’ from excessive reverse voltage
[Answer: (iii)]

Module
3
DC to DC Converters
Lesson
24
C uK and Sepic Converter
n

Instructional objective
• l and Sepic converters with those of

Compare the advantages and disadvantages of CuK
three basic converters.
• l and Sepic
Draw the circuit diagrams and identify the operating modes of CuK
converters.
• l and Sepic converters.

Draw the waveforms of the circuit variables associated with CuK
• l converter.
Calculate the capacitor voltage ripples and inductor current ripples in CuK

24.1 Introduction
Switch Mode Power Supply topologies follow a set of rules. A very large number of converters
have been proposed, which however can be seen to be minor variations of a group of basic DC-
DC converters – built on a set of rules. Many consider the basic group to consist of the three:
BUCK, BOOST and BUCK-BOOST converters. The CUK, essentially a BOOST-BUCK
converter, may not be considered as basic converter along with its variations: the SEPIC and the
zeta converters.
The Canonical Cell forms the basis of analyzing switching circuits, but the energy
transport mechanism forms the foundation of the building blocks of such converters. The Buck
converter may consequently be seen as a Voltage to Current converter, the Boost as a Current to
Voltage converter, the Buck-Boost as a Voltage-Current-Voltage and the CUK as a Current-
Voltage-Current converter. All other switching converter MUST fall into one of these
configurations if it does not increase the switching stages further for example into a V-I-V-I
converter which is difficult to realize through a single controlled switch. It does not require an
explanation that a current source must be made to deliver its energy into a voltage sink and vice-
versa. A voltage source cannot discharge into a voltage sink and neither can a current source
discharge into a current sink. The first would cause current stresses while the latter results in
voltage surges. This rule is analogous to the energy exchange between a source of Potential
Energy (Voltage of a Capacitor) and a sink of Kinetic Energy (Current in an Inductor) and vice-
versa. Both can however discharge into a dissipative load, without causing any voltage or current
amplification. The resonant converters also have to agree to some of these basic rules.
l
24.2 Analysis of C uK converter
The advantages and disadvantages of three basic non-isolated converters can be summerised as
given below.
(i) Buck converter

1
L
2 S1
iB
Vin
C
Fig. 24.1: Circuit schematic of a buck converter
Features of a buck converter are

• Pulsed input current, requires input filter.
• Continuous output current results in lower output voltage ripple.
• Output voltage is always less than input voltage.

(ii) Boost converter
L
1
S1
2
R
Vin
C
Fig. 24.2: Circuit schematic of a boost converter

Features of a boost converter are
• Continuous input current, eliminates input filter.
• Pulsed output current increases output voltage ripple.
• Output voltage is always greater than input voltage.
(iii) Buck - Boost converter

1 2
S1
L R
Vin
C
Fig. 24.3: Circuit schematic of a buck boost converter
Features of a buck - boost converter are

• Pulsed input current, requires input filter.
• Pulsed output current increases output voltage ripple
• Output voltage can be either greater or smaller than input voltage.
It will be desirable to combine the advantages of these basic converters into one converter.
l converter is one such converter. It has the following advantages.
CuK
• Continuous input current.
• Continuous output current.
• Output voltage can be either greater or less than input voltage.
l
CuK converter is actually the cascade combination of a boost and a buck converter.
L1 2 L2
S1
1 + +
R
Vin C - C2 -
2'
S2
1'
Fig. 24.4: Circuit schematic of a boost-buck converter
S1 and S2 operate synchronously with same duty ratio. Therefore there are only two switching
states.
(i) 0 < t ≤ DT
S1 to (1)
& S2 to (1')
The circuit configuration is given below

L1 L2 L1 C1
R R
Vin C1 C2 C2
(a)
(ii) DT < t < T; S1 to (2) & S2 to (2')

L1 L1 L2
R R
Vin C2 C2
(b)
Fig. 24.5: Circuit topology of a boost-buck converter during different
switching intervals
(a) 0 ≤ t < DT, (b) DT ≤ t < T
These two topologies can also be obtained from the following circuit which is the so called
l converter.
CuK

L1 C1 L2
1 2
S
R
Vin C2
(a)
vc1
L1 C1 L2
+ -
ic2 i0
iL1 iL2
1 2 +
Vin R V0
iB C2 -
(b)
Fig. 24.6: Schematic and Circuit representation of ĈuK converter.
(a) Schematic diagram, (b) Circuit diagram
24.2.1 Expression for average output voltage and inductor

currents
L1 L2
+
ic1 ic2 i0
iL1 iL2
- +
R V0
Vin C2 -
C1 +
-
(a) 0 < t ≤ DT
L1 L2
+
ic1 iL2 ic2 i0
iL1
+ +
VC1 R V0
Vin C2 -
C1 - L2
-
(b) DT < t ≤ T
Fig. 24.7: Equivalent Circuit of a ĈuK converter during different
conduction modes.
(a) 0 < t ≤ DT (b) DT < t ≤ T

Applying Volt-sec balance across L1
Vin DT + (Vin − VC 1 ) (1 − D ) T = 0 (24.1)
∴ Vin (1 − D ) VC 1 = 0
Vin
or VC1 = (24.2)
1− D
Applying Volt-sec balance across L2
(V0 + VC1 ) DT + V0 (1 − D ) T = 0 (24.3)
or V0 + DVC1 = 0 (24.4)
DVin
or V0 = − DVC1 = − (24.5)
1− D
Expression for average inductor current can be obtained from charge balance of C2
I L 2 + I0 = 0 (24.6)
V0 V
∴ I L 2 = − I0 = − = D in (24.7)
R 1− D R
From power balance
v02 D 2 Vin2
Vin I L1 = V0 I 0 = = (24.8)
R (1 − D )2 R
∴ I L1 = D 2 Vin (24.9)
(1 − D ) R
2
24.2.2 Current ripple and voltage ripple calculations

The waveforms of different circuit variables of Fig. 24.7 are given in Fig. 24.8.

iB
DT T
IL1 MAX
IL1
iL1
IL1 MIN
t
IL2 MAX
IL2
iL2
IL2 MIN
t
t1 t2
ic1 IL2 MAX
IL2 MIN
t
- IL1 MIN
- IL1 MAX
vc1 VC1 MAX
VC1
VC1 MIN
t
ic2
1/2 Iˆ L2 p-p
t1 t2 t
-1/2 Iˆ L2 p-p
Vc2
Vc2
Fig. 24.8: Waveforms of circuit variables in a ĈuK converter.

From the waveforms of Fig. 24.8
DVin T
I L1MAX = I L1 MIN + (24.10)
L1
Vin DT
IˆL1 = I L1MAX − I L1MIN = (24.11)
p− p L1
From equation 24.9
I L1MAX + I L1 MIN = 2 I L1 = 2 D 2 Vin (24.12)

(1 − D ) 2 R
⎡ ⎤ DVin
∴ I L1MAX = ⎢ D 2 + RT ⎥ (24.13)
⎣ (1 − D ) 2 L1 ⎦ R
⎡ ⎤ DVin
I L1MIN = ⎢ D 2 − RT ⎥ (24.14)
⎣ (1 − D ) 2 L1 ⎦ R
V0 V
I L 2 MAX = I L 2 MIN − (1 − D )T = I L 2 MIN + in DT (24.15)
L2 L2
Vin DT
∴ IˆL 2 = I L 2 MAX − I L 2 MIN = (24.16)
p− p L2
From equation 24.7
I L 2 MAX + I L 2 MIN = −2 I 0 = 2 D in
V
(24.17)
1− D R
⎡ ⎤ DVin
∴ I L 2 MAX = ⎢ 1 + RT ⎥ (24.18)
⎣1 − D 2 L2 ⎦ R
⎡ ⎤ DVin
I L 2 MIN = ⎢ 1 − RT ⎥ (24.19)
⎣1 − D 2 L2 ⎦ R
For calculating voltage ripples it is noted that
vc1 = 1 ∫ ic1 dt
DT
(24.20)
c1 0
but for 0 < t ≤ DT ic1 = iL2 (24.21)

1 DT i dt = 1 DT i dt
c1 ∫0 c1 c1 ∫0 L 2
(24.22)

⎡I + I L 2 MIN RT ⎤ DTI L 2 I 0 DT
or vˆc1 = DT ⎢ L 2 MAX + = = (24.23)
C1 ⎣ 2 2 L2 ⎥⎦ c1 c1
D 2Vin T
or vˆc1 = (24.24)
RC1(1 − D )
t2
vˆc 2 = 1 ∫ ic 2 dt which is the hatched area under ic2 waveform in Fig. 24.8
c 2 t1
V DT Vin DT 2
∴ vˆc = 1 × 1 × T × in = (24.25)
c1 2 2 2 L2 8 L2 C2
l converter of given
Equations 24.11, 24.16, 24.24 and 24.25 can be utilized to design a CuK
specification

The SEPIC Converter
The previous chapter discussed the single stage conversion Buck and Boost converters
along with the two-stage Buck-Boost converter. This chapter offers a few additional topologies.
Fig. 24.9(a): A basic converter: BUCK converter

Fig. 24.9(a) is that of a basic Buck converter. From the voltage source C1, the converter charges
the current sink constituted by the inductor-diode (L-D). The current is further converted into
voltage without a switching stage (amplification) at C2. The canonical switching cell is
approached if the capacitors C1 and C2 are combined to be represented by a single capacitor C.
The cell includes T-C-L-D, the basic building block of DC-DC converters. The Boost converter
is realized if the positions of D and T are interchanged in Fig.24.9 (a). Now power flows in from
the right. Here, the energy stored in the inductor during each ON period of switch T is
transferred to the Capacitor during its OFF period.
The CUK converter as the dual of the Buck-Boost converter has current input and current
output stages. The basic SEPIC is a modification of the basic Boost and the CuK topologies.
Consider the Boost converter in Fig 24.9(b). At steady state, the average voltage across the input
inductor is zero. Equating the inductor voltages for the period when the switch T is ON with that
when it is OFF,
Vin .TON = ( Vout − Vin ) .TOFF
(24.26)
or, Vout = ( 1 ).Vin
1− ∂
where, ∂ is the duty ratio of the switch.
Fig. 24.9(b): BOOST converter
Fig. 24.10 Modified Boost with load across Diode for Boost-Buck
Operation. (left) without output filter, (right) with filter.
In the path, Vin-L-D-Vout, in Fig. 24.9(b), the average voltages across all the elements are
known. Thus, that appearing across the diode D is Vout – Vin. This voltage from Eqn 1 is:

V D = [(1 1 − ∂ ) − 1].Vin
= (∂ )Vin
1− ∂
A Boost-Buck converter is thus realized. This is the voltage that would appear in an
unfiltered form at the load in Fig. 24.10 (left). Now, since the source is a current source, the
output stage must be capacitive (voltage sink) which is taken care of by C2-D. The voltage across
D has high ripples, which can be filtered much like the Buck converter with an L (and a C3). The
CUK converter is thus realized. It is a I-V-I converter.
A glaring drawback of this derived converter topology is that the polarity of the output is
reversed. This is not acceptable for various reasons.
Now it is the turn of the Diode to be interchanged with the filter inductor. The inductor is
thus converted to be part of the switching circuit and it not just a filter. The SEPIC results – not
an entirely different one - but easily derivable from the previous topologies.
The SEPIC officially stands for “Single-Ended Primary Inductance Converter”. However,
the unofficial interpretation is more descriptive: “Secondary Polarity Inverted Cuk”.
Fig. 24.11(a): The basic SEPIC topology
Again, the basic input–output relation can be derived by considering the two inductors to
have average null voltage across themselves.
If the link capacitor has a voltage Vc across itself (consider it to be reasonably constant),
then for the input inductor, the volt-secs during the ON and OFF periods of the switch are:
Vin .TON = (VC − Vout − Vin )TOFF
(24.27)
or , VC = Vout − Vin (. 1 )
TOFF
For the output inductor,
VC .TON = V out .TOFF (24.28)
Eliminating, Vc and writing TON = ∂ . T,
Vout = ( ∂ )Vin (24.29)

1− ∂
Thus the SEPIC is also basically a BOOST-BUCK converter akin to the CUK converter.
(The Boost stage comes first followed by the Buck stage and it is also I-V-I converter)
In the practical SEPIC converter, the two inductors are coupled with the polarities as
indicated by dots in Fig. 24.11(a). The turns ratio is and the coupling is very tight. For such a
coupled-transformer SEPIC, equating the positive and negative volt-secs for the two inductors,
(Vin .K .VC ).TON = (Vout + VC − Vin − K .Vout ).TOFF (24.30)
for the input inductor, and
(VC − K ' .Vin ).TON = [Vout − K ' (Vout + VC − Vin )].TOFF (24.31)
Equations (24.28) and (24.29) can be obtained from the above two by substituting both K and K’
to zero to have no coupling between the two coils.
Fig. 24.11(b) The practical SEPIC topology with coupled inductors
The above two equations result in an identity to indicate that such a system cannot work.
This can be explained by examining the operation of the circuit. Initially when the
transistor is OFF, the capacitor C2 charges to the supply voltage Vin. When the transistor is
switched ON, the resulting active circuit is shown in Fig 24.12.
Fig. 24.12: Active part of the circuit when transistor is switched

with C2 charged toVin
The circuits to the left and right of the transistor are identical and both the windings are induced
with the supply voltages, resulting in null emfs on either side, which explains why the ideal
circuit will not work. However, neither the coupling between the inductors nor the effective turns
ratio can be unity. This results in a circuit with the features of the uncoupled circuit and the
circuit performs.
The second voltage source, VC, induces N.VC into the primary, where N is the turns ratio. For the
interesting case, Vin = VC = V1, if the turns ratio, n, is increased slightly from unity, by 1/k (where
k < 1 is the coupling coefficient between windings), then the voltage induced by Vin will increase
the voltage at the Drain of the transistor to N. V1, thereby "bootstrapping" the leakage inductance
of the input inductor. Because the voltage at each end of this leakage inductance is the same, its
inductance is effectively infinite. Consequently, all variations in magnetizing current, (through
M) due to a varying V1 is supplied from the secondary winding source. By symmetry, setting
n = k causes the secondary-winding current to become constant while the primary source
supplies the magnetizing-current variations.
This effect can be desirable because, for n = 1/k, it results in constant (DC) primary current.
Noisy switching current does not appear at the converter input but is diverted instead to the
secondary winding. However, typical values of k are slightly less than one, and turns ratios of
nearly 1:1 may not be easy to wind. One simplification is to use a 1:1 transformer, such as a low-
cost, commodity, common-mode power-line input-filter choke, and add a small additional
inductance in series with the primary winding. This effectively increases the leakage inductance
so that the same secondary-winding dominance of magnetizing current is obtained with n = 1.

The circuit is an alternative to the Boost converter and outputs an range which includes
the input range also being a Boost-Buck converter. It is superior to the other converters both in
terms of the input current purity and efficiency.
Fig. 24.13: Drain voltages of FLYBACK and SEPIC converters
The waveforms in Fig. 24.13 show the voltage at the transistor Drain present on the fly
back (Boost) and SEPIC circuits. The fly back transformer leakage inductance produces a
voltage spike that adds an additional level to the "flat-top" voltage. This level is about 1.5 times
the supply voltage for inputs around 20 V. In comparison, the SEPIC FET switching waveform
is clamped, and shows very little overshoot, or ringing. This clamping results in less switching-
loss, output voltage noise and a power stage that can be operated at a much higher frequency
than that of the fly back.
Again, the fly back transformer leakage inductance also produces a significant voltage
spike relative to the SEPIC at the output diode. A relatively high voltage (~200V) output diode is
required for the fly back to handle the large negative ringing compared to the SEPIC’s 60V
Schottky diode. The 0.5 volt forward drop of the SEPIC’s Schottky diode relative to the one volt
forward drop of the flyback's ultra-fast diode, results in significant power savings for the SEPIC.

Module
3
DC to DC Converters
Lesson
25
Design of Transformer for
Switched Mode Power
Supply (SMPS) Circuits
(i) Explain the underlying principles behind the design of a high frequency transformer
and inductor.
(ii) Do a preliminary design of a high frequency transformer for some popular
configurations of SMPS circuits.
(iii) Do a preliminary design of a high frequency inductor.
(iv) Estimate the size of an SMPS transformer of some given VA rating.
Transformers are required for galvanic isolation between input and output voltages and for
voltage and current scaling. It also helps in optimizing the device voltage and current ratings.
The switches, diodes and other circuit elements on the high voltage side of the transformer are
subjected to higher voltages but only lower currents. Similarly the devices put on the low voltage
side are subjected to less voltage stress but higher current stress. The dc-to-dc buck converter
shown in Fig. 25.1, which is used to get a low voltage output from a high input dc voltage
illustrates this point clearly. The circuit in Fig. 25.1(a) uses a step down transformer with proper
turns ratio and has the advantages discussed above. On the other hand the switch and diode and
the filter inductor in Fig. 25.1(b) need to withstand both input side voltage and output side
current. Also, the switch in case (b) will be constrained to operate in a narrow range, which may
cause lesser accuracy in output voltage control.
NP: NS
D1 L
Edc
C Load S
D2 +
_ L
Edc
L
S C O
D A
D
(a) (b)
Fig. 25.1: DC to DC buck converters: (a) Isolated type (b) Non-isolated type
Transformers used in switched mode power supply circuits are significantly different from the
power transformers that are used in utility ac supply system. Following are the important
differences:
(i) The input and output voltages and currents of a SMPS transformer are mostly
non-sinusoidal, whereas the transformers connected to utility ac supply are almost
always subjected to sinusoidal voltages and currents.
(ii) The currents and voltages of SMPS transformer are of very high frequency where
as utility type transformers are subjected to low frequency supply voltages.
(iii) SMPS transformers generally handle much smaller power than the utility
transformer.

SMPS transformer-core, because of high frequency operation, is generally made of hard
magnetic material like ferrites whereas the low frequency power transformers mostly use soft
magnetic material like silicon steel. Ferrites have very high ohmic resistance and the area
enclosed under the hysteresis loop of their B-H magnetization curve is significantly lower than
that of silicon steel. As a result, even at very high frequency operation, the hysteresis and eddy
current losses are low. [Low hysteresis loss is due to less B-H loop area and low eddy current
loss is due to very high resistivity of the core material.] The ferrites have low magnetic
permeability (typical value of relative permeability is around 100) and low saturating value of
flux density (typical value is around 0.4 Tesla) that are considerably less than that of silicon
steel. Ferrites are also brittle and fragile. The efforts are on to search for alternatives to ferrites
that may have higher permeability, may handle higher flux density and may be more rugged.
The fundamental principles concerning emf generation etc. in SMPS-transformers and power
transformers are identical and hence, in this lesson, many concepts of conventional transformer
design have been borrowed.
25.1 Recapitulation of Governing Equations for Utility Transformer

In case of sinusoidal flux of peak magnitude ‘ φm ’ and frequency ‘f’ linking the transformer
windings, the emf generated per turn of the winding will have a rms magnitude ‘Et’ given by:
Et = 4.44 f φm -----------------------------------------------(25.1)
The peak flux through the core is the product of peak flux density (Bm) and the core area (Ac),
i.e.,
φm = Bm Ac ----------------------------------------------- (25.2)
The windings are placed around the core and are accommodated in the window of the
transformer. The transformer window area (Aw) is related with the winding’s current rating and
the number of turns. For a single-phase transformer the relation between them is given by:
Aw kw δ = 2 N I ----------------------------------------------- (25.3)
,where kw is the window utilization factor and δ is the current density through the cross-
sectional area of the transformer windings. Window utilization factor, roughly varies between
0.35 to 0.6 and is dependent on the insulation requirements of the windings. A typical figure for
the current density through copper conductors of naturally cooled transformers is 3X106 amps
per square meter. If the current density through primary and secondary windings is taken
identical, they occupy equal window-space of the transformer. Some times the current densities
through the two windings may differ depending on their physical ability to dissipate heat. The
VA rating of a single phase transformer (= N Et I) can now be found from the above equations
as:
VA rating = 2.22 f Bm δ kw Ac Aw ----------------------------(25.4)

For the given operating frequency (f) the product ‘Ac Aw’, known as area product is roughly
proportional to the VA rating of the transformer as other parameters have nearly fixed
magnitudes.
25.2 Derivation of Design Equations for SMPS Transformer

The nature of voltage and flux waveforms in SMPS transformers is different from that of utility
transformer. Moreover SMPS circuits of different topologies generate different kinds of winding
voltages (and hence the flux-linked waveforms) and need to be considered separately.
In this section some representative voltage and flux waveforms have been taken up and through
them the transformer design procedure has been illustrated.
25.2.1 Transformer with Square-Wave Voltage and Bipolar Flux

Fig. 25.2 shows the typical winding voltage and core-flux waveform produced by one of the
popular SMPS topologies that utilizes a H-bridge converter to get high frequency ac voltage
from the dc input. The primary side of the SMPS transformer is connected to the H-bridge output
and the secondary side voltage is rectified and filtered to get regulated dc output voltage of
desired magnitude. The transformer windings carry bi-direction current and the flux linking the
windings is also bipolar. The input dc bus voltage is unregulated and often varies over a large
range. The duty ratio ‘D’ of the switches is controlled within 0<D<0.5 to regulate the output
voltage. The mean of the rectified secondary side voltage, under steady state and after accounting
for voltage drops in the rectifier diode and filter inductor, equals the desired load voltage and can
be assumed fixed to the output voltage ‘Vo’. However under dynamic condition, which may arise
due to sudden change in load or supply voltage, the mean (dc) output voltage on the secondary
side may be significantly higher than its steady state magnitude. For calculation of peak flux in
the core, the worst-case condition will correspond to maximum duty ratio (D=0.5) and maximum
magnitude of input voltage. The worst-case current through the windings will correspond to
maximum duty ratio (D=0.5) and peak magnitude of output (load) current. Now the transformer
may be designed as per the design steps given below:
(i) Determination of primary to secondary turns ratio (NP/ NS):- This can be found from
the knowledge of operating range over which the input dc voltage may vary. Let the
input voltage vary from Vmin to Vmax. With minimum input voltage ‘Vmin’ and duty
ratio ‘D’ = 0.5, the magnitude of square-shaped secondary side voltage should equal
(Vo + VR), where VR is the estimated voltage drop in the transformer winding, output
rectifier and filter circuit under maximum load condition. The transformer turns ratio
can thus be estimated to NP/ NS = Vmin /(Vo + VR). The actual number of turns in the
windings will be found as shown below in step (v).
(ii) Determination of peak magnitude of flux in the transformer core: As per above
discussion, the maximum flux in the core will correspond to a square wave voltage of
magnitude Vmax across the primary winding (refer to Fig. 25.2 with D=0.5). The
frequency of voltage waveform ‘f’(=1/T) is same as the frequency at which the
converter switches are turned on and is fixed beforehand. Now by simple integration
of the square wave voltage waveform, the peak flux ‘ φm ’ is related to the input
voltage as, Vmax = 4.0 f φm NP = 4.0 f Bm Ac NP ---------------------------(25.5)

(iii) Determination of winding current rating and requirement of window area: Let ‘Iom’
be the peak expected load current. The secondary winding of the transformer should
be rated to supply this current. Most SMPS circuits, with low magnitude of output
voltage, have a center-tapped secondary winding followed by a mid-point rectifier
circuit realized using two diodes (instead of bridge rectifier having four diodes). This
results in only one diode voltage drop during rectification, unlike two diode drops for
the bridge rectifier circuit. For SMPS with low output voltage, saving one diode drop
can result in significant increase in the efficiency. For this same reason, the diodes
used on the secondary side are Schottky diodes having low on-state voltage drop.
Each half of the center-tapped secondary winding requires NS turns as determined in

(i) above and they carry the load (dc) current only in alternate half cycles. Thus the
I
rms current rating of each half equals om and the net copper cross-sectional area
2
2NS Iom
required for the secondary winding is , where δ is the current density (as
δ
described in relation to Eqn.25.3). If the secondary was not center-tapped, the
rectifier used would be bridge type and the copper area for the secondary would have
N I
been just S om . The primary side carries the reflected secondary current and the
δ
NS Iom
required copper area for primary would equal . The total window area
δ
requirement for the transformer can now be given as:
N I
( )
A w k w = S om 1 + 2 ------------ (25.6),
δ
where Aw is the window area and kw is the window utilization factor (as discussed in
Sec.25.1).
(iv) Expression for VA rating of the transformer: Combining Eqns. (25.5) and (25.6) one
gets,
N
( )
Vmax S Iom 1 + 2 = 4fBm δk w A c A w --------------------------(25.7)
NP
Using relations derived in (i) above, Eqn.25.7 may be rewritten as:
( )
Vo Iom K1K 2 1 + 2 = 4fBm δk w A c A w --------------------------(25.8)
Vmax V + VR
where K1 = , a factor allowing for input voltage variation and K 2 = 0 ,
Vmin Vo
a factor coming due to voltage drop in rectifier diode, filter inductor etc. Vo Iom is the
( )
peak output power from the SMPS. The factor 1 + 2 on the L.H.S. of Eqn.27.8
will become 2.0 if the secondary winding is not center-tapped.
(v) Selection of transformer core and determination of number of turns in the windings:

Knowing the area product ‘Ac Aw’, as given by Eqn.25.8, the appropriate
transformer core is to be selected from the core-manufacturer’s catalog. Once the
area product matches, the details of other dimensions of the transformer core are
found from the catalog. Knowing window area (Aw) and core area (Ac), the number
of turns in the windings can be decided using Eqns. Like (25.5) or (25.6).
25.2.2 Transformer with Unipolar Flux

Many switched mode power supply circuits use only one controlled switch (like the forward
converter discussed in Lesson-23). The winding current and core-flux for most of these
transformers are unidirectional. Fig. 25.3 shows the typical winding voltage along with the
corresponding core-flux waveform for a forward converter. As shown in Lesson-23, when the
forward converter switch is turned on the primary winding is subjected to input dc voltage. As
soon as the primary winding is turned-off, the tertiary winding starts conducting and the voltage
across primary goes negative with a magnitude that equals the product of input voltage and the
turns ratio between the primary and tertiary windings. The maximum duty ratio (Dmax) of the
switch is also limited by the turns ratio between the primary and tertiary winding to allow
resetting of the transformer flux (as given in Sec.23.4 of Lesson-23). The maximum input
voltage (Vmax), switching frequency ‘f’(=1/T) and the maximum duty ratio (Dmax) are related
with the peak magnitude of core-flux is calculated as
Vmax Dmax = f φm NP = f Bm Ac NP -----------------------------------------------(25.9)
Eqn.25.9 may be compared with Eqn.25.5 for a typical value of Dmax = 0.5 (which corresponds
to the case when primary and tertiary windings have identical number of turns). Because of
unipolar nature of flux the utilization of core (in terms of emf generation) is poorer here.
The primary to secondary turns ratio (NP/ NS ) for the forward converter can be estimated as
done previously for the H-bridge converter. Accordingly, NP/ NS = Vmin Dmax /(Vo + VR), where
Vo is the required output voltage and VR denotes the voltage drop in output rectifier and filter
circuit.
The maximum rms current through the secondary winding can be equated to Iom D max and the
2NS Iom D max
window area (Aw) requirement is given by A w k w = -----------------(25.10)
δ
From Eqn.25.9 and 25.10, the VA rating of the transformer is given as:
NS
Iom ( D max ) = 0.5fBm δk w A c A w , which may be rewritten as
1.5
Vmax
NP
Vo Iom K1K 2 D max = 0.5fBm δk w A c A w ------------------------------------------(25.11)
Eqn.25.11 is similar to Eqn.25.8 above. The symbols used also denote the same. Knowing the
window area, the transformer core selection and other designs are done as described above in
connection with the H-bridge topology. The extra tertiary winding of a forward converter
transformer carries only magnetization current, which is a quite small and even a thin gauge wire
will serve the purpose. However, with the addition of tertiary winding the insulation requirement

of the transformer increases significantly and hence the window utilization factor (kw) becomes
low.
Voltage
+V
DT
T/2 3T/2 time
0
T
DT
-V
Flux
+φm
time
0
- φm
Fig. 25.2: Winding voltage and core-flux waveforms for a H-bridge type SMPS supply
Voltage
+VF
DT time
0
T
-VR
Flux +φmax
time
0
Fig. 25.3: Winding voltage and core-flux waveforms for a forward type SMPS supply
25.2.3 Design of Inductor-Transformer

The fly-back type SMPS circuits use a different kind of transformer, which as indicated in
Lesson-22, may be more appropriately called as inductor-transformer. Such a transformer is
more like two coupled inductors. These two coupled-inductors don’t conduct simultaneously,
unlike the two coupled-windings of a normal transformer. Also, the inductance needs to have a
finite magnitude so that current can build through it during each high frequency cycle and the
inductor may store the desired magnitude of energy. The windings of an inductor-transformer
facilitate energy storage in the magnetic field whereas the windings of an ideal transformer
(having infinitely large permeability ‘μ’ of the core) cannot be used for storing energy as energy

B2
density equals 0.5 . For finite magnitude of flux density ‘B’, the magnitude of ‘μ’ should be
μ
small to have higher energy per unit volume. ‘μ’ and magnetic reluctance have inverse relation,
as ‘μ’ decreases the reluctance increases. For a practical inductor the reluctance of its flux-path
should not be zero.
For an inductor, working in the linear region of the core’s magnetization, the following relation
holds good between inductance (L), reluctance (R) and the number of turns (N) of the inductor:
N2
L= . However a practical inductor still requires a good core with high permeability to
R
increase (i) coupling between the windings, (ii) to guide the flux path and hence decrease the
stray magnetic field lines and (iii) to keep the inductor size small. However to keep the
reluctance of the flux-path at the desired value, an appropriate length of air-gap is introduced in
the flux path. Fig.25.4 shows a double ‘E’ core with windings put around the central limb. After
the windings are placed in position, a non-magnetic material (like, paper) is inserted between the
faces of the core and the two ‘E’s of the core are clamped together. The non-magnetic material
acts like air-gap in the core. A preferred way of creating air-gap may be to grind some length
from only the central limb of the core. If ‘lg’ is the length of air-gap in the core, the inductance
(L) can be expressed as:
N 2 A c μ0
L= ------------------------------------------------------------------------ (25.12)
lg
where Ac is the area of the core’s limb on which the windings have been placed and μ0 is
the permeability of air-gap. In the above expression for inductance, the fringing effect of the flux
and the reluctance of the flux path through magnetic core have been neglected.
The core material should not saturate with the peak expected current (Ip) in the inductor. The
peak flux density in the core (Bm) can be related with the peak magnitude of current as
LI p = NA c Bm ------------------------------------------------------------------------ (25.13)
Knowing the current shape through the inductor, one calculates its rms magnitude (Ip,rms) and
NI p,rms
determines the window area required as A w k w = ------------------------------(25.14)
δ
Combining Eqns.25.13 and 25.14, one gets
LI p I p,rms = Bm δk w A c A w ------------------------------------------------------------- (25.15)
Eqn.25.15, gives the area product from which rest of the design can be proceeded as in the case
of transformer design shown above. LHS of Eqn.25.15 is indicative of the energy holding
capacity of the inductor (some what like VA rating of the transformer discussed above). Should
there be a couple winding (an inductor-transformer) the area product expression needs to be
modified to include the window space requirement of the secondary winding as well.

H F H H F H
A A A U A
U
L L L L
F
L F F L F
L L
P P P P
R S R R S R
I E I I E I
C C
Fig. 25.4: A typical SMPS transformer with a double ‘E’ type ferrite core and
interleaved primary and secondary winding
25.3 Transformer Winding

Often sandwiched type windings (as shown in Fig.25.4, where the secondary winding is
sandwiched between two halves of the primary) are used to reduce leakage inductance of the
windings. Sandwiching increases the insulation requirement between the windings.
For very high frequency applications, it may be preferred to use ribbon-conductor or copper foil
in place of solid circular conductors. This helps in better utilization of winding’s copper as high
frequency current is effectively limited to the surface of the conductor.
Many applications require grounded shields around the windings to reduce electro-magnetic
interference (EMI) caused by the SMPS transformers. As discussed in this lesson the SMPS
transformers often carry very high frequency ripples. These shields are essentially 3/4th turn of a
metallic foil put around the windings. There should be proper insulation between the shield and
Quiz Problems
(1) For a high frequency transformer the relation between the transformer size and frequency
of voltage waveform can be given as:
(a) Size increases with frequency
(b) Size decreases with frequency
(c) Core size reduces but copper weight increases with increase in frequency
(d) Size is independent of frequency
(2) The assembly of fly-back and forward type transformer cores may differ in the following
sense:
(a) Air-gap is inserted in fly-back type but it is undesirable for forward type.
(b) Air-gap in the flux path is undesirable for both types
(c) Only forward type must have a suitably length of air-gap
(d) Little air-gap is deliberately put for both transformers

(3) Transformers of forward type and H-bridge type SMPS circuits of identical VA rating
and frequency differ in the following sense:
(a) The forward type transformer will be bigger
(b) The H-bridge circuit will require bigger transformer
(c) They will be of identical size
(d) Only the window area of H-bridge transformer will be bigger
(4) The size of SMPS transformers operating over large input voltage range will compare
with similar rated transformer operating over a narrower input voltage range in the
following manner:
(a) Larger input voltage range will require larger transformer
(b) Larger voltage range requires smaller transformer
(c) Size remains independent of voltage range
(Answers: 1-b, 2-a, 3-a, 4-a)

Module
4
AC to AC Voltage
Converters
Lesson
26
AC to AC Voltage
Converters
(i) AC-AC power conversion topologies at fixed frequency
(ii) Power converter options available for the conversion
(iii) Ability to formulate equations describing the current waveform for the PAC
(iv) Ability sketch the current waveform by observation of the circuit
(v) Ability to assess the performance of the converter of the topologies
26.1 Introduction
AC to AC voltage converters operates on the AC mains essentially to regulate the output
voltage. Portions of the supply sinusoid appear at the load while the semiconductor switches
block the remaining portions. Several topologies have emerged along with voltage regulation
methods, most of which are linked to the development of the semiconductor devices.
Fig 26.1 Some single phase AC-AC voltage regulator topologies. (a) Back-to-back
SCR; (b) One SCR in (a) replaced by a four-diode full wave diode bridge; (c) A
bi-directionally conducting TRIAC; (d) The SCR in (b) replaced by a transistor.
The regulators in Fig 26.1 (a), (b) and (c) perform quite similarly. They are called Phase
Angle Controlled (PAC) AC-AC converters or AC-AC choppers. The TRIAC based converter
may be considered as the basic topology. Being bi-directionally conducting devices, they act on
both polarities of the applied voltage. However, dv dt re −applied their ratings being poor, they tend
to turn-on in the opposite direction just subsequent to their turn-off with an inductive load. The
'Alternistor' was developed with improved features but was not popular. The TRIAC is common
only at the low power ranges. The (a) and (b) options are improvements on (c) mostly regarding
current handling and turn-off-able current rating.
A transistorised AC-AC regulator is a PWM regulator similar to the DC-DC converters. It

also requires a freewheeling path across the inductive load, which has also got to be bi-
directional. Consequently, only controlled freewheeling devices can be used.

26.2 Operation with resistive loads
Fig. 26.2 illustrates the operation of the PAC converter with a resistive load. The device(s) is
triggered at a phase-angle 'α' in each cycle. The current follows the voltage wave shape in each
half and extinguishes itself at the zero crossings of the supply voltage. In the two-SCR topology,
one SCR is positively biased in each half of the supply voltage. There is no scope for conduction
overlap of the devices. A single pulse is sufficient to trigger the controlled devices with a
resistive load. In the diode-SCR topology, two diodes are forward biased in each half. The SCR
always receives a DC voltage and does not distinguish the polarity of the supply. It is thus
always forward biased. The bi-directional TRIAC is also forward biased for both polarities of the
supply voltage.
Fig. 26.2 Operation of a Phase Angle Controlled AC-AC converter with a resistive load
The rms voltage Vrms decides the power supplied to the load. It can be computed as
π
1
π α∫
Vrms = 2V 2
sin 2 ωt dωt
α sin 2α
= V 1− +
π 2π

Fig. 26.3 The rms output voltage and the most important harmonics versus triggering
angle α.
As is evident from the current waveforms, the PAC introduces significant harmonics both into
the load and the supply. This is one of the main reasons why such controllers are today not
acceptable. The ideal waveform as shown in Fig 26.2 is half wave symmetric. However it is to be
achieved by the trigger circuits. The controller in Fig. 26.4 ensures this for the TRIAC based
circuit. While the TRIAC has a differing characteristic for the two polarities of biasing with the
32V DIAC - a two terminal device- triggering is effected when the capacitor voltage reaches 32
V. This ensures elimination of DC and even components in the output voltage.
Fig. 26.4 DIAC based trigger circuit for a TRIAC to ensure symmetrical triggering
in the two halves of the supply.
For the SCR based controllers, identical comparators for the two halves of the AC supply, which
generates pulses for the two SCRs ensures DC and even harmonic free operation.
The PAC operates with a resistive load for all values of α ranging from 0o
The fundamental current, if can be represented as
2V ⎡ α sin 2α 1 cos 2α
if = ⎢ ( π− + ) sin ωt − ( − ) cos ωt ⎤⎥ 26.1
Rπ ⎣ 2 2 2 2 ⎦
In machine drives it is only the fundamental component, which is useful. However, in

resistance heating type of application all harmonics are of no consequence. The corrupted supply
current nevertheless is undesirable.

26.3 Power Factor
The power factor of a nonlinear deserves a special discussion. Fig. 26.2 shows the supply
voltage and the non-sinusoidal load current. The fundamental load/supply current lags the
supply voltage by the φ1, 'Fundamental Power Factor' angle. Cosφ1 is also called the
'Displacement Factor'. However this does not account for the total reactive power drawn by the
system. This power factor is inspite of the actual load being resistive! The reactive power is
drawn also y the trigger-angle dependent harmonics. Now
average power P
power factor = = 26.2
apparent voltamperes VI L
VI L1 cos φ1
= 26.3
VI L
I L1
distortion factor =
IL
The Average Power, P drawn by the resistive load is
1 2π 1 π 2V 2
P=
2π ∫0
viL d ωt =
π ∫α R
sin 2 ωt dwt 26.4
2V ⎡
2
α sin 2α ⎤
= ⎢π− + 26.5
Rπ ⎣ 2 2 ⎥⎦
The portion within square brackets in Eq. 26.5 is identical to the first part of the
expression within brackets in Eq. 26.1, which is called the Fourier coefficient 'B1'. The rms load
B
voltage can also be similarly obtained by integrating between α and π and the result can be
combined with Eq. 26.5 to give
power factor = per − unit rms load − current
= per − unit load power
= B p.u..
1
Fig. 26.5 Variation of various performance parameters with triggering angle

26.4 Operation with inductive loads
With inductive loads the operation of the PAC is illustrated in Fig 26.5. The current builds up
from zero in each cycle. It quenches not at the zero crossing of the applied voltage as with the
resistive load but after that instant. The supply voltage thus continues to be impressed on the load
till the load current returns to zero. A single-pulse trigger for the TRIAC 26.1 (c) or the anti-
parallel SCR (b) has no effect on the devices if it (or the anti-parallel device) is already in
conduction in the reverse direction. The devices would fail to conduct when they are intended to,
as they do not have the supply voltage forward biasing them when the trigger pulse arrives. A
single pulse trigger will work till the trigger angle α > φ, where φ is the power factor angle of the
inductive load. A train of pulses is required here. The output voltage is controllable only between
triggering angles φ and 180o.
The load current waveform is further explained in Fig. 26.6. The current is composed of two
components. The first is the steady state component of the load current, iss and the second, itr is
the transient component.
Fig. 26.6 Operation of a single phase PAC with an inductive load
Fig 26.7 Load current for a single phase AC-AC converter with a R_L load. Vs -
supply voltage, iss -steady state current component , itr - transient current
component and iload - load current (= iss + itr).

With an inductance in the load the distinguishing feature of the load current is that it must
always start from zero. However, if the switch could have permanently kept the load connected
to the supply the current would have become a sinusoidal one phase shifted from the voltage by
the phase angle of the load, φ. This current restricted to the half periods of conduction is called
the 'steady-state component' of load current iss. The 'transient component' of load current itr, again
in each half cycle, must add up to zero with this iss to start from zero. This condition sets the
initial value of the transient component to that of the steady state at the instant that the
SCR/TRIAC is triggered. Fig. 26.6 illustrates these relations.
When a device is in conduction, the load current is governed by the equation

L di + Ri =v s
dt
− (
R α
−t )
i load =
2V
[ sin (ω t − φ ) + sin (α − φ )e L ω
]
Z
Since at t = 0, iload = 0 and supply voltage vs = √2Vsinωt the solution is of the form
The instant when the load current extinguishes is called the extinction angle β. It can be
inferred that there would be no transients in the load current if the devices are triggered at the
power factor angle of the load. The load current I that case is perfectly sinusoidal.
26.5 AC-AC Chopper
Fig. 26.8 A complete Transitorised AC-AC chopper topology of the version shown in
Fig. 26.1 and the corresponding load voltage and current waveforms for an inductive
load. The output voltage is shown to be about 50% for a 0.5 Duty Ratio chopping.
The AC-AC converter shown in Fig 26.1 has to be augmented with two additional controlled
devices clamping the load as indicated in Fig. 26.7. A large capacitor across the supply terminals
is also to be inserted. These devices which are mostly transistors of the same variety as used for
the chopper are necessary to clamp the voltages generated by the switching-off of the current
carrying inductors in the load while the input capacitor takes care of the line inductances. The
harmonics in the line current and load voltage waveforms are significantly different from those
with the PACs. Mostly switching frequency harmonics are present in both the waveforms.

26.6 PAC as a static switch
Both single phase and three phase PACs are often used as static switches for applications like
switching on of highly inductive loads without transients or for regulating output AC voltages by
switching in tapings of a transformer. Such sequence control PACs while controlling the output
voltage also permit improvement of the power factor as seen by the source. Sequence control can
be two or multiple phase depending upon the application. Typical load voltage and current
waveforms are shown in Fig. 26.8. The outer TRIACs connected to thwe higher voltage leads of
the input transformer are triffered at the desired angle α, to realize the required load voltage.
Obviously this voltage is greater than that available at the low voltage terminal of the
transformer. This device continues conduction into the next half of the supply voltage till the
load current falls to zero. The inner TR2 starts conduction subsequently, requiring a wide pulse
or a train of pulses. TR1 can be however triggered by a single pulse.
Fig. 26.9 Load voltage and current control with a two-stage sequence control
26.7 Practice Questions and Problems with Answers

Q1 A single-phase transformer, assumed to have a negligible resistance compared to its
inductance is switched on via a PAC. At what trigger angle will the operation be free from
transients?
A1 For the transformer load φL ≈ 90ο

Therefore for transient free operation α = 90ο
Q2 For the load described in Q1, the PAC is triggered by a single pulse at α = 60ο . Sketch the
load current waveform.

A2 Since α < φL, the load current should have been continuous. However, the current in the
SCR first triggered extinguishes at a β the total load current, iL = iss + itr = 0. For this load
which can be considered to be highly inductive β ≈ 360ο, say ≈ 360ο. Thus the first SCR
conducts till that angle. The anti-parallel SCR is triggered at α = 60ο corresponding to a
β ≈ 180 + 60 = 240ο when it is still reverse biased. It fails to conduct. The load thus sees
only a unipolar current. The load current and voltage waveforms are illustrated in Fig 26.
A2. Note that both the load voltage and current waveforms contain DC components.
Fig. 26. A2 The load current waveform and its steady-state and transient
components when a highly inductive load is switched using single narrow trigger
pulses.

Module
4
AC to AC Voltage
Converters
Lesson
27
Three-phase AC
Regulators
• The circuits used for the three-phase ac regulators (ac to ac voltage converters)
• The operation of the above circuits with three-phase balanced resistive (R) load, along with the
waveforms
• The important points of comparison of the performance with different types of circuits
Introduction
In the last lesson − first one in the first half of this module, various circuits of the single-
phase ac regulators, also termed as ac to ac voltage converters, are described. In the basic circuit,
one Triac, or two thyristors, connected back to back, are used. The operation of the above circuits
with different types of loads − resistive (R) and inductive (R-L), along with the waveforms, is then
discussed. Lastly, the output voltage waveform is analysed.
In this lesson − the second one in the first half, firstly, the circuits of the three-phase ac
regulators, also termed as ac to ac voltage converters, are described. The operation of the above
circuits with three-phase balanced resistive (R) load, along with the waveforms, is then discussed. The
two basic circuits are three-phase three-wire type with load connected in star and three-phase delta-
connected one. Lastly, the important points of comparison of the performance with different types of
circuits, including the above two, are presented.
Keywords: Three-phase ac regulator circuits, AC to AC voltage converter, balanced three-phase
star- and delta-connected loads
Three-phase AC Regulators
There are many types of circuits used for the three-phase ac regulators (ac to ac voltage
converters), unlike single-phase ones. The three-phase loads (balanced) are connected in star or
delta. Two thyristors connected back to back, or a triac, is used for each phase in most of the
circuits as described. Two circuits are first taken up, both with balanced resistive (R) load
Three-phase, Three-wire AC Regulator with Balanced Resistive
Load
The circuit of a three-phase, three-wire ac regulator (termed as ac to ac voltage converter)
with balanced resistive (star-connected) load is shown in Fig. 27.1. It may be noted that the
resistance connected in all three phases are equal. Two thyristors connected back to back are
used per phase, thus needing a total of six thyristors. Please note the numbering scheme, which is
same as that used in a three-phase full-wave bridge converter or inverter, described in module 2
or 5. The thyristors are fired in sequence (Fig. 27.2), starting from 1 in ascending order, with the
angle between the triggering of thyristors 1 & 2 being 60° (one-sixth of the time period ( T ) of a
complete cycle). The line frequency is 50 Hz, with T = 1 / f =20 ms. The thyristors are fired or
triggered after a delay of α from the natural commutation point. The natural commutation point
is the starting of a cycle with period, ( 60° = T / 6 ) of output voltage waveform, if six thyristors
are replaced by diodes. Note that the output voltage is similar to phase-controlled waveform for a
converter, with the difference that it is an ac waveform in this case. The current flow is
bidirectional, with the current in one direction in the positive half, and then, in other (opposite)

direction in the negative half. So, two thyristors connected back to back are needed in each
phase. The turning off of a thyristor occurs, if its current falls to zero. To turn the thyristor on,
the anode voltage must be higher that the cathode voltage, and also, a triggering signal must be
applied at its gate.
A IL T1 ia a
+ T4 +
+
EAN EL Ean R
- -
- + B T3 ib b -
R n
T6 + - -
- EBN
ECN Ebn R
+ Ecn
T5 ic +
C T2 c
Fig. 27.1 Three-phase, three-wire ac regulator
The procedure for obtaining the expression of the rms value of the output voltage per phase
for balanced star-connected resistive load, which depends on range of firing angle, as shown
later, is described. If E s is the rms value of the input voltage per phase, and assuming the
voltage, E AN as the reference, the instantaneous input voltages per phase are,
e AN = 2 E s sin ω t , e BN = 2 E s sin (ω t − 120°) and eCN = 2 E s sin (ω t + 120°)
Then, the instantaneous input line voltages are,
e AB = 6 E s sin (ω t + 30°) , e BC = 6 E s sin (ω t − 90°) and
eCA = 6 E s sin (ω t + 150°)

E EAB EBC ECA EAB EBC EAB EBC ECA EAB
E
π/6 π π
0 2π ωt 0 ωt
E EAN E
EAN EBN ECN
EAN EBN ECN
0 π 2π 3π ωt 0 π 2π ωt
I g1 I g1
0 ωt 0 ωt
I g3 I g3
0 ωt 0 ωt
I g5 I g5
0 ωt 0 ωt
I g2 I g2
0 ωt 0 ωt
I g4
I g4
0 ωt 0 ωt
I g6 I g6
0 4 5 6 1 2 3 4 5 6 ωt 0 5 5 6 611 2 23 34 45 ωt
5 6 1 2 3 4 5 6 1
ECA EBC 6 6 1 122 3 34 45 56
E EAB EBC EAB
Ean
Ean
0 ωt
0 ωt α 10.5 EAB 0.5 EAC
α 0.5 EAB
(a) For α = 60°
0.5 EAB 0.5 EAC
(b) For α = 120°
Fig. 27.2 Waveforms for three-phase three-wire ac regulator
The waveforms of the input voltages, the conduction angles of thyristors and the output
voltage of one phase, for firing delay angles ( α ) of (a) 60° and (b) 120° are shown in Fig. 27.2.
For 0° ≤ α ≤ 60° (π / 6) , immediately before triggering of thyristor 1, two thyristors (5 & 6)
conduct. Once thyristor 1 is triggered, three thyristors (1, 5 & 6) conduct. As stated earlier, a
thyristor turns off, when the current through it goes to zero. The conditions alternate between
two and three conducting thyristors.

At any time only two thyristors conduct for 60° ≤ α ≤ 90° .Although two thyristors conduct
at any time for 90° ≤ α ≤ 150° , there are periods, when no thyristors are on. For α ≥ 150° , there
is no period for which two thyristors are on, and the output voltage becomes zero at
α = 150° (5 π / 6) . The range of delay angle is 0° ≤ α ≤ 150° .
The expressions of the rms value of the output voltage per phase for balanced star-connected
resistive load are as follows. Please note that θ = ω t .
For 0° ≤ α ≤ 60° :
1
2π
⎡ 1 ⎤ 2
E0 = ⎢ ∫ (e ) 2 dθ ⎥
⎣⎢ 2 π
AN
0 ⎦⎥
1
⎧⎪ 2 ⎡ π /3
sin θ 2 π / 2 +α
sin θ
2 2π / 3
sin θ 2 π / 2 +α
sin θ
2 π
sin θ2 ⎤ ⎫⎪ 2
= 6 Es ⎨
⎪⎩ 2 π
⎢
⎢⎣
∫
α 3
dθ +
π
∫ /2
4
dθ + ∫
π / 3+α 3
dθ + ∫
π /2 4
dθ + ∫
2π / 3+α
3
dθ ⎥ ⎬
⎥⎦ ⎪⎭
1
⎡1 ⎛ π α sin 2α ⎞⎤ 2
= 6 Es ⎢ ⎜ − + ⎟
⎣π ⎝6 4 8 ⎠⎥⎦
For 60° ≤ α ≤ 90° :
1
⎧⎪ 2 ⎡ 5π / 6 −π / 3 +α
sin θ 2 5π / 6 −π / 3 +α
sin θ ⎤ ⎫⎪ 2
2
E0 = 6 Es ⎨
⎪⎩ 2π
⎢ ∫
⎢⎣ π / 2 −π / 3+α 4
dθ + ∫
π / 2 −π / 3 +α
4
dθ ⎥ ⎬
⎥⎦ ⎪⎭
1 1
⎡1 ⎛ π 3 sin 2α 3 cos 2α ⎞⎤ 2 ⎡ ⎛π 3 sin (2α + 30° ⎞⎤ 2
= 6 Es ⎢ ⎜ − + ⎟ ⎥ = 6 Es ⎢ 1 ⎜ + ⎟⎥
⎜ 12 ⎟ ⎜ 12 ⎟
⎣⎢ π ⎝ 16 16 ⎠⎦⎥ ⎣⎢ π ⎝ 8 ⎠⎦⎥
For 90° ≤ α ≤ 150° :
1
⎧⎪ 2 ⎡ π
sin θ 2
sin θ
π
⎤ ⎫⎪ 2 2
E0 = 6 Es ⎨ ⎢ ∫ dθ + ∫ dθ ⎥ ⎬
⎪⎩ 2π ⎢⎣π / 2 −π / 3+α 4 π / 2 −π / 3 +α
4 ⎥⎦ ⎪⎭
1 1
⎡1 ⎛ 5π α sin 2α 3 cos 2α ⎞⎤ 2
⎟⎥ = 6 Es ⎢ 1 ⎛⎜ 5π − α + sin (2α + 60°) ⎞⎟⎥
⎡ ⎤2
= 6 Es ⎢ ⎜ − + +
⎜ 24 4 ⎟
⎣⎢ π ⎝ 16 16 ⎠⎦⎥ ⎣ π ⎝ 24 4 8 ⎠⎦
Three-phase Delta-connected AC Regulator with Balanced

Resistive Load
The circuit of a three-phase, delta-connected ac regulator (termed as ac to ac voltage
converter) with balanced resistive load is shown in Fig. 27.3. It may be noted that the resistance
connected in all three phases are equal. Two thyristors connected back to back are used per
phase, thus needing a total of six thyristors. As stated earlier, the numbering scheme may be
noted. It may be observed that one phase of the balanced circuit is similar to that used for single-
phase ac regulator described in the previous lesson (26) of the module. Since the phase current in
a balanced three-phase system is only ( 1 / 3 ) of the line current, the current rating of the
thyristors would be lower than that if the thyristors are placed in the line.

IL ia
A a
+ - + iab
R T5
T2
EAB EL
ECA T4
T1 R
T3 -
- ica
- - c
B R
+ ib b ibc
EBC T6
- + ic
C
Fig. 27.3 Delta connected three-phase ac regulator
Assuming the line voltage E AB as the reference, the instantaneous input line voltages are,
e AB = 2 E s sin ω t , e BC = 2 E s sin (ω t − 120°) and eCA = 2 E s sin (ω t + 120°)
It may be noted that E s is the rms value of the line voltage in this case. The waveforms of the
input line voltages, phase and line currents, and the thyristor gating signals, for α = 120° are
shown in Fig. 27.4.

E EAB EBC ECA EAB EBC
Em
0 π 2π 3π ωt
I g1
0
ωt
I g2
0 ωt
I g3
0
ωt
I g4
0
ωt
I g5
0 ωt
I g6
0
iab ωt
0
ωt
ibc
0
ωt
ica
0
ωt
ia
0 ωt
ib
0 ωt
ic
0 π 3π ωt
2π
For α = 120°
Fig. 27.4 Waveforms for three-phase delta-connected ac regulator

The rms value of the output phase voltage is obtained as
1 1 1
⎡ 1 2π ⎤2 ⎡ 2 π ⎤2 ⎡1 ⎛ 1 ⎞⎤ 2
E0 = ⎢ ∫ AB θ = ∫ s θ θ = π − α + α
2 2 2
( e ) d ⎥ ⎢ 2 ( E ) sin d ⎥ E s ⎢ ⎜ sin 2 ⎟⎥
⎣ 2π α ⎦ ⎣ 2π α ⎦ ⎣π ⎝ 2 ⎠⎦
When α = 0 , the maximum value of the output voltage is obtained, and the control range of
0
delay angle is 0° ≤ α ≤ 180° (π ) .

The line currents, which can be determined from the phase current, are,
ia = iab − ica , ib = ibc − iab and ic = ica − ibc .
From Fig. 27.4, it can be observed that the line currents depend on the delay angle, and may be
discontinuous. The rms value of line and phase currents in this case can be determined by
numerical solution or Fourier analysis.
If I n is the rms value of the nth harmonic component of a phase current, the rms value of the
phase current is obtained from
[ ]
1
I ab = I + I + I + I + I + I + " + I
1
2 2
3
2
5
2
7
2
9
2
11
2 2
n
For delta connection, the triplen harmonic components (i.e., those of order, n = 3 m , where m is
an odd integer) of the phase currents flow around the delta, and would not appear in the line.
This is due to the fact that these harmonic currents are like the zero sequence component, being
in phase in all three phases of the load. So, the rms value of the line current is,
[ ]
1
I a = 3 I 12 + I 52 + I 72 + I 112 + " + I n2 2
As a result, the rms value of the line current would not follow the normal relationship of a three-
phase system such that I a < 3 I ab .
Comparison of the Different Circuits used for Three-phase AC

Regulators
Besides the two circuits shown in figures 27.1 & 27.3, other circuits used for three-phase ac
regulators (ac to ac voltage converters), are shown in Fig. 27.5a-c. As given in point #6, the
balanced load for the circuits (Fig. 27.1 & 27.3) is taken as inductive (R-L) one, not resistive as
shown. The important points of comparison between the circuits are stated.
A ZL, RL
T1
T4
B ZL, RL
T3
T6
ZL, RL
C T5
T2
Fig. 27.5(a) 3-wire delta load

N
A ZL, RL
T1
T4
ZL, RL
B T3
T6
ZL, RL
C T5
T2
Fig. 27.5(b) 4-wire star load
A ZL, RL
T1
T4
B ZL, RL
T3
T6
C ZL, RL
T5
T2
Fig. 27.5(c) Control in delta

1. In two circuits (Fig. 27.3 & 27.5b), the individual phase controllers control their own loads
independently of the other. As stated earlier, they can, therefore be studied as three single-
phase controllers.
2. In other circuits, the individual phase controllers affect the other phase loads also, and they
have to be studied as complete three-phase circuits, as stated earlier in one case (Fig. 27.1).
3. The peak voltages occur across thyristors at or near the fully off state. In case of two circuits
(Fig. 27.3 & 27.5c), the maximum thyristor voltage is the peak of the line voltage, whereas in
the circuit (Fig. 27.5b), it is the peak of the phase voltage; in two circuits (Fig. 27.1 & 27.5a),
the maximum thyristor voltage will be somewhere between the peak of the phase and line
voltages depending on the leakage currents of the thyristors, the method of firing and the
presence of voltage-sharing resistors across the thyristors.
4. All the five circuits can be used under phase control.

5. The range of phase angle required to achieve full output range from zero to maximum varies
between the circuits, and are given in Table 27.1.
6. The maximum current in the thyristors is decided from the fully on condition, and the size of
the thyristors to be used should be chosen from this condition. The peak, mean and rms
values of the thyristor currents (Table 27.1) are related to the rms value of the input (ac)
current, which should be found by applying the full supply voltage to the load circuit. The
load impedance per phase is equal in magnitude (Z) and angle ( ϕ ), which is taken as
positive, as it is mostly inductive (R-L).
7. The difference between the two circuits (Fig. 27.1 & 27.5b) is that in the second one, the
neutral point is available, making it a 4-wire one.
8. The difference between the two circuits (Fig. 27.1 & 27.5a) is that in the second one, the
three-phase balanced loads are connected in delta, which can be converted into its equivalent
star, making it identical to the first circuit (Fig. 27.1). Also, the current in the thyristors in the
second case (Fig. 27.5a) are the line currents, which are higher than the phase currents, which
are flowing in the thyristors in the first one.
9. The difference between the two circuits (Fig. 27.1 & 27.5c) is that, in the second one, the
thyristors connected back to back, are in delta, with the load connected in the three lines.
Also, the current in the thyristors in the second case (Fig. 27.c) are the phase currents, which
are lower than the line currents, which are flowing in the thyristors in the first one.
Table 27.1 summarises the current and voltage rating parameters associated with all these
circuits used as three-phase ac controllers. E ac and I ac are the rms values of the line voltage
and line current respectively.
It may be mentioned that other types of circuits for three-phase ac regulator can be used, but
either the circuits are not bidirectional, i.e. unidirectional, or if they are bidirectional, in one half,
only diode connected back to back per phase, instead of thyristor, is used. In the second case,
only in one half with the thyristor per phase, controlled output voltage as shown earlier is
obtained, but in the other one, uncontrolled output voltage, same as input one, is obtained. In the
first case, where only one thyristor per phase is used, in one half, controlled output voltage is
obtained, but in the second half, output voltage is zero, as only one device, but not two devices,
is used. The readers are requested to refer to text books.
In this lesson – the second one in the first half, firstly the study of two basic circuits – one
with star connection and the other with delta connection, for three-phase ac regulator (ac to ac
voltage converter) are taken up. The operation with three-phase balanced resistive load, along
with waveforms, is then described. Lastly, the important points of comparison of the
performance with different types of circuits, including the above two, are presented. In the next,
i.e. third and final lesson in the first half, the control circuit for ac regulators will be described in
detail.

Table 27.1 Rating of the Parameters used in
Three-phase AC Regulators
Circuits Delay Maximum Maximum Thyristor Thyristor

(Fig. No.) angle, α input line load power current
for full current dissipation
V RWm Peak Mean RMS
control ( ac - rms)
I
(degrees) Vac I ac I ac I ac
27.1 150 E ac 3 I ac2 R 1.225 1.414 0.45 0.707
3Z
27.3 180 3 E ac I ac2 R 1.414 0.816 0.26 0.408
Z
27.5a 150 3 E ac I ac2 R 1.225 1.414 0.45 0.707
Z
27.5b 180 E ac 3 I ac2 R 0.816 1.414 0.45 0.707
3Z
27.5c 150 E ac 3 I ac2 R 1.414 0.816 0.26 0.408
3Z

Module
4
AC to AC Voltage
Converters
Lesson
28
Phase Angle Control in
Triac-based Single-phase
AC Regulators
• The circuit used for the phase angle control in triac-based single-phase ac regulators (ac to ac
voltage converters)
• The operation of the various blocks used in the circuit, along with the waveforms
• The harmonic analysis of the output voltage of a single-phase ac regulator with resistive load
Introduction
In the last lesson − second one in the first half of this module, various circuits of the three-
phase ac regulators, also termed as ac to ac voltage converters, are described. Two basic circuits
− star-connected and delta-connected, are first taken up. The operation of the two circuits with three-
phase balanced resistive (R) load, along with the waveforms, is then discussed. Lastly, the important
points of comparison of the performance with different types of circuits, including the above two, are
presented. In this case, the load is balanced inductive (R-L) one.
In this lesson − the third and final one in the first half, firstly, the circuit used for the phase
angle control in triac-based single-phase ac regulator, also termed as ac to ac voltage converter,
is presented. Then, the operation of the various blocks used in the above circuit, along with the
waveforms, is described. Finally, the harmonic analysis of the output voltage of a single-phase ac
regulator with resistive load is, briefly discussed.
Keywords: Phase angle controller circuit, Triac-based single-phase ac regulator, or ac to ac

voltage converter, harmonic analysis of the output voltage waveform.
Phase Angle Controller Circuit for Triac-based Single-phase AC

Regulator
The phase angle controller circuit for a triac-based single-phase ac regulator (ac to ac voltage
converter), is shown in Fig. 28.1. The power circuit (also shown in Fig. 26.1c (lesson #26))
consists of a Triac in series with inductive (R-L) load, fed from a single phase supply, with rated
voltage of, say 220 V(rms), having rated frequency ( f = 50 Hz). Before going into the operation
of the phase angle controller circuit, some important points of the bidirectional controlled device
(TRIAC), used in the ac circuit, having already been introduced in lesson #4 (module 1), is
briefly presented, as it is not frequently used. Similarly, for the same reasons, DIAC (may have
been introduced earlier), being used here as an uncontrolled bidirectional device, is also briefly
described.
TRIAC
A Triac is equivalent to two thyristors connected back to back as shown in Fig. 26.1a. Thus, it is
a bidirectional switching device, in contrast to the thyristor, which is a unidirectional device,
having reverse blocking characteristic, preventing the flow of current from Cathode to Anode.
So, when it (triac) is in conduction mode, current flows in both directions (forward and reverse).
This switching device is called as TRIAC (TRIode AC switch), with the circuit symbol shown in

Fig. 28.1. The three terminals of the triac are designated as MT1 , MT2 and gate, G , shown in
the same figure. These are similar to the terminals – A (Anode), K (Cathode) and G (Gate), of
the thyristor The terminal, MT1 is taken as the reference point for the measurement of the
voltages and currents at other two terminals, G (gate) and MT2 . The gate (G) is near to the
terminal, MT1 . The thyristor conducts with the current direction from Anode to Cathode
(positive), when a positive pulse is fed at the Gate terminal with respect to Cathode, and at that
time, with positive voltage applied between Anode and Cathode terminals, being connected in
series with the load. The triac conducts in the positive direction from MT2 to MT1 , when a
positive pulse is applied at the gate (G) terminal with respect to MT1 and at the same time, the
positive voltage is applied between two terminals, MT2 (+) and MT1 (−). Similarly, the triac
conducts in negative direction from MT1 to MT2 , when a negative pulse is applied at the gate
(G) terminal with respect to MT1 and at the same time, the positive voltage is applied between
two terminals, MT1 (+) and MT2 (−). Please note that the voltage between two terminals, MT2
and MT1 , is negative, in this case. So, the triac can conduct in both directions (positive and
negative) as given here, whereas the thyristor conducts in one (positive) direction only. Only
one triac is needed, whereas it is to be replaced by two thyristors, with consequent change in the
control circuit. The V-I characteristics of both thyristor and triac, have been discussed in lesson
#4 (module 1). A thyristor turns off (non-conducting mode), if the current through it, falls below
holding current. Similarly, a triac turns off (non-conducting mode), if the magnitude of the
current, irrespective of its direction, falls below holding current. As a triac is connected in an ac
circuit, and if the load in the circuit is resistive, the triac turns off at the zero crossing points of
the voltage in each half (the supply (input) voltage reaches zero at the end of each half cycle).
This will be nearly valid, if the load inductance is small, though the triac in that case turns off, as
the current though it goes to zero, after the zero crossing point is reached in each half. The case
of higher inductance in the load has been discussed in detail in lesson #26 (module 3).
The triac is a low power device, used in voltage control circuits, used as light dimmers, speed
control for fan motors (single-phase), etc. Some of the advantages and disadvantages of the triac
vis-a-vis thyristor are given.
Advantages
1. Triacs are triggered by positive or negative polarity voltages applied at the gate terminal.
2. A triac needs a single heat sink of slightly larger size, whereas anti-parallel thyristor pair
needs two heat sinks of slightly smaller sizes, but due to the clearance total space required is
more for thyristors.
Disadvantages
1. Triacs have low dv / dt rating as compared to thyristors.
2. Triacs are available in lower rating as compared to thyristors.
3. Since a triac can be triggered in either direction, a trigger circuit for triac needs careful
consideration.
4. The reliability of triacs is lower than that of thyristors.

DIAC
A Diac is equivalent to two diodes connected back to back. Also, it is a bidirectional device, in
contrast to the diode, which is a unidirectional device, having reverse blocking characteristic,
preventing the flow of current from Cathode to Anode. So, when it (diac) is in conduction mode,
current flows in both directions (forward and reverse). This switching device is called as DIAC
(DIode AC switch), with the circuit symbol shown in Fig. 28.1. The two terminals of the diac are
designated as T1 and T2 , shown in the same figure. These are similar to the terminals, A (Anode)
and K (Cathode), of the diode. The diac conducts, when the break-over voltage is reached in
either polarity across its two terminals. When T1 is positive with respect to T2 , and if at that time
if the voltage, V12 exceeds VBO1 (break-over voltage), the diac conducts in positive direction
from T1 to T2 . Similarly, when T2 is positive with respect to T1 , and if at that time if the
voltage, V21 exceeds VBO 2 (break-over voltage), the diac conducts in negative direction from T2
to T1 . So, a diac can conduct in both directions (positive and negative), whereas a diode conducts
only in positive direction from Anode (A) to Cathode (K), if, at that time, the voltage, V AK
exceeds VBO (break-over voltage). A diode does not conduct in the negative direction, if the
voltage, V AK is negative. A diode turns off (non-conducting mode), if the current through it, falls
below holding current. Similarly, a diac turns off (non-conducting mode), if the magnitude of the
current, irrespective of its direction, falls below holding current. If the V-I characteristic of diode
is known, as given in lesson #2 (module 1), the V-I characteristic of diac, on the lines of the triac
can be developed. The students are requested to study the characteristic of diac from a text book,
as it is not included here for obvious reason.
Now, the operation of the phase angle controller circuit (Fig. 28.1) is presented, with the
waveforms at various points shown in Fig. 28.2. The power circuit, the main component of
which is the triac, has been described earlier. The diac is symmetrical, unlike the triac, as
described earlier. So, the diac (Fig. 28.1) can be connected in opposite direction, with T1 in place
of T2 , and vice versa, i.e., T2 , T1 in place of T1 . But the operation here is described with the
connection as in the figure. The triac is not symmetrical, though it conducts in both directions
like diac. Two reasons are: the presence of third terminal, Gate (G), and the gate signal to be fed
between G & MT1 (reference) for triggering. The snubber part ( Rs & C s ), shown in the figure,
is used for the protection of the triac – the power switching device. The remaining part, including
the diac used for triggering of the triac, is the controller for the triac.

RS CS Snubber
TRIAC
A MT2 MT1
G D
+ l
1-phase
∼ Rpot. DIAC R1 o
ac
a
supply
- T1 T2 d
vc C
+ - Control
Circuit
B
Fig. 28.1: Phase angle controller circuit for a single-phase ac regulator using TRIAC
Vm
vi
0
π/2 π 3π/2 2π 5π/2 3π
θ (ωt)
-Vm
(a)
π+α1 π+α2
2π
vc 0
α1 α2 π 2π+α1 2π+α2 3π
θ (Ver
DIAC breaks
down
(b)

Vm
vL
π+α1 5π/2
2π
0
α1 π/2 π 3π/2 2π+α1 3π
θ
-Vm
(c)
Vm
vL
π+α2
0
α2 π 2π 2π+α2 3π
θ
-Vm
(d)
Fig. 28.2: Waveforms at various points of the controller circuit
(a) Input (source) voltage, vAB
(b) Voltage across capacitor, c(vc)
(c) Output (load) voltage, vDB with Rput = R2 (lower)
(d) Output (load) voltage, vDB with Rput = R3 (higher)
As soon the input (supply) voltage is given to the circuit, the capacitor, C starts getting
charged through the potentiometer resistance, R pot = R2 , the value of which is low and the load
resistance. The polarity of the input voltage is important. The start of the input voltage is taken as
the positive zero-crossing point (Fig. 28.2a), when the voltage changes from negative to positive.
The point, A is now positive with respect to B (Fig. 28.1). The polarity of the voltage across the
capacitor, C is that the left hand side is positive, with the right hand side as negative. The
capacitor voltage ( vC ) is shown in Fig. 28.2b. As soon as the capacitor voltage, vC reaches the
break-over voltage ( VBO ) of the diac (about 30 V), the diac starts to conduct in the positive
direction from T1 to T2 . At this point, the triac gets a positive pulse at its gate (G is now positive
with respect to MT1 ) and also MT2 is at a higher potential than MT1 . So, the triac is turned on at
the angle, θ = α 1 = ω t1 = 2 π f t1 . The current through the triac is in the positive direction from
MT2 to MT1 . Please note that the time constant of the charging circuit is related to the
potentiometer resistance ( R2 ), which is low. So, the time needed for the capacitor voltage to
reach the break-over voltage ( VBO ) is t1 ∝ α 1 . The triac is turned off at θ = π , when the input

voltage reaches the negative zero-crossing point. So, the conduction period (angle in rad) is from
α 1 to π in the positive half. The output (load) voltage ( v L = v DB ) waveform (Fig. 28.2c) is
nearly same as the input voltage ( vi = v AB ), neglecting the voltage drop across the triac. The
capacitor voltage (Fig. 28.2b) starts decreasing at t = t1 , and reaches zero after some time, the
time being small. The discharge path is through diac, the resistance R1 , and the gate, G & MT1
terminals of the triac, the total resistance is quite low. So, the time constant during discharge is
quite low, as compared to that during charging. The resistance, R1 is used to decrease the
capacitor current during discharge.
The pattern is repeated in the negative half of the input voltage, which is briefly described.
The capacitor, C starts charging in the opposite direction through the same path as given earlier.
The charging starts from the negative zero-crossing of the input voltage (Fig. 28.2a). The
polarity of the input voltage is now opposite, with the point, B being positive with respect to A.
The polarity of the capacitor voltage (Fig. 28.2b) is also opposite, with the right hand side as
positive, and the left hand side as negative. The charging time constant remains same (low), as it
was earlier. The capacitor voltage, vC (in magnitude) reaches the break-over voltage ( VBO ) of
the diac after time t1 ∝ α 1 , measured from the negative zero-crossing of the input voltage
( θ = π ). The diac now starts to conduct in the negative direction from T2 to T1 . At this point,
the triac gets a negative pulse at its gate (G is now negative with respect to MT1 ) and also MT1 is
at a higher potential than MT2 . So, the triac is turned on at the angle, ( θ = π + α 1 ). The current
through the triac is in the negative direction from MT1 to MT2 . The triac is turned off at the next
positive zero-crossing point ( θ = 2 π ). The conduction period (Fig. 28.2c) is from ( π + α 1 ) to
( 2 π ) in the negative half, the total conduction time ( π − α 1 ) being same in both half. The output
voltage waveform is identical, but it is opposite in this (negative) half. As in the earlier case, the
capacitor voltage (Fig. 29.2b) starts decreasing, and reaches zero after some time, the discharge
path remaining same. Thus, the diac helps in the turning on of the triac in both directions,
making the control circuit simple with few components only (Fig. 28.1). Though the function of
the diac could have been performed by using two diodes connected back to back, the control
circuit would have to be modified.
To change the conduction period, or the start of conduction of the triac, the potentiometer
resistance is to be increased from R2 to R3 , which is higher. The capacitor voltage waveform for
this case is shown in Fig. 28.2b as dotted line, as the time constant of the charging circuit also
increases. So, the time needed for the capacitor voltage (in magnitude, as both halves are
considered) to reach the break-over voltage ( VBO ) of the diac is now ( t 2 ∝ α 2 ). The conduction
period in the positive half (Fig. 28.2d) is from α 2 > α 1 to π , the total time in both half is
( π − α 2 ). The conduction period decreases. The rms value of the output voltage also decreases.
Other conditions, say during discharge of the capacitor voltage remaining same, is not described.
The range of phase angle delay, in the ideal case, is 0° < α < π . But normally, the lower
limit is higher than 0° , while the upper limit is lower than π (180°) . The input voltage (Fig.
28.2a) is zero at the two limits ( 0° & 180° ) in the ideal case. As the input voltage has to exceed
at least the voltage drop in the triac, and the capacitor voltage (Fig. 28.2b) also has to reach the
break-over voltage of the diac as given earlier, the normal range of phase angle delay is to be
used, not the ideal ones. Also, if the load is inductive, the current in the triac has to exceed a
threshold value, before the gate pulse can be withdrawn. Otherwise, the triac may not be

triggered, returning to off state again. This point may have been described in the case of phase-
controlled single-phase (bridge) converters (ac-dc), with inductive load in series with battery or
back emf, in lessons #10-11 (module 2).
Harmonic Analysis of the Output Voltage Waveform

Before the harmonic analysis of the output voltage waveform is taken up, the following
points may be noted. The output (load) voltage in ac regulators (both single-phase and three-
phase) decreases, as the delay angle is increased. This can be observed from the voltage
waveforms given in the previous lessons (#26-27) in the first half of this module (#4), for both
types of ac regulators. These are mainly used to decrease the speed of the induction motor with
fan type load ( TL ∝ N 2 ), not for constant load torque operation. The application is in the low
power range. The major disadvantage of these regulators is that the power factor and also
displacement factor decrease, with the increase in delay angle.
The harmonics are also present in the output (load) voltage waveforms, being phase-
controlled ones, of ac regulators. The harmonic analysis of the output voltage waveform (Fig.
28.3) of a single-phase ac regulator with resistive (R) load (please see the waveforms given in
figures 28.2c-d, which are nearly same as Fig. 28.3) is briefly presented. The symbols, including
some described earlier, are given.
v0 = Instantaneous value of the output (load) voltage
Vm = 2 V = Peak value of the input voltage
V = Vm / 2 = RMS value of the input voltage
f = 1 / T = Frequency (Hz) of the supply (input)
ω = 2 π f = Angular frequency (rad/s)
θ = ω t = Angle (rad)
T = 1 / f = Time period (s)
a n & bn are the maximum values of the sine and cosine components of the harmonics of order n,
present in the output voltage waveform respectively.
cn & θ n are the maximum value (amplitude), and phase angle, of nth harmonic component
respectively.
The relationships are cn = a n2 + bn2 , and θ n = tan −1 (bn / an ) ,
and the other relationships are an = cn cos θ n and bn = cn sin θ n .
The rms value of nth harmonic component = cn / 2

Vm
vo
π+α 2π
α π
θ(ωt)
-Vm
Fig. 28.3: Input and output voltage waveforms of a single-phase ac

regulator with resistive load.
The output (load) voltage waveform (Fig. 28.3) consists of two parts, the first one is positive
in the positive half cycle, while the second part is negative in the next (negative) half cycle. The
waveform has half-wave asymmetry, with only odd ( n = 2 m + 1 ) harmonics being present. The
even ( n = 2 m ) harmonics are not present in this case, as the second part is cancelled by the first
part. Also to be noted that the average value is zero. This can also be computed by the formulas
for the harmonic analysis of the output (load) voltage waveform of the buck converter (dc-dc)
circuit, given in lesson #18 in module 3. It can be observed for the single-phase ac regulator
circuit shown in lesson #26 in this module (#4) that the switching device (triac or two thyristors
connected back to back) is turned on at the delay angle, θ = α , and then turns off at θ = π ,
when the input voltage and also the output current goes to zero, in the first (positive) half, as the
load is resistive (R). This is repeated in the second (negative) half.
The output (load) voltage waveform for one cycle is,
v0 = 0 for α < θ < 0 ; v0 = Vm sin θ = 2 V sin θ for π < θ < α ;
v0 = 0 for (π + α ) < θ < π ; v0 = Vm sin θ = 2 V sin θ for (2 π ) < θ < (π + α )
In terms of the Fourier components, the expression is,
∞ ∞
v0 = ∑ (an sin nθ + bn cos nθ ) =
n =1, 3, 5, 7 ,"
∑c n
n =1, 3, 5, 7 ,"
sin (nθ + θ n )
where,
π π
2 2
an = ∫ v0 sin ( n θ ) dθ ; bn = ∫ v0 cos ( n θ ) dθ
π 0 π 0
Please note that two formulas given here, differ from two formulas given in lesson #18 (module
3). The expressions for the components of the fundamental and third harmonic, of the output
voltage are derived. The students are requested to derive, say the expressions for the other, say
fifth harmonic components.
π π
2 2 ⎛ 2V ⎞π
a1 = ∫ v0 (θ ) sin θ dθ = ∫ 2 V (sin θ ) 2 dθ = ⎜⎜ ⎟ ∫ (1 − cos 2θ ) dθ
⎟
π 0 πα ⎝ π ⎠α

⎛ 2V ⎞ ⎛ 2V ⎞ ⎛ 2V ⎞
⎟ ((π − α ) + 12 sin 2 α ) = ⎜
= ⎜⎜ ⎜ π ⎟ ((π − α ) + 0.5 sin 2 α )
⎟ (θ − 12 sin 2 θ ) απ = ⎜ ⎟
π ⎟ ⎜ π ⎟
⎝ ⎠ ⎝ ⎠ ⎝ ⎠
⎛ 2V ⎞
= ⎜⎜ ⎟ ((π − α ) + sin α cos α )
π ⎟
⎝ ⎠
2
π
2
π
⎛ 2V ⎞π
b1 = ∫ v0 (θ ) cos θ dθ = ∫ 2 V sin θ cos θ dθ = ⎜⎜ ⎟ ∫ sin 2 θ dθ
⎟
π 0 πα ⎝ π ⎠α
⎛ V ⎞ ⎛ V ⎞ ⎛ 2V ⎞
= ⎜⎜ ⎟ (cos 2 θ ) απ = −⎜ ⎟ (1 − cos 2 α ) = −⎜ ⎟ (sin α )2
⎟ ⎜ ⎟ ⎜ ⎟
⎝ 2π ⎠ ⎝ 2π ⎠ ⎝ π ⎠
2
π
2
π
⎛ 2V ⎞π
a3 = ∫ v0 (θ ) sin 3θ dθ = ∫ 2 V sin θ sin 3θ dθ = ⎜⎜ ⎟ ∫ (cos 2 θ − cos 4 θ ) dθ
⎟
π 0 πα ⎝ π ⎠α
⎛ 2V ⎞ 1 ⎛ 2V ⎞
= ⎜⎜ ⎜ 4 π ⎟ (sin 4 α − 2 sin 2 α )
⎟ ( 2 sin 2 θ − 14 sin 4 θ ) απ = ⎜ ⎟
⎟
⎝ π ⎠ ⎝ ⎠
2
π
2
π
⎛ 2V ⎞π
b3 = ∫ v0 (θ ) cos 3θ dθ = ∫ 2 V sin θ cos 3θ dθ = ⎜⎜ ⎟ ∫ (sin 4 θ − sin 2 θ ) dθ
⎟
π 0 πα ⎝ π ⎠α
⎛ 2V ⎞ 1 ⎛ 2V ⎞
= ⎜⎜ ⎜ 4 π ⎟ (cos 4 α − 2 cos 2 α + 1)
⎟ ( 4 cos 4 θ − 12 cos 2 θ ) απ = ⎜ ⎟
⎟
⎝ π ⎠ ⎝ ⎠
Using two sets of two expressions given earlier, the rms value ( cn / 2 ) and phase angle
( θ n ), of the harmonic components of the output (load) voltage, are obtained. As there is no
inductance in the load circuit, the rms values of the harmonic components of the output current
are proportional to those (the rms values of the harmonic components) of the output voltage. It
may be stated that the rms values of the harmonic components of both output voltage and current
decrease, though not in inverse proportion to ( n ) as given in lesson #18 (module 3), as the order
of harmonic ( n ) increases.
The expression for the rms value of the output voltage, as a function of phase angle delay α ,
is given in lesson #26 of this module (4), and not repeated here. The relation between the rms
value, V0r and the rms values of all odd harmonic components is,
V0 r = ∑ (c
n =1, 3, 5, 7 ,"
n / 2)2
It may be noted that this expression is different from that given in the section on the harmonic
analysis of the output voltage waveform of a buck converter (dc-dc) in lesson #18 (module 3).
This is, because the average value, V0 is zero, and the rms values of all even harmonic
components are also zero, with only odd harmonic components being present, as this waveform
has half-wave asymmetry (given earlier). The rms values of all odd harmonic components,
including that of fundamental one, can, first, be computed as per the formula given earlier. It
may be noted that, the rms values of only a few odd harmonic components need be computed,
because the rms values decrease, as the order of harmonic increases, as given earlier. Then, using
the expression for the rms value, it (rms value) can be computed. Finally, it can be checked from
the expression for the rms value (given in lesson #26).

The rms value of the fundamental ( n = 1 ) component of the output voltage, ( c1 / 2 ) is
maximum (highest) for α ≈ 0° with α > 0° , in normal case, though it reaches maximum at
α = 0° (ideal case). Also the rms value of the output voltage, V0r is maximum (nearly same as
the rms value of input voltage) for α ≈ 0° , and is slightly higher than the rms value of its
fundamental component. If the expression under the square root for the rms value is divided into
two parts – the rms value of fundamental component and the rms values of other odd harmonic
components, starting from third one, the new form is,
V0 r = (c1 / 2 ) 2 + ∑ (c
n = 3, 5, 7 ,"
n / 2)2
This expression can also be written as,

∑ (c
n = 3, 5 , 7 ,"
n / 2 ) 2 = (V0 r ) 2 − (c1 / 2 ) 2
From this expression, and also from the expressions given earlier, it can be observed that the rms
values of all odd harmonic components, except fundamental one, starting from third, are very
low.
The rms value of the fundamental component of the output voltage, ( c1 / 2 ) is minimum
(lowest) for α ≈ π (180°) with α < π , in normal case, though it is minimum (zero) at α = π
(ideal case). Also the rms value of the output voltage, V0r is minimum (not zero, but nearly zero)
for α ≈ π , and is slightly higher than the rms value of its fundamental component. From the
expression, using the rms value, and the rms value of fundamental component only, and other
expressions given earlier, it can be observed that the rms values of all odd harmonic components,
which also includes fundamental one in this case, are very low.
This type of harmonic analysis can be performed for the output voltage of controlled
(half/full) single/three-phase converters (ac-dc) with resistive load, as discussed in lessons #10-
11 & 13-14 in module 2. In the case of three-phase ones, the resistive load is balanced one.
Taking the case of a single-phase controlled bridge converter with resistive load, the output
voltage waveform obtained is of the same type, except that it is a dc one, with the second half of
the periodic waveform being also positive, unlike the case shown in Fig. 28.1. The voltage
waveform in that case, has half-wave symmetry (having dc and only even ( n = 2 m ) harmonic
components, but no odd harmonic components), unlike the case here, of the voltage waveform
having half-wave asymmetry (with only odd ( n = 2 m + 1 ) harmonic components, but no even
harmonic and also dc components, as given earlier).
In this lesson − the third and final one in the first half of this module, the circuit used for the
phase angle control in triac-based single-phase ac regulator or ac to ac voltage converter is, first,
presented. Then, the operation of the various blocks used in the above circuit, along with the
waveforms, is described. Finally, the harmonic analysis of the output voltage of a single-phase ac
regulator with resistive load is, briefly discussed. Starting with the next (fourth) lesson ─ first
one in the second half, the various types of cyclo-converters, used as ac to ac voltage converters,
are presented. The power circuit using mostly thyristors, the output voltage waveforms for both
single-phase and three-phase ones, and the various blocks of control circuit required (in brief),
are mostly described in detail.

Module
4
AC to AC Voltage
Converters
Lesson
29
Introduction to Cyclo-
converters
• The cyclo-converter circuits − basic principle of operation
• The circuit for the single-phase to single-phase cyclo-converter using thyristors
• The operation of the above cyclo-converter circuit, along with the voltage waveforms
Introduction
Earlier in the last three (4.1-4.3) lessons (first half) of this module, the circuit and operation
of ac to ac voltage controllers − both single-phase and three-phase, were described in detail. The
devices used are either triac, or thyristors connected back to back. In this lesson (4.4) − first one
in the second half of this module, the cyclo-converter is introduced as a type of power controller,
where an alternating voltage at supply frequency is converted directly to an alternating voltage at
load frequency (normally lower), without any intermediate dc stage. As will be shown in the last
(fifth) module, an alternating voltage at any frequency (output) is obtained using an inverter as a
power controller from a dc voltage fed at its input. This input, i.e. dc voltage, is again obtained
using a rectifier (converter) with ac voltage (normally at supply frequency) fed at its input. This
type has been described in module 2. Note that this is a two-stage process with an intermediate
dc stage. Now-a-days, the power switching devices used in the inverter circuit belong to
transistor family (termed as self-commutated ones), starting with power transistors, whereas
thyristors are still being used in the converter (rectifier) circuits. These devices are called force-
commutated ones, when used in dc chopper circuits (described in module 3), but in this case, i.e.
converter circuits, line commutation takes place. As stated earlier, the output frequency of the
cyclo-converter is limited to about one-third of supply (line) frequency of 50 Hz.
Initially, the basic principle of operation used in a cyclo-converter is discussed. Then, the
circuit of a single-phase to single-phase cyclo-converter using thyristors is presented. This is
followed by describing the operation of the above cyclo-converter circuit, along with voltage
waveforms. The readers at this stage, have gone through the following lessons − single-phase
fully controlled converter using thyristors, for obtaining dc output voltage from ac supply (#2.2),
and ac to ac voltage controllers − both single-phase and three-phase, using either triac, or
thyristors connected back to back (#4.1-4.3). In the above cases, the output voltage obtained is,
in the form of phase-controlled one, as can be observed from the waveforms shown in the above
lessons. In the present case, the output voltage of the cyclo-converter circuit (single-phase) using
thyristors, is synthesized from the above phase-controlled voltage waveforms, so as to obtain an
ac waveform (output) of low frequency, with the input being an ac voltage of higher frequency,
say line. The angle, at which the thyristors are triggered, is controlled to obtain the desired
waveform.
Keywords: Single-phase to single-phase cyclo-converter using thyristors, Voltage waveforms.
Cyclo-converter
Basic Principle of Operation
The basic principle of operation of a cyclo-converter is explained with reference to an
equivalent circuit shown in Fig. 29.1. Each two-quadrant converter (phase-controlled) is

represented as an alternating voltage source, which corresponds to the fundamental voltage
component obtained at its output terminals. The diodes connected in series with each voltage
source, show the unidirectional conduction of each converter, whose output voltage can be either
positive or negative, being a two-quadrant one, but the direction of current is in the direction as
shown in the circuit, as only thyristors − unidirectional switching devices, are used in the two
converters. Normally, the ripple content in the output voltage is neglected.
iP iN
+ iO
eP = Em sin ωot
∼ eo ac load ∼ eN = Em sin ωot
-
Positive (P) Negative (N)

converter converter
Control Circuit
er = Er sin ωot
Fig. 29.1: Equivalent circuit of cyclovonverter

The control principle used in an ideal cyclo-converter is to continuously modulate the firing
angles of the individual converters, so that each produces the same sinusoidal (ac) voltage at its
output terminals. Thus, the voltages of the two generators (Fig. 29.1) have the same amplitude,
frequency and phase, and the voltage of the cyclo-converter is equal to the voltage of either of
these generators. It is possible for the mean power to flow either ‘to’ or ‘from’ the output
terminals, and the cyclo-converter is inherently capable of operation with loads of any phase
angle − inductive or capacitive. Because of the uni-directional current carrying property of the
individual converters, it is inherent that the positive half-cycle of load current must always be
carried by the positive converter, and the negative half-cycle by the negative converter,
regardless of the phase of the current with respect to the voltage. This means that each two-
quadrant converter operates both in its rectifying (converting) and in its inverting region during
the period of its associated half-cycle of current.
The output voltage and current waveforms, illustrating the operation of an ideal cyclo-
converter circuit with loads of various displacement angles, are shown in Fig. 29.2. The
displacement angle of the load (current) is 0° (Fig. 29.2a). In this case, each converter carries
the load current only, when it operates in its rectifying region, and it remains idle throughout the
whole period in which its terminal voltage is in the inverting region of operation. In Fig. 29.2b,
the displacement angle of the load is 60° lagging. During the first 120° period of each half-
cycle of load current, the associated converter operates in its rectifying region, and delivers
power to the load. During the latter 60° period in the half-cycle, the associated converter

operates in its inverting region, and under this condition, the load is regenerating power back into
the cyclo-converter output terminals, and hence, into the ac system at the input side. These two
are illustrative cases only. Any other case, say capacitive load, with the displacement angle as
leading, the operation changes with inverting region in the first period of the half-cycle as per
displacement angle, and the latter period operating in rectifying region. This is not shown in Fig.
29.2, which can be studied from a standard text book.

Single-phase to Single-phase Cyclo-converter
The circuit of a single-phase to single-phase cyclo-converter is shown in Fig. 29.3. Two full-
wave fully controlled bridge converter circuits, using four thyristors for each bridge, are
connected in opposite direction (back to back), with both bridges being fed from ac supply (50
Hz). Bridge 1 (P – positive) supplies load current in the positive half of the output cycle, while
bridge 2 (N – negative) supplies load current in the negative half. The two bridges should not
conduct together as this will produce short-circuit at the input. In this case, two thyristors come
in series with each voltage source. When the load current is positive, the firing pulses to the
thyristors of bridge 2 are inhibited, while the thyristors of bridge 1 are triggered by giving pulses
at their gates at that time. Similarly, when the load current is negative, the thyristors of bridge 2
are triggered by giving pulses at their gates, while the firing pulses to the thyristors of bridge 1
are inhibited at that time. This is the circulating-current free mode of operation. Thus, the firing
angle control scheme must be such that only one converter conduct at a time, and the change
over of firing pulses from one converter to the other, should be periodic according to the output
frequency. However, the firing angles the thyristors in both converters should be the same to
produce a symmetrical output.
iP iN
+ iO
P1 P2 N1 N2
l
o
1-phase eO a 1-phase
ac d ac
supply supply
-
P4 P3 N4 N3
Bridge 1 (Positive) Bridge 2 (Negative)
Fig. 29.3: Single-phase to single-phase cycloconverter (using thyristor bridges)

When a cyclo-converter operates in the non-circulating current mode, the control scheme is
complicated, if the load current is discontinuous. The control is somewhat simplified, if some
amount of circulating current is allowed to flow between them. In this case, a circulating current
limiting reactor is connected between the positive and negative converters, as is the case with
dual converter, i.e. two fully controlled bridge converters connected back to back, in circulating-
current mode. The readers are requested to refer to any standard text book. This circulating
current by itself keeps both converters in virtually continuous conduction over the whole control
range. This type of operation is termed as the circulating-current mode of operation. The
operation of the cyclo-converter circuit with both purely resistive (R), and inductive (R-L) loads
is explained.
Resistive (R) Load: For this load, the load current (instantaneous) goes to zero, as the input
voltage at the end of each half cycle (both positive and negative) reaches zero (0). Thus, the

conducting thyristor pair in one of the bridges turns off at that time, i.e. the thyristors undergo
natural commutation. So, operation with discontinuous current (Fig. 29.4) takes place, as current
flows in the load, only when the next thyristor pair in that bridge is triggered, or pulses are fed at
respective gates. Taking first bridge 1 (positive), and assuming the top point of the ac supply as
positive with the bottom point as negative in the positive half cycle of ac input, the odd-
numbered thyristor pair, P1 & P3 is triggered after phase delay ( α 1 ), such that current starts
flowing through the load in this half cycle. In the next (negative) half cycle, the other thyristor
pair (even-numbered), P2 & P4 in that bridge conducts, by triggering them after suitable phase
delay from the start of zero-crossing. The current flows through the load in the same direction,
with the output voltage also remaining positive. This process continues for one more half cycle
(making a total of three) of input voltage ( f 1 = 50 Hz). From three waveforms, one combined
positive half cycle of output voltage is produced across the load resistance, with its frequency
being one-third of input frequency ( f 2 = f1 / 3 = 16 23 Hz). The following points may be noted.
The firing angle (α) of the converter is first decreased, in this case for second cycle only, and
then again increased in the next (third) cycle, as shown in Fig. 29.4b. This is, because only three
cycles for each half cycle is used. If the output frequency needed is lower, the number of cycles
is to be increased, with the firing angle decreasing for some cycles, and then again increasing in
the subsequent cycles, as described earlier.
es
5π
0
π 2π 3π 4π 6π
(a)
Mean output
e0 voltage
α2 α3 4π 5π 6π
0
α1 π 2π 3π α5
α4 α6
(b)
Fig. 29.4: Input (a) and output (b) voltage waveforms of a cyclo-
converter with an output frequency of 16 23 Hz for resistive
(R) load
To obtain negative output voltage, in the next three half cycles of input voltage, bridge 2 is
used. Following same logic, if the bottom point of the ac supply is taken as positive with the top
point as negative in the negative half of ac input, the odd-numbered thyristor pair, N1 & N3
conducts, by triggering them after suitable phase delay from the zero-crossing. Similarly, the
even-numbered thyristor pair, N2 & N4 conducts in the next half cycle. Both the output voltage
and current are now negative. As in the previous case, the above process also continues for three
consecutive half cycles of input voltage. From three waveforms, one combined negative half
cycle of output voltage is produced, having same frequency as given earlier. The pattern of firing
angle − first decreasing and the increasing, is also followed in the negative half cycle. One
positive half cycle, along with one negative half cycle, constitute one complete cycle of output
(load) voltage waveform, its frequency being 16 23 Hz as stated earlier. The ripple frequency of
the output voltage/ current for single–phase full-wave converter is 100 Hz, i.e., double of the
input frequency. It may be noted that the load (output) current is discontinuous (Fig. 29.4c), as
also load (output) voltage (Fig. 29.4b). The supply (input) voltage is shown in Fig. 29.4a. Only
one of two thyristor bridges (positive or negative) conducts at a time, giving non-circulating
current mode of operation in this circuit.
Inductive (R-L) Load: For this load, the load current may be continuous or discontinuous
depending on the firing angle and load power factor. The load voltage and current waveforms are
shown for continuous and discontinuous load current in Fig. 29.5 and 29.6 respectively.
es
0 π 3π 4π 5π 7π
2π 6π 8π
Mean o/p output (a)

e0 voltage
5π 6π 7π
0 π 2π 3π 4π 8π
Mean o/p output (b)

voltage
i0
0
α1 α2 α3
(c)
Fig. 29.5: Input (a) and output (b) voltage, and current
(c) waveforms for a cyclo-converter with discontinuous

es
0 π 2π 3π 4π 5π 7π
6π 8π
Mean o/p output (a)

e0 voltage
5π 6π 7π 8π
0
π 2π 3π 4π
α1 α2 α3 α4 α5 α6 α7
α8
(b)
i0
(c)
i0
(d)
Fig. 29.6: Input (a) and output (b) voltage, and current (c, d) waveforms
for a cyclo-converter with continuous load current.
(a) Discontinuous load current

The load current in this case is discontinuous, as the inductance, L in series with the
resistance, R, is low. This is somewhat similar to the previous case, but difference also exists as
described. Here, also non-circulating mode of operation takes place, with only one of the bridges
− #1 (positive), or #2 (negative), conducting at a time, but two bridges do not conduct at the
same time, as this will result in a short circuit. In this case, the output frequency is assumed as
( f 2 = 12.5 Hz), the input frequency being same as ( f 1 = 50 Hz), i.e., f 1 = 4 ⋅ f 2 , or f 2 = f 1 / 4 .
So, four positive half cycles, or two full cycles of the input to the full-wave bridge converter
(#1), are required to produce one positive half cycle of the output waveform, as the output
frequency is one-fourth of the input frequency as given earlier. As in the previous case with
resistive load, taking bridge 1, and assuming the top point of the ac supply as positive, in the
positive half cycle of ac input, the odd-numbered thyristor pair, P1 & P3, is triggered after phase
delay ( θ = ω t = α 1 ), such that current starts flowing the inductive load in this half cycle. But

here, the current flows even after the input voltage has reversed (after θ = π ), till it reaches zero
at ( θ = β 1 ) with (π +α 2) > β 1 > π , due to inductance being present in series with resistance, its
value being low. It may be noted that the thyristor pair is, thus, naturally commutated. In the next
(negative) half cycle, the other thyristor pair (even-numbered), P2 & P4, is triggered at (π +α 2) .
The current flows through the load in the same direction, with the output voltage also remaining
positive. The current goes to zero at (π + β 2) , with (π +α 3) > β 2 > π . This procedure continues
for the next two half cycles, making a total of four positive half cycles. From these four
waveforms, one combined positive half cycle of output voltage is produced across the inductive
load. The firing angle (α) of the converter is first decreased, in this case for second half cycle
only, kept nearly same in the third one, and finally increased in the last (fourth) one, as shown in
Fig. 29.5b.
To obtain negative output voltage, in the next four half cycles of output voltage, bridge 2 is
used. Following same logic, if the bottom point of the ac supply is taken as positive in the
negative half of ac input, the odd-numbered thyristor pair, N1 & N3 conducts, by triggering them
after phase delay ( θ = 4 ⋅ π + α 1 ). The current flows now in the opposite (negative) direction
through the inductive load, with the output voltage being also negative. The current goes to zero
at ( 4 ⋅ π + β 1 ), due to load being inductive as given earlier. Similarly, the even-numbered
thyristor pair, N2 & N4 conducts in the next half cycle, after they are triggered at ( 5 ⋅ π + α 2 ). The
current goes to zero at ( 5 ⋅ π + β 2 ). Both the output voltage and current are now negative. As in
the previous case, the above process also continues for two more half cycles of input voltage,
making a total of four. From these four waveforms, one combined negative half cycle of output
voltage is produced with same output frequency. The pattern of firing angle − first decreasing
and then increasing, is also followed in the negative half cycle. It may be noted that the load
(output) current is discontinuous (Fig. 29.5c), as also load (output) voltage (Fig. 29.5b). The
supply (input) voltage is shown in Fig. 29.5a. One positive half cycle, along with one negative
half cycle, constitute one complete cycle of output (load) voltage waveform, its frequency being
12.5 Hz as stated earlier. The ripple frequency remains also same at 100 Hz, with the ripple in
load current being filtered by the inductance present in the load.
(b) Continuous load current
As given above, the load current is discontinuous, as the inductance of the load is low. If the
inductance is increased, the current will be continuous. Most of the points given earlier are
applicable to this case, as described. To repeat, non-circulating mode of operation is used, i.e.,
only one of the bridges − #1 (positive), or #2 (negative), conducts at a time, but two bridges do
not conduct at the same time, as this will result in a short circuit. Also, the ripple frequency in the
voltage and current waveforms remains same at 100 Hz. The output frequency is one-fourth of
input frequency (50 Hz), i.e., 12.5 Hz. So, for each half-cycle of output voltage waveform, four
half cycles of input supply are required. Taking bridge 1, and assuming the top point of the ac
supply as positive, in the positive half cycle of ac input, the odd-numbered thyristor pair, P1 &
P3, is triggered after phase delay ( θ = ω t = α 1 ), such that current starts flowing the inductive
load in this half cycle. But here, the current flows for about one complete half cycle, i.e., up to
the angle, ( π + α 1 ) or ( π + α 2 ), whichever is higher, even after the input voltage has reversed,
due to the high value of load inductance. In the next (negative) half cycle, the other thyristor pair
(even-numbered), P2 & P4, is triggered at (π +α 2) . At that time, reverse voltage is applied across
each of the conducting thyristors, P1/P3, and the thyristors turn off. The current flows through the
load in the same direction, with the output voltage also remaining positive. Also, the current

flows for about one complete half cycle, i.e., up to the angle, ( π + α 2 ) or ( π + α 3 ), whichever is
higher. This procedure continues for the next two half cycles, making a total of four positive half
cycles. From these four waveforms, one combined positive half cycle of output voltage is
produced across the inductive load. The firing angle (α) of the converter is first decreased, in this
case for second half cycle only, kept nearly same in the third one, and finally increased in the last
(fourth) one, as shown in Fig. 29.6b.
To obtain negative output voltage, in the next four half cycles of output voltage, bridge 2 is
used. Following same logic, if the bottom point of the ac supply is taken as positive in the
negative half of ac input, the odd-numbered thyristor pair, N1 & N3 conducts, by triggering them
after phase delay ( θ = 4 ⋅ π + α 1 ). The current flows now in the opposite (negative) direction
through the inductive load, with the output voltage being also negative. The current flows for
about one complete half cycle, i.e., up to the angle, ( 5 ⋅ .π + α 1 ) or ( 5 ⋅ π + α 2 ), whichever is
higher, as the load is inductive. Similarly, the even-numbered thyristor pair, N2 & N4 conducts in
the next half cycle, after they are triggered at ( 5 ⋅ π + α 2 ). As described earlier, both the
conducting thyristors turn off, as reverse voltage is applied across each of them. Both the output
voltage and current are now negative. Also, the current flows for about one complete half cycle,
i.e. up to the angle, ( 5 ⋅ π + α 2 ) or ( 5 ⋅ π + α 3 ), whichever is higher. As in the previous case, the
above process also continues for two more half cycles of input voltage, making a total of four.
From these four waveforms, one combined negative half cycle of output voltage is produced
with same output frequency of 12.5 Hz. The pattern of firing angle − first decreasing and then
increasing, is also followed in the negative half cycle. It may be observed that the load (output)
current is continuous (Fig. 29.6c), as also load (output) voltage (Fig. 29.6b). The load (output)
current is redrawn in Fig. 29.6d, under steady state condition, while the supply (input) voltage is
shown in Fig. 29.6a. One positive half cycle, along with one negative half cycle, constitute one
complete cycle of output (load) voltage waveform.
Advantages and Disadvantages of Cyclo-converter

Advantages
1. In a cyclo-converter, ac power at one frequency is converted directly to a lower frequency in
a single conversion stage.
2. Cyclo-converter functions by means of phase commutation, without auxiliary forced
commutation circuits. The power circuit is more compact, eliminating circuit losses
associated with forced commutation.
3. Cyclo-converter is inherently capable of power transfer in either direction between source
and load. It can supply power to loads at any power factor, and is also capable of
regeneration over the complete speed range, down to standstill. This feature makes it
preferable for large reversing drives requiring rapid acceleration and deceleration, thus suited
for metal rolling application.
4. Commutation failure causes a short circuit of ac supply. But, if an individual fuse blows off,
a complete shutdown is not necessary, and cyclo-converter continues to function with
somewhat distorted waveforms. A balanced load is presented to the ac supply with
unbalanced output conditions.

5. Cyclo-converter delivers a high quality sinusoidal waveform at low output fre-quencies,
since it is fabricated from a large number of segments of the supply waveform. This is often
preferable for very low speed applications.
6. Cyclo-converter is extremely attractive for large power, low speed drives.
Disadvantages
1. Large number of thyristors is required in a cyclo-converter, and its control circuitry becomes
more complex. It is not justified to use it for small installations, but is economical for units
above 20 kVA.
2. For reasonable power output and efficiency, the output frequency is limited to one-third of
the input frequency.
3. The power factor is low particularly at reduced output voltages, as phase control is used with
high firing delay angle.
Converter Inverter
+
3-phase
load
ac supply
- 3-phase
Vdc
output
Fig. 29.7: DC link converter
The cyclo-converter is normally compared with dc link converter (Fig. 29.7), where two
power controllers, first one for converting from ac input at line frequency to dc output, and the
second one as inverter to obtain ac output at any frequency from the above dc input fed to it. The
thyristors, or switching devices of transistor family, which are termed as self-commutated ones,
usually the former, which in this case is naturally commutated, are used in controlled converters
(rectifiers). The diodes, whose cost is low, are used in uncontrolled ones. But now-a-days,
switching devices of transistor family are used in inverters, though thyristors using force
commutation are also used. A diode, connected back to back with the switching device, may be a
power transistor (BJT), is needed for each device. The number of switching devices in dc link
converter depends upon the number of phases used at both input and output. The number of
devices, such as thyristors, used in cyclo-converters depends on the types of connection, and also
the number of phases at both input and output. It may be noted that all features of a cyclo-
converter may not be available in a dc link converter. Similarly, certain features, like Pulse
Width Modulation (PWM) techniques as used in inverters and also converters, to reduce the
harmonics in voltage waveforms, are not applied in cyclo-converters. The various circuits used
and their operational aspects are discussed in detail in the next (last) module (#5) on DC to AC
Converters termed as Inverters.
Advantages and Disadvantages of DC Link Converter
Advantages
1. The output frequency can be varied from zero to rated value, with the upper frequency limit,
being decided by the turn-off time of the switching devices, which is quite low due to the use
of transistors in recent time.

2. .The control circuit here is simpler, as compared to that used in cyclo-converter.
3. It has high input power factor, if diode rectifier is used in the first stage. If phase-controlled
thyristor converter is used, power factor depends upon phase angle delay.
4. It is suitable for higher frequencies, as given earlier.
Disadvantages
1. The conversion is in two stages, using two power controllers − one as converter and other as
inverter, as stated earlier.
2. Forced commutation is required for the inverter, if thyristors are used, even though phase
control is used in converter, where natural commutation takes place.
3. The feature of regeneration is somewhat difficult, and also is involved to incorporate in a dc
link converter.
4. The output waveform of the inverter is normally a stepped one, which may cause non-
uniform rotation of an ac motor at very low frequencies (< 10 Hz). The distorted waveform
also causes system instability at low frequencies. This can be reduced by using PWM
technique as given earlier.
In this lesson, the first one in the second half of this module (#4), the cyclo-converter is first
introduced, along with the basic principle of operation. The circuit and the operation of single-
phase to single-phase cyclo-converter, with both resistive and inductive loads, are described in
detail, with voltage and current waveforms. The current is discontinuous, with resistive and
inductive (with low value of inductance) loads, but can be continuous, if the inductance is higher.
In the next lesson, the circuit and operation of three-phase to single-phase cyclo-converter,
followed by three-phase to three-phase one, will be described in detail.

Module
4
AC to AC Voltage
Converters
Lesson
30
Three-phase to Single-
phase Cyclo-converters
• The three-phase to single-phase cyclo-converter circuit, using two three-phase full-wave
thyristorised bridge converters
• The operation of the above cyclo-converter circuit, along with the voltage waveforms
Introduction
In the last lesson − first one in the second half of this module, firstly, the basic principle of
operation of the cyclo-converter circuits has been presented. This followed by the discussion of
the circuit, and the operation of the single-phase to single-phase cyclo-converter circuit with both
resistive and inductive loads, in detail. Two full-wave bridge converters (rectifiers) connected
back to back, with four thyristors as power switching device in each bridge, are used. Also
described are the advantages and disadvantages of the cyclo-converter. The dc link converter is
introduced briefly, along with its advantages and disadvantages.
In this lesson − the second one in the second half, firstly, the three-phase to single-phase
cyclo-converter circuit, using two three-phase full-wave thyristorised bridge converters, is
presented. Then, the operation of the above cyclo-converter circuit, with both resistive and
inductive loads, is described in detail, along with voltage waveforms. The mode of operation
used is the non-circulating current one. The following are discussed in brief −.the circulating
current mode of operation for the above, and also the cyclo-converter circuit, using two three-
phase half-wave converters.
Keywords: Three-phase to single-phase cyclo-converter, Voltage waveforms, Non-circulating
current, and Circulating current modes of operation, Three-phase full-wave bridge, and half-
wave converters.
Three-phase to Single-phase Cyclo-converter

The circuit of a three-phase to single-phase cyclo-converter is shown in Fig. 30.1. Two three-
phase full-wave (six-pulse) bridge converters (rectifier) connected back to back, with six
thyristors for each bridge, are used. The ripple frequency here is 300 Hz, six times the input
frequency of 50 Hz. So, low value of load inductance is needed to make the current continuous,
as compared to one using single-phase bridge converters described in the previous lesson (#4.4)
with ripple frequency of 100 Hz. Also, the non-circulating current mode of operation is used,
where only one converter − bridge 1 (positive) or bridge 2 (negative), conducts at a time, but
both converters do not conduct at the same time. It may be noted that each thyristor conducts for
about 120° (π / 3) , i.e., one-third of one complete cycle, whereas a particular thyristor pair, say
1& 2 conduct for about 60° (π / 6) , i.e., one-sixth of a cycle. The thyristors conduct in pairs as
stated, one (odd-numbered) thyristor in the top half and the other (even-numbered) one in the
bottom half in two different legs. Two thyristors in one leg are not allowed to conduct at a time,
which will result in short circuit at the output terminals. The sequence of conduction of the
thyristors is 1 & 6, 1 & 2, 3 & 2, and so on. When thyristor 1 is triggered, the conducting
thyristor (#5) in top half, being reverse biased at that time, turns off. Similarly, when thyristor 2
is triggered, the conducting thyristor (#6) in bottom half, being reverse biased at that time turns

off. This sequence is repeated in cyclic order. So, natural or line commutation takes place in this
case. Otherwise, the procedure is similar to the one as discussed in the previous lesson.
iP iN
P1 P3 P5 N1 N3 N5
+
l
3-phase A A 3-phase
o
ac B a B ac
iO
supply C d C supply
-
P4 P6 P2 N4 N6 N2
Fig. 30.1: Three-phase to single-phase cycloconverter

The procedure to be followed in the triggering of the thyristors in sequence in the two bridge
converters has been briefly given earlier. The readers are requested to go through two lessons
(#2.5-2.6) in module 2 (AC-DC Converters), or any standard text book. As given in the earlier
lesson (#4.4), the firing angle (α) of two converters is first decreased starting from the initial
value of 90° to the final value of 0° , and then again increased to the final value of 90° , as
shown in Fig. 30.2. Also, for positive half cycle of the output voltage waveform, bridge 1 is
used, while bridge 2 is used for negative half cycle. The two half cycles are combined to form
one complete cycle of the output voltage, the frequency being decided by the number of half
cycles of input voltage waveform used for each half cycle of the output. As more no. of segments
of near 60° (π / 6) is used, the output voltage waveform becomes near sinusoidal, with its
frequency also being reduced.
The initial value of firing angle delay is kept at α 1 ≈ 90° , such the average value (dc) of the
output voltage in this interval of near 60° (π / 6) [ Vav ∝ cos α 1 = cos 90° = 0.0 ], is zero. It may
be noted that the next thyristor in sequence is triggered at α 2 < 90° , as the firing angle is
decreased for each segment, to obtain higher voltage Vav ∝ cos α 2 = +ve , to form the sine wave
at the output. This can be observed from the points, M, N, O, P, Q, R & S, shown in Fig. 30.2.
From these segments, the first quarter cycle of the output voltage waveform from 0° to 90° , is
obtained. The second quarter cycle of the above waveform from 90° to 180° , is obtained, using
the segments starting from the points, T, U, V, W, X &Y (fig. 30.2). It may be noted that the
firing angle delay at the point, Y is α = 90° , and also the firing angle is increased from 0° (T)
to 90° (Y) in this interval. When the firing angle delay is 0° , the average value of the segment is
Vav ∝ cos α = cos 0° = 1.0 . The two quarter cycles form the positive half cycle of the output
voltage waveform. In this region, the bridge 1 (positive) is used. To obtain the negative half
cycle of the output voltage waveform ( 180° − 360° ), the other bridge converter (#2) termed
negative (N) is used in the same manner as given earlier, i.e. its firing angle delay (α) is first
decreased starting from the initial value of 90° to the final value of 0° , and then again increased

to the final value of 90° , as given earlier. The two half cycles (positive and negative) together
give one complete cycle ( 0° − 360° ) of the output voltage waveform.
Fabricated output voltage

Mean output voltage
α = 90° α = 0° α = 90°
e0
R ST U
Q V
P W
0 X
M N Y θ = ωt
Fig. 30.2 Output voltage waveforms for a three-phase to single phase

cyclo-converter.
The load on the output of the cyclo-converter is assumed to be inductive (R-L). The load can
also be capacitive. For inductive load, the output current (Fig. 30.3) lags behind the voltage by its
phase angle, φ (assumed to be positive). The load power factor is also +ve ( cos φ ). It may be
noted that the current is unidirectional in a thyristor converter. As the current, being alternating
in nature, flows in both directions in a complete cycle, two converters are connected in anti-
parallel. The positive (P) converter carries current during positive half cycle of output current,
while the other, i.e. negative (N) one carries current in the negative half cycle. As discussed in
the previous lesson (#29), P-converter acts as a rectifier, when the output voltage is positive, and
as an inverter, when the output voltage is negative (Fig. 30.3). Similarly, N-converter acts as a
rectifier, when the output voltage is negative, and as an inverter, when the output voltage is
positive. It can thus be inferred, in general, that one of two converters would operate as rectifier,
if its output voltage and current have the same polarity, and as an inverter, if these are of
opposite polarity.

Fabricated output voltage Mean output voltage
α = 90° α = 0° α = 90°
e0
θ = ωt
(a)
Inversion Inversion Inversion
Rectification Rectification
i0
Current in positive group Current in negative group

Angle of load
impedance (φ) (b)
Fig. 30.3 Voltage (a) and current (b) waveforms for a three phase full-wave (six-
pulse) cycloconverter.
Circulating Current Mode of Operation

In all the cases described earlier (Lesson 29 and current one (#30)), both for single-phase to
single-phase and for single-phase to three-phase cyclo-converters, circulating current-free or
non-circulating current mode of operation was described, wherein only one of two bridge
converters conducts at a time, but not both, in which case the converters would be short-
circuited. The positive (P) converter conducts, when the current is in the positive half of the
cycle, whereas the negative one conducts with the current flowing in the negative half. But, in
this case, i.e. circulating current mode of operation of the cyclo-converter, both the converters
would conduct at a time, with an inter-group reactor (IGR) between the positive and negative
groups as shown in Fig. 30.4. It may be noted that, though the output voltages of two converters
in the same phase have the same average value, but their output voltage waveforms as a function
of time are, however, different, and as a result, there is a net potential difference (voltage) across
two converters. Due to this voltage, the reactor is inserted to limit the circulating current. As
described, the main converter − positive/negative, as the case may be, acts in the rectifier mode,
and the other one acts in the inverter mode, with the average value along with the sign, of the
output voltage being same. Thus, the sum of their firing delay angle must be 180° (π ) . In other
words, if α p and α n are the firing angles for positive and negative group of converters,

respectively, then these firing angles must be controlled so as to satisfy the condition
(α p + α n ) = 180° (π ) .
IG reactor
iP a iN
b c
P1 P3 P5 N1 N3 N5
+
l
3-phase A A 3-phase
o
ac B a B ac
iO
supply C d C supply
-
P4 P6 P2 N4 N6 N2
Fig. 30.4: Cycloconverter (circulating current mode) with Inter-group(IG) reactor
The continuous current of each group in the circulating current mode imposes a higher
loading on each group compared to the non-circulating current mode of operation. In practice,
this mode, i.e. circulating current one, would only be used, when the load current is low, so that
continuous load current with a better waveform can be maintained. At the higher levels of load
current, the groups would be blocked to prevent circulating current. Control circuits would be
used to sense the level of the load current, allowing firing pulses to each group at low current
level, but blocking firing pulses to one or the other group at the higher current levels. The reactor
would be designed to saturate at higher current levels, when the cyclo-converter is operating in
the non-circulating current mode, thus permitting a smaller one.
Cyclo-converter, using two three-phase half-wave converters
A three-phase to single-phase cyclo-converter, using two three-phase half-wave converters, is
shown in Fig. 30.5. The principle of operation is same here as described earlier. Each thyristor
conducts for around 120° ( 2 ⋅ π / 3) , with the thyristors in each converter triggered in sequence,
i.e. 1, 2 & 3, whether it is P-type or N-type. It may be noted that the thyristors, 1, 2 & 3 are
connected to the phases, A, B & C, respectively, in series with the load impedance, as shown in
Fig. 30.5. The ripple frequency is 150 Hz, three times the input frequency of 50 Hz, as this
converter is a three-pulse one. So, the inductance in the inductive (R-L) load must be high, as
compared to one used in the earlier case, to make the current continuous. This inductance acts as
the filter for the output (load) current. The mode of operation here is non-circulating current one.
It may be noted that harmonic content, both in the output voltage and current waveforms, is
higher than those present in the earlier case using two three-phase full-wave bridge converters.
This is, because six pulses are used in a cycle for the earlier one, the ripple frequency being 300
Hz. Also three thyristors are used in each converter, i.e., a total of only 6 devices for two
converters are needed, whereas earlier, six thyristors are used for each bridge converter, needing
a total of 12 devices. This means that the cost is much lower, as also the control circuit in this

case is much simpler and cheaper, as only three pulses per each converter are needed. This may
be preferred, as only the harmonic content is more, which may not be a demerit in most of the
applications. If it is used to drive ac motors, the high impedance at the ripple frequency is
expected to make the output current near sinusoidal one, with the result that no additional
filtering component is needed. Other conditions, being same, are not described here, and the
waveforms also not shown, which is given in standard text book, or may be drawn from the
waveforms given in .the earlier case.
A A
B B
C C
3-phase 3-phase
supply supply
P1 P2 P3 N1 N2 N3
L
o
a
d
-
Fig. 30.5: Three-phase to single phase cycloconverter (two three-phase
half-wave converter)
In this lesson, firstly, the three-phase to single-phase cyclo-converter, using two three-phase
full-wave bridge converters, is described, with the circuit and various output voltage and current
waveforms. The non-circulating current mode of operation is presented in detail, so as to obtain
sinusoidal output voltage waveform. The circulating current mode is briefly discussed, along the
change in the circuit. Lastly, the circuit for the same type of cyclo-converter, with two three-
phase half-wave converters, is given, stating briefly the differences for this case. In the next
lesson, the three-phase to three-phase cyclo-converter will be taken up first. Three such circuits,
as described in this lesson, are needed in this case. Lastly, the analysis of the cyclo-converter
output wave-forms will be presented.

Module
4
AC to AC Voltage
Converters
Lesson
31
Three-phase to Three-
phase Cyclo-converters
• The three-phase to three-phase cyclo-converter circuit, using six three-phase half-wave
thyristorised converters
• The operation of the above cyclo-converter circuit
• The analysis of the cyclo-converter output waveform
Introduction
In the last lesson − second one in the second half of this module, firstly, the circuit and the
operation of the three-phase to single-phase cyclo-converter, with both resistive and inductive
loads, are described in detail. Two three-phase full-wave bridge converters (rectifiers) connected
back to back, with six thyristors as power switching devices in each bridge, are used. The mode
of operation is non-circulating current one, in which only one converter is conducting at a time.
The following are briefly presented − the circulating current mode of operation with both
converters conducting at a time, and the same type of cyclo-converter, using two three-phase
half-wave converters, stating mainly the merits.
In this lesson − the third one in the second half, firstly, the three-phase to three-phase cyclo-
converter circuit, using six three-phase half-wave thyristorised converters (two per each phase), is
described. The operation of the above cyclo-converter circuit is briefly discussed. The mode of
operation is the non-circulating current one. Lastly, the analysis of the cyclo-converter output
waveform is presented. The procedure for obtaining the expression for the output voltage (rms)
per phase for cyclo-converter is described.
Keywords: Three-phase to three-phase cyclo-converter, Three-phase half-wave converters.
Output waveform analysis
Three-phase to Three-phase Cyclo-converter

The circuit of a three-phase to three-phase cyclo-converter is shown in Fig. 31.1. Two three-
phase half-wave (three-pulse) converters connected back to back for each phase, with three
thyristors for each bridge, are needed here. The total number of thyristors used is 18, thus
reducing the cost of power components, and also of control circuits needed to generate the firing
pulses for the thyristors, as described later. This may be compared to the case with 6 (six) three-
phase full-wave (6-pulse) bridge converters, having six thyristors for each converter, with total
devices used being 36. Though this will reduce the harmonic content in both output voltage and
current waveforms, but is more costly. This may be used, where the total cost may be justified,
along with the merit stated. This has also been discussed in the last section of the previous lesson
(#30). The ripple frequency is 150 Hz, three times the input frequency of 50 Hz. In Fig. 31.1, the
circulating current mode of operation is used, in which both (positive and negative) converters in
each phase, conduct at the same time. Inter-group reactor in each phase as shown, is needed here.
But, if non-circulating current mode of operation is used, where only one converter (positive or
negative) in each phase, conducts at a time, the reactors are not needed.

A 3-φ supply
B
C
P N P N P N
Phase A Phase B Phase C
3-phase
load
Fig. 31.1: Three-phase to three-phase cycloconverter
It may be noted that the circuit in each of the three phases is similar to the cyclo-converter
circuit shown in Fig. 30.5. The firing sequence of the thyristors for the phase groups, B & C are
same as that for phase group A, but lag by the angle,120° and 240° , respectively. Thus, a
balanced three-phase voltage is obtained at the output terminals, to be fed to the three-phase
load. The average value of the output voltage is changed by varying the firing angles ( α ) of the
thyristors, whereas its frequency is varied by changing the time interval ( T / 3 = 1 /(3 ⋅ f 0 ) ), after
which the next (incoming) thyristor is triggered. With a balanced load, the neutral connection is
not necessary, and may be omitted, thereby suppressing all triplen harmonics.
Normally, the output frequency of the cyclo-converter is lower than the supply (input)
frequency (step-down region), limited to about one-third of it ( f 0 = f i / 3 ). This is necessary for
obtaining reasonable power output, efficiency and harmonic content. If the output frequency is to
be increased, the harmonic distortion in the output voltage increases, because its waveform is
composed of fewer segments of the supply voltage. Thus, the losses in cyclo-converter and also
in ac motor become excessive. By using more complex converter circuits with higher pulse
numbers, the output voltage waveform is improved, with the maximum useful ratio of output to
input frequency is increased to about one-half.
Analysis of the Cyclo-converter Output Waveform
An expression for the fundamental component of the phase voltage (rms) delivered by the
cyclo-converter is obtained by the procedure given here.
An m-phase converter circuit is assumed in which each phase conducts for ( (2 ⋅ π ) / m )
electrical radians in one cycle of supply (input) voltage. For example, in a three-phase, half-wave
(three-pulse) converter (m = 3), each phase conducts for ( (2 ⋅ π ) / 3 = 120° ) radians in a cycle of

( 2 ⋅ π ) radians. Similarly, in a three-phase, full-wave (six-pulse) converter (m = 6), the
conduction period of the periodic waveform is ( (2 ⋅ π ) / 6 = π / 3 = 60° ) radians in one cycle.
The output voltage waveform for an m-phase converter with firing delay angle α , is shown
in Fig. 31.2. With the time origin, PP′ taken at the peak value of the supply voltage, the
instantaneous phase voltage is given by e = E m cos ω t = 2 E ph cos ω t
where, E ph = Supply voltage per phase (rms).
(- π/m + α) Ec (π/m + α)
α P′
Em
- π/m P π/m ωt
2π/m
Fig. 31.2: Output voltage waveform for m-phase converter with firing angle α
From Fig. 31.2, it can be observed that the conduction period is from ( − π / m ) to ( π / m ), if the
firing delay angle is α = 0° . For the firing delay angle α , the conduction period is from
( − (π / m) + α ) to ( (π / m) + α ). From the above cases, the total conduction period is ( (2 ⋅ π ) / m ).
The average value of the output voltage is,
((π / m ) +α )
⎛ m ⎞ ⎛ m⎞ ⎛π ⎞
E dc = ⎜ ⎟⋅ ∫ 2 E ph cos ω t d (ω t ) = 2 E ph ⋅ ⎜ ⎟ ⋅ sin ⎜ ⎟ ⋅ cos α
⎝ 2 ⋅ π ⎠ ( − (π / m )+α ) ⎝π ⎠ ⎝ m⎠
This expression is obtained for dc to ac converter in module 2, and also available in text book.
When the firing delay angle is α = 0° , E dc has the maximum value of
⎛ m⎞ ⎛π ⎞
E d 0 = 2 ⋅ E ph ⋅ ⎜ ⎟ ⋅ sin ⎜ ⎟
⎝π ⎠ ⎝ m⎠
If the delay angle in the cyclo-converter is slowly varied as given earlier, the output phase
voltage at any point of the low frequency cycle may be calculated as the average voltage for the
appropriate delay angle. This ignores the rapid fluctuations superimposed on the average low
frequency waveform. Assuming continuous conduction, the average voltage is E dc = E d 0 ⋅ cos α .
If E 0 r is the fundamental component of the output voltage (rms) per phase for the cyclo-
converter, then the peak output voltage for firing angle of 0° is,
⎛ m⎞ ⎛π ⎞
2 ⋅ E 0 r = E d 0 = 2 ⋅ E ph ⋅ ⎜ ⎟ ⋅ sin ⎜ ⎟
⎝π ⎠ ⎝ m⎠
⎛m⎞ ⎛π ⎞
or, E0 r = E ph ⋅ ⎜ ⎟ ⋅ sin ⎜ ⎟
⎝π ⎠ ⎝ m⎠
However, the firing angle of the positive group, α p cannot be reduced to zero ( 0° ), for this value
corresponds to a firing angle of ( α n = 180° ) in the negative group. It may be noted that the firing
delay angles of the two (positive and negative) converters are related by ( α P + α n = 180° ), or
α p = 180° − α n . In practice, inverter firing cannot be delayed by 180° , because sufficient margin

must be allowed for commutation overlap and thyristor turn-off time, as given in module 2.
Consequently, the delay angle of the positive group cannot be reduced below a certain finite
value, α min . Therefore, the maximum output voltage per phase is,
Edc (max) = Ed 0 ⋅ cos α min = r ⋅ Ed 0 .
where, r = cos α min , and is called the ‘voltage reduction factor’.
Thus, the expression for the fundamental component of the phase voltage (rms) delivered by
⎡ ⎛m⎞ ⎛ π ⎞⎤
the cyclo-converter is, E 0 r = r ⋅ ⎢ E ph ⋅ ⎜ ⎟ ⋅ sin ⎜ ⎟⎥
⎣ ⎝π ⎠ ⎝ m ⎠⎦
Since α min is necessarily greater than zero, the voltage reduction factor is always lower than
unity. By deliberately increasing α min , and thereby reducing the range of variation of α about
the value of 90° , the output voltage, E0 r can be reduced, and a static method of voltage control
is obtained. In practice, the output voltage is lower than the theoretical value obtained earlier,
due to the influence of the commutation overlap and the circulating current between the positive
and negative groups. Thus, the expression for the output voltage (rms) per phase for a three-
phase to three-phase or a three-phase to single-phase cyclo-converter given earlier is obtained.
In this lesson, firstly, the circuit, and the operation, in brief, of the three-phase to three-phase
cyclo-converter, is described. Six three-phase half-wave converters are used in this case, with
two converters, connected back to back, per phase. A total of 18 thyristors are needed as power
switching devices, having three thyristors for each converter. Lastly, the analysis of the output
waveform for the cyclo-converter is presented. The procedure for obtaining the expression for
the output voltage (rms) per phase for cyclo-converter is described. In the next, i.e. last lesson of
this module on ac to ac voltage converters, the complete control circuit for the three-phase to
three-phase cyclo-converter, will be presented. The functional blocks, with circuits and
waveforms, will be described.

Module
4
AC to AC Voltage
Converters
Lesson
32
Control Circuit for Three-
phase to Three-phase
Cyclo-converters
• The control circuits used for the three-phase to three-phase cyclo-converters using two three-
phase converters, to generate the firing pulses for the thyristors
• The functional blocks, including the circuit and waveforms
Introduction
In the last lesson − third one in the second half of this module, firstly, the circuit along with
the operation of the three-phase to three-phase cyclo-converter, are described in brief. Two three-
phase half-wave converters, with three thyristors as power switching devices in each converter,
are needed, per phase, thus, using six such converters having a total of 18 thyristors. The mode
of operation is non-circulating current one, in which only one converter is conducting at a time.
Lastly, the analysis of the output waveform is presented.
In this lesson − the fourth and final one in the second half, the complete control circuit for the
three-phase to three-phase cyclo-converter, is presented in detail, showing how the firing pulses
are generated to trigger the thyristors. The function of the various blocks, with their respective
functions, and also circuit diagrams as needed, is described.
Keywords: The control circuit for the three-phase to three-phase cyclo-converter, functional
blocks.
Control Circuit for Cyclo-converters
The function of the control circuit used in this case is to deliver correctly timed, properly
shaped, firing pulses to the gates of the thyristors in the power converter (rectifier/inverter)
circuits, so as to generate a voltage of desired wave shape at the output terminals of a cyclo-
converter. The functional block diagram of the control circuit for the three-phase to three-phase
cyclo-converter, in the non-circulating current mode of operation, is shown in Fig. 32.1. The
same control circuit is applicable to the cyclo-converter operating in circulating current mode,
but the block designated as converter group selection will not be present in this case. There are
four functional blocks in the circuit as given here.
1. Synchronising circuit
2. Reference voltage sources
3. Logic and triggering circuit
4. Converter group selection circuit

Synchronizing e
and
modulating
signals
P-converter
e
er Logic e0
Reference and Load
signals trigger
circuit i0
N-converter
er
Converter
group
selection
i0
Fig. 32.1 Control circuit block diagram for a cycloconverter with

non-circulating current mode
Synchronising Circuit
The main function of the synchronising circuit is to derive low voltage signals to the control
circuit, which operates at low voltages. These low voltage signals must be synchronised to the
voltages applied to the main power circuit. Step-down transformers may be used for this purpose
with the filter circuit to avoid waveform distortion, if any. While deriving the modulating
voltages at the supply frequency, the phase shifting network may also be required. To determine
the instants at which the firing signals are to be produced, to be fed to the gates of the thyristors
in the two converter groups, the modulating signals are compared with the reference voltages.
Reference Voltage Sources
The reference signal is designed to control the output voltage in the sense that the output
voltages tend to follow the reference signal. It means that, if the amplitude and frequency of the
reference signal is varied, then the amplitude and frequency of the output voltage varies
automatically. In the case of three-phase to three-phase cyclo-converter, the reference signal does
additional function of shifting eOA , eOB & eOC , by phase shift of 120° . The three-phase variable
frequency, variable voltage sine wave reference voltage can be designed in various ways. As the
frequency of the reference voltage signal is low, normally limited to 16 23 Hz, one-third of the
line frequency of 50 Hz (may be higher (25 Hz) in some case), one of the design approach as
given here, is to use a mixer, wherein two signals having frequencies, f c & f d are mixed to

obtain frequencies ( f c ± f d ). Then, a low pass filter is used to obtain a signal of required
frequency, ( f c − f d ). The details are as follows.
φA fd
fc ± fd Low fc - fd
Mixer 1 pass
filter era
fc
Variable frequency
Astable φB fd fc ± fd Low fc - fd
multi- Ring Mixer 2 pass
vibrator counter filter erb
fc
fd fc ± fd Low fc - fd
Mixer 3 pass
φC filter erc
fc
φ3
φ2 Fixed
frequency
φ1 oscillator (fc)
Fig. 32.2 Reference voltage generator block diagram.

The reference voltage generator block diagram is shown in Fig. 32.2. An astable multi-
vibrator is used to generate a square wave with frequency, ( 3 ⋅ f d ), which is then fed to a three-
stage ring counter, whose output is three numbers of three-phase, square wave ( φ A , φ B & φC ) of
frequency f d , at a phase shift of 120° . The fixed frequency oscillator ( f c ) produces three
outputs ( φ1 , φ 2 & φ 3 ), which may be taken as three-phase. Three mixers − one for each phase, as
stated earlier, are used to combine the fixed and variable frequencies. The output of each mixer
stage is a square wave with half-wave symmetry, consisting of a fundamental and a series of odd
harmonics. If all higher order higher harmonics are neglected, the output signal has only two
frequencies, sum or difference of the fixed and variable frequencies, as given earlier. Then, a low
pass filter is used to select the low frequency signal ( f c − f d ), and also eliminate the high
frequency one ( f c + f d ). Finally, the three reference signals obtained are in the form,
era = r ⋅ Em sin (2 π ( f c − f d ) t ) ,
erb = r ⋅ E m sin (2 π ( f c − f d ) t − 120°) ,
erc = r ⋅ Em sin (2 π ( f c − f d ) t + 120°) ,
where, Em is the peak of the cosine modulating wave.
From the above equations, it can be observed that the amplitude and frequency of the reference
waveforms are controlled by varying r and f d respectively, while the phase sequence of the
three-phase outputs is controlled by setting f d , greater or lower than f c . The amplitude is varied
by changing r from 0 to 1, i.e. 1 ≤ r ≤ 0 .

era
+ 1 4
Comp. CPG JK FF 7
ea - AND D.C.
TP1
CLR
4'
CPG JK FF 7'
1' AND DC
TN1
CLR
erb
+ 2
Comp. CPG JK FF 8
eb - 5 AND DC
TP2
CLR
CPG = clock pulse
generator
CPG
2'
JK FF AND DC 8'
5' TN 2
CLR
erc
+ 3
Comp. CPG JK FF 9
ec - 6 AND DC
TP3
CLR
CPG
3' JK FF AND DC 9'
6' TN 3
CLR
BC
era = reference voltage for phase and DC = driver circuit consisting of pulse
output isolation, amplification, and high
ea, eb, ec = modulating signals frequency modulation.
Comp. = comparator BC = group selection and blanking
circuit logic
Fig. 32.3 Block diagram of logic and trigger circuit

Logic and Triggering Circuit
The block diagram of the main logic and triggering circuit for the output of phase A, using
the reference voltage, era , is shown in Fig. 32.3. Two similar blocks − one with the reference
voltage, erb , and the other with the reference voltage, erc , are used for the other two phases, B &
C of the output, in the case of a three-phase to three-phase cyclo-converter circuit.
The reference voltage, era is compared with the modulating voltages, ea , eb and ec ,
corresponding respectively to the supply voltages, e A , e B and eC . The comparators produce
short pulses. These pulses drive clock-pulse generator ( c p ), which is a positive edge-triggered
mono-stable multi-vibrator. Therefore, six pulses are obtained (4, 4′ , 5, 5′ , 6, 6′ ). Now, these
short pulses act as clock pulses to the flip-flops. The clearing of the pulses is done, when they are
not required. This clearing is done in the sequence, 6 → 5 → 4. This limits the presence of
pulses only when that thyristor is supposed to conduct, otherwise pulse is blocked. The pulse
output of the flip-flop is ANDed with the input coming from the blanking circuit. The output of
the AND gate is given to the driver circuit, which amplifies and isolates the pulses and drives the
respective thyristors. With the circulating current mode of operation, no blanking circuit is
needed. Hence, this input may be set at the logic ‘1’ permanently.
The block diagram of the logic circuit is general in the sense that the reference signals and
modulating signals could be of any wave-shape. In most applications, the sinusoidal reference
signals and co-sinusoidal modulating signals are commonly employed. The basic principle of the
co-sinusoidal modulation is the same as that of cosine wave crossing-pulse timing control
employed for firing of the thyristors in phase-controlled converters given in standard text books.
The typical waveforms at different points of the logic and triggering circuit (Fig. 32.3) are shown
in Fig. 32.4. The waveforms are drawn for one half cycle of the output voltage for the positive
converter with load having unity power factor. The same procedure can be followed for
developing the output voltage of the other half cycle of the positive converter. For the negative
converter, different modulating signals have to be taken into account. This is taken care of by
using an inverter at the output of each comparator (Fig. 32.3).

eA eB eC eA eB eC eA eB eC eA eB
0
θ = ωt
(a)
0
θ = ωt
(b)
1
0
2
0
3
0
(c)
4
0
5
0
6
0
(d)
7
0
8
0
9
0
(e)
Fig. 32.4 Various waveforms of logic circuit (Fig. 32.3) for one phase only.
(a) supply voltage of a three-phase half-wave (three-pulse) cycloconverter
showing output voltage of one half cycle. (b) modulating signals for positive
converter and reference voltage (100%). (c) outputs of comparators
Version used in 8
2 EE IIT, Kharagpur
the positive group. (d) clock pulse for positive group (e) gate pulses to
thyristors.
Circuit for Converter Group Selection
The block diagram of the converter bank selection is shown in Fig. 32.5. The load current is
allowed to flow through the P-converter or the N-converter through suitable logic. D is the delay
during which period the firing pulses to both the converters are inhibited. The delays are not
introduced in some control schemes, where a small circulating current is permitted during the
cross-over instants of the fundamental current only. The scheme is still recognized as the non-
circulating current operation since during a major portion of the output cycle, it operates in the
non-circulating current mode.
D P-converter
i0
Logic
D N-converter
Fig. 32.5 Converter group selection in non-circulating current scheme
The circuit is an essential part of the control scheme of a cyclo-converter with the non-
circulating mode of operation. The function is to ensure that only one converter operates at a
time depending upon the polarity of the current. The positive converter is operated, when the
load current is positive, and the negative converter is operated, when the load current is negative.
The converter group selection is not straight forward primarily due to non-ideal nature of the
output current waveform. Since the actual load voltage waveform itself is far from sinusoidal, the
load current is also non-sinusoidal. Depending upon load circuit parameters and converter pulse
number, the load current may become zero before the fundamental half-period. If the group
selection and blanking circuit were to operate at each current zero instant, it may cause erratic
switching of converters. The result of this is to further distort the output voltage. One possible
solution to this problem is to see that the blanking circuit operates at the zero crossing of the
fundamental current. The fundamental component of the load current is extracted, and the
converter bank selection is made to occur at the zero crossings of this fundamental component of
the current. There are, however, some operational difficulties, in the design of filter components
specially, when the cyclo-converter is required to operate over a range of the output frequency,
and with variable load. The filter, which operates satisfactorily over the desired range of
frequency, will have to be used. Thus, the envelope distortion of the output current and the
output voltage are reduced, and the possible steady state discontinuous conduction within the
fundamental period does not cause any erratic switching of converters.
Because of filters, certain amount of phase shift may be introduced between the zero
crossings of the fundamental output current and actual load current. In order to eliminate the
waveform distortion, certain amount of circulating current may be allowed to flow during this
short overlap period in some control schemes. The presence of circulating current is a must in
such a design. However, if no circulating current is permitted to flow, some distortion in the
output voltage is to be tolerated. This distortion arises due to the delays introduced at the zero
crossings of the load current to ensure turn-off of thyristors in the outgoing group before the
thyristors in the incoming group are turned on.

There may be other approaches, in one of which a closed loop control of the output voltage is
used to automatically select the converter banks. This is not described here, but may be studied
from the text books.
In this lesson − last one in this module, the complete control circuit used for three-phase to
three-phase cyclo-converter is discussed in detail. The functional blocks, with relevant circuits
and waveforms, are described, stating how the triggering signals for the thyristors are generated.
In the next, i.e. last module of the course on Power Electronics, the various types of dc to ac
converters, also known as inverters, with relevant points, will be presented.

Module
5
DC to AC Converters
Lesson
33
Introduction to Voltage
Source Inverters
(i) Identify the essential components of a voltage source inverter.

(ii) Explain the principle behind dc to ac conversion.
(iii) Identify the basic topology of single-phase and three-phase inverters and explain
its principle of operation.
(iv) Explain the gate drive circuit requirements of inverter switches.
The word ‘inverter’ in the context of power-electronics denotes a class of power conversion (or
power conditioning) circuits that operates from a dc voltage source or a dc current source and
converts it into ac voltage or current. The ‘inverter’ does reverse of what ac-to-dc ‘converter’
does (refer to ac to dc converters). Even though input to an inverter circuit is a dc source, it is
not uncommon to have this dc derived from an ac source such as utility ac supply. Thus, for
example, the primary source of input power may be utility ac voltage supply that is ‘converted’
to dc by an ac to dc converter and then ‘inverted’ back to ac using an inverter. Here, the final ac
output may be of a different frequency and magnitude than the input ac of the utility supply.
[The nomenclature ‘inverter’ is sometimes also used for ac to dc converter circuits if the
power flow direction is from dc to ac side. However in this lesson, irrespective of power
flow direction, ‘inverter’ is referred as a circuit that operates from a stiff dc source and
generates ac output. If the input dc is a voltage source, the inverter is called a voltage
source inverter (VSI). One can similarly think of a current source inverter (CSI), where the
input to the circuit is a current source. The VSI circuit has direct control over ‘output (ac)
voltage’ whereas the CSI directly controls ‘output (ac) current’. Shape of voltage
waveforms output by an ideal VSI should be independent of load connected at the output.]
The simplest dc voltage source for a VSI may be a battery bank, which may consist of several
cells in series-parallel combination. Solar photovoltaic cells can be another dc voltage source.
An ac voltage supply, after rectification into dc will also qualify as a dc voltage source. A
voltage source is called stiff, if the source voltage magnitude does not depend on load connected
to it. All voltage source inverters assume stiff voltage supply at the input.
Some examples where voltage source inverters are used are: uninterruptible power supply (UPS)
units, adjustable speed drives (ASD) for ac motors, electronic frequency changer circuits etc.
Most of us are also familiar with commercially available inverter units used in homes and offices
to power some essential ac loads in case the utility ac supply gets interrupted. In such inverter
units, battery supply is used as the input dc voltage source and the inverter circuit converts the dc
into ac voltage of desired frequency. The achievable magnitude of ac voltage is limited by the
magnitude of input (dc bus) voltage. In ordinary household inverters the battery voltage may be
just 12 volts and the inverter circuit may be capable of supplying ac voltage of around 10 volts
(rms) only. In such cases the inverter output voltage is stepped up using a transformer to meet the
load requirement of, say, 230 volts.
33.1 How to Get AC Output From DC Input Supply?

Figs. 33.1(a) and 33.1(b) show two schematic circuits, using transistor-switches, for generation
of ac voltage from dc input supply. In both the circuits, the transistors work in common emitter
configuration and are interconnected in push-pull manner. In order to have a single control signal

for the transistor switches, one transistor is of n-p-n type and the other of p-n-p type and their
emitters and bases are shorted as shown in the figures. Both circuits require a symmetrical
bipolar dc supply. Collector of n-p-n transistor is connected to positive dc supply (+E) and that
of p-n-p transistor is connected to negative dc supply of same magnitude (-E). Load, which has
been assumed resistive, is connected between the emitter shorting point and the power supply
ground.
In Fig. 33.1(a), the transistors work in active (amplifier) mode and a sinusoidal control voltage of
desired frequency is applied between the base and emitter points. When applied base signal is
positive, the p-n-p transistor is reverse biased and the n-p-n transistor conducts the load current.
Similarly for negative base voltage the p-n-p transistor conducts while n-p-n transistor remains
reverse biased. A suitable resistor in series with the base signal will limit the base current and
keep it sinusoidal provided the applied (sinusoidal) base signal magnitude is much higher than
the base to emitter conduction-voltage drop. Under the assumption of constant gain (hfe) of the
transistor over its working range, the load current can be seen to follow the applied base signal.
Fig. 33.2(a) shows a typical load voltage (in blue color) and base signal (green color) waveforms.
This particular figure also shows the switch power loss for n-p-n transistor (in brown color). The
other transistor will also be dissipating identical power during its conduction. The quantities in
Fig. 33.2(a) are in per unit magnitudes where the base values are input supply voltage (E) and the
load resistance (R). Accordingly the base magnitudes of current and power are E/R and E2/R
respectively. As can be seen, the power loss in switches is a considerable portion of circuit’s
input power and hence such circuits are unacceptable for large output power applications.
As against the amplifier circuit of Fig. 33.1(a), the circuit of Fig. 33.1(b) works in switched
mode. The conducting switch remains fully on having negligible on-state voltage drop and the
non-conducting switch remains fully off allowing no leakage current through it. The load voltage
waveform output by switched-mode circuit of Fig. 33.1(b) is rectangular with magnitude +E
when the n-p-n transistor is on and –E when p-n-p transistor is on. Fig. 33.2(b) shows one such
waveform (in pink color). The on and off durations of the two transistors are controlled so that (i)
the resulting rectangular waveform has no dc component (ii) has a fundamental (sinusoidal)
component of desired frequency and magnitude and (iii) the frequencies of unwanted harmonic
voltages are much higher than that of the fundamental component. The fundamental sine wave in
Fig. 33.2(b), shown in blue color, is identical to the sinusoidal output voltage of Fig. 33.2(a).
Both amplifier mode and switched mode circuits of Figs. 33.1(a) and 33.1(b) are capable of
producing ac voltages of controllable magnitude and frequency, however, the amplifier circuit is
not acceptable in power-electronic applications due to high switch power loss. On the other
hand, the switched mode circuit generates significant amount of unwanted harmonic voltages
along with the desired fundamental frequency voltage. As will be shown in some later lessons,
the frequency spectrum of these unwanted harmonics can be shifted towards high frequency by
adopting proper switching pattern. These high frequency voltage harmonics can easily be
blocked using small size filter and the resulting quality of load voltage can be made acceptable.

+E +E
S LOAD (R) LOAD (R)

* *
S
-E -E
Fig. 33.1 (a): A push-pull Fig. 33.1 (b): A push-pull
active amplifier circuit switched mode circuit

The magnitude, phase and frequency of the fundamental voltage waveform in Fig. 33.2(b) is
solely determined by the magnitude of supply voltage and the switching pattern of the push-pull
circuit shown in Fig. 33.1(b). Thus, as long as the transistors work in the switch-mode (fully on
or fully off), the output voltage is essentially load-independent.
33.2 What If The Load Is Not Resistive?

Circuit of Fig. 33.1(b) will not be able to output proper voltage waveform for a non-resistive load
for the reasons mentioned below.
Transistors used in the circuit of Fig. 33.1(b) are meant to carry only unidirectional current (from
collector to emitter) and thus if the upper (n-p-n) transistor is on, the current must enter the star
(*) marked terminal of the load and this same terminal will get connected to the positive dc
supply (+E), other load terminal being at ground potential. When n-p-n transistor turns off and p-
n-p type turns on, the load voltage and current polarities reverse simultaneously (p-n-p transistor
can only carry current coming out of star marked end of load). Such one to one matching
between the instantaneous polarities of load voltage and load current can be achieved only in
purely resistive loads. For a general load the instantaneous current polarity may be different from
instantaneous load-voltage polarity. As pointed out in section 33.1, the inverter switching-pattern
fixes the output waveform irrespective of the load. Thus the magnitude, phase and frequency of
the fundamental voltage output by a VSI is independent of the nature of load. Thus it turns out
that for a non-resistive load the switches in the circuit of Fig. 33.1(b) should be able to carry bi-
directional current and at the same time be controllable. [A mechanical switch realized using
an electromagnetic contactor is one example of the bi-directional current carrying
controllable switch. However electromagnetic contactors are not capable of operating at
high frequency, in the range of kilohertz, and may not be suitable for present application.]
If an anti-parallel diode is connected across each transistor switch, as shown in Fig. 33.3(a), the
combination can conduct a bi-directional current. Now the transistor in anti-parallel with the
diode may be considered as a single switch. [A major difference exists between this bi-
directional electronic switch and a bi-directional current carrying mechanical switch. The
mechanical switch can be subjected to bi-directional voltage. When off, the mechanical
switch can block both positive and negative voltage across its terminals. The electronic
switch of Fig. 33.3(a) can block only one polarity of voltage, the one that keeps the diode
reverse biased. Under this polarity of voltage the switch can remain off as long as the base
(or the gate) terminal is not given the turn-on signal. When applied voltage polarity is
reversed the diode starts conducting and so the switch is not able to block the flow of
reverse current.] In spite of unidirectional voltage blocking capability, the new electronic
switch (similar to the one shown in Fig. 33.3(a)) suffices for the inverter application as pointed
out in the following paragraphs.
The push-pull circuit operation is now revisited using bi-directional current carrying switches.
The modified circuit is shown in Fig. 33.3(b). It may be noted that both IGBT and BJT type
transistors, when bypassed by anti-parallel diode, qualify as bi-directional current carrying
switches. However, IGBT switch is controlled by gate voltage whereas the BJT

+E
Input /
SW1
Output Q1 D1
+ LOAD
Gate Analogous to
(control) Control S *
Q2 D2
_ SW2
Input /
Output -E
Fig. 33.3(a): Bi-directional controlled Fig. 33.3 (b): Modified push-pull circuit
switch
switch is controlled using base current. [IGBT switches are easier to use, are much faster and
are available in higher voltage and current ratings. As a result BJT switches are becoming
obsolete.] In the circuit of Fig. 33.3(b), n-p-n transistor (Q1) together with diode (D1) constitutes
the upper switch (SW1). Similarly lower switch (SW2) consists of p-n-p transistor (Q2) in anti-
parallel with diode (D2). By applying positive base-to-emitter voltage of suitable magnitude to
transistor ‘Q1’, the upper switch is turned on. Once the upper switch (diode ‘D1’or transistor
‘Q1’) is conducting star end of load is at ‘+E’ potential and diode ‘D2’ of lower switch gets
reverse biased. Transistor ‘Q2’ is also reverse biased due to application of positive base voltage
to the transistors. Thus while switch ‘SW1’is conducting current, switch ‘SW2’ is off and is
blocking voltage of magnitude ‘2E’. Similarly when applied base voltage to the transistors is
made negative, ‘Q1’ is reverse biased and ‘Q2’ is forward biased. This results in ‘SW1’ turning
off and ‘SW2’ turning on. Now ‘SW1’ blocks a voltage of magnitude ‘2E’.
It may be interesting to see how diodes follow the switching command given to the transistor
part of the switches. To illustrate this point some details of circuit operation with an inductive
load, consisting of a resistor and an inductor in series, is considered. As is well known, current
through such loads cannot change abruptly. The electrical inertial time constant of the load,
given by its L (inductance) / R (resistance) ratio, may in general be large compared to the chosen
switching time period of the transistor switches. Thus the transistors ‘Q1’ and ‘Q2’ may turn-on
and turn-off several times before the load current direction changes. Let us consider the time
instant when instantaneous load current is entering the star end of the load in Fig. 33.3(b). Now
with the assumed load current direction when ‘Q1’ is given turn-on signal current flows from
positive dc supply, through transistor ‘Q1’, to load. Next, when ‘Q1’ is turned-off and ‘Q2’ is
turned on (but load current direction remaining unchanged) the load current finds its path
through diode of lower switch (D2). Whether ‘D2’ or ‘Q2’ conducts, voltage drop across ‘SW2’ is
virtually zero and it can be considered as a closed or a fully-on switch. In the following
switching cycle when ‘Q1’ is turned on again (load current direction still unchanged) the load
current path reverts back from ‘D2’ to ‘Q1’. It may not be difficult to see how this happens.
While current flowed through ‘D2’ the load circuit got connected to negative emf (-E) of the
supply. When ‘Q1’ conducts the positive (+E) emf supports the load current. The natural choice
for load current is to move from ‘D2’ to ‘Q1’. In fact turning on of ‘Q1’ will make ‘D2’ reverse
biased. The reader may repeat a similar exercise when the instantaneous load current comes out
of the star end of load. Thus it will be evident that diodes do not need a separate command to
turn on and off. Irrespective of the load current direction, turning on of ‘Q1’ makes ‘SW1’ on and
similarly turning off of ‘Q1’ (with simultaneous turn-on of ‘Q2’) makes ‘SW2’on. ‘Q1’ and ‘Q2’
are turned on in a complementary manner. It may not be difficult to see that the circuit of Fig.
33.3(b) will work satisfactorily for a purely resistive load and a series connected resistor-
capacitor load too.
The push-pull circuit of Fig. 33.3(b) has some technical demerits that have been discussed
below.
First, it needs a bipolar dc supply with identical magnitudes of positive and negative supply
voltages. For practical reasons it would have been simpler if only one (uni-polar) dc source was
required. In fact some circuit topologies realize a bi-polar dc supply by splitting the single dc
voltage-source through capacitive potential divider arrangement. [A resistive potential divider
will be terribly inefficient.] Two identical capacitors of large magnitude are put across the dc
supply and the junction point of the capacitors is used as the neutral (ground) point of the bi-
polar dc supply. Fig. 33.3(c) shows one such circuit where a single dc supply has been split in
two halves. In such circuits the voltages across the two capacitors may not remain exactly
balanced due to mismatch in the loading patterns or mismatch in leakage currents of the
individual capacitors. Also, unless the capacitors are of very large magnitude, there may be
significant ripple in the capacitor voltages, especially at low switching frequencies. The
requirement of splitting a single dc source is eliminated if a full bridge circuit, as mentioned in
the next section, is used.
The second demerit of the push-pull circuit shown in Fig. 33.3(b) is the requirement of two
different kinds of transistors, one n-p-n type and the other p-n-p type. The switching speeds of n-
p-n and p-n-p transistors are widely different unless they are produced carefully as matched
pairs. In power electronic applications, n-p-n transistors are preferred as they can operate at
higher switching frequencies. Similarly n-channel MOSFETs and IGBTs are preferred over their
p-channel counterparts. The difficulty in using two n-p-n transistors in the above discussed push-
pull circuit is that they can no longer have a common base and a common emitter point and thus
it won’t be possible to have a single base drive signal for controlling both of them. The base
signals for the individual transistors will then need to be separate and isolated from each other.
The difficulty in providing isolated base signals for the two transistors is, often, more than
compensated by the improved capability of the circuit that uses both n-p-n transistors or n-
channel IGBTs. The circuit in Fig. 33.3(c) shows identical transistors (n-channel IGBTs) for both
upper and lower switches. The gate drive signals of the two transistors (IGBTs) now need to be
different and isolated as the two emitter points are at different potentials. The circuit in Fig.
33.3(c) is better known as a half bridge inverter.

P
+ Q1 D1
_ 0.5Edc
+
Edc
_ O LOAD A
+ Q2 D2
_ 0.5Edc
N
Fig. 33.3(c): Topology of a 1-phase half bridge VSI
33.3 General Structure of Voltage Source Inverters

Figs. 33.4 (a) and 33.4(b) show the typical power-circuit topologies of a single-phase and a
three-phase voltage source inverter respectively. These topologies require only a single dc
source and for medium output power applications the preferred devices are n-channel IGBTs.
‘Edc’ is the input dc supply and a large dc link capacitor (Cdc) is put across the supply terminals.
Capacitors and switches are connected to dc bus using short leads to minimize the stray
inductance between the capacitor and the inverter switches. Needless to say that physical layout
of positive and negative bus lines is also important to limit stray inductances. Q1, Q2, Q3 etc. are
fast and controllable switches. D1, D2, D3 etc. are fast recovery diodes connected in anti-parallel
with the switches. ‘A’, ‘B’ and ‘C’ are output terminals of the inverter that get connected to the
ac load. A three-phase inverter has three load-phase terminals whereas a single-phase inverter
has only one pair of load terminals.
The current supplied by the dc bus to the inverter switches is referred as dc link current and has
been shown as ‘idc’ in Figs 33.4(a) and 33.4(b). The magnitude of dc link current often changes
in step (and some times its direction also changes) as the inverter switches are turned on and off.
The step change in instantaneous dc link current occurs even if the ac load at the inverter output
is drawing steady power. However, average magnitude of the dc link current remains positive if
net power-flow is from dc bus to ac load. The net power-flow direction reverses if the ac load
connected to the inverter is regenerating. Under regeneration, the mean magnitude of dc link
current is negative. [The dc link current may conceptually be decomposed into its dc and ac
components. The individual roles of the ‘dc voltage source’ and the ‘dc link capacitor’ may
be clearly seen with respect to the dc and ac components of the dc link current. For the dc
component of current the capacitor acts like open circuit. As expected, under steady state,
the capacitor does not supply any dc current. The dc part of bus current is supplied solely
by the dc source. A practical dc voltage source may have some resistance as well as some
inductance in series with its internal emf. For dc component of bus current, the source
voltage appears in series with its internal resistance (effect of source inductance is not felt).
But for ac component of current, the internal dc emf of source appears as short and its
series impedance (resistance in series with inductance) appears in parallel with the dc-link

capacitor. Thus the ac component of current gets divided into these two parallel paths.
However, the high frequency component of ac current mainly flows through the capacitor,
as the capacitive impedance is lower at high frequencies. The step change in dc link current
is associated with significant amount of high frequency components of current that
essentially finds its path through the capacitor.]
For an ideal input (dc) supply, with no series impedance, the dc link capacitor does not have any
role. However a practical voltage supply may have considerable amount of output impedance.
The supply line impedance, if not bypassed by a sufficiently large dc link capacitor, may cause
considerable voltage spike at the dc bus during inverter operation. This may result in
deterioration of output voltage quality, it may also cause malfunction of the inverter switches as
the bus voltage appears across the non-conducting switches of the inverter. Also, in the absence
of dc link capacitor, the series inductance of the supply line will prevent quick build up or fall of
current through it and the circuit behaves differently from the ideal VSI where the dc voltage
supply is supposed to allow rise and fall in current as per the demand of the inverter circuit.
[It may not be possible to reduce supply line inductance below certain limit. Most dc
supplies will inherently have rather significant series inductance, for example a
conventional dc generator will have considerable armature inductance in series with the
armature emf. Similarly, if the dc supply is derived after rectifying ac voltage, the ac
supply line inductance will prevent quick change in rectifier output current. The effect of
ac line inductance is reflected on the dc side as well, unless this inductance is effectively
bypassed by the dc side capacitor. Even the connecting leads from the dc source to the
inverter dc bus may contribute significantly to the supply line inductance in case the lead
lengths are large and circuit lay out is poor. It may be mentioned here that an inductance,
in series with the dc supply, may at times be welcome. The reason being that for some types
of dc sources, like batteries, it is detrimental to carry high frequency ripple current. For
such cases it is advantageous if the dc source has some series inductance. Due to series
inductance of the source, the high frequency ripple will prefer to flow through the dc link
capacitor and thus relieve the dc source.]
The dc link capacitor should be put very close to the switches so that it provides a low
impedance path to the high frequency component of the switch currents. The capacitor itself
must be of good quality with very low equivalent series resistor (ESR) and equivalent series
inductor (ESL). The length of leads that interconnect switches and diodes to the dc bus must also
be minimum to avoid insertion of significant amount of stray inductances in the circuit. The
overall layout of the power circuit has a significant effect over the performance of the inverter
circuit.

idc idc
Q1 D1 Q3 D3 D1 D3 D5
Q1 Q3 Q5
Edc Edc
+ Cdc + Cdc A
_ _ B C
A LOAD B
Q2 D2 Q4 D4 D2 D4 D6
Q2 Q4 Q6
Fig. 33.4(a): Topology of a 1-phase VSI Fig. 33.4(b): Topology of a 3-phase VSI
[One of the thumb rules for good circuit layout is to put the conductor pairs carrying same
magnitude but opposite direction of currents close by, the minimum distance between them
being decided only by their voltage isolation requirement. Thus the positive and negative
terminals of the dc bus should run close by. A twisted wire pair may be an example of two
closely running wires.]
The details of the inverter circuits shown in Figs. 33.4(a) and 33.4(b) are discussed in later
lessons. However it may be mentioned here that these circuits are essentially extension of the
half bridge circuit shown in Fig. 33.3(c). For example, the single-phase bridge circuit of Fig.
33.4(a) may be thought of as two half-bridge circuits sharing the same dc bus. Thus the single
phase ‘full-bridge’ (often, simply called as ‘bridge’) circuit has two legs of switches, each leg
consisting of an upper switch and a lower switch. Junction point of the upper and lower switches
is the output point of that particular leg. Voltage between output point of legs and the mid-
potential of the dc bus is called as ‘pole voltage’ referred to the mid potential of the dc bus. One
may think of pole voltage referred to negative bus or referred to positive bus too but unless
otherwise mentioned pole voltages are assumed to be referred to the mid-potential of the dc bus.
The two pole voltages of the single-phase bridge inverter generally have same magnitude and
frequency but their phases are 1800 apart. Thus the load connected between these two pole
outputs (between points ‘A’ and ‘B’) will have a voltage equal to twice the magnitude of the
individual pole voltage. The pole voltages of the 3-phase inverter bridge, shown in Fig. 33.4(b),
are phase apart by 1200 each.
33.4 Need For Isolated Gate-Control Signals For The Switches

As already mentioned the switches in bridge configurations of inverters, as in Figs. 33.3(c),
33.4(a) and 33.4(b), need to be provided with isolated gate (or base) drive signals. The individual
control signal for the switches needs to be provided across the gate (base) and source (or emitter)
terminals of the particular switch. The gate control signals are low voltage signals referred to the
source (emitter) terminal of the switch. For n-channel IGBT and MOSFET switches, when gate
to source voltage is more than threshold voltage for turn-on, the switch turns on and when it is
less than threshold voltage the switch turns off. The threshold voltage is generally of the order of
+5 volts but for quicker switching the turn-on gate voltage magnitude is kept around +15 volts

where as turn-off gate voltage is zero or little negative (around –5 volts). It is to be remembered
that the two switches of an inverter-leg are controlled in a complementary manner. When the
upper switch of any leg is ‘on’, the corresponding lower switch remains ‘off’ and vice-versa.
When a switch is ‘on’ its emitter and collector terminals are virtually shorted. Thus with upper
switch ‘on’, the emitter of the upper switch is at positive dc bus potential. Similarly with lower
switch ‘on’, the emitter of upper switch of that leg is virtually at the negative dc bus potential.
Emitters of all the lower switches are solidly connected to the negative line of the dc bus. Since
gate control signals are applied with respect to the emitter terminals of the switches, the gate
voltages of all the upper switches must be floating with respect to the dc bus line potentials. This
calls for isolation between the gate control signals of upper switches and between upper and
lower switches. Only the emitters of lower switches of all the legs are at the same potential (since
all of them are solidly connected to the negative dc bus) and hence the gate control signals of
lower switches need not be isolated among themselves. As should be clear from the above
discussion, the isolation provided between upper and lower switches must withstand a peak
voltage stress equal to dc bus voltage. Gate-signal isolation for inverter switches is generally
achieved by means of optical-isolator (opto-isolator) circuits. Fig.33.5 shows a typical opto-
isolator circuit. The circuit makes use of a commercially available opto-coupler IC, shown within
dotted lines in the figure. Input stage of the IC is a light emitting diode (LED) that emits light
when forward biased. The light output of the LED falls on reverse biased junction of an optical
diode. The LED and the photo-diode are suitably positioned inside the opto-coupler chip to
ensure that the light emitted by the LED falls on the photo-diode junction. The gate control
pulses for the switch are applied to the input LED through a current limiting resistor of
appropriate magnitude. These gate pulses, generated by the gate logic circuit, are essentially in
the digital form. A high level of the gate signal may be taken as ‘on’ command and a low level
(at ground level) may be taken as ‘off’ command. Under this assumption, the cathode of the LED
is connected to the ground point of the gate-logic card and anode is fed with the logic card
output. The circuit on the output (photo-diode) side is connected to a floating dc power supply,
as shown in Fig. 33.5. The control (logic card) supply ground is isolated from the floating-supply
ground of the output. In the figure the two grounds have been shown by two different symbols.
The schematic connection shown in the figure indicates that the photo-diode is reverse biased. A
resistor in series with the diode indicates the magnitude of the reverse leakage current of the
diode. When input signal to LED is high, LED conducts and the emitted light falls on the reverse
biased p-n junction. Irradiation of light causes generation of significant number of electron-hole
pairs in the depletion region of the reverse biased diode. As a result magnitude of reverse leakage
current of the diode increases appreciably. The resistor connected in series with the photo-diode
now has higher voltage drop due to the increased leakage current. A signal comparator circuit
senses this condition and outputs a high level signal, which is amplified before being output.
Thus an isolated and amplified gate signal is obtained and may directly be connected to the gate
terminal of the switch (often a small series resistor, as suggested by the switch manufacturer, is
put between the output signal and the gate terminal of the switch).

+VCC (floating)
Photo-diode
Signal
L Output
comparator and
E
power amplifier
D
circuit
Control Floating
Ground Ground
Fig.33.5: A schematic opto-isolator circuit
33.5 Classification of Voltage Source Inverters

Voltage source inverters can be classified according to different criterions. They can be classified
according to number of phases they output. Accordingly there are single-phase or three-phase
inverters depending on whether they output single or three-phase voltages. It is also possible to
have inverters with two or five or any other number of output phases. Inverters can also be
classified according to their ability in controlling the magnitude of output parameters like,
frequency, voltage, harmonic content etc. Some inverters can output only fixed magnitude
(though variable frequency) voltages whereas some others are capable of both variable voltage,
variable frequency (VVVF) output. Output of some voltage source inverters is corrupted by
significant amount of many low order harmonics like 3rd, 5th, 7th, 11th, 13th order of the desired
(fundamental) frequency voltage. Some other inverters may be free from low order harmonics
but may still be corrupted by some high order harmonics. Inverters used for ac motor drive
applications are expected to have less of low order harmonics in the output voltage waveform,
even if it is at the cost of increased high order harmonics. Higher order harmonic voltage
distortions are, in most ac motor loads, filtered away by the inductive nature of the load itself.
Inverters may also be classified according to their topologies. Some inverter topologies are
suitable for low and medium voltage ratings whereas some others are more suitable for higher
voltage applications. The inverters shown in Figs. 33.3(c), 33.4(a) and 33.4(b) are two level
inverters as the pole voltages may acquire either positive dc bus or negative dc bus potential. For
higher voltage applications it may not be uncommon to have three level or five level inverters.
Quiz Problems
1. A large capacitor, put across dc bus of a voltage source inverter, is intended to:
(a) allow a low impedance path to the high frequency component of dc link current.
(b) to minimize high frequency current ripple through the ideal dc source.
(c) to maintain a constant dc link current.
(d) to protect against switch failure.
2. A diode in anti-parallel with the controlled switch, like IGBT, is used in VSI to:
(a) prevent reversal of dc link current.

(b) allow a non-unity power factor load at the output.
(c) protect the circuit against accidental reversal of dc bus polarity.
(d) none of the above.
3. The inverter switches work in fully-on or fully-off mode to achieve:
(a) easier gate control circuit for the switching devices.
(b) minimum distortion in the output voltage waveform.
(c) reduced losses in the switches.
(d) satisfactory operation for non-resistive load at the output.
4. Gate (base) signals to the VSI switches, using n-channel IGBTs, need to be isolated to
allow:
(a) protection of switches against short at the inverter output terminals.
(b) switches to be connected in bridge fashion.
(c) lower losses in the gate drive circuit.
(d) a dc link voltage higher than the switch voltage rating.
(Answers to the quiz problems: 1-a, 2-b, 3-c, 4-b)

Module
5
DC to AC Converters
Lesson
34
Analysis of 1-Phase,
Square - Wave Voltage
Source Inverter
(i) Explain the operating principle of a single-phase square wave inverter.
(ii) Compare the performance of single-phase half-bridge and full-bridge inverters.
(iii) Do harmonic analysis of load voltage and load current output by a single-phase
inverter.
(iv) Decide on voltage and current ratings of inverter switches.
Voltage source inverters (VSI) have been introduced in Lesson-33. A single-phase square wave
type voltage source inverter produces square shaped output voltage for a single-phase load. Such
inverters have very simple control logic and the power switches need to operate at much lower
frequencies compared to switches in some other types of inverters, discussed in later lessons. The
first generation inverters, using thyristor switches, were almost invariably square wave inverters
because thyristor switches could be switched on and off only a few hundred times in a second. In
contrast, the present day switches like IGBTs are much faster and used at switching frequencies
of several kilohertz. As pointed out in Lesson-26, single-phase inverters mostly use half bridge
or full bridge topologies. Power circuits of these topologies are redrawn in Figs. 34.1(a) and
34.1(b) for further discussions.
P P idc
Sw1 Sw3
+ Sw1
C_ 0.5Edc
Edc
Edc
+ + Cdc
_ O LOAD A _ A LOAD B
+
C_ 0.5Edc
Sw2 Sw2 Sw4

N N
Fig. 34.1(a): A 1-phase half bridge VSI Fig. 34.1(b): A 1-phase full-bridge VSI
In this lesson, both the above topologies are analyzed under the assumption of ideal circuit
conditions. Accordingly, it is assumed that the input dc voltage (Edc) is constant and the switches
are lossless. In half bridge topology the input dc voltage is split in two equal parts through an
ideal and loss-less capacitive potential divider. The half bridge topology consists of one leg (one
pole) of switches whereas the full bridge topology has two such legs. Each leg of the inverter
consists of two series connected electronic switches shown within dotted lines in the figures.
Each of these switches consists of an IGBT type controlled switch across which an uncontrolled
diode is put in anti-parallel manner. These switches are capable of conducting bi-directional
current but they need to block only one polarity of voltage. The junction point of the switches in
each leg of the inverter serves as one output point for the load.
In half bridge topology the single-phase load is connected between the mid-point of the input dc
supply and the junction point of the two switches (in Fig. 34.1(a) these points are marked as ‘O’
and ‘A’ respectively). For ease of understanding, the switches Sw1 and Sw2 may be assumed to

be controlled mechanical switches that open and close in response to the switch control signal. In
fact in lesson-33 (section 33.2) it has been shown that the actual electronic switches mimic the
function of the mechanical switches. Now, if the switches Sw1 and Sw2 are turned on alternately
with duty ratio of each switch kept equal to 0.5, the load voltage (VAO) will be square wave with
a peak-to-peak magnitude equal to input dc voltage (Edc). Fig. 34.2(a) shows a typical load
voltage waveform output by the half bridge inverter. VAO acquires a magnitude of +0.5 Edc when
Sw1 is on and the magnitude reverses to -0.5 Edc when Sw2 is turned on. Fig. 24.2 also shows
the fundamental frequency component of the square wave voltage, its peak-to-peak magnitude
being equal to 4 Edc . The two switches of the inverter leg are turned on in a complementary
π
manner. For a general load, the switches should neither be simultaneously on nor be
simultaneously off. Simultaneous turn-on of both the switches will amount to short circuit across
the dc bus and will cause the switch currents to rise rapidly. For an inductive load, containing an
inductance in series, one of the switches must always conduct to maintain continuity of load
current. In Lesson-33 (section 33.2) a case of inductive load has been considered and it has been
shown that the load current may not change abruptly even though the switching frequency is
very high. Such a situation, as explained in lesson-33, demands that the switches must have bi-
directional current carrying capability.
34.1 Harmonic Analysis of The Load Voltage And Load Current

Waveforms
The load voltage waveform shown in Fig. 34.2(a) can be mathematically described in terms of its
Fourier’s components as:
2E
VAO = ∑ nπdc sin(nwt ) ……………………………………… (34.1)
n =1,3,5,7,...,∞
,where ‘n’ is the harmonic order and w is the frequency (‘f’) of the square wave. ‘f’ also
2π
happens to be the switching frequency of the inverter switches. As can be seen from the
expression of Eqn. 34.1, the square wave load voltage consists of all the odd harmonics and their
magnitudes are inversely proportional to their harmonic order. Accordingly, the fundamental

2
frequency component has a peak magnitude of Edc and the nth harmonic voltage (n being odd
π
2
integer) has a peak magnitude of Edc . The magnitudes of very high order harmonic voltages
nπ
become negligibly small. In most applications, only the fundamental component in load voltage
is of practical use and the other higher order harmonics are undesirable distortions. Many of the
practical loads are inductive with inherent low pass filter type characteristics. The current
waveforms in such loads have less higher order harmonic distortion than the corresponding
distortion in the square-wave voltage waveform. A simple time domain analysis of the load
current for a series connected R-L load has been presented below to corroborate this fact. Later,
for comparison, frequency domain analysis of the same load current has also been done.
34.1.1 Time Domain Analysis

The time domain analysis of the steady state current waveform for a R-L load has been presented
here. Under steady state the load current waveform in a particular output cycle will repeat in
successive cycles and hence only one square wave period has been considered. Let t=0 be the
instant when the positive half cycle of the square wave starts and let I0 be the load current at this
instant. The negative half cycle of square wave starts at t=0.5T and extends up to T. The circuit
equation valid during the positive half cycle of voltage can be written as below:
di
Ri + L = 0.5Edc , for 0 < t < 0.5T ………………………..………….(34.2)
dt
Similarly the equation for the negative half cycle can be written as
di
Ri + L = −0.5 Edc , for 0.5T < t < T ………………………………….(34.3)
dt
, where T (=1/f) is the time period of the square wave.
The instantaneous current ‘i’ during the first half of square wave may be obtained by solving
Eqn.(34.2) and putting the initial value of current as I0.
−t −t
(1 − e τ ) + I 0 e τ
0.5 Edc
Accordingly, i (t ) = for 0 < t < 0.5T ……………..(34.4)
R
, where τ= L/R is the time constant of the R-L load.
The current at the end of the positive half cycle becomes the starting current for the negative half
cycle.
−T −T
(1 − e 2τ ) + I 0 e 2τ . The
0.5 Edc
Thus the next half cycle starts with an initial current =
R
circuit equation for the next half cycle may now be written as
T T
−(t − ) −(t − )
2 ⎡ 0.5E −T −T ⎤ 2
i(t ) = −
0.5Edc
(1 − e τ )+⎢ dc
(1 − e 2τ ) + I 0e 2τ ⎥ e τ for 0.5T <t< T
R ⎢⎣ R ⎥⎦
Simplifying the above equation one gets:

T
−(t − )
0.5 Edc −t −t E 2
i (t ) = − (1 + e τ ) + I 0 e τ + dc e τ , for 0.5T < t < T …….(34.5)
R R
Under steady state, the instantaneous magnitude of inductive load current at the end of a periodic
cycle must equal the current at the start of the cycle. Thus putting t=T in Eqn. (34.5), one gets the
expression for I0 as,
0.5Edc −T −T E −T
I0 = − (1 + e τ ) + I 0 e τ + dc e 2τ
R R
⎛ −T ⎞ 0.5E −T E ⎛ −T ⎞
or, I 0 ⎜1 − e τ ⎟ = dc
(1 − e τ ) + dc ⎜ e 2τ − 1⎟
⎜ ⎟ R R ⎜ ⎟
⎝ ⎠ ⎝ ⎠
⎛ ⎞ ⎡ −T ⎤
0.5Edc Edc ⎜ 1 ⎟ 0.5Edc ⎢1 − e 2τ ⎥
or, I 0 = − ⎟=− R ⎢ −T ⎥
………….(34.6)
R R ⎜⎜ −T ⎟ ⎢ ⎥
⎝ 1 + e 2τ ⎠ ⎣1 + e
2τ
⎦
Substituting the above expression for I0 in Eqn. (34.4) one gets,
⎡ −T −t ⎤
0.5 Edc ⎢1 + e 2τ − 2e τ ⎥
i(t ) = ⎥ , for 0 < t < 0.5T ………..………..(34.7)
R ⎢⎢ −T
⎥
+ 2τ
⎣ 1 e ⎦
It may be noted from Eqn. (34.7) that the load current at the end of the positive half cycle of
square wave (at t=0.5T) simply turns out to be –I0. This is expected from the symmetry of the
load voltage waveform. Load current expression for the negative half cycle of square wave can
similarly be calculated by substituting for I0 in Eqn. (34.5). Accordingly,
⎡ T ⎤
⎢ −(t − ) ⎥
⎢ 2 ⎥
0.5 Edc Edc ⎢ e τ
i (t ) = − + ⎥ , for 0.5T < t < T
R R ⎢⎛ −T ⎞ ⎥
⎢ ⎜ 1 + e 2τ ⎟ ⎥
⎢⎜ ⎟ ⎥
⎣⎝ ⎠ ⎦
⎡ T ⎤
⎢ −(t − ) ⎥
−T 2
0.5 Edc ⎢1 + e 2τ − 2e τ ⎥
or, i (t ) = − ⎢ ⎥ , for 0.5T < t < T ............... (34.8)
R ⎢ −T ⎥
⎢ 1 + e 2τ ⎥
⎢ ⎥
⎣ ⎦

The current expressions given by Eqns. (34.7) and (34.8) have been plotted in Figs. 34.2(b) to
34.2(e) for different time constants of the R-L load. The current waveforms have been
E
normalized against a base current of 0.5 dc . The square wave voltage waveform, normalized
R
against a base voltage of 0.5Edc has also been plotted together with the current waveforms. It can
be seen that the load current waveform repeats at fundamental frequency and the higher order
harmonic distortions reduce as the load becomes more inductive. For L/R ratio of 2, the 3rd order
harmonic distortion in the load current together with its fundamental component has been shown
in Fig. 34.2(e). In this case, it can be seen that the relative harmonic distortion in load current
waveform is much lower than that of the voltage waveform shown in Fig. 34.2(a). The basis for
calculating the magnitude of different harmonic components of load current waveform has been
shown in the next subsection that deals with frequency domain analysis.
34.1.2 Frequency Domain Analysis

The square shape load voltage may be taken as superposition of different harmonic voltages
described by Eqn. 34.1. The load current may similarly be taken as superposition of harmonic
currents produced by the different harmonic voltages. The load current may be expressed in
terms of these harmonic currents. To illustrate this the series connected R-L load has once again
been considered here. First the expressions for different harmonic components of load current are
calculated in terms of load parameters: R and L/R (or τ) and inverter parameters: dc link voltage
(Edc) and time period of square wave (T).

For the fundamental harmonic frequency the load impedance (Z1) and load power factor angle
(φ1) can be calculated to be
⎛ 2π L ⎞
R 2 + ( 4π L
2 2
Z1 = 2) and φ1 = tan −1 ⎜ ⎟ ……….…….(34.9)
T ⎝ TR ⎠
The load impedance and load power factor angle for the nth harmonic component (Zn and φn
respectively) will similarly be given by,
⎛ 2π nL ⎞
R 2 + (4π n L
2 2 2
Zn = 2) and φn = tan −1 ⎜ ⎟ …….…….(34.10)
T ⎝ TR ⎠
The fundamental and nth harmonic component of load current, (Iload)1 and (Iload)n respectively, can
be found to be
2 Edc 2 Edc
(Iload)1 = sin( wt − Φ1 ) and (Iload)n = sin(nwt − Φ n ) ………(34.11)
π Z1 nπ Z n
The algebraic summation of the individual harmonic components of current will result in the
following expression for load current.
2 Edc
I Load = ∑ sin(nwt − Φ n ) ……………………………….(34.12)
n =1,3,5,7,...,∞ nπ Z n
From Eqns. 34.10 and 34.12 it may be seen that the contribution to load current from very higher
order harmonics become negligible and hence the infinite series based expression for load
current may be terminated beyond certain values of harmonic order ‘n’. For L/R ratio = 2T, the
individual harmonic components of load current normalized against a base current of
0.5 Edc
have been calculated below:
R
4
(Iload)1,normalized = sin( wt − tan −1 4π ) = 0.1sin( wt − 1.491)
π 1 + 16π 2
4
(Iload)3,normalized = sin(3wt − tan −1 12π ) = 0.011sin(3wt − 1.544)
3π 1 + 144π 2
4
5π 1 + 400π 2
4
(Iload)7,normalized = sin(7 wt − tan −1 28π ) = 0.002sin(7 wt − 1.559)
7π 1 + 784π 2
4
11π 1 + 1936π 2

It may be concluded that for L/R = 2T, the contribution to load current from 13th and higher
order harmonics are less than 1% of the fundamental component and hence they may be
neglected without any significant loss of accuracy.
Fig. 34.2(f) shows the load voltage and algebraic summation of the first five dominant harmonics
(fundamental, 3rd, 5th, 7th and 11th) in the load current, the expressions for which have been given
above. In Fig. 34.2(g) the load current waveforms of Fig. 34.2(e) and 34.2(f) have been
superimposed for comparison. It may be seen that the load current waveform of Fig. 34.2(f)
calculated using truncated series of the frequency domain analysis very nearly matches with the
exact waveform of Fig. 34.2(e), calculated using time domain analysis.
34.2 Analysis Of The Single-Phase Full Bridge Inverter

Single-phase half bridge inverter has already been described above. The single-phase full bridge
circuit (Fig. 34.1(b)) can be thought of as two half bridge circuits sharing the same dc bus. The
full bridge circuit will have two pole-voltages (VAO and VBO), which are similar to the pole
voltage VAO of the half bridge circuit. Both VAO and VBO of the full bridge circuit are square
waves but they will, in general, have some phase difference. Fig. 34.3 shows these pole voltages
staggered in time by ‘t’ seconds. It may be more convenient to talk in terms of the phase
displacement angle ‘Φ’ defined as below:
t
Φ = (2π ) Radians.……………………………….(34.13)
T
, where ‘t’ is the time by which the two pole voltages are staggered and ‘T’ is the time period of
the square wave pole voltages.
The pole voltage VAO of the full bridge inverter may again be written as in Eqn. 34.1, used
earlier for the half bridge inverter. Taking the phase shift angle ‘Φ’ into account, the pole-B
voltage may be written as
2E
VBO = ∑ nπdc sin n(wt − Φ) ………………………………………(34.14)
n =1,3,5,7,...,∞
Difference of VAO and VBO gives the line voltage VAB. In full bridge inverter the single phase
load is connected between points ‘A’ and ‘B’ and the voltage of interest is the load voltage VAB.
Taking difference of the voltage expressions given by Eqns. 34.1 and 34.14, one gets
2E
VAB = ∑ nπdc [sin nwt − sin n(wt − Φ)] ………………………………………(34.15)
n =1,3,5,7,...,∞

The fundamental component of VAB may be written as
2 Edc 4E Φ Φ
VAB ,1 = [sin wt − sin( wt − Φ)] = dc cos( wt − ) sin ……………………...(34.16)
π π 2 2
The nth harmonic component in VAB may similarly be written as
2 Edc 4E Φ nΦ
VAB ,n = [sin nwt − sin n( wt − Φ)] = dc cos n( wt − ) sin ………….……(34.17)
nπ nπ 2 2
From Eqn. 34.16, the rms magnitude of the fundamental component of load voltage may be
written as
Φ
(VAB ,1 ) rms = 0.9 Edc sin …………………………………………...……………….(34.18)
2
The rms magnitude of load voltage can be changed from zero to a peak magnitude of 0.9 Edc .
The peak load voltage magnitude corresponds to Φ = 180 degrees and the load voltage will be
zero for Φ = 00. For Φ = 180 degrees, the load voltage waveform is once again square wave of
time period T and instantaneous magnitude E.
As the phase shift angle changes from zero to 1800 the width of voltage pulse in the load voltage
waveform increases. Thus the fundamental voltage magnitude is controlled by pulse-width
modulation.
Also, from Eqns. 34.17 and 34.1 it may be seen that the line voltage distortion due to higher
order harmonics for pulse width modulated waveform (except for Φ = 1800) is less than the
corresponding distortion in the square wave pole voltage. In fact, for some values of phase shift
angle (Φ) many of the harmonic voltage magnitudes will drastically reduce or may even get
eliminated from the load voltage. For example, for Φ = 600 the load voltage will be free from 3rd
and multiples of third harmonic.

34.3 Voltage And Current Ratings Of Inverter Switches
Switches in each leg of the inverter operate in a complementary manner. When upper switch of a
leg is on the lower switch will need to block the entire dc bus voltage and vice versa. Thus the
switches must be rated to block the worst-case instantaneous magnitude of dc bus voltage. In
practical inverters the switch voltage ratings are taken to be somewhat higher than the worst-case
dc voltage to account for stray voltages produced across stray inductances, the turn-on transient
voltage of a power diode etc. For a well laid out circuit a 50% margin over the dc-bus voltage
may be the optimum switch voltage rating. Each switch of the inverter carries load current during
half of the current cycle. Hence the switches must be rated to withstand the peak magnitude of
instantaneous load current. The semiconductor switches have very small thermal time constant
and they cannot withstand overheating for more than a few milli seconds. Thus even though the
load current passes through the switches only in alternate half cycles, the thermal limit may be
reached during half cycle of current itself. It may be pointed out that each inverter switch
consists of a controlled switch in anti-parallel with a diode. The distribution of current between
the diode and the controlled switch will depend on the load power factor at the operating
frequency. In general both diode as well as the controlled switch should be rated to carry the
peak load current.
34.4 Applications Of Square Wave Inverter

The square wave voltage-source inverter discussed in this lesson finds application in many low
cost ac motor drives, uninterruptible power supply units and in circuits utilizing electrical
resonance between an inductor and a capacitor. Some examples of circuits utilizing resonance
phenomenon are induction heating units and electronic ballasts for fluorescent lamps.
Quiz Problems
1. A single-phase full bridge inverter with square wave pole voltages is connected to a dc
input voltage of 600 volts. What maximum rms load voltage can be output by the
inverter? How much will be the corresponding rms magnitude of 3rd harmonic voltage
(a) Approximately 270 volts of fundamental and 30 volts of 3rd harmonic voltage
(b) Approx. 480 volts fundamental and 160 volts of 3rd harmonic voltage
(c) Approx. 540 volts fundamental and 180 volts of 3rd harmonic voltage
(d) Approx. 270 volts fundamental and 90 volts of 3rd harmonic voltage
2. How does the output power handling capacity of a single-phase half bridge inverter
compare with that of a single-phase full bridge inverter when they are connected to same
dc bus voltage and the peak current capability of the inverter switches is also same. Also
compare their costs.
(a) The half bridge inverter can output double power but cost also doubles.
(b) The half bridge inverter can output only half the power but cost is less.
(c) The half bridge inverter can output only half the power but cost is nearly same
(d) The output power capability is same but half bridge inverter costs less.
3. A single-phase full bridge inverter is connected to a purely resistive load. Each inverter
switch consists of an IGBT in anti-parallel with a diode. For this load how does the diode
conduction loss compare with the IGBT conduction loss?

(a) Diode and IGBT will have nearly same conduction loss
(b) Diode conduction loss will be nearly half of the IGBT loss
(c) Diode will have no conduction loss
(d) IGBT will have no conduction loss
4. Using frequency domain analysis estimate the ratio of 5th and 7th harmonic currents in a
purely inductive load that is connected to the output of a single phase half bridge inverter
with square wave pole voltages.
(a) 5th harmonic current will be nearly double of the 7th harmonic current
(b) 5th harmonic current will be 40% more than the 7th harmonic current
(c) 5th harmonic current will be zero while 7th harmonic current will be present
(d) Both 5th and 7th harmonic currents will be zero
(Answers to the quiz problems: 1-d, 2-b, 3-c, 4-a)

Module
5
DC to AC Converters
Lesson
35
3-Phase Voltage Source
Inverter With Square
Wave Output
(i) Explain the operating principle of a three-phase square wave inverter.
(ii) Understand the limitations and advantages of square-wave inverters.
(iii) Do harmonic analysis of load voltage and load current output by the three-phase
sq. wave inverter.
The basic configuration of a Voltage Source Inverter (VSI) has been described in Lesson 33.
Single-phase half-bridge and full-bridge configurations of VSI with square wave pole voltages
have been analyzed in Lesson 34. In this lesson a 3-phase bridge type VSI with square wave pole
voltages has been considered. The output from this inverter is to be fed to a 3-phase balanced
load. Fig. 35.1 shows the power circuit of the three-phase inverter. This circuit may be identified
as three single-phase half-bridge inverter circuits put across the same dc bus. The individual pole
voltages of the 3-phase bridge circuit are identical to the square pole voltages output by single-
phase half bridge or full bridge circuits. The three pole voltages of the 3-phase square wave
inverter are shifted in time by one third of the output time period. These pole voltages along with
some other relevant waveforms have been plotted in Fig. 35.2. The horizontal axis of the
waveforms in Fig. 35.2 has been represented in terms of ‘ωt’, where ‘ω’ is the angular frequency
(in radians per second) of the fundamental component of square pole voltage and ‘t’ stands for
time in second. In Fig. 35.2 the phase sequence of the pole voltages is taken as VAO, VBO and
VCO. The numbering of the switches in Fig. 35.1 has some special significance vis-à-vis the
output phase sequence.
P idc B
Sw1 Sw3 Sw5
Edc + Cdc
_ A
A B C N
3-phase
balanced load
Sw4 Sw6 Sw2

n C
Fig. 35.1: A 3-phase Voltage Source Inverter (VSI) feeding a balanced load

VAO
0.5Edc
Sw1 Sw1
0
Sw4 Sw4
- 0.5Edc ωt
VBO 0.5Edc
Sw3 Sw3
0
Sw6 Sw6 Sw6
- 0.5Edc ωt
VCO 0.5Edc
Sw5 Sw5 Sw5
0
Sw2 Sw2
- 0.5Edc ωt
VAB Edc
0
ωt
-Edc
2/3Edc
VAN
1/3Edc
0
-1/3Edc
-2/3Edc ωt
2/3Edc
VBN 1/3Edc
0
-1/3Edc
-2/3Edc
0 π/3 2π/3 π 4π/3 5π/3 2π 7π/3 8π/3 3π 10π/3 11π/3 3π ωt
Fig. 35.2: Some relevant voltage waveforms output by a 3-phase square wave VSI
To appreciate the particular manner in which the switches have been numbered, the conduction-
pattern of the switches marked in Fig. 35.2 may be noted. It may be seen that with the chosen
numbering the switches turn on in the sequence:- Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw1, Sw2,
….and so on. Identifying the switching cycle time as 360 degrees (2π radians), it can be seen that
each switch conducts for 1800 and the turning on of the adjacent switch is staggered by 60
degrees. The upper and lower switches of each pole (leg) of the inverter conduct in a

complementary manner. To reverse the output phase sequence, the switching sequence may
simply be reversed.
Considering the symmetry in the switch conduction pattern, it may be found that at any time
three switches conduct. It could be two from the upper group of switches, which are connected to
positive dc bus, and one from lower group or vice-versa (i.e., one from upper group and two
from lower group). According to the conduction pattern indicated in Fig. 35.2 there are six
combinations of conducting switches during an output cycle:- (Sw5, Sw6, Sw1), (Sw6, Sw1,
Sw2), (Sw1, Sw2, Sw3), (Sw2, Sw3, Sw4), (Sw3, Sw4, Sw5), (Sw4, Sw5, Sw6). Each of these
combinations of switches conducts for 600 in the sequence mentioned above to produce output
phase sequence of A, B, C. As will be shown later the fundamental component of the three
output line-voltages will be balanced. The load side phase voltage waveforms turn out to be
somewhat different from the pole voltage waveforms and have been dealt with in the next
section.
35.1 Determination Of Load Phase-Voltages

Fig. 35.1 shows a star connected balanced 3-phase load. The three load terminals are connected
to the three output points (A, B, C) of the inverter. The neutral point ‘N’ of the load is
deliberately left open for some good reasons mentioned later. The load side phase voltages VAN,
VBN and VCN can be determined from the conduction pattern of the inverter switches. With
reference to Fig. 35.2, it may be seen that for 0≤ωt≤π/3, switches Sw5, Sw6 and Sw1 conduct.
Under the assumption of ideal switches Fig. 35.3(a) will represent the equivalent inverter and
load circuit during the time interval 0≤ωt≤π/3. In the equivalent circuit representation the non-
conducting switches have been omitted and a cross (X) sign is used to represent a conducting
switch. For a balanced 3-phase load the instantaneous phase voltage waveforms have been
derived below for the following two cases (i) when the 3-phase load is purely resistive and (ii)
when the load, in each phase, consists of a resistor in series with an inductor and a back e.m.f. In
both the cases the equivalent circuit of Fig. 35.3(a) has been referred to derive the expression for
load-phase voltage.
Sw1
A
X
Sw5 VAN = 1/3 Edc

X C VBN = -2/3 Edc
N
+ VCN = 1/3 Edc
Edc _
Sw6
B
X
Fig. 35.3(a): Schematic load circuit during conduction of Sw5, Sw6 and Sw1
For case (i), when the load is a balance resistive load, it is very easy to see that the instantaneous
phase voltages, for 0≤ωt≤π/3, will be given by VAN = 1/3 Edc, VBN = -2/3 Edc, VCN = 1/3 Edc.
For case (ii), the following circuit relations hold good.

di A di di
VAN = RiA + L + E A , VBN = RiB + L B + EB , VCN = RiC + L C + EC .…..……(35.1)
dt dt dt
VAN − VBN = Edc , VAN = VCN ..………………………………………………………..(35.2)
where, iA , iB , iC are the instantaneous load-phase currents entering phases A, B and C
respectively. EA , EB and EC are the instantaneous magnitudes of load phase-emfs. R and L are
the per-phase load resistance and inductance that are connected in series with the corresponding
phase-emf. Since the load is balanced (with its neutral point floating) the algebraic sum of the
instantaneous phase currents and the phase emfs will be zero. Accordingly,
iA + iB + iC = 0 and EA + EB + EC = 0………………………………………(35.3)
From Eqns. 35.1 and 35.3, the following may be deduced:
d (i + i ) di
VAN + VCN = R (i A + iC ) + L A C + ( E A + EC ) = −( RiB + L B + EB ) = −VBN .... (35.4)
dt dt
Now from Eqns. 35.2 and 35.4 it can be easily found that VAN = 1/3 Edc, VBN = -2/3 Edc, VCN =
1/3 Edc.
Thus the instantaneous magnitudes of load phase voltages, in case of a more general (but
balanced) R-L-E load are same as in case of a simple balanced resistive load.
Fig. 35.3(b) shows the equivalent circuit during π/3≤ωt≤2π/3, when the switches Sw6, Sw1 and
Sw2 conduct. The instantaneous load phase voltages may be found to be VAN = 2/3 Edc, VBN =
VCN = -1/3 Edc.
Sw1
A
X
+
Edc _ VAN = 2/3 Edc
Sw2
X C VBN = -1/3 Edc
N
VCN = -1/3 Edc
Sw6
B
X
Fig. 35.3(b): Schematic load circuit during conduction of Sw6, Sw1 and Sw2
The load phase voltage waveforms for other switching combinations may be found in a similar
manner. Two of the phase voltages, VAN and VBN , along with line voltage VAB have been plotted
over two output cycles in Fig. 35.2. It may be seen that voltage VBN is similar to VAN but lags it
by one third of the output cycle period. Further, it can be verified that the load phase voltage VCN
also has a waveform identical to the two other phase voltages but time displaced by one third of
the output time period. VCN waveform leads VAN by 120 degrees in the time (ωt) frame. It
should be obvious that the fundamental component of the phase voltage waveforms will
constitute a balanced 3-phase voltage having a phase sequence A, B, C. It may also be recalled
that by suitably changing the switching sequence the output phase sequence can be changed. The
phase voltage waveforms of Fig. 35.2 show six steps per output cycle and are also referred as the

six-stepped waveform. A more detailed analysis of the load voltage waveforms is done in the
following section.
35.2 Harmonic Analysis Of Load Voltage Waveforms

The individual pole voltage waveforms output by the 3-phase square wave inverter are identical
to the output waveform of a single-phase half bridge inverter. As a consequence, the harmonic
analysis of the voltage waveform presented in section 34.1 of Lesson 34 is valid here too. The
expression for line voltage VAB is identical to the one given in Lesson 34 (Eqn.34.15), with ‘Φ’
of Eqn. 34.15 replaced by 2π/3 radians. For convenience the expressions for pole-A voltage
‘ VAO ’ and line voltage ‘ VAB ’ are reproduced below in Eqns.35.5 and 35.6. The relevant
waveforms are shown in Fig.35.2.
2 Edc
VAO = ∑ sin(nwt ) ………………………………………....….(35.5)
n =1,3,5,7,...,∞ nπ
2 Edc ⎡ 2π ⎤
VAB = ∑ nπ ⎢
⎣
sin nwt − sin n( wt −
3
) ⎥ ………………………....(35.6)
⎦
n =1,3,5,7,...,∞
Using equations 35.5 and 35.6, the expressions for remaining pole and line voltages can be
written simply by shifting the time (ωt) origin by the phase shift angle shown in Fig.35.2.
Accordingly the expressions for pole voltage VBO and line voltage VBC are written below in Eqns.
35.7 and 35.8 respectively.
2E 2π
VBO = ∑ nπdc sin n(wt − 3 ) ……………………………………...(35.7)
n =1,3,5,7,...,∞
⎡
2 Edc 2π 4π ⎤
VBC = ∑ ⎢⎣sin n( wt − 3 ) − sin n( wt − 3 ) ⎥⎦ …………….…...(35.8)
n=1,3,5,7,...,∞ nπ
It may be verified that difference of VAO and VBO leads to the expression for VAB . The
expression for a particular harmonic component in the voltage waveforms is determined simply
by substituting ‘n’ in above equations by the harmonic order. Accordingly the fundamental
magnitude of line voltages VAB , VBC and VCA can be written as:
2 Edc ⎡ 2π ⎤ 2 3Edc π
VAB ,1 = ⎢ sin wt − sin( wt − )⎥ = sin( wt + )
π ⎣ 3 ⎦ π 6
2 3Edc π 2 3Edc 7π
VBC ,1 = sin( wt − ) , VCA,1 = sin( wt − )
π 2 π 6
The three fundamental line voltages are balanced (have identical magnitudes and are phase apart
by 1200). For most practical loads only the fundamental component of the inverter output voltage
is of interest. However the inverter output also contains significant amount of higher order
harmonic voltages that cause undesirable distortion of the output waveform. It may, though, be
noted that there are no even harmonics and the line voltages are free from 3rd and multiples of 3rd
order harmonics. Also, as the harmonic order (n) increases their magnitudes decrease inversely
with the harmonic order. When expressed as a fraction of fundamental voltage magnitude, the
line voltage distortions are mainly due to 20% of 5th harmonic, nearly 14% of 7th, nearly 9% of

11th and nearly 8% of 13th harmonic. Since most loads are inductive in nature with a low pass
filter type characteristics the effect of very high order harmonics may be neglected.
It may be noted that though the pole voltages have 3rd and multiples of 3rd order harmonic
distortions, the line voltages are free from these distortions. Hence the load neutral point, rather
than being connected to the mid-potential point of the input dc supply (as in a single-phase half
bridge inverter), is deliberately left floating. The floating neutral point does not allow a closed
path for the 3rd and multiples of 3rd harmonic currents to flow (3rd or multiples of 3rd harmonic
current, if present in the load phases, have identical instantaneous magnitudes in all the three
phases and their algebraic sum needs to flow in or out of the load neutral point). By keeping the
load neutral point floating, not only the need for bringing out the mid-potential point of dc
supply is done away with, the triplen harmonic distortions of the load current is totally
eliminated. Since there are no triplen harmonic currents in the load, the load-phase voltages are
also free from triplen harmonic distortions. In fact the six-stepped load-phase voltages shown in
Fig. 35.2 are found to be free from triplen harmonics. It turns out that by removing all triplen
harmonics from the square-shaped pole voltage waveform one can arrive at the corresponding
load-phase (six-stepped) voltage waveform. Accordingly the load-phase voltages may be
expressed in terms of its harmonic contents as shown below.
2 Edc
VAN = ∑ sin(nwt ) ……………………………………….....(35.9)
n =1,5,7,11,13...,∞ nπ
2 Edc 2π
VBN = ∑ nπ
sin n( wt −
3
) …………………………………...(35.10)
n=1,5,7,11,13...,∞
2 Edc 2π
VCN = ∑ sin n( wt + ) …………………………………...(35.11)
n=1,5,7,11,13...,∞ nπ 3
For a balanced three-phase load, the instantaneous magnitude of any phase current can be
determined by superposition of different harmonic currents of the phase. For a simple three-
phase R-L load, the phase-A current ( iA ) expression in terms of resistance (R) and inductance
(L) of the load may be written as:
2 Edc nω L
iA = ∑ sin[nwt − tan −1 ( )] …………….....(35.12)
n=1,5,7,11,13...,∞ nπ R 2 + n 2ω 2 L2 R
Phase-B and phase-C current expressions can be obtained simply by replacing ωt in Eqn. 35.12
2π 2π
by (ω t − ) and (ω t + ) respectively. A close look at Eqn. 35.12 will reveal that for a
3 3
purely inductive 3-phase load the 5th, 7th, 11th and 13th harmonic distortion in the load current (as
a percentage of fundamental component of current) will respectively be 4%, 2.04%, 0.83% and
0.59%. These distortions are much less than the corresponding distortions in the load voltage
waveforms. As a result the load current for highly inductive R-L load will have close to
sinusoidal shape.

35.3 Voltage And Current Ratings Of Inverter Switches
As in a single-phase square-wave inverter, switches in each leg of the three-phase inverter
operate in a complementary manner. When upper switch of a leg is on the lower switch will need
to block the entire dc bus voltage and vice versa. Thus the switches must be rated to block the
worst-case instantaneous magnitude of dc bus voltage. An extra safety margin over the worst-
case dc voltage, as discussed in Lesson-34, section 34.3, is recommended. Each inverter-switch
carries load-phase current during half of the current cycle. Hence the switches must be rated to
withstand the peak expected magnitude of instantaneous load-phase current. For a non-unity
power factor load, the diode connected in anti-parallel with the switch will conduct part of the
switch current. The distribution of current between the diode and the controlled switch will
depend on the load power factor at the operating frequency. In general both diode as well as the
controlled switch should be rated to carry the peak load current. These diodes also need to block
a peak reverse voltage equal to worst case voltage across the switches.
35.4 Use And Limitations Of 3-Phase Square Wave Inverter

The three-phase square wave inverter as described above can be used to generate balanced three-
phase ac voltages of desired (fundamental) frequency. However harmonic voltages of 5th, 7th
and other non-triplen odd multiples of fundamental frequency distort the output voltage. In many
cases such distortions in output voltages may not be tolerable and it may also not be practical to
use filter circuits to filter out the harmonic voltages in a satisfactory manner. In such situations
the inverter discussed in this lesson will not be a suitable choice. Fortunately there are some
other kinds of inverters, namely pulse width modulated (PWM) inverters, discussed in the next
lesson, which can provide higher quality of output voltage.
The square wave inverter discussed in this lesson may still be used for many loads, notably ac
motor type loads. The motor loads are inductive in nature with the inherent quality to suppress
the harmonic currents in the motor. The example of a purely inductive load discussed in the
previous section illustrates the effectiveness of inductive loads in blocking higher order harmonic
currents. In spite of the inherent low-pass filtering property of the motor load, the load current
may still contain some harmonics. These harmonic currents cause extra iron and copper losses in
the motor. They also produce unwanted torque pulsations. Fortunately the torque pulsations due
to harmonic currents are of high frequencies and their effect gets subdued due to the large
mechanical inertia of the drive system. The motor speed hardly changes in response to these
torque pulsations. However in some cases torque pulsations of particular frequencies may cause
unwanted resonance in the mechanical system of the drive. A special notch filter may then be
required to remove these frequencies from the inverter output voltage.
The input dc voltage to the inverter is often derived from an ac source after rectification and
filtering. A simple diode bridge rectifier followed by a filter capacitor is often the most cost-
effective method to get dc voltage from ac supply. In some applications, like in un-interrupted
power supplies, the dc input may be coming from a bank of batteries. In both these examples, the
input dc magnitude is fairly constant. With fixed input dc voltage the square-wave inverter can
output only fixed magnitude of load voltage. This does not suit the requirement in many cases
where the load requires a variable voltage variable frequency (VVVF) supply. In order that ac
output voltage magnitude is controllable, the inverter input voltage will need to be varied using
an additional dc-to-dc converter. However a better solution will be to use a PWM inverter (to be

discussed in the next lesson), which can provide a VVVF output with enhanced output voltage
quality.
In spite of the limitations, discussed above, the square wave inverter may be a preferred choice
on account of its simplicity and low cost. The switch control circuit is very simple and the
switching frequency is significantly lower than in PWM inverters. This results in low switching
losses. The switch cost may also be lower as one may do away with slower switching devices
and slightly lower rated switches. Another advantage over PWM inverter is its ability to output
higher magnitude of fundamental voltage than the maximum that can be output from a PWM
inverter (under the given dc supply condition). Listed below are two applications where a 3-
phase square wave inverter could be used.
(i) A low cost solid-state frequency changer circuit: This circuit converts the 3-phase ac
(input) voltages of one frequency to 3-phase ac (output) voltages of the desired
frequency. The input ac is first converted into dc and then converted back to ac of new
frequency. The square wave inverter discussed in this lesson may be used for dc to ac
conversion. Such a circuit may, for example, convert 3-phase ac voltages of 50 Hz to 3-
phase ac voltages of 60 Hz. The input to this circuit could as well have come from a
single-phase supply, in which case the single-phase ac is first converted into dc and
then converted back to 3-phase ac of the desired frequency.
(ii) An uninterrupted power supply circuit: Uninterrupted power supply circuits are used to
provide uninterrupted power to some critical load. Here a critical load requiring 3-
phase ac supply of fixed magnitude and frequency has been considered. In case ac
mains supply fails, the 3-phase load may be electronically switched, within few
milliseconds, to the output of the 3-phase square wave inverter. Input dc supply of the
inverter often comes from a battery bank.
Problems
(1) A 3-phase square wave inverter feeds a balanced 3-phase resistive-inductive load. The
load phase current will contain, apart from the fundamental frequency current, the
following harmonic currents:
(a) All odd multiples of fundamental
(b) All odd and even multiples of fundamental
(c) All even multiples of fundamental except 6th and multiples of 6th
(d) All odd multiples of fundamental except 3rd and multiples of 3rd
(2) The six-stepped load phase voltage of a 3-phase square wave inverter, with a dc link
voltage of 100 volts, will have the following rms magnitudes of 1st, 3rd and 5th harmonic
voltages:
(a) 10V, 30V and 50V respectively
(b) 100V, 33.3V and 20V respectively
(c) 90V, 30V and 0 respectively
(d) 45V, 0 and 9V respectively
(3) A 3-phase square wave inverter, fed from a fixed dc input, is capable of producing the
following type of ac (fundamental component) voltages:

(a) Variable voltage variable frequency type
(b) Fixed voltage variable frequency type
(c) Variable voltage fixed frequency type
(d) None of the above
(4) A 3-phase square wave inverter feeds a balanced 3-phase inductance type load. The
worst-case load phase current (peak magnitude) is expected to be 100 amps and the
worst-case dc input voltage is expected to be 600 volts. The diodes of the inverter will be
subjected to the following peak voltage and current stresses:
(a) 600V, 100A
(b) 600V, 70.7A
(c) 424V, 70.7A
(d) 424V, 100A
(Answers: 1-d, 2-d, 3-b, 4-a)

Module
5
DC to AC Converters
Lesson
36
3-Phase Pulse Width
Modulated (PWM)
Inverter
(i) Explain the philosophy behind PWM inverters.
(ii) Understand the advantages and disadvantages of PWM inverters.
(iii) Compare the quality of output voltage produced by different PWM inverters
Pulse width modulated (PWM) inverters are among the most used power-electronic circuits in
practical applications. These inverters are capable of producing ac voltages of variable
magnitude as well as variable frequency. The quality of output voltage can also be greatly
enhanced, when compared with those of square wave inverters discussed in Lesson-35. The
PWM inverters are very commonly used in adjustable speed ac motor drive loads where one
needs to feed the motor with variable voltage, variable frequency supply. For wide variation in
drive speed, the frequency of the applied ac voltage needs to be varied over a wide range. The
applied voltage also needs to vary almost linearly with the frequency. PWM inverters can be of
single phase as well as three phase types. Their principle of operation remains similar and hence
in this lesson the emphasis has been put on the more general, 3-phase type PWM inverter.
There are several different PWM techniques, differing in their methods of implementation.
However in all these techniques the aim is to generate an output voltage, which after some
filtering, would result in a good quality sinusoidal voltage waveform of desired fundamental
frequency and magnitude. As will be discussed later in this chapter, for the inverter topology
considered here, it may not be possible to reduce the overall voltage distortion due to harmonics
but by proper switching control the magnitudes of lower order harmonic voltages can be
reduced, often at the cost of increasing the magnitudes of higher order harmonic voltages. Such a
situation is acceptable in most cases as the harmonic voltages of higher frequencies can be
satisfactorily filtered using lower sizes of filter chokes and capacitors. Many of the loads, like
motor loads have an inherent quality to suppress high frequency harmonic currents and hence an
external filter may not be necessary.
To judge the quality of voltage produced by a PWM inverter, a detailed harmonic analysis of the
voltage waveform needs to be done. In the following discussions some of the results of harmonic
analysis done in the previous lessons have been borrowed. In Lesson-35, while discussing the 3-
phase square wave inverter it was shown that the magnitudes of fundamental components of the
inverter pole voltage (voltage between the output of an inverter leg and the mid potential point of
the input dc supply) and the load phase voltage are identical provided the load is a balanced 3-
phase load. In fact, after removing 3rd and multiples of 3rd harmonics from the pole voltage
waveform one obtains the corresponding load phase voltage waveform. The pole voltage
waveforms of 3-phase inverter are simpler to visualize and analyze and hence in this lesson the
harmonic analysis of load phase and line voltage waveforms is done via the harmonic analysis of
the pole voltages. It is implicit that the load phase and line voltages will not be affected by the 3rd
and multiples of 3rd harmonic components that may be present in the pole voltage waveforms.

36.1 Nature Of Pole Voltage Waveforms Output By PWM
Inverters
Unlike in square wave inverters the switches of PWM inverters are turned on and off at
significantly higher frequencies than the fundamental frequency of the output voltage waveform.
The typical pole voltage waveform of a PWM inverter is shown in Fig. 36.1 over one cycle of
output voltage. In a three-phase inverter the other two pole voltages have identical shapes but
they are displaced in time by one third of an output cycle. Compared to the square pole voltage
waveform seen in Lesson-35, the pole voltage waveform of the PWM inverter changes polarity
several times during each half cycle. The time instances at which the voltage polarities reverse
have been referred here as notch angles. It may be noted that the instantaneous magnitude of pole
voltage waveform remains fixed at half the input dc voltage (Edc). When upper switch (SU),
connected to the positive dc bus is on, the pole voltage is + 0.5 Edc and when the lower switch
(SL), connected to the negative dc bus, is on the instantaneous pole voltage is - 0.5 Edc. The
switching transition time has been neglected in accordance with the assumption of ideal
switches. It is to be remembered that in voltage source inverters, meant to feed an inductive type
load, the upper and lower switches of the inverter pole conduct in a complementary manner. That
is, when upper switch is on the lower is off and vice-versa. Both upper and lower switches
Pole
Voltage
0.5Edc
SU SU SU SU SU SU SU SU SU
ωt
0
SL SL SL SL SL SL SL SL SL
-0.5Edc
α1 α3 π/2 π-α3 π-α1 π+α1 π+α3 3π/2 2π-α3 2π-α1
0 α2 α4 π-α4 π-α2 π π+α2 π+α4 2π-α4 2π-α2 2π
Fig.36.1: A typical pole-voltage waveform of a PWM inverter
should not remain on simultaneously as this will cause short circuit across the dc bus. On the
other hand one of these two switches in each pole (leg) must always conduct to provide
continuity of current through inductive loads. A sudden disruption in inductive load current will
cause a large voltage spike that may damage the inverter circuit and the load.
36.2 Harmonic Analysis Of Pole Voltage Waveform

The pole voltage waveform shown in Fig. 36.1 has half wave odd symmetry and quarter-wave
mirror symmetry. The half wave odd symmetry of any repetitive waveform f(ωt), repeating after
every 2π/ω duration, is defined by f(ωt) = - f(π+ωt). Such a symmetry in the waveform amounts

to absence of dc and even harmonic components from the waveform. All inverter output voltages
maintain half wave odd symmetry to eliminate the unwanted dc voltage and the even harmonics.
The half wave odd symmetry followed by quarter wave mirror symmetry, defined by f(ωt) = f(π-
ωt), results in presence of only sine components in the Fourier series representation of the
waveform. It may be verified that quarter wave symmetry may not hold good once the time
origin is shifted arbitrarily. However the half-wave odd symmetry is maintained in spite of
shifting of time origin. This is quite expected, as by just shifting the time origin new (even)
harmonic frequencies will not creep up in the voltage waveform, whereas by shifting time origin
the sine wave may become cosine or may have some other phase-shift. The quarter wave
symmetry talked above is not necessary for improvement of the output waveform quality; it
merely simplifies the Fourier analysis of the pole voltage waveform. It may also be noted that the
quarter wave symmetry is not achieved at the cost of compromising the inverter’s output
capability (in terms of magnitude and quality of achievable output voltage).
With the assumed quarter wave mirror symmetry and half wave odd symmetry the waveform
shown in Fig. 36.1 may be decomposed in terms of its Fourier components as below:-
VAO = ∑ bn sin nω t ……………………………………………………..(36.1)

n=1,3,5,....∞
where VAO is the instantaneous magnitude of the pole voltage shown in Fig. 36.1 and
bn is the peak magnitude of its nth harmonic component. Because of the half wave and quarter
wave symmetry of the waveform, mentioned before, the pole voltage has only odd harmonics
and has only sinusoidal components in the Fourier expansion. Thus the pole voltage will have
fundamental, third, fifth, seventh, ninth, eleventh and other odd harmonics. The peak magnitude
of nth harmonic voltage is given as:
2E
bn = (1 − 2 cos nα1 + 2 cos nα 2 − 2 cos nα 3 + 2 cos nα 4 ) …………………..(36.2)
nπ
, where α1 , α 2 ¸ α3 and α 4 are the four notch angles in the quarter cycle ( 0 ≤ ω t ≤ π 2 ) of
the waveform.
Now, as described in the beginning of this lesson, the third and multiples of third
harmonics do not show up in the load phase and line voltage waveforms of a balanced 3-phase
load. Most of the three phase loads of interest are of balanced type and for such loads one need
not worry about triplen (3rd and multiples of 3rd) harmonic distortion of the pole voltages. The
peak magnitudes of fundamental ( b1 ) and three other lowest order harmonic voltages that matter
most to the load can be written as:
2E
b1 = (1 − 2 cos α1 + 2 cos α 2 − 2 cos α 3 + 2 cos α 4 ) ….…………………..(36.3)
π
2E
b5 = (1 − 2 cos 5α1 + 2 cos 5α 2 − 2 cos 5α 3 + 2 cos 5α 4 ) ………………...(36.4)
5π
2E
b7 = (1 − 2 cos 7α1 + 2 cos 7α 2 − 2 cos 7α 3 + 2 cos 7α 4 ) ………………..(36.5)
5π
2E
b11 = (1 − 2 cos11α1 + 2 cos11α 2 − 2 cos11α 3 + 2 cos11α 4 ) …………...(36.6)
11π
It can be seen that the 3rd and 9th harmonics have been not considered, as they will not appear in
the load side phase and line voltages. Most of the industrial loads are inductive in nature with an

inherent quality to attenuate currents due to higher order harmonic voltages. Thus after
fundamental voltage, the other significant voltages for the load are 5th, 7th and 11th etc.
Generally, only the fundamental frequency component in the output voltage is of interest and all
other harmonic voltages are undesirable. As such one would like to eliminate as many low order
harmonics as possible. Accordingly the fundamental voltage magnitude ( b1 ) may be set at the
desired value and the magnitudes of fifth ( b5 ), seventh ( b7 ) and eleventh ( b11 ) harmonics may
be set to zero. These voltage magnitudes when substituted in the expressions given by Eqns. 36.3
to 36.6 will lead to the solutions of the notch angles. One may like to eliminate many more
unwanted harmonic frequencies from the load voltage waveform but this will require
introduction of more notch angles per quarter cycle of the pole voltage. In fact if there are ‘k’
notch angles per quarter cycle, ‘k’ number of equations may be written each of which determines
the magnitude of a particular harmonic voltage. Now, each time a notch angle is encountered in
the pole voltage waveform, the top and bottom switches of that particular pole undergo a
switching transition (on to off or vice versa). The switching frequency (fsw) of the inverter
switches can be equated to
fsw = 2 k f1 …………...…………...………………………….....(36.7)
, where one turn-on and one turn-off has been taken as one switching cycle, ‘k’ is the number of
notches per quarter cycle and f1 is the frequency of fundamental component in the output
voltage. Thus it can be seen that a better quality output waveform (in terms of elimination of
more numbers of unwanted harmonic voltages) comes at the cost of increasing the switching
frequency of the inverter. The switching frequency is directly proportional to the switching
losses in the inverter switches. Also, the switch must be capable of being switched on and off at
the required frequency. The IGBT switches used in medium power inverters are generally
switched at a frequency of 20 kHz or more. With a switching frequency of 20 kHz and the output
(fundamental) frequency of 50 Hz there will be up to 200 notches per quarter cycle of the output
waveform. The load voltage can thus be made virtually free of low order harmonics and the load
current (for an inductive load) can be expected to have a good quality sinusoidal waveform. The
switching frequency of 20 kHz is important in another sense too. The range of audible noise for
human beings extends from few Hertz to 20 kHz. Thus if the switching frequency is 20 kHz or
beyond, the switching frequency related audible noise will not be present when the inverter
operates. The inverter operation can then be very quite. If the inverter operates at low frequency,
the connecting wires to the switches etc. also carry low frequency current producing low
frequency vibrations (due to interaction of current with the stray magnetic field produced by
other conductors etc.) and result in audible noise. Similarly low frequency current through
inductors and transformers also produce audible noise. The humming or whistling type noise due
to low switching frequency may at times be too annoying and unacceptable.
36.3 Trade Off Between Low Order And High Order Harmonics
The 3-phase inverter with six switches connected in the bridge fashion is also known as a two-
level inverter because the inverter pole-voltage alternates between the two voltage levels of +0.5
Edc and - 0.5 Edc (the switching transition time has been neglected). The root mean square (rms)
of the pole voltage equals 0.5 Edc. Now a periodic function ‘ f (ω t ) ’ when expressed in terms of
its Fourier components satisfies the following mathematical identity.

[ f (ω t )rms ]2 = ⎡⎣ f (ω t )1,rms ⎤⎦ ∑
2 2
+ ⎡⎣ f (ω t ) n ,rms ⎤⎦ ………………………..(36.8)
n = 2,3,4,....,∞
In Eqn. (36.8), f (ω t )rms is the rms magnitude of the given periodic waveform where as
f (ω t )1,rms and f (ω t )n,rms are the rms magnitudes of the fundamental component and nth
harmonic component of the waveform respectively.
Also, if the waveform ‘ f (ω t ) ’ has half wave odd symmetry and quarter wave mirror symmetry,
its fundamental voltage can be expressed as
π
2
f (ω t )1,rms =
π ∫ { f (ω t ) sin ω t}dω t ……………………………………....(36.9)
ω t =0
Now let f (ω t ) in the above equations (36.8 and 36.9) be replaced by the two-level pole voltage
waveform of the PWM inverter. The term on the left hand side of Eqn. (36.8) equals (0.5Edc)2.
The first term on the right hand side of Eqn. (36.8) is the square-of-rms (i.e., mean of square)
magnitude of the fundamental component of pole voltage whereas the second term on the right
hand side denotes the mean-of-square magnitude of the unwanted ripple in the pole voltage. As
can be seen, the rms magnitude of the fundamental pole voltage is always going to be less than
0.5Edc. Further, as given by Eqn. (36.9), the fundamental magnitude (rms) of PWM inverter’s
output pole-voltage will be less than 0.45Edc, which is the rms magnitude of fundamental pole
voltage of a 3-phase square wave inverter. [In case of square wave output, both f (ω t ) and
sin ω t are positive during 0 ≤ ω t ≤ π but the sign of f (ω t ) in PWM waveform alternates
between positive and negative values.]
In case of PWM inverter the magnitude of fundamental output voltage is fixed by suitable pulse
width modulation (by selection of suitable notch angles for the waveform in Fig. 36.1). However,
as can be seen from Eqn. (36.8), the reduction in fundamental magnitude leads to increase in the
rms magnitude of the unwanted ripple voltage. Also, after fixing the fundamental voltage
magnitude if it is desired to eliminate some of the low order harmonics, it will be at the cost of
increasing the magnitudes of higher order harmonics. Thus, as far as the quality of inverter pole
voltage alone is concerned the PWM technique is not helping. However considering the fact that
most of the loads are inductive in nature with low pass filter type characteristics the load current
quality effectively improves by eliminating lower order harmonics from the pole voltage
waveform (even if the higher order harmonic magnitudes increase). In case the load, on its own,
is not able to filter out the harmonic voltages satisfactorily the inverter output may be passed
through some external filter before being applied to load. The required size of the external filter
will be small if the inverter output is free from low frequency harmonics.
36.4 Brief Description Of Some Popular PWM Techniques

The schematic PWM waveform shown in Fig. 36.1, is only representative in nature. The logic
described to select notch angles is also specific to one particular PWM technique that is known
as selective harmonic elimination technique. There are several other PWM techniques, the
important ones are:- SINE-PWM technique, Space Vector based PWM technique, Hysteresis
current controller based PWM technique etc. A few of these techniques have been dealt with, in
detail in the next few lessons.

Some of the PWM techniques can be realized using analog circuits alone; some others are more
easily realized with the help of digital processors like microprocessor, Digital signal processor
(DSP) or Personal Computer (PC), whereas some other PWM controllers could be a hybrid
between analog and digital circuits. For example, the selective harmonic elimination technique
described above requires numerical solutions of the transcendental equations for arriving at the
required notch angles. These transcendental equations are solved off-line and the information
regarding notch angles (switching instances) is stored in digital memory, like EPROM. It may be
realized that the notch instances may not occur at regular time intervals. Similarly fundamental
output voltage requirement may not remain fixed for all output frequencies and hence the
transcendental equations (similar to Eqns. 36.3 to 36.6) will be different for different output
frequencies. Also, as per Eqn. 36.7, if the switching frequency is kept constant, there will be
more notch angles (per quarter cycle) at low output frequencies and less number of notches at
higher frequencies. Thus the set of notch angles for one frequency may be different from the
notch angles at some other frequency. For satisfactory implementation of this technique,
generally the desired output frequency range is divided in few discrete frequencies. For example,
it may be desired to output a 3-phase balanced voltage in the frequency range of 5 Hz to 50 Hz
with the constraint that the ratio between output voltage magnitude and output frequency should
remain fixed to some predetermined value. Under this situation the output voltage range may be
discretized in steps of, say, 1Hz. Thus the available output may vary from 5 Hz to 50 Hz through
the following discrete values of intermediate frequencies: 6 Hz, 7 Hz, 8 Hz, …, 49 Hz. The
desired magnitudes of output voltage for all these discrete frequencies is found out and
accordingly the notch angles are calculated to eliminate as many unwanted harmonics as possible
(keeping in mind the constraint on switching frequency). Now switching information for
successive output frequencies may be stored in successive memory blocks. For each of these
output frequencies, it may be convenient to discretize one complete output cycle time interval in
small steps (say, in steps of 10 microseconds) and the inverter switching word (as described
below) at these successive time intervals are then stored in the successive memory locations. The
switching word combines the switching information for all three legs (all six switches) of the
inverter and may be obtained in the form of a six bit binary word, each bit corresponding to one
particular switch. When a particular bit value is ‘1’ that particular switch may require being
turned-on. Similarly ‘0’ bit value may correspond to turn-off command of the switch. Now if the
memory block, containing switching information is addressed sequentially after every 10
microsecond (this being the time step, chosen above, to discretize the output cycle time period)
the desired switching pattern for the inverter switches may be obtained. The notch angles can
thus be realized with a maximum time error of 10 microseconds (which for 50 Hz output
corresponds to an error of 0.180 only). After completion of one output cycle the next cycle is
simply repeated like the previous one. One may move from one memory block to another
memory block (by suitably multiplexing the memory address-word) to obtain the inverter-
switching pattern for some other output frequency. The selective harmonic elimination technique
described above is also known as stored-PWM technique. The overall memory requirement may
be large but since the memory cost has been reducing over the years the stored-PWM technique
remains one of the most attractive techniques.
In contrast to the selective harmonic elimination technique discussed above, some other PWM
techniques, notably SINE-PWM and Space Vector-PWM techniques, try to match the mean
value of load voltage under the rectangular PWM waveform with the mean voltage of the desired
output waveform over every small time interval of the output cycle. If, for example, the desired
output voltage is a sinusoidal waveform of a given magnitude and of frequency ‘f1’, then for
every small time interval ‘Δt’ of the output cycle period (such that Δt << 1/ f1) the mean (dc)
magnitude under desired sine wave and the mean dc voltage under the PWM pulses are made
equal. Now barring the mismatch in the instantaneous magnitudes of the sine wave and the PWM
wave within the small time period ‘Δt’, the two waveforms are matching. Thus the PWM
waveform may be considered to be the superposition of the desired output waveform and ripple
voltages of time period Δt. The ripple voltage waveform in each ‘Δt’ time interval may not be
identical and hence ripple voltage may consist of a band of harmonics of high frequency. In the
frequency axis the high frequency harmonic voltages are far away from the desired voltage of
fundamental frequency ‘f1’ and hence suitable low pass filter circuits may be used to block the
unwanted harmonic currents without affecting the magnitude of the fundamental frequency
current. Further details of these techniques may be found in later lessons.
P
+
_ 0.5Edc
SU
+
Edc IL
_ O LOAD A
+
_ 0.5Edc
SL
N
Fig. 36.2: 1-phase half bridge VSI for CCPWM control
Another popular PWM technique is current controlled PWM (CCPWM) technique. Here the
instantaneous magnitude of load current is directly controlled, within some tolerable error band,
to match the desired current shape. This technique is described below for a single-phase half
bridge inverter shown in Fig.36.2. The positive sense for the load current (IL) is taken along the
direction of arrow in Fig. 36.2. The actual load current is sensed with the help of a current sensor
and compared with its reference magnitude. The error in load current can be controlled, as
described below, by proper switching of the inverter switches. The load could be a R-L load or a
R-L-E load. In case of R-L-E load, it is assumed that the back emf (E) of the load has a peak
magnitude lower than the magnitude of instantaneous pole voltage (0.5Edc). To increase the
actual current along the direction of arrow (or to reduce the current flowing in a direction
opposite to the arrow) upper switch ‘SU’ needs to be turned on, whereas turning on of lower
switch ‘SL’ will produce the reverse effect. This can be verified simply by writing and analyzing
the loop voltage equation.
36.5 Two-Level Versus Three-Level PWM Inverters

As described in section 36.3, the three-phase bridge inverter consisting of six switches (shown in
Lesson-35) can output pole voltages of only two levels +0.5Edc and -0.5Edc. In contrast to a two-
level inverter, a three-level inverter is capable of producing three different pole-voltage levels,
namely, +0.5Edc, zero and -0.5Edc. The circuit details of three-level inverter will not be discussed

in this course but it can easily be shown that the three-level inverter will have better harmonic
spectrum in comparison to the two-level inverter. As described by Eqn. (36.8) in section 36.3,
any reduction in the fundamental output voltage magnitude of a two level inverter results in
increased rms magnitude of unwanted ripple in the output waveform. Now, let Eqn. (36.8) be
considered in relation to a three-level inverter. Since the pole voltage can now have zero level
too, the rms magnitude of the pole voltage can be brought below 0.5Edc. For lower magnitude of
fundamental pole-voltage, as given by Eqn. (36.9), suitable intervals of zero voltage level may be
introduced such that with lowering of fundamental voltage the rms of the overall pole voltage
also reduces. Thus the rms of the ripple voltage, in case of three-level inverter, can be made
lower than that of the two-level inverter.
P idc
Sw1 Sw3
Edc
+ Cdc
_ A LOAD B
Sw2 Sw4
N
Fig. 36.3: A 1-phase full-bridge VSI
The three-level versus two-level comparison can be applicable to a single-phase PWM inverter
too. Consider the single-phase full bridge circuit shown in Fig.36.3. For this circuit if all the time
one of the two diagonal pair of switches, (Sw1 and Sw4) or (Sw2 and Sw3), conduct the load
voltage will have two levels; +E or –E. By suitably switching between one diagonal pair to
another diagonal pair one can obtain a PWM waveform similar to the pole voltage waveform of a
three-phase PWM inverter (only change is in the voltage magnitude). Now if the allowed
switching combination includes conduction of Sw1 along with Sw3 (or Sw2 along with Sw4) the
load voltage may have three-levels, i.e., +E, zero and –E. As with a three-phase inverter, the
single phase PWM inverter too will have lower voltage distortion in case of three-level load
voltage (than the corresponding distortion in two level output).
36.6 Considerations On Switch Voltage And Current Ratings

As in square wave inverter the switches of PWM inverter must also be rated for the maximum dc
link voltage. There will, however, be a significant difference in the switch current ratings of the
square wave and PWM inverter for comparable magnitudes of inverters’ output current. This is
due to the increased switching losses in the PWM inverter. Since the switches in PWM inverter
operate at much higher frequencies than in square wave inverter, the switching losses in the
former are comparable to the conduction losses. This calls for suitable de-rating of the switch
current rating. For medium power rated inverters mostly IGBT switches (with fast acting anti-
parallel diodes) are used. Generally molded blocks of six switches and six diodes, connected in

bridge fashion with their power and control terminals brought out, are commercially available.
These molded blocks come with isolated metallic case that need to be mounted on suitably sized
heat sinks for dissipation of thermal losses in the switch. The switch manufacturers provide the
turn-on and turn-off loss data for the switches for different magnitudes of dc link voltage, switch
current and gate-to-emitter voltages. Similarly conduction loss data for the switches and the
diodes are also provided. The thermal resistance data (thermal resistance between case and
semiconductor-junction) for the switches and diodes are also provided. The heat-sink
manufacturers provide data / guide lines for calculating the thermal resistance between heat sink
and ambient. The inverter designer needs to do a detailed analysis of the worst-case thermal
losses and temperature rise and need to limit the switch current accordingly. In PWM inverters,
because of large number of switching per output cycle, the load current frequently jumps from
controlled switch (say, IGBT) to diode and hence the diodes of the switches must also be rated to
carry the peak magnitude of load current. It is to be kept in mind that in PWM inverters the load
current polarity changes only according to the output frequency and not according to the
switching frequency. For load power factor close to one, as the PWM inverter’s output voltage
decreases the diode conduction duration increases. The worst-case diode losses also need to be
determined for deciding on the de-rating factor for diode currents.
Quiz Problems
(1) A PWM inverter is operated from a dc link voltage of 600 volts. The maximum rms line
voltage (fundamental component) will be less than or equal to:
(a) 600 volts
(b) 300 volts
(c) 467 volts
(d) 582 volts
(2) In the harmonic analysis of the pole-voltage waveform (produced by a three-phase PWM
inverter feeding a balanced three-phase load) the 3rd and multiples of 3rd harmonics are
ignored because:
(a) They will not appear in pole voltage
(b) They will not appear in load phase voltage
(c) They will not appear in load phase and line voltage
(d) They will appear in line voltage but not in phase voltage
(3) An IGBT based PWM inverter, with very large number of (nearly) evenly distributed
notches per output cycle, is used to feed a three-phase balanced R-L load with a load
power factor of 0.9. The peak magnitude of diode current and the IGBT current will have
the following relation:
(a) They will be equal
(b) Peak diode current will be less than half of the peak IGBT current
(c) Diode current will nearly be zero
(d) Peak diode current will be less than one third of the peak IGBT current
(4) A PWM inverter is capable of producing the following type of output voltage:
(a) Variable in magnitude and frequency
(b) Variable voltage, fixed frequency
(c) Fixed voltage, variable frequency
(d) Fixed voltage, fixed frequency
Answers to Quiz problems: 1-c, 2-c, 3-a, 4-a

Module
5
DC to AC Converters
Lesson
37
Sine PWM and its
Realization
After completion of this lesson, the reader shall be able to:
1. Explain the concept of sine-modulated PWM inverter
2. Design a simple controller for the sine-PWM inverter
3. Calculate output voltage magnitude from the inverter operating parameters
4. Compare sine-modulated PWM inverter with square wave inverter
The PWM inverter has been introduced in Lesson 36 and Fig. 36.1 shows a typical pole voltage
waveform, over one output cycle of the PWM inverter. It can be seen that the pole voltage
consists of large number of rectangular pulses whose widths are modulated suitably to provide
control over the output voltage (fundamental component) magnitude and, additionally, control
over the harmonic spectrum of the output waveform.
In Sine-PWM inverter the widths of the pole-voltage pulses, over the output cycle, vary in a
sinusoidal manner. The scheme, in its simplified form, involves comparison of a high frequency
triangular carrier voltage with a sinusoidal modulating signal that represents the desired
fundamental component of the pole voltage waveform. The peak magnitude of the modulating
signal should remain limited to the peak magnitude of the carrier signal. The comparator output
is then used to control the high side and low side switches of the particular pole. Fig. 37.1 shows
an op-amp based comparator output along with representative sinusoidal and triangular signals as
inputs. In the comparator shown in Fig. 37.1, the triangular and sinusoidal signals are fed to the
inverting and the non-inverting input terminals respectively and the comparator output
magnitudes for high and low levels are assumed to be +VCC and -VCC.
+VCC
Modulating Q
signal
+
Q -VCC
-
Carrier
signal
Time (mili sec.)
Fig. 37.1: A schematic circuit for comparison of Modulating and Carrier signals
The comparator output signal ‘Q’ is used to turn-on the high side and low side switches of
the inverter pole. When ‘Q’ is high, upper (high side) switch of the particular pole is turned on
and when ‘Q’ is low the lower switch is turned on.
The pole voltage, thus obtained is a replica of the comparator output voltage. When ‘Q’= + VCC,
the pole voltage (measured with respect to the mid potential point of the dc supply) is +0.5Edc and

when ‘Q’= (-)VCC, the pole voltage becomes (-0.5)Edc. The input dc voltage to the inverter (Edc)
has been assumed to be of constant magnitude. Thus, on a normalized scale, the harmonic
contents in the comparator output voltage and the pole voltage waveforms are identical.
37.1 Analysis Of The Pole Voltage Waveform With A Dc

Modulating Signal
Before analyzing the sine-modulated pole voltage waveform, it would be revealing to consider a
pure dc signal (of constant magnitude) as the modulating wave. The magnitude of the dc
modulating signal is constrained to remain between the minimum and maximum magnitudes of
the triangular carrier signal. Fig. 37.2 illustrates one such case where the triangular carrier signal
varies between -1.0 and +1.0 units of voltage and the magnitude of the modulating wave is kept
at 0.4 unit of voltage. Now, the high frequency triangular carrier waveform is compared with the
dc modulating signal and the comparator output is used to control the high and low level
switches (SU and SL respectively) of the inverter pole shown in Fig. 37.2.
A
+
0.5Edc _ SU
Time in m.sec.
+ Edc
_ Pole
+VCC 0.5Edc O Voltage
Q +
VAO 0.5Edc _ SL
-VCC - 0.5Edc
Fig. 37.2: Inverter pole voltage for a pure dc modulating waveform

The figure also shows the comparator output (Q) and the pole voltage (VAO) waveforms for this
case. As can be seen, with pure dc modulating signal the pole voltage consists of pulses of
identical shapes repeating at carrier frequency. The Fourier series decomposition of pole voltage
waveform results into a mean (dc) voltage and harmonic voltages whose frequencies are integral
multiples of carrier frequency. By using simple mathematics the high-duration of the pulses ( th ),
during which the pole voltage magnitude is 0.5Edc, can be found to be

Tc V
th = (1 + m ) ………………………………………………………………….... (37.1),
2 Vlc
where Tc is the time period of the triangular carrier waveform, Vm is the magnitude of the
modulating signal and Vl is the peak (positive) magnitude of the carrier signal.
c
In a similar manner the low-duration ( tl ) of pulses during which the pole voltage magnitude is -
0.5Edc, can be found as:
Tc V
tl = (1 − m ) …………………………………………………………………... (37.2)
2 Vlc
The dc component of the pole voltage ( V0 ) can be found to be
Vm
V0 = 0.5 Edc …………………………………………………………………... (37.3)
Vl
c
The dc modulating signal could acquire any magnitude between + Vlc and - Vlc and accordingly the
mean magnitude of pole voltage can vary within +0.5Edc and -0.5Edc. When the modulating
signal magnitude ( Vm ) is zero, the high and low durations of the pole output pulses will be
identical and the mean pole voltage magnitude will be zero.
As mentioned before, apart from the dc component, the pole voltage consists of harmonics of
integral multiples of carrier frequency. The lowest order harmonic-frequency being same as the
carrier frequency.
37.2 Pole Voltage Waveform With Sinusoidal Modulating Signal

In the previous section a pure dc modulating signal was considered. Let now a slowly varying
sinusoidal voltage, with the following constraints, be considered as the modulating signal:
1. The peak magnitude of the sinusoidal signal is less than or equal to the peak magnitude of
the carrier signal. This ensures that the instantaneous magnitude of the modulating signal
never exceeds the peak magnitude of the carrier signal.
2. The frequency of the modulating signal is several orders lower than the frequency of the
carrier signal. A typical figure will be 50 Hz for the modulating signal and 20 Kilohertz
for the carrier signal. Under such high frequency ratios, the magnitude of modulating
signal will be virtually constant over any particular carrier-signal time period.
Because of the above assumptions some results of the previous section, where a pure dc
modulating signal was considered, may be used. Since the slowly varying modulating signal is
virtually constant over a high frequency carrier time period, the mean magnitude of the inverter
pole voltage averaged over a carrier time period will be proportional to the mean magnitude of
the modulating signal. Thus the discretely averaged magnitude of pole voltage (averaged over
successive high frequency carrier time period) is similar to the modulating signal. The pole
voltage waveform thus has a low frequency component whose instantaneous magnitude is

proportional to the modulating signal (also implying that they will have same frequency and will
be in-phase). Apart from this low frequency component the pole voltage will also have high
frequency harmonic voltages. However, unlike in the case of pure dc modulating signal the
harmonic frequencies are now not simply integral multiples of carrier frequency. This is so
because here the widths of the high frequency pole-voltage pulses do not remain constant
through out. The pulse widths get modulated as per equations (37.1) and (37.2) due to slowly
varying modulating signal. As a result the harmonics in the pole voltage waveform are of
frequencies that are shifted from the carrier (and multiples of carrier frequency) by the integral
multiples of modulating wave frequency. In fact one gets a band of harmonic frequencies
centered around the carrier and integral multiples of carrier frequency. The individual
frequencies that form the band are displaced from these central frequencies by integral multiples
of modulating wave frequency. However, the modulating wave frequency being negligible
compared to the carrier frequency, the dominant harmonics are still in the vicinity of carrier
frequency and multiples of carrier frequency. A more detailed harmonic analysis of the sine-
modulated pole voltage waveforms is beyond the scope of this course. The low frequency
(modulating frequency) component of the pole output voltage is often referred as fundamental
frequency component.
Now, in some cases the ratio of carrier and modulating frequencies may not be very high but the
pole voltage still has a fundamental frequency component proportional to and in-phase with the
modulating signal. The essential advantage of having very high carrier frequency, in comparison
to the modulating wave frequency, is that the useful fundamental frequency component of pole
voltage and the unwanted harmonics (having frequencies close to the carrier and multiples of
carrier frequency) are far apart on the frequency spectrum and one can virtually filter away the
harmonic voltages without attenuating the magnitude of the fundamental frequency component
by putting a suitable low pass filter. The filter size requirement remains small if the harmonics
are of high frequencies. In some applications, like ac motor drive application, the inherent low
pass filtering characteristics of the motor-load itself is enough to satisfactorily block the flow of
harmonic currents to the load. In such cases the need for external filter may not arise.
It may be obvious that high carrier frequency calls for high switching frequency of the inverter
switches. In fact the switches turn-on and turn-off once during each carrier cycle. Generally the
switches used in high power applications (say, more than few hundred kW) can be switched only
at sub kilohertz frequency and hence the carrier frequency cannot be arbitrarily high. The
switching frequency related losses are also to be considered before deciding the carrier frequency
of the sine-PWM inverter.
What Is Modulation Index?

Modulation index is the ratio of peak magnitudes of the modulating waveform and the carrier
waveform. It relates the inverter’s dc-link voltage and the magnitude of pole voltage
(fundamental component) output by the inverter. Now let ‘ Vm m sin(ω t ) ’ be the modulating signal
and let the magnitude of triangular carrier signal vary between the peak magnitudes of + Vl and -
c
Vlc . The ratio of the peak magnitudes of modulating wave ( Vm l

m ) and the carrier wave ( Vc ) is
defined as modulation-index ( m ). In other words:

Vm
m= m
…………………………………………………………………... …...(37.4)
l
V
c
Normally the magnitude of modulation index is limited below one (i.e., 0< m <1). From the
discussion in the previous section it can be concluded that for 0< m <1, the instantaneous
magnitude of fundamental pole voltage (VAO,1) will be given by:
VAO,1 = 0.5Edc( m sin ω t ) ………………………………………………... …....(37.5),
where ‘ ω ’ is the angular frequency of the modulating waveform. For m = 1 the pole output
1
voltage (fundamental component) will have a rms magnitude of 0.35Edc (= Edc). This
2 2
magnitude, as can be found out from Sec. 34.1 of Lesson 34, is only 78.5% of the fundamental
pole voltage magnitude output by a square wave inverter operating from the same dc link
voltage.
What Is Over-Modulation?
When the peak magnitude of modulating signal exceeds the peak magnitude of carrier signal
(resulting in m >1), the PWM inverter operates under over-modulation. During over-modulation
the fundamental component of the pole voltage increases slightly with increase in modulation
index but the linear relation between them, as shown by Eqn. (37.5), no longer continues. Also,
lower frequency harmonics crop up in the pole-output waveform. It may easily be seen that for
‘ m ’ very high (say m = infinity), the pole voltage shape will be identical to the square wave
shape discussed in Lesson-34. Over modulation is generally not preferred because of the
introduction of lower frequency harmonics in the output waveform and subsequent distortion of
the load current.
37.3 A 1-Phase Sine-PWM Inverter Of H-Bridge Topology

Lesson-34 shows the half bridge and full bridge topologies of a single phase square-wave
inverter. The single-phase full bridge is also called as H-bridge because of its resemblance with
the letter ‘H’. [The two legs (poles) of the inverter resemble the two vertical lines of ‘H’ and the
horizontal line denotes the load, which is connected to the pole output points.] The switches and
the load in a single-phase full bridge PWM inverter are connected exactly as in a square-wave
inverter circuit. The difference lies in the conduction pattern of the inverter switches. In the
square-wave inverter the switches conduct continuously for 1800 in each output cycle whereas in
PWM inverter large number of switching take place in each output cycle.
The half bridge sine-PWM inverter employing only one leg has already been described in the
previous section. The full bridge inverter employs one additional leg but the control signals of
the half bridge circuit may still be employed for switches of the other leg. As in the square-wave
inverter (Lesson-34) the diagonal switches of the two legs may be turned on together to produce
a load voltage that has double the magnitude of individual pole voltage. The PWM signals for
the high and low level switches of one leg (obtained by sine-triangle comparison) may again be
used for low and high level switches, respectively, of the other leg.

Modulating Modulating
Signal for Signal for
Pole-A Pole-B
Carrier
signal
0.5Edc
0
VAO
-0.5Edc
0.5Edc
0
VBO
-0.5Edc
Edc Angular freq. for fundamental
component in rad./sec
VAB
- Edc
Fig. 37.3: Sine-PWM waveforms for single-phase H-Bridge inverter
Alternately (also, preferably), the modulating waveform for the other leg may be inverted
(keeping the carrier waveform same). The two inverted modulating waveforms are then
compared with the same carrier waveform using two different comparators. The comparator
outputs, one for each leg, are then used to switch the high and low level switches as in the half
bridge circuit.
Fig.37.3 shows the relevant waveforms that use two inverted sine waves as modulating signals
for the two legs of the inverter. For better visibility the ratio between the carrier and modulating

wave frequencies has been assumed equal to ‘eight’ (normally carrier frequency is much higher)
and circuit waveforms for only part of the modulating wave cycle has been shown. In Fig.37.3,
the blue colored modulating wave is used for pole-A of the inverter and the green colored for
pole-B. The corresponding pole voltages (VAO, VBO) and the load voltage (VAB) are also shown
in the figure.
The scheme, using two inverted modulating waves, has the following advantages over the one
that uses single modulating wave and employs simultaneous switching of the diagonal switches
of the two legs:- (i) Overall harmonic distortion of the load voltage waveform is reduced and (ii)
the frequency of the ripple voltage in the load waveform doubles. Both these points may be
verified by mere inspection of the load voltage waveform shown in Fig.37.3. In case of single
modulating wave, the instantaneous load voltage has double the amplitude of pole-A voltage and
thus the harmonic distortion of the load voltage and pole voltage remains same. It may be noted
that the instantaneous magnitude of load voltage, in this case, has two levels (+0.5Edc and -
0.5Edc). In the alternate scheme, using two inverted modulating waves, the load voltage has
double the number of pulses per carrier time period, thus doubling the ripple frequency. Now,
higher the frequency of unwanted ripple-voltage, easier it is to filter out the ripple current. Also,
the load voltage now has three levels (+0.5Edc, zero, and -0.5Edc). Presence of zero duration
reduces the rms magnitude of the overall load voltage (fundamental component along with
harmonics), while keeping the magnitude of fundamental component of load voltage same as in
the previous case (the rms of the overall load voltage for the two-level waveform equals Edc).
Thus the overall distortion of the load voltage waveform is less.
37.4 Generation Of 3-Phase Sine-PWM Waveform

A three-phase inverter, as discussed in Lessons 36, can be used to output a three-phase sine
modulated pole-voltage pulses. Switches in each of the three poles of the inverter are
individually controlled as per the technique discussed in the previous section. For a balanced
three-phase output voltage from the inverter poles, the three sinusoidal modulating signals (one
for each pole) must also be balanced three-phase signals. The carrier waveform for all the three
poles may remain identical. The fundamental components of individual pole output voltages (for
0< m <1) will thus be proportional to the corresponding modulating signals. For m = 1, the rms
magnitude of line-to-line voltage (fundamental component) output by the inverter will be equal
3
to Edc (= 0.612Edc). A typical line voltage waveform (difference of two pole voltage
2 2
waveforms) will appear similar to the line voltage waveform (VAB) shown in Fig.37.3.
37.4 A Typical Circuit For Generation Of PWM Waveforms

As mentioned in the preceding section, a three-phase sine-PWM inverter would require a
balanced set of three sinusoidal modulating signals along with a triangular carrier signal of high
frequency. For a variable-voltage-variable-frequency (VVVF) type inverter, a typical
requirement for adjustable speed drives of ac motors, the magnitude as well as frequency of the
fundamental component of inverter’s output voltage needs to be controlled. This calls for
generation of three-phase balanced modulating signals of variable magnitude and frequency
which it may be emphasized, need to have identical magnitudes and phase difference of 120
degrees between them at all operating frequencies.

Generating a balanced three phase SINE waveforms of controllable magnitude and frequency is
a pretty difficult task for an analog circuit and hence a mixed analog and digital circuit is often
preferred. Fig. 37.4 shows a scheme, in block diagram, where the 3-phase analog SINE waves
are generated with the help of EPROMs, D/A converters etc.
EPROM#1 SINE
D/A
Frequency (1K) loaded Wave
Converter
Control with SINE #1
Wave Data +V
+V
Voltage to Divide by 10 bit Ref. Volt.

8 bit VM
VC Freq. (V/f) 210 address Data
Converter counter
EPROM#2 D/A
loaded with Converter
1200 shifted #2
SINE Data
1200 shifted
SINE Wave
Fig.37.4: Schematic circuit for generation of balanced sinusoidal signals
In the circuit of Fig.37.4, two EPROMs are loaded with discrete values of SINE wave. The first
EPROM contains Sin(Φ) values and the second EPROM contains Sin(Φ-1200) , for 00 < Φ <
3600. Let us assume that the EPROMs have 1K (=1024) memory locations. In EPROM#1 Sin(Φ)
values are stored serially at discrete but regular intervals of Φ values. Accordingly the first
location of EPROM#1 contains Sin(00) in digital form, i.e., all the bits are zeroes. The second
memory location contains Sin(3600/1024) in the digital form and so on. Similarly the first
memory location of EPROM#2 contains Sin(1200) and second memory location has Sin(1200 +
3600/1024) in digital form. The contents of a particular memory location can be accessed
asynchronously by feeding the corresponding address word. A 1K EPROM will have 10 address
lines. All address bits, when zero, point to first memory location. As the address word
increments the subsequent memory locations are addressed. The EPROMs generally have a 8 –
bit word length. Now, Sin(Φ) value, over the full range of Φ, may either be positive or negative.
So while digitizing them care must be taken to identify one bit of the word as the sign bit. For
example, in the 8 bit (byte length) word the MSB may be used as sign bit with the understanding
that if this sign bit is zero the number is positive and if this bit is 1 the number is negative
(alternately, one may store ‘1+ Sin(Φ)’ in the memory and the need to store negative numbers
will not arise). Leaving one bit (say MSB) as sign bit the 0.0 to 1.0 scale of Sin(Φ) magnitude is
divided in 27 = 128 equal parts and accordingly the SINE value is digitized. Thus when Sin(Φ) =
1/128 the word to be stored should be 0000 0001. For lesser but positive value of Sin(Φ) the
word is 0000 0000. If, for example, Sin(Φ) = -1/64, the word to be stored should be 1000 0010.
Here “1” at the MSB location indicates that the number is negative. As seen in the block diagram
of Fig.37.4, each EPROM output is fed to a D/A (Digital to Analog) converter to finally come up
with analog value of Sin(Φ). Now in the D/A converter, the sign bit is not to be fed. The MSB
input of D/A could be grounded. A separate simple logic circuit could take the MSB output of
EPROM for sign changing of the D/A output. One such simple arrangement (Fig.37.5) uses an

analog switch, an op-amp and a few resistors to assign correct sign to the analog output of the
D/A converter.
R
Sign
Corrected
R -
D/A output
O/P Op-
+ Amp
of
D/A
Analog
Switch
1 = ON
0 = Off { MSB of
EPROM
GND
Fig.37.5: A simple sign corrector Circuit
As mentioned earlier, an alternative arrangement for storing data in the EPROM could be to store
[1+ Sin(Φ)] value in the memory locations so that negative numbers are not encountered. While
decoding the digital value into analog form (using Digital to Analog converter) the analog
equivalent of this extra “1” may be subtracted using a simple Op-amp based subtractor circuit.
In the circuit of Fig.37.4, a control voltage VC is applied to a voltage to frequency (V/f)

converter. The V/f converter should preferably have a linear relation between the applied voltage
and output frequency. The V/f converter output is fed as clock to a divide by 210 ripple counter
circuit. Ten address lines for the 1K EPROM are connected to the ten output lines of the ripple
counter. For a 2K EPROM eleven address lines are required and the appropriate counter would
then be a divide by 211 counter. The consecutive clock pulses to the ripple counter increment the
EPROM’s address word sequentially, pointing to the next EPROM memory location after each
clock. The EPROM outputs data of the addressed memory location asynchronously. Since the
SINE wave data is loaded in the EPROM sequentially, the digital value of SINE wave is output
by the EPROM in the correct sequence. The D/A converter then converts the EPROM output
into an analog signal. The SINE wave output by D/A converter is however only a stepped
approximation of the continuous SINE wave but the number of steps per sine-wave cycle being
large (=612), the resolution is sufficient for the present purpose. The Address lines for the two
EPROMs are tied together. Thus when, say, first memory location of EPROM#1 is addressed the
first location of EPROM#2 is also simultaneously addressed. The SINE waves stored in the two
EPROMs are phase shifted by 1200 and hence the corresponding D/A converters output 1200
shifted SINE waves. The ten-bit address word generated by ripple counter repeats after 1024
counts and accordingly SINE wave data from the EPROMs are also repeated after 1024 counts
(this count represents one output cycle time period of the sinusoidal modulating wave). The rate
at which the address bus data changes decides the frequency of the output waveform, which
eventually is controlled by the control voltage VC. D/A converters have reference voltage (+VRef
and - VRef) pins provided for setting the maximum and minimum excursion of the output voltage
waveform. In the circuit of Fig.37.4, it is assumed that -VRef pins are grounded and +VRef pins
are connected to the reference voltage ‘VM’. Thus ‘VM’ decides the magnitude of analog

sinusoidal signal output by the D/A converter. The magnitude control signal ‘VM’ may be tied to
frequency control signal ‘VC’ and one may achieve proportional change in inverter’s output
voltage and frequency. The circuit in Fig.37.4 produces two SINE waveforms having identical
magnitude and frequency but phase shifted by 1200. The third modulating SINE wave could be
generated simply by adding these two waveforms followed by a sign inversion. [Sin(Φ) + Sin(Φ-
1200) = - Sin(Φ-2400)]. Thus a simple circuit using a couple of op-amps will get the third SINE
wave.
High frequency triangular carrier waveform generator and comparator etc. are pretty simple
circuits to realize. The comparator output gives the required PWM pattern. The output frequency
(as well as magnitude) can be varied in an open-loop or closed-loop by varying the control
voltages VC and VM.
Quiz Problems
(1) The over-modulation of sine-PWM inverter is generally avoided because it introduces:
(a) lower frequency harmonics in the inverter output waveform
(b) non-linearity between the magnitudes of modulating signal and fundamental voltage
output by the inverter
(c) both the above
(d) none of the above
(2) A three-phase sine-PWM inverter operates from a dc link voltage of 600 volts. For
modulation index = 1.0 the rms magnitude of line voltage of fundamental frequency will
be equal to:
(a) 600 volts
(b) nearly 367 volts
(c) nearly 481 volts
(d) nearly 581 volts
(3) The carrier waveform of a sine-modulated PWM inverter is of 10 kHz frequency. When
the fundamental output frequency of the inverter is 50 Hz, the inverter switches need to
be turned-on and turned-off at a rate of
(a) 1000 times per second
(b) 10,000 times per second
(c) 50,000 times per second
(d) 50 times per second
(4) A three-phase sine-modulated PWM inverter is used to get a balanced 3-phase

fundamental output voltage. The modulating waveforms must have
(a) Three DC signals of identical magnitude
(b) Three balanced ac signals of fundamental frequency
(c) Three identical and in-phase ac signals of fundamental frequency
(d) Three balanced ac signals of carrier frequency
Answers to Question Problwm: 1-c, 2-b, 3-b, 4-b.

Module
5
DC to AC Converters
Lesson
38
Other Popular PWM
Techniques
After completion of this lesson, the reader shall be able to:
1. Explain the concept of sine+3rd harmonic modulated PWM inverter
2. Explain Space-Vector based PWM (SVPWM) technique
3. Estimate output voltage of the inverter using above PWM techniques
4. Compare at least five different PWM techniques for a 3-phase inverter
Lessons-36 and 37 have dealt with PWM inverters. As pointed out in these lessons, the two main
advantages of PWM inverters in comparison to square-wave inverters are (i) control over output
voltage magnitude (ii) reduction in magnitudes of unwanted harmonic voltages. It was also
shown that PWM results in lower magnitude of output voltage of fundamental frequency. In the
context of SPWM (Lesson-37) it was seen that good quality output voltage requires the
modulation index (m) to be less than or equal to 1.0. For m>1 (over-modulation), the
fundamental voltage magnitude increases but at the cost of decreased quality of output
waveform. The maximum fundamental voltage that the SPWM inverter can output (without
resorting to over-modulation) is only 78.5% of the fundamental voltage output by square-wave
inverter. In this lesson some more PWM techniques have been introduced. The merits and
demerits of different PWM techniques may be compared under comparable circuit conditions on
the basis of factors like (i) quality of output voltage (ii) obtainable magnitude of output voltage
(iii) ease of control etc. The peak obtainable output voltage from the given input dc voltage is
one important figure of merit for the inverter and has been discussed in some more detail below.
38.1 How To Get More Output Voltage From The Same DC Bus
Voltage?
The inverter switches need to be rated to withstand the peak magnitude of input dc link voltage,
the maximum expected load current and should be able to safely dissipate the heat generated in
the switch due to conduction and switching losses. Because of high frequency switching, the
switches in PWM inverters have significantly more switching loss than in square wave inverters.
Often the switch chosen in PWM inverters is oversized, in terms of its current rating, so that the
sum total of switching loss and conduction loss remains well within the heat dissipation
capability of the switch and the associated heat sink. One may talk of the VA rating of the
switch, being the product of the switch voltage and current ratings. The switch cost may be
roughly taken as proportional to its VA rating. The VA rating of the inverter equals the
maximum VA of load power (considering only the fundamental component of output voltage
and current) that the inverter may output. On account of higher fundamental output voltage and
less switching loss, a square-wave inverter will produce a higher VA (for the given switch VA
ratings) than a PWM inverter. The square wave inverter can use slower switches, requires
simpler control circuit and thus the inverter cost comes further down. However due to better
quality of output voltage (and hence current), PWM inverters may be unavoidable in many
applications.
For identical magnitudes of switching frequency and switch voltage stress some particular PWM
techniques may allow more output voltage than other PWM techniques (in spite of comparable
quality of output voltages). Sometimes the lower achievable output voltage may mean that the
inverter is not suitable for given application. For example, consider a typical case where a 3-
phase 400 volts rated induction motor is to be fed from a PWM inverter for a wide range of
speed control. The dc bus voltage to the inverter is, in most cases, achieved after rectifying the 3-

phase utility ac supply. Often a three-phase diode bridge rectifier followed by a large filter
capacitor is used to get dc bus voltage. The magnitude of dc bus voltage, so achieved, may be
considered close to the peak magnitude of supply line voltage. For 400 volts, 50 Hz, 3-phase
supply system the dc bus voltage will be around 566 volts (i.e. 400√2 volts). Now using a
SPWM inverter with a dc link voltage of 566 volts, one can output maximum rms line voltage of
347 volts only (= 0.612 Edc, as shown in Sec. 37.4 of Lesson-37). The SPWM inverter will, thus,
not be able to meet the rated voltage demand of 400 volts for the motor. Instead of SPWM
inverter, had one used a square wave inverter, the maximum magnitude of line voltage
(fundamental component) output by the inverter would have been 441 volts (= 0.78 Edc, as per
Sec. 35.2, Lesson-35). Thus, on account of lower output voltage a SPWM inverter may be
unsuitable in certain application. Fortunately, there are some other PWM techniques that can
output good quality line voltage waveforms (similar to SPWM inverter) and can output higher
voltage. In this lesson two such popular PWM techniques namely, sine+3rd harmonic modulation
and space vector modulation techniques have been described. Later two more PWM techniques
that were briefly touched upon in Lesson-36 have been elaborated further.
38.2 Sine + 3rd Harmonic PWM Technique

The idea of Sine+3rd harmonic modulation technique is based on the fact that the 3-phase
inverter-bridge feeding a 3-phase ac load does not provide a path for zero-sequence component
of load current. As shown in Lessons-35 & 36, only three output points are brought out from a
three-phase inverter-bridge. These output points are connected to the three supply terminals of
the load. Such an arrangement does not cause any confusion for the delta connected load but for
a star connected load the neutral point remains floating. However for a balanced, three-phase,
star-connected load this should not be a drawback as the fundamental component in the load
phase voltage is identical to the fundamental component of inverter’s pole voltage. In fact, the
floating neutral point has the advantage that no zero sequence current (which includes dc, third
and integer multiples of third harmonics) will be able to flow through the load and hence even if
the pole voltage is distorted by, say, 3rd and integral multiples of third harmonics the load side
phase and line voltages will not be affected by these distortions. The Sine+3rd harmonic PWM
technique is a modification over the SPWM technique discussed in Lesson-37 wherein
deliberately some amount of third harmonic voltage is introduced in the pole voltage waveform.
Accordingly a suitable amount of third harmonic signal is added to the sinusoidal modulating
signal of fundamental frequency. Now, the resultant waveform (modified modulating signal) is
compared with the high frequency triangular carrier waveform. The comparator output is used
for controlling the inverter switches exactly as in SPWM inverter. Thus, as brought out in
Sec.37.2 of Lesson-37, the low frequency component of the pole voltage will be a replica of the
modified modulating signal provided (i) The instantaneous magnitude of the modified
modulating signal is always less than or equal to the peak magnitude of the carrier signal and (ii)
the carrier frequency is significantly higher than the frequency of modulating signal.
Accordingly, the pole voltage of Sine+3rd harmonic PWM inverter has same composition of
fundamental and third harmonic as in the modified modulating signal. However, as per the
earlier discussion, the third harmonic component of pole-voltage will not appear in the load
phase and line voltages. The advantage of adding small amount of third harmonic in the
modulating waveform is that it brings down the peak magnitude of the resultant modulating
waveform. The modified modulating waveform appears more flat topped than its fundamental
component. Thus if the fundamental sinusoidal modulating wave had a peak magnitude equal to
the peak magnitude of the triangular carrier wave (corresponding to modulation index ‘m’ = 1.0),

the addition of small percentage of 3rd harmonic to the fundamental wave causes the peak
magnitude of the combined signal to become lower than triangle wave’s peak magnitude.
1.1547 Sin(ωt)
0.193 Sin(3ωt)
ωt in radians
Fig. 38.1: The modulating signal for Sine+3rd harmonic modulation
In other words, a fundamental frequency signal having peak magnitude slightly higher than the
peak magnitude of the carrier signal, if mixed with suitable amount of 3rd harmonic may result in
a modified signal of peak magnitude not exceeding that of the carrier signal. Thus the peak of the
modulating signal remains lower than the peak of triangular carrier signal and still the
fundamental component of output voltage has a magnitude higher than what a SPWM can output
with m = 1.0. As described earlier the load sees only the fundamental component of pole voltage
(and not the third harmonic) and thus the achievable load (output) voltage magnitude is higher
than that of SPWM inverter. It is to be noted that higher output voltage is achieved without
compromising on the quality of the output waveform. Fig. 38.1 illustrates this logic, wherein
[1.1547 Sin(ωt) +0.193 Sin(3ωt)] is the modulating waveform with a resultant peak magnitude
of just 1.0. A higher amount of third harmonic will cause the magnitude limit to be exceeded.
Thus the fundamental voltage output by the inverter employing Sine+3rd harmonic modulation
technique can be higher by nearly 15.47% than a simple SPWM inverter. Now let the practical
example of 400 volt rated induction motor drive considered in Sec. 38.1 be reconsidered but with
an inverter employing sine +3rd harmonic modulation. The maximum output voltage can now go
to 347*1.1547 volts = 400 volts and the peak voltage requirement of the drive will be met.
38.3 Space Vector PWM (SV-PWM) Technique

The space vector modulation technique is somewhat similar to the Sine+3rd harmonic PWM
technique but the method of implementation is different. Before going into details of this
technique, it would be useful to explore the concept of voltage space-vector, in analogy with the
concept of flux space-vector as used in three-phase ac machine. The stator windings of a three-
phase ac machine (with cylindrical rotor), when fed with a three-phase balanced current produce
a resultant flux space-vector that rotates at synchronous speed in the space. The flux vector due
to an individual phase winding is oriented along the axis of that particular winding and its
magnitude alternates as the current through it is alternating. The magnitude of the resultant flux
due to all three windings is, however, fixed at 1.5 times the peak magnitude due to individual

phase windings. The resultant flux is commonly known as the synchronously rotating flux
vector.
Now, in analogy with the fluxes, if a three phase balanced voltage is applied to the windings of a
three-phase machine, a rotating voltage space vector may be talked of. The resultant voltage
space-vector will be rotating uniformly at the synchronous speed and will have a magnitude
equal to 1.5 times the peak magnitude of the phase voltage. Fig. 38.2 (a) shows a set of three-
phase balanced sinusoidal voltages. Let these voltages be applied to the windings of a three-
phase ac machine as shown in Fig. 38.2(b). Now, during each time period of the phase voltages
six discrete time instants can be identified, as done in Fig. 38.2(a), when one of the phase
voltages have maximum positive or negative instantaneous magnitude. The resultants of the
three space-voltages at these instants have been named V1 to V6. The spatial positions of these
resultant voltage space-vectors have been shown in Fig. 38.2(b). At these six discrete instants,
these vectors are aligned along the phase axes having maximum instantaneous voltage. As shown
in Fig. 38.2(a) the magnitude of these voltage vectors is 1.5 times the peak magnitude of
individual phase voltage.
The instantaneous voltage output from a 3-phase inverter, discussed in earlier lessons, cannot be
made to match the three sinusoidal phase voltages of Fig. 38.2(a) at all time instants. This is so
because the inverter outputs are obtained from rectangular pole voltages and contain, apart from
the fundamental, harmonic voltages too. However, the instantaneous magnitudes of the inverter
outputs and the sinusoidal voltages can be made to match at the six discrete instants (talked
above) of the output cycle. At these six discrete instants one of the phase voltages is at its
positive or negative peak magnitude and the other two have half of the peak magnitude. The
polarity of the peak phase-voltage is opposite to that of the other two phase-voltages. A similar
pattern is seen in the instantaneous phase voltages output by a 3-phase inverter and is explained
below.
Fig. 38.3 shows a three-phase voltage source inverter whose output terminals are fed to the three
terminal of a three-phase ac machine (in fact to any three-phase balanced load). From the
knowledge of 3-phase voltage source inverters, it may be obvious that the two switches of each
inverter pole conduct in a complementary manner. Thus the six switches of the three poles will
have a total of eight different switching combinations. Out of these eight combinations, two
combination wherein all the upper switches or all the lower switches of each pole are
simultaneously ON result in zero output voltage from the inverter. These two combinations are
referred as null states of the inverter. The remaining six switching combinations, wherein either
two of the high side (upper) switches and one of the low side (lower) switch conduct, or vice-
versa, are active states. During the six active states the phase voltages output by the inverter to a
balanced 3-phase linear load are as detailed in Sec.35.1 of Lesson 35. Accordingly instantaneous
magnitude of two of the phase voltages are 1/3rd Edc and the third phase voltage is 2/3rd Edc
(where Edc is the dc link voltage). The voltage polarities of the two phases getting 1/3rd Edc are
identical and opposite to the third phase having 2/3rd Edc. Fig. 38.3 also shows, in a tabular form,
the instantaneous magnitudes of the three load-phase voltages (normalized by the dc link voltage
magnitude) during the six active states of the inverter. The switching states of the inverter have
been indicated by a 3-bit switching word. The 1st (MSB) bit for leg ‘A’, 2nd bit for leg ‘B’ and 3rd
bit for leg ‘C’. When a particular bit is 1, the high (upper) side switch of that leg is ON and when
the bit is 0, the low side switch is ON. Thus a switching word 101 indicates that high side
switches of legs ‘A’ and ‘C’ and low side switch of leg ‘B’ conduct. The resulting voltage
pattern is identical to the voltage pattern of space voltage vector V1 of Fig. 38.2 provided 2/3rd

Edc equals the peak magnitude of phase voltage in Fig. 38.2. The table given in Fig. 38.3 shows
how six active states of the inverter produce space voltage vectors V1 to V6 that can be identified
on one to one basis with the six voltage vectors of Fig. 38.2. There are some important
differences between the resultant space voltage vectors due to the sinusoidal phase voltages of
Fig. 38.2 and the space voltage vectors formed by the inverter output voltages. These are
described in the next section.
V1 V2 V3 V4 V5 V6 V2
A
VAn VBn VCn V1 V3
ωt in
rad/sec n
C
B V4
V6
V5
(a) (b)
Fig. 38.2: The concept of voltage space-vectors: (a) 3-phase balanced voltages
(b) The voltage space-vectors
Switch
QAU QBU QCU states (V1) (V2) (V3) (V4) (V5) (V6)
101 100 110 010 011 001
+ A vAn 1/3 2/3 1/3 -1/3 -2/3 -1/3
_ EDC B
vBn
C -2/3 -1/3 1/3 2/3 1/3 -1/3
QAL QBL QCL vCn 1/3 -1/3 -2/3 -1/3 1/3 2/3
Fig. 38.3: Space vectors output by a 3-phase voltage source inverter
38.3.1 Smoothly Rotating Space Voltage Vector From Inverter

The continuously varying sinusoidal waveforms, as shown in Fig. 38.2, result in a space voltage
vector of fixed magnitude rotating at fixed (synchronous) speed in the space. If the inverter could
have produced ideal sinusoidal 3-phase voltages, the resultant space voltage vector would have
also moved smoothly in space with constant magnitude and constant angular speed. However by
now the reader would know that the practical power electronic inverter could never produce the
perfectly ideal sinusoidal voltages. In fact when the inverter switches from one active state to
another, the space voltage vector changes its direction abruptly, the abrupt change in direction

being in multiples of 60 electrical degrees. If at a time only one bit of the inverter switching
word changes (i.e., only one leg of the inverter changes the switching state) the abrupt change in
space vector direction is by 60 electrical degrees.
Knowing that the inverter cannot produce ideal sinusoidal voltage waveforms, a good PWM
inverter aims to remove low frequency harmonic components from the output voltage at the cost
of increasing high frequency distortion. The high frequency ripple in the output voltage can
easily be filtered by a small external filter or by the load inductance itself. In terms of voltage
space vectors the above trade-off between low and high frequency ripples means that the
resultant voltage vector will have two components; (i) a slowly moving voltage vector of
constant magnitude and constant speed superimposed with (ii) a high frequency ripple
component whose direction and magnitude changes abruptly.
The space-vector PWM technique aims to realize this slowly rotating voltage space vector
(corresponding to fundamental component of output voltage) from the six active state voltage
vectors and two null state vectors. The active state voltage vectors have a magnitude = Edc and
they point along fixed directions whereas null state vectors have zero magnitude. Fig. 38.4 shows
the voltage space-vector plane formed by the active state and null state voltage vectors. The null
state voltage vectors V7 and V8 are each represented by a dot at the origin of the voltage space
plane. The switching word for V7 is 000, meaning all lower side switches are ON and for V8 is
111, corresponding to all upper side switches ON. The active-state voltage space vectors point
along directions shown previously in Fig. 38.2(b). A regular hexagon is formed after joining the
tips of the six active voltage vectors. The space-plane of Fig. 38.4 can be divided in six identical
zones (I to VI). The output voltage vector from the inverter (barring high frequency
disturbances) should be rotating with fixed magnitude and speed in the voltage plane. Now it is
possible to orient the resultant voltage space-vector along any direction in the space plane using
the six active vectors of the inverter. Suppose one needs to realize a space voltage vector along a
direction that lies exactly in the center of sector-I of the space-plane shown in Fig.38.4. For this
the inverter may be continuously switched (at high frequency) between V1 and V2 active states,
with identical dwell time along these two states. The resultant vector so realized will occupy the
mean angular position of V1 and V2 and the magnitude of the resultant vector can be found to be
0.866 times the magnitude of V1 or V2 (being the vector sum of 0.5 V1 and 0.5 V2). Further, the
magnitude of the resultant voltage vector can be controlled by injecting suitable durations of null
state.
V2 (100)
(101) V1 I V3 (110)
II
V7
VI III
V8
(001) V6 V IV V4 (010)
V5 (011)
Fig. 38.4: The voltage space-vectors output by a 3-phase inverter
In general both magnitude and direction control of the resultant voltage vector can be achieved
by properly controlling the dwell times of two adjacent active voltage vectors and null voltage
vectors. The two active state vectors chosen are the ones that define the boundary of the space-
plane sector in which the desired resultant vector lies. The following illustrative example may be
helpful.
Example:
Let us assume that a resultant vector ‘VX’ of magnitude α(Edc), lying in sector-I and making an
angle ‘θ’ from active vector V1 is to be realized (Fig. 38.5). Let us further assume that TS is the
sampling time for which the desired vector VX may be assumed to be stationary in space along
the described direction. Now as per the above discussion the desired vector is to be realized
using active vectors V1, V2 and null vectors V7, V8. Let the respective dwell time along these
vectors be t1, t2, t7 and t8 such that
t1+ t2 + t7 + t8 = TS ----------------------------------------------- (38.1)
V2 (100)
V1 VX
(101)
θ
Sector-I
Fig. 38.5: The voltage space-vectors output by a 3-phase inverter

t1 t
Now the resultant space vector VX is the vector sum of ( V1 ) and 2 ( V2 ) , where V1 and V2
TS TS
are space vectors, each having magnitude Edc. Thus, according to vector algebra,
t t
α = 1 Cosθ + 2 Cos π − θ
TS TS
(
3 ) -------------------------------- (38.2)
and
t1
TS
t
TS 3(
Sinθ = 2 Sin π − θ ) ------------------------------- (38.3)
From Eqns. (38.2) and (38.3), one can determine the fraction of sampling time during which the
inverter is along active states V1 and V2.

t
Accordingly, 1 =
α
=
3(
αSin π − θ )
( ))
-------------------- (38.4)
TS Cosθ + SinθCot π − θ
3 ( Sin π
3 ( )
t2 α αSinθ
= =
( ( )) ( )
and ----------- (38.5)
TS
3 )
Cos π − θ + CotθSin π − θ
3 ( Sin π
3
The total null duration is generally equally divided between t7 and t8 and hence
⎛
t 7 = t 8 = 0.5 ⎜1 −
t1 t 2 ⎞
− ⎟ = 0.5 − 0.5α ⎜ 3 (
⎛ Sin π − θ + Sinθ ⎞)⎟
⎝ TS TS ⎠
⎜
⎜
⎝
Sin π
3 ( )
⎟⎟ ------------ (38.6)
⎠
Knowing the magnitude factor ‘α’ and the angular position ‘θ’ the inverter switching-pattern is
determined as per the above equations. Along any fixed direction ‘θ’, the magnitude of the
voltage space vector is controlled by controlling the null duration time. For maximum magnitude
along a particular direction the null vector duration must be zero. Thus, from Eqn. (38.6) one can
determine the maximum possible voltage magnitude factor ‘αmax’ along ‘θ’ as
α max =
( )
Sin π
3
( )
Sin π − θ + Sinθ
3
-------------------------------- (38.7)
As θ is varied in the range 0 ≤ θ ≤ π , the minimum magnitude of αmax is encountered at

3
θ = π and equals 0.866. Thus to have a rotating space voltage vector (fundamental component)
6
of uniform magnitude over the whole voltage space-plane, the upper limit on the voltage vector
magnitude will be 0.866 Edc. The tip of the corresponding space voltage vector falls on the
interior circle of the hexagon in Fig. 38.4. It may be recalled that the SPWM technique can
output maximum (corresponding to modulation index = 1.0) voltage space vector magnitude
E E
= 1.5 dc = 0.75E dc , where dc is the peak magnitude of fundamental phase voltage (Lesson-37)
2 2
and the factor 1.5 is due to the resultant of the three phases. Thus space-vector PWM technique
can output 1.1547 (=0.866/0.75) times more voltage, exactly as in Sine+3rd harmonic modulation
technique discussed in the beginning of this lesson (section 38.2).
38.3.2 Algorithm For Producing Sinusoidal Output Voltages Using

SV-PWM
As would be clear from the discussions in the above sections, the SV-PWM is concerned with
the control of inverter output voltages in a unified manner. It does not control the individual
phase voltages separately. The instantaneous magnitude and direction of the desired resultant
voltage vector is decided as per the frequency and magnitude of inverter’s fundamental output
voltage. The SV-PWM is best realized with the help of a digital computing device, like
microprocessor or Digital Signal Processor. The algorithm to be executed is outlined below:

(1) Get the input data like; input dc link voltage (Edc), desired output frequency ‘fOP’ (this
will determine the speed of the resultant voltage vector), desired phase sequence of
output voltage (will determine which way, clockwise or anticlockwise, the resultant
voltage vector is moving), desired magnitude of output voltage and the desired switching
frequency. It will be shown later that the switching frequency (fSW) and sampling time
period (TS) are related. During each sampling time period three switching take place,
where one turn-on and one turn-off is taken as one switching.
(2) Calculate magnitude factor ‘α’ from the knowledge of input dc link voltage and the
desired output voltage (α Edc = 3/2 times peak of phase voltage). Also, calculate the
sampling time period TS = 1/(3 fSW).
(3) Initialize sector position = I, and angle ‘θ’ = 0. Assume the rotating space voltage vector
to remain stalled at this position for the sampling time period ‘TS’. Calculate the time
duration for active and null state vectors as per Eqns. (38.4) to (38.6). Output the inverter
switching pulses as per the calculated time durations so as to realize the space vectors in
the following sequence: V8(111), V1 (101), V2 (100), V7 (000).
(4) Calculate the next position angle θ = 2TS πfOP + θold for clockwise rotation in the vector
space-plane of Fig. 38.4. The reader should be able to work out the changes when the
rotation is anti-clock wise. Recalculate the time durations as in step (3) above but this
time the switching sequence will be V7(000), V2 (100), V1 (101), V8 (111).
(5) Step (4) is to be repeated but every time the switching sequence alternates between the
sequences given in steps 4 and 5. This helps in reducing the switching losses. The reader
may note that this way there are only 3 switching per sampling period. The switching to
next space vector involves change of only one bit of the switching word (i.e., only one
turn-on and one turn-off). When the space vector enters sector-II (for θ ≥ π / 3 ), the
vector V1 is replace by V2 and V2 is replaced by V3. At the same time, angular position is
reset to a value within π / 3 ≥ θ ≥ 0 by subtracting 60 degrees from the old value. Every
time the voltage vector enters a new sector the angle θ is readjusted so that it varies
between 0 and 60 degrees. The active state vectors are also reassigned as described
above. The process continues to produce a continuously rotating voltage space vector of
fixed magnitude and fixed speed.
38.4 Some Other Popular PWM Techniques

By now the readers must be familiar with sine-PWM (SPWM), sine +3rd harmonic PWM and
space vector PWM (SV-PWM) techniques. In the following sections two more PWM techniques
are briefly touched upon. These are (i) selective harmonic elimination technique and (ii) current
controlled PWM (CCPWM) technique.
38.4.1 Selective Harmonic Elimination Technique

In Lesson-36 (sections 36.1 and 36.2) it was shown that some selected harmonics could be
eliminated from the inverter output voltage by introducing notches at suitable time instants
(angles) in the pole voltage waveform. To eliminate more number of unwanted harmonics from
the output one needs to have more notches per output cycle. For the required magnitude of
output voltage and frequency and the inverter’s dc bus voltage, these notch angles need to be

calculated off-line using digital computer and later used for generating the switching sequence.
The notch angle information for all three phases taken together can be converted into a matrix of
switching word for the inverter. The consecutive switching word information at short and regular
time interval (in time steps of, say, 10 microseconds) is stored for a full output cycle in
consecutive locations of a memory device, like, EPROM. To output the proper switching signal
these stored values are output sequentially by sequentially incrementing the address word of the
EPROM. The time rate at which the address changes should be identical to the time rate at which
the information was stored. The switching word information is then converted into gate control
signals for the inverter switches. As the inverter’s input and output parameters change, the
switching matrix changes too. For an inverter producing variable voltage, variable frequency
output the total requirement of memory size becomes large. However the cost of memory chips
is coming down and hence the scheme is one of the preferred PWM schemes.
38.4.2 Current Controlled PWM (CCPWM) Technique

In this technique, reference load current (as desired by the user) signals are generated and the
inverter switches are controlled so that the actual inverter phase currents match these within
tolerable error limits. The scheme requires current sensors to sense actual phase currents. For a
three-phase load, sensing two phase-currents suffices as the third phase current can be obtained
by algebraic manipulation of the other two. The actual currents are compared with the
corresponding reference currents to generate the required switching action. Most often hysteresis
type bang-bang controllers are used. To increase the magnitude of current leaving the inverter
pole (and entering the load terminal), the high side switch of the particular pole is turned on.
Conversely the low side switch is turned on to decrease the magnitude of load current. Turning
of high side switch causes input dc voltage to support the load phase current. The load phase
current flows against the input dc voltage when low side switch is ON. The control actions for
individual legs are generally independent of each other but the rate at which current changes in
one leg may get affected by the switching state of the other legs. The control required is simple
and the load current is directly controlled, hence the name CCPWM. The necessity of two
numbers of fast current sensors may be seen as a drawback but current sensor costs are coming
down and most inverter circuits employ current sensors, any way, for protection against over-
current. Another draw back of the scheme may be associated with the hysteresis controller, if
used. The switching frequency of such controllers becomes dependent on load parameters and
may not remain optimum for the given load. There are, however, other control schemes for
CCPWM inverter where the switching frequency can remain fixed in spite of load parameter
changes.
Quiz problems
1. For a dc link voltage of 142 volts, which of the following PWM schemes can produce
good quality line voltage (free from lower order harmonics) of 95 volts (rms) and 50 Hz.
(a) Sine PWM
(b) Sine+3rd harmonic PWM
(c) Space vector PWM
(d) all the above

2. The third harmonic component in the pole voltages of a 3-phase inverter, connected to a
balanced 3-phase load, affects:
(a) load-phase voltage
(b) load-line voltage
(c) load-phase current
(d) none of the above
3. An inverter designed to work with fixed input dc voltage is fed with a fluctuating dc
voltage. The basic controller for the following PWM scheme can still be used to output
good quality current of constant magnitude:
(a) Sine
(b) (b) Sine+3rd Harmonic
(c) (c) Space Vector
(d) (d) Current Controlled PWM
4. With 283 volts dc link voltage connected to a 3-phase inverter what maximum phase
voltage (rms magnitude) of good quality can be output by Sine PWM and Space Vector
PWM:
(a) 50 and 75 volts
(b) 100 and 115 volts
(c) 141 and 200 volts
(d) 200 and 282 volts
Answers: 1-b & c, 2-d, 3-d, 4-b.

Module
5
DC to AC Converters
Lesson
39
Current Source Inverter
• The circuit for single-phase Current Source Inverter (CSI) using thyristors
• Auto-Sequential Commutated mode of operation for 1-ph. Inverter (ASCI), with waveforms
• Three-phase Current Source Inverter (CSI) − circuit and operation, with waveforms
Introduction
In the previous six (5.1-5.6) lessons in this module, the circuit and operation of single-phase
and three-phase Voltage Source Inverters (VSI), with waveforms, were described in detail. Also,
the presence of harmonics in voltage waveforms, along with its reduction mainly by Pulse Width
Modulation (PWM) techniques, was presented. Presently, mainly self-commutated switching
devices, like say transistors, are used in the above circuits, replacing thyristors, with bulky
commutation circuits needed to turn them OFF, these being force-commutated ones. In the last
two (5.7-5.8) lessons in this module, the circuit and operation of different types of single-phase
and three-phase Current Source Inverters (CSI), with waveforms, will be described in detail. The
device used here is thyristor. In this lesson (5.7), initially, the circuit of single-phase CSI will be
presented. The Auto-Sequential Commutated mode of operation for this Inverter (ASCI), using
thyristors, will be discussed in detail, with waveforms. Then, the circuit and operation of three-
phase CSI, along with relevant waveforms, will be presented. Finally, the advantages and
disadvantages of CSI over VSI, in brief, are described
For the VSI, as the full form denotes, the output voltage is constant, with the output current
changing with the load − type, and/or the values of the components. But in the CSI, the current is
nearly constant. The voltage changes here, as the load is changed. In an Induction motor, the
developed torque changes with the change in the load torque, the speed being constant, with no
acceleration/deceleration. The input current in the motor also changes, with the input voltage
being constant. So, the CSI, where current, but not the voltage, is the main point of interest, is
used to drive such motors, with the load torque changing.
Keywords: Single-phase and Three-phase Current Source Inverter (CSI), ASCI mode of
operation, CSI using thyristors

Single-phase Current Source Inverter
I a
Th1 Th2
C1 = C/2
a + - I
I D1 I D2
L'
+ Load (L)
D4 D3
VS
+ -
b
I C2 = C/2
Th4 Th3
b
Fig. 39.1: Single phase current source inverter (CSI) of ASCI type.
The circuit of a Single-phase Current Source Inverter (CSI) is shown in Fig. 39.1. The type
of operation is termed as Auto-Sequential Commutated Inverter (ASCI). A constant current
source is assumed here, which may be realized by using an inductance of suitable value, which
must be high, in series with the current limited dc voltage source. The thyristor pairs, Th1 & Th3,
and Th2 & Th4, are alternatively turned ON to obtain a nearly square wave current waveform.
Two commutating capacitors − C1 in the upper half, and C2 in the lower half, are used. Four
diodes, D1–D4 are connected in series with each thyristor to prevent the commutating capacitors
from discharging into the load. The output frequency of the inverter is controlled in the usual
way, i.e., by varying the half time period, (T/2), at which the thyristors in pair are triggered by
pulses being fed to the respective gates by the control circuit, to turn them ON, as can be
observed from the waveforms (Fig. 39.2). The inductance (L) is taken as the load in this case, the
reason(s) for which need not be stated, being well known. The operation is explained by two
modes.

ig1,
ig3
0
T/2 T
ig2,
ig4
0
T/2 T
VCo
vC
0
t T/2 T
-VCo
t2
t1
i0
0
T/2 T
-I
I iC1 iD1 iD2

i01,
iD
0
T/2 T
-I
Th1 & Th3 Th2 & Th4 Th1 & Th3

triggered triggered triggered
Fig. 39.2: Voltage and current waveforms

Mode I: The circuit for this mode is shown in Fig. 39.3. The following are the assumptions.
Starting from the instant, t = 0 − , the thyristor pair, Th2 & Th4, is conducting (ON), and the
current (I) flows through the path, Th2, D2, load (L), D4, Th4, and source, I. The commutating
capacitors are initially charged equally with the polarity as given, i.e., vC1 = vC 2 = −VC 0 . This
mans that both capacitors have right hand plate positive and left hand plate negative. If two
capacitors are not charged initially, they have to pre-charged.
I a
I Th1 Th2
- +
e f
C1=C/2 I
D1 D2
I c d
L I
D4 D3
I - +
g h
C2=C/2
Th4 Th3
I
b
Fig. 39.3: Mode I (1 phase CSI)
At time, t = 0, thyristor pair, Th1 & Th3, is triggered by pulses at the gates. The conducting
thyristor pair, Th2 & Th4, is turned OFF by application of reverse capacitor voltages. Now,
thyristor pair, Th1 & Th3, conducts current (I). The current path is through Th1, C1, D2, L, D4,
C2, Th3, and source, I. Both capacitors will now begin charging linearly from ( − VC 0 ) by the
constant current, I. The diodes, D2 & D4, remain reverse biased initially. The voltage, v D1 across
D1, when it is forward biased, is obtained by going through the closed path, abcda
as v D1 + Vco − (1 /(C / 2) ) ⋅ ∫ I ⋅ dt = 0 It may be noted the voltage across load inductance, L is zero
(0), as the current, I is constant. So, v D1 = −Vco + (2 / C ) ⋅ ∫ I ⋅ dt
As the capacitor gets charged, the voltage v D1 across D1, increases linearly. At some time,
say t1, the reverse bias across D1 becomes zero (0), the diode, D1.starts conducting. An identical
equation can be formed for diode, D3 also. Actually, both diodes, D1 & D3, start conducting at the
same instant, t1. The time t1 for which the diodes, D1 & D3, remain reverse biased is obtained by
equating, v D1 = −Vco + ((2 ⋅ I ⋅ t1 ) / C ) = 0 . The time is given by, t1 = (C /(2 ⋅ I ) ) ⋅ VC 0 . The
capacitor voltages vC1 = vC 2 = vC , appear as reverse voltage across the thyristors, Th2 & Th4,
when the thyristors, Th1 & Th3, are triggered. The value of vC is

vC1 = vC 2 = vC = −Vco + (2 / C ) ⋅ ∫ I ⋅ dt , which, if computed at t = t1 , comes out as,
vC1 = vC 2 = vC (t1 ) = −Vco + ((2 ⋅ I ⋅ t1 ) / C ) = −Vco + ((2 ⋅ I ) / C ) ⋅ (C /(2 ⋅ I ) ) ⋅ VC 0 = 0 ,
using the value of t1 obtained earlier. This means that the voltages across C1 & C2, varies linearly
from − VC 0 to zero in time, t1. Mode I ends, when t = t1 , and vC = 0 . Note that t1 is the circuit
turn-off time for the thyristors.
a
I Th1 iC1 Th2

+ -
e
f
C1=C/2
D1 D2
L
I c d
i0
D4 D3
C2=C/2
+ -
g h
iC2
Th4 Th3
I
b
Fig. 39.4(a): Mode II (1-phase CSI)
I C
e (g) + -
f (h)
I ie
i0
c d
L
I
Fig. 39.4(b): Equivalent circuit for mode II
Mode II: The circuit for this mode is shown in Fig. 39.4a. Diodes, D2 & D4, are already
conducting, but at t = t1 , diodes, D1 & D3, get forward biased, and start conducting. Thus, at the
end of time t1, all four diodes, D1–D4 conduct. As a result, the commutating capacitors now get
connected in parallel with the load (L). For simplicity in analysis, the circuit is redrawn as

shown in Fig. 39.4b, where the equivalent capacitor is C / 2 , as C1 = C 2 = C . The equation for
the current at the node is, I + i0 = iC (= iC1 + iC 2 ) , where, iC1 = iC 2 = iC / 2 The voltage balance
equation is,
di
L ⋅ 0 = −(1 / C ) ⋅ ∫ iC ⋅ dt = = −(1 / C ) ⋅ ∫ ( I + i0 ) ⋅ dt
dt
d 2 i0 i0 I d 2 i0 i I
or, L ⋅ + = − or, + 0 =−
dt 2
C C dt 2
(L ⋅ C) (L ⋅ C)
2
d i
or, ( L ⋅ C ) ⋅ 20 + i0 = − I
dt
The solution of the equation is, i0 = A ⋅ cos (ω 0 ⋅ t ) + B ⋅ sin (ω 0 ⋅ t ) + K ,
where, A, B & K are constants, natural frequency,
( )
f 0 = 1 / (2 ⋅ π ) ⋅ ( L ⋅ C ) , ω 0 = (2 ⋅ π ) ⋅ f 0 = 1 / ( L ⋅ C ) , and time period,
T = 1 / f 0 = (2 ⋅ π ) / ω 0 = (2 ⋅ π ) ⋅ ( L ⋅ C ) .
The initial conditions at t = 0 are, i0 = I and d i0 / dt = 0 . It should be noted that the time, t is
measured from the instant, the diodes, D1 & D3, start coducting, i.e., from the instant, mode I is
over. Using the initial conditions stated earlier, the current is, i0 = I ⋅ (2 ⋅ cos (ω 0 ⋅ t ) − 1) . The
capacitor current is iC = I + i0 = 2 ⋅ I ⋅ cos (ω 0 ⋅ t ) .
1 ⎛ 2⋅ I ⎞
The voltage across capacitor is, vC = ⋅ ∫ iC ⋅ dt =⎜⎜ ⎟⎟ ⋅ sin (ω 0 ⋅ t ) .
C ⎝ ω0 ⋅ C ⎠
This expression can also be obtained as,
vC = v L = L ⋅ (d i0 / dt ) = ((2 ⋅ I ) ⋅ (ω 0 ⋅ L) ) ⋅ sin (ω 0 ⋅ t ) , where, ω 0 ⋅ L = 1 /(ω 0 ⋅ C ) , as can be
derived using ω 0 = 1 / ( L ⋅ C ) . So, the above expressions are same, and can be written as,
( )
vC = (2 ⋅ I ) ⋅ ( L / C ) ⋅ sin (ω 0 ⋅ t ) , substituting the expression for ω 0 in any of the above
expressions. So, iC1 = iC 2 = I ⋅ cos (ω 0 ⋅ t ) , and
i D1 = I − iC1 = I ⋅ (cos (ω 0 ⋅ t ) − 1) , in the interval 0 < t < t 2 .
As the current, iC1 tends to reverse, diode, D3 prevents its reversal. Similarly, the diode, D4
prevents the reversal of the current, iC 2 . From the initiation of mode II, a time, t2 must elapse for
the current, iC1 to become zero (0). The time, t 2 is,
t 2 = (π / 2) / ω 0 = (π / 2) ⋅ ( L ⋅ C ) = (1 /(4 ⋅ f 0 ) ) = T / 4 , as (ω 0 ⋅ t 2 ) = (π / 2) , using,
iC1 = I ⋅ cos (ω 0 ⋅ t 2 ) = 0 . The capacitor voltage at time, t 2 is, vC = ((2 ⋅ I ) /(ω 0 ⋅ C ) ) = VC 0 . Note
that this is also the maximum value. Now, the load current is, i0 = I ⋅ (2 − 1) = I . This shows that
the load current has reversed from +I to –I during mode II, after time, t2. It is also seen that the
capacitor voltage changes by 2 ⋅ VC 0 (from − VC 0 to VC 0 ) during each commutation interval. The
time t1 , after substituting VC 0 , comes out as,
t1 = (C /(2 ⋅ I ) ⋅ VC 0 = (C /(2 ⋅ I ) ⋅ ((2 ⋅ I ) /(ω 0 ⋅ C ) ) = 1 / ω 0 = ( L ⋅ C ) .
The total commutation interval is, t c = t1 + t 2 = (1 + (π / 2) ) / ω 0 = (1 + (π / 2) ) ⋅ ( L ⋅ C ) .

At the end of the process, constant current flows in the path, Th1, D1, load (L), D3, Th3, and
source, I. This continues till the next commutation process is initiated by the triggering of the
thyristor pair, Th2 & Th4.
The complete commutation process is summarized here. The process (mode I) starts with the
triggering of the thyristor pair, Th1 & Th3. Earlier, the thyristor pair, Th2 & Th4 were conducting.
With the two commutating capacitors charged earlier with the polarity as shown (Fig. 39.3), the
conducting thyristor pair, Th2 & Th4 turns off by the application of reverse voltage. Then, the
voltages across the capacitors decrease to zero at time, t1 (end of mode I), as constant (source)
current, I flows in the opposite direction. Mode II now starts (Fig. 39.4a), as the diodes, D1 & D3,
get forward biased, and start conducting. So, all four diodes D1-D4, conduct, and the load
inductance, L is now connected in parallel with the two commutating capacitors. The current in
the load reverses to the value –I, after time, t 2 (end of mode II), and the two capacitors also are
charged to the same voltage in the reverse direction, the magnitude remaining same, as it was
before the start of the process of commutation (t = 0). It may be noted that the constant current, I
flows in the direction as shown, a part of which flows in the two capacitors.
In the above discussion, one form of load, i.e. inductance L only, has been considered. The
procedure remains nearly same, if the load consists of resistance, R only. The procedure in mode
I, is same, but in mode II, the load resistance, R is connected in parallel with the two
commutating capacitors. The direction of the current, I remains same, a part of which flows in
the two capacitors, charging them in the reverse direction, as shown earlier. The derivation,
being simple, is not included here. It is available in books on this subject.
Three-phase Current Source Inverter
X
+
Th1 Th3 Th5

C1 C3
D1 C5 D3 D5 L
iA
A L R R
iB
Vdc B N
iC R
C
D4 D6 D2 L
C4 C6
Th4 C2 Th6 Th2
-
Y
Fig. 39.5(a): Three-phase current source inverter (CSI)
The circuit of a Three-phase Current Source Inverter (CSI) is shown in Fig. 39.5a. The type
of operation in this case is also same here, i.e. Auto-Sequential Commutated Inverter (ASCI). As
in the circuit of a single-phase CSI, the input is also a constant current source. The output current
(phase) waveforms are shown in Fig. 39.5b. In this circuit, six thyristors, two in each of three
arms, are used, as in a three-phase VSI. Also, six diodes, each one in series with the respective
thyristor, are needed here, as used for single-phase CSI. Six capacitors, three each in two (top
and bottom) halves, are used for commutation. It may be noted that six capacitors are equal, i.e.
C1 = C 2 = " = C6 = C . The diodes are needed in CSI, so as to prevent the capacitors from
discharging into the load. The numbering scheme for the thyristors and diodes are same, as used
in a three-phase VSI, with the thyristors being triggered in sequence as per number assigned
(Fig. 39.5b).

I
180° 300°
iA 0
120° 360°
θ
-I
I
120°
300° 360°
IB 0
240°
60°
-I
60° 180°
IC 0
240° 360°
-I
on Th1 Th2 Th3 Th4 Th5 Th6 Th1

off
Th5 Th6 Th1 Th2 Th3 Th4 Th5
0
60° 120° 180° 240° 300° 360°
Thyristors conducting
Fig. 39.5(b): Phase current waveforms

The commutation process in a three-phase CSI is described in brief. The circuit, when two
thyristors, Th1 & Th2, and the respective diodes, are conducting, is shown in Fig. 39.6a. The
current is flowing in two phases, A & C. The three capacitors in the top half, are charged
previously, or have to pre-charged as shown. But the capacitors in the bottom half are not shown.
I X
+
L′
Th1 C1 Th3 C3 Th5
+ - - +
I
D1 + -
D3 D5
C5
I (iA)
A A
B
C
I (iC)
D2
I Th2
-
Y I
Fig. 39.6(a): Three-phase CSI with two thyristors, Th1 & Th2 conducting
Mode I: The commutation process starts, when the thyristor, Th3 in the top half, is triggered, i.e.
pulse is fed at its gate. Immediately after this, the conducting thyristor, Th1 turns off by the
application of reverse voltage of the equivalent capacitor. Mode I (Fig. 39.6b) now starts. As the
diode D1 is still conducting, the current path is via Th3, the equivalent capacitor, D1, and the load
in phase A (only in the top half). The other part, i.e. the bottom half and the source, is not
considered here, as the path there remains same. The current, I from the source now flows in the
reverse direction, thus the voltage in the capacitor, C1 (and also the other two) decreases. It may
be noted the equivalent capacitor is the parallel combination of the capacitor, C1 and the other
part, being the series combination of the capacitors, C3 & C5 ( C ′ = C / 2 ). It may be shown the its
value is C eq = C / 3 , parallel combination of C & C / 2 , as C1 = C3 = C5 = C . Also, the current
in the capacitor, C1 is ( 2 / 3) ⋅ I , and the current in other two capacitors, C3 & C5 is I / 3 . When
the voltage across the capacitor, C1 (and also the other two) decreases to zero, the mode I ends.

I X
L′
I
Th1 Th3 Th5
2I/3 C1 C3 I/3
+ - - +
I
+ -
D1 C5 D3 I/3 D5
I (iA)
A
B
C
I (iC)
D2
I
Th2
Y I
Fig. 39.6(b): Mode I (3-phase CSI)
Mode II: After the end of mode I, the voltage across the diode, D3 goes positive, as the voltage
across the equivalent capacitor goes negative, assuming that initially (start of mode I) the voltage
was positive. It may be noted that the current through the equivalent capacitor continues to flow
in the same direction. Mode II (Fig. 39.6c) starts. Earlier, the diode, D1 was conducting. The
diode, D3 now starts conducting, with the voltage across it being positive as given earlier. A
circulating current path now exists between the equivalent capacitor, two conducting diodes, D1
& D3 and the load (assumed to be inductive − R & L, per phase) of the two phases, A & B, the
two loads and also the two diodes being now connected in series across the equivalent capacitor.
The current in this path is oscillatory, and goes to zero after some time, when the mode II ends.
The diode, D1 turns off, as the current goes to zero. So, at the end of mode II, the thyristor, Th3 &
the diode, D3 conduct. This process has been described in detail in the earlier section on single-
phase CSI (see mode II). It may be noted that the polarity of the voltage across the equivalent
capacitor (at the end of mode II) has reversed from the initial voltage (at the beginning of mode
I). This is needed to turn off the outgoing (conducting) thyristor, Th3, when the incoming
thyristor, Th5 is triggered. The complete commutation process as described will be repeated. The
diodes in the circuit prevent the voltage across the capacitors discharging through the load.

I X
+
L′
Th1 I Th3 Th5
- + + -
C1 C3
- +
D1 C5 D3 D5
iA
A
iB
B
C
I (iC)
D2
I
Th2
-
Y I
Fig. 39.6(c): Mode II (3-phase CSI)
The circuit is shown in Fig. 39.6d, with two thyristors, Th3 & Th2, and the respective diodes
conducting. The current now flows in two phases, B & C, at the end of the commutation process,
instead of phase A at the beginning (Fig. 39.6a). It may be noted the current in the bottom half
(phase C) continues to flow, and also the thyristor, Th2 & the diode, D2 remain in conduction
mode. This, in brief, is the commutation process, when the thyristor, Th3 is triggered and the
current is transferred to the thyristor, Th3 & the diode, D3 (phase B), from the thyristor, Th1 & the
diode, D1 (phase A).

I
+
L′ I
Th1 Th3 Th5
C1
- + + -
C3
- +
C5
D1 D3 D5
I
A
I (iB)
B B
C C
I (iC)
D2
I
Th2
-
Y I
Fig. 39.6(d): Three-phase CSI with two thyristors, Th3 & Th2 conducting
Comments
In the introductory remarks, one merit of CSI has been stated, i.e. it can be used for the speed
control of ac, specially induction, motors subject to variation in load torque. In recent years,
self-commutated power switching devices, such as power transistors etc., are being used in VSI,
but not costly inverter-grade thyristors (having low turn-off time), along with bulky commutation
circuits. These circuits also need additional diodes for feeding the reactive power back to the
supply, when used with heavily inductive loads. The advantages and disadvantages of CSI vis-à-
vis VSI are given.
Advantages
1. The circuit for CSI, using only converter grade thyristor, which should have reverse blocking
capability, and also able to withstand high voltage spikes during commutation, is simple.
2. An output short circuit or simultaneous conduction in an inverter arm is controlled by the
‘controlled current source’ used here, i.e., a current limited voltage source in series with a
large inductance.
3. The converter-inverter combined configuration has inherent four-quadrant operation
capability without any extra power component.

Disadvantages
1. A minimum load at the output is required, and the commutation capability is dependant upon
load current. This limits the operating frequency, and also puts a limitation on its use for UPS
systems.
2. At light loads, and high frequency, these inverters have sluggish performance and stability
problems.
In this lesson − the seventh one of this module, the current source inverter (CSI) vis-à-vis
VSI, is introduced. The commutation process for Auto-Sequential Commutated Inverter (ASCI)
mode of operation in single-phase CSI, is mainly described, along with circuit diagram and
relevant waveforms, in detail. Then, the commutation process for the same mode of operation,
i.e. ASCI, in three-phase CSI, is described, along with various circuit diagrams, in brief. Finally,
the advantages and disadvantages of CSI over VSI, are presented. In the next lesson, eighth and
last one, of this module, the load-commutated CSI, and also the Pulse Width Modulation (PWM)
techniques used in CSI, will be discussed.

Module
5
DC to AC Converters
Lesson
40
Load-commutated
Current Source Inverter
(CSI)
Study of the circuit and operation for Load-commutated Current Source Inverter (CSI)
Introduction
In the last lesson (5.7) – seventh one in this module, the circuit and operation of single-phase
and three-phase Current Source Inverters (CSI), with relevant waveforms, have been described in
detail. The device used is thyristor. The type is the Auto-Sequential Commutated Inverter
(ASCI). In this lesson (5.8) – eighth and final one in this module, the circuit and operation of
load-commuted CSI, including waveforms, will be presented in detail.
Keywords: Load-commutated current source inverter (CSI)
Load-Commutated CSI
In the last lesson, ASCI mode of operation for a single-phase Current Source Inverter (CSI)
was presented. Two commutating capacitors, along with four diodes, are used in the above
circuit for commutation from one pair of thyristors to the second pair. Earlier, also in VSI, if the
load is capacitive, it was shown that forced commutation may not be needed. The operation of a
single-phase CSI with capacitive load (Fig. 40.1) is discussed here. It may be noted that the
capacitor, C is assumed to be in parallel with resistive load (R). The capacitor, C is used for
storing the charge, or voltage, to be used to force-commutate the conducting thyristor pair as will
be shown. As was the case in the last lesson, a constant current source, or a voltage source with
large inductance, is used as the input to the circuit.
+ a
i
Th1 Th2
iC
C i
+ -
c v0
I Vin d
= vC
Load (R)
Th3
Th4
- b
Fig. 40.1: Load-commuted CSI

The power switching devices used here is the same, i.e. four thyristors only in a full- bridge
configuration. The positive direction for load current and voltage, is shown in Fig. 40.1. Before t
= 0, the capacitor voltage is vC = −V1 , i.e. the capacitor has left plate negative and right plate
positive. At that time, the thyristor pair, Th2 & Th4 was conducting. When (at t = 0), the thyristor

pair, Th1 & Th3 is triggered by the pulses fed at the gates, the conducting thyristor pair, Th2 &
Th4 is reverse biased by the capacitor voltage vC = −V1 , and turns off immediately. The current
path is through Th1, load (parallel combination of R & C), Th3, and the source. The current in the
thyristors is iTh1 = iTh3 = I , the output current is iac = I ; the capacitor voltage, vC changes from
− V1 to V1 , as the capacitor gets charged by the current iC during the time, (T / 2) > t > 0 . The
load voltage is v0 = vC . Thus, the waveform of the current, i0 = (v0 / R) = (vC / R) through load
resistance, R has the same nature as that of vC (Fig. 40.2). Similarly, when (at t = T / 2 ), the
thyristor pair, Th2 & Th4 is triggered by the pulses fed at the gates, the conducting thyristor pair,
Th1 & Th3 is reverse biased by the capacitor voltage vC = V1 , and turns off immediately. The
current path is through Th2, load (parallel combination of R & C), Th4, and the source. The
current in the thyristors is iTh 2 = iTh 4 = I , but the output current is iac = − I ; the capacitor
voltage, vC changes from V1 to − V1 , as the capacitor gets charged by the current iC during the
time, T > t > (T / 2) .

ig1,
ig3
0 T/2 T
ig2, iTh1, I
iTh3
ig4
0 t T/2 T 0 T/2 T
I1, I
v0, V1 iTh2,
iTh4
i0 0
T/2 T 0 T/2 T
-I1,
-V1,
I+I1 I
I-I1 iac
0 T/2 T
iC 0 T/2 T
-I
-(I-I1)
Th1, Th3 Th2, Th4
-(I+I1)
Th1, Th3 Th2, Th4 Th1, Th3
triggered triggered triggered
V1
vin
0
T/2 T
-V1
V1
vTh1,
vTh3
0 T/2 T
-V1
Fig. 40.2: Voltage and current waveforms.

Various current and voltage waveforms during one cycle T > t > 0 , are shown in Fig. 40.2.
At t = 0, the capacitor voltage is vC = −V1 , then v0 = vC = −V1 , and the load current through R is
i0 = −(V1 / R) = − I1 . As stated earlier, during the time (T / 2) > t > 0 , the capacitor gets charged,
with its voltage changing from − V1 to V1 . So, At t = T / 2 , the load current is
i0 = (vC / R) = (v0 / R) = (V1 / R) = I1 . The input voltage is vin = v0 , during (T / 2) > t > 0 , and
vin = −v0 , during T > t > (T / 2) .
It may be observed that, when the thyristor pair, Th1 & Th3 is conducting for (T / 2) > t > 0 ,
the currents iC , i0 are leaving node A (Fig. 40.1), and the current, I is entering node A.
Therefore, the equivalent circuit for (T / 2) > t > 0 , is shown in Fig. 40.3a. The current in node
A, is iC + i0 = I or, iC = I − i0 . At t = 0, i0 = − I 1 , and iC = I + I 1 . The mathematical steps for a
steady solution of the output current, and other parameters, such as input voltage etc., are given
later. Just after (T/2), when the thyristor pair, Th2 & Th4 is conducting, the currents iC , i0 are
entering node B (Fig. 40.1), and so also the current, I. The equivalent circuit for T > t > (T / 2) ,
is shown in Fig. 40.3b. The current in node B is iC + i0 + I = 0 or, iC = −( I + i0 ) . At t = (T/2),
i0 = I 1 , and iC = −( I + I1 ) . The cycle repeats itself.
I c (a) - I c (a) +
i0 iC i0 iC
I I
R v0 = vC V1 R v0 = vC V1
C C
-
d (b) + d (b)
(a) (b)
Fig. 40.3: (a) Equivalent circuit for 0 < t < T/2

(b) Equivalent circuit for T/2 < t < T
The steps to be followed to find the expression of the output current, and other parameters
are described. The voltage balance equation for the equivalent circuit (Fig. 40.3a) is,
R ⋅ i0 − (1 / C ) ⋅ ∫ ( I − i0 ) dt + v1 = 0
d i0 i0 I
Differentiating it, we get R ⋅ + =
dt C C
Solving it, with the initial condition for i0 as given earlier,
( )
i0 = I ⋅ 1 − e − t /( R⋅C ) − I 1 ⋅ e −t /( R⋅C )
To arrive at a steady solution only, the following steps are followed. At t = (T/2), the current is
( )
i0 = I 1 , as shown later. So, I1 = I ⋅ 1 − e −T /( 2⋅R⋅C ) − I1 ⋅ e −T /( 2⋅R⋅C )
⎡1 − e −T /( 2⋅R⋅C ) ⎤
or, I1 = I ⋅ ⎢ −T /( 2⋅R⋅C ) ⎥
= I , if (T /( 2 ⋅ R ⋅ C ) ) >> 1 or, T >> ( R ⋅ C )
⎣1 + e ⎦

So, using the above expression, the output current, or the current in resistance, R comes out as,
⎡ 2 ⋅ (e − t /( R⋅C ) ) ⎤
i0 = I ⋅ ⎢1 − −T /( 2⋅ R ⋅C ) ⎥
⎣ 1+ e ⎦
The output voltage v0 , or the capacitor voltage vC is,
⎡
v 0 = vC = i0 ⋅ R = ( R ⋅ I ) ⋅ ⎢1 −
(
2 ⋅ e − t /( R⋅C ) ⎤ )
−T /( 2⋅ R⋅C ) ⎥
⎣ 1+ e ⎦
The turn-off time provided by the circuit for each thyristor is obtained from the condition that,
when t = tOFF , v0 = vC = i0 ⋅ R = 0 . So,
v0 = vC = i0 ⋅ R = ( R ⋅ I ) ⋅ ⎢1 −
(
⎡ 2 ⋅ e − tOFF /( R⋅C ) ) ⎤⎥ = 0
⎢⎣ 1 + e −T /(2⋅R⋅C ) ⎥⎦
or, e − tOFF /( R⋅C ) = (1 + e −T /(2⋅R⋅C ) ) / 2
⎛ ⎞
= −( R ⋅ C ) ⋅ log e ⎡⎣(1 + e−T /(2⋅R⋅C ) ) / 2 ⎤⎦
2
or, tOFF = ( R ⋅ C ) ⋅ log e ⎜ −T /(2⋅ R⋅C ) ⎟
⎝ 1+ e ⎠
The average value of the input voltage, Vin is,
⎛ 1 ⎞
T /2
⎛ 2⋅I ⋅R⎞ ⎡ T /2
( )
2 ⋅ e − t /( R⋅C ) ⎤
Vin = ⎜ ⎟⋅
⎝T /2⎠
∫0 (i0 ⋅ R) dt = ⎜⎝ T ⎟⎠ ⋅ ∫0 ⎢⎣ 1 + e −T /( 2⋅R⋅C ) ⎥⎦ dt
1 −
⎡ ⎛ 4 ⋅ R ⋅ C ⎞ ⎛ 1 − e −T /( 2⋅R⋅C ) ⎞⎤
or, Vin = ( I ⋅ R ) ⋅ ⎢1 − ⎜ ⎟ ⋅ ⎜⎜ ⎟
−T /( 2⋅ R⋅C ) ⎟ ⎥
⎣ ⎝ T ⎠ ⎝ 1 + e ⎠⎦
When the input power ( Vin ⋅ I ) is positive, power is delivered to the load.
The following points may be noted.
1. It may be observed from the equation given earlier that, as the inverter frequency ( f = 1 / T )
is increased, the turn-off time provided by the circuit decreases. But, the circuit commutation
time, t off , should be more than the turn-off time of the thyristor, t q , for reliable operation.
This means that there is an upper limit to the inverter frequency, beyond which the thyristors
in the inverter circuit will fail to commutate.
2. When the inverter frequency ( f = 1 / T ) is low, or time period, T is high, the graph of i0 (t )
or v0 (t ) as given in Fig. 40.2, becomes flatter as shown by dotted line in Fig. 40.4. As this
graph is nearer to a square wave, it can be inferred that, for low inverter frequencies, the
inverter has square wave output for load current or load voltage ( i0 / v0 ).
When the inverter frequency ( f = 1 / T ) is high, or time period, T is low, the waveform
of v0 or i0 is shown by full line in Fig. 40.4. As this graph is closer to a sine wave, it can be
noted that, for higher frequency, the CSI has sinusoidal wave shape for load (output) current
or voltage.

v0, i0
Small T
Large T
T
T/2 t
Fig. 40.4: Waveforms for CSI with resistive (R) load
(a) Square wave output: It has been found that, for obtaining square wave of the load current,
T /( 2 R C ) > 5.0 . If t q is the turn-off time for the thyristors used in CSI, then form the
equation given earlier,
( )
t q = ( R C ) log e 2 /(1 + e −5 ) ≈ ( R C ) log e 2 = 0.69 ( R C )
or, C = t q /(0.69 R)
For T /( 2 R C ) = 5.0 or T = 10 R C , the maximum frequency is,
f max = 1 / T = 1 /(10 R C )
Substituting the value of C obtained earlier, f max = 0.069 / t q
(b) Sinusoidal wave output: For obtaining sinusoidal wave of the load current, the capacitive
reactance, X C at three times the minimum frequency, f min , should be lower than R / 2 , i.e.,
1 R
at 3 f min , X C = ≤ ,
2 π 3 f min C 2
or C ≥ 0.106 /( R f min)
The inverter should therefore be operated at frequencies higher than f min in order to obtain
the sinusoidal wave shape.
In this lesson (5.8) – eighth and final one in this (last) module (5), the circuit and operation,
of load-commuted CSI, including waveforms, are discussed in detail. In this module (5), mainly
two types of dc-ac converters, termed as inverters – Voltage Source (VSI) and Current Source
(CSI), have been presented. Both single-phase and three-phase inverters have been described,
with relevant waveforms. Starting with the use of Pulse Width Modulation (PWM) techniques,
used for voltage control in VSI, other variations, such as Sine PWM, have been taken up.
Incidentally, this is the last lesson for the course on ‘Power Electronics’.

Power Electronic-EE IIT Kharagpur

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Module

(i) Create an awareness of the general nature of Power electronic equipment;

A passenger lift in a modern building equipped with a Variable-Voltage-Variable-Speed

Fig. 1.1 The block diagram of a typical Power Electronic converter

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How is Power electronics distinct from linear electronics?

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Linear operation Switching operation

Utilisation of transistor rating of secondary Utilisation of transistor rating optimised

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Spec: Input : 230 V, 50 Hz, Output: 12 V regulated DC, 20 W

Ferrite core HF transfr:

Line freq transformer: (a) (b)

Power Semiconductor device - history

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Subsequent developments in converter topologies – especially the three-level inverter

1200V Version 3 ASIPM

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RECTIFIERS ACCESSORIES REGENERATIVE NON-REGENERATIVE INTEGRATED

POWER SILICON SCR BJT IGCT

Fig. 1.5 Power semiconductor device variety

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Silicon Controlled Rectifier (SCR)

Asymmetrical, light-activated, reverse conducting SCR's Quite a few varieties of the

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Power Converter Topologies

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DC to DC Chopper Constant to variable DC or

DC to AC Inverter DC to AC of desired voltage and

AC to DC Rectifier AC to unipolar (DC) current

Base / gate drive circuit

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Protection of Power devices and converters

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Objective type questions

a) Highest switching speed;

If the primary pulse voltage = (Supply voltage – drive transistor drop)

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2.2 Review of Basic p-n Diode Characteristics

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IF = IS ( exp ( qv/kT ) ) -1 (2.1)

Fig 2.2: Volt-Ampere ( i-v ) characteristics of a p-n junction diode

(1) Fill in the blanks with the appropriate word(s).

2.3 Construction and Characteristics of Power Diodes

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2.3.1 Power Diode under Reverse Bias Conditions Back

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2.3.2 Power Diode under Forward Bias Condition

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(1) Fill in the blanks with the appropriate word(s).

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VRRM = 2 × 2 × 230V = 650V

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2.3.3 Switching Characteristics of Power Diodes

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Salient features of this characteristics are:

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