1d04d Compal LA-8392P (Satellite P850 P855)

A
QFKAA
Yosemite 10F
LA-8392P REV 1.0 Schematic

Intel Processor(Ivy Bridge / Sandy Bridge)
PCH(Panther Point)
2012-02-06 Rev 1.0
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/12/14
Deciphered Date
2012/12/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
SCHEMATICS, MB A8392
Document Number
Rev
4019HF
Thursday, February 16, 2012
Sheet
1
E
of
51
Intel CPU
Ivy Bridge
Sandy Bridge
eDP Conn.
Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
rPGA-989
page 13
37.5mm*37.5mm
Dual Channel
page 5,6,7,8,9,10
CRT
page 14
FDI X8
page 11,12
BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333/1600 MT/s
DMI X4
2.7GT/s
5GT/s
USB30 4x
USB Right
5V 5GT/s
USB20 port 2,3

USB30 port 3,4
page 25
USB20 4x
LVDS Conn.
USB Left
USB20 port 0,1

USB30 port 1,2
page 30
5V 480MHz
page 13
2
FingerPrinter
USB20 3x
5V 480MHz
EC SMBus
HDMI-CEC
page 15
page 40
USB port 11
page 13
HDMI Conn.
Intel PCH
Panther Point
page 15
RJ45
Int. Camera
USB port 8
page 29
RTL8105E-VD 10/100M
RTL8111F-VB 1G
5V 480MHz
PCIe Gen1 1x
PCIeMini Card
WiMax USB port 9
page 27
1.5V 5GT/s
PCIe Gen1 1x
SATA Gen3 port 1
1.5V 5GT/s
5V 6GHz(600MB/s)
page 31
PCIe port 1
USB20 3x
FCBGA-989
PCIeMini Card
WLAN PCIe port 2
PCIeMini Card
3G/TV#1
TV#2
USB port 12
USB port 10
page 27
mSATA
page 27
SATA port 1
page 27
B-CAS
page 26
25mm*25mm
Cardreader
RTS5229
PCIe port4
PCIe Gen1 1x
SATA Gen3 port 0
5V 6GHz(600MB/s)
SATA port 2
SATA ODD
SIM
page 27
1.5V 5GT/s
page 16,17,18,19,20,21,22,23,24
page 29
5V 3GHz(300MB/s)
SATA port 2
page 23
SATA HDD
SATA port 0
page 23
PCIe Gen2 2x
1.5V 5GT/s
LPC BUS
HD Audio
3.3V 33 MHz
3.3V 24MHz
USB3.0 Right-side
UPD720202
HDA Codec
SPI ROM
(4MB
+ 2MB)
page 16
Debug Port
page 36
PCIe port5
page 31
ALC280
ENE KB930/KB9012
USB3.0 Left-side
UPD720202
PCIe port6
page 32
page 33
page 35
RTC CKT.
page 16
SPK Conn
JPIO
(HP &page
MIC)
34
page 34
DC/DC Interface CKT.
Touch Pad
page 38
page 37
Int.KBD
page 36
EC ROM
(128KB)
page 36
CIR
page 35
G-Sensor
page 36
EC SMBus
Power Circuit DC/DC

page 39,40,41,42,43,
44,45,46,47,48,49
Finger Printer/B
page 26
Power On/Off CKT.

page 37
2011/12/14
Issued Date
Power/B
Compal Secret Data
Deciphered Date
2012/12/31
Title
Size
page 37
Date:
Document Number
Rev
B
4019HF
Sheet
E
of
51
DESIGN CURRENT 0.1A
+3VL
+5VL
DESIGN CURRENT 0.1A
B+
Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A
DESIGN CURRENT 11A
+5VALW
DESIGN CURRENT 1.8A
+1.8VS
DESIGN CURRENT 6.5A
+5VS
SUSP#
SY8033BDBC
SUSP
D
N-CHANNEL
BCPWON
SI4800
DESIGN CURRENT 0.1A
+5VS_L_BCAS
DESIGN CURRENT 0.4A
+5VS_LED
DESIGN CURRENT 0.3A
+3VS_HDP
DESIGN CURRENT 1.6A
+5VS_ODD
P-CHANNEL
AO-3413
KB_LED
TPS51125
P-CHANNEL
AO-3413
+5VS
LDO
G9191
ODD_EN#
P-CHANNEL
AO-3413
SYSON
Ipeak=6A, Imax=4.2A, Iocp min=8A DESIGN CURRENT 13.5A
SY8036
+1.5V
SUSP
N-CHANNEL
DESIGN CURRENT 5A
+1.5V_CPU
FDS6676AS
SUSP
C
N-CHANNEL
DESIGN CURRENT 1.5A
+1.5VS
FDS6676AS
0.75VR_EN#
DESIGN CURRENT 1A
+0.75VS
DESIGN CURRENT 6A
+VCCSA
DESIGN CURRENT 0.3A
+16VS
DESIGN CURRENT 7.5A
+3VALW
DESIGN CURRENT 0.1A
+3V_LAN
G2992
VCCPPWRGD
Ipeak=6A, Imax=4.A, Iocp min=8
SY8037
LNB EN
Imax=0.3A, Iocp min=0.8A
APW7137
Ipeak=5A, Imax=3.5A, Iocp min=6.2A
WOL_EN
P-CHANNEL
AO-3413
SUSP
N-CHANNEL
B
DESIGN CURRENT 6A
+3VS
DESIGN CURRENT 2A
+LCD_VDD
UMA_ENVDD
SI4800
P-CHANNEL
AO-3415
FELICA_PWR
DESIGN CURRENT 0.1A
P-CHANNEL
AO-3413
VR_ON
NCP6132A
+FLICA_VCC
DESIGN CURRENT 94A
+CPU_CORE
DESIGN CURRENT 50A
+GFX_CORE
DESIGN CURRENT 15A
+1.05VS_VCCP
SUSP#
Ipeak=14A, Imax=9.8A, Iocp min=16.92A
TPS51212
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Size
Date:
Document Number
Rev
B
4019HF
Sheet

1
of
51
Voltage Rails
( O MEANS ON
+RTCVCC
X MEANS OFF )
B+
+5VL
+5VALW
+3VL
+3VALW
+1.5V
+5VS
+3VS
+1.8VS
+VSB
power
plane
+1.5VS
1
+1.05VS
BTO Option Table
+0.75VS
+CPU_CORE
+VGA_CORE
Function
+GFX_CORE
description
+VTT
State
+VRAM_1.5VS
HDMI
Internal Display Port
HDMI
Internal Display Port
explain
HDMI
CEC
LVDS
EDP
BTO
HDMI@
CEC@
LVDS@
IEDP@
+3VS_DGPU
+1.05VS_DGPU
S1
S3
S5 S4/AC
S5 S4/ Battery only

S5 S4/AC & Battery
don't exist
Device
HEX
Address
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
+3VS
New Card
+3VS
WLAN/WIMAX
+3VS
Clock Generator
+3VS
3G
3G
TV Tuner
BCAS
mSATA
WIMAX
BTO
3G@
TV@
BCAS@
mSATA@
WIMAX@
LAN
Function
SPI ROM
description SPI ROM
Green CLK
G-SENSOR
Green CLK
G-SENSOR
explain
WIN8
Green CLK
Fingerprint
CIR
Fingerprint
CIR
FP@
CIR@
BTO
WIN8@
271@
Sleep&Charge
Camera & Mic
USB 3.0
Camera & Mic
G-SENSOR
14600
14617
Internal
NOGCLK@
GSENSOR@
14600@
14617@
IUSB30@
Camera & Mic
External
CAM@
EUSB30@
USB Repeater
USB Repeater
explain
TIUR
PRUR
BTO
TIUR@
PRUR@
EC SM Bus2 Address
SIGNAL
Full ON
SLP_S3# SLP_S4# SLP_S5#

HIGH
HIGH
HIGH
HEX
Address
Power
Device
HEX
Address
S1(Power On Suspend)
HIGH
HIGH
HIGH
16 H
0001 0110 b
+3VS
PCH
96 H
1001 0110 b
S3 (Suspend to RAM)
LOW
HIGH
HIGH
+3VL
HDMI-CEC
34 H
0011 0100 b
+3VS
NVIDIA GPU
9A H
1001 1010 b
+3VS
G-Sensor
40 H
0100 0000 b
S4 (Suspend to Disk)
LOW
LOW
HIGH
S5 (Soft OFF)
LOW
LOW
LOW
G3
LOW
LOW
LOW
Cap. Sensor
CIR
USB 3.0
NOGCLK
Device
+3VL
KBL@
Fingerprint
8111FVB@
Sleep&Charge
Smart Battery
HEX
Giga
8105ELDO@
Power
Device
KB Light
IVY@
10/100M
+3VL
Power
Ivy Bridge
SANDY@
STATE
EC SM Bus1 Address
Sandy Bridge
SLOT1
explain
description
Power
KB Light
LAN
SLOT2
description
Function
PCH SM Bus Address
KB Light
Ivy Bridge
MINI PCI-E SLOT
Function
S0
CPU
Sandy Bridge
Address
Virtual I2C
2011/12/14
Issued Date
Compal Secret Data
Deciphered Date
2012/12/31
Title
Size Document Number
Custom
Rev
B
4019HF
Date:
Sheet
E
of
51
JCPUB
100 MHz
<21> H_SNB_IVB#
C26
PROC_SELECT#
1 CC62
H_PWRGOOD_R
T1
T2
+1.05VS_VCCP
RC44
<35>
H_PECI
AN34
SKTOCC#
H_CATERR#
AL33
CATERR#
H_PECI
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
RC159
2 H_PROCHOT#_R
56_0402_5%
<35,40> H_PROCHOT#
RC45
TP_SKTOCC#
PAD
H_PROCHOT#
1 62_0402_5%
PAD
THERMAL
1000P_0402_50V7K 2
H_PWRGOOD
1 10K_0402_5%
H_THERMTRIP#
<21> H_THERMTRIP#
CLOCKS
H_SNB_IVB#
BCLK
BCLK#
A28
A27
CLK_CPU_DMI
CLK_CPU_DMI#
Stuff R41 and R42 if do not support eDP
CLK_CPU_DMI <17>
CLK_CPU_DMI# <17>
+1.05VS_VCCP
120 MHz
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
DDR3
MISC
PM_DRAM_PWRGD_R
1 CC63
MISC
@
1000P_0402_50V7K 2
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
A16
A15
CLK_CPU_EDP
CLK_CPU_EDP#
R8
H_DRAMRST#
AK1
A5
A4
SM_RCOMP_0 RC56
SM_RCOMP_1 RC59
SM_RCOMP_2 RC61
CLK_CPU_EDP <17>
CLK_CPU_EDP# <17>
CLK_CPU_EDP#
RC1571 LVDS@ 2 1K_0402_5%
CLK_CPU_EDP
RC1581 LVDS@ 2 1K_0402_5%
H_DRAMRST# <7>
1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%
2
2
2
DDR3 Compensation Signals

Layout Note:Place these
resistors near Processor
H_DRAMRST#
@
H_PECI
@
1000P_0402_50V7K 2
H_PM_SYNC
<18> H_PM_SYNC
H_PM_SYNC
1 CC71
@
1000P_0402_50V7K 2
AM34
PM_SYNC
RC187
BUF_CPU_RST#
1 CC66
<21> H_PWRGOOD
PM_SYS_PWRGD_BUF 1
RC58
Please place near JCPU
2 H_PWRGOOD_R
0_0402_5%
2 PM_DRAM_PWRGD_R
130_0402_5%
AP33
V8
UNCOREPWRGOOD
SM_DRAMPWROK
BUF_CPU_RST#
AR33
RESET#
+3VALW_PCH
+3VALW_PCH
2
10K_0402_5%
2 RC13
1
+3VS
AR26
AR27
AP30
T4
T5
XDP_TRST#_R
TDI
TDO
AR28
AP26
T6
T7
DBR#
AL35
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
by ESD requestion and place near CPU

2
RC55
1
51_0402_5%
Layout request for test point
0.1U_0402_10V7K
CC33
UC1
74AHC1G09GW_TSSOP5
TYCO_2013620-2_IVY BRIDGE
@
RC14
200_0402_5%
1
2
0_0402_5% B
2 A
PM_SYS_PWRGD_BUF
<18> DRAMPWROK
TCK
TMS
TRST#
1
RC12 @
<18,35> PM_PWROK
AP29
AP27
+1.5V_CPU
DRAMPWROK
1
200_0402_5%
PRDY#
PREQ#
@
1
2
CC34
180P_0402_50V8J
2
RC11
JTAG & BPM
1 CC70
PWR MANAGEMENT
1000P_0402_50V7K 2
RC25
39_0402_5%
@
2 0_0402_5%
SUSP
<9,27,38,43> SUSP
1 2
RC181
1
2
G
QC2
2N7002_SOT23
@
FAN Control Circuit
+5VS
0.5A
Buffered Reset to CPU
1
2
2 +FAN1
0_0603_5%
<35>
<35> FAN_SPEED1
1 0.1U_0402_10V7K
CC36
+1.05VS_VCCP
PLT_RST# <20,27,28,29,31,35,36>
@
JFAN
R2
10K_0402_5%
C1
10U_0805_10V6K
@ 1
+3VS
+3VS
R1
6
5
4
3
2
1
FANPWM
FANPWM
+FAN1
C2
0.01U_0402_25V7K
@
G2
G1
4
3
2
1
ACES_50278-00401-001
IN
OUT
GND
BUFO_CPU_RST#
FANPWM
BUF_CPU_RST#
C5
330P_0402_50V7K
@
RC35
43_0402_1%
1
2
1
D1
BAS16_SOT23-3
RC40
0_0402_5%
@
74AHC1G125GW_SOT353-5
1
C3
Add C5 for ESD request 02/01
C4
2
2
10U_0603_6.3V6M 1000P_0402_50V7K
RC38
75_0402_5%
OE#
VCC
UC2
PLT_RST#
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HF
Date:
Sheet

1
of
51
+1.05VS_VCCP
JCPUA
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
<18>
<18>
<18>
<18>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<18>
<18>
<18>
<18>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
B28
B26
A24
B23
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
G21
E22
F21
D21
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
G22
D22
F20
C21
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
A21
H19
E19
F18
B21
C20
D18
E17
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
<18> FDI_FSYNC0
<18> FDI_FSYNC1
FDI_FSYNC0
FDI_FSYNC1
J18
J17
FDI0_FSYNC
FDI1_FSYNC
<18> FDI_INT
FDI_INT
H20
FDI_INT
<18> FDI_LSYNC0
<18> FDI_LSYNC1
FDI_LSYNC0
FDI_LSYNC1
J19
H17
FDI0_LSYNC
FDI1_LSYNC
A18
A17
B16
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
C15
D15
eDP_AUX
eDP_AUX#
<13> H_EDP_TXP0
<13> H_EDP_TXP1
C17
F16
C16
G15
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
<13> H_EDP_TXN0
<13> H_EDP_TXN1
C18
E16
D16
F15
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
RC2
+1.05VS_VCCP
2 24.9_0402_1%
EDP_COMP
H_EDP_HPD#
eDP_COMP signals should be

shorted near balls and
routed with typical
impedance <25m ohm
<13> H_EDP_AUXP
<13> H_EDP_AUXN
+1.05VS_VCCP
PCI EXPRESS* - GRAPHICS
<18>
<18>
<18>
<18>
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
Intel(R) FDI
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
B27
B25
A25
B24
eDP
<18>
<18>
<18>
<18>
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
DMI
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_COMP
RC1
24.9_0402_1%
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 m ohm (12 mils)
Reserve RC3 for HW Review demand
RC3
1K_0402_5%
H_EDP_HPD#
S
IEDP@
RC4
100K_0402_5%
2
G
<13> CPU_EDP_HPD
2N7002_SOT23-3
QC1
IEDP@
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Issued Date
Custom
Rev
B
4019HF
Date:
Sheet
1
of
51
JCPUC
<11> DDR_A_D[0..63]
JCPUD
<11> DDR_A_BS0
<11> DDR_A_BS1
<11> DDR_A_BS2
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AE10
AF10
V6
SA_BS[0]
SA_BS[1]
SA_BS[2]
AE8
AD9
AF9
SA_CAS#
SA_RAS#
SA_WE#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
<11> DDR_A_CAS#
<11> DDR_A_RAS#
<11> DDR_A_WE#
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
AB6
AA6
V9
DDRA_CLK0
DDRA_CLK0#
DDRA_CKE0
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
AA5
AB5
V10
DDRA_CLK1
DDRA_CLK1#
DDRA_CKE1
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
AB4
AA4
W9
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
AB3
AA3
W10
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
AK3
AL3
AG1
AH1
DDRA_SCS0#
DDRA_SCS1#
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
AH3
AG3
AG2
AH2
DDRA_ODT0
DDRA_ODT1
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
DDR_A_DQS#0
C4
G6 DDR_A_DQS#1
DDR_A_DQS#2
J3
M6 DDR_A_DQS#3
AL6 DDR_A_DQS#4
AM8 DDR_A_DQS#5
AR12 DDR_A_DQS#6
AM15 DDR_A_DQS#7
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
D4
F6
K3
N6
AL5
AM9
AR11
AM14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDRA_CLK0 <11>
DDRA_CLK0# <11>
DDRA_CKE0 <11>
DDRA_CLK1 <11>
DDRA_CLK1# <11>
DDRA_CKE1 <11>
DDRA_SCS0# <11>
DDRA_SCS1# <11>
DDRA_ODT0 <11>
DDRA_ODT1 <11>
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
<11>
<11>
<11>
<12> DDR_B_BS0
<12> DDR_B_BS1
<12> DDR_B_BS2
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AA9
AA7
R6
SB_BS[0]
SB_BS[1]
SB_BS[2]
AA10
AB8
AB9
SB_CAS#
SB_RAS#
SB_WE#
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
<12> DDR_B_CAS#
<12> DDR_B_RAS#
<12> DDR_B_WE#
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
DDR SYSTEM MEMORY B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR SYSTEM MEMORY A
<12> DDR_B_D[0..63]
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
AE2
AD2
R9
DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
AE1
AD1
R10
DDRB_CLK1
DDRB_CLK1#
DDRB_CKE1
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
AB2
AA2
T9
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
AA1
AB1
T10
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
AD3
AE3
AD6
AE6
DDRB_SCS0#
DDRB_SCS1#
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
AE4
AD4
AD5
AE5
DDRB_ODT0
DDRB_ODT1
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D7
F3
K6
N3
AN5
AP9
AK12
AP15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C7
G3
J6
M3
AN6
AP8
AK11
AP14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDRB_CLK0 <12>
DDRB_CLK0# <12>
DDRB_CKE0 <12>
DDRB_CLK1 <12>
DDRB_CLK1# <12>
DDRB_CKE1 <12>
DDRB_SCS0# <12>
DDRB_SCS1# <12>
DDRB_ODT0 <12>
DDRB_ODT1 <12>
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
<12>
<12>
<12>
QC3
DDR3_DRAMRST#_R
1
H_DRAMRST#
3
2
<5> H_DRAMRST#
RC77
1K_0402_5%
2
SM_DRAMRST# <11,12>
BSS138_NL_SOT23-3
2
RC78
4.99K_0402_1%
RC76
1K_0402_5%
2
RC75
0_0402_5%
1
2
@
+1.5V
1
RC73
<11,17> DRAMRST_CNTRL_PCH
2 DRAMRST_CNTRL
0_0402_5%
1
Issued Date
Compal Secret Data
CC37
0.047U_0402_25V6K
2011/12/14
2012/12/31
Deciphered Date
Title
2
Custom
Rev
B
4019HF
Date:
Sheet

1
of
51
PEG AND DDR
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
VCCIO40
J23
+1.05VS_VCCP
+1.05VS_VCCP
0.1U_0402_10V7K
1
2
CC50
@
SVID
VIDALERT#
VIDSCLK
VIDSOUT
AJ29
AJ30
AJ28
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
0.1U_0402_10V7K
1
2
CC49
@
RC89
75_0402_5%
RC91
130_0402_5%
2
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
1
RC90 1
RC88 1
RC92
2
2 43_0402_1%
2 0_0402_5%
0_0402_5%
VR_SVID_ALRT# <46>
VR_SVID_CLK <46>
VR_SVID_DAT <46>
Pull high resistor on VR side
+CPU_CORE
to CPU
RC93
Close
100_0402_1%
AJ35 VCCSENSE_R RC94 1

AJ34 VSSSENSE_R RC95 1
2 0_0402_5%
2 0_0402_5%
VCCSENSE <46>
VSSSENSE <46>
1
VCC_SENSE
VSS_SENSE
B10
A10
VCCIO_SENSE
RC97
100_0402_1%
VCCIO_SENSE <44>
RC96
10_0402_1%
RC98
10_0402_1%
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES
8.5A
CORE SUPPLY
+1.05VS_VCCP
97A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
POWER
JCPUF
+CPU_CORE
+1.05VS_VCCP
Compal Secret Data
Issued Date
Close to CPU
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Date:
Rev
B
4019HF
@ TYCO_2013620-2_IVY BRIDGE
4
Sheet

1
of
51
+GFX_CORE
+GFX_CORE
POWER
JCPUG
RC105
10_0402_1%
+1.8VS_VCCPLL
CC58
@
2
330U_B2_2.5VM_R15M
CC59
CC60
1U_0402_6.3V6K
SENSE
LINES
VREF
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_AXG_SENSE <46>
VSS_AXG_SENSE <46>
1 RC106 2
10_0402_1%
+V_SM_VREF should
have 20 mil trace width
AL1
+1.5V_CPU
RC120
1 1K_0402_0.5%
2
+V_SM_VREF
1 1K_0402_0.5%
2
RC109
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
B4
D1
+VREF_DQA_M3
+VREF_DQB_M3
CC65
0.1U_0402_10V7K
2
+1.5V_CPU Decoupling:
1X 330U (6m ohm), 6X 10U
DDR3 -1.5V RAILS
GRAPHICS
5A
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
10U_0805_10V6K
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
10U_0805_10V6K
10U_0805_10V6K
1
CC55
CC56
CC51
10U_0805_10V6K
CC57
CC52
10U_0805_10V6K
CC53
ESR 6mohm
CC54
@
330U_D2_2VM_R6M
10U_0805_10V6K
C
+VCCSA Decoupling:
1X 330U (6m ohm), 3X 10U
+VCCSA
Bottom Socket Cavity
Co-lay for Cost Down Plan
SA RAIL
6A
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
M27
M26
L26
J26
J25
J24
H26
H25
10U_0805_10V6K
VCCSA_VID0
+VCCSA
10U_0805_10V6K
CC40
CC41
CC42
CC43
1
+
2
2
10U_0805_10V6K
B6
A6
A2
VCCPLL1
VCCPLL2
VCCPLL3
CC61
1U_0402_6.3V6K
VCCSA_SENSE
H23
VCCSA_VID[0]
VCCSA_VID[1]
C22
C24
VCCIO_SEL
A19
VCCSA_VID1
+VCCSA
ESR 17mohm
2+VCCSA_SENSE
0_0402_5%
1
1 RC189
0.90 V
0.80 V
0.75 V
0.65 V
For Sandy Bridge
1
+
CC44
@
330U_D2_2VM_R6M
@
CC67 2
330U_2.5V_M_R17
10U_0805_10V6K
Bottom Socket Edge
1.2A
10U_0805_10V6K
AK35
AK34
+1.5V_CPU
VCCPLL Decoupling:
1X 330U (6m ohm), 1X 10U, 2x1U
RC119
2
1
0_0805_5%
VAXG_SENSE
VSSAXG_SENSE
SM_VREF
+VCCSA_SENSE <45>
1 RC111
0_0402_5% @
MISC
+1.8VS
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
1.8V RAIL
33A
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
Close to CPU
H_VCCSA_VID0
H_VCCSA_VID1
H_VCCSA_VID0 <45>
Please
H_VCCSA_VID1 <45>
kindly check whether

pull down by 10k in PWR-Side
@
+1.5V_CPU
+1.5V_CPU
+1.5VS
PJ1
+1.5V
JUMP_43X118
Vgs=10V,Id=14.5A,Rds=6mohm
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
CC45 1
2 0.1U_0402_10V7K
RC192
470_0805_5%
CC68
10U_0805_10V6K
QC5B
CC69
0.1U_0402_25V6
RC193
1
2
220K_0402_5%
RC194
820K_0402_5%
2
1
+VSB
QC5A
2
2
SUSP
D
D
D
D
1U_0402_6.3V6K
1
2
CC73
4.7U_0805_10V4Z
FDS6676AS_SO8
RUN_ON_CPU1.5VS3
2N7002DW-T/R7_SOT363-6
S
S
S
G
8
7
6
5
2 0.1U_0402_10V7K
CC48 1
3 1
CC47 1
CC72
1
2
+1.5V
QC4
1
2
3
4
CC46 1
CC74
4.7U_0805_10V4Z
1
2
SUSP
SUSP
<5,27,38,43>
2N7002DW-T/R7_SOT363-6
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HF
Date:
Sheet

1
of
51
CFG Straps for Processor
VSS
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
CFG4
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
VCC_DIE_SENSE
VSS_DIE_SENSE
PAD T3
AH27
AH26
RSVD28
RSVD29
RSVD30
RSVD31
L7
AG7
AE7
AK2
RSVD32
W8
RSVD33
RSVD34
RSVD35
AT26
AM33
AJ27
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1: Normal Operation; Lane #

socket pin map definition
definition matches
0:Lane Reversed
AJ31
AH31
AJ33
AH33
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
AJ26
RSVD5
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
J20
B18
RSVD24
RSVD25
J15
RSVD27
RSVD37
RSVD38
RSVD39
RSVD40
T8
J16
H16
G16
CFG4
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
(CFG[17:0] internal pull high to VCCIO)
RC82
1K_0402_1%
IEDP@
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
AR35
AT34
AT33
AP35
AR34
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
JCPUE
RESERVED
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
JCPUI
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
CFG
JCPUH
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
Embedded Display Port Presence Strap

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10
B34
A33
A34
B35
C35
RSVD51
RSVD52
AJ32
AK32
BCLK_ITP
BCLK_ITP#
AN35
AM35
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
KEY
*
CFG4
1 : Disabled; No Physical Display Port

attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
AT2
AT1
AR1
PAD T64
B1
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*10: x8, x8 - Device 1 function 1 enabled ; function 2
@
CFG[6:5]
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately following xxRESETB

de assertion
0: PEG Wait for BIOS for training
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HF
Date:
Sheet
1
10
of
51
+1.5V
JDDR3L
DDR_A_BS2
<7> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDRA_CLK0
DDRA_CLK0#
<7> DDRA_CLK0
<7> DDRA_CLK0#
DDR_A_MA10
DDR_A_BS0
<7> DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
<7> DDR_A_WE#
<7> DDR_A_CAS#
DDR_A_MA13
DDRA_SCS1#
<7> DDRA_SCS1#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
CD25
1
1
CD26
+0.75VS
RD9
10K_0402_5%
+3VS
2.2U_0603_6.3V4Z
0.1U_0402_10V7K
DDR_A_D58
DDR_A_D59
RD8 1
2
10K_0402_5%
GND2
BOSS2
206
208
1
2
DDR_A_D20
DDR_A_D21
+VREF_DQA_M3
DDR_A_D22
DDR_A_D23
1
RD2
1K_0402_1%
BSS138_NL_SOT23-3
QC7
3
1
GND1
BOSS1
+VREF_DQA
@ 1
2
0_0402_5%
RC115
+VREF_DQA
@
1 RC117 2
1K_0402_1%
DDR_A_D28
DDR_A_D29
@
DRAMRST_CNTRL_PCH
DDR_A_DQS#3
DDR_A_DQS3
@
1 RC118 2
1K_0402_1%
DDR_A_D30
DDR_A_D31
<7,17>
+1.5V
@
1
+VREF_DQB_M3
205
207
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
Intel DDR Vref M3
DDR_A_D14
DDR_A_D15
RD10
1K_0402_1%
+VREF_DQB
QC8
BSS138_NL_SOT23-3
DDRA_CKE1
DDRA_CKE1 <7>
@ 1
2
0_0402_5%
RC116
DDR_A_MA15
DDR_A_MA14
+VREF_DQB
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
+1.5V
DDR_A_MA2
DDR_A_MA0
DDRA_CLK1
DDRA_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
2
33P_0402_50V8K
1
CD51
2
33P_0402_50V8K
1
CD52
2
33P_0402_50V8K
1
CD53
2
33P_0402_50V8K
1
CD54
2
33P_0402_50V8K
1
CD55
2
33P_0402_50V8K
+1.5V
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDRA_SCS0# <7>
DDRA_ODT0 <7>
RD6
1K_0402_1%
DDRA_ODT1 <7>
+VREF_CAA_DIMMA
DDR_A_D36
DDR_A_D37
DDR_A_D44
DDR_A_D45
1
CD50
DDRA_CLK1 <7>
DDRA_CLK1# <7>
+VREF_CAA
DDR_A_D38
DDR_A_D39
RD11
1K_0402_1%
RD7
1K_0402_1%
CD15
CD16
0.1U_0402_10V7K
DDR_A_D40
DDR_A_D41
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
SM_DRAMRST# <7,12>
2.2U_0603_6.3V4Z
DDR_A_D34
DDR_A_D35
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
RD1
1K_0402_1%
SM_DRAMRST#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
+1.5V
DDR_A_D12
DDR_A_D13
DDRA_CKE0
<7> DDRA_CKE0
<7>
DDR_A_D26
DDR_A_D27
DDR_A_MA[0..15]
DDR_A_D6
DDR_A_D7
DDR_A_D24
DDR_A_D25
<7>
<7>
DDR_A_D18
DDR_A_D19
DDR_A_D[0..63]
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D16
DDR_A_D17
<7>
DDR_A_DQS#[0..7]
DDR_A_D10
DDR_A_D11
DDR_A_DQS[0..7]
DDR_A_DQS#1
DDR_A_DQS1
Close to JDDRL.1
DDR3 SO-DIMM A
Reverse Type
DDR_A_D8
DDR_A_D9
DDR_A_D4
DDR_A_D5
DDR_A_D2
DDR_A_D3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
Layout Note:
Place near JDDRL
close to JDDRL.126
Layout Note: Place these 4 Caps near

Command and Control signals of DIMMA
Layout Note:
Place near JDDRL1.203 and 204
+1.5V
+1.5V
DDR_A_D52
DDR_A_D53
CD7
CD8
DDR_A_D54
DDR_A_D55
CD9
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2.2U_0603_6.3V4Z
0.1U_0402_10V7K
CD2
DDR_A_D0
DDR_A_D1
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
CD1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
+VREF_DQA
+1.5V
+0.75VS
2 390U_2.5V_M_R10
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
CD10 1
2 10U_0603_6.3V6M
CD11 1
2 10U_0603_6.3V6M
CD12 1
2 10U_0603_6.3V6M
CD13 1
2 10U_0603_6.3V6M
CD20 1
2 0.1U_0402_10V7K
CD17 1
2 0.1U_0402_10V7K
CD18 1
2 0.1U_0402_10V7K
CD19 1
2 0.1U_0402_10V7K
CD56 1
2 10U_0603_6.3V6M
CD24 2
1 1U_0402_6.3V6K
CD21 2
1 1U_0402_6.3V6K
CD22 2
1 1U_0402_6.3V6K
CD23 2
1 1U_0402_6.3V6K
PM_SMBDATA
PM_SMBCLK
PM_SMBDATA <12,17,27,37>
PM_SMBCLK <12,17,27,37>
+0.75VS
Compal Secret Data
2011/12/14
Issued Date
LCN_DAN06-K4406-0103
@
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HF
Date:
Sheet

1
11
of
51
+1.5V
+1.5V
JDDR3H
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
Close to JDDRH.1
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDRB_CKE0
<7> DDRB_CKE0
2
DDR_B_BS2
<7> DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDRB_CLK0
DDRB_CLK0#
<7> DDRB_CLK0
<7> DDRB_CLK0#
DDR_B_MA10
DDR_B_BS0
<7> DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
<7> DDR_B_WE#
<7> DDR_B_CAS#
DDR_B_MA13
DDRB_SCS1#
<7> DDRB_SCS1#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
RD14 1
2
10K_0402_5%
+3VS
2.2U_0603_6.3V4Z
1
@
CD48
2
1 RD15
2
10K_0402_5%
CD49
2
0.1U_0402_10V7K
+0.75VS
205
207
GND1
GND2
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
BOSS1
BOSS2
206
208
DDR_B_D6
DDR_B_D7
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_D12
DDR_B_D13
SM_DRAMRST#
DDR_B_D[0..63]
<7>
<7>
<7>
DDR_B_MA[0..15]
<7>
SM_DRAMRST# <7,11>
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDRB_CKE1
DDRB_CKE1 <7>
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDRB_CLK1
DDRB_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
DDRB_CLK1 <7>
DDRB_CLK1# <7>
+1.5V
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDRB_SCS0# <7>
DDRB_ODT0 <7>
RD12
1K_0402_1%
DDRB_ODT1 <7>
+VREF_CAB
+VREF_CAB_DIMMB
DDR_B_D36
DDR_B_D37
RD13
1K_0402_1%
CD46
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
CD47
0.1U_0402_10V7K
DDR_B_D40
DDR_B_D41
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
DDR_B_DQS#0
DDR_B_DQS0
2.2U_0603_6.3V4Z
DDR_B_D34
DDR_B_D35
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
Reverse Type
DDR3 SO-DIMM B
DDR_B_D4
DDR_B_D5
1
3
Layout Note:
Place near JDDRH
Layout Note: Place these 4 Caps near

Command and Control signals of DIMMB
Layout Note:
Place near JDDRH.203 and 204
Close to JDDRH.126
+1.5V
DDR_B_D52
DDR_B_D53
+1.5V
@
CD31 1
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CD27
0.1U_0402_10V7K
2.2U_0603_6.3V4Z
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CD28
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
DDR_B_D0
DDR_B_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
+VREF_DQB
+0.75VS
2 330U_B2_2.5VM_R15M
CD41 1
2 10U_0603_6.3V6M
CD36 1
2 10U_0603_6.3V6M
CD37 1
2 10U_0603_6.3V6M
CD38 1
2 10U_0603_6.3V6M
CD39 1
2 10U_0603_6.3V6M
CD40 1
2 10U_0603_6.3V6M
CD33 1
2 0.1U_0402_10V7K
CD29 1
2 0.1U_0402_10V7K
CD30 1
2 0.1U_0402_10V7K
CD32 1
2 0.1U_0402_10V7K
CD57 1
2 10U_0603_6.3V6M
CD45 2
1 1U_0402_6.3V6K
CD42 2
1 1U_0402_6.3V6K
CD43 2
1 1U_0402_6.3V6K
CD44 2
1 1U_0402_6.3V6K
PM_SMBDATA
PM_SMBCLK
PM_SMBDATA <11,17,27,37>
PM_SMBCLK <11,17,27,37>
+0.75VS
Compal Secret Data
2011/12/14
Issued Date
FOX_AS0A626-UASN-7F_204P
@
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HF
Date:
Sheet

E
12
of
51
<19> LCD_TXOUT2+
LCD_TXOUT2+
LVDS_TXOUT0-
<19> LCD_TXOUT2-
LCD_TXOUT2-
LVDS_TXOUT1+
<19> LCD_TXCLK+
LCD_TXCLK+
LVDS_TXOUT1-
<19> LCD_TXCLK-
LCD_TXCLK-
1 LVDS@ 2
R300
0_0402_5%
1 LVDS@ 2
R299
0_0402_5%
For RF
2A
C227
4.7U_0805_10V4Z
R108
100K_0402_5%
LVDS@
LVDS@ 2
C228
0.1U_0402_10V7K
LCD_ENVDD_R
1
2.2K_0402_5%
Prevent to use wrong interface panel.
1
L55 @
USB20_P11 <20>
USB20_N11 <20>
2
0_0402_5%
USB20_P13 <20>
USB20_N13_R
USB20_N13 <20>
1
C490
@
1
R97 3D@
BKOFF# <35>
SN74AHC1G08DCKR_SC70-5
Reserve for LVDS panel
Reserve for EMI request

2
RB751V40_SC76-2
PCH_PWM <19>
1 IEDP@ 2
R360
0_0402_5%
1
D17
R131
47K_0402_5%
+3VS_LVDSDDC
2 LVDS@ 1
R1440
0_0603_5%
eDP cable
MB side
CPU_EDP_HPD
<6>
+3VS
C248
0.1U_0402_10V7K
Pin 22
Issued Date
NC
Compal Secret Data
GND
eDP
IN2
2
0_0402_5%
LVDS
UMA_ENBKL <19,35>
1
2
R147
0_0402_5%
LVDS@
Prevent to use wrong interface panel.
Pin 22
LVDS@
WCM-2012-900T_0805
LVDS & eDP cable pine definition notice.

LVDS cable
MB side
2
4
RB751V40_SC76-2
R113
10K_0402_5%
USB20_P13_R
LED_PWM
IN1
P
1
D15
2
1
C489
@
IEDP@
U17
2
0_0402_5%
BKOFF#_R
1
1
R79 3D@
L60 @
C261
1
2
IEDP@ 0.1U_0402_10V7K
Reserve for eDP panel
USB for Glasses free 3D
0.1U_0402_25V6
1
C269
@
+LCD_VDD
IEDP@1
R103
B+
1
C393
close to Q17
C257
47P_0402_50V8J
@
For EMI
C247
@
1
C229
+3VS
B+
Add F3 to prevent
burn on PVT
@
Q20
AO3413_SOT23
LCDPWR_GATE 2
1
2
R96 CAM@ 0_0402_5%
0.1U_0402_25V6
C235
0.1U_0402_25V6
2
USB20_N11_R
+LCD_INV
0.1U_0402_25V6
C234
68P_0402_50V8J
2
W=80mils
1
C233
2
1
USB20_P11_R
+LCD_VDD
+3VS
R112
100K_0402_5%
1
2
R78 CAM@ 0_0402_5%
WCM-2012-900T_0805
1.5A
0.1U_0402_25V6
LVDS@
Q17
AO3413_SOT23
Reserve for EMI request
1.5A
F3
L2
3A_32V_S1206-F-3.0A
2
1
1
2
FBMA-L11-201209-221LMA30T_0805
1
C230
0.01U_0402_25V7K
2
Q1B
2N7002DW-T/R7_SOT363-6
For RF
+LCD_INV
1
R110 2LCDPWR_GATE
1
2
47K_0402_5%
1
10U_0603_6.3V6M
2
R260
<19> UMA_ENVDD
W=80mils
4.7U_0603_6.3V6K
0.1U_0402_10V7K
2 LCD_ENVDD_R
0_0402_5%
IEDP@
R389
0_0603_5%
LVDS@
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
+3VS
20MILS
1
R62
+3VS
for 3D with DCDC/B
R120
100K_0402_5%
IEDP@
GND_R
3D@ 1
2
R1442
0_0603_5%
+5VS
@
1
2 UMA_ENVDD
R361
0_0402_5%
Q1A
2N7002DW-T/R7_SOT363-6
USB20_N13_R
USB20_P13_R
GND_R
LVDS_ENVDD
LED_PWM
BKOFF#_R
R109
150_0603_5%
@
C258 47P_0402_50V8J
2
1
C226
0.1U_0402_10V7K
2
+LCD_VDD
+3VS
LCD_TZOUT0LCD_TZOUT0+
LCD_TZCLKLCD_TZCLK+
LVDS_ENVDD
+LCD_VDD
For LVDS 3D only

INT_MIC_CLK <33>
INT_MIC_DATA <33>
+LCD_VDD
LVDS_TXOUT1LVDS_TXOUT1+
LCD_TXOUT2LCD_TXOUT2+
LCD_TXCLKLCD_TXCLK+
E-T_0871K-F40N-00L
@
+5VS
AZ5125-02S.R7G_SOT23-3
INT_MIC_CLK
INT_MIC_DATA
+PANEL_VDD
+LCD_VDD_R
+3VS_LVDSDDC
LVDS_EDID_CLK
LVDS_EDID_DATA
LVDS_TXOUT0LVDS_TXOUT0+
reserve for 3D w/o DCDC/B
+LCD_VDD
3
D84
40MILS
@
1
2011/12/14
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HF
Date:
+LCD_VDD
+LCD_VDD
USB20_N11_R
USB20_P11_R
IEDP@
Q23
AO3413_SOT23
W=80mils
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
G1
G2
G3
G4
G5
G6
LCDPWR_GATE 1 2
+3VS
LVDS_EDID_DATA
1 IEDP@
0_0603_5%
1 @
0_0603_5%
2
R392
2
R390
+LCD_VDD_R
JLVDS4
41
42
43
44
45
46
1 CAM@ 2 +3VS_LVDS_CAM
R388
0_0603_5%
LVDS_EDID_CLK
W=80mils
CAM@
0.1U_0402_10V7K
1
2
C225
2
W=20mils
+3VS
@
<19> LCD_EDID_DATA
C256 47P_0402_50V8J
2
IEDP@ 2
C293
0.1U_0402_10V7K
1LVDS@
2
R106
0_0805_5%
LCD/PANEL BD. Conn.

only need for 3D with DCDC/B
@
,JLVDS Pin8 can connect to
2
1
+LCV_VDD directly for
R1441
0_0603_5%
3D w/o DCDC/B
+PANEL_VDD
<19> LCD_EDID_CLK
For RF
LVDS_TXOUT1-
LVDS_TXOUT0+
C915
<19> LCD_TXOUT1-
<6> H_EDP_TXN1
C914
<19> LCD_TXOUT1+
LVDS_EDID_DATA
<6> H_EDP_TXP1
C913
LVDS_TXOUT1+
<6> H_EDP_TXN0
1
C912
+5VS
LVDS_TXOUT0-
LVDS_EDID_CLK
<6> H_EDP_TXP0
LVDS_TXOUT0+
C891
IEDP@
1
20.1U_0402_10V7K
IEDP@
1
20.1U_0402_10V7K
IEDP@
1
20.1U_0402_10V7K
IEDP@
1
20.1U_0402_10V7K
IEDP@
1
20.1U_0402_10V7K
IEDP@
1
20.1U_0402_10V7K
<6> H_EDP_AUXN
1 LVDS@ 2
R262
0_0402_5%
1 LVDS@ 2
R263
0_0402_5%
LVDS@
1
2
R265
0_0402_5%
1 LVDS@ 2
R264
0_0402_5%
<19> LCD_TXOUT0+
<19> LCD_TXOUT0-
<6> H_EDP_AUXP
C890
OPT for 2D HD eDP Panel

G
Sheet
13
of
H
51
D4
D5
CRT CONNECTOR
D3
+3VS
If=1A
+5VS
+CRT_VCC_R
+CRT_VCC
D6
F1
DAN217_SC59
DAN217_SC59
DAN217_SC59
1
RB491D_SOT23-3
1
R189
1
R190
1
R191
<19> UMA_CRT_R
<19> UMA_CRT_G
<19> UMA_CRT_B
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
CRT_R_R
L3
2 NBQ100505T-800Y_0402
CRT_R_L
CRT_G_R
L4
2 NBQ100505T-800Y_0402
CRT_G_L
CRT_B_R
L5
2 NBQ100505T-800Y_0402
40 mils
1
2
0.5A_8V_KMC3S050RY
C237
0.1U_0402_10V7K
2
@
CRT_B_L
C241
1
C242
1
C243
2.2P_0402_50V8C
C240
2.2P_0402_50V8C
C239
2.2P_0402_50V8C
C238
2.2P_0402_50V8C
C251
@
2.2P_0402_50V8C
C250
@
2.2P_0402_50V8C
C249
@
2.2P_0402_50V8C
2.2P_0402_50V8C
2
1
150_0402_1%
2
1
150_0402_1%
2
1
150_0402_1%
R138 R139 R140
2.2P_0402_50V8C
JCRT
T65 PAD
CRT_R_L
CRT_DDC_DAT
CRT_G_L
HSYNC
CRT_B_L
+CRT_VCC
VSYNC
T66 PAD
By EMI demand
CRT_DDC_CLK
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
G
G
16
17
C-H_13-12201513CP
2
2
0.1U_0402_10V7K
2
R141
1
L6
2
10_0402_5%
1
2
C252
0.1U_0402_10V7K
2 A
D_CRT_VSYNC
1
L7
2
10_0402_5%
HSYNC
U7
SN74AHCT1G125GW_SOT353-5
C245
@
VSYNC
1
C246
@
10P_0402_50V8J
<19> UMA_CRT_VSYNC
D_CRT_HSYNC
+CRT_VCC
P
OE#
U6
10P_0402_50V8J
1
10K_0402_5%
5
1
<19> UMA_CRT_HSYNC
P
OE#
5
1
1
C244
+CRT_VCC
+CRT_VCC
+3VS
5
Q205B
4
<19> UMA_CRT_DATA
1
C282
33P_0402_50V8K
2
@
2
Q205A
1
<19> UMA_CRT_CLK
R159
4.7K_0402_5%
R153
4.7K_0402_5%
CRT_DDC_CLK
2N7002DW-T/R7_SOT363-6
CRT_DDC_DAT
2N7002DW-T/R7_SOT363-6
C285
33P_0402_50V8K
2 @
C284
470P_0402_50V8J
@
C283
470P_0402_50V8J
2 @
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
Sheet
E
14
of
51
CEC_INT#
P1_5/RXD0/CNTR01/INT11#
CEC_TEST
P1_4/TXD0
13
CEC_FSHUPD1 CEC@ 2
R170
4.7K_0402_5%
1 1
2 CEC@ 1CEC_XOUT 4
R171
47K_0402_5%
P1_3/KI3#/AN11/TZOUT
14
2
G
2 CEC@ 1CEC_XIN
R174
47K_0402_5%
HDMI_CEC
CEC_FSHUPD (Pin13)
Low= Force to update flash.
VCC/AVCC
P1_1/KI1#/AN9/CMP0_1
17
MODE
18
HDMI_DATA
P4_5/INT0#/RXD1
P3_3/TCIN/INT3#/SSI00/CMP1_0
19
HDMI_HPD_R
P3_4/SCS#/SDA/CMP1_1
20
XIN/P4_6
7
1
HDMI_CLK
R165
100K_0402_5%
CEC@
2 CEC@ 1
R176
4.7K_0402_5%
C262
1
0.1U_0402_10V7K
CEC@
HDMI_DATA
HDMI_CECIN
HDMI_CECOUT
10
P1_7/CNTR00/INT10#
HDMI_SCLK
HDMI_SDATA
1
Q48
BSH111_SOT23-3
CEC@
EC_SMB_DA1 <35,40,41>
Q50
2N7002_SOT23-3
CEC@
Q47
BSH111_SOT23-3
CEC@
16
R164
4.7K_0402_5%
CEC@
P4_2/VREF
CEC@
1
2
C848
1U_0402_6.3V6K
1
2
C263
0.1U_0402_10V7K
CEC@
HDMI_CLK
15
VSS/AVSS
+3VL
P1_2/KI2#/AN10/CMP0_2
2
G
R166
4.7K_0402_5%
CEC@
+3VL
1 R163
2
27K_0402_5%
CEC@
+3VL
XOUT/P4_7
CEC_INT# <35> +3VL
1 CEC@ 2
R168
4.7K_0402_5%
RESET#
11
12
2 CEC@ 1CEC_RST#
R169
4.7K_0402_5%
R581
27K_0402_5%
CEC@
HDMI_CECOUT
P3_7/CNTR0#/SSO/TXD1
P1_6/CLK0/SSI01
D9
CH751H-40PT_SOD323-2
CEC@
R162
10K_0402_5%
CEC@
Q49
2N7002_SOT23-3
CEC@
P3_5/SSCK/SCL/CMP1_2
+3VL
HDMI_CECIN
U16
Address: 0011010X
<35,40,41> EC_SMB_CK1
+3VL
+3VL
HDMI CEC Controller
R5F211A4C33SP-W4_LSSOP20
JHDMI1
CEC@
46@
+3VS
+HDMI_5V_OUT
HDMI Royalty
+HDMI_5V_OUT
P
2
U9
HDMI_HPD_C
R186
100K_0402_5%
HDMI@
HDMI_HPD_R
C265
0.1U_0402_10V7K
HDMI@
HDMI@
HDMI_SCLK
Q18
BSH111_SOT23-3
HDMI@
1
<19> UMA_HDMI_DATA
1
2
R185
2.2K_0402_5%
HDMI@
R184
2.2K_0402_5%
HDMI@
G
<19> UMA_HDMI_CLK
HDMIW/OLogo:RO0000001HM
HDMIW/Logo:RO0000002HM
HDMIW/Logo+HDCP:RO0000003HM
2
C264
0.1U_0402_10V7K
HDMI@
HDMI@
R145
HDMI_HPD_U 1
2
1K_0402_5%
OE#
HDMI W/Logo + HDCP
RO0000003HM
HDMI_SDATA
+3VL
Q19
BSH111_SOT23-3
HDMI@
HDMI@
2
1
R570
100K_0402_5%
HDMI@
2
1
R571
2.2K_0402_5%
+3VS
D55
HDMI_HPD_R
HDMI_HPD
<19,21>
HDMI@
@
2
0_0402_5%
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_CK-
4 L8
4
<19> UMA_HDMI_TXC+
<19> UMA_HDMI_TXCB
<19> UMA_HDMI_TX0+
<19> UMA_HDMI_TX0<19> UMA_HDMI_TX1+
<19> UMA_HDMI_TX1<19> UMA_HDMI_TX2+
<19> UMA_HDMI_TX2-
CV308
2 0.1U_0402_10V7K HDMI@
UMA_DVI_TXC+
CV304
2 0.1U_0402_10V7K HDMI@
UMA_DVI_TXC-
CV306
2 0.1U_0402_10V7K HDMI@
UMA_DVI_TXD0+
2 0.1U_0402_10V7K HDMI@
CV303
2 0.1U_0402_10V7K HDMI@
CV301
2 0.1U_0402_10V7K HDMI@
CV307
2 0.1U_0402_10V7K HDMI@
2 0.1U_0402_10V7K HDMI@
CV302
CV305
HDMI@
1
2
WCM-2012-900T_4P
HDMI_R_D1HDMI_R_D1+
HDMI_R_D0+
UMA_DVI_TXC+
1
R173
2
0_0402_5%
HDMI_R_CK+
HDMI_R_D0HDMI_R_D2-
UMA_DVI_TXD0-
UMA_DVI_TXD0+
UMA_DVI_TXD1+
1
R175
2
0_0402_5%
HDMI_R_D0+
HDMI_R_D2+
1 WCM-2012-900T_4P
1
2 2
UMA_DVI_TXD1UMA_DVI_TXD2+
HDMI@3
L9
1 HDMI@ 2
R195
680_0402_1%
1 HDMI@ 2
R197
680_0402_1%
1 HDMI@ 2
R198
680_0402_1%
1 HDMI@ 2
R202
680_0402_1%
1 HDMI@ 2
R201
680_0402_1%
1 HDMI@ 2
R203
680_0402_1%
HDMI@
1
2
R205
680_0402_1%
HDMI@
1
2
R206
680_0402_1%
HDMI@
D53
+5VS
F2
+HDMI_5V_OUT_F
+HDMI_5V_OUT
0.5A_8V_KMC3S050RY
HDMI@
D54
+5VL
C259
HDMI@
0.1U_0402_10V7K
B
PMEG2010AEH_SOD123
CEC@
D
2
G
+5VS
PMEG2010AEH_SOD123
1
R157
UMA_DVI_TXC-
Q24
2N7002_SOT23-3
HDMI@
UMA_DVI_TXD2UMA_DVI_TXD0-
1
R180
2
0_0402_5%
HDMI_R_D0-
UMA_DVI_TXD1-
1
R182
2
0_0402_5%
HDMI_R_D1-
HDMI Connector
JHDMI
4 L10
4
1
HDMI@
HDMI_HPD_C
HDMI_SDATA
HDMI_SCLK
HDMI_CEC
HDMI_R_CK-
1
2 2
WCM-2012-900T_4P
UMA_DVI_TXD1+
@
1
R183
2
0_0402_5%
HDMI_R_D1+
UMA_DVI_TXD2+
1
R187
2
0_0402_5%
HDMI_R_D2+
HDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2-
1 WCM-2012-900T_4P
1
2 2
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+HDMI_5V_OUT
HDMI_R_D2+
4
UMA_DVI_TXD2-
4L11 HDMI@ 3
1
R188
2
0_0402_5%
HDMI_R_D2-
Issued Date
Compal Secret Data

2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
20
21
22
23
SUYIN_100042GR019M23DZL
@
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
Document Number
Rev
B
4019HF
Sheet
1
15
of
51
UH1A
<33> PCH_SPKR
<33> AZ_RST_HD#
+RTCVCC
RH30 1
2 33_0402_5%
SM_INTRUDER#
2
1M_0402_5%
PCH_INTVRMEN
2
330K_0402_5%
RH33 1
+3VS
@
1
RH36
PCH_SPKR
2
1K_0402_5%
PCH_SPK
High = Enabled (No Reboot)
Low = Disabled (Default)
+3VALW_PCH
2
RH272
<33> AZ_SDOUT_HD
RH32 1
2 33_0402_5%
<35> PWRME_CTRL
RH25 1
2 0_0402_5%
INTRUDER#
INTVRMEN
AM10
AM8
AP11
AP10
SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
Y3
Y1
AB3
AB1
20K
SATAICOMPO
Y11
INT.PH 20K
SATAICOMPI
Y10
HDA_SYNCINT.PD
PCH_SPKR
T10
SPKR INT.PD
AZ_RST#
K34
HDA_RST#
20K
20K
E34
INT.PD
HDA_SDIN0
G34
INT.PD 20K
HDA_SDIN1
20K
C34
INT.PD
HDA_SDIN2
A34
INT.PD
HDA_SDIN3
A36
HDA_SDO INT.PD
20K
C36
HDA_DOCK_EN# / GPIO33
20K
20K
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCKINT.PD 20K
T67 PAD
PCH_JTAG_TMS
H7
JTAG_TMSINT.PH
T68 PAD
PCH_JTAG_TDI
K5
JTAG_TDI
T69 PAD
PCH_JTAG_TDO
H1
JTAG_TDO
JTAG
ME debug mode,
this signal has a weak internal pull down
= Disable (default)
*Low
High = Enable (flash descriptor security overide)
PCH_JTAG_TCK
signal has a weak internal pull

*This
H=>On Die PLL is supplied by 1.5V
down
<27> PCH_RTCX1_R
L=>On Die PLL is supplied by 1.8V

Need to pull high for Huron River platform
2
RH55
+3VALW_PCH
RH26 GCLK@
PCH_RTCX1
1
2
0_0402_5%
Placement near to YH1
+5VS
AZ_SYNC_R
2
33_0402_5%
1
RH56
2
1M_0402_5%
2
37.4_0402_1%
+1.05VS_VCC_SATA
SATA3_COMP
1
RH48
2
49.9_0402_1%
+1.05VS_SATA3
1
RH41
2
750_0402_1%
SATA3COMPI
AB13
SATA_LED#
RH29 2
1 10K_0402_5%
PCH_GPIO21
RH34 2
1 10K_0402_5%
PCH_GPIO19
RH28 1
2 10K_0402_5%
+RTCBATT
SATA3RBIAS
AH1
RBIAS_SATA3
T3
SPI_CLK
Y14
SPI_CS0#
PCH_SPICS1#
T1
SPI_CS1#
P3
SATA_LED#
PCH_SPIDI
V4
SPI_MOSI
INT.PD 20K
SATA0GP / GPIO21
V14
PCH_GPIO21
PCH_SPIDO
U3
SPI_MISO
INT.PH 20K
SATA1GP / GPIO19
P1
PCH_GPIO19
DH7
RB751V-40_SOD323-2
+RTCBATT
+3VL
If use GCLK, please delet DH1
PCH_GPIO19 <20>
INT.PH 20K
BOOT BIOS Strap Bit 0
PANTHER-POINT_FCBGA989
HM76R3@
1
RH54
<33> AZ_SYNC_HD
QH1
1
ODD
1
RH43
AB12
+3VS
m-SATA
SATAICOMP
SATA3RCOMPO
SATALED#
SATA_PRX_C_DTX_N1 <27>
SATA_PRX_C_DTX_P1 <27>
SATA_PTX_DRX_N1 <27>
SATA_PTX_DRX_P1 <27>
1
10K_0402_5%
HDD
PCH_SPICS0#
AZ_SYNC
1
1K_0402_5%
2
RH31
+RTCVCC
PCH_SPICLK
SPI
HDA_SYNC
SERIRQ
SERIRQ <35>
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
HDA_BCLK
L34
8/30 Change PWRME_CTRL# to HDA_SDO by PCH EDS
HDA_SDO
+3VS
SERIRQ
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
N34
N32
SERIRQ
V5
LPC_FRAME# <35,36>
AM3
AM1
AP7
AP5
AZ_SYNC
AZ_SDOUT
LPC_FRAME#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AZ_BITCLK
1
1K_0402_5%
D36
E36
K36
LPC
C17
AZ_SDIN0_HD
<33> AZ_SDIN0_HD
RH12 1
PCH_INTVRMEN
FWH4 / LFRAME#
INT.PH 20K LDRQ0#

INT.PH LDRQ1#
20K / GPIO23
<33> AZ_BITCLK_HD
Integrated SUS 1.05V VRM Enable

High - Enable Internal VRs
PCH_INTVRMEN (must be always pulled high)
2 33_0402_5%
K22
<35,36>
<35,36>
<35,36>
<35,36>
RH27 1
SRTCRST#
SM_INTRUDER#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
NOGCLK@
RTCRST#
G22
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
DH1
D20
PCH_SRTCRST#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
20K
20K
20K
20K
CH3
CH101
10P_0402_50V8J
1
15P_0402_50V8J
PCH_RTCRST#
C38
A38
B37
C37
INT.PH
INT.PH
INT.PH
INT.PH
RB751V-40_SOD323-2
RTCX2
CH8
CH5 1
1U_0402_6.3V6K
RTCX1
C20
0.1U_0402_10V7K
@
2
YH1
32.768KHZ_12.5P_1TJF125DP1A000D
NOGCLK@
A20
PCH_RTCX2
SATA 6G
AZ_BITCLK_HD
PCH_RTCX1
SATA
2PCH_SRTCRST#
RH24 1
20K_0402_5%
1
15P_0402_50V8J
NOGCLK@
RTC
JME
1
IHDA
iME Setting.
CH2
NOGCLK@
CH4 1
1U_0402_6.3V6K
RH2
10M_0402_5%
2
1
JCMOS @
1
2
PCH_RTCRST#
RH23 1
20K_0402_5%
CMOS Setting, near DDR Door

+RTCVCC
BSS138_NL_SOT23-3
@
1
2
RH274
0_0402_5%
+3VS
SPI ROM for BIOS & ME (4MByte )

1
47P_0402_50V8J
CH19
CH6
@ 0.1U_0402_10V7K
For RF
PCH_SPICLK
PCH_SPIDI
UH3
PCH_SPICS0#
1
RH66
1
RH67
PCH_SPI0_CLK
2
33_0402_5%
PCH_SPI0_DI
2
33_0402_5%
VCC
HOLD
VSS
4MB ROM P/N:

SA00003K800
SA00004LI00
PCH_SPI0_DO
1
RH68
PCH_SPIDO
2
33_0402_5%
PCH_SPI0_CLK
for EMI
CH7
10P_0402_50V8J
2
1
PCH_JTAG_TDO
PCH_JTAG_TDI
RH40
100_0402_1%
RH39
100_0402_1%
PCH_SPI1_CLK
for EMI
RH69
10_0402_5%
WIN8@
RH65
10_0402_5%
2MB ROM P/N:

SA000041N00
SA00003FO10
RH44
100_0402_1%
PCH_JTAG_TMS
RH38
200_0402_5%
RH45
200_0402_5%
MX25L1606EM2I-12G_SO8
WIN8@
RH46
200_0402_5%
8
7
6
5
VCC
HOLD#
SCLK
SI
CS#
SO
WP#
GND
1
2
3
4
+3VALW_PCH
1
RH50
PCH_JTAG_TCK
2
51_0402_1%
UH4
PCH_SPICS1#
PCH_SPIDO 1 WIN8@ 2 PCH_SPI1_DO
RH269
33_0402_5% +3VS
+3VALW_PCH
+3VALW_PCH
1
2
@ CH20
0.1U_0402_10V7K
1
2
CH100
WIN8@
RH267 33_0402_5%
PCH_SPI1_CLK
PCH_SPICLK
1 WIN8@ 2
PCH_SPI1_DI
PCH_SPIDI
1
2
RH271 33_0402_5%
WIN8@
SPI ROM for Win8 (2MByte )
Socket: SP07000F500/SP07000H900
Please place U13 & U4 close to U2 PCH,
please place RH66, RH67, RH68 near UH3
Please place RH267 near RH66, Please place RH271 near RH67,
Please place RH269 near RH68. +3VS 47P_0402_50V8J For RF
MX25L3205DM2I-12G SO8
CH21
10P_0402_50V8J
WIN8@
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HF
Date:
Sheet
1
16
of
51
BE34
BF34
BB32
AY32
PERN2
PERP2
PETN2
PETP2
BG36
BJ36
AV34
AU34
Card Reader
EX-USB30
<29>
<29>
<29>
<29>
PCIE_PRX_C_CRTX_N4
PCIE_PRX_C_CRTX_P4
PCIE_PTX_C_CRRX_N4
PCIE_PTX_C_CRRX_P4
<31>
<31>
<31>
<31>
PCIE_PRX_C_USBTX_N5
PCIE_PRX_C_USBTX_P5
PCIE_PTX_C_USBRX_N5
PCIE_PTX_C_USBRX_P5
<27>
<27>
<27>
<27>
TV tuner
PCIE_PRX_C_TVTX_N6
PCIE_PRX_C_TVTX_P6
PCIE_PTX_C_TVRX_N6
PCIE_PTX_C_TVRX_P6
CH18 1
CH16 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
CH12 1
CH9 1
EUSB30@
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
EUSB30@
EUSB30@
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
EUSB30@
CH10 1
CH1 1
BF36
BE36
AY34
BB34
PERN4
PERP4
PETN4
PETP4
PCIE_PRX_C_USBTX_N5
PCIE_PRX_C_USBTX_P5
PCIE_PTX_USBRX_N5
PCIE_PTX_USBRX_P5
BG37
BH37
AY36
BB36
PERN5
PERP5
PETN5
PETP5
BJ38
BG38
AU36
AV36
PERN6
PERP6
PETN6
PETP6
BG40
BJ40
AY40
BB40
PERN7
PERP7
PETN7
PETP7
+3VS
RH99 1
2 10K_0402_5% PCH_GPIO20
RH1041
2 10K_0402_5% CLKREQ_WLAN#
RH95 1
210K_0402_5%
BE38
BC38
AW38
AY38
CLKREQ_LAN#
Intel Spec:
PCIECLK_RQ0# is suspend well,
but we pull high to +3VS
for LAN en/disable function
LAN
<28>
<28>
CLK_LAN#
CLK_LAN
CLK_LAN#
CLK_LAN
CLKREQ_LAN#
<28> CLKREQ_LAN#
J2
CLK_WLAN#
CLK_WLAN
<27> CLK_WLAN#
<27> CLK_WLAN
WLAN
Y40
Y39
AB49
AB47
CLKREQ_WLAN#
<27> CLKREQ_WLAN#
M1
AA48
AA47
<29>
Card Reader <29>
CLK_CR#
CLK_CR
EX-USB30
<27> CLK_TV#
<27> CLK_TV
TV tuner
<27> CLKREQ_TV#
SML0CLK
SML0DATA
PCH_SMBCLK
PCH_SMBDATA
1 2.2K_0402_5%
2 RH70
1 2.2K_0402_5%
PCH_SMBDATA
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCH_SMLCLK1
SML1DATA / GPIO75
M16
PCH_SMLDATA1
CL_CLK1
L12
4.7K_0402_5%
4.7K_0402_5%
PM_SMBDATA <11,12,27,37>
2N7002DW-T/R7_SOT363-6
PM_SMBCLK <11,12,27,37>
+3VALW_PCH
LAN_EN <28>
2 RH78
1 2.2K_0402_5%
2 RH74
1 2.2K_0402_5%
+3VS
QH4B
PCH_SMLDATA1
3
QH4A
PCH_SMLCLK1
EC_SMB_DA2 <35,36>
2N7002DW-T/R7_SOT363-6
EC_SMB_CK2 <35,36>
M7
CL_DATA1
T11
CL_RST1#
P10
Control Link only for support Intel IAMT.

+3VALW_PCH
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
PCH_SMBALERT#
RH2621
2 10K_0402_5%
DRAMRST_CNTRL_PCH
RH76 1
2 1K_0402_5%
LAN_EN
RH75 1
2 10K_0402_5%
PCH_SMLCLK0
RH73 2
1 2.2K_0402_5%
PCH_SMLDATA0
RH77 2
1 2.2K_0402_5%
PCH_GPIO47
M10
AB37
AB38
PCH_GPIO47
RH89
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
AU22
CLK_CPU_DMI#
CLK_CPU_DMI
CLKOUT_DP_N
CLKOUT_DP_P
AM12
AM13
CLK_CPU_EDP#
CLK_CPU_EDP
CLKIN_DMI_N
CLKIN_DMI_P
BF18
BE18
PCH_CLK_DMI#
PCH_CLK_DMI
CLKIN_GND1_N
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_GND1_P
BJ30
BG30
CLKIN_GND1#
CLKIN_GND1
G24
E24
CLK_DOT#
CLK_DOT
CLKIN_SATA_N
CLKIN_SATA_P
AK7
AK5
CLK_SATA#
CLK_SATA
REFCLK14IN
K45
CLK_14M_PCH
CLKIN_PCILOOPBACK
H45
CLK_PCILOOP
XTAL25_IN
XTAL25_OUT
V47
V49
PCH_X1
PCH_X2
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
RH102
RH103
2N7002DW-T/R7_SOT363-6
DRAMRST_CNTRL_PCH <7,11>
LAN_EN
E14
Y43
Y45
PCH_SMLDATA0
SML1CLK / GPIO58
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
PCH_SMLCLK0
G12
C13
Y37
Y36
C8
+3VS
QH3B
3
QH3A
DRAMRST_CNTRL_PCH
A12
SML1ALERT# / PCHHOT# / GPIO74
PEG_A_CLKRQ# / GPIO47
CLK_CR#
CLK_CR
CLKREQ_USBA30#
<31> CLKREQ_USBA30#
SML0ALERT# / GPIO60
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLK_USBA30#
CLK_USBA30
<31> CLK_USBA30#
<31> CLK_USBA30
H14
C9
2 RH72
2N7002DW-T/R7_SOT363-6
PERN8
PERP8
PETN8
PETP8
V10
A8
PCH_SMBALERT#
PCH_SMBCLK
PCH_GPIO20
CLKREQ_CR#
<29> CLKREQ_CR#
SMBCLK
SMBDATA
PERN3
PERP3
PETN3
PETP3
PCIE_PRX_C_CRTX_N4
PCIE_PRX_C_CRTX_P4
PCIE_PTX_CRRX_N4
PCIE_PTX_CRRX_P4
PCIE_PRX_C_TVTX_N6
PCIE_PRX_C_TVTX_P6
PCIE_PTX_TVRX_N6
PCIE_PTX_TVRX_P6
SMBALERT# / GPIO11
E12
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
+3VALW_PCH
Link
CH14 2
CH17 2
PERN1
PERP1
PETN1
PETP1
SMBUS
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_C_WLANRX_N2
PCIE_PTX_C_WLANRX_P2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
BG34
BJ34
AV32
AU32
Controller
WLAN
<27>
<27>
<27>
<27>
CH13 2
CH11 2
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1
CLOCKS
LAN
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1
PCI-E*
<28>
<28>
<28>
<28>
UH1B
CLK_TV#
CLK_TV
V45
V46
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKREQ_TV#
L14
PCIECLKRQ5# / GPIO44 INT. PH 20K
1
10K_0402_5%
CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
CLK_CPU_EDP# <5>
CLK_CPU_EDP <5>
120 MHz for eDP
From Clock Gen.
PCH_CLK_DMI#
PCH_CLK_DMI
RH79 1
RH82 1
2 10K_0402_5%
2 10K_0402_5%
CLKIN_GND1#
CLKIN_GND1
RH85 1
RH86 1
2 10K_0402_5%
2 10K_0402_5%
CLK_DOT#
CLK_DOT
RH80 1
RH81 1
2 10K_0402_5%
2 10K_0402_5%
CLK_SATA#
CLK_SATA
RH83 1
RH84 1
2 10K_0402_5%
2 10K_0402_5%
CLK_14M_PCH
RH87 1
2 10K_0402_5%
For EMI
@
2
RH124
CLK_PCILOOP
CLK_PCILOOP <20>
@
2
1
CH28
22P_0402_50V8J
1
10_0402_5%
+3VALW_PCH
RH1101
210K_0402_5%
RH1121
210K_0402_5% CLKREQ_TV#
RH1191 LVDS@ 210K_0402_5%
AB42
AB40
Please place under DDR SODIMM.

10/25
PASSWORD_CLEAR#
CLKREQ_CR#
JPW
@
E6
PANEL_SEL
LVDS_SEL
210K_0402_5% PASSWORD_CLEAR#
RH1141
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PANEL_SEL
Y47
XCLK_RCOMP
1
RH115
CLKOUTFLEX0 / GPIO64
K43
CLK_FLEX0
T72
PAD
F47
CLK_FLEX1
T74
PAD
H47
CLK_FLEX2
T73
PAD
K49
DGPU_PRSNT#
XCLK_RCOMP
V40
V42
CLKOUT_PCIE6N
CLKOUT_PCIE6P
T13
V38
V37
CLKOUT_PCIE7N
CLKOUT_PCIE7P
K12
AK14
AK13
2
90.9_0402_1%
<27> PCH_X1_R
+1.05VS_VCCDIFFCLKN
INT.PH 20K
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
INT. PD 20K
INT. PD 20K
INT. PD 20K
NOGCLK@
RH1172
1 1M_0402_5%
NOGCLK@
YH2 25MHZ_20PF_7V25000016
PCH_X1
CH26
NOGCLK@
27P_0402_50V8J
Compal common design SW request to

add DGPU_Present on this GPIO67
+3VALW_PCH
RH282
1 HD@
1 FHD@
2
10K_0402_5%
2
10K_0402_5%
LVDS_SEL
LVDS_SEL
RH282
10K_0402_5%
3D@
LVDS_SEL
LVDS_SEL
Channel
PANEL_SEL
PANEL_SEL
Single
(Default)
Dual
Channel
3
GND
GND
PCH_X2
CH27
NOGCLK@
27P_0402_50V8J
DGPU_PRSNT#
LVDS
EDP
DGPU_PRSNT#
UMA
DIS/OPT
DGPU_PRSNT#
1
RH227
M/B SKU
RH261
1 IEDP@ 2
RH275
10K_0402_5%
PCH_X1
Placement near to YH2

INT. PD 20K
HM76R3@
RH116
RH37
1
2
0_0402_5%
GCLK@
PEG_B_CLKRQ# / GPIO56
FLEX CLOCKS
210K_0402_5% CLKREQ_USBA30#
RH1071
1 @
2
10K_0402_5%
+3VS
2
10K_0402_5%
PANEL_SEL
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HF
Date:
Sheet

1
17
of
51
UH1C
2
RH163
2
RH278
2
RH279
PCH_SUSPWRDN#_R
RI#
PCH_LOW_BAT#
PCH_RSMRST#
1
10K_0402_5%
PM_PWROK
1
10K_0402_5%
SYS_PWROK
1
10K_0402_5%
PM_PWROK
IN1
IN2
BE24
BC20
BJ18
BJ20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
<6>
<6>
<6>
<6>
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
<6>
<6>
<6>
<6>
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
UH5
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
FDI_INT
AW16
FDI_INT
BJ24
DMI_ZCOMP
FDI_FSYNC0
AV12
FDI_FSYNC0
BG25
DMI_IRCOMP
FDI_FSYNC1
BC10
FDI_FSYNC1
BH21
DMI2RBIAS
FDI_LSYNC0
AV14
FDI_LSYNC0
FDI_LSYNC1
BB10
FDI_LSYNC1
DSWVRMEN
A18
DSWVREN
1 PCH_SUSPWRDN#_R
0_0402_5%
<35> PCH_RSMRST#
Stuff R137 if EC does not want to

involve in the handshake mechanism
for the DeepSX state entry and exit
<35> PCH_SUSPWRDN#
@
RH132
1
RH161
2
330K_0402_5%
DH2
<35,41>
ACIN
FDI_FSYNC0
<6>
FDI_LSYNC0
<6>
FDI_LSYNC1
<6>
PWRBTN# INT.PH
20K
SLP_A#
G10
PM_SLP_A#
T77
PAD
ACPRESENT / GPIO31INT.PD 20K
SLP_SUS#
G16
PM_SLP_SUS#
T78
PAD
PCH_LOW_BAT#
E10
BATLOW# / GPIO72 INT.PH
PMSYNCH
AP14
H_PM_SYNC
RI#
A10
RI#
K14
PCH_GPIO29
P12
SYS_PWROK
L22
PWROK
APWROK
B13
DRAMPWROK
PCH_RSMRST#
C21
RSMRST#
Reserve this signal to EC by SW demand

2011/10/18a
EC_SWI#
CLKRUN# / GPIO32
N3
PCH_GPIO32
G8
SUS_STAT#
1
RH128
PCH_RSMRST#
2
0_0402_5%
Stuff R222 if do not support DeepSX state
+RTCVCC
E20
B9
PCH_DPWROK
<6>
FDI_FSYNC1
H20
WAKE#
DPWROK
FDI_INT <6>
PCH_ACIN
E22
PCH_DPWROK
INT.PH 20K
SYS_RESET#
Reserve for SW-node noise issue

place close to PCH
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
PBTN_OUT#
SUSACK#
K3
DRAMPWROK
2 PCH_SUSPWRDN#_R
0_0402_5%
<35> PBTN_OUT#
+3VALW_PCH
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
SUSWARN#/SUSPWRDNACK/GPIO30
PM_PWROK_R
2
0_0402_5%
<5> DRAMPWROK
@
2
RH281
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
K16
C12
L10
SUSACK#_R
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
SUS_STAT# / GPIO61
SUSACK#_R
2
0_0402_5%
XDP_DBRESET#
PM_PWROK
1
RH131
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
AY24
AY20
AY18
AU18
SYS_PWROK
@
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
RBIAS_CPY
2
750_0402_1%
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
1
RH127
RH47
2
1
1K_0402_5%
+3VS
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
AW24
AW20
BB18
AV18
DMI_COMP
2
49.9_0402_1%
@
1
RH133
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
1
RH126
<35> SUSACK#
O
3
<5,35> PM_PWROK
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
VGATE
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<35,46>
<6>
<6>
<6>
<6>

2011/10/18a
+3VS
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
+1.05VS_PCH
0_0402_5%
1 RH280 2
0.1U_0402_10V7K
1
2
CH103
BC24
BE20
BG18
BG20
FDI
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
System Power Management
2
RH234
2
RH157
2
RH155
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI
+3VALW_PCH
<6>
<6>
<6>
<6>
DSWVREN
RH150
RH151
1 330K_0402_5%
@
1 330K_0402_5%
EC_SWI# <28,31>
C
DSWVREN must be always pulled high to +RTCVCC

T76
PAD
32.768 KHz
SUSCLK / GPIO62
CLK_EC <35>
D10
PM_SLP_S5#
SLP_S4#
H4
PM_SLP_S4#
SLP_S3#
F4
PM_SLP_S3#
SLP_S5# / GPIO63
20K
N14
SLP_LAN# / GPIO29
DSWVREN - Internal Deep Sleep 1.05V regulator

HEnable
LDisable
PM_SLP_S5# <35>
PM_SLP_S4# <31,35>
Follow EC check list demand,

but don't implement CLKRUN# this fuction
PM_SLP_S3# <35>
+3VS
PCH_GPIO32
H_PM_SYNC <5>
RH2561
1
RH160
2 8.2K_0402_5%
2
10K_0402_5%
HM76R3@
1
CH23
SYS_PWROK
2
0.01U_0402_25V7K
1
CH24
PCH_RSMRST#
2
0.01U_0402_25V7K
EC_SWI#
RH1591
2 10K_0402_5%
1
CH25
PM_PWROK_R
2
0.01U_0402_25V7K
PCH_GPIO29
RH1621 @
2 10K_0402_5%
+3VALW_PCH
DH5
PM_PWROK
PCH_RSMRST#
DH6
<40,42>
POK
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HF
Date:
Sheet

1
18
of
51
UH1D
1
RH143
1
RH125
UMA_ENBKL
2
100K_0402_5%
2
RH145
LCTL_CLK
1
2.2K_0402_5%
2
RH146
LCTL_DATA
1
2.2K_0402_5%
2
RH149
LCD_EDID_CLK
1
2.2K_0402_5%
2
RH148
LCD_EDID_DATA
1
2.2K_0402_5%
2
RH142
UMA_CRT_CLK
1
2.2K_0402_5%
2
RH144
UMA_CRT_DATA
1
2.2K_0402_5%
1
RH156
UMA_CRT_B
2
150_0402_1%
1
RH152
UMA_CRT_G
2
150_0402_1%
1
RH154
UMA_CRT_R
2
150_0402_1%
L_DDC_CLK
INT.PD
L_DDC_DATA
LCTL_CLK
LCTL_DATA
T45
P39
L_CTRL_CLK
L_CTRL_DATA
<13> LCD_TXOUT0<13> LCD_TXOUT1<13> LCD_TXOUT2<13> LCD_TXOUT0+

<13> LCD_TXOUT1+
<13> LCD_TXOUT2+
<13> LCD_TZCLK<13> LCD_TZCLK+

<13> LCD_TZOUT0<13> LCD_TZOUT1<13> LCD_TZOUT2<13> LCD_TZOUT0+
<13> LCD_TZOUT1+
<13> LCD_TZOUT2+
<14> UMA_CRT_B
<14> UMA_CRT_G
<14> UMA_CRT_R
<14> UMA_CRT_CLK
<14> UMA_CRT_DATA
<14> UMA_CRT_HSYNC
<14> UMA_CRT_VSYNC
2
RH138
AF37
AF36
AM42
AM40
LVD_VREFH
LVD_VREFL
LCD_TXCLKLCD_TXCLK+
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2-
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LCD_TXOUT0+
LCD_TXOUT1+
LCD_TXOUT2+
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
SDVO_INTN
SDVO_INTP
AP39
AP40
RH140
2.2K_0402_5%
HDMI@
LVD_IBG
LVD_VBG
AE48
AE47
20K
+3VS
SDVO_CTRLCLK
SDVO_CTRLDATA
T40
K47
AP43
AP45
INT.PD 50
SDVO_STALLN
INT.PD 50
SDVO_STALLP
L_BKLTCTL
LCD_EDID_CLK
LCD_EDID_DATA
INT.PD 50SDVO_TVCLKINN
INT.PD 50SDVO_TVCLKINP
RH139
2.2K_0402_5%
HDMI@
P38
M39
UMA_HDMI_CLK <15>
UMA_HDMI_DATA <15>
INT.PD 20K
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
AT49
AT47
AT40
HDMI_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
UMA_HDMI_TX2UMA_HDMI_TX2+
UMA_HDMI_TXCUMA_HDMI_TXC+
DDPC_CTRLCLK
DDPC_CTRLDATA
P45
LVDS_IBG
2
2.37K_0402_1%
T79 PAD
<13> LCD_TXCLK<13> LCD_TXCLK+

+3VS
PCH_PWM
L_BKLTEN
L_VDD_EN
Digital Display Interface
J47
M45
LVDS
<13> PCH_PWM
<13> LCD_EDID_CLK
<13> LCD_EDID_DATA
UMA_ENBKL
UMA_ENVDD
HDMI_HPD
HDMI_HPD <15,21>
UMA_HDMI_TX2- <15>
UMA_HDMI_TX2+ <15>
UMA_HDMI_TX1- <15>
UMA_HDMI_TX1+ <15>
UMA_HDMI_TX0- <15>
UMA_HDMI_TX0+ <15>
UMA_HDMI_TXC- <15>
UMA_HDMI_TXC+ <15>
2
1
100K_0402_5%
RH254
HDMI
P46
P42
INT.PD 20K
LCD_TZCLKLCD_TZCLK+
AF40
AF39
LVDSB_CLK#
LVDSB_CLK
LCD_TZOUT0LCD_TZOUT1LCD_TZOUT2-
AH45
AH47
AF49
AF45
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LCD_TZOUT0+
LCD_TZOUT1+
LCD_TZOUT2+
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
UMA_CRT_B
UMA_CRT_G
UMA_CRT_R
N48
P49
T49
CRT_BLUE
CRT_GREEN
CRT_RED
UMA_CRT_CLK
UMA_CRT_DATA
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
UMA_CRT_HSYNC
UMA_CRT_VSYNC
M47
M49
CRT_HSYNC
CRT_VSYNC
CRT_IREF
1
1K_0402_0.5%
T43
T42
DAC_IREF
CRT_IRTN
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
AP47
AP49
AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
DDPD_CTRLCLK
DDPD_CTRLDATA
RH141
1 100K_0402_5%
C
M43
M36
INT.PD 20K
CRT
<13,35> UMA_ENBKL
<13> UMA_ENVDD
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
AT45
AT43
BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
RH255
1 100K_0402_5%
HM76R3@
B
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HF
Date:
Sheet
1
19
of
51
+3VS
U3RXDN1_R
U3RXDN2_R
U3RXDN3_R
U3RXDN4_R
U3RXDP1_R
U3RXDP2_R
U3RXDP3_R
U3RXDP4_R
U3TXDN1
U3TXDN2
U3TXDN3
U3TXDN4
U3TXDP1
U3TXDP2
U3TXDP3
U3TXDP4
<27>
<25>
RF_OFF#
ODD_DA#
B21
M20
AY16
BG46
TP21
TP22
TP23
TP24
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
RSVD1
RSVD2
RSVD3
RSVD4
AY7
AV7
AU3
BG4
RSVD5
RSVD6
AT10
BC8
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
RSVD23
AV5
AV10
DF_TVS RSVD24
USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4
AT8
RSVD26
RSVD27
AY5
BA2
RSVD28
RSVD29
AT12
BF3
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USBRBIAS#
C33
USBBIAS
USBRBIAS
B33
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
A14
K20
B17
C16
L16
A16
D14
C14
EHCI 1
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
K40
K38
H38
G38
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PCH_GPIO50
PCH_GPIO52
PCH_GPIO54
C46
C44
E40
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
RF_OFF#
PCH_GPIO53
PCH_GPIO55
D47
E42
F46
EHCI 2
GNT1# / GPIO51INT.PH 20K
INT.PH
20K
GNT2# / GPIO53
GNT3# / GPIO55INT.PH 20K
PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PCI_PME#
PLT_RST#
C6
2 RH167 CLK_EC_R
2 RH166 CLK_PCH
2 RH284 CLK_SIO
H49
H43
J48
K42
H40
<5,27,28,29,31,35,36> PLT_RST#
<35> CLK_PCI_EC
<17> CLK_PCILOOP
<36> CLK_PCI_DDR
22_0402_5% 1
22_0402_5% 1
22_0402_5% 1
K10
@
2
180P_0402_50V8J
1
CH15
CH22
47P_0402_50V8J
@
1 CH104
PLT_RST#
1K_0402_5% 2
1 RH285
RF_OFF#
1K_0402_5% 2
1 RH286
PCH_GPIO19
<30>
<30>
<30>
<30>
<25>
<25>
<25>
<25>
USB-RIGHT1
Intel Anti-Theft Techonlogy
USB-RIGHT2
High=Endabled
NV_ALE
Low=Disable(floating)
USB-Left1
USB-Left2
+1.8VS
NV_ALE
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12
USB20_N13
USB20_P13
USB20_N8 <26>
USB20_P8 <26>
USB20_N9 <27>
USB20_P9 <27>
USB20_N10 <27>
USB20_P10 <27>
USB20_N11 <13>
USB20_P11 <13>
USB20_N12 <27>
USB20_P12 <27>
USB20_N13 <13>
USB20_P13 <13>
1
RH165
1 @
RH164
2
1K_0402_5%
Finger Printer
WiMax
TV Tuner #1
Int. Camera
3G/ TV tuner #2
Glasses free 3D Panel
2
22.6_0402_1%
Within 500 mils
PME#
INT.PH
PLTRST#
20K
INT.PD
CLKOUT_PCI0
INT.PD
CLKOUT_PCI1
INT.PD
CLKOUT_PCI2
INT.PD
CLKOUT_PCI3
INT.PD
CLKOUT_PCI4
20K
20K
20K
20K
20K
USB_OC#0
USB_OC#1
USB_OC#2
SLP_CHG_M3
SLP_CHG_M4
USB_OC#5
USB30_SMI#
USBA30_SMI#
USB_OC#0 <30,35> USB-Right

USB_OC#1 <25,31,35>USB-Left &
eSATA
SLP_CHG_M3 <25>
SLP_CHG_M4 <25>
+3VALW_PCH
USBA30_SMI# <31>
USB30_SMI# 1
RH209
SLP_CHG_M3 1
RH196
SLP_CHG_M4 1
RH200
USB_OC#1
1
RH192
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
USB_OC#2
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
Boot BIOS Strap

RF_OFF#
@
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
HM76R3@
ODD_DA#
by ESD requestion and place near CPU
0.1U_0402_10V7K
NV_ALE
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
T80 PAD
RSVD25
INT.PD 20K
USB
<30> U3RXDN1_R
<30> U3RXDN2_R
<25> U3RXDN3_R
<25> U3RXDN4_R
<30> U3RXDP1_R
<30> U3RXDP2_R
<25> U3RXDP3_R
<25> U3RXDP4_R
<30> U3TXDN1
<30> U3TXDN2
<25> U3TXDN3
<25> U3TXDN4
<30> U3TXDP1
<30> U3TXDP2
<25> U3TXDP3
<25> U3TXDP4
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
PCI
PCH_GPIO54
2
8.2K_0402_5%
PCH_GPIO4
2
8.2K_0402_5%
PCI_PIRQB#
2
8.2K_0402_5%
PCI_PIRQC#
2
8.2K_0402_5%
PCH_GPIO52
2
8.2K_0402_5%
PCH_GPIO53
2
8.2K_0402_5%
PCI_PIRQA#
2
8.2K_0402_5%
ODD_DA#
2
8.2K_0402_5%
PCH_GPIO55
2
8.2K_0402_5%
PCH_GPIO2
2
8.2K_0402_5%
PCH_GPIO50
2
8.2K_0402_5%
RF_OFF#
2
8.2K_0402_5%
PCI_PIRQD#
2
8.2K_0402_5%
PCH_GPIO5
2
8.2K_0402_5%
1
RH318
1
RH319
1
RH320
1
RH321
1
RH324
1
RH323
1
RH325
1
RH322
1
RH326
1
RH327
1
RH328
1
RH329
1
RH283
1
RH290
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
RSVD
UH1E
PCH_GPIO19
0
0
1
1
0
1
0
1
Boot BIOS Loaction
1
RH177
1
RH183
USBA30_SMI# 1
RH201
USB_OC#0
1
RH188
LPC
USB_OC#5
Reserved
PCI
SPI
PCH_GPIO19 <16>
A16 Swap Override Strap

WL_OFF#
1K_0402_5% 2
1 RH287
Low= A16 swap override Enable

High= A16 swap override Disable
PCH_GPIO55
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HF
Date:
Sheet

1
20
of
51
<15,19> HDMI_HPD
EC_LID_OUT#
PCH_GPIO6
PCH_GPIO12
PCH_GPIO28
HDD2_DET#
2
10K_0402_5%
HDMI_HPD
2
10K_0402_5%
PCH_GPIO1
2
10K_0402_5%
BT_DET#
2
10K_0402_5%
OPTIMUS_EN#
2
10K_0402_5%
ODD_DETECT#
2
200K_0402_5%
PCH_GPIO6
2
10K_0402_5%
PCH_GPIO16
2
10K_0402_5%
EC_SCI#
2
10K_0402_5%
CIR_EN#
2
100K_0402_5%
ISDBT_DET
2
10K_0402_5%
PCH_GPIO49
2
10K_0402_5%
PCH_GPIO17
2
10K_0402_5%
PCH_GPIO37
2
1
RH198
100K_0402_5%
@
PCH_GPIO27
2
1
RH199
10K_0402_5%
CIR_EN#
2 CIR@ 1
RH296
10K_0402_5%
ISDBT_DET
1
2
RH297
47K_0402_5%
H36
BMBUSY# / GPIO0
TACH1 / GPIO1INT.PH
20K
TACH2 / GPIO6INT.PH
20K
20K
EC_SCI#
EC_SCI#
E38
TACH3 / GPIO7INT.PH
<35>
EC_SMI#
EC_SMI#
C10
GPIO8INT.PH
TACH4 / GPIO68
C40
TACH5 / GPIO69
B41
TACH6 / GPIO70
C41
TACH7 / GPIO71
A40
C4
LAN_PHY_PWR_CTRL / GPIO12
EC_LID_OUT#
G2
INT.PD
GPIO15
U2
D40
INT.PH 20K
20K
A20GATE
PECI
SATA4GP / GPIO16
<27>
BT_ON#
T81 PAD
<25> ODD_DETECT#
GPIO24
INT.PH
GPIO27
20K
P8
INT.PH
GPIO28
20K
20K
BT_ON#
K1
STP_PCI# / GPIO34
PCH_GPIO35
K4
GPIO35
ODD_DETECT#
V8
INT.PD
SATA2GP / GPIO36
M5
INT.PD
SATA3GP / GPIO37
OPTIMUS_EN#
N2
SLOAD / GPIO38
CIR_EN#
M3
SDATAOUT0 / GPIO39
V13
ISDBT_DET
3D_DET#
D
P4
GATEA20
GATEA20 <35>
AU16
P5
KB_RST#
PROCPWRGD
AY11
H_PWRGOOD
THRMTRIP#
AY10
PCH_THRMTRIP# 1
RH191
INT.PH 20K
INIT3_3V#
T14
INT.PD 20K
DF_TVS
AY1
TS_VSS1
AH8
TS_VSS2
AK11
TS_VSS3
AH10
TS_VSS4
AK10
20K
20K
NC_1
P37
SDATAOUT1 / GPIO48
VSS_NCTF_15
BG2
PCH_GPIO49
V3
SATA5GP / GPIO49 / TEMP_ALERT#
VSS_NCTF_16
BG48
HDD2_DET#
D6
GPIO57
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
KB_RST#
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
A4
VSS_NCTF_1
VSS_NCTF_19
BJ4
A44
VSS_NCTF_2
VSS_NCTF_20
BJ44
A45
VSS_NCTF_3
VSS_NCTF_21
BJ45
A46
VSS_NCTF_4
VSS_NCTF_22
BJ46
A5
VSS_NCTF_5
VSS_NCTF_23
BJ5
A6
VSS_NCTF_6
VSS_NCTF_24
BJ6
B3
VSS_NCTF_7
VSS_NCTF_25
C2
B47
VSS_NCTF_8
VSS_NCTF_26
C48
BD1
VSS_NCTF_9
VSS_NCTF_27
D1
BD49
VSS_NCTF_10
VSS_NCTF_28
D49
BE1
VSS_NCTF_11
VSS_NCTF_29
E1
BE49
VSS_NCTF_12
VSS_NCTF_30
E49
BF1
VSS_NCTF_13
VSS_NCTF_31
F1
BF49
VSS_NCTF_14
VSS_NCTF_32
F49
KB_RST# <35>
H_PWRGOOD <5>
NV_CLE
2
390_0402_5%
H_THERMTRIP# <5>
This signal has weak internal

pull-up, can't be pulled low
RH203
10K_0402_5%
OPTHD@
+3VS
OPTFHD@
1
2
RH203
10K_0402_5%
3D@
1
2
RH304
10K_0402_5%
3D_DET#
@
PCH_THRMTRIP# 2
CH30
1
1000P_0402_50V7K
12/20 for ESD request
DMI & FDI Termination Voltage

NV_CLE
Set to VCC when HIGH

B
Set to VSS when LOW

+1.8VS
E8
E16
3D_DET#
3D_DET#
SCLOCK / GPIO22
PCH_GPIO28
Follow Compal ORB

and Intel Check list 460603 V1.5
On-Die PLL Voltage Regulator

H: Enable
L: Disable
T5
PCH_GPIO27
PCH_GPIO37
<27> ISDBT_DET
INT.PH
TACH0 / GPIO17
CPU/MISC
BT_DET#
GATEA20
INT.PH 20K
INT.PD 350
PCH_GPIO17
ODD_EN# <38>
1
RH288
1
RH182
1
RH184
20K
PCH_GPIO12
PCH_GPIO16
ODD_EN#
INT.PH 20K
RCIN#
GPIO28
A42
<35>
BT_ON#
T7
PCH_GPIO1
<35> EC_LID_OUT#
1
RH180
1
RH292
1
RH190
1
RH185
1
RH193
1
RH178
1
RH197
1
RH179
1
RH293
1
RH194
1
RH181
1
RH195
1
RH186
HDMI_HPD
EC_SMI#
GPIO
1
1K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
+3VS
+3VS
ODD_EN#
INT.PH 20K
NCTF
2
RH204
1
RH205
1
RH289
1
RH202
1
RH207
UH1F
+3VALW_PCH
2 1K_0402_5% PCH_GPIO28
SKU
Non3D
3D
RH187
2.2K_0402_5%
RH206
HM76R3@
GPIO8
OPTIMUS_EN#
Integrated Clock Chip Enable (Removed)

H: Disable
L: Enable
OPTIMUS_EN#
HDD2_DET#
SKU
NonOPT
Optimus
SKU
ONE HDD
TWO HDD
RH298 1
NV_CLE
2 1K_0402_5%
EC_SMI#
2
RH189
1
1K_0402_5%
H_SNB_IVB# <5>
HDD2_DET#
Integrated clock enable functionality

is achieved by soft-strap
The current default is clock enable
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Custom
Rev
B
4019HF
Date:
Sheet
1
21
of
51
POWER
UH1G
+1.05VS_VCCP
2
1U_0402_6.3V6K
2
1U_0402_6.3V6K
+1.05VS_PCH
AN19
This pin can be left as NC if

On-Die VR is enabled (Default)
PAD
+1.05VS_PCH
AN16
VCCIO[15]
1U_0402_6.3V6K
CH43
10U_0603_6.3V6M
CH45
CH46
CH47
1U_0402_6.3V6K
CH44
1U_0402_6.3V6K
2
U47
CH35
0.01U_0402_25V7K
VCCIO[16]
VCCIO[17]
VCCIO[18]
AN27
VCCIO[19] 3709mA
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
BH29
1
VCCALVDS
AK36
VSSALVDS
AK37
VCCTX_LVDS[1]
AM37
VCCTX_LVDS[2]
AM38
VCCTX_LVDS[3]
AP36
+VCCA_LVDS
+VCCAFDI_VRM

PAD
VCC3_3[6]
+1.8VS
+VCCTX_LVDS
+VCCP_VCCDMI
S0 Iccmax
Current (A)
1.05
0.001
V5REF
0.001
V5REF_Sus
0.001
Vcc3_3
3.3
0.228
VccADAC
3.3
0.063
VccADPLLA
1.05
0.08
VccADPLLB
1.05
0.08
VccCore
1.05
1.7
VccDMI
1.1
0.047
VccIO
1.05
3.711
VccASW
1.05
0.903
VccSPI
3.3
0.01
VccDSW
3.3
0.001
VccDFTERM
1.8
0.002
VccRTC
3.3
N/A
VccSus3_3
3.3
0.095
CH40
22U_0805_6.3V6M
V33
VCC3_3[7]
V34
CH42
0.1U_0402_10V7K
VCCVRM[3]
AT16
+1.5VS
RH221
0_0603_5%
1
2
+VCCAFDI_VRM
AT20
+1.05VS_PCH
75mA
VCCCLKDMI
RH214
2
1
0_0805_5%
AB36 +1.05VS_VCC_DMI
1
RH213 +1.05VS_VCCP
0_0603_5%
1
2
+VCCP_VCCDMI
2
VCCIO[26]
VCCDFTERM[1]
VCC3_3[3]
VccAFDIPLL
AP17
CH39
CH48
1U_0402_6.3V6K
CH49
1U_0402_6.3V6K
VCCIO[25]
VCCVRM[2]
AU20
LH2
2
1
BLM18PG181SN1D_0603
0.01U_0402_25V7K
CH38
AP370.01U_0402_25V7K
VCCDMI[1]
BG6
+1.05VS_PCH
Voltage
2
0_0603_5%
+VCCP_VCCDMI
AP16
T83
1
RH208
+VCCAFDI_VRM
CH50
0.1U_0402_10V7K
Voltage Rail
V_PROC_IO
1mA
1U_0402_6.3V6K
+3VS
PCH Power Rail Table

Refer to PCH EDS R1.0
+3VS
VCCIO[20]
AP23
AN34
LH1
2+VCCA_DAC_R2
1
1_0603_1%
BLM18PG181SN1D_0603
1
CH37
10U_0603_6.3V6M
1
+3VS
AN26
AN33
0.1U_0402_10V7K
1
CH36
+VCCA_DAC
60mA
AN21
AP21
VSSADAC
VCCTX_LVDS[4]
VCCAPLLEXP
AN17
VCCADAC
U48
VCCIO[28]
BJ22
T82
1mA
CRT
CH34
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
LVDS
CH31
10U_0603_6.3V6M
+3VS
HVCMOS
DMI
CH33
DFT / SPI
VCC CORE
JUMP_43X118
1
CH32
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
RH299
1300mA
+1.05VS_PCH
1U_0402_6.3V6K
VCCIO
VCCIO[27]
FDI
PJ4
VCCDMI[2]
HM76R3@
VCCDFTERM[2]
AG17
1
190mA
VCCDFTERM[3]
+1.8VS
AG16
AJ16
2
VCCDFTERM[4]
VCCSPI
3.3
0.01
VccVRM
1.5
0.167
VccCLKDMI
1.05
0.07
VccSSC
1.05
0.095
VccDIFFCLKN
1.05
0.055
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.04
AJ17
+3VS
20mA
VccSusHDA
CH51
0.1U_0402_10V7K
V1
1
CH53
1U_0402_6.3V6K
+3VALW to +3V_PCH
Vgs=-4.5V,Id=3A,Rds<97mohm
+3VALW
+3VALW_PCH
PJ2
2
@
1
JUMP_43X79
QH2
AO3413_SOT23
D
1
@
2
1
@
2
RH1
20K_0402_5%~D
PCH_PWR_EN# 2
1
47K_0402_5%
CH98
0.1U_0402_10V7K~D
<23,28,38> PCH_PWR_EN#
CH102
0.01U_0402_25V7K
RH3
A
CH97
0.1U_0402_25V6
CH99
0.1U_0402_10V7K~D
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HF
Date:
Sheet

1
22
of
51
+3VS
+5VALW
LH5

QH6
+3VS_VCC_CLKF33
T38
VCC3_3[5]
CH65
1U_0402_6.3V6K
1
1
1
CH67
CH68
CH69
1U_0402_6.3V6K
LH7
1
BLM18PG181SN1D_2P
+1.05VS_VCCADPLLA
2
LH8
1
1U_0402_6.3V6K
2
VCCASW[3]
AA26
VCCASW[4]
AA31
VCCASW[7]
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
VCCASW[12]
AD31
VCCASW[13]
W21
VCCASW[14]
W23
VCCASW[15]
2 CH96
1U_0402_6.3V6K
RH244
+VCCDIFFCLK
0_0603_5%
+VCCRTCEXT
CH79
1U_0402_6.3V6K
CH78
0.1U_0402_10V7K
VCCASW[11]
AD29
+1.05VS_PCH
2
VCCASW[6]
AC26
2
2 CH94
1U_0402_6.3V6K
VCCASW[5]
W24
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W31
VCCASW[19]
W33
VCCASW[20]
N16
1
+VCCAFDI_VRM
Y49
T29
T24
VCCSUS3_3[9]
V23
VCCSUS3_3[10]
V24
VCCSUS3_3[6]
P24
VCCIO[34]
T26
V5REF_SUS
M26
+PCH_V5REF_SUS
DCPSUS[4]
AN23
+VCCA_USBSUS
VCCSUS3_3[1]
AN24
1mA
+5VALW_PCH
CH62 1
N20
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
VCCSUS3_3[5]
RH232
10_0402_5%
2 1U_0402_6.3V6K
DH3
P22
AA16
VCC3_3[8]
W16
VCC3_3[4]
T34
2
0.1U_0402_10V7K
2
+PCH_V5REF_RUN
CH70
1U_0402_6.3V6K
+3VS
AH13
VCCIO[13]
AH14
VCCIO[6]
AF14
+5VS
+3VS
RH237
10_0402_5%
CH63 & CH71 are

different by Intel CRB.
DH4
CH72
0.1U_0402_10V7K
+PCH_V5REF_RUN
VCCVRM[4]
+3VS
CH71
1U_0603_10V6K
+3VS
+1.05VS_SATA3
VCCIO[12]
DCPRTC
0.1U_0402_10V7K
AJ2
AF13
CH63
+3VALW_PCH
1
2
CH75
0.1U_0402_10V7K
VCCIO[5]
+PCH_V5REF_SUS
+3VALW_PCH
VCC3_3[1]
VCC3_3[2]
+3VALW_PCH
VCCSUS3_3[2]
Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB
CH61
0.1U_0402_10V7K
+1.05VS_PCH
1
CH66
P34
+3VALW_PCH
CH60
0.1U_0402_10V7K
1mA V5REF
+3VALW_PCH
VCCSUS3_3[7]
1010mA
RH330
2
1
47K_0402_5%
<22,28,38> PCH_PWR_EN#
119mA VCCSUS3_3[8]
USB
AA24
AC31
BLM18PG181SN1D_2P
+1.05VS_VCCADPLLB
2
CH93
CH95
1 10U_0603_6.3V6M
1 10U_0603_6.3V6M
1
1
2
VCCASW[2]
AA29
+1.05VS_PCH
VCCASW[1]
AA21
AA27
22U_0805_6.3V6M
2
2
22U_0805_6.3V6M
DCPSUS[3]
VCCIO[33]
1
@
VCCIO[14]
AA19
T27
T23
PCI/GPIO/LPC
CH64
VCCAPLLDMI2
AL29
Clock and Miscellaneous
+1.05VS_PCH
BH23
AL24
CH54
1U_0402_6.3V6K
@
VCCIO[32]
CH56
1U_0402_6.3V6K
DCPSUSBYP
+VCCSUS
1
VCCIO[31]
P28
1
1
V12
PAD T85
P26
+PCH_VCCDSW
+1.05VS_PCH
N26
VCCIO[30]
3mA
VCCDSW3_3
0.1U_0402_10V7K

VCCIO[29]
VCCACLK
AD49
T16
2
@
CH58
2
1
"@" Avoid leakage
T84
CH55
0.1U_0402_10V7K
1
D
AO3413_SOT23
1
PAD
RH228
20K_0402_5%~D
+1.05VS_PCH
CH59
0.1U_0402_10V7K~D
POWER
UH1J
+3VALW_PCH
CH74
1U_0402_6.3V6K
CH73
10U_0603_6.3V6M
CH80
0.1U_0402_10V7K~D
1
2
10UH_LB2012T100MR_20%
+5VALW_PCH
JUMP_43X39
@ PJ5
2
+3VS_VCC_CLKF33
1
+1.05VS_PCH
RH242
CH76
0.1U_0402_10V7K
2
1
+1.05VS_SATA3
0_0805_5%
CH77
1U_0402_6.3V6K
+1.05VS_VCCADPLLA
BD47
VCCADPLLA
+1.05VS_VCCADPLLB
BF47
VCCADPLLB
+VCCDIFFCLK
AF17
AF33
AF34
AG34
55mA
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
AG33
VCCSSC
RH247
+1.05VS_VCCDIFFCLKN
1
1
0_0603_5%
CH81
1U_0402_6.3V6K
2
+1.05VS_VCCDIFFCLKN
+1.05VS_PCH
CH84
1U_0402_6.3V6K
1
1
+VCCSST
V16
DCPSST
0.1U_0402_10V7K
+1.05VM_VCCSUS
CH85
T17
V19
DCPSUS[1]
DCPSUS[2]
80mA
80mA
+1.05VM_VCCSUS
0_0603_5%
CH83
1U_0402_6.3V6K
@
0_0603_5%
CH86
4.7U_0603_6.3V6K
CH87
CH88
1mA
+V_CPU_IO
0.1U_0402_10V7K
BJ8
V_PROC_IO
+RTCVCC
+VCCAFDI_VRM
VCCVRM[1]
AF11
+VCCAFDI_VRM
VCCIO[2]
AC16
+1.05VS_VCC_SATA
VCCIO[3]
AC17
VCCIO[4]
AD17

+1.05VS_VCC_SATA
+1.05VS_PCH
RH246
2
1
0_0805_5%
CH82
1U_0402_6.3V6K
T21
+VCCME_22
RH3002
1 0_0402_5%
VCCASW[23]
V21
+VCCME_23
RH3012
1 0_0402_5%
VCCASW[21]
T19
+VCCME_21
RH3022
1 0_0402_5%
VCCASW[22]
CPU
RH303 @
2
1
RH249
2
T86 PAD
+1.05VS_PCH
+3VALW_PCH
0.1U_0402_10V7K
0.1U_0402_10V7K
2
CH89
1U_0402_6.3V6K
2
CH90
A22
VCCRTC
RTC
AK1
+1.05VS_VCCP
+1.05VS_PCH
VCCAPLLSATA
95mA
HDA
MISC
+1.05VS_VCCDIFFCLKN
SATA
2
+1.05VS_PCH
10mA
VCCSUSHDA
P32
1
HM76R3@
0.1U_0402_10V7K
CH91
CH92
0.1U_0402_10V7K
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HF
Date:
Sheet

1
23
of
51
UH1I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
UH1H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
HM76R3@
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
HM76R3@
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Rev
B
4019HF
Date:
Sheet

1
24
of
51
SATA HDD
Conn.
+5VS
C356
10U_0805_10V4Z
C357
0.1U_0402_10V7K
C358
0.1U_0402_10V7K
JODD
C359
0.1U_0402_10V7K
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
Close to JHDD
JHDD
1
2
3
4
5
6
7
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
C369 1
C367 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
C368 1
C370 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
GND
1
C379
@
10U_0805_10V4Z 1U_0402_6.3V6K
2
2
C354
1
C380
0.1U_0402_10V7K
C360
2
0.1U_0402_10V7K
1
1000P_0402_50V7K
USB_OC#1 <20,31,35>
1
C362
4.7U_0805_10V4Z
2 @
Force Dedicated charger mode

(MODE3)
Pass-Through (USB) Mode:

Connect DP/DM to TDP/TDM
Force Apple 2A Charger Mode: Apple 2A resistor dividers
R1462 0_0402_5%
U2D_DN3
1EUSB30@ 2
R1463 0_0402_5%
U2D_DP3
1EUSB30@ 2
US20_N2
US20_P2
<20> U3RXDP4_R
<20> U3TXDP4
U2D_DN3 <31>
U3TXDP4
1
C903
2U3TXDP4_C
0.1U_0402_10V7K
U2D_DP3 <31>
U2D_DN2 <31>
<20> U3TXDN4
U3TXDN4
1
C904
SLP_CHG_M4
US20_N3
US20_P3
1
1000P_0402_50V7K
C364
4.7U_0805_10V4Z
2 @
4
L56
@
U3TXDP3_C_L
+USB_VCCC
C911
C900
220U_6.3V_M_R15
9
1
8
2
7
3
6
4
5
U3TXDN3_C_L
USB20_N2_S_R
USB20_P2_S_R
U3RXDP3
C901
U3RXDN3
SSTX+
VBUS
SSTXDGND
D+
SSRX+
GND
SSRX-
GND
GND
GND
GND
1000P_0402_50V7K
R73
1
L53
3
IUSB30@
2 R1449
0_0402_5%
4
L57
1
U3RXDN4
U3RXDN4 <31>
U3TXDP4_C_L
U3TXDP4_C_L <31>
3 3
IUSB30@
2 R1451
0_0402_5%
2 R1452
0_0402_5%
KINGCORE WCM-2012HS-670T
1
4
L58
SLP_CHG_M4 <20>
C892
<20> U3RXDN3_R
<20> U3TXDP3
U3TXDP3
1
C905
2U3TXDP3_C
0.1U_0402_10V7K
U8
CEN
DM
DP
CB1
PGND
CB0
TDM
TDP
VCC
8
7
6
5
U3TXDN4_C_L
D87
U3TXDP4_C_L 1 1
USB1_GND
0_0603_5%
R1447
0_0402_5%
2
USB20_P3_S
USB20_P3_S_R
USB20_N3_S
USB20_N3_S_R
@
109
U3TXDP4_C_L
U3TXDN4_C_L 2 2
98
U3TXDN4_C_L
U3RXDP4
4 4
77
U3RXDP4
U3RXDN4
5 5
66
U3RXDN4
U3TXDN4_C_L <31>
W=80mils
U3RXDP4 <31>
WCM-2012-900T_0805
@
1
R87
3 3
R77
1
L54
2
0_0402_5%
0_0402_5%
2
USB20_P2_S
USB20_P2_S_R
USB20_N2_S
USB20_N2_S_R
YSCLAMP0524P_SLP2510P8-10-9
3 3
IUSB30@
2 R1453
0_0402_5%
2 R1454
0_0402_5%
1
4
L59
U3RXDP3 <31>
1 @
U3RXDP3
U3RXDN3
D88
U3TXDP3_C_L 1 1
109
U3TXDP3_C_L
98
U3TXDN3_C_L
U3RXDP3
4 4
77
U3RXDP3
U3RXDN3
5 5
66
U3RXDN3
U3RXDN3 <31>
U3TXDP3_C_L
U3TXDN3_C_L 2 2
D85
USB20_P3_S_R
SLP_CHG_M4
US20_N2
US20_P2
<20> U3TXDN3
+5VALW
1
C893
MAX14600ETA+T_TDFN-EP8_2X2
0.1U_0402_10V7K
14600@
2
U3TXDN3
1
C906
2U3TXDN3_C
0.1U_0402_10V7K
U3TXDP3_C_L <31>
@D86
@
D86
2 2
USB20_N2_S_R 3
U3TXDN3_C_L
Compal Secret Data

2011/12/14
1
3
AZC199-02SPR7G_SOT23-3
U3TXDN3_C_L <31>
2012/12/31
Deciphered Date
Title
Date:
Size
MAX14617ETA+T
2
0_0402_5%
Issued Date
USB20_N3_S_R 2
3 3
3 3
IUSB30@
2 R1455
0_0402_5%
1
R88
USB20_P2_S_R
1
2
3
4
9
10
11
12
13
OCTEK_USB-09EAEB
0_0603_5%
@
2 R1450
0_0402_5%
1
U3RXDP4
JUSBRF
1 @
0_0402_5%
2 14617@ 1
R1471
SLP_CHG_CB2A
USB20_N2_S
USB20_P2_S
SLP_CHG_M3
USB0_GND
0_0603_5%
R1445
R1444
0.1U_0402_10V7K
For EMI
USB_OC#1
1 @
2U3TXDN4_C
0.1U_0402_10V7K
<20> U3RXDP3_R
+5VALW
W=80mils
WCM-2012-900T_0805
MAX14600ETA+T_TDFN-EP8_2X2
0.1U_0402_10V7K
14600@
2
14617@
2
C363
10
11
12
13
1000P_0402_50V7K
USB20_P2 <20>
U2D_DP2 <31>
8
7
6
5
<20> U3RXDN4_R
USB20_P3 <20>
R1464 0_0402_5%
U2D_DN2
1EUSB30@ 2
R1465 0_0402_5%
U2D_DP2
1EUSB30@ 2
CB0
TDM
TDP
VCC
6
7
8
5
OUT
OUT
OUT
OCB
2 R1448
0_0402_5%
USB20_N3 <20>
USB20_N2 <20>
CEN
DM
DP
CB1
PGND
IN
IN
EN/ENB
GND
R1460 0_0402_5% IUSB30@

USB20_N2
1
2
R1461 0_0402_5% IUSB30@
USB20_P2
1
2
1
2
3
4
9
2
3
4
1
GND
GND
GND
GND
OCTEK_USB-09EAEB
0_0603_5%
@
1 @
U5
SLP_CHG_CB2
USB20_N3_S
USB20_P3_S
SLP_CHG_M3
220U_6.3V_M_R15
U3RXDN4
C365
@
C899
R1446
R1458 0_0402_5% IUSB30@

USB20_N3
1
2
R1459 0_0402_5% IUSB30@
USB20_P3
1
2
C898
W=80mils
+USB_VCCC
SA00004KB00
SA00003TV00
US20_P3
W=80mils
2.5A
SY6288DCAC_MSOP8
Pass-Through (USB) Mode with CDP Emulation:

Auto Connect DP/DM to TDP/TDM depending on CDP status
US20_N3
C897
0.1U_0402_10V7K
USB20_P3_S_R
U3RXDP4
4.7U_0805_10V4Z
C902
2
C361
0.1U_0402_10V7K
USB_CHG_EN#
AUTO MODE
0.1U_0402_10V7K
For EMI
1
6
7
8
5
OUT
OUT
OUT
OCB
+USB_VCCA
IN
IN
EN/ENB
GND
2
3
4
1
SSTX+
VBUS
SSTXDGND
D+
SSRX+
GND
SSRX-
2.5A
9
1
8
2
7
3
6
4
5
U3TXDN4_C_L
USB20_N3_S_R
+USB_VCCC
STATUS
C894
CB2
(14617 only)
14617@
+USB_VCCA
W=80mils
W=80mils
U15
U8
10U_0805_10V4Z
JUSBRR
U14
MAX14617ETA+T
C355
+5VALW
+5VALW
U3TXDP4_C_L
SY6288DCAC_MSOP8
Place components closely ODD CONN.
1.1A
1
+USB_VCCA
<31,35> USB_CHG_EN#
CB1
SLP_CHG_M3
+5VS_ODD
ODD_DA# <20>
USB Right-Side
MAX14600 & MAX14617
U5
ODD_DETECT# <21>
+5VS_ODD
ODD_DA#
+5VS
USB Sleep & Charge Auto-Mode/Mode3
<20> SLP_CHG_M3
D
SA00004KB00
SA00003TV00
1 14617@ 2
R1470
0_0402_5%
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
+3VS
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
C378 1
C375 1
SANTA_204901-1
@
SANTA_190501-1
@
CB0
SLP_CHG_M4
C376 1
C377 1
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
15
14
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
GND
A+
AGND
BB+
GND
GND
GND
SATA ODD Conn
23
24
Place closely JHDD SATA CONN.
1.2A
1
Document Number
Rev
B
4019HF
Sheet

1
25
of
51
Screw cap for ESD request
B-CAS Circuit
+5VS
+5VALW
2
3
2
1
2N7002DW-T/R7_SOT363-6
BCPWON
QS1
AO3413_SOT23
BCAS@
+5VS_BCAS
BCAS@
CS2
2
0.01U_0402_25V7K
BCAS@ RS7
10K_0402_5%
RS8
2.2K_0402_5%
BCAS@
1
CS4
BCAS@
0.1U_0402_10V7K
2
+5VS_L_BCAS
current = 0A
CS3 BCAS@
4.7U_0603_6.3V6K
+5VS_L_BCAS
LS1 BCAS@
1
2
1 FBMA-L11-201209-221LMA30T_0805
CS5
BCAS@
1U_0402_6.3V6K
2
BCPWON
<27>
QS2B
BCAS@
RS5
2
1
47K_0402_5%
BCAS@
100K_0402_5%
Inrush
1 BCAS@
CS1
0.1U_0402_10V7K
BCAS@ RS2
+5VS_L_BCAS
BCRSTM
IN2
US1 BCAS@
Finger printer
IN1
<27>
1
BCRSTM 2
B_R_BCRST 1 BCAS@ 2
B_BCRST
RS9
100_0402_5%
B_BCRST
<27>
@
JFP
O
IN2
+3VS
B_R_XBCCLK1 BCAS@ 2
B_XBCCLK
RS11
100_0402_5%
B_XBCCLK <27>
USB20_N8
USB20_P8
D82
<20>
<20>
+3VS_FP
USB20_N8
USB20_P8
FP_GND
XBCLKM
IN1
1 R134
2
0_0603_5% 1
FP@
C480
0.1U_0402_10V7K
FP@
2
<27>
CPLGP1
CPLGP1
BCIO
BCIO
<27>
1
2
RS14
BCAS@
1.5K_0402_5%
QS2A
BCAS@
2
2N7002DW-T/R7_SOT363-6
2
1
2
RS13 BCAS@ B
10K_0402_5%
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:
JOINT_F1017WR-S-04P
10K_0402_5%
1
2
RS12
BCAS@
10K_0402_5%
QS4 BCAS@
2SB1197K_SOT23-3
+5VS_L_BCAS
BCAS@
2
4
3
2
1
For ESD
+5VS_L_BCAS
RS1
1
GND
GND
4
3
2
1
R133
0_0603_5%
FP@
@
6
5
<27>
1
XBCLKM
US2 BCAS@
Document Number
Rev
B
4019HF
Sheet
1
26
of
51
5
1
<5,9,38,43> SUSP
CM9
<35> TMPTU2_SXP
BT_CTRL
+3V_WLAN
E51_RXD_R
For isolate Intel Rainbow Peak and

Compal Debug Card.
GNDGND
54
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
53
GNDGND
54
Add BCCDET pull down

1 BCAS@ 2
RM23
470_0402_5%
LED_WIMAX#
ACES_51711-0520W-001
@
LED_WIMAX#
CPLGP1
CM13
0.1U_0402_10V7K
3G@
WiMax
DM1
RLZ20A_LL34
3G@
LED_WIMAX# <37>
1
CM15
10P_0402_50V8J
3G@ 2
+3VS
1
2
USB--3G/TV#1
COMMON
BCIO
1 BCAS@ 2
RM7
0_0402_5%
+UIM_PWR
2
0.1U_0402_25V4Z
1
2
3
VCC
RST
CLK
1
10K_0402_5%
NC
4
5
6
NC
UIM_VPP
SIM_DATA
MOLEX_47273-0001~D
CM16
10P_0402_50V8J
2 3G@
+3VL
CLK_X2
CLK_X1
0.1U_0402_10V7K
+3VL
0.1U_0402_10V7K
+1.05VS_VCCP
CCL3
GCLK@
VDD
+V3.3A
CLKREQ_TV# <17>
XTAL_OUT
XTAL_IN
4
7
13
17
VSS
VSS
VSS
Thermal Pad
25M_B
25M_A
10
11
RCL6
9
12
5
6
VDD_RTC_OUT
+RTCBATT
2
+3VS_280
0_0402_5%
PCH_RTCX1_R
PCH_RTCX1_R <16>
OSC_IN_R_R
PCH_X1_R_R
LAN_X1_R_R
CCL6
2.2U_0603_6.3V6K
GCLK@
3
GND
CCL5
18P_0402_50V8J
GCLK@
2
G
S
271@
2N7002_SOT23-3
QCL2
LAN_X1_R_R
1 @
RCL5
2
2
271@
CCL8
0.01U_0402_25V7K
271@
AO3413_SOT23
QCL1
CCL9 0.1U_0402_10V7K
2
1
271@
+3VS_280
CCL4
18P_0402_50V8J
GCLK@
SIM_CLK
1 3G@
RM11
1 BCAS@
RM12
2
0_0402_5%
2
0_0402_5%
SIM_DATA
PCIE_PRX_C_TVTX_P6
PCIE_PRX_C_TVTX_N6
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1
PCIE_PRX_C_TVTX_P6 <17>
PCIE_PRX_C_TVTX_N6 <17>
TV@ 2 0_0402_5%
2 0_0402_5%
TV@
PCIE_PTX_C_TVRX_N6
PCIE_PTX_C_TVRX_P6
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
PCIE_PTX_C_TVRX_N6 <17>
PCIE_PTX_C_TVRX_P6 <17>
LAN_X1_R <28>
OSC_IN_R
<33>
CCL12
4.7P_0402_50V8C
@
EMI request 12/17

271@
CCL7
0.1U_0402_10V7K
1
<33> HWEQ_EN
HWEQ_EN
GND
CLK_X2
RCL7
271@ 2
1
47K_0402_5%
GCLK@
25MHZ 12PF X3G025000DK1H-X
+3VALW
RCL4
10K_0402_5%
271@
2
0_0402_5%
2 SIM_CLK
0_0402_5%
CCL10
5P_0402_50V8C
GCLK@
OSC_IN_R_R
1 GCLK@ 2 OSC_IN_R
RCL3
33_0402_5%
1
2
CCL2
GCLK@
SIM_RESET
1 3G@
RM9
1 BCAS@
RM10
EMI request 11/06
TV@ 2 0_0402_5%
2 0_0402_5%
TV@
2
0_0402_5%
2
0_0402_5%
PCH_X1_R <17>
LAN_X1_R_R
1 GCLK@ 2 LAN_X1_R
RCL2
33_0402_5%
1
0.1U_0402_10V7K
0.1U_0402_10V7K
CCL13
GCLK@
BCIO
1 3G@
RM5
1 BCAS@
RM8
+RTCVCC
B_XBCCLK
+VCC_SIM
SA000058Z00
+3VALW
<26>
2
1 271@
14
SLG3NB271VTR_TQFN16_2X3
CCL1
GCLK@
PCH_X1_R_R
1 GCLK@ 2 PCH_X1_R
RCL1
0_0402_5%
CCL11
22U_0805_6.3V6M
GCLK@
32K
NC
B_XBCCLK
UIM_DATA
MSATA@
CM23 1
CM24 1
MSATA@
SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1
+3V_LAN
YCL1
CLK_X1
VBAT
NC
VDDIO_25M_A
VDDIO_25M_B
1
16
GCLK@
+3VALW_GCLK
2
15
8
3
+3V_LAN
+1.05VS_VCCP
<26>
CM14
22P_0402_50V8J
@
RM33 1
RM34 1
D
+3VALW_GCLK
B_BCRST
B_BCRST
UIM_CLK
MSATA@
CM21 1
CM22 1
MSATA@
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
1
UCL1
<26>
RM2
4.7K_0402_5%
@
GND
VPP
I/O
1
2
RCL9
0_0603_5% @
+UIM_PWR
CM10
@
TV@QM2
2N7002_SOT23-3
+3VALW_PCH
1 BCAS@ 2
RM4
0_0603_5%
1 3G@
2
RM1
0_0603_5%
+5VS_BCAS
ISDBT_DET <21>
UIM_RESET
please place near J3GTV
BCIO
Close to JPCIF
2
0_0402_5%
1 MSATA@2
RM14
0_0402_5%
1
2
USB20_P10 <20>
USB20_N10 <20>
TV@
CLKREQ_Q_TV#
RCL8
0_0603_5%
1
0_0402_5%
UIM_VPP
2
RM30
0_0402_5%
TV@
PLT_RST#
CPLGP1 <26>
TMPTU1_SXP <35>
ISDBT_DET_R
1 TV@
RM13
+3VS
2
RM35
+3VALW
1 3G@
2
RM30
0_0402_5%
RM31 1
RM32 1
To avoid LED flashing
RM3
1 3G@
2 0_0402_5% PM_SMBCLK
2 0_0402_5% PM_SMBDATA
USB--TV#2
1 @
2
+3VS
RM6
100K_0402_5%
1
2
+5VS
RM28
100K_0402_5%
WIMAX@
RM29
200K_0402_5%
WIMAX@
CM20
47P_0402_50V8J
@
2
2
4.7U_0805_10V4Z
B-CAS
+VCC_SIM
SIM_RESET
SIM_CLK
PM_SMBCLK <11,12,17,37>
PM_SMBDATA <11,12,17,37>
USB20_N9 <20>
USB20_P9 <20>
USB20_N12 <20>
USB20_P12 <20>
JSIM
PLT_RST# <5,20,28,29,31,35,36>
<20>
BCAS@
1 RM21 2 0_0402_5%
1 BCAS@ 2 0_0402_5%
RM22
USB20_P10_TV
USB20_N10_TV
0.01U_0402_50V7K
1
CM12 CM11
47P_0402_50V8J @
2
@
WLAN_OFF#
PLT_RST#
RF_OFF#
2
0.01U_0402_25V7K
RM19
1 3G@
1 3G@
RM20
USB20_P10_TV
USB20_N10_TV
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
COMMON
ISDBT_DET_R
RF_OFF#
PLT_RST#_FULL
ACES_51711-0520W-001
BCCDET
CM19
@
47P_0402_50V8J
2.75A
+16VS
53
Debug card using
RM16 2
0_0603_5%
BCAS@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+16VS
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
CM18
@
RM25
10_0402_5%2
1
2
0_0402_5%
RM26
<35,36> E51_TXD
<35,36> E51_RXD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
E51_RXD_R
+3V_WLAN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
WLAN/ WiFi
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1 RM27 2
1K_0402_5%
RM15 2
0_0603_5%
BCAS@
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
CM28
47P_0402_50V8J
2
2
@
4.7U_0805_10V4Z
JWLAN
<17> PCIE_PTX_C_WLANRX_N2
<17> PCIE_PTX_C_WLANRX_P2
2N7002DW-T/R7_SOT363-6
+3VS
+1.5VS
<17> PCIE_PRX_WLANTX_N2
<17> PCIE_PRX_WLANTX_P2
SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1
CM17
@
47P_0402_50V8J
+3VS
QM1B
CM27
CM7
CM8
47P_0402_50V8J
2
2
2
@
4.7U_0805_10V4Z
0.01U_0402_25V7K
<17> CLK_WLAN#
<17> CLK_WLAN
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
For SED
CM3
BT_CTRL 10_0402_5%2BT_CTRL_R
@ RM24
<26> BCRSTM
<26> BCPWON
QM1A
BT_ON#
2N7002DW-T/R7_SOT363-6
0.1U_0402_10V7K
1
1
<35> AOAC_WAKE#
<17> CLK_TV#
<17> CLK_TV
1
<21>
+1.5VS
<17> CLKREQ_WLAN#
BT_CTRL
2
0.01U_0402_25V7K
2
0_0402_5%
CM26
47P_0402_50V8J
@
3
CM2
1
RM18
For SED
1
4WLAN_OFF#
@
For RF
CM1
0.1U_0402_10V7K
1
UM1
BT_ON#
BCCDET
CLKREQ_Q_TV#
IN2
<26> XBCLKM
IN1
40 mils
BT_CRTL
1
<35,38> AOAC_EN#
WL_OFF#
+3V_WLAN
+1.5VS
JPCIF
+3V_WLAN
+1.5VS
WL_OFF#
Disable
For SED
0.1U_0402_10V7K
1
1
1
CM4
CM5
CM6
1
RM17
8.2K_0402_5%
<35>
BT
on module
Enable
CM25
47P_0402_50V8J
@
BT
on module
47P_0402_50V8J
For RF
1
+3V_WLAN
+3V_WLAN
120 mils
+1.5VS
Slot 1 Half PCIe Mini Card-WLAN/ WiMax
+3VS
Slot 2 Full PCIe Mini Card- 3G/ TV Tuner

Half PCIe Mini Card- JET
WLAN&BT Combo module circuits
0_0402_5%
Reserved for Swing Level adjustment

( Close GCLK side )
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
Sheet
27
of
51
+3V_LAN
UL1
CL1
<17> PCIE_PRX_C_LANTX_P1
CL2
<17> PCIE_PRX_C_LANTX_N1
8105ELDO@
CLKREQ_LAN#
1
D
2 0.1U_0402_10V7K PCIE_PRX_LANTX_N1
23
HSON
PCIE_PTX_C_LANRX_P1 17
PCIE_PTX_C_LANRX_N1 18
2N7002_SOT23-3
LANCLK_REQ#
3
QL53
<5,20,27,29,31,35,36> PLT_RST#
18111FVB@ 2
RL28
0_0402_5%
<18,31> EC_SWI#
EC_SWI#
RL22 1
+3V_LAN
CLKREQB
PLT_RST#
25
PERSTB
CLK_LAN
CLK_LAN#
19
20
REFCLK_P
REFCLK_N
LAN_X1
43
CKXTAL1
LAN_X2
44
CKXTAL2
28
LANWAKEB
ISOLATE#
26
ISOLATEB
ENSWREG
1
2
RL26
0_0402_5%
8111FVB@
+LAN_VDDREG
1
2
4
5
7
8
10
11
DVDD10
DVDD10
DVDD10
13
29
41
DVDD33
DVDD33
27
39
+3V_LAN
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
+3V_LAN
33
ENSWREG
34
35
VDDREG
VDDREG
GND
PGND
WOL_EN#
2
0_0402_5%
AVDD10
AVDD10
AVDD10
AVDD10
3
6
9
45
+LAN_VDD10
REGOUT
36
RTL8105E
Sx Enable Sx Disable
Wake up
Wake up
LOW
WOL_EN#
<27>
CL17
0.1U_0402_10V7K
8111FVB@
8111FVB@
+LAN_VDDREG
8111FVB@
1
8111FVB@ LL3
2
0_0603_5%
CL28
4.7U_0603_6.3V6K
8111FVB@
RL8 GCLK@
1
2
0_0402_5%
LAN_X1_R
8111FVB@
CL29
0.1U_0402_10V7K
2 8111FVB@
HIGH
RTL8111E/F
S0
NC
Pin14
NC
Pin15
NC
10K ohm PD
Pin38
NC
1K ohm PH
+3V_LAN
EMI request 11/06 Placement near to YH2

1
YL1 25MHZ_20PF_7V25000016
1
3
GND
1
+3VALW
2
GND
2
CL26
27P_0402_50V8J
NOGCLK@
CL27
27P_0402_50V8J
NOGCLK@
ENSWREG
1
CL19
1
CL20
1
CL21
1
CL22
1
CL23
1
CL24
1
CL25
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
8105E-VL/VD 8105E-VL/VD
8111F/F-VB
PWM Mode
LDO Mode
NC
RL4
0 ohm
(Pull High)
NC
8105E-VD 10/100M
8105ELDO@
0 ohm
(Pull Down)
RL23
2
1
CL681
4.7U_0805_10V4Z
@
LAN_MDI1+
LAN_MDI1-
CL682
1U_0402_6.3V6K
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
JRJ45
RJ45_MIDI1+
RJ45_MIDI1-
SP050007K00
10/100M transformer_HD245
RJ45_MIDI3-
PR4-
RJ45_MIDI3+
PR4+
RJ45_MIDI1-
PR2-
RJ45_MIDI2-
PR3-
RJ45_MIDI2+
PR3+
RJ45_MIDI1+
PR2+
RJ45_MIDI0-
PR1-
UL4
+3V_LAN rising time (10%~90%) need > 1ms and <100ms.

WOL
LAN_EN
ISOLATEB
S0
Sx
S0
Sx
---------------------------------------------0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0*
1
2
3
TCT1
TD1+
TD1-
MCT1
MX1+
MX1-
24
23
22
LAN_MDI2LAN_MDI2+
4
5
6
TCT2
TD2+
TD2-
MCT2
MX2+
MX2-
21
20
19
LAN_MDI1LAN_MDI1+
7
8
9
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
18
17
16
LAN_MDI0LAN_MDI0+
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
LAN_MDI3LAN_MDI3+
CL39 1000P_0402_50V7K 8111FVB@

2
1
1
2
RL11
75_0402_1%
8111FVB@
CL40 1000P_0402_50V7K 8111FVB@
2
1
1
2
RL12
75_0402_1%
8111FVB@
CL41 1000P_0402_50V7K
2
1
1
2
RL13
75_0402_1%
CL42 1000P_0402_50V7K
2
1
1
2
RL15
75_0402_1%
*
S3: after SUSP# assert low over 100ms
S4/S5: after SYSON assert low over 100ms
CL34
0.1U_0402_25V6
RJ45_MIDI3RJ45_MIDI3+
RJ45_MIDI0+
DL1
GND
GND
14
13
LED_GREEN_B2
12
LED_GREEN_B1
11
LED_YELLOW_A2
10
LED_YELLOW_A1
DL2
@
For ESD
PR1+
@
SANTA_130451-F
1
CL36
2
1000P_1808_3KV7K
SUPERWORLD_SWG150401
8111FVB@
LANGND
1
CL37
CAP NP
CL38
@
4.7U_0603_6.3V6K
Place CL34 colse

to LAN chip
Compal Secret Data
Issued Date
2011/12/14
2012/12/31
Deciphered Date
Title

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Rev
B
4019HF
Date:
RJ45_GND
SP050007400
For ESD
LAN Conn.
RJ45_MIDI0+
RJ45_MIDI0-
TD+
TDCT
NC
NC
CT
RD+
RD-
1
2
3
4
5
6
7
8
UL3 8105ELDO@
LAN_MDI0+
LAN_MDI0-
@
CL482
0.01U_0402_25V7K
PJ29
JUMP_43X79
@
+3V_LAN
AO3413_SOT23
3
@ QL51
2
LAN
0.1U_0402_10V7K
RL23
0_0402_5%
8105ELDO@
CL483
@
0.1U_0402_10V7K
@ RL432
1
47K_0402_5%
@
1
2
RL435
0_0402_5%
RL147
100K_0402_5%
@
@
1
2
RL434
0_0402_5%
0.1U_0402_10V7K
+3VALW
RL4
0_0402_5%
8111FVB@
LAN_X2
0.1U_0402_10V7K
UL1
HIGH
NOGCLK@
0.1U_0402_10V7K
For P/N and footprint

Please place them to ISPD page
LAN_X2
10PF_0402_50V9
2 1
2
RL29
22_0402_5%
GCLK@
GCLK@
LAN_X1
2,23,38> PCH_PWR_EN#
60 mils
+3VALW TO +3V_LAN
CL43
1
RL7
15K_0402_5%
<35> WOL_EN#
+3V_LAN
+LAN_REGOUT
SA00004Y710
RTL8111F-CGT_QFN48_6x6
8111FVB@
Close to Pin 21
+LAN_EVDD10
0.1U_0402_10V7K
CL19, CL20,CL21 close to pin 13,29,45, respectively

CL22 close to pin 3, respectively
CL23,CL24,CL25 close to pin 6,9,41, respectively
2
0_0603_5%
CL18
1U_0402_6.3V6K
21
1
RL433
RSET
1
LL2
EVDD10
0.1U_0402_10V7K
+LAN_EVDD10
+LAN_VDD10
+LAN_VDD10
ISOLATE#
2
46
2
2.49K_0402_1%
24
49
1
RL5
1K_0402_5%
RL6
@
CL9
0.1U_0402_10V7K
2 8111FVB@
LAN_EN
Layout Note: LL1 must be

within 200mil to Pin36,
CL13
CL13,CL9 must be within 4.7U_0603_6.3V6K
200mil to LL1
8111FVB@ 2
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
1
CL3
1
CL4
1
CL5
1
CL6
1
8111FVB@ CL7
1
8111FVB@ CL8
+3VS
+LAN_VDD10
EC_SWI#
8111FVB@
RL21 2
1 10K_0402_5%
2 1K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
16
RL2 2
RL1 2
RL25 2 @
LANCLK_REQ#
30
32
8111FVB@
+LAN_REGOUT
1
2
2.2UH +-5% NLC252018T-2R2J-N
8105ELDO@
RL24 2
1 10K_0402_5%
EECS
EEDI
HSIP
HSIN
LL1
+3V_LAN
CLK_LAN
CLK_LAN#
31
37
40
+3VS
<17>
<17>
LED3/EEDO
LED1/EESK
LED0
<17> CLKREQ_LAN#
HSOP
2
G
LAN_EN
LAN_EN
22
<17>
2 0.1U_0402_10V7K PCIE_PRX_LANTX_P1
<17> PCIE_PTX_C_LANRX_P1
<17> PCIE_PTX_C_LANRX_N1
CL3 to CL6 close to Pin 27,39,47,48

CL7 to CL8 close to Pin 12,42
+LAN_VDD10
Sheet

E
28
of
51
+AV12
+3VS
20 mils
1
CW1
2.2U_0603_6.3V6K
1
CW2
0.1U_0402_16V4Z
CW3
4.7U_0603_6.3V6K
20 mils
+DV12
40 mils
CW4
0.1U_0402_16V4Z
CW5
2.2U_0603_6.3V6K
CW6
0.1U_0402_16V4Z
All of cap. close to chip
UW1
CW7
1 +DV33_18
20
1U_0402_6.3V6K
PCIE_PTX_C_CRRX_P4
PCIE_PTX_C_CRRX_N4
PCIE_PRX_C_CRTX_P4
PCIE_PRX_C_CRTX_N4
3V3_IN
DV33_18
AV12
DV12_S
+VCC_2IN1
10
Card_3V3
1
12mils,
6.2K_0402_5%
2
RW1
<17>
<17>
<17>
<17>
+AV12
+DV12
9
15
7
11
+3VS
mils
CW8 1
CW9 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
<17> CLK_CR
<17> CLK_CR#
lengths < 200mils8

PCIE_PTX_C_CRRX_P4
PCIE_PTX_C_CRRX_N4
PCIE_PRX_CRTX_P4
PCIE_PRX_CRTX_N4
1
2
5
6
HSIP
HSIN
HSOP
HSON
CLK_CR
CLK_CR#
3
4
REFCLKP
REFCLKN
<5,20,27,28,31,35,36> PLT_RST#
<17> CLKREQ_CR#
+3VS
1
RW2
23
PERST#
24
CLK_REQ#
19
2
10K_0402_5%
GND
25
SP1
SP2
SP3
SP4
SP5
SP6
12
13
14
16
17
18
RREF
SD_DATA1_R
SD_DATA0_R
SDCLK_R
SDCMD_R
SD_DATA3_R
SD_DATA2_R
RW6
RW5
RW4
RW7
RW8
RW9
1
1
1
1
1
1
2
2
2
2
2
2
SD_DATA1
SD_DATA0
SDCLK
SDCMD
SD_DATA3
SD_DATA2
0_0402_5%
0_0402_5%
33_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
colse to chip
GPIO
SD_WP
20
SDWP
SD_CD#
21
SDCD#
MS_INS#
22
CW10
5P_0402_50V8C
For EMI
RTS5229-GR_QFN24_4X4
SA00004Z900
< 2 in 1 Card Reader >

Connector on bottom side
JREAD
SD_DATA0
SD_DATA1
SD_DATA2
SD_DATA3
SDCMD
SDCLK
7
8
9
1
DAT0
DAT1
DAT2
DAT3
2
5
CMD
CLK
12
13
GND
GND
+VCC_2IN1
WP
CD
10
11
SDWP
SDCD#
VDD
+VCC_2IN1
VSS1
VSS2
3
6
40 mils
CW11
10U_0805_10V6K
CW12
0.1U_0402_16V4Z
TAITW_PSDBTD-09GLBS1N14N0
@
CW12, CW11 colse to socket VDD
Compal Secret Data
Issued Date
2011/12/14
2012/12/31
Deciphered Date
Title

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
Rev
B
4019HF
Sheet

1
29
of
51
9
8
B_INp
B_INn
U3TXDP2
U3TXDN2
IUSB30@
CR34 1
2 0.1U_0402_10V7K U3TXDP2_C
CR35 1
2 0.1U_0402_10V7K U3TXDN2_C
U3TXDP2
U3TXDN2
RR49
RR44
RR46
RR45
+3VS
908
1127
15
1
1
2
1
IUSB30@
@
2
PRUR@ 2
@
1
@
2
0_0402_5%
3.3K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
OSx = NC
OSx = 0
OSx = 0
0 dB
0 dB
0 dB
VDD
VDD
15
16
17
18
A_EQ1/SDA_CTL
A_DE0/SCL_CTL
A_EQ0/NC
A_DE1/NC
<20>
USB20_P0
USB20_P0
-3.5 dB
-2.2 dB
-4.4 dB
-6.0 dB
-5.2 dB
-6.0 dB
1(default)
DEVICE FUNCTION
Normal Operation
Sleep Mode
CM
19
20
9
8
5
7
14
24
U3RXDN1_U_C
<20>
USB20_N0
L
L
H
H
A_OUTp
A_OUTn
12
11
B_INp
B_INn
B_OUTp
B_OUTn
22
23
PD#
REXT
TEST
I2C_EN
GND
GND
GPAD
Pericom
TI
DEVICE FUNCTION
1
1 @
PCUR@
U3RXDN1_U_C_L
U3RXDP1_U_C_L
U3TXDN1_U_C_L
U3TXDP1_U_C_L
TIUR@
Parade
PRUR@
USB3.0
USB30R@
A_DE1(Pin18) A_DE0(Pin16)
L
L
H
H
L
L
H
H
4
LR2
U3TXDP1_U_C
U3RXDP2_U_C
adaptive EQ enable
Loss up to 7dB
Loss up to 14.5dB
Loss up to 11.5dB
L
H
L
H
4
LR5
1
@
U3TXDP2_U_C
2
2
2
2
IUSB30@
0.1U_0402_10V7K
0.1U_0402_10V7K
IUSB30@
IUSB30@
0.1U_0402_10V7K
0.1U_0402_10V7K
IUSB30@
U3RXDP2_R
U3RXDN2_R
U3RXDP2_R <20>
U3RXDN2_R <20>
1 @
1
4
LR6
1
2
3
4
5
6
7
8
9
USB20_N1_L
USB20_P1_L
10
21
25
U3TXDN2_U_C_L
U3TXDP2_U_C_L
<20>
USB20_P1
USB20_P1
1 @
U3RXDP1_U_C_L
<20>
U3TXDN1_U_C_L
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
10
11
12
13
GND
GND
GND
GND
W=80mils
USB3_GND
LOTES_AUSB0015-P001A
0_0603_5%
2 RR39
0_0402_5%
IUSB30@
4 4
1
0_0603_5%
RR36
USB20_P1_L
WCM-2012-900T_0805
1
2 RR38
@
0_0402_5%
USB20_N1
USB20_N1
USB20_N1_L
DR7
U3TXDN1_U_C_L 1 1
DR1
U3TXDP1_U_C_L
USB20_P0_L
USB20_N0_L
2
1
2 RR43
0_0402_5%
109
U3TXDN1_U_C_L
98
U3TXDP1_U_C_L
U3RXDN1_U_C_L 4 4
77
U3RXDN1_U_C_L
U3RXDP1_U_C_L 5 5
6 6 U3RXDP1_U_C_L
3 3
8
Change ESD Diode for EMI request
DR8
U3TXDP2_U_C_L 1 1
U3RXDN2_U_C_L
DR4
U3TXDP2_U_C_L
3 3
IUSB30@
2 RR41
0_0402_5%
U3TXDP1_U_C_L 2 2
U3RXDP2_U_C_L
USB20_P1_L
USB20_N1_L
2
1
@
109
U3TXDP2_U_C_L
U3TXDN2_U_C_L 2 2
98
U3TXDN2_U_C_L
U3RXDP2_U_C_L 4 4
77
U3RXDP2_U_C_L
U3RXDN2_U_C_L 5 5
6 6 U3RXDN2_U_C_L
3 3
8
U3TXDN2_U_C_L
Change ESD Diode for EMI request
Compal Secret Data
Issued Date
2011/12/14
Deciphered Date
2012/12/31
Title

Custom
3
0_0603_5%
RR24
U3RXDN1_U_C_L
3 3
IUSB30@
2 RR40
0_0402_5%
USB2_GND
LOTES_AUSB0015-P001A
0_0603_5%
JUSBLF
+USB_VCCB
U3TXDP2_U_C
U3TXDN2_U_C
U3TXDN2_U_C
3.5dB
No de-emphasis
7dB
5dB with boost
output swing
L
H
L
H
W=80mils
3 3
IUSB30@
2 RR22
0_0402_5%
1 @
2 RR42
0_0402_5%
1
10
11
12
13
GND
GND
GND
GND
RR23
CR31
U3RXDP2_R_R
1
U3RXDN2_R_R
1
CR30
CR32
U3TXDP2_U
1
U3TXDN2_U
1
CR33
Date:
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
@
LR4
3 3
IUSB30@
2 RR20
0_0402_5%
U3RXDN2_U_C
B_DE1(Pin6) B_DE0(Pin3)
3.5dB
No de-emphasis
7dB
5dB with boost
output swing
L
H
L
H
USB20_N0_L
B2_EQ1
B2_DE0
B2_EQ0
B2_DE1
2 RR32
0_0402_5%
1
1000P_0402_50V7K
RR37
4
LR1
CR45
Compliance Test Mode
L
L
H
H
1
2
3
4
5
6
7
8
9
USB20_N0_L
USB20_P0_L
1 @
2 RR19
0_0402_5%
1
USB20_P0_L
2 RR26
0_0402_5%
IUSB30@
4 4
1
U3RXDN2_U_C_L
U3RXDP2_U_C_L
U3TXDN1_U_C
BOM Structure
B_EQ1(Pin4) B_EQ0(Pin2)
adaptive EQ enable
Loss up to 7dB
Loss up to 14.5dB
Loss up to 11.5dB
L
H
L
H
CR44
JUSBLR
+USB_VCCB
SN65LVPE502CPRGER_VQFN24_4X4
TIUR@
U3RXDP1_U_C
Parade suggest EQ1(Pin2) & EQ2(Pin17) to pull High use 7dB. All control has internally pulled down at ~150Kohm,
If add ESD Diode A_DE0(Pin16) and B_DE0(Pin3) need pull high to 7dB otherwise 3dB
A_EQ1(Pin15) A_EQ0(Pin17)
WCM-2012-900T_0805
1
2 RR25
@
0_0402_5%
USB20_N0
UR2
4
3
2
6
A_INp
A_INn
0(default) Normal Operation
CR41
1000P_0402_50V7K
PRUR@
REXT - swing pin(2.5K~10K) SA00004VQ00
When test RX need add RR18
CONTROL PINS SETTINGS

EN_RXD
1 @
LR3
UR2
B_EQ1/I2C_ADDR1
B_DE0/I2C_ADDR0
B_EQ0/NC
B_DE1/NC
0.1U_0402_10V7K
1
CR43
220U_6.3V_M_R15
SA00004YI00
1
13
NC(default)
PI3EQX7502IZDEX_TQFN 24P
PCUR@
DEx
CR40
OUTPUT DE CONTROL (at 2.5GHZ)
PS8710BTQFN24GTR-A1_TQFN24_4X4
EQUALIZATION
(dB)
A2_EQ1
A2_DE0
A2_EQ0
A2_DE1
U3RXDP2_U_C
U3RXDN2_U_C
<20>
<20>
NC(default)
U3RXDP1_R <20> 2
U3RXDN1_R <20>
1
2
1
2
1
2
1
2
1
2
10
21
25
IUSB30@
2 0.1U_0402_10V7K U3RXDP1_R
2 0.1U_0402_10V7K U3RXDN1_R
IUSB30@
IUSB30@
2 0.1U_0402_10V7K U3TXDP1_U_C
2 0.1U_0402_10V7K U3TXDN1_U_C
IUSB30@
CR42
0.1U_0402_10V7K
GND
GND
GPAD
CR19
1
1
CR18
CR22
1
1
CR23
CR29
U3TXDP1_U
U3TXDN1_U
0.1U_0402_10V7K
1
CR46
0.1U_0402_10V7K
22
23
UR2
OUTPUT SWING AND EQ CONTROL (at 2.5 GHZ)
B_OUTp
B_OUTn
CR36
0.1U_0402_10V7K
IUSB30@
1
2
CR37
IUSB30@
1
2 0.01U_0402_25V7K
TI: A_DE1B_DE1 need 0ohm to GND.

If use Parade and need control
A_DE1 & B_DE1 please use 4.7K
TI suggest EQ1(Pin2) & EQ2(Pin17) to pull Down use 7dB

DE1(Pin3) & DE2(Pin16) NC use 0dB
OS1(Pin4) & OS2(Pin15) NC use 1042mV
1042
U3RXDP1_R_R
U3RXDN1_R_R
4.7U_0805_10V4Z
4.7U_0805_10V4Z
CR26
0_0402_5%
RR50 TIUR@
0_0402_5%
RR53 @
0_0402_5%
RR64 TIUR@
4.7K_0402_5%
RR60 @
4.7K_0402_5%
RR54 @
4.7K_0402_5%
RR57 TIUR@
4.7K_0402_5%
RR59 @
4.7K_0402_5%
RR65 TIUR@
B2_DE0
B2_DE1
NC(default)
A_OUTp
A_OUTn
12
11
+3VS
RR50
0_0402_5%
PCUR@
EQx
B1_EQ1
B1_DE0
B1_EQ0
B1_DE1
4
3
2
6
SA000056E00
RR64
0_0402_5%
PCUR@
TRANSISTION BIT AMPLITUDE

(TYP mVpp)
PD#
REXT
TEST
I2C_EN
W=80mils
1
2
1
2
1
2
1
2
1
2
1
2
1
2
4.7K_0402_5%
A_INp
A_INn
B_EQ1/I2C_ADDR1
B_DE0/I2C_ADDR0
B_EQ0/NC
B_DE1/NC
RR57
4.7K_0402_5%
PCUR@
A2_DE0
A2_DE1
OSx
19
20
A_EQ1/SDA_CTL
A_DE0/SCL_CTL
A_EQ0/NC
A_DE1/NC
REXT - swing pin(2.5K~10K) SA00004VQ00

When test RX need add RR18
RR65
4.7K_0402_5%
PCUR@
B2_EQ0
B2_EQ1
U3RXDP1_U_C
U3RXDN1_U_C
5
7
14
24
CR39
4.7U_0805_10V4Z
2 @
+USB_VCCB
SN65LVPE502CPRGER_VQFN24_4X4
TIUR@
PS8710BTQFN24GTR-A1_TQFN24_4X4
PRUR@
RR52 @
4.7K_0402_5%
RR51 @
4.7K_0402_5%
RR61 @
4.7K_0402_5%
RR55 @
4.7K_0402_5%
RR62 @
4.7K_0402_5%
RR56 PRUR@
4.7K_0402_5%
A2_EQ0
A2_EQ1
RR63 @
4.7K_0402_5%
RR58 PRUR@
+3VS
USB_OC#0 <20,35>
1
SA00004KB00
SA00003TV00
SA00004YI00
15
16
17
18
IUSB30@
@
1
2 0_0402_5%
1 PRUR@ 2 3.3K_0402_5%
@
2
1 4.7K_0402_5%
@
1
2 4.7K_0402_5%
1
1000P_0402_50V7K
RR33
RR14
RR18
RR16
+3VS
For EMI
2
CR38
SY6288DCAC_MSOP8
VDD
VDD
A1_EQ1
A1_DE0
A1_EQ0
A1_DE1
IUSB30@
CR24 1
2 0.1U_0402_10V7K U3TXDP1_C
CR25 1
2 0.1U_0402_10V7K U3TXDN1_C
U3TXDP1
U3TXDN1
6
7
8
5
U3TXDP1
U3TXDN1
OUT
OUT
OUT
OCB
<20>
<20>
USB_EN#
<35> USB_EN#
IN
IN
EN/ENB
GND
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0_0402_5%
RR34 TIUR@
0_0402_5%
RR35 @
0_0402_5%
RR21 TIUR@
4.7K_0402_5%
RR12 @
4.7K_0402_5%
RR8
TIUR@
4.7K_0402_5%
RR7
4.7K_0402_5%
RR11 @
4.7K_0402_5%
RR29 TIUR@
TI: A_DE1B_DE1 need 0ohm to GND.

If use Parade and need control
A_DE1 & B_DE1 please use 4.7K
2
3
4
1
UR1
UR1
1
13
+USB_VCCB
UR3
RR34
0_0402_5%
PCUR@
W=60mils
2.5A
+5VALW
PI3EQX7502IZDEX_TQFN 24P
PCUR@
CR27
0.1U_0402_10V7K
IUSB30@
1
2
CR28
IUSB30@
1
2 0.01U_0402_25V7K
A1_DE0
A1_DE1
B1_DE0
B1_DE1
UR1
SA000056E00
+3VS
RR21
0_0402_5%
PCUR@
1
2
1
2
1
2
1
2
1
2
1
2
4.7K_0402_5%
RR7
4.7K_0402_5%
PCUR@
B1_EQ0
B1_EQ1
D
Note
1) keep differential trace mismatch less than +/- 5mil
2) keep USB3 impedance follow Intel SPEC
3) Power / GND pin trace 10mil
RR29
4.7K_0402_5%
PCUR@
RR28 @
4.7K_0402_5%
RR27 @
4.7K_0402_5%
RR13 @
4.7K_0402_5%
RR9
4.7K_0402_5%
RR15 @
PRUR@
4.7K_0402_5%
RR6
4.7K_0402_5%
A1_EQ0
A1_EQ1
RR17 @
4.7K_0402_5%
RR10 PRUR@
+3VS
Rev
B
4019HF

1
Sheet
30
of
51
+1.5V to +1.05V Transfer
+3V_USB
+1.5V
3
4
<17> CLK_USBA30
<17> CLK_USBA30#
EUSB30@
0.1U_0402_16V7K 2
<17> PCIE_PRX_C_USBTX_P5
0.1U_0402_16V7K 2
<17> PCIE_PRX_C_USBTX_N5
EUSB30@
EUSB30@
2
EUSB30@ CT42
CT40
0.1U_0402_16V4Z
0.1U_0402_16V7K
1
EUSB30@
QT3
1
2
2
RT13 47K_0402_5% 2
AO3413_SOT23
CT26
D
0.01U_0402_25V7K
EUSB30@
EUSB30@
1
+3V_USB
S 2N7002_SOT23-3
EUSB30@
<17> PCIE_PTX_C_USBRX_P5
<17> PCIE_PTX_C_USBRX_N5
7
8
25
AVDD33
AVDD33
39
33
30
21
42
VDD10
VDD10
VDD10
VDD10
PECLKP
PECLKN
U3TXDP2
37
TI_U3TX_C_DP3
PETXP
PETXN
U3TXDN2
U2DM2
38
45
TI_U3TX_C_DN3
U2D_DN2
PERXP
PERXN
U2DP2
U3RXDP2
44
40
U2D_DP2
TI_U3RXDP3_R
U3RXDN2
41
TI_U3RXDN3_R
PERSTB
PEWAKEB
PECREQB
OCI2B
OCI1B
UPD720202K8-701-BAA_QFN48_7X7
USBA30_SMI#_IC
46
11
1
RT65
1
RT66
1
RT67
1
RT68
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
SMIB
PPON2
PPON1
SA000051C10
SPISCK
SPICSB
SPISI
SPISO
24
23
XT1
XT2
27
IC(L)
OCL1#
17
19
18 USB30PWRON0 RT60 1
0_0402_5%
20
29
36
U2DP1
U3RXDP1
35
31
U2D_DP3
TI_U3RXDP4_R
U3RXDN1
32
TI_U3RXDN4_R
RREF
26
28
TI_U3TX_C_DP4
EUSB30@
YT2
1
2
EUSB30@EUSB30@EUSB30@EUSB30@EUSB30@
EUSB30@EUSB30@EUSB30@EUSB30@
EUSB30@
2 0.1U_0402_16V7K TI_U3TXDP3
EUSB30@
2 0.1U_0402_16V7K TI_U3TXDN3
U2D_DN2 <25>
U2D_DP2 <25>
U3TXDN1
U2DM1
U3TXDP1
15
14
16
13
CT61
1
CT87
1
CT65
1
CT71
TI_U3TX_C_DN4
1
U2D_DN3
PONRSTB
USB_CHG_EN# <25,35>
EUSB30@
2 0.1U_0402_16V7K TI_U3TXDP4
EUSB30@
2 0.1U_0402_16V7K TI_U3TXDN4
U2D_DN3 <25>
U2D_DP3 <25>
RT15 EUSB30@
2
1.6K_0402_1%
GND
CT67 0.01U_0402_25V7K
CT63 0.01U_0402_25V7K
CT62 0.01U_0402_25V7K
CT68 0.1U_0402_16V7K
EUSB30@
EUSB30@
EUSB30@
CT60 0.01U_0402_25V7K
CT66 0.01U_0402_25V7K
EUSB30@
CT70 0.1U_0402_16V7K
CT69 0.01U_0402_25V7K
EUSB30@EUSB30@EUSB30@EUSB30@EUSB30@
EUSB30@EUSB30@EUSB30@EUSB30@
47
48
10
EC_Q_SWIA#
CLKREQ_Q_USBA30#
RT14 1
2 10K_0402_5%
EUSB30@
1SS355TE-17_SOD323-2
1 1 2 2
DT2
EUSB30@
1
2
CT74
EUSB30@1U_0603_10V6K
+1.05V_USB
CT64 0.1U_0402_16V7K
CT56 0.01U_0402_25V7K
Close to U32.25
CT52 0.1U_0402_16V7K
CT57 0.01U_0402_25V7K
CT55 0.1U_0402_16V7K
CT58 10U_0603_6.3V6M
CT54 0.1U_0402_16V7K
CT51 0.1U_0402_16V7K
CT44 0.01U_0402_25V7K
CT53 0.01U_0402_25V7K
CT47 0.01U_0402_25V7K
+3VA_USB Close to U32.3
CT48 0.01U_0402_25V7K
CT50 0.01U_0402_25V7K
CT49 0.01U_0402_25V7K
4
5
49
UPD720202:
SMIB Low active
+3V_USB
1
2
<5,20,27,28,29,35,36> PLT_RST#
+3V & +1.05V has power sequence timing:

0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms
+3V_USB
CT41
1 PCIE_PRX_USBTX_P5
1 PCIE_PRX_USBTX_N5
CT81
RT12
EUSB30@ 100K_0402_5%
+3VA_USB
1
+3VALW
+3VALW
2
G
QT5
+1.05V_USB
VDD10
+3VALW to +3V Transfer
+3V_USB
UT6
EUSB30@
VDD33
Vout=0.8(1+10K/32.4K)
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05
~ 1.1025
EUSB30@
10U_0603_6.3V6M 1
VDD10
1
RT8
32.4K_0402_1%
EUSB30@
EUSB30@2
2
CT59
VDD10
GND
43
EN
34
1
2
BLM18AG601SN1D_2P
2 EUSB30@
1
RT6
10K_0402_1%
VDD33
22
VIN
VOUT
VIN
VOUT
VCNTL
POK
FB
VDD33
5
9
6
7
CT25
10U_0603_6.3V6M
+3V_USB
<18,35> PM_SLP_S4#
+3VA_USB
EUSB30@
LT9
1A
12
EUSB30@USBA30_POK
EUSB30@
APL5930KAI-TRG_SO8
1
+3V_USB
+1.05V_USB
UT3
CT43
10U_0603_6.3V6M
+3V_USB
VDD33
+1.5V
EUSB30@
1 RT5
2 USBA30_POK
4.7K_0402_5%
CLKREQ_Q_USBA30#
+3V_USB
2
EUSB30@
QT7B
2N7002KDWH_SOT363-6
EUSB30@
1
10K_0402_5%
2 RT61
1
EUSB30@
2
EUSB30@
EC_SWI# <18,28>
2
EC_Q_SWIA#
10K_0402_5%
2 RT62
1
EUSB30@
CT76
12P_0402_50V8J
+3V_USB
CT75
12P_0402_50V8J
24MHZ_12PF_X5H024000DC1H
+3V_USB
QT7A
6
CLKREQ_USBA30# <17>
2N7002KDWH_SOT363-6
EUSB30@
TI_U3RXDN3_R
+3V_USB
1 @
2 RT52
0_0402_5%
1
USBA30_SMI#_IC
+3V_USB
2N7002KDWH_SOT363-6
EUSB30@
1
OCL1#
10K_0402_5%
2 RT51
1
EUSB30@
QT6B
USBA30_SMI# <20>
2
10K_0402_5%
2 RT54
1
EUSB30@
+3V_USB
TI_U3RXDP3_R
U3RXDN3
TI_U3RXDN4_R
U3RXDN3 <25>
4
3 3
LT8 EUSB30@
1
2 RT38
@
0_0402_5%
1 @
2 RT40
0_0402_5%
1
4
U3RXDP3
TI_U3RXDP4_R
U3RXDP3 <25>
U3RXDN4
U3RXDN4 <25>
4
3 3
LT12EUSB30@
1
2 RT53
@
0_0402_5%
U3RXDP4
U3RXDP4 <25>
QT6A
6
USB_OC#1 <20,25,35>
2N7002KDWH_SOT363-6
EUSB30@
TI_U3TXDN3
1 @
LT14
1
2 RT47
0_0402_5%
EUSB30@
2
U3TXDN3_C_L <25>
TI_U3TXDN4
1 @
LT10
4 4
3 3
1
2 RT50
@
0_0402_5%
TI_U3TXDP3
U3TXDN3_C_L
U3TXDP3_C_L
U3TXDP3_C_L <25>
TI_U3TXDP4
2 RT48
0_0402_5%
EUSB30@
2
U3TXDN4_C_L
U3TXDN4_C_L <25>
4 4
3 3
1
2 RT39
@
0_0402_5%
U3TXDP4_C_L
U3TXDP4_C_L <25>
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Date:
Rev
4019HF
Sheet

E
B
31
of
51
Issued Date
Compal Secret Data
2011/12/14
2012/12/31
Deciphered Date
Title
Custom
Date:
Rev
4019HF
Sheet

E
B
32
of
51
2W 4ohm =40mil
1W 8ohm =20mil
+3VL
+DVDD_IN
1
RA29
2
RA25
100K_0402_5%
3
G
47K_0402_5%
RA24
CA44
0.01U_0402_25V7K
CA7
close to pin 41
2
0_0603_5%
AO3413_SOT23
QA2
CA1
+DVDD_IO
0.1U_0402_10V7K
0.1U_0402_10V7K
CA6
1
RA1
0.1U_0402_10V7K
CA5
+3VS
CA43
+5VALW
LA1
1
2 0.1U_0402_10V7K
2 PBY160808T-601Y-N_2P
1
1
+PVDD
2
0_0603_5%
1
10U_0603_6.3V6M
CA9
0.1U_0402_10V7K
0.1U_0402_10V7K
27
38
AVDD2
46
41
<35,38,44,45>
AVDD1
SUSP#
CA11
RA43
100K_0402_5%
MIC1_R_L 4.7U_0603_6.3V6K
MIC1_R_R
4.7U_0603_6.3V6K
CA14
CA15
2
CA16
For EMI
RA41
INT_MIC_CLK_R
FBMA-10-100505-301T
<13> INT_MIC_DATA
CAM@
1
<13> INT_MIC_CLK
MIC1_R_C_L
MIC1_R_C_R
28
29
LINE1_L
LINE1_R
SPK_OUT_L+
SPK_OUT_L-
42
43
39
40
LINE2_L
LINE2_R
SPK_OUT_R+
SPK_OUT_R-
45
44
19
20
1
36
2.2U_0603_10V6K 35
INT_MIC_CLK_R
CA49 CAM@
220P_0402_50V7K
AZ_RST_HD#
HP_OUT_L
HP_OUT_R
GPIO1/1st DMIC
GPIO0/DMIC-CLK
CA13
@
CA38
10U_0603_6.3V6M
LA5
2
1
0_0603_1%
SPKR-
2
CA29
@
10U_0603_6.3V6M
1
GPIO4
RESET#
10
BCLK
SDATA_OUT
SDATA_IN
EAPD+PD#
48
SPK_L1
<34>
SPK_L2
<34>
SPK_R1
<34>
SPK_R2
<34>
CA40
1U_0402_6.3V4Z
@
2
CA30
@
10U_0603_6.3V6M
1
2
CA31
@
10U_0603_6.3V6M
1
CA41
1U_0402_6.3V4Z
@
SPKL+
SPKLSPKR+
SPKRRA5
RA6
31
32
SYNC
Beep sound
PCI Beep
75_0402_1%
75_0402_1%
HP_L
HP_R
<34>
<34>
AZ_SYNC_HD
AZ_BITCLK_HD
EC_MUTE# Internal AMP

Hight
Enable
LOW
Disable
+3VALW
2
RA7
1
33_0402_5%
AZ_SDIN0_HD
<16>
1
RA3
RA11
4.7K_0402_5%
2
10K_0402_5%
EC_MUTE#
EC_MUTE# <35>
MONO_IN
0.1U_0402_10V7K
<16>
AZ_BITCLK_HD <16>
AZ_SDOUT_HD <16>
AZ_SDIN0_HD_R
CA27
1
2
RA10
1
2
47K_0402_5%
CA22
100P_0402_50V8J
11
CA12
0.1U_0402_10V7K
1
1
2
CA28
@
10U_0603_6.3V6M
1
<16> PCH_SPKR
CBP
CBN
<16> AZ_RST_HD#
MIC1_L
MIC1_R
+5VALW
RA2
1
2
0_0603_5%
close to pin 38
1
2
1
2
10U_0603_6.3V6M 10U_0603_6.3V6M
UA1
PVDD2
QA3B
CA10
1
2
10U_0603_6.3V6M
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
SM_EN
5>
close to pin 9
CA4
PVDD1
QA3A
2
1
0_0603_1%
LA4
2
1
0_0603_1%
SPKR+
0.1U_0402_10V7K
2
1
2
+AVDD
2
CA3
+DVDD
DVDD
2
0_0603_5%
LA3
DVDD_IO
1
RA12
2
10U_0805_10V4Z
close to pin 46
close to pin 27
+DVDD_IN
SPKL-
1
2
10U_0603_6.3V6M
CA45 0.1U_0402_10V7K
2
1
CA8
close to pin 3
CA2
placement near Audio Codec

LA2
2
1
0_0603_1%
+3VL
SPKL+
IN1
IN2
SENSE_A
13
SENSE A
1 RA42
2
10K_0402_5%
14
SENSE B
24
NC
UA3
JACK_SENSE 2
12
RA19 2 HWEQ_EN_D
4HWEQ_EN 1
1K_0402_5%
2
2
CA47
G
0.1U_0402_25V6
2N7002_SOT23-3
QA5
HWEQ_EN_D
18
+3VL
XA1
OSC@
1
0.1U_0402_10V7K
<27>
HWEQ_EN
4
2
CA39
HWEQ_EN
VDD
OUT
VCOUNT GND
OSC_OUT
1 RA28
2
10_0402_5%
OSC_IN
1
PCBEEP
37
LINE1_VREFO
23
AGPO/MIC1_VREFO
LDO_CAP
30
21
NC
VREF
25
@
AZ_BITCLK_HD 2
10_0402_5%
+MIC1_VREFO
CA48
1
1
2 @
RA27
10P_0402_50V8J
To solve noise issue
For EMI
please place near codec
close to pin 21
2
CA18
RA4
4.7K_0402_5%
1
10U_0603_6.3V6M
Ext.MIC/LINE IN JACK
AC_VREF
close to pin 22
47
AUX mode/GPIO2
JDREF
22
AC_JDREF
2 RA8
17
16
NC
NC
2
CA19
AUX_CLK_In
34
26
33
49
CPVEE
15
CPVEE
AVSS1
AVSS2
DVSS
1 20K_0402_1%
1
1
2.2U_0603_10V6K
CA20
2
2
0.1U_0402_10V7K
RA13
2
1K_0402_5% RA15
2
1
MIC1_R_R
CA21
2.2U_0603_6.3V6K
@
MIC1_R_L
2
1
1K_0402_5%
RA14
ALC280Q-GR_QFN48_6X6
CA42
10P_0402_50V8J
12.288MHZ_15PF_SSW012288D3CH
OSC@
MONO_OUT
SA000051D00
DGND AGND
RA26
1 271@ 2
0_0402_5%
<27> OSC_IN_R
MIC_SENSE#
OSC_OUT
2
RA16
1
2.2K_0402_5%
+MIC1_VREFO
MIC1_R
<34>
MIC1_L
<34>
+MIC1_VREFO
QA1A
RA17
2N7002DW-T/R7_SOT363-6
Placement near to UA1.15
100K_0402_5%
2
1
SJ000001A00
1
2.2K_0402_5%
5
SM_EN
GPIO3/SPDIFO
MONO_IN
2
100P_0402_50V8J
0.1U_0402_10V7K
1
2
CA46
1
CA17
+3VL
SENSE A
Impedance
Codec Signals
Function
39.2K
PORT-A (PIN 31, 32)
Headphone out
20K
PORT-B (PIN 19, 20)
Ext. MIC
10K
place close to chip

MIC_SENSE#
SENSE_A
NBA_PLUG
RA21
2 0.1U_0603_50V7K
CA24 1
2 0.1U_0603_50V7K
CA25 1
2 0.1U_0603_50V7K
CA26 1
2 0.1U_0603_50V7K
1
RA22
39.2K_0402_1%
+3VL
RA18
100K_0402_5%
EC
<35> SM_SENSE#
QA1B
2
10_0603_5%
2N7002DW-T/R7_SOT363-6
PORT-E
JACK_SENSE <34>
5.1K
1
20K_0402_1%
PORT-C (PIN 28, 29)

<34>
2
RA20
CA23 1
Sense Pin
39.2K
SENSE B
20K
2011/12/14
Issued Date
10K
Compal Secret Data
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
Sheet
1
33
of
51
HeadPhone/LINE OUT JACK

JLINE
6
5
4
<33> NBA_PLUG
<33>
HP_R
<33>
HP_L
LA6 1
2 HP_R_L
CHILISIN PBY100505T-121Y-N 0402
LA7 1
2 HP_L_L
3
2
1
1
3
1
2
CA32
100P_0402_50V8J
DA3 @
PJDLC05_SOT23-3
CA33
CA34 @
100P_0402_50V8J
2
0.1U_0402_10V7K
SINGA_2SJ-0960-D06
@
For EMI
EXT.MIC/LINE IN JACK
+3VL
RA23
4.7K_0402_5%
JEXMIC
6
5
4
<33> JACK_SENSE
<33>
MIC1_R
<33>
MIC1_L
LA8 1
2 MIC1_L_R
LA9 1
2 MIC1_L_L
3
2
1
SINGA_2SJ-0960-D06
@
CA35
100P_0402_50V8J
CA36
100P_0402_50V8J
DA4 @
PJDLC05_SOT23-3
CA37 @
2
0.1U_0402_10V7K
For EMI
SPK CONN.
@
DA5
PJDLC05_SOT23-3
3
1
2
JSPK
<33>
<33>
<33>
<33>
SPK_L1
SPK_L2
SPK_R1
SPK_R2
PJDLC05_SOT23-3
3
1
2
1
2
3
4
5
6
1
2
3
4
G1
G2
ACES_50278-00401-001
@
DA6
@
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
Sheet
34
of
51
+3VL
RB3
10_0402_5%
@
1
CLK_PCI_EC
PLT_RST#
EC_RST#
EC_SCI#
AOAC_EN#
<20> CLK_PCI_EC
<5,20,27,28,29,31,36> PLT_RST#
+3VL
RB2
47K_0402_5%
1
2
<21> EC_SCI#
<27,38> AOAC_EN#
EC_RST#
1
2
CB12 0.1U_0402_10V7K
KSI[0..7]
<36,37> KSI[0..7]
KSO[0..17]
<36,37> KSO[0..17]
+3VL
+3VS
RB12
1
1
RB13
RB15
1
1
RB16
2.2K_0402_5%
2 EC_SMB_CK1
2 EC_SMB_DA1
2.2K_0402_5%
<15,40,41>
<15,40,41>
<17,36>
<17,36>
2.2K_0402_5%
2 EC_SMB_CK2
2 EC_SMB_DA2
2.2K_0402_5%
<25,31> USB_CHG_EN#
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<21>
EC_SMI#
<20,25,31> USB_OC#1
<33> SM_EN
<36>
KB_LED
<5> FAN_SPEED1
<27> WL_OFF#
<27,36> E51_TXD
<27,36> E51_RXD
<5,18> PM_PWROK
<37> PWR_SUSP_LED#
<36> NUM_LED#
<18>
FUNCTION_LED#
EC_WL_BT_LED
FANPWM
GPUPWR_SKIN#
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
63
64
65
66
75
76
BATT_TEMPA
TMPTU1_SXP
ADP_I
ADP_V
TMPTU2_SXP
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
68
70
71
72
HDPINT
PCH_PWR_EN
PCH_SUSPWRDN#
SUSACK#
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
83
84
85
86
87
88
EC_MUTE#
USB_EN#
SM_SENSE#
HDPLOCK
TP_CLK
TP_DATA
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
97
98
99
109
VGATE
WOL_EN#
PWRME_CTRL
VCIN0_PH
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
119
120
126
128
AD Input
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
RB20
0_0402_5%
1
2
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
PS2 Interface
SPI Flash ROM
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
XCLKI/GPIO5D
XCLKO/GPIO5E
CB16
20P_0402_50V8
GPIO
<37>
1
CB9
ACIN_D
1
2
CB10 100P_0402_50V8J
2
100P_0402_50V8J
TMPTU1_SXP
1
RB4
2
10K_0402_5%
TMPTU2_SXP
1
RB5
2
10K_0402_5%
@
GPUPWR_SKIN#
1
RB28
TV tuner
temperature
2
10K_0402_5%
2
100K_0402_5%
EC_MUTE# <33>
USB_EN# <30>
SM_SENSE# <33>
HDPLOCK <36>
TP_CLK <37>
TP_DATA <37>
+3VS
VGATE
<18,46>
WOL_EN# <28>
PWRME_CTRL <16>
VCIN0_PH <40>
+3VL
CEC_INT#
1
RB7
2
100K_0402_5%
LID_SW#
1
RB35
2
47K_0402_5%
AOAC_WAKE#
1
RB29
RB37
10K_0402_5%
2
10K_0402_5%
C
+3VS
LNB_OC# <44>
LNB_EN <44>
AOAC_WAKE# <27>
UMA_ENBKL
CPSETIN
HDPACT
BATT_FULL_LED#
CAPS_LED#
PWR_ON_LED#
BATT_CHG_LOW_LED#
SYSON
VR_ON
USB_OC#0
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
100
101
102
103
104
105
106
107
108
PCH_RSMRST#
EC_LID_OUT#
PROCHOT_IN
H_PROCHOT#_EC
VCOUT0_PH_L
BKOFF#
PBTN_OUT#
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
110
112
114
115
116
117
118
ACIN_D
EC_ON_R
ON/OFFBTN#
LID_SW#
SUSP#
CEC_INT#
EC_PECI
V18R
124
+EC_V18R
SA_PGOOD
UMA_ENBKL <13,19>
CPSETIN <40>
HDPACT <36>
BATT_FULL_LED# <37>
CAPS_LED# <36>
PWR_ON_LED# <37>
BATT_CHG_LOW_LED# <37>
SYSON
<43>
VR_ON
<46>
USB_OC#0 <20,30>
PCH_RSMRST# <18>
EC_LID_OUT# <21> PROCHOT_IN connect
PROCHOT_IN <40> to power portion (9012
VS_ON
<40,42>
BKOFF# <13>
PBTN_OUT# <18>
SA_PGOOD <45>
TP_CLK
1
RB8
2
4.7K_0402_5%
TP_DATA
1
RB9
2
4.7K_0402_5%
SYSON
1
RB10
LNB_EN
1 BCAS@ 2
RB11
10K_0402_5%
EC_WL_BT_LED
1
RB14
2
10K_0402_5%
RB18
330K_0402_5%
2
1
NV-GPU GPS function control pin

connect to a OR-gate
in the power portion
ACIN_D
ON/OFFBTN# <37>
LID_SW# <36>
SUSP#
<33,38,44,45>
CEC_INT# <15>
1
RB19
2
4.7K_0402_5%
only)
VCOUT0_PH connect
to power portion (9012 only)
2
RB751V40_SC76-2
+3VL
1
DB1
ACIN
<18,41>
B
H_PECI
2
43_0402_1%
H_PECI
<5>

2011/10/18a
LNB_OC#
KB9012QF-A3_LQFP128_14X14
BATT_TEMPA
H_PROCHOT#_EC 1
RB6
HDPINT <36>
PCH_PWR_EN <38>
PCH_SUSPWRDN# <18>
SUSACK# <18>
LNB_EN
CB8
47P_0402_50V8J
+3VS
BATT_TEMPA <40>
TMPTU1_SXP <27>
ADP_I
<40,41>
ADP_V <41>
TMPTU2_SXP <27>
73
74
89
90
91
92
93
95
121
127
GPI
FANPWM <5>
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
GPIO
Bus
FUNCTION_LED#
H_PROCHOT#_EC 2
G
SSM3K7002F_SC59-3 S
VCIN0_PH connect to
power portion (9012 only)
SPI Device Interface
1
QB1
67
21
23
26
27
DA Output
RB22
100K_0402_5%
SUSP#
2
180P_0402_50V8J
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
H_PROCHOT# <5,40>
D
EC_WL_BT_LED
2
QB2 G
2N7002_SOT23-3
PWM Output
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
PLT_RST#
2
1U_0402_6.3V6K
SUSP#
1
RB21
2
10K_0402_5%
VR_ON
1
RB23
2
10K_0402_5%
CB15
4.7U_0805_10V4Z
SA00004OB20
CIR
1
CB14
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
1
CB13
CLK_EC
12
13
37
20
38
PM_SLP_S3#
SLP_S5#
EC_SMI#
CIR_IN
USB_OC#1
USB_CHG_EN#_R
SM_EN
KB_LED
FAN_SPEED1
WL_OFF#
E51_TXD
E51_RXD
PM_PWROK
PWR_SUSP_LED#
NUM_LED#
<18> PM_SLP_S3#
RB17
0_0402_5%
1
2 USB_CHG_EN#_R
1
2
3
4
5
7
8
10
11
24
35
94
113
CB11
10P_0402_50V8J
@
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
<21> GATEA20
<21> KB_RST#
<16> SERIRQ
<16,36> LPC_FRAME#
<16,36> LPC_AD3
<16,36> LPC_AD2
<16,36> LPC_AD1
<16,36> LPC_AD0
VR_HOT#
<37> WL_BT_LED#
1
CLK_PCI_EC
<46>
0_0402_5% RB1
1
2
CB6
2
2
1000P_0402_50V7K
UB1
EC_VDD/AVCC
2
0.1U_0402_10V7K
AGND/AGND
CB4
69
9
22
33
96
111
125
PVT change RF LED control

pin from PCH to EC
CB3
0.1U_0402_10V7K
1
2
GND/GND
GND/GND
GND/GND
GND/GND
GND0
For EMI
1000P_0402_50V7K
1
CB7
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
1
CB2
CB5
CB1
0.1U_0402_10V7K
+3VL
+5VL
1
Close to EC
<18,31> PM_SLP_S4#
Y
A
Voltage Comparator Pins FOR 9012 A3

4
TC7SH08FUF_SSOP5
VCIN0 pin109
VCIN1 pin102
>1.2V
VCOUT0 pin104
HIGH
@
1
RB25
RB27
100K_0402_5%
1
2
2
0_0402_5%
RB24
10K_0402_5%
<42>
SLP_S5#
2
EC_ON
2.2K_0402_5%
1
CB50
1U_0402_6.3V6K
UB2
<18> PM_SLP_S5#
EC_ON_R
1
RB36
CB17
0.1U_0402_10V7K
1
2
+3VALW
VCOUT1 pin103
LOW
<1.2V
+5VL
LOW
UB3
2 +5VL_CIR
100_0805_5% 1
CB18
4.7U_0805_10V4Z
2
CIR@
For KB9012 EC_ON low pulse work around
Issued Date
VCC
GND
GND
Compal Secret Data

2011/12/14
2012/12/31
Deciphered Date
Title
Date:
Vout
IRM-V538/TR1_3P
Size
5
CIR@
HIGH
E51_TXD
CIR_IN
CIR@
1
RB26
Document Number
Rev
B
4019HF
Sheet
1
35
of
51
SPI Flash (128KB)
LPC Debug Port
Lid SW
18
17
16 16
15 15
14 14
13 13
12 12
11 11
10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
@ JDB
ACES_88512-1641
+3VL
VDD
VOUT
LID_SW#
C453
0.1U_0402_16V4Z
<35>
GND
U21
APX9132ATI-TRL_SOT23-3
C452
10P_0402_50V8J
Place the JDB under DDR DIMM.
G18
G17
E51_RXD_DB
1
E51_TXD_DB R21 1
R23
@
@
2
2 0_0402_5%
0_0402_5%
E51_RXD <27,35>
E51_TXD <27,35>
PLT_RST# <5,20,27,28,29,31,35>
CLK_PCI_DDR <20>
LPC_AD0 <16,35>
LPC_AD1 <16,35>
LPC_AD2 <16,35>
LPC_AD3 <16,35>
LPC_FRAME# <16,35>
CLK_PCI_DDR
+3VS
+3VALW
C457
2 1
R393
22P_0402_50V8J
@
CLK_PCI_DDR
22_0402_5%
@
For EMI
Q38 KBL@
AO3413_SOT23
D
+5VS_LED
1
C836
0.1U_0402_10V7K
2 KBL@
1
2
3
4
G1
G2
5
6
SELF_TEST
E-T_6905K-Q04N-00R
@
+5VS
For EMI
KB_LED
Close to JKB
2
G
3
<35>
Q52
2N7002_SOT23-3
KBL@
KSO16
KSO17
KSO2
KSO1
KEYBOARD CONN.
KSO0
KSO4
KSI[0..7]
KSO[0..17]
KSI[0..7]
<35,37>
KSO[0..17] <35,37>
KSO3
KSO5
KSO14
36
35
GND2
GND1
JKB34
1
2
+3VS
34 34
KSO16
R372 300_0402_5%
33 33
32 32
KSO17
31 31
30 30
29 29
KSO2
28 28
KSO1
27 27
KSO0
26
26
KSO4
25 25
KSO3
24 24
KSO5
23 23
KSO14
22
22
KSO6
21 21
KSO7
20 20
KSO13
19 19
KSO8
18
18
KSO9
17 17
KSO10
16 16
KSO11
15 15
KSO12
14
14
KSO15
13 13
KSI7
12 12
KSI2
11 11
KSI3
10
10
KSI4
9 9
KSI0
8 8
KSI5
7
7
KSI6
6 6
KSI1
5 5
JKB4
2
1
+3VS
4 4
CAPS_LED# R376 300_0402_5%
3
CAPS_LED# <35>
3
2 2
NUM_LED#
NUM_LED# <35>
1 1
JKB
HB_A803419-SBHR21
@
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
CAPS_LED#
NUM_LED#
1
C401
1
C402
1
C404
1
C405
1
C406
1
C407
1
C408
1
C409
1
C410
1
C411
1
C412
1
C413
1
C415
1
C416
1
C417
1
C418
1
C419
1
C420
1
C421
1
C422
1
C423
1
C424
1
C425
1
C427
1
C429
1
C431
1
C433
1
C435
2
12
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
CG12
1U_0402_6.3V6K
GSENSOR@
+3VS_HDP
UG3
VIN
GND
SHDN#
VOUT
BP
G9191-330T1U_SOT23-5
4
6
8
ST
PD
FS
Rev
Voutx
Vouty
Voutz
3
5
7
NC1
NC2
NC3
NC4
NC5
10
11
14
15
16
GND1
GND2
1
13
VOUTXCG1
VOUTYCG2
VOUTZCG3
GSENSOR@
0.033U_0402_16V7K
1
2
0.033U_0402_16V7K
1
2
0.033U_0402_16V7K
1
2GSENSOR@
GSENSOR@
TSH352TR LGA 16P
GSENSOR@
+3VS_HDP
GSENSOR@
Vdd1
Vdd2
+5VS_LED
R587
10K_0402_5%
KBL@
1
2
3
4
+3VS_HDP
CG13
1U_0402_6.3V6K
GSENSOR@
2
SA00004GB00
CG14
2
1
@
0.22U_0402_10V4Z
SA000022I00
UG5
<17,35> EC_SMB_CK2
P1_6/CLK0/SSI01
11
P1_5/RXD0/CNTR01/INT11#
12
P1_4/TXD0
13
P1_3/KI3#/AN11/TZOUT
14
P3_5/SSCK/SCL/CMP1_2
HDPACT
<35>
+5VS
UG1
G-Sensor
JBLG
SELF_TEST
+3VS_HDP
P3_7/CNTR0#/SSO/TXD1
RG3 2
GSENSOR@
1
4.7K_0402_5%
RESET#
RG4 2
GSENSOR@
1GXOUT
4.7K_0402_5%
XOUT/P4_7
5
RG5 2
GSENSOR@
<35>
HDPINT
HDPINT
1GXIN
4.7K_0402_5%
RG6
2
1 4.7K_0402_5%
GSENSOR@
RG7
2
1 1K_0402_5%
GSENSOR@
1
CG7
0.1U_0402_10V7K
GSENSOR@ 2
2011/12/14
HDPLOCK <35>
VOUTZ
P1_2/KI2#/AN10/CMP0_2
15
P4_2/VREF
16
VOUTX
VOUTY
RG10 47K_0402_5%
2
1
GSENSOR@
SA00003A600
6
XIN/P4_6
VCC/AVCC
17
MODE
18
P4_5/INT0#/RXD1
P3_3/TCIN/INT3#/SSI00/CMP1_0
19
P3_4/SCS#/SDA/CMP1_1
20
10
1
P1_7/CNTR00/INT10#
CG8
GSENSOR@
0.1U_0402_10V7K
R5F211B4D34SP
2
Deciphered Date
+3VS_HDP
CG6
0.1U_0402_10V7K
GSENSOR@
EC_SMB_DA2 <17,35>
GSENSOR@
Compal Secret Data
Issued Date
VSS/AVSS
RG9
47K_0402_5%
GSENSOR@
Keyboard LED
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
Sheet
36
of
51
+3VL
+1.8VS
Power Button
+5VS
R395
+3VS
1
+3VS
1
+3VS
1
+3VS
1
C484
C483
Near CRT side
+3VS
C482
C481
+3VS
1U_0402_6.3V6K
1U_0402_6.3V6K
+5VS
C479
GND
GND
1U_0402_6.3V6K
6
5
7
8
B+
1
1U_0402_6.3V6K
G
G
L30ESD24VC3-2_SOT23-3
B+
0.1U_0402_25V6
For EMI request
NTC017-DA1J-D160T_4P
C478
<11,12,17,27> PM_SMBCLK
<11,12,17,27> PM_SMBDATA
0.1U_0402_25V6
+CRT_VCC
C474
1
2
3
4
5
6
0.1U_0402_25V6
PWR_ON_LED#
1
2
3
4
5
6
C473
+3VS
TP_DATA
TP_CLK
1U_0402_6.3V6K
D83
ON/OFFBTN#
SW3
1
Add C463/C464 for ESD request 12/20
JTP
<35>
<35>
C472
Touchpad Connector
ON/OFFBTN# <35>
C458
0.1U_0402_25V6
@
C464
0.1U_0402_25V6
C469
For debug
ON/OFFBTN#
0.1U_0402_25V6
C463
0.1U_0402_25V6
0.1U_0402_25V6
100K_0402_5%
Near UH1
D
ACES_88058-060N
YSDA0502C_SOT23-3
@
5
6
+5VS
1
Near Q24
+5VS
+3VALW_PCH
1
Near PC268
+3VALW_PCH
1
+3VALW_PCH
1
B+
1
B+
1
C491
1U_0402_6.3V6K
C488
TP_CLK
1U_0402_6.3V6K
TP_DATA
1U_0402_6.3V6K
C487
+5VALW
1U_0402_6.3V6K
C486
2
390_0402_5%
1U_0402_6.3V6K
C485
1
R22
C477
ON/OFFBTN#
C476
PWR_ON_LED#
0.1U_0402_25V6
GND
GND
1
2
3
4
C475
1
2
3
4
0.1U_0402_25V6
+5VS
D89
1U_0402_6.3V6K
@
@
JPOWER
please place near JFUNCTION
JOINT_F1017WR-S-04P
Add C469~C487 for ESD request 02/01
Screw Hole
WiMAX LED
LED_WIMAX# <27>
+3VS
BATT_FULL_LED# <35>
D23
BATT_CHG_LOW_LED# <35>
1
2
R66
510_0402_5%
+5VALW
A
3
Amber
HT-210UD5/BP5-A1681 _AMBER-WHITE
HT-110UD5_AMBER
White LED bright when AC-adaptor is plugged and a Battery is full charged
R819
2
1
10K_0402_5%
WIMAX@
3
H1
6
Q156A
2N7002DW-T/R7_SOT363-6
WIMAX@
VGA
H2
H_4P2
@
H3
H_4P7
@
H7
H_4P2x4P7
@
H_4P0N
@
2
390_0402_5%
R52
2
510_0402_5%
R48
+5VALW
CPU
D21
White
BATT CHARGE /FULL LED & AC IN
Q156B 2N7002DW-T/R7_SOT363-6
WIMAX@
WL_BT_LED# <35>
MINI CARD -- 3G
Amber LED bright when charging battery from AC-adaptor
MINI CARD -- WLAN
Amber LED blink during Critical Low battery

H28
H29
H_3P3
@
1
H_3P3
@
POWER LED
D22
White
R49
PWR_ON_LED# <35>
NPTH
H_3P0
@
H16
H_3P0
@
H20
H_3P0
@
H21
H_3P0
@
H23
H_3P0
@
H24
H_3P0
@
H30
H_3P0
@
H22
H_3P2x3P7N
@
H_3P2N
@
1
H_3P0
@
H15
H_3P0
@
Amber
HT-210UD5/BP5-A1681 _AMBER-WHITE
H14
H13
H10
PWR_SUSP_LED# <35>
2
390_0402_5%
R53
2
510_0402_5%
2
1
+5VALW
PCB Fedical Mark PAD

FD3
@
FD4
@
1
FD2
@
FUNCTION/B Connector
FD1
@
JFUN
GND
GND
6
5
4
3
2
1
4
3
2
1
R8
+5VS_FUNC 2
White LED
ISPD
FUNCTION_LED# <35>
KSO0
<35,36>
KSO0
KSIFUNCTION
2 R1467 KSI7
0_0402_5%
1 ECO@ 2 R1466 KSI6
0_0402_5%
JOINT_F1017WR-S-04P
Green LED
390_0402_5%
1
+5VS
1 3D@
D90
KSI7
<35,36>
KSI6
<35,36>
KSIFUNCTION
I/O1
I/O3
GND
VDD
I/O2
I/O4
ZZZ
UH1
DAZ0OT00200
R1
SA00005AGH0
SLJ8C
HM77R1@
UH1
HM76R1@
KSO0
PCB LA-8392P
Panther Point 82HM77 C-1 HM77
R1
SA00005FHA0
SLJ8E
Panther Point HM76 SLJ8E C1
SC500009S00 VF=2.8V~3.15V, Isink<15mA

SC500004W00 VF=2.75V~3.15V, Isink<15mA
FUNCTION_LED#
PJP1
AZC099-04S.R7G_SOT23-6
45@
R3
SA00005FHE0
SLJ8E
HM76R3@
DC30100AA00
PJP1
please place near JFUNCTION
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
1
Sheet
37
of
51
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
2
1
1
<22,23,28> PCH_PWR_EN#
C821
PCH_PWR_EN#
1 R5534 2
0_0402_5%
<35> PCH_PWR_EN
Q190
SUSP
2
G
2N7002_SOT23-3
D
Q5527
2
G
Q11B
C822
0.1U_0402_10V7K
470_0805_5%
Q11A
3 1
6
R413
820K_0402_5%
@
1 R410
2
+VSB
200K_0402_5%
S SB570020110
2N7002E-T1-E3_SOT23-3
R5529
100K_0402_5%
C468
R407
0.1U_0402_10V7K
C467
R470
470_0805_5%
R5545
10K_0402_5%
For EMI
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
SI4800BDY_SO8
+5VS
Q10B
C461
1U_0402_6.3V6K
Q10A
1
2
3
4
6
R412
820K_0402_5%
S
S
S
G
C466
R406
1 R409
2
+VSB
120K_0402_5%
C465
0.022U_0402_25V7K
4.7U_0805_10V4Z
SI4800BDY_SO8
1
D
D
D
D
4.7U_0805_10V4Z
1
C462
Q30
8
7
6
5
+1.8VS
+5VALW
+5VS
0.01U_0402_25V7K
1
4.7U_0805_10V4Z
C460
C459
1U_0402_6.3V6K
4.7U_0805_10V4Z
1
2
3
4
S
S
S
G
D
D
D
D
470_0805_5%
Q29
8
7
6
5
Vgs=10V,Id=9A,Rds=18.5mohm
+5VALW
Vgs=10V,Id=9A,Rds=18.5mohm
3 1
+3VS
+5VALW TO +5VS
+3VALW
+3VALW TO +3VS
Add Q41 for S3

resume problem
12/14
+3VALW
R422
100K_0402_5%
0.75VR_EN# <43>
R421
22_0805_5%
0.75VR_EN
<5,9,27,43> SUSP
Q44B
2N7002DW-T/R7_SOT363-6
SUSP
Q6A
Q189
SUSP
2
G
2N7002_SOT23-3
<33,35,44,45> SUSP#
+1.8VS
+5VALW
Q60
2N7002_SOT23-3
2
G
C389 near to Q49

C387,C388 near to D84
+5VS_ODD
+3VALW TO +3V_WLAN
for AOAC and WOWL
Q53A
2
1
<27,35> AOAC_EN#
2
2
C392
@
C386,C385 near to PC364
0.1U_0402_10V7K
10U_0603_6.3V6M
C384
<21>
ODD_EN#
2N7002DW-T/R7_SOT363-6
Q53B
2
Q45
2
47K_0402_5%
+3V_WLAN
C908
0.01U_0402_25V7K
R440
R105
0_0805_5%
@
AO3413_SOT23
Q210
C471
0.1U_0402_10V7K
AO3413_SOT23
C217
0.01U_0402_25V7K
1
C679
4.7U_0805_10V4Z
@
need mount R105 if system

don't support AOAC or WOWL
2
PJ28
JUMP_43X79
@
+5VS_ODD
+3VALW
10U_0603_6.3V6M
+5VS
R441
10K_0402_5%
0.1U_0402_10V7K
R1457
C392,C390 near to PL332
2
1
47K_0402_5%
C384 near to RW2
C907
+5VS
C391
R1456
100K_0402_5%
+3VS
C383
+5VS
+3VALW
+3VALW
0.1U_0402_10V7K
ODD_EN#
2N7002DW-T/R7_SOT363-6
2
C389
+5VS
0.1U_0402_10V7K
10U_0603_6.3V6M
C391 near to CH93
+5VS
C374
2
C388
6 1
C374,C383 near to
PQ402 and place on TOP
3
C387
+5VS TO +5VS_ODD
R457
470_0805_5%
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
C373
0.1U_0402_10V7K
C372
10U_0603_6.3V6M
+5VALW
+5VALW
C372,C373 near to PQ352
C382
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
10U_0603_6.3V6M
C381
C371
C366
C470
10U_0603_6.3V6M
2N7002DW-T/R7_SOT363-6
2
100K_0402_5%
1
R158
<44,45> VCCP_PWRGOOD
4
2
R468
470_0805_5%
Reserve for SW-node noise

place at noise source
For filter noise
+1.05VS_VCCP
SUSP
Q44A
2N7002DW-T/R7_SOT363-6
+0.75VS
R425
100K_0402_5%
<43> 0.75VR_OFF#
2N7002DW-T/R7_SOT363-6
+5VALW
For S3 CPU Power Saving
Q6B
Un-used Dual MOS
C680
1U_0402_6.3V6K
@
C390
C386
@
0.1U_0402_10V7K
10U_0603_6.3V6M
+3VS
@
C385
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
Sheet
E
38
of
51
VIN
@ PJP1
PL1
SMB3025500YA_2P
1
2
PF1
1
2
PC4
100P_0402_50V8J
1
2
SINGA_2DW-0005-B03
PC3
1000P_0402_50V7K
DC_IN_S2
2
10A_125V_451010MRL
PC2
100P_0402_50V8J
DC_IN_S1 1
PC1
1000P_0402_50V7K
RTC Battery
2
PBJ1
2
PR5
PR6
560_0603_5% 560_0603_5%
1
2 1
2 +RTCBATT
+RTCBATT
@ MAXEL_ML1220T10
SP093MX0000
@ PJ333
+3VLP
@
1
+3VL
+3VALWP
JUMP_43X39
PJ332
1 1
+3VALW
JUMP_43X118
(100mA,40mils ,Via NO.= 2)
(5A,200mils ,Via NO.= 10)

OCP=6.2A
@ PJ353
@ PJ352
VL
+5VL
+5VALWP
JUMP_43X39
+5VALW
@ PJ162
JUMP_43X118
(10.63A,425mils ,Via NO.= 20)

OCP=12.3A
+16VSP
+16VS
JUMP_43X79
@ PJ72
+VSBP
+VSB
@ PJ402
JUMP_43X39
(120mA,40mils ,Via NO.= 1)
JUMP_43X118
@ PJ182
+1.8VSP
@ PJ403
+1.8VS
+1.05VS_VCCPP
JUMP_43X118
+1.05VS_VCCP
JUMP_43X118
(1.65A,70mils ,Via NO.= 4)

OCP=4.2A
(14A,560mils ,Via NO.=28)

OCP=16.92A
ACIN
@ PJ76
4
+0.75VSP
JUMP_43X79
(0.5A,40mils ,Via NO.= 1)
+0.75VS
+1.5VP
@ PJ152
1 1
Precharge detector
Min.
typ.
Max.
H-->L 14.42V 14.74V 15.23V
L-->H 15.39V 15.88V 16.39V
+1.5V
JUMP_43X118
(6A, 240mils ,Via NO.= 12)

OCP=9.5A
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
D
Sheet
39
of
51
PH1 under CPU botten side :

CPU thermal protection at 90 degree C
Recovery at 56 degree C
Rset = 3 * Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
VMB
SUYIN_200045MR009G171ZR
PF2
BATT_S1
9
8
7
6
5
4
3
2
1
1
2
@ PJP2
PC8
0.01U_0402_25V7K
PC7
1000P_0402_50V7K
@ PC15
.1U_0402_16V7K
PR14
1K_0402_1%
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
Rtmh at 90C = 7.87K, Rtml at 56C = 26.1K

Rset = 3 * 7.87K = 23.61K ==> 23.7K
Rhyst = (23.7K * 26.1K) / (3 * 26.1K - 23.7K) = 11.33K ==> 11.3K
BATT+
15A_65V_451015MRL
1
9012@ PR17
10.7K_0402_1%
VL
1
1
930@ PC9
0.1U_0603_25V7K
930@ PR15
23.7K_0402_1%
2
+3VL
PR16
6.49K_0402_1%
2
1
1
3
BATT_TEMPA <35>
EC_SMB_DA1 <15,35,41>
<5,35> H_PROCHOT#
D
930@ PQ7
SSM3K7002FU_SC70-3
2
G
930@ PU2
1
VCC TMSNS1
GND RHYST1
OT1 TMSNS2
OT2 RHYST2
G718TM1U_SOT23-8
100K_0402_1%_NCP15WF104F03RC
@PC17
@
PC17
.1U_0402_16V7K
1
2
PROCHOT_IN <35>
9012@ PR32
0_0402_5%
1
2
9012@ PR27
100K_0402_1%
1
PR25
100K_0402_1%
1
2 1
QC@ PR30
56.2K_0402_1%
QC@ PR35
100K_0402_1%
2
1
QC@ PQ8B
PC11 @
0.1U_0603_25V7K
QC@
PC16
.1U_0402_16V7K
VL
DMN66D0LDW-7_SOT363-6
1
2
+VSBP
5
CPSETIN
<35>
PR24
PC10
0.22U_0603_25V7K
2
1
PR23
100K_0402_1%
VL
QC@
PQ8A
PQ5
TP0610K-T1-E3_SOT23-3
B+
1
1
930@ PR28
30.9K_0402_1%
<35,42> VS_ON
VCIN0_PH <35>
PH1
9012@PR22
9012@
PR22
12.7K_0402_1%
EC_SMB_CK1 <15,35,41>
ADP_I
PR21
100_0402_1%
9012@ PR33
0_0402_5%
<35,41>
2
PR20
100_0402_1%
930@ PR29
100K_0402_1%
+3VS
PR19
1K_0402_1%
930@ PR18
11.3K_0402_1%
1
2
+3VLP
PD6
PJSOT24C_SOT23-3
PD5
2
PJSOT24C_SOT23-3
3
9
8
7
6
5
4
3
2
1
GND
GND
GND
GND
13
12
11
10
PL2
SMB3025500YA_2P
1
2
22K_0402_1%
PR26
<18,42>
POK
PQ6
SSM3K7002FU_SC70-3
2
G
Adaptor protection
Adaptor
@ PC12
.1U_0402_16V7K
Throttling point ADP_I
Recovery point
ADP_I
90W
113.5W
1.783V
86.4W
1.357V
65W
71.8W
1.504V
62.5W
1.308V
0_0402_5%
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
D
Sheet
40
of
51
for reverse input protection
PQ206
SI1304BDL-T1-E3_SC70-3
2
G
B+
PQ201
SIS412DN-T1-GE3_POWERPAK8-5
5
PR217
2DH_CHG1 4
0_0402_5%
PC214
1
2
BQ24725_BATDRV
PR216
0_0402_5%
1
2
PC216
0.01U_0402_50V7K
@ PC231
220P_0402_25V8K
1
2
1
2
1
2
Remember to change PC124 from SE000006S80

to SE025104K80 (2011-02-22)
ILIM
SCL
9
PC209
0.1U_0603_16V7K
+3VALW
10
SDA
8
2
10K_0402_1%
IOUT
PR204
@ PC233
220P_0402_25V8K
11
@PC206
@
PC206
680P_0603_50V7K
@ PC232
68P_0402_50V8J
2
1
BATDRV
ACOK
<18,35> ACIN
PR219
PC201
10U_0805_25V6K
12
PC223
0.1U_0402_25V6
2
1
PC202
10U_0805_25V6K
SRN
ACDET
+3VL
BATT+
PC203
10U_0805_25V6K
ACDRV
2 BQ24725_ACOK 5
10K_0402_1%
SRP
BQ24725_ACDRV
PR218
10_0603_1%
SRP1
2 CSOP1
PR214
6.8_0603_5%
SRN1
2 CSON1
3
2
1
CMSRC
13
BQ24725_CMSRC
BQ24725RGRR_VQFN20_3P5X3P5
PR225
0.01_1206_1%
4
1 CSON1
14
GND
1 CSOP1
ACP
CHG
2
2
DL_CHG
15
PR206
4.7_1206_5%
LODRV
PL202
4.7UH_ETQP3W4R7WFN_5.5A_20%
PQ202
AO4468L_SO8
REGN
ACN
5
6
7
8
17
PAD
2BQ24725_BATDRV_1
PR203
4.12K_0603_1%
BQ24725_LX
16
BTST
HIDRV
18
19
PHASE
21
1
2
3
PC215
0.1U_0402_25V6
DH_CHG1
3
2
1
1 1
20
PU200
@ PC230
100P_0402_25V8K
2
1
1
2
PC220
0.1U_0402_25V6
PC219
0.1U_0402_25V6
1
2
PC227
10U_0805_25V6K
1
2
PC226
10U_0805_25V6K
1
PD202
RB751V-40_SOD323-2
BQ24725_REGN2
DH_CHG
BQ24725_LX
1U_0603_25V6K
VCC
BQ24725_ACP
PR222
4.12K_0603_1%
1U_0603_25V6K
PC205
1
8
7
6
5
BQ24725_BATDRV
0.047U_0402_25V7K
PR210
10_1206_1%
1
2
PD201
BAS40CW_SOT323-3
PC207
1
2
BQ24725_ACN
@ PC229
68P_0402_50V8J
2
1
PC212
0.1U_0402_25V6
1
2
VIN
1
PR221
4.12K_0603_1%
2
1
PC224
10U_0805_25V6K
PR205
0_0603_5%
BQ24725_BST 2
1
PC218
0.1U_0402_25V6
BQ24725_ACDRV_1
PQ205
MDS2659URH_SO8
PR215
0.01_2512_1%
1
4
PC217
0.1U_0603_25V7K
2
1
PC222
10U_0805_25V6K
8
7
6
5
PC221
10U_0805_25V6K
1
2
3
PL201
1UH_10.3A_20%
1
2
1
2
@ PR220
0_0402_5%
1
2
PC213
2200P_0402_50V7K
P2
PQ204
MDS2659URH_SO8
PC225
10U_0805_25V6K
P1
PQ203
TPCA8057-H 1N PPAK56-8
1
2
5
3
PC208
0.1U_0402_25V6
VIN
PR213
3M_0402_5%
BQ24725_VCC
2
PR212
1M_0402_5%
PC204
0.01U_0402_25V7K
PR201
100K_0402_1%
402K_0402_1%
VIN
PR208
270K_0402_1%
PR207
154K_0402_1%
VIN
BQ24725_ACDET
PR209
BQ24725_ILIM
ILIM and external DPM

3.97A
PR227
10K_0402_1%
1
2
EC_SMB_DA1 <15,35,40>
ADP_V
<35,40>
ADP_I
PR228
100P_0402_50V8J
PC228
.1U_0402_16V7K
47K_0402_1%
Please locate the RC

Near EC chip
2011-02-22
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
<35>
PC210
2
1
PR226
309K_0402_1%
EC_SMB_CK1 <15,35,40>
2
PR211
100_0402_5%
PC269
100P_0402_50V8J
2
1
Max.
PR202
66.5K_0402_1%
2
1
H-->L
L--> H
Typ
17.3V
17.8V
PC211
0.1U_0402_25V6
2
1
Vin Dectector
Min.
Document Number
Rev
B
4019HF
D
Sheet
41
of
51
2VREF_8205
PC363
1U_0603_10V6K
12
DRVL2
DRVL1
19
LG_5V
PC368
2200P_0402_25V7K
2
1
PC366
PQ352
FDMC7692S_MLP8-5
1 2
1
VCLK
3
2
1
18
17
16
TPS51125
VL
3/5V _B+
Ipeak=10.63A
Imax=7.44A
F=245KHz
Total Capacitor 440uF
ESR 8.5mohm
1
PQ360A
5
G
PC365
0.1U_0603_25V7K
2VREF_8205
PQ360B
3
4
PC364
4.7U_0805_10V6K
ENTRIP2
1
PR361
PC362
1U_0402_6.3V6K
@ PC240
220P_0402_25V8K
LG_3V
+5VALWP
PL352
2.2UH_PCMC063T-2R2MN_8A_20%
1
2
@ PC239
68P_0402_50V8J
2
1
LL1
LX_5V
PC352
220U_6.3V_M
2
1
LL2
20
PC351
220U_6.3V_M
11
@ PC356
@ PR356
680P_0603_50V7K 4.7_1206_5%
LX_3V
PQ351
21
<18,40>
PC355
2 0.1U_0603_25V7K
PR358
1
2
0_0603_5%
DRVH1
POK
3
2
1
DRVH2
13
10U_0805_25V6K
2
1
PC369
4.7U_0805_25V6K
2
1
1
ENTRIP1
10
1
2
3
VFB1
UG_3V
PR355
BST_5V 1
2
0_0603_5%
UG_5V
AO4468L_SO8
ENTRIP1
VREF
22
VREG5
VBST1
VIN
VBST2
PR360
499K_0402_1%
1
2
Ipeak=5A
Imax=3.5A
F=305KHz
Total Capacitor 330uF
ESR 15mohm
VFB2
BST_3V
EN0
B+
15mohm
TONSEL
23
100K_0402_5%
1 2
@ PC336
680P_0603_50V7K
@ PC238
220P_0402_25V8K
PC331
330U_6.3V_M
@ PC237
68P_0402_50V8J
2
1
ENTRIP2
24
PGOOD
PQ332
+
VO1
VREG3
@ PR336
4.7_1206_5%
VO2
GND
2
0_0603_5%
PR357
165K_0402_1%
1
2
SKIPSEL
PR335
1
2
0_0603_5%
3/5V _B+
15
1
2
3
PR338
P PAD
ENTRIP2
25
14
1
PC361
PU330
PC335
0.1U_0603_25V7K
1
2
PR365
19.1K_0402_1%
1
2
PR337
150K_0402_1%
1
2
8
7
6
5
+3VALWP
PL332
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
1
2
PR363
20K_0402_1%
1
2
4.7U_0805_10V6K
@ PC236
220P_0402_25V8K
PQ331
@ PC235
100P_0402_25V8K
2
1
PC360
4.7U_0805_25V6K
2
1
PC367
2200P_0402_25V7K
2
1
+3VLP
PR364
30K_0402_1%
1
2
ENTRIP1
B+
PL331
FBMA-L11-201209-121LMA50T_0805
2
1
@ PC234
68P_0402_50V8J
2
1
3/5V _B+
PR362
14K_0402_1%
1
2
SB00000EO00
VL
PR370
2
1
100K_0402_1%
<35,40>
VS_ON
9012@ PR373
0_0402_5%
PQ361
DTC115EUA_SC70-3
0.01U_0402_16V7K
@PC370
2
1
1
1
<35> EC_ON
PR372
42.2K_0402_1%
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
Sheet
1
42
of
51
HW side:
C106 330uF 17m
C218 390uF 10m
VGA@ CV122 390uF 10m
@ C189 330uF 15m
UMA
Ipeak=8.5A
Imax=5.95A
Rtrip=5.9K, OCP=11.338A
F=315KHz
Total Capacitor 1050uF,
ESR 4.43mohm
DIS
Ipeak=20A
Imax=14A
Rtrip=14K, OCP=24.136A
F=315KHz
ESR 3.07mohm
1
2
@ PC245
68P_0402_50V8J
2
1
PC159
22U_0805_6.3V6K
PC158
22U_0805_6.3V6K
2
1
PC157
22U_0805_6.3V6K
2
1
1
2
@ PC244
220P_0402_25V8K
PR165
100K_0402_1%
1
2
PC155
22U_0805_6.3V6K
2
1
LX
SS
6
PU150
SY8036DBC_DFN10_3x3
@PC166
@
PC166
0.1U_0402_10V7K
FB
+1.5VP
2
EN
3
PC160
22P_0402_50V8J
LX
PL152
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2
PR164
150K_0402_1%
1
2
SVIN
PG
4
1
+1.5V
VTTREF_1.5V
off
on
on
@PJ75
@
PJ75
JUMP_43X79
Note: S3 - sleep ; S5 - power off
PU75
VIN
VCNTL
GND
NC
VREF
NC
VOUT
NC
TP
+3VALW
PC264
2
PR280
1K_0402_1%
2
@ PR282
@PR282
0_0402_5%
1
2
PC265
4.7U_0805_6.3V6K
<38> 0.75VR_OFF#
<5,9,27,38> SUSP
EN_1.5V
PVIN
TP
PR163
0_0402_5%
1
2
SYSON
LX
1
2
PC154
22U_0805_6.3V6K
PC153
22U_0805_6.3VAM
1
2
PC152
2200P_0402_50V7K
@ PC241
220P_0402_25V8K
<35>
PVIN
+0.75VSP
off
off
on
Level
L
L
H
@ PC243
100P_0402_25V8K
2
1
1
2
Mode
S5
S3
S0
@ PC242
68P_0402_50V8J
2
1
10
1.5V_B+
11
+5VALW
PL151
HCB1608KF-121T30_0603
1
2
PR156
4.7_1206_5%
1
2
SNUB_+1.5VP
@PC156
@
PC156
680P_0603_50V7K
0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A
1U_0603_10V6K
+0.75VSP
PC263
.1U_0402_16V7K
2
1
1
2
PR281
1K_0402_1%
PQ260
SSM3K7002FU_SC70-3
PC261
.1U_0402_16V7K
2
G
1
<38> 0.75VR_EN#
G2992F1U_SO8
PR279
75K_0402_1%
1
2
PC262
10U_0805_6.3V6M
For shortage changed
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Size
Date:
Document Number
Rev
B
4019HF
D
Sheet
43
of
51
PL401
FBMA-L11-201209-121LMA50T_0805
2
1
PR402
6.49K_0402_1%
2
1
<38,45> VCCP_PWRGOOD
PR405
PC405
2.2_0603_1%
0.1U_0603_25V7K
1
2 BST1_+1.05VSP 1
2
1
2
@ PC246
220P_0402_25V8K
@ PC248
100P_0402_25V8K
@ PC247
68P_0402_50V8J
2
1
PQ401
MDV1525URH
+5VALW
PC411
2200P_0402_25V7K
2
1
PR401
3.4K_0402_1%
2
1
@ PC404
4.7U_0805_25V6-K
2
1
PC403
10U_0805_25V6K
2
1
PC402
10U_0805_25V6K
2
1
+1.05VSP_B+
B+
DIS
Ipeak=14A
Imax=9.8A
F=300KHz
ESR 2.5mohm
RF_+1.05VSP
TST
DRVL
PC407
1U_0603_10V6K
3
2
1
PR408
470K_0402_1%
@ PC408
0.1U_0402_16V7K
11
@ PC409
1000P_0402_50V7K
1
2
+1.05VSP1
@ PR409
1.2K_0402_1%
1
2
1
+
PC406
680P_0603_50V7K
1SNUB_+1.05VSP 2
TP
TPS51212
PQ402
TPCA8059-H_PPAK56-8-5
+5VALW
LG_+1.05VSP
+1.05VS_VCCPP
PR411
4.99K_0402_1%
2
1
PR413
100_0402_1%
2
1
VCCIO_SENSE <8>
VCCIO_SENSE1
V5IN
PC249
0.1U_0402_25V6K
VFB
+1.05VS_VCCPP
PL402
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
2
@ PC250
68P_0402_50V8J
FB_+1.05VSP
UG_+1.05VSP1
SW
SW_+1.05VSP
EN
PC401
330U_2.5V_M
PC410
.1U_0402_16V7K
EN_+1.05VSP
PR403
0_0402_5%
1
2
UG_+1.05VSP
10
DRVH
PR406
4.7_1206_5%
VBST
TRIP
<33,35,38,45> SUSP#
PGOOD
PR407
0_0402_5%
1
2
BST_+1.05VSP
1
TRIP_+1.05VSP
3
2
1
PU400
PR404
64.9K_0402_1%
1
2
PR410
10K_0402_1%
PR807
2
@ PR808
100K_0402_1%
2
1
@ PC1039
0.1U_0402_10V7K
47K_0402_1%
<35>
LNB_OC#
1
2
@ PC267
100P_0402_25V8K
APW7137BI-TRG_SOT23-5
FB
EN
@ PC266
100P_0402_25V8K
1
2
LX
GND
TV@ PC1037
10U_0805_25V6K
PU160
VIN
TV@ PC1036
10U_0805_25V6K
TV@
TV@ PR810
47K_0402_1%
1
2
TV@ PR805
604K_0603_1%
+16VSP
TV@ PR806
51.1K_0402_1%
APL3511CBI-TRG_SOT23-5
TV@
PL162
MCK1608471YZF_0603
1
2
EN#
OCB
TV@ PC1035
2.2U_0603_16V6K
GND
VIN
LNB_EN
TV@ PC964
22U_0805_6.3V6M
<35>
TV@
1
VOUT
1
TV@ PC963
22U_0805_6.3V6M
+5VALW
TV@ PL161
10UH_MLPS-5020-100M-E_1.5A_20%
LX_AVDD
1
2
PU161
@ PC1040
0.1U_0402_10V7K
2
1
TV@
TV@ PD203
BAT43WS-7-F_SOD323-2
Compal Secret Data
Issued Date
2011/12/14
Deciphered Date
2012/12/31
Title

Custom
Date:
5
Rev
B
4019HF
Sheet
1
44
of
51
The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
VID [0]
0
0
1
1
VID[1]
0
1
0
1
VCCSA Vout
0.9V
0.8V
0.725V
0.675V
PC456
680P_0603_50V7K
output voltage adjustable network
SNUB_+VCCSA
+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A
PR456
4.7_1206_5%
PVIN
LX
10
SVIN
LX
FB
PG
VOUT
EN
VID1
VID0
PR459
100K_0402_5%
2
1
SA_PGOOD <35>
+3VS
+VCCSA_EN
PR458
0_0402_5%
1
2
PR461
1K_0402_5%
1
2
PR460
1K_0402_5%
1
2
<38,44>
+VCCSA
PC454
22U_0805_6.3V6M
1
2
11
PL452
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2
+VCCSA_PHASE
PC453
22U_0805_6.3V6M
1
2
PC452
22U_0805_6.3V6M
1
2
+VCCSAP_FB
2
LX
13
1
2
PC458
22U_0805_6.3VAM
1
2
PC459
22U_0805_6.3VAM
PC460
0.1U_0603_25V7K
PC461
2200P_0402_50V7K
PC457
68P_0402_50V8J
PU450
SY8037BDCC
12 PVIN
PC451
22U_0805_6.3V6M
1
2
+VCCSA_PWR_SRC
PC455
0.1U_0402_10V7K
PL451
HCB1608KF-121T30_0603
1
2
GND
+5VALW
PR455
100_0402_5%
2
1
VCCP_PWRGOOD
PR457
0_0402_5%
2
1
+VCCSA_SENSE <9>
H_VCCSA_VID0 <9>
H_VCCSA_VID1 <9>
PL182
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2
@ PR182
499K_0402_1%
0.1U_0402_10V7K
PR184
10K_0402_1%
1
2
PC185
FB_1.8V
Ipeak=1.308A
ILIM = 4A
F=1MHz
PC183
22U_0805_6.3VAM
1
1
150K_0402_1%
PR183
20K_0402_1%
PR186
2
NC
TP
NC
1
EN_1.8V
PC186
PR181
11
<33,35,38,44> SUSP#
FB=0.6Volt
PC182
22U_0805_6.3VAM
FB
EN
PC184
22U_0805_6.3VAM
+1.8VSP
SVIN
3
4.7_1206_5%
LX
LX_1.8V
680P_0603_50V7K
PVIN
LX
PC187
68P_0402_50V8J
2
1
PVIN
PG
10
+5VALW
PU180
SY8033BDBC_DFN10_3X3
PL181
HCB1608KF-121T30_0603
1
2
Compal Secret Data
Issued Date
2011/12/14
Deciphered Date
2012/12/31
Title
Size
C
Date:

Document Number
Rev
B
4019HF
1
Sheet
45
of
51
PR582
1K_0402_1%
1
2
DROOP
PH503
100K_0402_1%_TSM0B104F4251RZ
2 PR588 1
137K_0402_1%
2
1
GFX@ PH502
100K_0402_1%_TSM0B104F4251RZ
GFX@ PR561
137K_0402_1%
2
1
LG2
6132P_VCCP
LG1
HG1
BST1
DC@ PR576
41.2K_0402_1%
1
2
TSENSE
<47>
SW2
<47>
CSP1A
CSP3
SW1
<47>
<47>
1
2 BST1_1 1
2
PR505
PC505
2.2_0603_5%
0.22U_0402_10V6K
3P: 73.2K
2P: 41.2K
DRVEN <47>
CSP3
.1U_0402_16V7K
CSP1
CSP2
CSP3
CSREF
CSP2
3P: 21K
2P: 12.4K
CSREF
<47>
CSP1
CSREF
PC575
1000P_0402_50V7K
6132_PWM <47>
CSREF
CSP2A
DC@ PR577
0_0402_5%
SW1A
3D@ PR600
0_0402_5%
<47>
1
2 BST2_1 1
2
PR515
PC515
<47>
2.2_0603_5%
0.22U_0402_10V6K
PC564
<47>
1
2
1
2
PR574
2.2U_0603_10V7K
PR5732
0_0402_5%
1
<47>
+5VS
0_0402_5%
Option for
2 phase CPU
HG2
Option for
1 phase GFX
DCG@ PR571
0_0402_5%
2
1
LG1A
BST2
1
2 BST3_1 1
2
GFX@ PR525 GFX@ PC525
<47>
2.2_0603_5%
0.22U_0402_10V6K
HG1A
DC@ PR590
806_0402_1%
QC@ PR579
6.98K_0402_1%
1
2
QC@ PC569
0.047U_0402_16V7K
SWN3
<47>
3P: install
2P: @
PR5832
6.98K_0402_1%
SWN2
<47>
SWN1
<47>
PC571
0.047U_0402_16V7K
PR5872
1
6.98K_0402_1%
PC576
0.047U_0402_16V7K
CSSUM
3P: 3.65K
2P: 9.53K
PC581
1000P_0402_50V7K
CSREF
1
2
3P: 23.7K
2P: 24.9K
3P: 806
2P: 1K
3P: 1500p
PC579
1
2
DC@ PR592
24.9K_0402_1%
1
2
3P: 2200p
2P: 3300p
.1U_0402_16V7K
CSCOMP
DC@ PR597
1K_0402_1%
1
2
DC@ PR589
8.06K_0402_1%
3P: 348
2P: 1.21K
FB_CPU2
PC577
0.033U_0402_16V7K
2P: 4.32K
BST3
PC568
1
2
CSCOMP
2P: 1000p
PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
DC@ PC570
10P_0402_50V8J
2
1
PR584
DC@ PC572
DC@ PR585
49.9_0402_1%
1000P_0402_50V7K 4.32K_0402_1%
PR586
PC574
1
2FB_CPU1 1
2
2
1COMP_CPU12
1
10_0402_1%
0.033U_0402_16V7K
DC@ PC573
1
2FB_CPU3 1
2
3P: 330p
3P: 6.04K
3300P_0402_50V7K
TRBST#
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PWMA
BSTA
HGA
SWA
LGA
BST2
HG2
SW2
LG2
PVCC
PGND
LG1
SW1
HG1
BST1
Disable: 0 Ohm
3P: 22p
2P: 10p
<47>
1
2
0_0402_5%
<8> VCCSENSE
PR580
PC567
1000P_0402_50V7K
VSP
<47>
2P: 36K
1P: 26.1K
6132_PWMA <47>
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSN
1
2
0_0402_5%
<8> VSSSENSE
SWN2A
DIFFA
TRBSTA#
FBA
COMPA
IMONA
ILIMA
DROOPA
CSCOMPA
CSSUMA
PR578
TRBST#
FB_CPU
COMP_CPU
IMON
ILIM_CPU
1
2
DC@ PR581 12.4K_0402_1% DROOP
<18,35> VGATE
SWN1A
+5VS
VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT
NCP6132AMNR2G QFN 60P
ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF
<35> VR_HOT#
DCG@ PR564
26.1K_0402_1%
1
2
2
1
PR575
10K_0402_5%
PC566
47P_0402_50V8J
Disable: 0 Ohm
TSENSE
2P: install
1P: @
PR572 1K_0402_1%
+3VS
GFX@ PC560
.1U_0402_16V7K
QCG@PC559
QCG@
PC559
0.047U_0402_16V7K
1
2
QCG@PR562
QCG@
PR562
6.98K_0402_1%
2
1
CSP2A
6.98K_0402_1%
2
@ PR605
0_0402_5%
CPU_B+
GFX@ PR559
1
@ PR606
0_0402_5%
PR570
95.3K_0402_1%
1
2
CSREFA <47>
GFX@ PC556
0.047U_0402_16V7K
@ PR607
0_0402_5%
VR_ON
2VR_SVID_DAT1
0_0402_5%
1
2
3
VR_ON_CPU
4
VR_SVID_DAT1 5
VR_SVID_ALRT# 6
PR569
VR_SVID_CLK
7
VBOOT
8
1
2
10K_0402_1% ROSC_CPU
9
VRMP
10
VR_HOT#
11
VGATE
12
13
14
DIFF_CPU
15
PR567
0_0402_5%
1
2
CSREFA
TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM
PC563
.1U_0402_16V7K
6132_VCC
2
1
PC561
2.2U_0603_10V7K
1
2
<35>
PR568
PU500
PC565
0.01U_0402_25V7K
2
PR566
54.9_0402_1%
2
1
130_0402_1%
1
2
PR565
<8> VR_SVID_DAT
<8> VR_SVID_ALRT#
<8> VR_SVID_CLK
PR563
2_0603_5%
1
2
+5VS
PC562
.1U_0402_16V7K
GFX@ PC558
1000P_0402_50V7K
CSP1A
GFX@ PC557
1000P_0402_50V7K
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
+1.05VS_VCCPP
3D@ PR601
0_0402_5%
3D@ PR602
0_0402_5%
Disable: 0 Ohm
GFX@ PR558
63.4K_0603_1%
CSP2A
CSP1A
TSENSEA
1
2
DCG@ PR560
16.5K_0402_1%
2P: 21.5K
1P: 15.8K
<9> VCC_AXG_SENSE
CSREFA
SWN1A
<9> VSS_AXG_SENSE
1P: @
1
2 SWN2A
QCG@PR557
QCG@
PR557
64.9K_0603_1%
GFX@ PC555
3300P_0402_25V7K
COMPA1 1
GFX@ PR556
5.11K_0402_1%
GFX@ PR555
1K_0402_1%
2
1 NTC_PH203
GFX@ PR553
165K_0402_1%
2P: install
GFX@ PC554
10P_0402_50V8J
1
2
GFX@ PC553
330P_0402_50V7K
FBA2
1
2
1
2
GFX@ PR554
10_0402_1%
1
2
TSENSEA
GFX@ PH501
220K_0402_5%_ERTJ0EV224J
DCG@ PR549
24.9K_0402_1%
Disable: 0 Ohm
GFX@ PC551
0.033U_0402_16V7K
GFX@ PR550
806_0402_1%
1
2
FBA1
GFX@ PR548
8.06K_0402_1%
1
2
Disable: 0 Ohm
TRBSTA#
GFX@ PC548
.1U_0402_16V7K
1
2
2P: 24K
1P: 24.9K
GFX@ PC552
1000P_0402_50V7K
DROOPA
CSREFA
1
2
2P: 1.65K
1P: 1K
Disable: 0 Ohm
@ PR603
0_0402_5%
Disable: 0 Ohm
GFX@ PR547
GFX@ PC547
10_0402_1%
0.033U_0402_16V7K
1
2 FBA3 1
2
DCG@ PR552
1K_0402_1%
1
2
CSCOMPA
@ PR604
0_0402_5%
QCG@ PR564
39K_0402_1%
QCG@ PR560
24K_0402_1%
QCG@ PR552
1.65K_0402_1%
QCG@ PR549
24K_0402_1%
3D@ PR571
0_0402_5%
DC/QC GFX SWITCH
3D@ PC560
0_0402_5%
GFX@ PR551
75K_0402_1%
3D@ PR552
0_0402_5%
3D@ PR549
0_0402_5%
3D@ PC549
0_0402_5%
3D@ PC554
0_0402_5%
GFX@ PC550
680P_0402_50V7K
DISABLE GFX function
GFX@ PC549
1200P_0402_50V7K
DC@ PC578
1200P_0402_50V7K 2P: 1200p
1
2
PC580
470P_0402_50V7K
1
2
1
2
PR594
PR595
75K_0402_1%
165K_0402_1%
2
PH504
PR5912
130K_0603_1%
SWN1
PR5932
130K_0603_1%
SWN2
2
QC@ PR596
130K_0603_1%
SWN3
3P: install
2P: @
1
220K_0402_5%_ERTJ0EV224J
DC/QC CPU SWITCH
QC@ PR576
73.2K_0402_1%
QC@ PR581
21K_0402_1%
QC@ PC578
1500P_0402_50V7K
QC@ PR592
23.7K_0402_1%
QC@ PC573
2200P_0402_50V7K
QC@ PR585
6.04K_0402_1%
QC@ PC570
22P_0402_50V8J
QC@ PR590
806_0402_1%
QC@ PC572
330P_0402_50V7K
QC@ PR597
806_0402_1%
Compal Secret Data
Issued Date
2011/12/14
2012/12/31
Deciphered Date
Title
QC@ PR589
8.06K_0402_1%
Date:
Custom
4
Rev
B
4019HF
Sheet
1
46
of
51
CSREF <46>
LG2
5
4
10_0402_1%
<46>
2
2
3
2
1
SWN1
HG3
EN
SW
SW3
GND
DRVL
3
SH00000HD00
PR599
V2N_CPU 2
NCP5911MNTBG_DFN8_2X2
3
2
1
SWN2
SH00000HD00
V3N_CPU 2
1
QC@ PR519
10_0402_1%
CSREF
SWN3
<46>
CPU_B+
CPU_B+
VCC
NCP5911MNTBG_DFN8_2X2
4
3
2
1
LG2A
QC 45W GT2
VID1=1.23V
IccMax=46A
Icc_Dyn=37A
Icc_TDC=38A
R_LL=3.9m ohm
OCP~55A
DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A
Compal Secret Data
Issued Date
2011/12/14
Deciphered Date
2012/12/31
Title
Size
C
Date:
QCG@ PC521
10U_0805_25V6K
2
1
QCG@ PQ519
MDV1525URH
5
@ PQ517
MDV1525URH
2
SH00000HD00
3
V2N_GFX
+GFX_CORE
QCG@ PL506
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4
SW2A
PR546
4.7_1206_5%
GND
DRVL
VCC_GFX2
QCG@ PR528
0_0402_5%
HG2A
QCG@ PR523
<46>
10_0402_1%
2
1
CSREFA
PC546
680P_0402_50V7K
EN
3
2
1
SW
PWM
QCG@ PR544
2.2_0603_1%
2
1
DRVH
2
EN_GFX2
SNUB_GFX2 2
FLAG
QCG@ PQ510
2
SWN1A <46>
BST
QCG@ PR521
0_0402_5%
QCG@ PR520
2
1
2K_0402_1%
1
3
2
1
+5VS 2
10_0402_1%
PC526
680P_0402_50V7K
BSTA2_1
2
DRVEN
QCG@ PC583
2.2U_0603_10V7K
1CSREFA
@ PC260
220P_0402_25V8K
2 PR522
@ PC259
68P_0402_50V8J
2
1
1
2
SH00000HD00
@ PC257
220P_0402_25V8K
@ PC258
100P_0402_25V8K
2
1
@ PC256
68P_0402_50V8J
2
1
PC519
10U_0805_25V6K
2
1
<46> 6132_PWMA
3
V1N_GFX
PR526
4.7_1206_5%
QCG@ PR545
2.2_0603_5%
1
2
QCG@ PU502
+GFX_CORE
PL505
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4
2
2
3
2
1
SNUB_GFX1
LG1A
PQ508
5
<46>
PC518
10U_0805_25V6K
2
1
@ PQ515
MDV1525URH
SW1A
1
<46>
3
2
1
PQ513
MDV1525URH
5
4
3
2
1
HG1A
BSTA2
QCG@ PC545
0.22U_0402_10V6K
2Phase: install
1Phase:: @
<46>
<46>
DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=33A
R_LL=1.9m ohm
OCP~65A
QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=56A
R_LL=1.9m ohm
OCP~110A
PR524
2.2_0603_1%
2
1
CSREF
10_0402_1%
QC@ PC511
10U_0805_25V6K
2
1
@ PQ511
MDV1525URH
5
QC@ PQ509
MDV1525URH
LG3
1
2
VCC
+CPU_CORE
QC@ PL504
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
SNUB_CPU3
2K_0402_1%
2
1 VCC_VCORE3 4
QC@ PR527
0_0402_5%
2
1
QC@ PR518
0_0402_5%
QCG@ PC522
10U_0805_25V6K
2
1
PR536
4.7_1206_5%
DRVH
PC536
680P_0402_50V7K
PWM
4
QC@ PR534
2.2_0603_1%
2
1
3
2
1
3
2
1
FLAG
QC@ PQ506
QC@ PR517
2
1EN_VCORE3
DRVEN
BST
QC@ PC582
2.2U_0603_10V7K
<46>
+5VS
<46> 6132_PWM
QC@ PC535
0.22U_0402_10V6K
BSTA1_1
QC@ PU501
QC@ PC510
10U_0805_25V6K
2
1
CPU_B+
QC@ PR535
2.2_0603_5%
BSTA1 1
2
PC508
10U_0805_25V6K
2
1
PC507
10U_0805_25V6K
2
1
1
<46>
PR516
4.7_1206_5%
SW2
PQ507
MDV1525URH
5
3
2
1
<46>
+CPU_CORE
PL503
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4
SNUB_CPU2
PR598
2
V1N_CPU
SH00000HD00
@ PC255
220P_0402_25V8K
+CPU_CORE
@ PC254
68P_0402_50V8J
PR514
2.2_0603_1%
2
1
HG2
3
2
1
<46>
@ PQ505
MDV1525URH
1
2
PC270
0.1U_0402_25V4K
PC520
68U_25V_M
PC517
100U_25V_M
PC513
100U_25V_M
@ PC251
220P_0402_25V8K
@ PC253
100P_0402_25V8K
2
1
@ PC252
68P_0402_50V8J
2
1
B+
PC516
680P_0402_50V7K
1SNUB_CPU1
PQ502
5
3
2
1
LG1
<46>
PR506
4.7_1206_5%
SW1
PL502
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<46>
PC502
10U_0805_25V6K
2
1
CPU_B+
PL501
HCB4532KF-800T90_1812
2
1
PC506
680P_0402_50V7K
PC501
10U_0805_25V6K
2
1
PQ503
MDV1525URH
3
2
1
HG1
3
2
1
<46>
PR504
2.2_0603_1%
2
1
@ PQ501
MDV1525URH
CPU_B+
PQ504
PC268
0.1U_0402_25V4K
2
1
SWN2A <46>

Document Number
Rev
B
4019HF
1
Sheet
47
of
51
PC910
10U_0805_6.3V6M
1
+
PC950
330U_D2_2V_Y
PC962
22U_0805_6.3V6M
PC949
330U_D2_2V_Y
1
2
@ PC948
PC931
22U_0805_6.3V6M
330U_D2_2V_Y
1
PC930
22U_0805_6.3V6M
PC961
22U_0805_6.3V6M
PC960
22U_0805_6.3V6M
PC959
22U_0805_6.3V6M
PC951
22U_0805_6.3V6M
PC925
22U_0805_6.3V6M
1
PC929
22U_0805_6.3V6M
@ PC935
330U_D2_2V_Y
1
PC928
22U_0805_6.3V6M
PC934
330U_D2_2V_Y
1
PC927
22U_0805_6.3V6M
PC924
22U_0805_6.3V6M
QCG@ PC933
330U_D2_2V_Y
1
PC926
22U_0805_6.3V6M
PC923
22U_0805_6.3V6M
PC932
330U_D2_2V_Y
PC958
22U_0805_6.3V6M
2
1
PC957
22U_0805_6.3V6M
PC920
22U_0805_6.3V6M
PC956
22U_0805_6.3V6M
PC955
22U_0805_6.3V6M
PC922
22U_0805_6.3V6M
PC954
22U_0805_6.3V6M
PC921
22U_0805_6.3V6M
+1.05VS_VCCP
PC953
22U_0805_6.3V6M
PC952
22U_0805_6.3V6M
PC919
22U_0805_6.3V6M
2
1
PC939
22U_0805_6.3V6M
PC947
22U_0805_6.3V6M
PC918
22U_0805_6.3V6M
PC938
22U_0805_6.3V6M
PC946
22U_0805_6.3V6M
PC917
22U_0805_6.3V6M
PC937
22U_0805_6.3V6M
PC945
22U_0805_6.3V6M
PC916
22U_0805_6.3V6M
PC936
22U_0805_6.3V6M
PC944
22U_0805_6.3V6M
PC943
22U_0805_6.3V6M
PC915
10U_0805_6.3V6M
+CPU_CORE
1
Socket Top
7 x 22 F (0805)
2 x (0805) no-stuff
sites
PC942
22U_0805_6.3V6M
PC914
10U_0805_6.3V6M
PC941
22U_0805_6.3V6M
PC913
10U_0805_6.3V6M
PC940
22U_0805_6.3V6M
PC912
10U_0805_6.3V6M
5 x 22 F (0805)
5 x (0805) no-stuff
sites
+GFX_CORE
PC911
10U_0805_6.3V6M
Socket Bottom
1
PC909
10U_0805_6.3V6M
PC908
10U_0805_6.3V6M
PC907
10U_0805_6.3V6M
PC906
10U_0805_6.3V6M
Below is 458544_CRV_PDDG_0.5 Table 5-8.
+CPU_CORE
+CPU_CORE
Chief River
1
+
1
+
PC901
330U_D2_2V_Y
1
PC902
330U_D2_2V_Y
1
PC903
330U_D2_2V_Y
330uF*9m
470uF*4.5m
22uF
10uF
16
10
1
PC904
330U_D2_2V_Y
PC905
330U_D2_2V_Y
8layer for DC CPU
8layer for QC CPU
16
10
6layer for DC CPU
16
10
6layer for QC CPU
16
10
GFX_CORE DC
12
GFX_CORE QC
12
1.05V_VCCP
12
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:

Document Number
Rev
B
4019HF
Sheet
1
48
of
51
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
-------------------------------------------------------------------------------------------------------------------------------1.
2.
3.
4.
5.
6.
7.
8.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
P51-PWR_+3VALWP/+5VALWP
P53-PWR_ +1.05VS_VCCP/+16VSP
P54-PWR_+VCCSAP/1.8VSP
P57-PWR +CPU_CORE DECOUPLING
P53-PWR_ +1.05VS_VCCP/+16VSP
P49-PWR_BATTERY CONN / OTP
Change PU330 to RT8205L

Change PU400 to RT8237C
Change PU450 to SY8037B
Change HMOS to MDV1525
Change HMOS to MDV1525
Change PD5,PD6 to SCA00001G00
Change PR589 from 348 to 8.06k
Change PR590 from 3.65k to 806
Change PC574 from 680P to 0.033u
Change PR548 from 1.21k to 8.06k
Change PR550 from 10.7k to 806
Add snubber and boost resistor
Add PR22 30k,PR27 100k, PR32 0 Ohm
Change PC360 to SE000006R80
Add PR17 14k, PR33 0 Ohm
Add PR373 0 Ohm
Change source
Change source
Change source
Change source
Change source
ESD team request
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
For 3x3 H-MOS solution
For 120W adapter protect(9012)
Change source
For CPU temperature protect(9012)
For 3/5V always power on(9012)
Issued Date
Compal Secret Data
2011/12/14
Deciphered Date
2012/12/31
Title
Custom
Date:
Rev
B
4019HF
Sheet
49
of
51
HW PIR (Product Improve Record)

QFKAA LA-8392P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2011/11/11
----------------------------------------------------------------------------------------------------------------------------------Item
Page
Date
Request
Solution
----------------------------------------------------------------------------------------------------------------------------------1)
13
2011/9/29a
by ESD demand
change D84 to SCA00001L00
2)
26
2011/9/29a
by ESD demand
3)
28
2011/9/29a
by ESD demand
4)
05
2011/10/05a
follow HW4 check list
reserve decoupling cap CC66, CC71, CC70 for H_PM_SYNC & H_PECI, BUF_CPU_RST#
5)
19
2011/10/05a
by Customer demand
add LVDS dual channel signal
6)
13
2011/10/05a
by Customer demand
add LVDS dual channel signal and 0ohm: R267 R268 R269 R270 R283 R329 R333 R337 (OPTFHD@)
and R500 R501 R502 R503 R504 R505 R507 R508 (3D@)
7)
17
2011/10/05a
by Customer demand
change RH116 to HD@
add RH282 FHD@
8)
35
2011/10/18a
discuss with EC
change Function_LED from EC_GPIO4D, PIN86 to EC_GPIO11, PIN25
change HDPLOCK from EC_GPIO11, PIN25 to EC_GPIO4D, PIN86
add GPUPWR_SKIN# on EC_GPIO13, pin27.
add RB28 for GPUPWR_SKIN#
change HDPACT from EC_GPIO43, PIN76 to EC_GPIO50, PIN89
reserve SUSACK# and PCH_SUSPWRDN# by SW demand
9)
18
2011/10/18a
by SW ME demand.
change PCH_SUSPWRDN_R to PCH_SUSPWRDN#_R
add PCH_SUSPWRDN# to EC and RH132
remove T75
change SUSACK# to SUSACK#_R
add RH133 and SUSACK# to EC
10)
30
2011/10/31a
by Layout demand
swap LR2, LR1, DR7
11)
32
2011/10/31a
by Layout demand
swap LT3, LT2
12)
20
2011/10/31a
by PWR 16V OC control demand
remove RH1, RH174, and change net-name from LNBPWR_MONITOR to LNB_OC
13)
37
2011/11/1a
new touch pad add new function
add JTP connector Pin 5 (PM_SMBCLK) , Pin6 (PM_SMBDATA)
14)
27
2011/11/1a
TV tuner(BCAS) 16V reserve
add RM15 and RM16 reserve for TV tuner (BCAS)
15)
33
2011/11/1a
avoid SM_EN floating
reserve RA43 for SM_EN 100K pull down reserve
16)
33
2011/11/1a
for vendor request
exchange location of RA28 and CA42
17)
33
2011/11/1a
for vendor request
RA26 pin2 change name from OSC_IN to OSC_OUT
18)
33
2011/11/1a
for vendor request, S&M HP need shut down
delete DA1. add RA19 ,QA5 ,RA42 ,
19)
23
2011/11/1a
for lot6 0.5W power consumption
delete CH57, PJ3 then add PJ5, QH6 ,CH59 , RH228
20)
38
2011/11/2a
add R5545, Q5527, R5529, R5534
21)
23
2011/11/2a
reserve RH228
22)
37
2011/11/2a
change D21 power from +5VL to +5VALW
23)
27
2011/11/6a
by EMI demand
add CCL10
24)
28
2011/11/6a
by EMI demand
add CL43, RL29
25)
29
2011/11/6a
by EMI demand
change RW4 from 0ohm to 33ohm, CW10 from 5pF to 6.8pF
26)
25
2011/11/7a
common with ME define location
change JUSB3RR to JUSBRR, JUSB3RF to JUSBRF
27)
30
2011/11/7a
change JUSB3LR to JUSBLR, JUSB3LF to JUSBLF
28)
27
2011/11/7a
change J3GTV to JPCIF
29)
37
2011/11/7a
change JFUNCTION to JFUN
30)
22
2011/11/7a
delete CH105, CH106; add QH2, CH97, CH98, RH1, RH3
31)
35
2011/11/7a
add EC pin 70 for PCH_PWR_EN
32)
37
2011/11/7b
by proto plan demand
change PCH version to SA00004NQ90(B0) and BOM option to SA00005AG10(C0)
33)
20
2011/11/7b
change net name from LNB_OC to LNB_OC#; add RH290 to pull high LNB_OC#
34)
37
2011/11/7b
by Layout team demand
delete H4, H8; modify H7, H22, H30 to NPTH
35)
20
2011/11/9a
EC common core for WL_OFF#
UH1.F46 and RH326 chagne net name from WL_OFF# to PCH_GPIO55
36)
35
2011/11/9a
change UB1.29 net name from CPSETIN to WL_OFF#
37)
27
2011/11/9a
add RM17 for WL_OFF# pull high to +3V_WLAN
38)
35
2011/11/9a
CPSETIN signal change from UB1.29 to UB1.74
39)
35
2011/11/9a
add RB37 10kohm pull high to +3VS for LNB_OC#
40)
13
2011/11/9d
for dual-channel power support
remove BOM selection IEDP@ for R109, R110, C230, C233, Q1
41)
13
2011/11/9d
change R108, C228, Q17 to LVDS@; change Q1, C230, C233, R109, R110 to always mount
42)
13
2011/11/9d
add R390, R1442, R1441, R106
43)
13
2011/11/9d
change R106 to LVDS@, R1441 to @, R361 to @, R1442 to 3D@, R390 to @
44)
13
2011/11/9d
for 3D panel camera
add R79, R97, L60
45)
13
2011/11/9d
add R361; change R62 from 100 to 0
46)
21
2011/11/9d
add RH304
47)
27
2011/11/14a
for vendor recommand
change YCL1 from SJ10000CU00 to SJ10000EF00, CCL4 and CCL5 from 30pF to 15pF
48)
29
2011/11/15a
by EMI demand
change CW10 from 6.8pF to 5pF
49)
27
2011/11/15d
by EMI demand
change BOM structure of CCL10 from @ to GCLK@
50)
28
2011/11/15d
by EMI demand
change BOM structure of RL29, CL43 from @ to GCLK@
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Custom
Date:
Rev
B
4019HF
Sheet
1
50
of
51
HW PIR (Product Improve Record)

----------------------------------------------------------------------------------------------------------------------------------Item
Page
Date
Request
Solution
----------------------------------------------------------------------------------------------------------------------------------1)
18
2011/11/29a
For DVT hang
Add CH23 CH24 CH25 for SW-node noise.
2)
13
2011/11/29a
For ME request
Change location from JLVDS to JLVDS4
3)
38
2011/11/29a
For noise issue
Add C366, C470 at +5VALW power rail; add C381 at +1.8VS power rail
4)
05
2011/12/07a
For leakage
Change from +3VALW to +3VALW_PCH of UC1
5)
38
2011/12/07a
For design change
Add C382 for +1.8VS
6)
33
2011/12/13a
For Codec leakage
Add RA29 for leakage
7)
18
2011/12/13a
For noise issue
Mount CH23,CH24,CH25.
8)
05
2011/12/13a
For leakage
Change pin5 of UC1 from +3VALW to +3VALW_PCH
9)
15
2011/12/13a
For leakage issue
Change pin5 of U9 from +5VL to +HDMI_5V_OUT
10)
38
2011/12/13a
For noise issue
Add C372,C373,C374,C383,C384,C385,C386,C387,C388,C389,C390,C391,C392
11)
35
2011/12/13a
For design change LNB_EN
Change LNB_EN from PCH to EC
12)
35
2011/12/13a
For design change RF LED
Change RF LED control pin from PCH to EC
13)
38
2011/12/13a
For S3 resume sequence
Add Q41 for S3 sequence
14)
26
2011/12/15a
For ME request
Change JFP/JPOWER/JFUN from zif to non-zif
15)
31
2011/12/15a
For adjust EXT 3.0 sequence
Change +3V to +3V_USB control pin from syson to PM_SLP_S4#
16)
32
2011/12/15a
For adjust EXT 3.0 sequence
Change +3V to +3V_USB control pin from syson to PM_SLP_S4#
17)
13
2011/12/17a
For Prevent LVDS burn issue
Add F3 (Poly fuse to prevent burn issue)
18)
37
2011/12/19a
For ME delete stand-off
Delete H25,H26,H27
19)
37
2011/12/19a
For Wimax flash issue
Change +5VS to +3VS of Wimax LED
20)
37
2011/12/19a
For layout request
Add net name +5VS_FUNC with Function conn power pin
21)
21
2011/12/22a
For ESD request
Reserve CH30(1000P) for PCH_THRMTRIP#
22)
13
2011/12/22a
For ME request
change C381, C382, C470, C366 from 0805 to 0603 size

----------------------------------------------------------------------------------------------------------------------------------Item
Page
Date
Request
Solution
----------------------------------------------------------------------------------------------------------------------------------1)
27
2012/01/12a
For GCLK
Add CCL13(0.1u) for +3VALW
2)
27
2012/01/12a
For MSATA pin define.
Add RM30 (MSATA define that Pin22 is reserve, so other function need to add PLT_RST#).
3)
27
2012/01/18a
For GLCK
Change CCL13 from +3VLAW to +3VALW_GCLK
4)
27
2012/01/30a
For TV tuner use PCIE interface
Add RM31~RM35 and QM2
5)
17
2012/01/30a
Change PCIE 6 from USB to TV tuner
6)
17
2012/01/30a
Change CLK_USB30 to CLK_TV and CLKREQ_USB30# to CLKREQ_TV#
7)
37
2012/01/30a
For MP
Unmount SW3
8)
11
2012/01/30a
For M1 only
Unmount RC117/RC118/QC7/QC8
9)
32
2012/01/30a
For Internal USB30 only
Delete Page 32
10)
37
2012/02/01a
For ESD request
Add C469, C472~C479, C481~C488, C491
Compal Secret Data
2011/12/14
Issued Date
Deciphered Date
2012/12/31
Title
Custom
Date:
Rev
B
4019HF
Sheet
1
51
of
51

1d04d Compal LA-8392P (Satellite P850 P855)

Transféré par

Informations du document

Description originale:

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

1d04d Compal LA-8392P (Satellite P850 P855)

Transféré par

Droits d'auteur :

Formats disponibles

A

LA-8392P REV 1.0 Schematic

Compal Electronics, Inc.

Compal Secret Data

Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2

1.5V DDRIII 1066/1333/1600 MT/s

USB20 port 2,3

USB20 port 0,1

SATA Gen3 port 1

SATA Gen3 port 0

DC/DC Interface CKT.

Power Circuit DC/DC

Power On/Off CKT.

Compal Electronics, Inc.

Compal Secret Data

DESIGN CURRENT 0.1A

DESIGN CURRENT 0.1A

DESIGN CURRENT 11A

DESIGN CURRENT 1.8A

DESIGN CURRENT 6.5A

DESIGN CURRENT 0.1A

DESIGN CURRENT 0.4A

DESIGN CURRENT 0.3A

DESIGN CURRENT 1.6A

Ipeak=6A, Imax=4.2A, Iocp min=8A DESIGN CURRENT 13.5A

DESIGN CURRENT 1.5A

DESIGN CURRENT 0.3A

DESIGN CURRENT 7.5A

DESIGN CURRENT 0.1A

Ipeak=6A, Imax=4.A, Iocp min=8

Imax=0.3A, Iocp min=0.8A

DESIGN CURRENT 94A

DESIGN CURRENT 50A

DESIGN CURRENT 15A

Ipeak=14A, Imax=9.8A, Iocp min=16.92A

Compal Electronics, Inc.

Compal Secret Data

Thursday, February 16, 2012

BTO Option Table

Internal Display Port

Internal Display Port

S5 S4/ Battery only

description SPI ROM

Camera & Mic

Camera & Mic

Camera & Mic

SLP_S3# SLP_S4# SLP_S5#

PCH SM Bus Address

MINI PCI-E SLOT

Compal Electronics, Inc.

Compal Secret Data

Thursday, February 16, 2012

Stuff R41 and R42 if do not support eDP

RC1571 LVDS@ 2 1K_0402_5%

RC1581 LVDS@ 2 1K_0402_5%

DDR3 Compensation Signals

Please place near JCPU

by ESD requestion and place near CPU

Layout request for test point

JTAG & BPM

FAN Control Circuit

Buffered Reset to CPU

Add C5 for ESD request 02/01