use IEEE.std_logic_1164.

all;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_unsigned.all;
entity afficheur is
port(j:in std_logic_vector(3 downto 0);
a: out std_logic_vector(6 downto 0));
end afficheur;
architecture arch of afficheur is
begin
process(j)
begin
case j is
when "0000" => a<="1000000";
when "0001" => a<="1111001";
when "0010" => a<="0100100";
when "0011" => a<="0110000";
when "0100" => a<="0011001";
when "0101" => a<="0010010";
when "0110" => a<="0000010";
when "0111" => a<="1111000";
when "1000" => a<="0000000";
when "1001" => a<="0010000";
when others => a<="0000110" ;
end case;
end process;
end arch;