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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_std_logic_vector.ALL;
entity booth_multiplier8 is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
prod : out STD_LOGIC_VECTOR (15 downto 0));
end booth_multiplier8;
architecture Behavioral of booth_multiplier8 is
component full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end component;
component half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end component;
component new_full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end component new_full_adder;
component new_half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
diff : out STD_LOGIC;
borrow : out STD_LOGIC);
end component;
type row is array (8 downto 0) of std_logic_vector(8 downto 0);
signal p : row;
signal pp0,pp1,pp2,pp3 : std_logic_vector (8 downto 0):= (others=>'0');
signal sig_mcd: std_logic_vector(8 downto 0):= (others=>'0');
signal sig_minusA : std_logic_vector(8 downto 0):= (others=>'0');
signal sig_twiceA: std_logic_vector(8 downto 0):= (others=>'0');
signal sig_twice_minusA :std_logic_vector(8 downto 0):= (others=>'0');
signal s0,c0:std_logic_vector(4 downto 0):= (others=>'0');
signal s1,c1:std_logic_vector(8 downto 0):= (others=>'0');
signal s2,c2:std_logic_vector(12 downto 0):= (others=>'0');
signal s1_0,s1_1,s1_2,c1_2,s1_3,c1_3,s2_0,s2_1,c1_0,c1_1,c2_0,c2_1,s2_2,c2_2,s2_
3,c2_3:std_logic_vector(8 downto 0):= (others=>'0');
signal c2_4,c2_5,s2_4,s2_5:std_logic_vector(10 downto 0):= (others=>'0');
begin

process(A,B)
variable D : std_logic_vector(8 downto 0):= (others=>'0');
variable mcd: std_logic_vector(8 downto 0):= (others=>'0');
variable minusA : std_logic_vector(8 downto 0):= (others=>'0');
variable twiceA: std_logic_vector(8 downto 0):= (others=>'0');
variable twice_minusA :std_logic_vector(8 downto 0):= (others=>'0');
variable minusA4 : std_logic_vector(7 downto 0):= (others=>'0');
begin
D :=B&'0';
minusA4:=std_logic_vector((unsigned(not A)+1));
if A="10000000" then
minusA:="010000000";
else
minusA:=minusA4(7)&minusA4;
end if;
mcd:= A(7)&A;
twiceA:=std_logic_vector(A)&'0';
twice_minusA:=minusA(7 downto 0)& '0';
sig_mcd<=mcd;
sig_minusA<=minusA;
sig_twiceA<=twiceA;
sig_twice_minusA<=twice_minusA;
for i in 0 to 3 loop
if D(2+2*i downto 0+2*i)="001" or
p(2*i)<=mcd ;
elsif D(2+2*i downto 0+2*i)="011"
p(2*i)<=twiceA;
elsif D(2+2*i downto 0+2*i)="100"
p(2*i)<=twice_minusA;
elsif D(2+2*i downto 0+2*i)="101"

D(2+2*i downto 0+2*i)="010" then


then
then
or D(2+2*i downto 0+2*i)="110" then

p(2*i)<=minusA ;
else
p(2*i)<=(others=>'0');
end if;
end loop;
end process;
pp0<=p(0);
pp1<=p(2);
pp2<=p(4);
pp3<=p(6);
ha1:half_adder
fa2:full_adder
fa3:full_adder
ha4:half_adder
ha5:half_adder

port
port
port
port
port

map(p(6)(0),p(4)(2),s0(0),c0(0));
map(p(6)(1),p(4)(3),p(2)(5),s0(1),c0(1));
map(p(6)(2),p(4)(4),p(2)(6),s0(2),c0(2));
map(p(6)(3),p(4)(5),s0(3),c0(3));
map(p(6)(4),p(4)(6),s0(4),c0(4));

----------------------------------------------------------------------------------------ha1_0:half_adder port map(p(4)(0),p(2)(2),s1(0),c1(0));


fa1_1:full_adder port map(p(4)(1),p(2)(3),p(0)(5),s1(1),c1(1));

fa1_2:full_adder port map(s0(0),p(2)(4),p(0)(6),s1(2),c1(2));


fa1_3:full_adder port map(c0(0),s0(1),p(0)(7),s1(3),c1(3));
fa1_4:new_full_adder port map(p(0)(8),s0(2),c0(1),s1_1(4),c1_1(4));
fa1_5:full_adder port map(s0(3),c0(2),p(2)(7),s1(5),c1(5));
fa1_6:new_full_adder port map(p(2)(8),s0(4),c0(3),s1_3(6),c1_3(6));
fa1_7:full_adder port map(c0(4),p(4)(7),p(6)(5),s1(7),c1(7));
ha1_8:new_half_adder port map(p(4)(8),p(6)(6),s1(8),c1(8));
---------------------------------------------------ha2_0:half_adder port map(p(0)(2),p(2)(0),s2(0),c2(0));
fa2_1:full_adder port map(p(0)(3),p(2)(1),c2(0),s2(1),c2(1));
fa2_2:full_adder port map(s1(0),p(0)(4),c2(1),s2(2),c2(2));
fa2_3:full_adder port map(c1(0),s1(1),c2(2),s2(3),c2(3));
fa2_4:full_adder port map(c1(1),s1(2),c2(3),s2(4),c2(4));
fa2_5:full_adder port map(c1(2),s1(3),c2(4),s2(5),c2(5));
nfa2_6:new_full_adder port map(s1(4),c1(3),c2(5),s2_0(6),c2_0(6));
fa2_6:full_adder port map(s1(4),c1(3),c2(5),s2_1(6),c2_1(6));
fa2_7:full_adder port map(c1(4),s1(5),c2(6),s2(7),c2(7));
nfa2_8:new_full_adder port map(s1(6),c1(5),c2(7),s2_2(8),c2_2(8));
fa2_8:full_adder port map(s1(6),c1(5),c2(7),s2_3(8),c2_3(8));
fa2_9:full_adder port map(c1(6),s1(7),c2(8),s2(9),c2(9));
nfa2_10:new_full_adder port map(s1(8),c1(7),c2(9),s2_4(10),c2_4(10));
fa2_10:full_adder port map(s1(8),c1(7),c2(9),s2_5(10),c2_5(10));
fa2_11:full_adder port map(c1(8),p(6)(7),c2(10),s2(11),c2(11));
nha2_12:new_half_adder port map(p(6)(8),c2(11),s2(12),c2(12));

process(c0(1),s0(2),c0(3),s0(4),p(6)(6),s2_0,c2_0,s2_1,c2_1,s2_2,c2_2,s2_3,c2_3,
s2_4,c2_4,s2_5,c2_5)
begin
if c0(1)='0' and s0(2)='0' then
s2(6)<=s2_0(6);
c2(6)<=c2_0(6);
else
s2(6)<=s2_1(6);
c2(6)<=c2_1(6);
end if;
if c0(3)='0'and s0(4)='0' then
s2(8)<=s2_2(8);
c2(8)<=c2_2(8);
else
s2(8)<=s2_3(8);
c2(8)<=c2_3(8);
end if;
if p(6)(6)='0' then
s2(10)<=s2_4(10);

c2(10)<=c2_4(10);
else
s2(10)<=s2_5(10);
c2(10)<=c2_5(10);
end if;
end process;
prod(14 downto 2)<=s2(12 downto 0);
prod(15)<=s2(12);
prod(1 downto 0)<= p(0)(1 downto 0);
end Behavioral;