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7/7/2015

6850AsynchronousCommunicationsInterfaceAdapter

AsynchronousCommunicationsInterface
Adapter(ACIA)

The ACIA contains almost all the logic required to set up an asynchronous data link between a
computer and an external system. A simplified and complete block diagram of the 6850 ACIA
is illustrated below:

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6850AsynchronousCommunicationsInterfaceAdapter

The Internal Registers of the 6850 ACIA


The hardware model may be divided into three sections the processor side, the receiver
side and the transmitter side.

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6850AsynchronousCommunicationsInterfaceAdapter

The 6850 ACIA


As far as the CPU is concerned, the 6850 behaves almost exactly like static memory. The
important difference is that the 6850's memory accesses are synchronised to an external E
clock. The timing of synchronous memory transfers to/from the 6850 ACIA can be seen
below.
Operation of the ACIA
The software model of the 6850 ACIA has four useraccessible registers, as shown below:

RegisterSelection Scheme of the 6850 ACIA


These registers are transmit data register (TDR), receive data register (RDR), system control
register (CR) and a system status register (SR). Note that there are four registers, but only
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6850AsynchronousCommunicationsInterfaceAdapter

one registerselect input RS, which can distinguish between only two registers. The 6850 uses
the R/!W signal to distinguish between the four this is possible because two registers are
read only and two are write only.
Full details of the 6850 ACIA are available, if required.

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