Differential Amplifiers:

Second Stage
Dr. Paul Hasler

Differential Transistor Pairs

MOSFET Diff-Pair

BJT Diff-Pair

The bottom transistor (the one with Ibias) sets the total current
The upper two transistors compete for a fraction of this current

BJT Differential Pair Analysis

Analysis of Diff-Pair

Source of Common-Mode Gain

Differential Pair Currents

3

Output current
(nA)

2.5

Iout-

Iout+

1.5

0.5

0
-0.4

-0.3

-0.2

-0.1

0.1

Differential input
voltage (V)

0.2

0.3

0.4

Above VT MOSFET Large-Signal

Above VT MOSFET Large-Signal

Start with 2 equations

2i 1/2 2iD2 1/2

vIDvGS1vGS2 D1

ISSiD1iD2

Above VT MOSFET Large-Signal

Start with 2 equations

2i 1/2 2iD2 1/2

vIDvGS1vGS2 D1

ISSiD1iD2

Above VT MOSFET Large-Signal

Start with 2 equations

2i 1/2 2iD2 1/2

vIDvGS1vGS2 D1

ISSiD1iD2

ISS ISS v2ID 2v4ID 1/2

iD1 2 2 I
SS 4I2
SS

ISS ISS v2ID 2v4ID 1/2

iD2 2 2 I 2
SS 4I
SS

Above VT MOSFET Large-Signal

Start with 2 equations

2i 1/2 2iD2 1/2

vIDvGS1vGS2 D1

ISSiD1iD2

ISS ISS v2ID 2v4ID 1/2

iD1 2 2 I
SS 4I2
SS

ISS ISS v2ID 2v4ID 1/2

iD2 2 2 I 2
SS 4I
SS

K'1ISSW1 1/2
4L1

gmiD1/vID(VID0)(ISS/4)1/2

Above VT MOSFET Large-Signal

Start with 2 equations

2i 1/2 2iD2 1/2

vIDvGS1vGS2 D1

ISSiD1iD2

ISS ISS v2ID 2v4ID 1/2

iD1 2 2 I
SS 4I2
SS

ISS ISS v2ID 2v4ID 1/2

iD2 2 2 I 2
SS 4I
SS

K'1ISSW1 1/2
4L1

gmiD1/vID(VID0)(ISS/4)1/2

Gain Changes with Bias Current

Common-Mode Input Range

Maximum: Q1 in Forward-active

Minimum: Q3 in Forward-active

MOS Common-Mode Input Range

Maximum: M1 in Saturation

Minimum: M3 in Saturation

vic(max)=VDD0.5ISSRDvDS1(sat)+VGS1
=VDD0.5ISSRD+VT1

vic(min)=VSS+vDS3(sat)+VGS1

Micro-Surgery

Small Signal: BJT Diff-Pair

Common-Mode Circuit

Common-Mode Circuit

An emitter-degenerated amplifier
Gain ~ - Rc / (2 REE)

MOS Common-Mode Circuit

MOS Common-Mode Circuit

An emitter-degenerated amplifier
Gain ~ - RD / (2 Rss)

Differential-Mode Gain

Differential-Mode Gain

Gain = - gm Rc

CMRR ~ - 2 gm RE
~ - 2 (IEE/ 2 UT) RE

MOS Differential Mode Circuit

MOS Differential Mode Circuit

Gain = - gm RD

CMRR ~ - gm Rss
~ - (Iss/ ( Vgs - VT) ) Rss

Mismatch in Transistor Circuits

Objective
Theobjectiveofthispresentationis:
1.)Illustratethemethodofanalyzingmismatches
2.)Analyzetheinputcurrentandvoltageoffsetsfordifferentialamplifiers
Outline
Thegeneralapproachtoanalyzingmismatches
InputvoltageandcurrentoffsetsofBJTdifferentialamplifiers
InputvoltageoffsetsofMOSdifferentialamplifiers

BJT Mismatch Modeling

Mismatch Modeling in MOS

BJT Mismatch Modeling

Differential Amplifiers II
Review of Basic Differential Pairs
Above Threshold Differential Amplifiers
Small-Signal Analysis: Differential and
Common mode circuits
Modeling of Mismatch