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General Description
The ABT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
Features
Y
Y
Y
Y
Y
Y
Commercial
Military
Package
Number
Package Description
20-Lead (0.300 Wide) Molded Small Outline, JEDEC
74ABT373CSC (Note 1)
M20B
74ABT373CSJ (Note 1)
M20D
74ABT373CPC
N20B
54ABT373J/883
J20A
MSA20
54ABT373W/883
W20A
20-Lead Cerpack
54ABT373E/883
E20A
MTC20
74ABT373CMSA (Note 1)
74ABT373CMTC (Notes 1, 2)
Note 1: Devices also available in 13 reel. Use suffix e SCX, SJX, MSAX, and MTCX.
Note 2: Contact factory for package availability.
Connection Diagrams
Pin Assignment
for DIP, SOIC, SSOP and Flatpak
Pin Assignment
for LCC
Pin Names
D0 D7
LE
OE
O0 O7
Description
Data Inputs
Latch Enable Input
(Active HIGH)
Output Enable Input
(Active LOW)
TRI-STATE Latch
Outputs
TL/F/11547 2
TL/F/115471
TRI-STATE is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/11547
RRD-B30M115/Printed in U. S. A.
September 1995
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