Laws and Theorems of Boolean Algebra

Operations with 0 and 1:

1. X  0  X
2. X  1  1

1D. X 1  X
2D. X 0  0

Idempotent laws:
3. X  X  X

3D. X X  X

Involution law:
4. (X)  X
Laws of complementarity:
5. X  X  1

5D. X X  0

Commutative laws:
6. X  Y  Y  X

6D. XY  YX

Associative laws:
7. (X  Y )  Z  X  (Y  Z )
XYZ

7D. (XY)Z  X(YZ )  XYZ

Distributive laws:
8. X(Y  Z)  XY  XZ

8D. X  YZ  (X  Y )(X  Z )

Simplification theorems:
9. XY  XY  X
10. X  XY  X
11. (X  Y)Y  XY

9D. (X  Y)(X  Y)  X
10D. X(X  Y )  X
11D. XY  Y  X  Y

DeMorgans laws:
12. (X  Y  Z  . . .)  XY Z . . .

12D. (XYZ . . .)  X  Y  Z  . . .

Duality:
13. (X  Y  Z  . . .)D  XYZ . . .

13D. (XYZ . . .)D  X  Y  Z  . . .

Theorem for multiplying out and factoring:

14. (X  Y)(X  Z)  XZ  X Y
14D. XY  X Z  (X  Z )(X  Y )
Consensus theorem:
15. XY  YZ  XZ  XY  XZ

15D. (X  Y)(Y  Z)(X  Z)

 (X  Y ) (X  Z)

The Consensus Theorem

The consensus theorem is very useful in simplifying Boolean expressions. Given an
expression of the form XY  X
Z  YZ, the term YZ is redundant and can be eliminated to form the equivalent expression XY  X
Z.
The term that was eliminated is referred to as the consensus term. Given a pair
of terms for which a variable appears in one term and the complement of that variable in another, the consensus term is formed by multiplying the two original terms
together, leaving out the selected variable and its complement. For example, the
consensus of ab and a
c is bc; the consensus of abd and b
de
is (ad)(de
)  ade
. The
consensus of terms ab
d and a
bd
is 0.
The consensus theorem can be stated as follows:
XY  X
Z  YZ  XY  X
Z

Example

A
C
D  A
BD  BCD  ABC  ACD

First, we eliminate BCD as shown. (Why can it be eliminated?)

Now that BCD has been eliminated, it is no longer there, and it cannot be used
to eliminate another term. Checking all pairs of terms shows that no additional
terms can be eliminated by the consensus theorem.
Now we start over again:
A
C
D  A
BD  BCD  ABC  ACD

This time, we do not eliminate BCD; instead we eliminate two other terms by the
consensus theorem. After doing this, observe that BCD can no longer be eliminated. Note that the expression reduces to four terms if BCD is eliminated first, but
that it can be reduced to three terms if BCD is not eliminated.
Sometimes it is impossible to directly reduce an expression to a minimum number
of terms by simply eliminating terms. It may be necessary to first add a term using the
consensus theorem and then use the added term to eliminate other terms. For example,
consider the expression
F  ABCD  B
CDE  A
B
 BCE

If we compare every pair of terms to see if a consensus term can be formed, we find
that the only consensus terms are ACDE (from ABCD and B
CDE) and A
CE

(from A
B
and BCE
). Because neither of these consensus terms appears in the
original expression, we cannot directly eliminate any terms using the consensus theorem. However, if we first add the consensus term ACDE to F, we get
F  ABCD  B
CDE  A
B
 BCE
 ACDE
Then, we can eliminate ABCD and B
CDE using the consensus theorem, and F
reduces to
F  A
B
 BCE
 ACDE
The term ACDE is no longer redundant and cannot be eliminated from the final
expression.

In each case, multiply out to obtain a sum of products: (Simplify where possible.)
(a) (W  X
 Z
) (W
 Y
) (W
 X  Z
) (W  X
) (W  Y  Z)
(b) (A  B  C  D) (A
 B
 C  D
) (A
 C) (A  D) (B  C  D)

Factor to obtain a product of sums. (Simplify where possible.)

(a) BCD  C
D
 B
C
D  CD
(b) A
C
D
 ABD
 A
CD  B
D

3 Is the following distributive law valid? A BC  (A B)(A C) Prove your answer.

4 (a) Reduce to a minimum sum of products (three terms):

(X  W) (Y Z )  XW

(b) Reduce to a minimum sum of products (four terms):

(A BC)  BD  ACD
(c) Reduce to a minimum product of sums (three terms):
(A
 C
 D
) (A
 B  C
) (A  B  D) (A  C  D)

5 Simplify algebraically to a minimum sum of products (five terms):

(A  B
 C  E
) (A  B
 D
 E) (B
 C
 D
 E
)

6 Prove algebraically that the following equation is valid:

A
CD
E  A
B
D
 ABCE  ABD  A
B
D
 ABD  BCD
E

1 (a)

(W + X' + Z') (W' + Y') (W' + X + Z') (W + X') (W + Y + Z)

= (W + X') (W' + Y') (W' + X + Z') (W + Y + Z)
= (W + X') [W' + Y' (X + Z')] (W + Y + Z )
= [W + X' (Y + Z)] [W' + Y'(X + Z')] = WY' (X + Z') + W'X' (Y + Z) {Using (X + Y) (X' + Z) = X'Y +XZ with X=W}
= WY'X + WY'Z' + W'X'Y + W'X'Z

1 (b)

(A + B + C + D) (A' + B' + C + D') (A' + C) (A + D) (B + C + D)

= (B + C + D) (A' + C) (A + D) = (B + C + D) (A'D + AC) {Using (X + Y) (X' + Z) = X'Y + XZ with X = A}

= A'DB + A'DC + A'D + ABC + AC + ACD = A'D + AC
2 (a)

BCD + C'D' + B'C'D + CD

= CD + C'(D' + B'D) = (C' + D) [C + (D' + B'D)] {Using (X + Y) (X' + Z) = X'Y + XZ with X=C}
= (C' + D) [C + (D' + B') (D' + D)] = (C' + D) (C + D' + B')

2 (b)

A'C'D' + ABD' + A'CD + B'D

= D' (A'C' + AB) + D (A'C + B')
= D' [(A' + B) (A + C')] + D [(B' + A') (B' + C)] {Using XY + X'Z = (X' + Y) (X + Z) twice inside the brackets}
= [D + (A' + B) (A + C')] [D' + (B' + A') (B' + C)] {Using XY + X'Z = (X' + Y) (X + Z) with X = D}
= (D + A' + B) (D + A + C') (D' + B' + A') ( D' + B' + C) {Using the Distributive Law}

A BC = (A B) (A C) is not a valid distributive law. PROOF: Let A = 1, B = 1, C = 0.

LHS: A BC = 1 1 0 = 1 0 = 1. RHS: (A B) (A C) = (1 1) (1 0) = 0 1 = 0.

4 (a)

(X + W) (Y Z) + XW'
= (X + W) (YZ' + Y'Z) + XW'
= XYZ' + XY'Z + WYZ' + WY'Z + XW'
Using Consensus Theorem
WYZ' + WY'Z + XW'

4 (c)

4 (b) (A BC) + BD + ACD = A'BC + A(BC)' + BD +

ACD
= A'BC + A (B' + C') + BD + ACD
= A'BC + AB' + AC' + BD + ACD
= A'BC + AB' + AC' + AD + BD + ACD
(Add consensus term AD, eliminate ACD)
= A'BC + AB' + AC' + BD
(Remove consensus term AD)

(A' + C' + D') (A' + B + C') (A + B + D) (A + C + D)

= (A' + C' + D') (B + C' + D) (A' + B + C') (A + B + D) (A + C + D) Add consensus term

= (A' + B + C') (A + B + D)
= (A' + C' + D') (B + C' + D) (A + C + D) Removing consensus terms

(A + B' + C + E') (A + B' +D' + E) (B' + C' + D' + E') = [A + B' + (C + E') (D' + E)] (B' + C' + D' + E')
= (A + B' + D'E' + CE) (B' + C' + D' + E') = B' + (A + D'E' + CE) (C' + D' + E')
CD' {Add consensus term}
= B' + AC' + AD' + AE' + C'D'E' + D'E' + D'E' + CD'E = B' + AC' + AD' + AE' + CD' +CD'E + D'E'
= B' + AC' + AE' + CD' + D'E'

A'CD'E + A'B'D' + ABCE + ABD = A'B'D' + ABD + BCD'E

Proof: LHS: A'CD'E + BCD'E + A'B'D' + ABCE + ABD Add consensus term to left-hand side and use it to
eliminate two consensus terms
= BCD'E + A'B'D' + ABD
This yields the right-hand side.
LHS = RHS

7 Simplify each of the following expressions:

(a) KLMN
 K
L
MN  MN

(b) KL
M
 MN
 LM
N

(c) (K  L
)(K
 L
 N)(L
 M  N
)
(d) (K
 L  M
 N)(K
 M
 N  R)(K
 M
 N  R
)KM

8 Factor to obtain a product of sums:

(a) K
L
M  KM
N  KLM  LM
N

(b) KL  K
L
 L
M
N
 LMN

(c) KL  K
L
M  L
M
N  LM
N

(d) K
M
N  KL
N
 K
MN
 LN
(e) WXY  WX
Y  WYZ  XYZ

(four terms)
(four terms)
(four terms)
(four terms)
(three terms)

9 Multiply out to obtain a sum of products:

(a) (K
 M
 N)(K
 M)(L  M
 N
)(K
 L  M)(M  N) (three terms)
(b) (K
 L
 M
)(K  M  N
)(K  L)(K
 N)(K
 M  N)
(c) (K
 L
 M)(K  N
)(K
 L  N
)(K  L)(K  M  N
)
(d) (K  L  M)(K
 L
 N
)(K
 L
 M
)(K  L  N)
(e) (K  L  M)(K  M  N)(K
 L
 M
)(K
 M
 N
)

10 Eliminate the exclusive-OR, and then factor to obtain a minimum product of sums:
(a) (KL M)  M
N

(b) M
(K N
)  MN  K
N

7 (a) KLMN' + K'L'MN + MN' = K'L'MN + MN' = M(K'L'N + N') = M(N' + K'L') {Th. 11C with Y = N'} = MN' + K'L'M
7 (b) KL'M' + MN' + LM'N' = KL'M' + N'(M + LM') = KL'M' + N'(M + L) = KL'M' + MN' + LN'
7 (c) (K + L') (K' + L' + N) (L' + M + N') = L' + K (K' + N) (M + N') = L' + KN (M + N') = L' + KMN
7 (d) (K' + L + M' + N) (K' + M' + N + E) (K' +M' + N + E') KM
= [K' + M' + (L + N) (N + R) (N + R')] KM {Th. 8N twice with X = K' + M'} = [K' + M' + (L + N)N] KM
= [K' + M' + N] KM = KMN
8 (a)

K'L'M + KM'N + KLM + LM'N' = M' (KN + LN') + M (K'L' + KL)

= M' [(K + N') (L + N)] + M [(K' + L) (K + L')] {Th. 14 twice with X = N and X = L}
= [M + (K + N') (L + N) ] [M' + (K' + L) (K + L')] {Th. 14 with X = M}
= (M + K + N') (M + L + N) (M' + K' + L) (M' + K + L') {Distributive Law}

8(b)

KL + K'L' + L'M'N' + LMN' = L' (K' + M'N') + L (K + MN')

= (L + K' + M'N') (L' + K + MN') {Th. 14 with X = L}
= (L + K' + M') (L + K' + N') (L' + K + M) (L' + K + N')
KL + K'L'M + L'M'N + LM'N' = L' [K'M + M'N] + L [K + M'N'] = L' [(M + N) (M' + K')] + L [(K + M') (K + N')]
= [L + (M + N) (M' + K')][L' + (K + M') (K + N')] = (L + M + N) (L + M' + K') (L' + K + M') (L' + K + N')

8(c)

8(d) K'M'N + KL'N' + K'MN' + LN = N (K'M' + L) + N' (KL' + K'M) = N ( L + K') (L + M') + N' (L' + K') (K + M)
= [N' + (L + K') (L + M')] [N + (L' + K') (K + M)] = (N' + L + K') (N' + L + M') (N + L' + K') (N + K + M)
8(e) WXY + WX'Y + WYZ + XYZ' = WY (X + X' + Z) + XYZ' = WY + XYZ' = Y (W + XZ') = Y (W + X) (W + Z')
9 (a)

(K' + M' + N) (K' + M) (L + M' + N') (K' + L + M) (M + N)

= (M' + NL + K'N') (M + K'N) = M (LN + K'N') + (M'K'N) {Using XY + X'Z = (X + Z)(X' + Y) with X = M}
= MLN + MK'N' + M'K'N

9 (b)

(K' + L' + M') (K + M + N') (K + L) (K' + N) (K' + M + N)

= [K' + N (L' + M')] [K + L ( M + N')] = KN (L' + M') + K'L (M + N') = KNL' + KNM' + K'LM + K'LN'

9(c)

(K' + L' + M) (K + N') (K' + L + N') (K + L) (K + M + N')

= [K' + (L' + M) ( L + N')] (K + LN') = (K' + LM + L'N') (K + LN') {Th. 14 with X = L}
= K (LM + L'N') + K'LN' {By Th. 14 with X = K}
= KLM + KL'N' + K'LN'

9(d)

(K + L + M) (K' + L' + N') (K' + L' + M') (K + L + N) = ( K + L + MN) (K' + L' + M'N')
= K ( L' + M'N') + K'( L + MN) {Th. 14 with X = K} = KL' + KM'N' + K'L + K'MN

9 (e)

(K + L + M) (K + M + N) (K' + L' + M') (K' + M' + N') = (K + M + LN) (K' + M' + L'N')
= K(M' + L'N') + K'(M + LN) = KM' + KL'N' + K'M + K'LN
Alt. soln's: KM' + K'M + L'MN' + LM'N (or) KM' + K'M + K'LN + L'MN' (or) KM' + K'M + KL'N' + LM'N

10 (a)

(KL M) + M'N' = (KL)'M + KLM' + M'N' = (K' + L') M + KLM' + M'N' = M(K' + L') + M'(KL + N')
= (M' + K' + L') ( M + N' + KL) = (M' + K' + L') (M + N' + K) (M + N' + L)

10 (b)

M'(K N') + MN + K'N = M' [K'N' + KN] + MN + K'N = K'M'N' + KM'N + MN + K'N
= K'M'N' + N(M + KM' + K')
= K'M'N' + N(M + K' + M') = K'M'N' + N = N + K'M' = (K' + N)(M' + N)

11 (a) Implement a full subtracter using a minimum number of gates.

(b) Compare the logic equations for the full adder and full subtracter. What is the
relation between si and di? Between ci1 and bi1?

12 A combinational logic circuit has four inputs (A, B, C, and D) and one output Z.
The output is 1 iff the input has three consecutive 0s or three consecutive 1s. For
example, if A  1, B  0, C  0, and D  0, then Z  1, but if A  0, B  1, C  0,
and D  0, then Z  0. Design the circuit using one four-input OR gate and four
three-input AND gates.

13 Design a combinational logic circuit which has one output Z and a 4-bit input
ABCD representing a binary number. Z should be 1 iff the input is at least 5, but is
no greater than 11. Use one OR gate (three inputs) and three AND gates (with no
more than three inputs each).

11 (a) difference, di = xi yi bi; bi+1 = bi xi' + xi'yi + bi yi

xi yi bi
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1

bi+1
0
1
1
1
0
0
0
1

di
0
1
1
0
1
0
0
1

11 (b) di = si; bi+1 is the same as ci+1 with xi replaced by xi'

12

13

AB CD

00 0 0

00 0 1

00 1 0

00 1 1

01 0 0

01 0 1

01 1 0

01 1 1

10 0 0

10 0 1

10 1 0

10 1 1

11 0 0

11 0 1

11 1 0

11 1 1

AB CD

00 0 0

00 0 1

00 1 0

00 1 1

01 0 0

01 0 1

01 1 0

01 1 1

10 0 0

10 0 1

10 1 0

10 1 1

11 0 0

11 0 1

11 1 0

11 1 1

Z = A'B'C'D' + A'B'C'D + AB'C'D'

+ ABCD' + ABCD + A'BCD
= A'B'C' + ABC + AB'C'D' +
A'BCD
= A'B'C' + ABC + AB'C'D' +
A'BCD + BCD + B'C'D'
(Added consensus terms) Z
= A'B'C' + ABC + BCD +
B'C'D'

A'
B'
C'
A
B
B
C

B'
C'
C
D'
D

Z = A'BC'D + A'BCD' + A'BCD +

AB'C'D' + AB'C'D + AB'CD'
+ AB'CD
= A'BD + AB'C' + AB'C + A'BCD' =
AB' + A'BD + A'BCD' + A'BC
(Added consensus terms)
Z = AB' + A'BD + A'BC

A'
B
C
A'
B
D
A
B'

14 Complete the following timing diagram for an S-R latch. Assume Q begins at 1.
S
R
Q

15 An AB latch operates as follows:If A  0 and B  0, the latch state isQ  0; if

either A  1 or B  1 (but not both), the latch output does not change; and when
both A  1 and B  1, the latch state is Q  1.
(a) Construct the state table and derive the characteristic equation for this AB latch.
(b) Derive a circuit for the AB latch that has four two-input NAND gates and two
inverters.
(c) In your circuit of Part (b), are there any transitions between input combinations
that might cause unreliable operation? Verify your answer.

(d) In your circuit of Part (b), is there a gate output that provides the signal Q
?
Verify your answer.
(e) Derive a circuit for the AB latch using four two-input NOR gates and two
inverters.
(f) Answer Parts (c) and (d) for your circuit of Part (e).

14

S
R
Q

15 (a)

Present
State
Q
0
1

AB
00
0
0

Next State Q+
AB
AB
11
01
0
1
1
1

15(b)

AB
10
0
1

A
B

Q+ = AB + QA + QB
Q+ = AB + Q(A + B)
15 (c)

A change between AB = 01 and 10 can cause Q to

change depending on the inverter delays.

15 (d) P = Q' + A'B' equals Q' in all stable states.

15(e)

A
B

15 (f) A change between AB = 01 and 10 can cause Q

to change depending on the inverter delays.
P = Q'(A' + B') equals Q' in all stable states.

P
Q+ = (AB + Q)(A + B)

16: Design a combinational logic circuit which has one output Z and a 4-bit

input ABCD representing a binary number. Z should be 1 if and only if

the input is at least 5, but is no greater than 11. Use one OR gate (three
inputs) and three AND gates (with no more than three inputs each).

17: Design a combinational circuit with three inputs and one output for the
following requirements:
(i) The output is 1 when the binary value of the inputs is less than 3. The
output is 0 otherwise.
(ii) The output is 1 when the binary value of the inputs is an odd number.

18: Draw the logic diagram of a fourbit binary ripple countdown

counter using:

(i) Flipflops that trigger on the positiveedge of the clock

(ii) Flipflops that trigger on the negativeedge of the clock.

19: Given a 64 8 ROM chip with an enable input, how the external

connections necessary to construct a 256 8 ROM with four chips and

a decoder.

16
AB CD
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1

Z
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0

Z = A'BC'D + A'BCD' + A'BCD +

AB'C'D' + AB'C'D + AB'CD'
+ AB'CD
= A'BD + AB'C' + AB'C
+ A'BCD' = AB' + A'BD
+ A'BCD' + A'BC
(Added consensus terms)
Z = AB' + A'BD + A'BC

A'
B
C
A'
B
D
A
B'

17
(1)
xyz

000
001
010
011
100
101
110
111

1
1
1
0
0
0
0
0

yz
x

00

0
x

m0

01

1
m4

11

m1

m3

10

x'
y'

m2

m5

m7

m6

x'
y'

z
F = x'y' + x'z'

(2)
xyz

000
001
010
011
100
101
110
111

0
1
0
0
0
0
0
0

yz
x

00

0
x

m0

01

11

m1

m3

1
m4

10

m2

m5

m7

1
z
F=z

z
m6

18
A0

Count

A1

A2

A3

A1

A2

Count

A0

A3

Logic 1
Reset

Reset
With T flip-flops

With D flip-flops

19
6
6
Address
(8 bits)

Data
(8 bits)

2x4
Decoder

En

En

En

En

64 x 8 ROM

64 x 8 ROM

64 x 8 ROM

64 x 8 ROM

20 Derive the state table and the state diagram of the sequential circuit shown in
Figure below. Explain the function that the circuit performs.

Present
state
Next
state

A counter with a repeated sequence of 00, 01, 10.

A B A B

FF
Inputs
T A TB

0
0
1
1

0
1
1
1

0
1
0
0

0
0
0
0

00

01

11

10

1
1
0
1

TA = A + B
TB = A' + B
Repeated sequence:
01 10
00