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University of California, Davis

Solid-State Circuits Research Laboratory


Dept. of Electrical and Computer Engineering

Michael Q. Le, Paul J. Hurst, and Kenneth C. Dyer

An Analog DFE for Disk Drives


Using a Mixed-Signal Integrator

Measured Results

Circuits

Mixed-Signal Integrator

DFE Background

Outline

1+

2t
PW50

-3T -2T -T 0

Precursor ISI

Received signal is a superposition of L(t )

L(t ) =

T 2T 3T

Postcursor ISI

Cursor

0 0 1 1 1 1 0 0

Lorentzian models isolated transition:

Read Voltage:

Magnetization:

Binary Data:

Read Signal

Read
Head
LPF

DFE

Feedback
Equalizer

Out

Analog equalizers save area and power over digital

Equalizers remove intersymbol interference (ISI)

Preamp
& AGC

Forward
Equalizer

Block Diagram of DFE Read Channel

c0

Input
(from FE)

c4
x

z -1

c1

Integrator
1/1000

c1

c2
z -1

z -1

c3

Quantizer

e[n] = error
_
+

x
z

-1

[n] = decision

[n] = sign(error)

Mixed-Signal DFE Architecture

[n][n-k]

[n][n-k]

[n][n-k]

up

6-bit
DAC

6-bit
DAC

4-bit Pre
Analog Integrator
Counter Borrow down

Carry

4-bit Pre
6-bit U/D
Borrow
Counter
Counter

Carry

10-bit U/D
Counter

Discrete-Time Integrators

ck

ck

ck

OR

Borrow

1
7
(freq U=1 or D=1) I off
(counter DC gain) 2I

Pre-counter DC gain =

Offset @ digital input

1 I off
7 2I

CH

Charge Pump

I2

I off t
I t
+ (U+D)
2CH
CH

4-b Pre-counter

reset

4-b U/D
Counter

ck [n+1] = ck [n] + (U-D)

[n][n-k]

Carry

I1

Mixed-Signal Integrator

ck

Iin
(from FE)

c0

Ifb

I2V

c4

c1

VRL

VRH

-1

c2

1
-1

z -1

c1

x
z -1

[n] = decision

[n] = error

Mixed-Signal Integrator

z -1

c3

_
+
_
+
_
+
2-bit Flash ADC

Analog DFE Architecture

NB

DB

I1

-C k

Current sources held in saturation by N/NB

Use gate-channel capacitance of PMOS transistors

Common-mode feedback controls I 2

VGG

+Ck

UB

Charge Pump

M1

Bias

Bias

+ A
- +

600

M2

Out-

In-

Negative feedback reduces input impedance

Transresistance of 600 set by load resistors

In+

Out+

600

Vdd

Current to Voltage Converter (I2V)

Bandlimited
Noise

Random
Binary Data

1-z
AWG

Forward
Equalizer

Clock Generator

Logic
Analyzer

Lorentzian
PW50 = 2T

Analog
DFE

-1

Test Setup

Normalized Input

1.5
0

0.5

0.5

1.5

500

Sample

1000

Equalized Slicer Input at 10Mb/s

1500

Bit-Error Rate

1e-12

1e-11

1e-10

1e-09

1e-08

1e-07

1e-06

1e-05

1e-04

1e-03

10

11

12

13
14
SNR at DFE Input (dB)

Measured at 150 Mb/s, PW50 = 2T

Measured at 100 Mb/s, PW50 = 2T

Ideal Slicer with no ISI

BER Performance

15

16

17

differential voltage (V)

differential voltage (V)


1
0

0.5

1
0

0.5

1
time (s)

1.5

0.5

1
time (s)

1.5

Coefficients with Pre-counters @ 150 Mb/s

0.5

Coefficients without Pre-counters @ 150 Mb/s

c2
c1

c0
c4
c3

c2
c1

c4
c0
c3

differential voltage (V)

differential voltage (V)


1
0

0.5

1
0

0.5

1
time (s)

1.5

6
time (s)

~1200T
8

10

Convergence with Pre-counters @ 150 Mb/s

0.5

~180T

Convergence without Pre-counters @ 150 Mb/s

12

c1

c2

c4
c3

c1

c2

c4
c3

1 m CMOS
1.8 mm 2
4 ISI + 1 DC offset
220 mW @ 150Mb/s
15.3 dB @ 100 Mb/s
16.0 dB @ 150 Mb/s

Technology
Core Area
Number of Taps
Power Dissipation
SNR required for
BER = 1 x 10 -8

Performance Summary (5V, 25 C, PW50 = 2T)