Interview Questions:

1) Draw waveform for the following code(a & b)

always @(posedge clk)
begin
a<=b;
b<=a;
end

initial
begin
a = 0;
b =1;
#100 $finish;
End

2) Draw waveform for the following code(a & b)

always @(posedge clk)
begin
a=b;
b=a;
end

initial
begin
a = 0;
b =1;
#100 $finish;
end

3) Draw a state diagram for the following

This is checker which checks the following rules and any of
the following fails it will enter a ERROR state
->after reset goes low A and B pulse can go high
->A and B cant go high at the same time
->there should be a A pulse in between 2 B pulses
->there should be a B pulse in between 2 A pulses
(there is no particular fixed delay between pulses)
->pulse should not be high for more than 1 clk pulse

4) Draw state diagram for the following sequence 11011101

(non-overlapping).

5) Find simplified equation for X and Y

6) Describe FULL signal of a asynchronous FIFO (async read and

write signals).
7) Find the minimum depth of the following FIFO
READ signal is clk frequency divided by 100
WRITE signal is clk frequency divided by 2
8) Write Verilog code for SIPO for the following architecture

Si: Serial In
Se: input enable
So: Serial output
Pe: output enable

9) Calculate the maximum clk frequency needed in terms of

a. Tsu
b. Thd
c. Wire delay(Wd)
d. C2Q delay
e. Q2D delay
f.