An Introduction to Synopsys

Design Automation
Jeremy Lee
jslee@engr.uconn.edu
November 7, 2007

Introduction
Why the need CAD tools?
Time to market decreasing (< a year)
Designs are becoming more complex
(System-on-a-chip)
Synopsys is one of many EDA
vendors vying for designer mindshare

Introduction (cont.)
Why do we (in academia) need CAD
tools?
Keep our research relevant to
industry
Know what needs improving
(academia on cutting edge)

What will be covered?

Overview of tools
Whats available?
What do the tools do?

Example Flow
Will not be a step-by-step how-to.

Getting Synopsys Started at UConn

Synopsys Linux binaries are available on the
ECS fileserver:
/apps/ecs-apps/software/synopsys
Releases: Y-2006, Z-2007
bashrc and cshrc files located at
/apps/ecs-apps/software/synopsys/etc
Synopsys directory can be mounted directly
using NFS
files:/ApplicationDirectories/nfs/ecsapps/software/synopsys
Tools are location dependent
Must be in same directory structure as on server

Gui or console modes

Synopsys Galaxy Platform at

UConn (Y-2006)

Design Automation

Design Compiler
JupiterXT
Astro
Physical Compiler

Sign-off /
Validation /
Verification
PrimeTime SI/PX/VX
PrimePower
Star-RCXT
Formality
VCS
Nanosim
HSpice

Design for Test

DFT Compiler
DFT MAX
TetraMAX

Design Automation
Design Compiler
RTL to gate-level synthesis

Physical Compiler
Layout-aware RTL to gate-level synthesis

JupiterXT
Floorplanning tool

Astro
Placement and routing

Design Compiler (DC)

Synthesizes gate level netlists from
RTL-level
Optimizes netlists
Removes unused or redundant logic
Tie-off nets that are constant

Requires standard cell library timing

characterization
Attempts to meet timing and area
constraints (SDC File)

Libraries
Supposed to be provided by fab
Gates in standard cell library
Operating condition corners
Gate delays

Wire load models

Compensates delay for fan-out

SDC File
Synopsys Design Constraints (SDC)
Set up clock period
Specifies timing and area
requirements that are to be met
during mapping and optimization

SDC Constraints
Input Delay
Output Delay

Driving Cell
Load

DC Flow
Libraries

Netlist

Read
Libraries

Read
Netlist

Map to
Link Library
(if gate-level)

SDC
Cons.

Apply
Constraints

Map to
Target Library
and Optimize
Write-out
Optimized
Netlist

JupiterXT
Floorplanning

Power/Ground Network Planning

Pin/Power pad placement
Blockages
Memory placement

Performed through GUI or command

line

Astro
Placement and routing tool
Requires physical information of
standard cell library (provided by fab)
Graphic Data System (GDSII)
Library Exchange Format (LEF)

Physical design in multiple formats

GSDII
Design Exchange Format (DEF)

Astro Flow
Libraries

Netlist

SDC
Cons.

Open
Libraries

Import
Netlist and
Constraints

Read/Setup
Floorplan

Run
Placement

Routing

Physical
Design

Synopsys Galaxy Platform at

UConn (Y-2006)

Design Automation

Design Compiler
JupiterXT
Astro
Physical Compiler

Sign-off /
Validation /
Verification
PrimeTime SI/PX/VX
PrimePower
Star-RCXT
Formality
VCS
Nanosim
HSpice

Design for Test

DFT Compiler
DFT MAX
TetraMAX

Sign-off/Validation/Verification
Formality
Verify netlist

PrimeTime SI/PX/VX
Timing validation (signal-integrity,
power-aware, variation-aware)

PrimePower
Power validation

Sign-off/Validation/Verification
(cont.)
Star-RCXT
Extraction tool

VCS
HDL simulator

NanoSim
HDL simulator w/ parasitics

HSpice
Spice simulator

PrimeTime SI/PX/VX (PT-SI/PX/VX)

Calculates and reports path delays
Verify operating frequency after logic
synthesis
Can be back-annotated with extracted
parasitics for post-layout verification

PT-SI/PX/VX Flow
Parasitics
Libraries

*New*

Read
Libraries

Back-annotate
design
Netlist

Read
Netlist

Map to
Link Library
(if gate-level)

SDC
Cons.

Process
Variation

Report
Timing results

Meet
spec?
Apply
Constraints

Yes
Next
phase

No

ECO

Putting the Pieces Together

Logic
Libraries

RTL

SDC

Netlist

Cons.

Physical
Libraries

Physical
Synthesis

Logic
Synthesis

Layout
Gate
Netlist

Extraction
Fails

Sign-off
Passes

Fails

Sign-off
Passes

To
Fab

Synopsys Galaxy Platform at

UConn (Y-2006)

Design Automation

Design Compiler
JupiterXT
Astro
Physical Compiler

Sign-off /
Validation /
Verification
PrimeTime SI/PX/VX
PrimePower
Star-RCXT
Formality
VCS
Nanosim
HSpice

Design for Test

DFT Compiler
DFT MAX
TetraMAX

Design for Test

DFT Compiler
Scan chain insertion

DFT Max
Test compression tool

TetraMax
Automatic test pattern generation
(ATPG)

Additional Reading
Synopsys Website
www.synopsys.com

Documentation
Synopsys OnLine Documenation (SOLD)
Available on any of the UConn ECS Linux
servers

Electronic Synopsys Users Group

(ESNUG)
www.deepchip.com