Apple Macbook Air A1304 (MLB M96)

8
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
SCHEM,MLB,M96
EVT
08/01/2008
DATE
DATE
D
(.csa)
Date
Page
Contents
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
Sync
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
(.csa)
Page
TABLE_TABLEOFCONTENTS_HEAD
N/A
Table of Contents
N/A
System Block Diagram
WFERRY-WF
Power Block Diagram
POWER
CONFIGURATION OPTIONS
05/11/2006
06/30/2005
(N/A)
N/A
(MASTER)
(N/A)
Acoustic Cap BOM Config Tables
N/A
Functional Test and No-Tests
(MASTER)
06/15/2006
Power Aliases
WFERRY
SIGNAL ALIAS /RESET
(MASTER)
(MASTER)
10
02/04/2008
CPU FSB
M97
11
CPU Power & Ground
(MASTER)
04/26/2006
02/04/2008
02/04/2008
02/04/2008
02/04/2008
(MASTER)
12
CPU Decoupling & VID
MSARWAR
eXtended Debug Port (XDP)
M97
13
14
MCP CPU Interface
M97
15
MCP Memory Interface
M97
MCP Memory Misc
M97
16
17
MCP PCIe Interfaces
02/04/2008
02/04/2008
02/04/2008
02/04/2008
02/04/2008
02/04/2008
02/04/2008
M97
18
MCP Ethernet & Graphics
M97
19
MCP PCI & LPC
M97
20
MCP SATA & USB
M97
21
MCP HDA & MISC
M97
22
MCP Power & Ground
M97
MCP Standard Decoupling
M97
25
26
MCP Graphics Support
M97
SB Misc
M97
28
29
FSB/DDR3 Vref Margining
02/04/2008
02/04/2008
01/15/2008
01/30/2008
(MASTER)
BEN
30
DDR3 Support
T18_MLB
31
DDR3 DRAM Channel A (0-31)
(MASTER)
32

33
(MASTER)
DDR3 DRAM Channel B (0-31)
(MASTER)
34

35
06/20/2005
DDR BYPASSING 1
MEMORY
DDR BYPASSING 2
MEMORY
Memory Active Termination
M70
Wireless M93 Connector
M70
36
Date
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Contents
Sync
52
02/04/2008
M97 SMBUS CONNECTIONS
BEN
Voltage Sensors
M70
Current Sensing
YUNWU
TEMPERATURE SENSORS
M70
Fan
M70
Sudden Motion Sensor (SMS)
M76_MLB
SPI ROM
CHANGZHANG
DC-In & Battery Connectors
M70
IMVP6 CPU VCore Regulator
POWER
MCP CORE REGULATOR
MINGJING
53
01/09/2007
54
02/04/2008
55
01/09/2007
56
01/09/2007
59
01/12/2007
61
02/15/2008
69
01/09/2007
71
07/13/2005
72
06/24/2008
73
1.8V LDO Supply

74
05/21/2008
1V05 S5 Power Supply
RXU_K20
1.5V/0.75V Supplies
M70
5V / 3.3V Power Supply
RXU_K20
POWER SEQUENCING
YUAN.MA
POWER FETS
YUAN.MA
PBUS Supply/Battery Charger
M70
LVDS,Camera Conn. and ALS Conn.
GPU
DISPLAYPORT SUPPORT
NMARTIN
DisplayPort Connector
M98_MLB
LED Backlight Driver
(MASTER)
LCD Backlight Support
M97
75
01/09/2007
76
05/21/2008
77
02/04/2008
78
02/04/2008
79
01/09/2007
90
06/23/2006
93
12/18/2007
94
01/17/2008
97
(MASTER)
98
02/04/2008
99
Additional CPU/GPU Decoupling

100
02/04/2008
CPU/FSB Constraints
M97
Memory Constraints
M97
MCP Constraints 1
M97
MCP Constraints 2
M97
SMC Constraints
M97
M96 Power and Ground Nets
(MASTER)
M96 RULE DEFINITIONS
M97
101
02/04/2008
102
02/04/2008
103
02/04/2008
106
02/04/2008
108
(MASTER)
109
02/04/2008
06/20/2005
37
01/09/2007
41
01/09/2007
42
(MASTER)
Hatch and Audio Connectors
(MASTER)
SATA Connectors
CHANGZHANG
USB EXTERNAL CONNECTORS
M70
45
02/05/2008
46
01/09/2007
48
IPD Connector
49
02/21/2008
SMC
M97
SMC SUPPORT
M70
LPC+SPI Debug Connector
CHANGZHANG
50
01/09/2007
51
01/24/2008
DIMENSIONS ARE IN MILLIMETERS
APPLE INC.
METRIC
XX
X.XX
DRAFTER
Schematic / PCB #s
PART NUMBER
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
QTY
ENG APPD
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
DESCRIPTION
REFERENCE DES
051-7631
SCHEM,MLB,M96
SCH
CRITICAL
CRITICAL
820-2375
PCBF,MLB,M96
PCB
CRITICAL
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
X.XXX
BOM OPTION
TITLE
DO NOT SCALE DRAWING
DRAWING
SIZE
TITLE=M96_MLB
ABBREV=DRAWING
LAST_MODIFIED=Fri Aug
SCHEM,MLB,M96
NONE
THIRD ANGLE PROJECTION
1 09:54:13 2008
MATERIAL/FINISH
NOTED AS
APPLICABLE
DRAWING NUMBER
REV.
051-7631
2.3.0
SHT
OF
71
D
U1000
CPU
1.6/1.8 GHz
J6900/80
Pg 10
J1300
Pg 11
DC/Batt
Power
Conn
Supplies
PG 51
PG 52-59
MINI XDP CONN

PG 12
FSB
64-Bit
J9000
TOP ALS
J4100
M93
PG 60
800 MHz
MEM Active
Parallel
FSB
J4200
Pg 14
HDMI
J9000
Pg 15/16
FLAT PANEL
PG 37
U3100
U3110
U3120
U3130
U3210
U3220
U3230
U3240
U1400
Main Memory
Display Port
Term
J4800
Pg 35
IPD
DDR3 - Dual Channel

0.75V - 64 Bits
DDR3 RAM
1066 MHz
LVDS
Pg 18
CPU/MCP T-Diode Thermal Sensor
U5515
PG 47
Local TEMP near power supplies
U5550
PG 47
Local TEMP near Air Vent
U5560
PG 47
Local TEMP near Front Edge
U5570
PG 47
PG 40
Pg29/30
LVDS Int Disp

Conn
PG 36
Misc
Pg 21
Camera
MCP79U
SUDDEN MOTION DETECT U5900
PG 60
PG 49
U3300
U3310
U3320
U3330
U3410
U3420
U3430
U3440
USB
Ln0
Pg 20
Core
VOLTAGE SENSORS
PCI-E
Pg31/32
SMB
Pg 17
BSA
MGMT
ADC
Fan
Ser
J5100
LPC
Pg 19
Prt
FrankCard Conn
U4900
PG 43
PG 41
U9500
NAND Flash
Flash
Controller
PG 64
SMC
Ln3
NAND
PG 48
DDR3 RAM
Pg 24
Ln2
U9600
U9601
J5600
Ln1
FAN CONN
PG 45
SATA
DACS
LAN
PCI
HDA
Pg20
Pg18
Pg18
Pg 19
Pg 21
SPI
Pg 21
PG 63
J4500
HDD SATA
U6100
Conn
Well Spring
SPI
J4200
J4800
Trackpad/Keyboard
PG 38
Boot ROM
PG 40
External
USB
PG 50
PG 37
J9050
DIGITAL MIC
J4100
CONNECTOR
M93 AirPort/BT
PG 60
Pg 36
J4260
Audio
Connector
Pg 37
System Block Diagram
SYNC_MASTER=WFERRY-WF
SYNC_DATE=05/11/2006

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
2
71
DC-JACK
M96 POWER SYSTEM ARCHITECTURE
01
6A FUSE
PP18V5_DCIN
D6901
PPDCIN_G3H_R
PP18V5_G3H_CHGR
02
PPDCIN_G3H
PPVBATT_G3H_R
J6980
PPBUSB_G3H
D6901
PPVIN_G3H_DCIN
04
SMC_RESET_L
03
3.425V G3HOT
LTC3470A
VIN
U6900
(PAGE 51)
SMBUS_SMC_BSA_SDA
7A FUSE
R7980
PPVBAT_G3H_CHGR_REG
SMC PWRGD
RN5VD30A-F
U5000
(PAGE 42)
ENABLE
SMBUS_SMC_BSA_SCL
ENABLES
PP3V42_G3H_SMC
D6901
F6900
PPBUSB_G3H
PP3V42_G3H_REG
DEBUG_RESET_L
LPC_RESET*
Q7853
SMC_LRESET_L
FC_RESET_L
PP1V05_S0_FET
PBUSA_G3H
VOUT
2S2P
BATTERY
ISL6258
U7900
PCA9557D_RESET_L
VIN
(0.002)
R7930
Q7950
42
AIRPORT_RST_L
02
P1V05S0_EN
26
(PAGE 59)
CHGR_BGATE
U1400
1.05V
10
P1V05_S5_EN
(S5)
ENA1
33
MCPCORES0_EN
(S0)
ENA2
BKLT_PLT_RST_L
MCP79U
11
Q5315
VIN
01
27
PCIE_RESET*
PBUS Supply/
BATTERY CHARGER
43
(200 mA MAX CURRENT)
PP1V05_S5_REG
(7 A MAX CURRENT)
VOUT1
MCPCORE
40
PPMCPCORE_S0_REG
VOUT2
MCP_PS_PWRGD
34
PS_PWRGD
PWRBTN*
(25 A MAX CURRENT)

RSMRST*
ISL6236
PG1
U7200
(PAGE 53)
BATT_POS_F
P1V05_S5_PGOOD
PG2
FSB_CPURST_L
12
MCPCORES0_PGOOD
CPU_RESET*
CPU_PWRGD
35
CPU_PWRGD
41
38
02
PPVCORE_S0_CPU_REG
CPUVCORE
PPVCORE_S0_CPU
VOUT
VIN
(30 A MAX CURRENT)
PP3V3_S5_PWRCTI
IMVP_VR_ON
R-100K
C-NoStuff
C
MCP79U
R-1K
C-0.47uF
39
VR_PWRGOOD_DELAY
ISL6261CRZ PGOOD
U7100
(PAGE 52)
37
16
P5VS3_EN_L
DELAY
15
VR_ON
DELAY
Q7710
VR_PWRGOOD_DELAY
MCPCORES0_PGOOD
26
22
=PPBUSB_G3H
25
04
SMC_ADAPTER_PRESENT
PP1V5_S0_VMON
IMVP_VR_ON
DDRREG_EN
SMC
SLP_S3*
PWRGOOD
19
DELAY
R-5.1K
C-0.47uF
CPU
PPBUSA_G3H
P3V3S3_EN
PM_SLP_S4_L
SLP_S5*
U2850
26
03
PP3V42_G3H_PWRCTL
U7770
LTC2909
ADJ1
FSB_CPURST_L
35
RESET*
P5V3V3_PGOOD
PP1V05_S0_VMON
U1000
(PAGE 10)
44
S0PGOOD_PWROK
ADJ2
RST*
ALL_SYS_PWRGD
(PAGE 57)
U4900
(PAGE 41)
DELAY
Q7700
P60
SMC_PM_G2_EN
PM_G2_P3V3S5_EN_L
PP3V3S5_EN_L
R-100K
C-NoStuff
WOW_EN
(S5)
08
PCI_RESET0*
DELAY
07
29
P1V05_S5_EN
SMC_PM_G2_EN
R-5.1K
C-0.47uF
26
10
PM_WLAN_EN_L
PP3V3_S5_PWRCTL
PM_SLP_S3_L
09
P3V3S0_EN
Q7840
PP5V_S0_FET
P5VS0_EN
28
26
PBUSVSENS_EN
02
P5VS0_EN_L 27
DELAY
R-0
C-0.47uF
P1V05S0_EN
(S0)
16
26
Q7621
P5VS3_EN_L
DELAY
R-5.1k
C-0.47uF
P1V8S0_EN
(S0)
VIN
3.3V
VO2
(S3)
08
26
09
DELAY
CPUVTTS0_EN
(S0)
SENSE
(? A MAX CURRENT)
13
PP3V3_S3
RSMRST_IN(P13)
RESET
20
P3V3S3_EN_L
P1V8_S0_EN
EN
PPVIN_S0_P1V8S0
1.8V S0
TPS19918
U7360
VIN
33
VOUT
(PAGE 54)
SMC_LRESET_L
SMC_RESET_L
PP1V8_S0_REG
(200 mA MAX)
RST*
32
15
15
28
Q7830
PM_PWRBTN_L
P17(BTN_OUT)
05
PLT_RST*
31
06
PWR_BUTTON(P90)
21
BATTERY ONLY:
18
37
(PAGE 57)
PGOOD1,2
36
IMVP_VR_ON
RSMRST_PWRGD
RSMRST_PWRGD
MR
99ms DLY
IMVP_VR_ON(P16)
SMC_ONOFF_L
DELAY
MCPCORES0_EN
(S0)
PWRGD(P12)
PM_RSMRST_L
RSMRST_OUT(P15)
U7740
TPS19918
PP1V5_S5_PGOOD
12
Q7810
P5V3V3_PGOOD
R-22k
C-0,47uF
P3V3_S5_PWRCTL
PP3V3_S5
TPS51120
U7600
(PAGE 60)
SMC
ALL_SYS_PWRGD
(S5)
MCPDDR_EN
(S0)
14
22
PP5V_S3
09
PP3V3_S5_REG
PP3V3S5_EN_L
EN2
R-33k
C-0.47uF
VO1
31
DELAY
R-0
C-0.47uF
5V
EN1
17
PP5V_S3_REG
(? A MAX CURRENT)
PM_SLP_S5_L
SLP_S5_L(P95)
PM_SLP_S4_L
SLP_S4_L(P94)
PM_SLP_S3_L
SLP_S3_L(P93)
24
PP3V3_S0_FET
U4900
(PAGE 41)
P3V3S0_EN_L
27
Q7801
Power Block Diagram
27
=PP1V5_S0_FET
PP1V5_S3_P1V5S0FET
SYNC_MASTER=POWER
PP0V75_S3_VTTREF

MCPDDR_EN
22
26
VIN
VLDOIN
1.5V
DDRREG_EN
S5
MEM_VTT_EN_R
R2870
DDRVTT_EN

S3
VOUT1
23
PP1V5_S3_REG
(11 A MAX CURRENT)

0.75V
VOUT2
PP0V75_S0_REG
30
29
TPS51116
U7500
(PAGE 55)
SIZE
DRAWING NUMBER
D
DDRREG_PGOOD
APPLE INC.
24
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
3
71
PAGE_BORDER=TRUE
BOMs
BOMOPTION Groups
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
M96_COMMON
ALTERNATE,COMMON,M96_COMMON1,M96_COMMON2,M96_COMMON3
M96_COMMON1
MCP_B02,BOOTROM_DEVEL,SMC_PRGRM,BOOT_MODE_USER,JTAG_ALLDEV,MEMRESET_HW,MEMRESET_MCP,VREFMRGN
M96_COMMON2
LPCPLUS,XDP,XDP_CONN
M96_COMMON3
MCP_CS1_NO
M96_HYNIX
DRAM_HYNIX
M96_MICRON
DRAM_MICRON,DRAM_SPD_2
TABLE_BOMGROUP_ITEM
630-9734
PCBA,MLB,1.6GHZ,HY 2GB,SS CAP,M96
EEE_4DA,M96_COMMON,M96_HYNIX,M96_SS_CAP,CPU_1_6GHZ
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
630-9735
PCBA,MLB,1.6GHZ,HY 2GB,MU CAP,M96
EEE_4DB,M96_COMMON,M96_HYNIX,M96_MU_CAP,CPU_1_6GHZ
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
630-9514
PCBA,MLB,1.6GHZ,HY 2GB,TY CAP,M96
EEE_2AL,M96_COMMON,M96_HYNIX,M96_TY_CAP,CPU_1_6GHZ
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
630-9738
PCBA,MLB,1.8GHZ,HY 2GB,SS CAP,M96
EEE_4DC,M96_COMMON,M96_HYNIX,M96_SS_CAP,CPU_1_8GHZ
630-9516
PCBA,MLB,1.8GHZ,HY 2GB,MU CAP,M96
EEE_2AN,M96_COMMON,M96_HYNIX,M96_MU_CAP,CPU_1_8GHZ
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
630-9517
PCBA,MLB,1.8GHZ,HY 2GB,TY CAP,M96
EEE_2AP,M96_COMMON,M96_HYNIX,M96_TY_CAP,CPU_1_8GHZ
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
M96_SS_CAP
SS_CAP_2_2UF,SS_CAP_10UF,SS_CAP_1UF
M96_MU_CAP
MU_CAP_2_2UF,MU_CAP_10UF,MU_CAP_1UF
M96_TY_CAP
TY_CAP_2_2UF,TY_CAP_10UF,TY_CAP_1UF
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Module Parts
PART NUMBER
Bar Code Label / EEE #s

PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:4DA]
CRITICAL
EEE_4DA
826-4393
[EEE:4DB]
CRITICAL
EEE_4DB
826-4393
[EEE:2AL]
CRITICAL
EEE_2AL
826-4393
[EEE:4DC]
CRITICAL
EEE_4DC
826-4393
[EEE:2AN]
CRITICAL
EEE_2AN
826-4393
[EEE:2AP]
CRITICAL
EEE_2AP
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
337S3658
IC,PDC,QS,1.60GHZ,17W,1066,6M
U1000
CRITICAL
BOM OPTION
CPU_1_6GHZ
337S3659
IC,PDC,QS,1.80GHZ,17W,1066,6M
U1000
CRITICAL
CPU_1_8GHZ
338S0604
IC,GMCP,MCP79U-A01Q,27MMX27MM,BGA1588
U1400
CRITICAL
MCP_A01Q
338S0601
IC,GMCP,MCP79U-B01,27MMX27MM,BGA1588
U1400
CRITICAL
MCP_B01
338S0637
IC,GMCP,MCP79U-B02,27MMX27MM,BGA1588
U1400
CRITICAL
MCP_B02
335S0615
IC, 32MBIT 8-PIN SERIAL FLASH, WSON8
U6100
CRITICAL
BOOTROM_BLANK_4MB
341S2382
IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M96
U6100
CRITICAL
BOOTROM_DEVEL
341S2326
IC,EFI,BOOTROM FINAL (LOCKED),M96
U6100
CRITICAL
BOOTROM_FINAL
338S0563
IC,SMC,HS8/2117
U4900
CRITICAL
SMC_BLANK
341S2327
IC,PRGRM,SMC (NEW),M96
U4900
CRITICAL
SMC_PRGRM
333S0476
HYNIX,DDR3,128M16,9x11.5
U3100,U3110,U3120,U3130
CRITICAL
DRAM_HYNIX
333S0476
U3200,U3210,U3220,U3230
CRITICAL
DRAM_HYNIX
333S0476
U3300,U3310,U3320,U3330
CRITICAL
DRAM_HYNIX
333S0476
U3400,U3410,U3420,U3430
CRITICAL
DRAM_HYNIX
333S0475
MICRON,DDR3,128M16,9x11.5
U3100,U3110,U3120,U3130
CRITICAL
DRAM_MICRON
333S0475
U3200,U3210,U3220,U3230
CRITICAL
DRAM_MICRON
333S0475
U3300,U3310,U3320,U3330
CRITICAL
DRAM_MICRON
333S0475
U3400,U3410,U3420,U3430
CRITICAL
DRAM_MICRON
353S1938
IC,ISL6258,REV2,BAT CHGR, 28P QFN
U7900
CRITICAL
Alternate Parts
128S0093
ALTERNATE FOR
PART NUMBER
128S0092
376S0466
740S0067
PART NUMBER
REFERENCE DESIGNATOR(S)
DESCRIPTION
ALL
33UF 20% 16V DCASE
376S0410
ALL
Si4413 for Si4405
740S0028
ALL
0.5A OC FUSE
104S0023
104S0018
ALL
1206 1/4W .002 OHM
152S0684
152S0421
ALL
1.0UH,22A,10MOHM
376S0627
376S0723
ALL
POWER NFET, 30V, 18A
152S0905
152S0861
ALL
IND,IHLP4040CZ,0.68uH,18A
BOM OPTION
CONFIGURATION OPTIONS
SYNC_MASTER=(N/A)
SYNC_DATE=(N/A)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
4
71
1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

SAMSUNG
PART NUMBER
MURATA
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
138S0629
CAP, 1UF, 6.3V, 10%, 0402
C7947,C7360,C2504,C2505
CRITICAL
SS_CAP_1UF
138S0629
CAP, 1UF, 6.3V, 10%, 0402
C2506,C2507,C2516,C2517,C7100,C7101,C7103
CRITICAL
138S0629
CAP, 1UF, 6.3V, 10%, 0402
C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603
CRITICAL
PART NUMBER
TAIYO YUDEN
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
QTY
DESCRIPTION
138S0628
CAP, 1UF, 6.3V, 10%, 0402
C7947,C7360,C2504,C2505
CRITICAL
MU_CAP_1UF
PART NUMBER
138S0630
CAP, 1UF, 6.3V, 10%, 0402
REFERENCE DES
C7947,C7360,C2504,C2505
CRITICAL
CRITICAL
BOM OPTION
TY_CAP_1UF
SS_CAP_1UF
138S0628
CAP, 1UF, 6.3V, 10%, 0402
C2506,C2507,C2516,C2517,C7100,C7101,C7103
CRITICAL
MU_CAP_1UF
138S0630
CAP, 1UF, 6.3V, 10%, 0402
C2506,C2507,C2516,C2517,C7100,C7101,C7103
CRITICAL
TY_CAP_1UF
SS_CAP_1UF
138S0628
CAP, 1UF, 6.3V, 10%, 0402
C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603
CRITICAL
MU_CAP_1UF
138S0630
CAP, 1UF, 6.3V, 10%, 0402
C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603
CRITICAL
TY_CAP_1UF
2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

SAMSUNG
PART NUMBER
MURATA
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
138S0632
10
CAP, 2.2UF, 6.3V, 20%, 0402
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249
CRITICAL
SS_CAP_2_2UF
138S0632
10
CAP, 2.2UF, 6.3V, 20%, 0402
C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259
CRITICAL
138S0632
CAP, 2.2UF, 6.3V, 20%, 0402
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
CRITICAL
138S0632
10
CAP, 2.2UF, 6.3V, 20%, 0402
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909
138S0632
10
CAP, 2.2UF, 6.3V, 20%, 0402
138S0632
10
CAP, 2.2UF, 6.3V, 20%, 0402
138S0632
10
138S0632
PART NUMBER
TAIYO YUDEN
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
QTY
DESCRIPTION
138S0633
10
CAP, 2.2UF, 6.3V, 20%, 0402
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249
CRITICAL
MU_CAP_2_2UF
PART NUMBER
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249
REFERENCE DES
CRITICAL
CRITICAL
TY_CAP_2_2UF
BOM OPTION
SS_CAP_2_2UF
138S0633
10
CAP, 2.2UF, 6.3V, 20%, 0402
C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259
CRITICAL
MU_CAP_2_2UF
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259
CRITICAL
TY_CAP_2_2UF
SS_CAP_2_2UF
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
CRITICAL
MU_CAP_2_2UF
138S0634
CAP, 2.2UF, 6.3V, 20%, 0402
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
CRITICAL
TY_CAP_2_2UF
CRITICAL
SS_CAP_2_2UF
138S0633
10
CAP, 2.2UF, 6.3V, 20%, 0402
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909
CRITICAL
MU_CAP_2_2UF
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909
CRITICAL
TY_CAP_2_2UF
C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919
CRITICAL
SS_CAP_2_2UF
138S0633
10
CAP, 2.2UF, 6.3V, 20%, 0402
C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919
CRITICAL
MU_CAP_2_2UF
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919
CRITICAL
TY_CAP_2_2UF
C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929
CRITICAL
SS_CAP_2_2UF
138S0633
10
CAP, 2.2UF, 6.3V, 20%, 0402
C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929
CRITICAL
MU_CAP_2_2UF
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929
CRITICAL
TY_CAP_2_2UF
CAP, 2.2UF, 6.3V, 20%, 0402
C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939
CRITICAL
SS_CAP_2_2UF
138S0633
10
CAP, 2.2UF, 6.3V, 20%, 0402
C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939
CRITICAL
MU_CAP_2_2UF
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939
CRITICAL
TY_CAP_2_2UF
12
CAP, 2.2UF, 6.3V, 20%, 0402
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296
CRITICAL
SS_CAP_2_2UF
138S0633
12
CAP, 2.2UF, 6.3V, 20%, 0402
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296
CRITICAL
MU_CAP_2_2UF
138S0634
12
CAP, 2.2UF, 6.3V, 20%, 0402
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296
CRITICAL
TY_CAP_2_2UF
138S0632
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516
CRITICAL
SS_CAP_2_2UF
138S0633
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516
CRITICAL
MU_CAP_2_2UF
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516
CRITICAL
TY_CAP_2_2UF
138S0632
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541
CRITICAL
SS_CAP_2_2UF
138S0633
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541
CRITICAL
MU_CAP_2_2UF
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541
CRITICAL
TY_CAP_2_2UF
138S0632
CAP, 2.2UF, 6.3V, 20%, 0402
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555
CRITICAL
SS_CAP_2_2UF
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555
CRITICAL
MU_CAP_2_2UF
138S0634
CAP, 2.2UF, 6.3V, 20%, 0402
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555
CRITICAL
TY_CAP_2_2UF
138S0632
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616
CRITICAL
SS_CAP_2_2UF
138S0633
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616
CRITICAL
MU_CAP_2_2UF
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616
CRITICAL
TY_CAP_2_2UF
138S0632
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641
CRITICAL
SS_CAP_2_2UF
138S0633
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641
CRITICAL
MU_CAP_2_2UF
138S0634
10
CAP, 2.2UF, 6.3V, 20%, 0402
C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641
CRITICAL
TY_CAP_2_2UF
138S0632
CAP, 2.2UF, 6.3V, 20%, 0402
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655
CRITICAL
SS_CAP_2_2UF
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655
CRITICAL
MU_CAP_2_2UF
138S0634
CAP, 2.2UF, 6.3V, 20%, 0402
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655
CRITICAL
TY_CAP_2_2UF
138S0632
CAP, 2.2UF, 6.3V, 20%, 0402
C2530,C2531,C2532,C2533,C2534,C2535,C2536
CRITICAL
SS_CAP_2_2UF
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
C2530,C2531,C2532,C2533,C2534,C2535,C2536
CRITICAL
MU_CAP_2_2UF
138S0634
CAP, 2.2UF, 6.3V, 20%, 0402
C2530,C2531,C2532,C2533,C2534,C2535,C2536
CRITICAL
TY_CAP_2_2UF
138S0632
CAP, 2.2UF, 6.3V, 20%, 0402
C2550,C2551,C2552,C2553,C2555,C2560,C2562,C2564
CRITICAL
SS_CAP_2_2UF
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
C2550,C2551,C2552,C2553,C2555,C2560,C2562,C2564
CRITICAL
MU_CAP_2_2UF
138S0634
CAP, 2.2UF, 6.3V, 20%, 0402
C2550,C2551,C2552,C2553,C2555,C2560,C2562,C2564
CRITICAL
TY_CAP_2_2UF
138S0632
CAP, 2.2UF, 6.3V, 20%, 0402
C2570,C2571,C2572,C2573,C2574,C2575,C2576,C2610
CRITICAL
SS_CAP_2_2UF
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
C2570,C2571,C2572,C2573,C2574,C2575,C2576,C2610
CRITICAL
MU_CAP_2_2UF
138S0634
CAP, 2.2UF, 6.3V, 20%, 0402
C2570,C2571,C2572,C2573,C2574,C2575,C2576,C2610
CRITICAL
TY_CAP_2_2UF
138S0632
CAP, 2.2UF, 6.3V, 20%, 0402
C4800,C7362,C7511
CRITICAL
SS_CAP_2_2UF
138S0633
CAP, 2.2UF, 6.3V, 20%, 0402
C4800,C7362,C7511
CRITICAL
MU_CAP_2_2UF
138S0634
CAP, 2.2UF, 6.3V, 20%, 0402
C4800,C7362,C7511
CRITICAL
TY_CAP_2_2UF
10UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS

SAMSUNG
PART NUMBER
MURATA
REFERENCE DES
CRITICAL
BOM OPTION
PART NUMBER
TAIYO YUDEN
QTY
DESCRIPTION
QTY
DESCRIPTION
QTY
DESCRIPTION
138S0626
10
CAP, 10UF, 6.3V, 20%, 0603
C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209
CRITICAL
SS_CAP_10UF
138S0625
10
CAP, 10UF, 6.3V, 20%, 0603
C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209
REFERENCE DES
CRITICAL
CRITICAL
BOM OPTION
MU_CAP_10UF
PART NUMBER
138S0627
10
CAP, 10UF, 6.3V, 20%, 0603
C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209
REFERENCE DES
CRITICAL
CRITICAL
BOM OPTION
TY_CAP_10UF
138S0626
10
CAP, 10UF, 6.3V, 20%, 0603
C1210,C1211,C1212,C1213,C1214,C1215,C1216,C1217,C1218,C1219
CRITICAL
SS_CAP_10UF
138S0625
10
CAP, 10UF, 6.3V, 20%, 0603
C1210,C1211,C1212,C1213,C1214,C1215,C1216,C1217,C1218,C1219
CRITICAL
MU_CAP_10UF
138S0627
10
CAP, 10UF, 6.3V, 20%, 0603
C1210,C1211,C1212,C1213,C1214,C1215,C1216,C1217,C1218,C1219
CRITICAL
TY_CAP_10UF
138S0626
10
CAP, 10UF, 6.3V, 20%, 0603
C1220,C1221,C1222,C1223,C1224,C1225,C1226,C1227,C1228,C1229
CRITICAL
SS_CAP_10UF
138S0625
10
CAP, 10UF, 6.3V, 20%, 0603
C1220,C1221,C1222,C1223,C1224,C1225,C1226,C1227,C1228,C1229
CRITICAL
MU_CAP_10UF
138S0627
10
CAP, 10UF, 6.3V, 20%, 0603
C1220,C1221,C1222,C1223,C1224,C1225,C1226,C1227,C1228,C1229
CRITICAL
TY_CAP_10UF
138S0626
CAP, 10UF, 6.3V, 20%, 0603
C1230,C1231,C1280
CRITICAL
SS_CAP_10UF
138S0625
CAP, 10UF, 6.3V, 20%, 0603
C1230,C1231,C1280
CRITICAL
MU_CAP_10UF
138S0627
CAP, 10UF, 6.3V, 20%, 0603
C1230,C1231,C1280
CRITICAL
TY_CAP_10UF
138S0626
CAP, 10UF, 6.3V, 20%, 0603
C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012
CRITICAL
SS_CAP_10UF
138S0625
CAP, 10UF, 6.3V, 20%, 0603
C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012
CRITICAL
MU_CAP_10UF
138S0627
CAP, 10UF, 6.3V, 20%, 0603
C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012
CRITICAL
TY_CAP_10UF
138S0626
CAP, 10UF, 6.3V, 20%, 0603
C7266,C7267,C7269,C7401,C7605
CRITICAL
SS_CAP_10UF
138S0625
CAP, 10UF, 6.3V, 20%, 0603
C7266,C7267,C7269,C7401,C7605
CRITICAL
MU_CAP_10UF
138S0627
CAP, 10UF, 6.3V, 20%, 0603
C7266,C7267,C7269,C7401,C7605
CRITICAL
TY_CAP_10UF
Acoustic Cap BOM Config Tables
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
5
71
Functional Test Points

NB NO_TESTS
These are normally testpoints but become NC
FUNC TEST - XDP/ITP CONNECTOR
NO_TEST
x2
x2
I647
I649
I638
I640
I639
FUNC TEST - M93 WIRELESS CONNECTOR
FUNC TEST - BATTERY CONNECTOR

BATT_POS
TRUE
GND
TRUE
SMC_BS_ALRT_L
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMBUS_SMC_BSA_SDA
TRUE
I470
I475
39 40 49
I479
42 69
I478
42 69
I476
I480
I648
I650
x6
I706
I668
I667
I669
I714
FUNC TEST - Power Supplies
I595
49
I477
x6
FUNC TEST - DC-IN CONNECTOR

PP18V5_DCIN
TRUE
ADAPTER_SENSE
TRUE
GND
TRUE
I483
49 70
I484
49
I482
I499
I500
FUNC TEST - FAN CONNECTOR

=PP5V_S0_FAN
TRUE
FAN_RT_PWM
TRUE
FAN_RT_TACH
TRUE
GND
TRUE
I501
7 46
I502
46
I503
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
AIRPORT_RST_L
PCIE_WAKE_L
CK505_SRC_CLKREQ6_L
PCIE_CLK100M_MINI_N_F
PCIE_CLK100M_MINI_P_F
PCIE_E_D2R_N_F
PCIE_E_D2R_P_F
PCIE_E_R2D_C_N_F
PCIE_E_R2D_C_P_F
AIRPORT_RST_L
=SMB_AIRPORT_DATA
=SMB_AIRPORT_CLK
PCIE_E_R2D_C_N_F
PCIE_E_R2D_C_P_F
PP3V3_S3_AP_AUX
6 24 34
I92
6 16 34
I454
I455
34
I457
34
I460
34
I459
34
I458
6 34
I461
6 34
I466
6 24 34
I463
6 34 42
I462
6 34 42
I467
6 34
I469
6 34
I474
34 70
I473
PPVCORE_S0_CPU
PP0V75_S0
PP1V05_S0
PP1V5_S0
PP1V5_S3
PP1V05_S5
PPMCPCORE_S0
PP5V_S0
PP3V3_S0
PP3V3_S3
PP5V_S3
PP3V3_S5
PP3V42_G3H
PP18V5_G3H
PPDCIN_G3H
PPBUS_G3H
PPBUS_R_G3H
PP1V8_S0
46
I472
I471
I741
I742
I743
I744
I745
I746
FUNC TEST - AIRPORT

CK505_SRC_CLKREQ6_L
TRUE
PCIE_WAKE_L
TRUE
AIRPORT_RST_L
TRUE
=SMB_AIRPORT_CLK
TRUE
=SMB_AIRPORT_DATA
TRUE
GND
TRUE
I757
I748
I749
I750
6 16 34
6 24 34
I751
6 34 42
I752
6 34 42
I753
I755
FUNC TEST - MIC

PP3V3_S0_MIC_F
TRUE
AUD_MIC_DATA_F
TRUE
AUD_MIC_CLK_F
TRUE
GND_MIC_F
TRUE
I756
I646
I735
I736
I737
I738
I740
I739
7 70
I681
7 70
I683
7 70
I682
7 70
I684
7 70
I685
7 70
I687
7 70
I686
7 70
I688
7 70
I689
7 70
I691
7 70
I690
7 70
I692
7 70
I694
7 70
I695
7 70
I696
7 70
I697
7 70
I698
FUNC TEST - SATA HDD

PP3V3_S0_HDD_F
TRUE
SATA_HDD_R2D_N
TRUE
SATA_HDD_R2D_P
TRUE
SATA_HDD_D2R_C_N
TRUE
SATA_HDD_D2R_C_P
TRUE
GND
TRUE
I701
I700
36 70
I702
36 67
I703
36 67
I704
36 67
I705
59
59
I716
59
I717
I718
HDA_SYNC
HDA_BIT_CLK
AUD_MIC_DATA
HDA_SDOUT
=PPVIN_S0_AUDIO
HDA_SDIN0
AUD_MIC_CLK
PM_SLP_S3_L
20 35 68
I720
20 35 68
I721
35 59
I722
20 35 68
I723
7 35
I725
20 35 68
I726
35 59
I727
20 34 35 39 56
I728
FUNC TEST - RIO HATCH CONNECTOR

DP_ML_C_N<3..0>
TRUE
DP_ML_C_P<3..0>
TRUE
DP_AUX_CH_C_N
TRUE
DP_AUX_CH_C_P
TRUE
DP_CA_DET_Q
TRUE
HDMI_CEC
TRUE
DP_HPD_Q
TRUE
PP3V3_S0_DPPWR
TRUE
USB2_EXTA_F_P
TRUE
USB2_EXTA_F_N
TRUE
PP5V_S3_USB2_EXTA_F
TRUE
GND
TRUE
61 67
35 60 61 67
x2
I654
35 60 61 67
I655
35 61
I656
35 61
I657
35 61
I658
35 61 70
I659
35 37
I660
35 37
I661
35 37 70
I662
I663
I665
I508
I509
I510
I512
I511
I513
Power Supply NO_TESTs
I514
I515
NO_TEST
I517
I516
I518
I520
I519
I521
I676
I734
9 12
65
12
12
12
12
12
12
12
12
12 20 42 68
12 20 42 68
9 12
65
12
12 20
12 18 68
12 20
12 20
12 13 65
12 13 65
12 65
9 12
24
12
9 12
65
9 12
65
9 12
65
7 12
7 9
10 11 12
61 67
x2
I506
XDP_BPM_L<0..5>
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
XDP_PWRGD
XDP_OBS20
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
XDP_TCK
JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L
MCP_DEBUG<7..0>
JTAG_MCP_TDI
JTAG_MCP_TMS
FSB_CLK_ITP_P
FSB_CLK_ITP_N
XDP_CPURST_L
XDP_DBRESET_L
XDP_TDO_CONN
XDP_TRST_L
XDP_TDI
XDP_TMS
=PP3V3_S0_XDP
=PP1V05_S0_CPU
36 67
I664
I507
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
59 70
I719
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I680
I699
FUNC TEST - AUDIO CONNECTOR

I645
7 70
I754
I747
I593
I666
I711
FUNC TEST - IPD CONNECTOR

SMC_LID
TRUE
PP3V42_G3H_IPD_F
TRUE
SMC_SYS_KBDLED
TRUE
SMC_SYS_LED
TRUE
=USB2_TPAD_N
TRUE
=USB2_TPAD_P
TRUE
SMC_ONOFF_L
TRUE
=USB2_IR_N
TRUE
=USB2_IR_P
TRUE
PP5V_S0_KBDLED_F
TRUE
PP5V_S3_TOPCASE_F
TRUE
=I2C_TPAD_SCL
TRUE
=I2C_TPAD_SDA
TRUE
SMC_ONOFF_L
TRUE
=USB2_IR_N
TRUE
=USB2_IR_P
TRUE
PP5V_S0_KBDLED_F
TRUE
LSOC_PRESS_H_R
TRUE
I712
38 39 40
x10I713
FUNC TEST - CAMERA USB, LVDS, ALS

PP5V_S3_CAMERA_F
TRUE
USB2_CAMERA_F_P
TRUE
USB2_CAMERA_F_N
TRUE
LCDBKLT_RTN<1..6>
TRUE
LVDS_IG_A_DATA_N<0..2>
TRUE
LVDS_IG_A_DATA_P<0..2>
TRUE
PPVOUT_S0_LCDBKLT
TRUE
LVDS_IG_A_CLK_F_N
TRUE
LVDS_IG_A_CLK_F_P
TRUE
LVDS_IG_DDC_CLK
TRUE
LVDS_IG_DDC_DATA
TRUE
PP3V3_S0_LCD_F
TRUE
PP3V3_LCDVDD_SW_F
TRUE
=I2C_ALS_SDA
TRUE
=I2C_ALS_SCL
TRUE
GND
TRUE
59 70
59
59
59 62
17 59 67
17 59 67
59 62 70
59 67
59 67
17 59
17 59
59 70
59 70
42 59
42 59
38 70
38 39
38 39
8 38
8 38
6 38 39 40
6 8 38
6 8 38
6 38 70
38 70
38 42
38 42
6 38 39 40
6 8 38
6 8 38
6 38 70
38
CLOCK NO_TESTS
NO_TEST
x13I522
REQUIRED NETS
LVDS NO_TESTS
TRUE
GND
NICE2HAVE NETS
NO_TEST
Functional Test and No-Tests

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
6
71
7
"S0" RAILS
50
=PPVCORE_S0_CPU_REG
27 A
PPVCORE_S0_CPU
=PPVCORE_S0_CPU
51
=PPMCPCORE_S0_REG
11.551 A
PPMCPCORE_S0
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0.9V
MAKE_BASE=TRUE
=PPVCORE_S0_MCP
=PPVCORE_S0_MCP_VSENSE
54
=PP0V75_S0_REG
1.075 A
PP0V75_S0
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PPVTT_S0_VTTCLAMP
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
57
=PP1V05_S0_FET
7.047 A
PP1V05_S0
6 70
54
=PP0V75_S3_VTTREF
=PPVTT_S3_DDR_BUF
10 11 64
6 70
54
=PP1V5_S3_REG
PP1V5_S3
VOLTAGE=1.8V
MAKE_BASE=TRUE
12.984 A
21 22
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_P1V5S0FET
=PP1V5_S3_MEMRESET
43
6 70
57
=PP3V3_S3_FET
PP3V3_S3
VOLTAGE=3.3V
MAKE_BASE=TRUE
57
315 mA
33
6 70
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP5V_S3_REG
5.027 A
PP1V5_S0
VOLTAGE=1.5V
MAKE_BASE=TRUE
VOLTAGE=5V
MAKE_BASE=TRUE
52
=PP1V8_S0_REG
19 mA
PP1V8_S0
11
15 22 66
=PP3V3_S0_FET
PP3V3_S0
VOLTAGE=3.3V
MAKE_BASE=TRUE
2.046 A
49 24
=PP3V42_G3H_REG
PP3V42_G3H
=PP1V05_S5_MCP_VDD_AUXC 21 22
=PP1V05_S5_P1V05S0FET 57
=PP1V05_RMGT_P1V05RMGTFET 57
25
=PP3V42_G3H_SMC
=PP3V42_G3H_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_IPD
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_CHGR
=PP3V42_G3H_LPCPLUS
6 70
55
=PP3V3_S5_REG
PP3V3_S5
VOLTAGE=3.3V
MAKE_BASE=TRUE
27 28 31 33
29 30 32 33
4.011 A
57
6 70
=PP3V3_S5_AIRPORT_AUX 34
=PP3V3_S5_LCD
59
=PP3V3_S5_MCP
21 22
=PP3V3_S5_MCPPWRGD
24
=PP3V3_S5_MCP_GPIO
17 19 20
=PP3V3_S5_P1V05FET
57
=PP3V3_S5_PWRCTL
56
=PP3V3_S5_ROM
41 48
=PP3V3_S5_SMBUS_MCP_1 42
=PP3V3_S5_MEMRESET
26
=PP3V3_S5_P3V3RMGTFET 57
=PP3V3_S5_P1V05RMGTFET 57
26
6 70
42
42
58 49
=PP18V5_G3H_CHGR
=PP3V3_S0_DPCONN
61
=PP3V3_S0_FAN
46
=PP3V3_S0_IMVP
50
=PP3V3_S0_LCD
59
=PP3V3_S0_LCDBKLT
62
=PP3V3_S0_MCP
20 21 22
=PP3V3_S0_MCP_GPIO
17 18 20
=PP3V3_S0_MCP_PLL_UF 22
=PP3V3_S0_MCP_VPLL_UF 23
=PP3V3_S0_PWRCTL
24 56
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_THRM_SNR
45
=PP3V3_S0_VMON
56
=PP3V3_S0_XDP
6 12
=PPVIN_S0_P1V8S0
52
=PP3V3_S0_LPCPLUS
41
=PP3V3_S0_HDD
36
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_MCP_0 42
=PP3V3R1V5_S0_MCP_HDA 20 22
=PP3V3_S0_SMC_LS
40
=PP3V3_S0_MIC
59
39 40
40
42
38
37
58
41
PP18V5_G3H
6 70
VOLTAGE=18.5V
MAKE_BASE=TRUE
49
=PPDCIN_G3H
PPDCIN_G3H
6 70
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PPVIN_G3H_P3V42G3H
58 44
=PPBUSA_G3H
49
PPBUS_R_G3H
6 70
VOLTAGE=12.6V
MAKE_BASE=TRUE
50
54
51
53
6 70
C
58 44
=PPBUSB_G3H
PPBUS_G3H
6 70
VOLTAGE=12.6V
MAKE_BASE=TRUE
6.207 A
=PPVIN_S3_5VS3
=PPVIN_S5_3V3S5
=PPVIN_S0_AUDIO
=PPVIN_G3H_DCIN
=PPBUS_S0_LCDBKLT
=PPBUS_G3HRS5
6 70
6 70
6 70
VOLTAGE=3.42V
MAKE_BASE=TRUE
165 mA
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP3V3R1V8_S0_MCP_IFP_VDD
57
6 70
=PP5V_S3_CAMERA
59
=PP5V_S3_MCPDDRFET
57
=PP5V_S3_P1V05S0FET 57
=PP5V_S3_TOPCASE
38
=PP5V_S3_VTTCLAMP
57
=PP5V_S3_1V5S30V75S0 54
=PP5V_S3_EXTUSB
37
=PP5V_S3_P5VS0FET
57
=PP5V_S3_MCPREG
51
6 70
=PP1V5_S0_CPU
10
=PP1V5_S0_VMON
56
=PP1V8R1V5_S0_MCP_MEM
PP1V05_S5
VOLTAGE=1.05V
MAKE_BASE=TRUE
7.368 A
=PPVIN_S5_CPU_IMVP
=PPVIN_S5_1V5S30V75S0
=PPVIN_S0_MCPCORES0
=PPVIN_S5_1V05
PP5V_S3
3.134 A
=PP1V5_S0_FET
=PP1V05_S5_REG
13 A
55
53
70
=PP3V3_S3_BT
34
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMC
40
=PP3V3_S3_SMS
47
=PP3V3_S3_VREFMRGN
25
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_DDRREG
54
=PP3V3_S3_MCPREG
51
=PP3V3_S3_MCP_GPIO
20
33
=PP1V05_S0_CPU
6 9 10 11 12
=PP1V05_S0_MCP_AVDD_UF 22
=PP1V05_S0_MCP_FSB
8 13 21 22
=PP1V05_S0_MCP_HDMI_VDD 17 23
=PP1V05_S0_MCP_PEX_DVDD 7 22
=PP1V05_S0_MCP_PLL_UF 22
=PP1V05_S0_MCP_SATA_DVDD 19 22
=PP1V05_S0_SMC_LS
40
=PP1V05_S0_VMON
56
57
PP0V75_S3
VOLTAGE=0.75V
MAKE_BASE=TRUE
1.075 A
"G3H" RAILS
"S5" RAILS
"S3" RAILS
VOLTAGE=0.9V
MAKE_BASE=TRUE
55
55
6 35
49
63
43
"RMGT" RAILS
17 23
PP3V3_RMGT
57
=PP3V3_RMGT_FET
57
=PP1V05_RMGT_FET
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_ENET_MCP_RMGT
PP1V05_RMGT
70
17 22
70
VOLTAGE=1.05V
MAKE_BASE=TRUE
17 22
=PP1V05_ENET_MCP_PLL_MAC
22
42
42
PEX & SATA AVDD/DVDD aliases

A
70 22
57
=PP5V_S0_FET
562 mA
=PP1V05_S0_MCP_PEX_AVDD0
PP1V05_S0_MCP_PEX_AVDD
Power Aliases
16
206 mA (A01)
16
SYNC_MASTER=WFERRY
MAKE_BASE=TRUE
PP5V_S0
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_CPU_IMVP
=PP5V_S0_DP_AUX_MUX
=PP5V_S0_FAN
=PP5V_S0_KBDLED
=PP5V_S0_LPCPLUS
6 70
206 mA (A01)
22 7
50
=PP1V05_S0_MCP_PEX_DVDD0
=PP1V05_S0_MCP_PEX_DVDD
16
57 mA (A01)
16

57 mA (A01)
60

6 46

38

41
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
7
71
PCI-E ALIASES
EMI SPRING CLIPS

16
=PEG_D2R_N<15:0>
CRITICAL
=PEG_D2R_P<15:0>
NC_PEG_D2R_P<15:0>
16
=PEG_R2D_C_N<15:0>
NC_PEG_R2D_C_N<15:0>
NO_TEST=TRUE
16
D
Z0900
4.5OD2.0H-M1.6X0.35
Z0910
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_PEG_PRSNT_L
PEG_CLKREQ_L
TP_PEG_CLKREQ_L
PEG_CLK100M_P
TP_PEG_CLK100M_P
NC_MCP_CLK27M_XTALIN
TP_PEG_CLK100M_N
16
EXTGPU_PWR_EN
TP_EXTGPU_PWR_EN
MAKE_BASE=TRUE
CRT_IG_G_Y_Y
NC_CRT_IG_G_Y_Y
17
CRT_IG_B_COMP_PB
NC_CRT_IG_B_COMP_PB
MAKE_BASE=TRUE
17
CRT_IG_HSYNC
NC_CRT_IG_HSYNC
17
CRT_IG_VSYNC
NC_CRT_IG_VSYNC
22 21 13 7
MAKE_BASE=TRUE
NO STUFF
LVDS ALIASES
STDOFF-4.0OD2.4H-0.5-THNP
HDA PULL-DOWN
Z0912
LVDS_IG_A_DATA_P<3>
NC_LVDS_IG_A_DATA_P3
67 17
LVDS_IG_A_DATA_N<3>
NC_LVDS_IG_A_DATA_N3
18
NO_TEST=TRUE
AUD_I2C_INT_L IS PU ON MCP PAGE
67 17
LVDS_IG_B_CLK_N
NC_LVDS_IG_B_CLK_N
67 17
LVDS_IG_B_DATA_P<3:0>
NC_LVDS_IG_B_DATA_P<3:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
LVDS_IG_B_DATA_N<3:0>
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATA_N<3:0>
MAKE_BASE=TRUE
13
18
CPU_PECI_MCP
FW_PME_L
ODD_PWR_EN_L
TP_CPU_PECI_MCP
MAKE_BASE=TRUE
TP_FW_PME_L
MAKE_BASE=TRUE
TP_ODD_PWR_EN_L
15
15
15
=DVI_HPD_GMUX_INT
15
20K
39
39
39
39
39
39
39
39
39
39
39
39
15
SATA ALIASES
5%
1/20W
MF
2 201
NO_TEST
39
15
R0940
NO-CONNECT UNUSED SMC INTERFACE PORTS
39
15
UNUSED SATA ODD SIGNALS

19
19
19
19
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
15
15
TP_SATA_ODD_R2D_C_P
TP_SATA_ODD_R2D_C_N
TP_SATA_ODD_D2R_P
TP_SATA_ODD_D2R_N
MAKE_BASE=TRUE
15
MAKE_BASE=TRUE
15
MAKE_BASE=TRUE
15
MAKE_BASE=TRUE
15
15
LAN ALIASES
15
15
UNUSED ETHERNET RG/MII INTERFACE
15
17
ENET_RXD<0>
17
ENET_MDIO
17
ENET_CLK125M_RXCLK
17
ENET_RXD<1>
17
ENET_RX_CTRL
17
ENET_INTR_L
17
ENET_RXD<2>
17
ENET_CLK125M_TXCLK
17
ENET_RXD<3>
17
MCP_MII_VREF
15
OUT
65 13 9
OUT
65 13 12 9
OUT
65 13 9
OUT
65 13 9
OUT
5%
1/20W
MF
2 201
CPU_DPRSTP_L
FSB_BREQ0_L
FSB_CPURST_L
CPU_INTR
CPU_NMI
NO_TEST
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
UNUSED USB PORTS
68
8 7 6 5
68
RP0930
RP0931
RP0932
68 19
10K
10K
10K
68 19
5%
1/32W
4X0201-HF
NC_MEM_A_CLK4P
NC_MEM_A_CLK4N
NC_MEM_A_CLK3P
NC_MEM_A_CLK3N
NC_MEM_A_CS_L<2>
NC_MEM_A_CS_L<3>
NC_MEM_A_CKE<2>
NC_MEM_A_CKE<3>
NC_MEM_B_CLK4P
NC_MEM_B_CLK4N
NC_MEM_B_CLK3P
NC_MEM_B_CLK3N
NC_MEM_B_CS_L<2>
NC_MEM_B_CS_L<3>
NC_MEM_B_ODT<2>
NC_MEM_B_ODT<3>
NC_MEM_B_CKE<2>
NC_MEM_B_CKE<3>
TP_MEM_A_CLK4P
TP_MEM_A_CLK4N
TP_MEM_A_CLK3P
TP_MEM_A_CLK3N
TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>
TP_MEM_A_CKE<2>
TP_MEM_A_CKE<3>
TP_MEM_B_CLK4P
TP_MEM_B_CLK4N
TP_MEM_B_CLK3P
TP_MEM_B_CLK3N
TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>
TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>
TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>
MAKE_BASE=TRUE
68 19
8 7 6 5
5%
1/32W
4X0201-HF
5%
1/32W
4X0201-HF
68
68
1 2 3 4
150
USB ALIASES
68 19
8 7 6 5
R0998
MEM ALIASES
NC_SMC_PA0
TRUE
MAKE_BASE=TRUE
NC_SMC_PA1
TRUE
MAKE_BASE=TRUE
NC_ESTARLDO_EN
TRUE
MAKE_BASE=TRUE
NC_SMC_P26
TRUE
MAKE_BASE=TRUE
NC_SMC_P41
TRUE
MAKE_BASE=TRUE
NC_SMC_P67
TRUE
MAKE_BASE=TRUE
NC_SMC_GFX_OVERTEMP_L TRUE
MAKE_BASE=TRUE
NC_EXCARD_OC_L
TRUE
MAKE_BASE=TRUE
NC_SMC_P24
TRUE
MAKE_BASE=TRUE
NC_SMC_EXCARD_CP
TRUE
MAKE_BASE=TRUE
NC_ALS_RIGHT
TRUE
MAKE_BASE=TRUE
NC_ALS_GAIN
TRUE
MAKE_BASE=TRUE
NC_SMC_FAN_1_CTL
TRUE
MAKE_BASE=TRUE
NC_SMC_FAN_2_CTL
TRUE
MAKE_BASE=TRUE
NC_SMC_FAN_3_CTL
TRUE
MAKE_BASE=TRUE
NC_SMC_FAN_1_TACH
TRUE
MAKE_BASE=TRUE
NC_SMC_FAN_2_TACH
TRUE
MAKE_BASE=TRUE
NC_SMC_FAN_3_TACH
TRUE
MAKE_BASE=TRUE
NC_SMC_RSTGATE_L
TRUE
MAKE_BASE=TRUE
NC_ISENSE_CAL_EN
TRUE
MAKE_BASE=TRUE
NC_SMC_FWE
TRUE
MAKE_BASE=TRUE
NC_SMC_ANALOG_ID
TRUE
MAKE_BASE=TRUE
NC_ALS_LEFT
TRUE
NC_SMC_NB_DDR_ISENSEMAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SMC_P10
TRUE
MAKE_BASE=TRUE
NC_SMC_PA5
TRUE
MAKE_BASE=TRUE
NC_SMC_GPU_ISENSE
TRUE
65 50 13 9
MISC NC MCP79 ALIASES
DP HOTPLUG PULL-DOWN
17
R0996
R0920
5%
1/20W
MF
2 201
HPLUG_DET2
39
NO STUFF
5%
1/20W
MF
2 201
MAKE_BASE=TRUE
39
SMC ALIASES
39
MAKE_BASE=TRUE
MAKE_BASE=TRUE
39
5%
1/20W
MF
201
NC_LVDS_IG_B_CLK_P
NO_TEST=TRUE
20
39
5%
1/20W
MF
201
62
67 17
100K
39
150
5%
1/20W
MF
201
MAKE_BASE=TRUE
AUD_IPHS_SWITCH_EN
4.5OD2.0H-M1.6X0.35
39
R0999 1
200
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
Z0904
39
NO STUFF
R0997 1
220
NO STUFF
LVDS_IG_B_CLK_P
67 17
UNUSED IPHS SIGNAL(FOR IPHONE JACK)
39
NO STUFF
R0995 1
MAKE_BASE=TRUE
67 17
Z0911
4.5OD2.0H-M1.6X0.35
39
=PP1V05_S0_MCP_FSB
UNUSED LVDS SIGNALS
39
266
133
200
(166)
333
100
(400)
(RSVD)
Exist in MRB but not Intel designs. Here for CYA.

If found to be necessary, will move to page14.csa
MAKE_BASE=TRUE
NO_TEST=TRUE
39
FSB MHZ
0
1
0
1
0
1
0
1
Extra FSB Pull-ups
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
SMC_PA0
SMC_PA1
ESTARLDO_EN
SMC_P26
SMC_P41
SMC_BIL_BUTTON_L
SMC_GFX_OVERTEMP_L
SMC_EXCARD_OC_L
SMC_P24
SMC_EXCARD_CP
ALS_RIGHT
ALS_GAIN
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
SMC_EXCARD_PWR_EN
ISENSE_CAL_EN
SMC_FWE
SMC_ANALOG_ID
ALS_LEFT
SMC_NB_DDR_ISENSE
SMC_P10
SMC_PA5
SMC_GPU_ISENSE
13
0
0
1
1
0
0
1
1
NC_CRT_IG_R_C_PR
17
Z0902
39
=MCP_BSEL<0:2>
OUT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
4.5OD2.0H-M1.6X0.35
CRT_IG_R_C_PR
TP_EXTGPU_RESET_L
PCIE_FC_PRSNT_L
Z0903
CPU_BSEL<0:2>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
IN
NC_MCP_CLK27M_XTALOUT
NO_TEST=TRUE
MAKE_BASE=TRUE
EXTGPU_RESET_L
MCP_CLK27M_XTALOUT
65 9
0
0
0
0
1
1
1
1
MAKE_BASE=TRUE
NO_TEST=TRUE
PCIE_MINI_PRSNT_L
Z0901
NO_TEST=TRUE
AIRPORT CARD AND TURBOMEM PRESENT SIGNAL
NC_MCP_TV_DAC_VREF
MCP_CLK27M_XTALIN
17
MAKE_BASE=TRUE
4.5OD2.0H-M1.6X0.35
MCP_TV_DAC_VREF
17
NO_TEST=TRUE
MAKE_BASE=TRUE
PEG_CLK100M_N
16
17
17
MAKE_BASE=TRUE
67 16
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
PEG_PRSNT_L
NC_MCP_TV_DAC_RSET
NO_TEST=TRUE
NC_PEG_R2D_C_P<15:0>
16
BOSSES
STANDOFFS
=PEG_R2D_C_P<15:0>
MCP_TV_DAC_RSET
17
MAKE_BASE=TRUE
NO_TEST=TRUE
16
67 16
MAKE_BASE=TRUE
16
SC0900
1
EMI-SPRING
PS-25N
BSEL<2..0>
UNUSED CRT & TV-OUT INTERFACE
NC_PEG_D2R_N<15:0>
NO_TEST=TRUE
CPU FSB FREQUENCY STRAPS
DACS ALIASES
UNUSED GPU LANES
PLACE CLIPS PER MCO ON TOPSIDE NEAR BATTERY CONNECTOR J6900
1 2 3 4
1 2 3 4
68 19
68 19
TP_USB_EXTB_P
TP_USB_EXTB_N
TP_USB_EXTC_P
TP_USB_EXTC_N
TP_USB_EXTD_P
TP_USB_EXTD_N
TP_USB_EXCARD_P
TP_USB_EXCARD_N
TP_USB_MINI_P
TP_USB_MINI_N
USB_EXTB_P
USB_EXTB_N
USB_EXTC_P
USB_EXTC_N
USB_EXTD_P
USB_EXTD_N
USB_EXCARD_P
USB_EXCARD_N
USB_MINI_P
USB_MINI_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
EXTERNAL PORT A
MAKE_BASE=TRUE
37
=USB2_EXTA_P
USB_EXTA_P
37
=USB2_EXTA_N
USB_EXTA_N
37
19 68
MAKE_BASE=TRUE
19 68
MAKE_BASE=TRUE
=EXTAUSB_OC_L
USB_EXTA_OC_L
19
MAKE_BASE=TRUE
CAMERA
17
17
17
17
17
17
ENET_RESET_L
MCP_CLK25M_BUF0_R
ENET_PWRDWN_L
ENET_MDC
ENET_TX_CTRL
ENET_TXD<3..0>
NC_ENET_RESET_L
MAKE_BASE=TRUE
NC_MCP_CLK25M_BUF0_R
MAKE_BASE=TRUE
NC_ENET_PWRDWN_L
MAKE_BASE=TRUE
NC_ENET_MDC
MAKE_BASE=TRUE
NC_ENEX_TX_CTRL
MAKE_BASE=TRUE
NC_ENET_TXD<3..0>
MAKE_BASE=TRUE
59
=USB2_CAMERA_P
USB_CAMERA_P
59
=USB2_CAMERA_N
USB_CAMERA_N
19 68
MAKE_BASE=TRUE
19 68
MAKE_BASE=TRUE
TRACKPAD(WELLSPRING)
38 6
=USB2_TPAD_P
USB_TPAD_P
38 6
=USB2_TPAD_N
USB_TPAD_N
19 68
MAKE_BASE=TRUE
19 68
MAKE_BASE=TRUE
IR
38 6
=USB2_IR_P
USB_IR_P
38 6
=USB2_IR_N
USB_IR_N
19 68
MAKE_BASE=TRUE
19 68
MAKE_BASE=TRUE
BT (M93)
34
34
=USB2_BT_P
=USB2_BT_N
USB_BT_P
MAKE_BASE=TRUE
USB_BT_N
19 68
19 68
MAKE_BASE=TRUE
SIGNAL ALIAS /RESET
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)

20
SMC_IG_THROTTLE_L
SMC_GFX_THROTTLE_L
GND
VOLTAGE=0V
39
MAKE_BASE=TRUE
SMC_SMS_INT_L
40
=SMC_SMS_INT
SIZE
MAKE_BASE=TRUE
APPLE INC.
SMC_ADAPTER_EN
40 39 20
SMC_ADAPTER_PRESENT
SCALE
SHT
NONE
REV.
051-7631
34
MAKE_BASE=TRUE
DRAWING NUMBER
39
2.3.0
OF
8
71
OMIT
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
65 13
65 13
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
IN CPU_A20M_L
OUT CPU_FERR_L
IN CPU_IGNNE_L
R1
R5
U1
P4
W5
AN1
AK4
AG1
AT4
AK2
AT2
AH2
AF4
AJ5
AH4
AM4
AP4
AR5
AJ1
AL1
AM2
AU5
AP2
AR1
AN5
C7
D4
F10
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
BR0*
FSB_BREQ0_L
M2
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
IN
N1
FSB_LOCK_L
BI
RESET*
RS0*
RS1*
RS2*
TRDY*
G5
K2
H4
K4
L1
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
HIT*
HITM*
H2
F2
FSB_HIT_L
FSB_HITM_L
B40
D8
LOCK*
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
65
AY8
BA7
BA5
AY2
AV10
AV2
AV4
AW7
AU1
AW5
AV8
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
R1000
6 7 10 11 12
54.9
1%
1/20W
MF
201
8 13 65
CPU_IERR_L
CPU_INIT_L
IERR*
INIT*
=PP1V05_S0_CPU
13 65
13 65
IN
8 12 13 65
IN
13 65
IN
13 65
IN
13 65
IN
13 65
BI
13 65
BI
13 65
OMIT
BI
6 12 65
BI
6 12 65
BI
6 12 65
BI
6 12 65
BI
R1001 1
54.9
1%
1/20W
MF
201
6 12 65
2
6 12 65
IN
65 13 8
IN
65 13 8
IN
65 13
IN
24 12 6
OUT
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
XDP_DBRESET_L
CPU_TEST1
9 CPU_TEST2
TP_CPU_TEST3
9 CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
F8
C9
C5
E5
J7
E37
D40
C43
AE41
AY10
AC43
65 13
BI
BI
65 13
BI
9 12 65
65 13
BI
IN
6 9 12 65
65 13
BI
IN
6 9 12 65
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
OUT
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
OUT
45
OUT
45
B10
PM_THRMTRIP_L
OUT
13 40 65
FSB_CLK_CPU_P
FSB_CLK_CPU_N
BI
6 9 12 65
D38
BB34
BD34
A35
C35
BI
65 13
IN
OUT
13 40 50 65
H CLK
BCLK0
BCLK1
BI
65 13
IN
THERMAL
STPCLK*
LINT0
LINT1
SMI*
65 13
BI
ICH
65 13
BI
65 13
5%
1/20W
MF
201
THERMTRIP*
65 13
65 13
BI
68
A20M*
FERR*
IGNNE*
BI
6 9 12 65
R1002 1
PROCHOT*
THRMDA
THRMDC
65 13
IN
13 65
65 13
BI
IN
13 65
65 13
BI
65 13
BI
65 13
BI
65 13
BI
NC_CPU_RSVD_J9
65 13
BI
NC_CPU_RSVD_F4
NC_CPU_RSVD_H8
NC_CPU_RSVD_V2
NC_CPU_RSVD_Y2
NC_CPU_RSVD_AG5
NC_CPU_RSVD_AL5
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
65 13
BI
DBR*
RSVD7
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
J9
F4
H8
V2
Y2
AG5
AL5
1K
CPU JTAG Support

65 12 9 6
XDP_TMS
R1090
1
65 12 9
XDP_TDI
54.9
1%
1/20W
MF
201
65 25
R1092
54.9
1
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)
1%
1/20W
MF
2 201
CPU_TEST4
C1014
R1094
XDP_TRST_L
649
CPU_GTLREF
GTLREF
54.9
1%
1/20W
MF
201
10%
16V
X5R
402
MISC
R1010
0
5%
1/20W
MF
201
R1011 1
1K
NO STUFF
1
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
65
65
65
65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
BI
13 65
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
65 8
65 8
65 8
OUT CPU_BSEL<0>
OUT CPU_BSEL<1>
OUT CPU_BSEL<2>
BSEL0
BSEL1
BSEL2
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
TP_CPU_PSI_L
IN
8 13 50 65
IN
13 65
IN
13 65
IN
12 13 65
IN
13 65
R1023 1
R1021 1
54.9
1%
1/20W
MF
201
54.9
1%
1/20W
MF
201
5%
1/20W
MF
2 201
R1022
R1020
27.4
R1012
1K
5%
1/20W
MF
201 2
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
COMP0
COMP1
COMP2
COMP3
0.1uF
NO STUFF
1%
1/20W
MF
201
NO STUFF
65 12 9 6
D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*
NO STUFF
R1093
XDP_TCK
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>
CPU_TEST1 9
CPU_TEST2 9
R1006
65 12 9 6
D0*
D1*
BGA
D2*
(2 OF 8)
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*
2K
1%
1/20W
MF
201
XDP_TDO
54.9
1%
1/20W
MF
201
R1091
65 12 9 6
R1005
U1000
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
DATA GRP 2
BI
65 13
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
13 65
BI
PENRYN-SFF
BI
65 13
N5
F38
J1
BI
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
65 13
DEFER*
DRDY*
DBSY*
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
DATA GRP 0
BI
M4
J5
L5
DATA GRP 3
65 13
ADS*
BNR*
BPRI*
BGA
(1 OF 8)
PENRYN-SFF
BI
U1000
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
CONTROL
BI
65 13
A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*
ADDR GROUP0
BI
65 13
P2
V4
W1
T4
AA1
AB4
T2
AC5
AD2
AD4
AA5
AE5
AB2
AC1
Y4
XDP/ITP SIGNALS
65 13
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>
DATA GRP1
BI
ADDR GROUP1
65 13
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.
PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
27.4
1%
1/20W
MF
201
1%
1/20W
MF
201
PLACEMENT_NOTE (all 4 resistors):
1%
1/20W
MF
201
Place within 12.7mm of CPU
CPU FSB
SYNC_MASTER=M97

SYNC FROM M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
9
71
(3 OF 8)
VCC
VCC
27A
AD28
AD30
AB28
AB30
Y28
Y30
AK26
AH26
AF26
AK28
AK30
AH28
AH30
AF28
AF30
AP26
AM26
AP28
AP30
AM28
AM30
AY26
AV26
AT26
AY28
AY30
AV28
AV30
AT28
AT30
BD26
BB26
BD28
(CPU IO POWER 1.05V) 2.5A
VCCP
N37
L37
K38
J37
W37
V38
U37
R37
P38
AC37
AB38
AA37
AK38
AJ37
AG37
AF38
=PP1V05_S0_CPU
6 7 9 10 11 12
(CPU INTERNAL PLL POWER 1.5V) 0.130A

VCCA
VID
VCCSENSE
VSSSENSE
=PP1V5_S0_CPU
B34
D34
BD8
BC7
BB10
BB8
BC5
BB4
AY4
CPU_VID<0>
OUT
11 50 65
CPU_VID<1>
OUT
11 50 65
CPU_VID<2>
OUT
11 50 65
CPU_VID<3>
OUT
11 50 65
CPU_VID<4>
OUT
11 50 65
CPU_VID<5>
OUT
11 50 65
CPU_VID<6>
OUT
11 50 65
VCCA=1.5 ONLY
7 11
=PPVCORE_S0_CPU
OMIT
U1000
BGA
(7 OF 8)
VCC
VCC
K20
M16
M18
K16
K18
V20
T20
P20
V16
V18
T16
T18
P16
P18
AD20
AB20
Y20
AD16
AD18
AB16
AB18
Y16
Y18
AK20
AK16
AK18
AH20
AF20
AH16
AH18
AF16
AF18
AP20
AM20
AP16
AP18
AM16
AM18
AY20
AV20
AT20
AY16
AY18
AV16
AV18
AT16
AT18
BD20
BB20
BD16
BD18
BB16
BB18
AP14
AM14
AY14
AV14
AT14
BD14
BB14
7 10 11 64
R1100
100
BD12
1%
1/20W
MF
AE37
AP38
AN37
AL37
C33
B32
H36
F36
G35
F34
E33
E35
D32
K36
N35
L35
J35
W35
V36
P36
U35
R35
AB36
AC35
AA35
AK36
AF36
AJ35
AG35
AE35
AP36
AN35
AL35
C13
B14
B12
H12
H14
G11
G13
F12
F14
E11
E13
D14
D12
K10
N11
N13
M14
L11
L13
K12
K14
J11
J13
V10
P10
W11
W13
V12
V14
U11
U13
T14
R11
OMIT
U1000
BGA
(8 OF 8)
VCCP
VCCP
R13
P12
P14
AB10
AD14
AC11
AC13
AB12
AB14
AA11
AA13
Y14
AK10
AF10
AK12
AK14
AJ11
AJ13
AH14
AG11
AG13
AF12
AF14
AE11
AE13
AP10
AR11
AR13
AP12
AN11
AN13
AL11
AL13
AU11
AU13
N7
N9
L7
L9
W7
W9
U7
U9
R7
R9
AC7
AC9
AA7
AA9
AJ7
AJ9
AG7
AG9
AE7
AE9
AR7
AR9
AN7
AN9
AL7
AL9
A33
A13
6 7 9 10 11 12
Y6
Y8
AK6
AK8
AH6
AH8
AF6
AF8
AP6
AP8
AM6
AM8
AY6
AW9
AU7
AV6
AU9
AT6
AT8
BD6
BC9
BB6
BA9
C3
B4
G3
E3
D2
N3
L3
J3
W3
U3
R3
AC3
AA3
OMIT
U1000
BGA
(6 OF 8)
VSS
2 201
BC13
CPU_VCCSENSE_P
CPU_VCCSENSE_N
OUT
OUT
50 65
50 65
R1101
LAYOUT NOTE:
100
PLACE R1100 AND R1101
1%
1/20W
MF
201
WITHIN 1 INCH OF CPU W/ NO STUB
LAYOUT NOTE:
CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
2
ZO=27.4 OHM DIFFERENTIAL TRACE ROUTING.
VSS
AJ3
AG3
AE3
AR3
AN3
AL3
AW3
AU3
BD4
BC3
BB2
BA3
G1
E1
AW1
BA1
A39
A41
A31
A27
A29
A21
A23
A25
A17
A19
A15
A11
A9
A5
A7
B42
H42
F42
D42
D44
F44
M42
K42
V42
T42
P42
AD42
AB42
Y42
AK42
AH42
AF42
AP42
AM42
AY42
AV42
AT42
AV44
AY44
BB42
BA43
C39
H38
G37
E39
N39
M38
L39
J39
W39
U39
T38
R39
AD38
AC39
AA39
Y38
AJ39
AH38
AG39
AE39
AR37
AR39
AN39
AM38
AL39
AW37
AW39
AU37
AU39
AT38
BD38
BD40
BC41
BA39
B36
D36
H34
M36
M34
K34
T36
V34
T34
P34
AD36
Y36
AD34
AB34
Y34
AK34
AH36
AH34
AF34
AR35
AM36
OMIT
U1000
BGA
(4 OF 8)
VSS
VSS
E21
E23
E25
N21
N23
N25
L21
L23
L25
J21
J23
J25
W21
W23
W25
U21
U23
U25
R21
R23
R25
AC21
AC23
AC25
AA21
AA23
AA25
AJ21
AJ23
AJ25
AG21
AG23
AG25
AE21
AE23
AE25
AR21
AR23
AR25
AN21
AN23
AN25
AL21
AL23
AL25
AW21
AW23
AW25
AU21
AU23
AU25
BC21
BC23
BC25
BA21
BA23
BA25
C19
C17
G17
G19
E17
E19
N17
N19
L17
L19
J17
J19
W17
W19
U17
U19
R17
R19
AC17
AC19
AA17
AA19
AJ17
AJ19
AG17
AG19
AP34
AM34
AV36
AT36
AY34
AW33
AW35
AV34
AU35
BD36
BB36
BC33
BA33
C31
C29
C27
G31
E31
G27
G29
E27
E29
N31
L31
J31
N27
N29
L27
L29
J27
J29
W31
W27
W29
U31
R31
U27
U29
R27
R29
AC31
AA31
AC27
AC29
AA27
AA29
AJ31
AG31
AE31
AJ27
AJ29
AG27
AG29
AE27
AE29
AR31
AR27
AR29
AN31
AL31
AN27
AN29
AL27
AL29
AW31
AU31
AW27
AW29
AU27
AU29
BC31
BA31
BC27
BC29
BA27
BA29
C25
C23
C21
G21
G23
G25
LAYOUT NOTE:
OMIT
U1000
BGA
(5 OF 8)
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
BGA
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
OMIT
U1000
BD30
BB28
BB30
B24
B22
H22
H24
F22
F24
D24
D22
M22
M24
K22
K24
V22
V24
T22
T24
P22
P24
AD22
AD24
AB22
AB24
Y22
Y24
AK22
AK24
AH22
AH24
AF22
AF24
AP22
AP24
AM22
AM24
AY22
AY24
AV22
AV24
AT22
AT24
BD22
BD24
BB22
BB24
B20
B18
B16
H20
F20
D20
H16
H18
F16
F18
D18
D16
M20
7 10 11 64
(CPU CORE POWER)
H32
G33
F32
N33
M32
L33
K32
J33
W33
V32
U33
T32
R33
P32
AD32
AC33
AB32
AA33
Y32
AK32
AJ33
AH32
AG33
AF32
AE33
AR33
AP32
AN33
AM32
AL33
AY32
AV32
AU33
AT32
AT34
BD32
BB32
B26
B30
B28
H26
F26
D26
H28
H30
F28
F30
D30
D28
M26
K26
M28
M30
K28
K30
V26
T26
P26
V28
V30
T28
T30
P28
P30
AD26
AB26
Y26
=PP1V05_S0_CPU
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
64 11 10 7
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
VSS
VSS
AE17
AE19
AR17
AR19
AN17
AN19
AL17
AL19
AW17
AW19
AU17
AU19
BC17
BC19
BA17
BA19
C15
C11
H10
G15
E15
M10
N15
L15
J15
M12
T10
W15
U15
R15
T12
AD10
Y10
AC15
AA15
AD12
Y12
AH10
AJ15
AG15
AE15
AH12
AM10
AR15
AN15
AL15
AM12
AT10
AW15
AU15
AY12
AW11
AW13
AV12
AT12
BC15
BA15
BC11
BB12
BA11
BA13
B6
H6
G9
F6
E9
D6
M6
M8
K6
K8
U5
V6
V8
T6
T8
P6
P8
AD6
AD8
AB6
AB8
PROVIDE A TEST POINT (WITH NO STUB)

TO CONNECT A DIFFERENTIAL PROBE
BETWEEN VCCSENSE AND VSSSENSE
CPU Power & Ground
SYNC_DATE=(MASTER)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
10
71
CPU VCORE HF AND BULK DECOUPLING

3x 330uF. 32x 10uF 0603, 28x 2.2uF 0402 + 40x 2.2uF 0402
64 10 7
=PPVCORE_S0_CPU
10UF 0603 = APN:138S0568 = MURATA,TAIYO,TDK,SAMSUNG

LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1200
C1201
C1202
C1203
C1204
C1205
C1206
C1207
C1208
C1209
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
CPU VCORE VID CONNECTIONS

CPU_VID<0..6>
65 50 10
IMVP6_VID<0..6>
65
MAKE_BASE=TRUE
LAYOUT NOTE:
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1210
C1211
C1212
C1213
C1214
C1215
C1216
C1217
C1218
C1219
20%
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20%
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1220
C1221
C1222
C1223
C1224
C1225
C1226
C1227
C1228
C1229
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
OMIT
10UF
10UF
10UF
10UF
10UF
10UF
OMIT
10UF
10UF
10UF
LAYOUT NOTE:
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20%
6.3V OMIT
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
LAYOUT NOTE:
CRITICAL
CRITICAL
C1230
C1231
20% OMIT
6.3V
X5R
603
20% OMIT
6.3V
X5R
603
10UF
10UF
VCCA (CPU AVdd) DECOUPLING

LAYOUT NOTE:
10 7
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1240
C1241
C1242
C1243
C1244
C1245
C1246
C1247
C1248
C1249
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
=PP1V5_S0_CPU
1x 10uF, 1x 0.01uF
C1280
20%
6.3V
CERM OMIT
402-LF
10uF
C1281
0.01UF
20%
OMIT
6.3V
X5R
603
10%
10V
X5R
201
LAYOUT NOTE:
PLACE C1281 NEAR PIN B34 OF U1000
B
LAYOUT NOTE:
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1250
C1251
C1252
C1253
C1254
C1255
C1256
C1257
C1258
C1259
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
12 10 9 7 6
VCCP (CPU I/O) DECOUPLING
=PP1V05_S0_CPU
1X 330UF, 12X 2.2UF
2.2UF
C1283
C1284
C1285
C1286
2.2UF
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
C1287
2.2UF
C1288
2.2UF
20%
2 6.3V
CERM OMIT
402-LF
LAYOUT NOTE:
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1260
C1261
C1262
C1263
C1264
C1265
C1266
C1267
2.2UF
CRITICAL
20%
6.3V OMIT
CERM
402-LF
20%
6.3V OMIT
CERM
402-LF
20%
6.3V OMIT
CERM
402-LF
20%
6.3V OMIT
CERM
402-LF
20%
6.3V OMIT
CERM
402-LF
20%
6.3V OMIT
CERM
402-LF
20%
6.3V OMIT
CERM
402-LF
20%
6.3V OMIT
CERM
402-LF
C1290 1
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
330UF
20%
2.5V
POLY-TANT
CASE-C2-SM
C1291
C1292
C1293
C1294
2.2UF
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
C1295
2.2UF
C1296
2.2UF
20%
2 6.3V
CERM OMIT
402-LF
LAYOUT NOTE:
PLACE C1290 CLOSE TO CPU
PLACE C1283-C1288 CLOSE TO FSB ADDRESS PINS
CPU Decoupling & VID
PLACE C1291-C1296 CLOSE TO FSB DATA PINS

LAYOUT NOTE:
CRITICAL
1
PLACE ON SAME SIDE AS CPU
CRITICAL
1
C1270
CRITICAL
1
C1271
LAYOUT NOTE:
C1272
330UF
330UF
330UF
20%
2.0V
POLY-TANT
D2T-SM1
20%
2.0V
POLY-TANT
D2T-SM1
20%
2.0V
POLY-TANT
D2T-SM1
SYNC_MASTER=MSARWAR
PLACE ON SAME SIDE AS CPU

Intel recommends 3x220UF @ 9mOHM

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
11
71
MCP79-specific pinout
12 7 6
12 11 10 9 7 6
=PP3V3_S0_XDP
=PP1V05_S0_CPU
XDP_CONN
CRITICAL
XDP
R1305 1
J1300
54.9
1%
1/20W
MF
201
D
65 9 6
BI
65 9 6
BI
65 9 6
65 9 6
IN
65 9 6
IN
OBSDATA_A0
OBSDATA_A1
XDP_BPM_L<1>
XDP_BPM_L<0>
6
6
6
6
XDP
OBSFN_A0
OBSFN_A1
XDP_BPM_L<3>
XDP_BPM_L<2>
IN
65 9 6
F-ST-SM
XDP_BPM_L<5>
XDP_BPM_L<4>
BI
OBSDATA_A2
OBSDATA_A3
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
OBSFN_B0
OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
OBSDATA_B0
OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
OBSDATA_B2
OBSDATA_B3
R1399
65 13 9
CPU_PWRGD
IN
1K
XDP_PWRGD
5%
1/20W
MF
201
IN
20 12
OUT
68 42 20 6
BI
68 42 20 6
BI
65 12 9 6
OUT
LTH-030-01-G-D-NOPEGS
2
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
XDP_OBS20
PM_LATRIGGER_L
JTAG_MCP_TCK
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
SDA
SCL
TCK1
TCK0
XDP_TCK
NC
10
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
From XDP connector

=PP3V3_S0_XDP
12 7 6
=PP1V05_S0_CPU
65 12 9 6
IN
65 12 9 6
IN
65 12 9 6
IN
65 12 9 6
IN
12 11 10 9 7 6
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST_L
MCP_DEBUG<0>
MCP_DEBUG<1>
BI
6 18 68
BI
6 18 68
OBSDATA_C2
OBSDATA_C3
MCP_DEBUG<2>
MCP_DEBUG<3>
BI
6 18 68
BI
6 18 68
OBSFN_D0
OBSFN_D1
JTAG_MCP_TDI
JTAG_MCP_TMS
OUT
6 12 20
OUT
6 12 20
OBSDATA_D0
OBSDATA_D1
MCP_DEBUG<4>
MCP_DEBUG<5>
BI
6 18 68
BI
6 18 68
OBSDATA_D2
OBSDATA_D3
MCP_DEBUG<6>
MCP_DEBUG<7>
BI
6 18 68
BI
6 12
6 12 20
6 18 68
IN
6 13 65
IN
6 13 65
XDP
R1303
1
OUT
IN
1K
FSB_CPURST_L
5%
1/20W
MF
201
6 9 24
IN
8 9 13 65
PLACEMENT_NOTE=Place close to CPU to minimize stub.
6 12
OUT
6 9 12 65
OUT
6 9 12 65
OUT
6 9 12 65
C1301
0.1UF
998-1571
10%
6.3V
X5R
201
To XDP connector
and/or level translator
U1000
CPU
XDP
R1313
65 9
XDP_TDO
XDP_TDO_CONN
5%
1/20W
MF
201
JTAG_ALLDEV
OBSDATA_C0
OBSDATA_C1
IN
OUT
XDP_PRESENT#
XDP
0.1uF
10%
6.3V
X5R
201
JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L
FSB_CLK_ITP_P
ITPCLK/HOOK4
FSB_CLK_ITP_N
ITPCLK#/HOOK5
VCC_OBS_CD
65 6 XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
XDP_TDO_CONN
TDO
XDP_TRST_L
TRSTn
XDP_TDI
TDI
XDP_TMS
TMS
XDP
C1300
OBSFN_C0
OBSFN_C1
C1316
OUT
6 12
XDP connector
0.1UF
10%
6.3V
2 X5R
201
JTAG_ALLDEV
C1311
0.1UF
10%
6.3V 2
X5R
201
R1311
10K
5%
1/20W
MF
201 2
11
JTAG_ALLDEV
U1400
MCP
VCCA VCCB
U1310
NLSV4T244
65 12 9 6
NO STUFF
R13121
0
IN
6
9
12
65
IN
XDP_TCK
XDP_TMS
XDP_TRST_L
JTAG_LVL_TRANS_EN_L
2
3
4
5
12
UQFN
A1
B1
A2
B2
A3
B3
JTAG_ALLDEV
A4
B4
JTAG_MCP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L
10
9
8
7
12 20
XDP
6 12 20
R1314
6 12 20
6 12 20
20
JTAG_MCP_TDO
5%
1/20W
MF
201
OE*
GND
JTAG_MCP_TDO_CONN
OUT
6 12
XDP connector
5%
1/20W
MF
201 2
IN
eXtended Debug Port (XDP)
SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
12
71
U1400
MCP79U
BGA
(1 OF 12)
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
22 21 13 8 7
=PP1V05_S0_MCP_FSB
R1410 1
B
65 40 9
IN
65 9
IN
R1415 1
54.9
62
1%
1/20W
MF
201
5%
1/20W
MF
201
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
65 9
BI
R1416
62
5%
1/20W
MF
201
65
65 9
65
65
65
65
65
65
NO STUFF
R1420
IN
IN
IN
NO STUFF
R1421
1K
1K
5%
1/20W
MF
201
5%
1/20W
MF
201
R1422
1K
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>
AA57 CPU_DSTBP1#
AB56 CPU_DSTBN1#
AE57 CPU_DBI1#
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
J53 CPU_DSTBP2#
H54 CPU_DSTBN2#
F56 CPU_DBI2#
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
K60 CPU_DSTBP3#
L59 CPU_DSTBN3#
G59 CPU_DBI3#
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
AH60
AM60
AN59
AL59
AR59
AT60
AK60
AV60
AV58
AW61
AR61
AW59
AT58
AU59
AU57
AP56
AM54
AY56
AP54
AY54
AM56
AK56
AN55
AL57
AR55
AV54
AW55
AN57
AR57
AT56
BA57
AV56
AW57
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
AP60 CPU_ADSTB0#
AT54 CPU_ADSTB1#
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
BI
NO STUFF
1
AC61 CPU_DSTBP0#
AB60 CPU_DSTBN0#
U61 CPU_DBI0#
FSB_ADS_L
FSB_BNR_L
9
BI
FSB_BREQ0_L
8
BI
65 FSB_BREQ1_L
FSB_DBSY_L
9
BI
FSB_DRDY_L
9
BI
FSB_HIT_L
9
BI
FSB_HITM_L
9
BI
FSB_LOCK_L
9
IN
FSB_TRDY_L
9
OUT
65 9
PM_THRMTRIP_L
CPU_FERR_L
BI
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>
OUT
65 50 40 9
OUT
CPU_PECI_MCP
CPU_PROCHOT_L
5%
1/20W
MF
201
=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_A32#
CPU_A33#
CPU_A34#
CPU_A35#
AJ61
AK58
AM58
AJ59
AN61
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
AH56
AH54
BB60
AV52
AK54
AJ57
AG55
AJ55
BG59
BD60
CPU_ADS#
CPU_BNR#
CPU_BR0#
CPU_BR1#
CPU_DBSY#
CPU_DRDY#
CPU_HIT#
CPU_HITM#
CPU_LOCK#
CPU_TRDY#
B60
BJ59
BL61
BH60
CPU_PECI
CPU_PROCHOT#
CPU_THERMTRIP#
CPU_FERR#
OMIT
FSB
65 9
E59 CPU_BSEL2
C61 CPU_BSEL1
C59 CPU_BSEL0
(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)
AG59
AD58
AE59
AA61
AF58
AC59
AG61
AF60
Y58
AA59
V58
U59
V60
AD60
W59
Y60
AF56
AC57
AB54
V56
AD54
AA55
AG57
AD56
V54
U55
T56
U57
W57
Y54
Y56
AC55
R55
R57
G57
L57
H56
J57
K56
E57
M54
P56
N57
J55
L55
T54
P54
M56
M60
P58
R59
P60
M58
R61
H60
H58
F60
T60
F58
J59
L61
J61
E61
N59
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
CPU_BPRI# AY60
CPU_DEFER# AF54
FSB_BPRI_L
FSB_DEFER_L
OUT
9 65
OUT
9 65
BCLK_OUT_CPU_P BP58
BCLK_OUT_CPU_N BN59
FSB_CLK_CPU_P
FSB_CLK_CPU_N
OUT
9 65
OUT
9 65
BCLK_OUT_ITP_P BT58
BCLK_OUT_ITP_N BU59
FSB_CLK_ITP_P
FSB_CLK_ITP_N
OUT
6 12 65
OUT
6 12 65
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
BCLK_OUT_NB_P BN61
BCLK_OUT_NB_N BP60
65
65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
BI
9 65
FSB_CLK_MCP_P
FSB_CLK_MCP_N
Loop-back clock for delay matching.
65 9
OUT
65 9
OUT
65 9
R1430
R1435
49.9
49.9
1%
1/20W
MF
201
1%
1/20W
MF
201
OUT
70 22
65
65
65
R1431 1
65
49.9
1%
1/20W
MF
201
1%
1/20W
MF
201
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
206
20
29
15
mAAR37
mAAR39
mAAR41
mAAR43
V1P1_DLLDLCELL_AVDD
V1P1_PLL_MCLK
V1P1_PLL_FSB
V1P1_PLL_CPU
BN57 BCLK_VML_COMP_VDD
BM56 BCLK_VML_COMP_GND
BU61 CPU_COMP_VCC
BL59 CPU_COMP_GND
R1436
49.9
PP1V05_S0_MCP_PLL_FSB
270 mA (A01)
BA59 CPU_RS0#
BA61 CPU_RS1#
BE61 CPU_RS2#
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
BCLK_IN_N BV60
BCLK_IN_P BW61
CPU_A20M#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_SMI#
BG61
BC59
BK60
BF60
BB58
BE59
CPU_PWRGD BR59
CPU_RESET# D60
CPU_SLP#
CPU_DPSLP#
CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#
BK58
BT60
BM60
BD58
BH58
CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L
OUT
9 65
OUT
9 65
OUT
9 65
OUT
8 9 65
OUT
8 9 65
OUT
9 65
=PP1V05_S0_MCP_FSB
7 8 13 21 22
NO STUFF
1
R1440
150
OUT
OUT
8 9 12 65
OUT
9 65
OUT
9 65
OUT
9 65
OUT
9 65
OUT
8 9 50 65
MCP CPU Interface
5%
1/20W
MF
201
SYNC_MASTER=M97
9 12 65

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
REV.
051-7631
2.3.0
OF
13
71
U1400
MCP79U
MCP79U
BGA
(2 OF 12)
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 28
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 27
BI
66 28
OUT
66 28
OUT
66 28
OUT
66 28
OUT
66 27
OUT
66 27
OUT
66 27
OUT
66 27
OUT
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
BN5
BM6
BL9
BN9
BP4
BL5
BL7
BM8
BV6
BU7
BV12
BT12
BU5
BT6
BU11
BT10
BM12
BN15
BN17
BL13
BN11
BP10
BM14
BP16
BU15
BT16
BU21
BT18
BU13
BT14
BU19
BV20
BT40
BV36
BV42
BT42
BU35
BV38
BU39
BU41
BN41
BM42
BN47
BP46
BP42
BP40
BN45
BP48
BT44
BU49
BV48
BT48
BU43
BV44
BT50
BV50
BR51
BU53
BV56
BT56
BT52
BU51
BU55
BU57
MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
BP6
BV8
BP12
BV14
BT38
BN43
BU45
BR53
MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0
BGA
(3 OF 12)
MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N
MEMORY PARTITION 0
66 28
OMIT
OMIT
U1400
BN7
BP8
BT8
BU9
BN13
BP14
BU17
BV18
BT36
BU37
BM44
BP44
BU47
BT46
BV54
BT54
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MRAS0# BN25
MCAS0# BP22
MWE0# BM24
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MBA0_2 BM26
MBA0_1 BP24
MBA0_0 BN27
MA0_14
MA0_13
MA0_12
MA0_11
MA0_10
MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>
BP28
BK26
BK24
BH28
BR23
BR27
BP26
BK28
BT26
BU27
BU23
BU25
BV24
BT24
BV26
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>
BI
28 66
66 30
BI
BI
28 66
66 30
BI
BI
28 66
66 30
BI
BI
28 66
66 30
BI
BI
28 66
66 30
BI
BI
28 66
66 30
BI
BI
28 66
66 30
BI
BI
28 66
66 30
BI
BI
27 66
66 30
BI
BI
27 66
66 30
BI
BI
27 66
66 30
BI
BI
27 66
66 30
BI
BI
27 66
66 30
BI
BI
27 66
66 30
BI
BI
27 66
66 30
BI
BI
27 66
66 30
BI
66 30
BI
66 30
BI
66 30
BI
66 30
BI
66 30
BI
OUT
27 28 33 66
66 30
BI
OUT
27 28 33 66
66 30
BI
OUT
27 28 33 66
66 30
BI
66 30
BI
66 30
BI
66 30
BI
66 30
BI
66 30
BI
OUT
27 28 33 66
66 30
BI
OUT
27 28 33 66
66 30
BI
OUT
27 28 33 66
66 30
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
OUT
27 28 33 66
OUT
27 28 33 66
OUT
27 28 33 66
OUT
27 28 33 66
OUT
BI
66 29
BI
66 29
BI
66 29
BI
27 28 33 66
OUT
27 28 33 66
OUT
27 28 33 66
OUT
27 28 33 66
OUT
27 28 33 66
OUT
27 28 33 66
OUT
27 28 33 66
OUT
66 29
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
27 28 33 66
OUT
27 28 33 66
OUT
27 28 33 66
OUT
27 28 33 66
MEMORY
CONTROL
0A
NC AC41
NC AC43
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
66 29
BI
MCLK0A_1_P BH30
MCLK0A_1_N BJ29
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
OUT
33
66 29
BI
OUT
33
66 29
BI
MCLK0A_0_P BJ33
MCLK0A_0_N BH32
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
66 29
27 28 33 66
BI
OUT
OUT
27 28 33 66
MCS0A_1# BT20
MCS0A_0# BN23
MEM_A_CS_L<1>
MEM_A_CS_L<0>
MODT0A_1 BP20
MODT0A_0 BN21
MEM_A_ODT<1>
MEM_A_ODT<0>
MCKE0A_1 BR21
MCKE0A_0 BT22
MEM_A_CKE<1>
MEM_A_CKE<0>
66 29
BI
66 29
BI
OUT
27 28 33 66
66 30
OUT
OUT
27 28 33 66
66 30
OUT
66 30
OUT
OUT
27 28 33 66
66 30
OUT
OUT
27 28 33 66
66 29
OUT
66 29
OUT
OUT
27 28 33 66
66 29
OUT
OUT
27 28 33 66
66 29
OUT
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
BW1
BN3
BP2
BW3
BU1
BN1
BY2
BV2
CA5
BY4
BY10
CA11
BW5
CA3
BY6
BW9
BY16
BY12
BW19
BY18
BW11
CA15
BW15
BW17
BY24
CA21
BW27
BW25
BY20
CA23
BY26
BW23
BW31
BW33
BY34
CA35
CA29
BY28
BW35
CA33
BY36
BY38
BW41
BY44
BW43
BW37
CA41
BY42
BW45
BW47
BW51
BY52
BY46
CA45
CA51
CA47
CA59
BW53
BY58
BW59
CA53
BY54
CA57
BW57
MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
BU3
CA9
CA17
CA27
BY32
CA39
BY48
BY60
MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0
MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N
MEMORY PARTITION 1
BR3
BT2
BY8
BW7
BY14
BW13
BY22
BW21
BY30
BW29
BY40
BW39
BW49
BY50
BW55
BY56
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MRAS1# BM30
MCAS1# BK30
MWE1# BN31
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MBA1_2 BK34
MBA1_1 BP32
MBA1_0 BM32
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
BK36
BU31
BP36
BN33
BV32
BU33
BR35
BN35
BM36
BT34
BP34
BR33
BK32
BT32
BV30
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
BI
30 66
BI
30 66
BI
30 66
BI
30 66
BI
30 66
BI
30 66
BI
30 66
BI
30 66
BI
29 66
BI
29 66
BI
29 66
BI
29 66
BI
29 66
BI
29 66
BI
29 66
BI
29 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
OUT
29 30 33 66
MEMORY
CONTROL
1A
NC AD42
NC AD44
MCLK1A_1_P BJ17
MCLK1A_1_N BH18
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
33
OUT
33
MCLK1A_0_P BH20
MCLK1A_0_N BJ21
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT
29 30 33 66
OUT
29 30 33 66
MCS1A_1# BN37
MCS1A_0# BM38
MEM_B_CS_L<1>
MEM_B_CS_L<0>
OUT
29 30 33 66
OUT
29 30 33 66
MODT1A_1 BN39
MODT1A_0 BH34
MEM_B_ODT<1>
MEM_B_ODT<0>
OUT
29 30 33 66
OUT
29 30 33 66
MCKE1A_1 BK38
MCKE1A_0 BP38
MEM_B_CKE<1>
MEM_B_CKE<0>
OUT
29 30 33 66
OUT
29 30 33 66
MCP Memory Interface
SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
14
71
OMIT
U1400
MCP79U
D
8
8
8
8
8
8
8
8
66 22 15 7
70 22
TP_MEM_A_CLK4P
TP_MEM_A_CLK4N
BJ39 MCLK0B_1_P
BH38 MCLK0B_1_N
TP_MEM_A_CLK3P
TP_MEM_A_CLK3N
BJ35 MCLK0B_0_P
BH36 MCLK0B_0_N
TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>
BM20 MCS0B_0#
BN19 MCS0B_1#
TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>
BK18 MODT0B_0
BM18 MODT0B_1
TP_MEM_A_CKE<2>
TP_MEM_A_CKE<3>
BK20 MCKE0B_0
BP18 MCKE0B_1
NC AD46
NC AE41
R1610 1
40.2
TP_MEM_B_CLK4P
TP_MEM_B_CLK4N
MCLK1B_0_P BH24
MCLK1B_0_N BJ23
TP_MEM_B_CLK3P
TP_MEM_B_CLK3N
MCS1B_0# BT30
MCS1B_1# BN29
TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>
MODT1B_0 BP30
MODT1B_1 BT28
TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>
MCKE1B_0 BU29
MCKE1B_1 BR29
TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>
17
12
19
39
mA
mA
mA
mA
Y38
W41
W39
V42
V1P1_PLL_XREF_XS
V1P1_PLL_DP
V1P1_PLL_CORE
V1P1_PLL_V
MRESET0# J27
66
BP56 MEM_COMP_1P8V
BR57 MEM_COMP_GND
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
40.2
A13
A19
A25
A31
A37
A43
A49
A55
A61
A7
AB10
AB4
AB52
AB58
AC19
AC21
AC23
AC25
AC27
AC29
AC31
AC33
AC35
AC37
AC39
AD16
AD48
AE1
AE13
AE19
AE21
AE23
AE25
AE27
AE29
AE31
AE33
AE35
AE37
AE39
AE43
AE49
AE55
AE61
AE7
AF16
AF48
AG13
AG19
AG21
AG23
AG25
AG27
AG29
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
V1P8_MEM_VDDP
R1611 1
1%
1/20W
MF
201
8
8
8
8
8
8
8
8
8
8
TP or NC for DDR2.
MCP_MEM_RESET_L
OUT
66
MCLK1B_1_P BJ27
MCLK1B_1_N BH26
PP1V05_S0_MCP_PLL_CORE
87 mA (A01)
1%
1/20W
MF
201
MEMORY CONTROL 1B
AF42 NC
AF44 NC
MEMORY CONTROL 0B
BGA
(4 OF 12)
BD12
BD14
BD16
BD18
BD20
BD24
BD26
BD28
BD30
BD32
BD34
BD36
BD38
BD42
BD44
BF12
BF14
BF18
BF20
BF24
BF26
BF30
BF32
BF36
BF38
BF42
BF44
26
7 15 22 66
4771 mA (A01, DDR3)
AR23
AR25
AR27
AR29
AR31
AR33
AR35
AR53
AT10
NC AT16
AT18
AT20
AT24
AT26
AT28
AT32
AT34
AT42
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
AG31
AG33
AG35
AG37
AG39
AH10
AH12
AH16
AH4
AH46
MCP Memory Misc

SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
15
71
OMIT
U1400
MCP79U
BGA
(5 OF 12)
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
34
AA3
AB2
U3
U1
AC1
AC3
R5
P4
AM2
AN1
AJ1
AJ3
AK2
AL3
AA5
AB6
AU3
AT2
AJ5
AK6
AP6
AM6
AP2
AN3
AY2
AW3
AR5
AT4
AV6
AW5
BE1
BD2
=PEG_D2R_P<0>
=PEG_D2R_N<0>
=PEG_D2R_P<1>
=PEG_D2R_N<1>
=PEG_D2R_P<2>
=PEG_D2R_N<2>
=PEG_D2R_P<3>
=PEG_D2R_N<3>
=PEG_D2R_P<4>
=PEG_D2R_N<4>
=PEG_D2R_P<5>
=PEG_D2R_N<5>
=PEG_D2R_P<6>
=PEG_D2R_N<6>
=PEG_D2R_P<7>
=PEG_D2R_N<7>
=PEG_D2R_P<8>
=PEG_D2R_N<8>
=PEG_D2R_P<9>
=PEG_D2R_N<9>
=PEG_D2R_P<10>
=PEG_D2R_N<10>
=PEG_D2R_P<11>
=PEG_D2R_N<11>
=PEG_D2R_P<12>
=PEG_D2R_N<12>
=PEG_D2R_P<13>
=PEG_D2R_N<13>
=PEG_D2R_P<14>
=PEG_D2R_N<14>
=PEG_D2R_P<15>
=PEG_D2R_N<15>
Int PU
M12 PE0_PRSNT_16#
PEG_PRSNT_L
IN
Int PU
C5 PEB_CLKREQ#
MINI_CLKREQ_L
IN
PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N
PCI EXPRESS
AW19 NC
Int PU
J9 PEC_CLKREQ#
TP_FW_CLKREQ_L
AW21 NC
Int PU
TP_EXCARD_CLKREQ_L
TP_PCIE_EXCARD_PRSNT_L
H8 PED_CLKREQ#
TP_FC_CLKREQ_L
TP_PCIE_FC_PRSNT_L
E7 PEE_CLKREQ#
E5 PEE_PRSNT#
D6 PED_PRSNT# Int PU
Int PU
Int PU
Int PU
A3 PEF_CLKREQ#
B2 PEF_PRSNT#
TP_MCP_GPIO_17
EXTGPU_PWR_EN
OUT
Int PU
IN
OUT
PEG_CLKREQ_L
EXTGPU_RESET_L
Int PU
B4 PEG_CLKREQ#
A5 PEG_PRSNT#
Int PU
AA1
Y2
V2
W3
V4
Y4
R3
T2
AF4
AD4
AD2
AE3
AH2
AG3
AG1
AF2
AM4
AN5
AR1
AR3
AW1
AV2
AK4
AL5
AR7
AT6
BA1
BA3
AU5
AV4
BC3
BB2
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PE0_REFCLK_P E3
PE0_REFCLK_N E1
PEG_CLK100M_P
PEG_CLK100M_N
OUT
8 67
OUT
8 67
PE1_REFCLK_P H4
PE1_REFCLK_N F4
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
OUT
34 67
OUT
34 67
PE2_REFCLK_P J5
PE2_REFCLK_N H6
TP_PCIE_CLK100M_FW_P
TP_PCIE_CLK100M_FW_N
PE3_REFCLK_P F6
PE3_REFCLK_N G5
TP_PCIE_CLK100M_EXCARD_P
TP_PCIE_CLK100M_EXCARD_N
PE4_REFCLK_P D2
PE4_REFCLK_N C1
TP_PCIE_CLK100M_FC_P
TP_PCIE_CLK100M_FC_N
NC AW23
NC AW25
NC AW27
NC AW29
34 6
IN
PCIE_WAKE_L
PEX_RST0# J17
PCIE_RESET_L
OUT
24
67 34
IN
PE1_TX0_P M2
PE1_TX0_N N3
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
34 67
IN
M4 PE1_RX0_P
N5 PE1_RX0_N
OUT
67 34
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
OUT
34 67
TP_PCIE_FW_D2R_P
TP_PCIE_FW_D2R_N
J3 PE1_RX1_P
K2 PE1_RX1_N
PE1_TX1_P L1
PE1_TX1_N L3
TP_PCIE_FW_R2D_C_P
TP_PCIE_FW_R2D_C_N
TP_PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_D2R_N
P2 PE1_RX2_P
R1 PE1_RX2_N
PE1_TX2_P M6
PE1_TX2_N P6
TP_PCIE_EXCARD_R2D_C_P
TP_PCIE_EXCARD_R2D_C_N
TP_PCIE_FC_D2R_P
TP_PCIE_FC_D2R_N
G3 PE1_RX3_P
F2 PE1_RX3_N
PE1_TX3_P J1
PE1_TX3_N H2
TP_PCIE_FC_R2D_C_P
TP_PCIE_FC_R2D_C_N
B
IN
IN
J19 PE_WAKE# Int PU (S5)
PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N
57 mA (A01)
AA13
AA7
AD14
AF14
W9 V1P1_PEX_DVDD0
Y10
Y12
Y8
T6 V1P1_PEX_DVDD1
U7 V1P1_PEX_DVDD1
V14 V1P1_PLL_PEX
PP1V05_S0_MCP_PLL_PEX
70 22
84 mA (A01)
67
AA9
AB8
AC13
AC9
AD10
AD12
AD8
V1P1_PEX_AVDD0
AE9
AF10
AF12
AF8
AG9
C3 PEX_CLK_COMP
MCP_PEX_CLK_COMP
B
OUT
OUT
206 mA (A01)
N11
V1P1_PEX_AVDD1 N9
P10
MCP PCIe Interfaces
NO STUFF
SYNC_MASTER=M97
2.37K
R1710
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX
1%
1/20W
MF
201

PLACEMENT_NOTE=Place within 12.7mm of U1400

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
16
71
OMIT
U1400
MCP79U
BGA
(6 OF 12)
IN
IN
IN
IN
IN
IN
A33
J29
A35
C31
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
R1810 1
PP1V05_ENET_MCP_PLL_MAC
70 22
V30
BUF_25MHZ B30
OUT
41
IN
OUT
Interface Mode
MCP Signal
TMDS/HDMI
DisplayPort
=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N
DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

NOTE: 20K pull-down required on DP_HOTPLUG_DET.
NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.
F26 XTALIN_TV
E27 XTALOUT_TV
MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT
TV
C
Y
Comp
/
/
/
/
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
IN
Interface
ENET_TXD<0>
RGMII
MII
8
8
8
8
ENET_CLK125M_TXCLK
ENET_TX_CTRL
ENET_MDC
ENET_MDIO
OUT
OUT
NOTE: All Apple products set strap to

MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.
BI
ENET_PWRDWN_L
MCP_CLK25M_BUF0_R
ENET_RESET_L
=PP3V3_S0_MCP_GPIO
R1860 1
100K
5%
1/20W
MF
201
BA33
7 18 20
R1861
100K
5%
1/20W
MF
201
MCP_DDC_CLK0
MCP_DDC_DATA0
NC
NC
NC
BA31
RGB DAC Disable:
BA29
BA27
Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.
NC
NC
BA25
BA23
Component
TV_DAC_RED F54
Pr
Y
TV_DAC_GREEN E55
Pb
TV_DAC_BLUE D56
TV_DAC_HSYNC A47
TV_DAC_VSYNC E41
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
TV DAC Disable:
OUT
OUT
OUT
CRT_IG_HSYNC
CRT_IG_VSYNC
OUT
OUT
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
OUT
59 67
OUT
59 67
OUT
6 59 67
OUT
6 59 67
OUT
6 59 67
OUT
6 59 67
OUT
6 59 67
OUT
6 59 67
OUT
8 67
OUT
8 67
OUT
8 67
OUT
8 67
OUT
8 67
OUT
8 67
OUT
8 67
OUT
8 67
OUT
8 67
OUT
8 67
OUT
8 67
OUT
8 67
6 59
Okay to float all TV_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.
IN
63
OUT
63 62
OUT
59
OUT
60
OUT
60
OUT
60
OUT
60
OUT
60
OUT
60
OUT
60
OUT
60
OUT
67 60
OUT
67 60
OUT
IN
60
IN
LVDS:
Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
H18 GPIO_6
F16 GPIO_7
LPCPLUS_GPIO
DP_IG_CA_DET
BI
60
H52 TV_DAC_RSET
J51 TV_DAC_VREF
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
RGB ONLY
OUT
DACS
MCP_MII_VREF
BA35
DDC_CLK0 C43
DDC_DATA0 F40
47K
5%
1/20W
MF
201
NC
NC
AW39 NC
AW41 NC
=PP3V3_S5_MCP_GPIO
R1820
MII_RESET# B32
20 19 7
RGMII_PWRDWN C35
E33 MII_COMP_VDD
H32 MII_COMP_GND
49.9
1%
1/20W
MF
201
E31
D32
J31
B34
MII_MDC F28
MII_MDIO E29
V1P1_DUAL_MACPLL
5 mA (A01)
7 22
131 mA (A01)
W29
MII_TXCLK F32
MII_TXEN C33
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
R1811
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
J37 LCD_BKL_CTL
C45 LCD_BKL_ON
D44 LCD_PANEL_PWR
LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
F50 HDMI_TXC_P
E51 HDMI_TXC_N
=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>
E53
F52
C53
B54
J47
H48
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
J49 DP_AUX_CH0_P
H50 DP_AUX_CH0_N
=DVI_HPD_GMUX_INT
=MCP_HDMI_HPD
D42 HPLUG_DET2
B46 HPLUG_DET3
23 7
N41 VAP8_IFPA_VDD_0
P38 V1P8_IFPB_VDD_1
190 mA (A01, 1.8V)

PP3V3_S0_MCP_VPLL
70 23
16 mA (A01)
23 7
67 23
67 23
=PP1V05_S0_MCP_HDMI_VDD
95 mA (A01)
MCP_HDMI_RSET
OUT
MCP_HDMI_VPROBE
OUT
HDMI_TXD0_P
HDMI_TXD0_N
HDMI_TXD1_P
HDMI_TXD1_N
HDMI_TXD2_P
HDMI_TXD2_N
8 mA
8 mA
T38 V3P3_PLL_IFPAB
T44 V3P3_PLL_HDMI
T42 V1P1_HDMI_VDD
A59 HDMI_RSET
A57 HDMI_VPROBE
IFPA_TXC_P E49
IFPA_TXC_N F48
FLAT PANEL
1%
1/20W
MF
201
V28
Network Interface Select
H28 RGMII_INTR
ENET_INTR_L
IN
49.9
V1P0_DUAL_RMGT
V1P0_DUAL_RMGT
7 17 22
83 mA (A01)
BA19
MII_VREF B36
NC
NC
NC
AW33
AW35
P28
G29 MII_RXCLK
D30 MII_RXDV
ENET_CLK125M_RXCLK
ENET_RX_CTRL
AW31
22 17 7
LAN
V3P3_DUAL_RMGT
NC
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
J43
H44
E47
F46
C51
B52
J45
H46
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

IFPB_TXC_P F42
IFPB_TXC_N E43
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
J41
H42
E45
F44
C47
B48
J39
H40
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
DDC_CLK2 G39
DDC_DATA2 H38
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
OUT
DDC_CLK3 B44
DDC_DATA3 A45
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
OUT
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
OUT
23 67
OUT
23 67
IFPAB_RSET A51
IFPAB_VPROBE B50
BI
BI
6 59
60
60
MCP Ethernet & Graphics
SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
17
71
OMIT
U1400
20 17 7
=PP3V3_S0_MCP_GPIO
MCP79U
BGA
(7 OF 12)
68 18
68 18
18
8
18
OUT
OUT
IN
68 12 6
BI
68 12 6
BI
68 12 6
BI
68 12 6
BI
68 12 6
BI
68 12 6
BI
68 12 6
BI
68 12 6
BI
PCI_REQ0_L
PCI_REQ1_L
CRTMUX_SEL_TV_L
AUD_IPHS_SWITCH_EN
MCP_RS232_SIN_L
MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
AJ9
AD6
AH6
AP8
AC5
BC5
BK4
BE5
BH4
BE3
BA5
BJ3
BJ5
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
NC
NC
PCI_GNT2#
PCI_GNT3#
PCI_GNT4#
BE57
18
BE9
AE5
AC7
AF6
TP_LVDSMUX_SEL_IG_L
TP_DPMUX_SEL_IG_L
MCP_RS232_SOUT_L
OUT
68 18
OUT
OUT
68 18
18
18
BE53
BD8
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
18
MCP_RS232_SOUT_L
RP1900
8.2K
6
5%
1/32W
PCI_REQ0_L
PCI_REQ1_L
CRTMUX_SEL_TV_L
RP1900
RP1901
RP1901
8.2K
8.2K
8.2K
8 5%
1/32W
4X0201-HF
7 5%
1/32W
4X0201-HF
5%
1/32W
4X0201-HF
5%
1/32W
4X0201-HF
MCP_RS232_SIN_L
RP1901
8.2K
4X0201-HF
BD56
FIXME: ADJUST PINOUT PER LAYOUT
BD52
BD48
BC57
NC
BC9
BD50
BD54
BC53
BB8
BB6
BD6
BE49
BE55
PCI
BB56
BB54
BB52
BB50
BB48
BB46
BB44
BB42
BA53
FIXME: USED TO BE PM_LATRIGGER_L
Int PU (S5)
PCI_RESET0# G17
PCI_RESET1# G21
MEM_VTT_EN_R
TP_PCI_RESET1_L
OUT
24
BB38
BB36
BB34
BB32
BB30
PCI_CLK0 AM10
NC BE7
PCI_CLK2 AG5
NC
TP_PCI_CLK0
68
PCI_CLK33M_MCP_R
BB28
1
BB26
BB24
R1910
22
BB20
BB10
BA9
PCI_CLKIN AG7
68
PCI_CLK33M_MCP
41
LPC_FRAME_R_L
LPC_PWRDWN_L
5%
1/20W
MF
201
PLACEMENT_NOTE=Place close to pin R8
BA7
BA55
BA49
BA43
BA41
LPC_FRAME# AJ7
LPC_PWRDWN# AL9
R1960
22
LPC_FRAME_L
2
5%
1/20W
MF
201
OUT
39 41 68
OUT
39 41
OUT
24 68
41 39
41 39
BI
AH8 PCI_CLKRUN#
PM_CLKRUN_L
IN
FW_PME_L
TP_LPC_DRQ0_L
LPC_SERIRQ
AN9 LPC_DRQ1#
AN7 LPC_DRQ0#
AT8 LPC_SERIRQ
Int PU
LPC
BA39
LPC_RESET0# E17
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_RESET_L
AM8
AK8
AK10
AR9
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
Int PU
Int PU
LPC_CLK0 BB4
GND
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
22
22
22
22
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
1/20W
MF
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
AL7
AM16
AM48
AN13
AN19
AN21
AN23
AN25
AN27
AN29
AN31
AN33
AN35
AN37
AN39
AN53
AP10
AP12
AP16
AP4
AP42
AP44
AP46
AP48
AP52
AP58
AT14
AT30
AT36
AT38
AT48
AU1
AU13
BI
39 41 68
BI
39 41 68
BI
39 41 68
BI
201
LPC_CLK33M_SMC_R
1
AH48
AH52
AH58
AJ19
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AJ33
AJ35
AJ37
AJ39
AK16
AK48
AL1
AL13
AL19
AL21
AL23
AL25
AL27
AL29
AL31
AL33
AL35
AL37
AL39
AL43
AL49
AL55
AL61
R1961
R1962
R1963
R1964
OUT
39 41 68
24 68
R1965
10K
5%
1/20W
MF
201
Strap for Boot ROM Selection (See HDA_SDOUT)
MCP PCI & LPC

SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
18
71
OMIT
U1400
MCP79U
BGA
(8 OF 12)
67 36
OUT
67 36
OUT
67 36
IN
67 36
IN
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_D2R_N
SATA_HDD_D2R_P
USB0_P F36
USB0_N E37
BH2 SATA_A0_TX_P
BG3 SATA_A0_TX_N
BG1 SATA_A0_RX_N
BF2 SATA_A0_RX_P
OUT
8
8
IN
IN
BL1 SATA_A1_TX_P
BK2 SATA_A1_TX_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
BL3 SATA_A1_RX_N
BM2 SATA_A1_RX_P
BK44
BK16
BK12
BJ9
BJ53
BJ45
BJ11
BH8
USB3_P C41
USB3_N B42
NC
NC
NC
NC
8 68
BI
8 68
BI
8 68
BI
8 68
BI
8 68
USB_CAMERA_P
USB_CAMERA_N
BI
8 68
BI
8 68
USB_IR_P
USB_IR_N
BI
8 68
BI
8 68
IR
USB4_P F38
USB4_N E39
NC
NC
NC
NC
8 68
BI
Camera
SATA
USB
OUT
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
BI
AirPort (PCIe Mini-Card)

USB_MINI_P
USB1_P E35
F34
USB_MINI_N
USB1_N
External D
USB_EXTD_P
USB2_P B38
USB_EXTD_N
USB2_N C37
D
8
External A
USB_EXTA_P
USB_EXTA_N
USB5_P J35
USB5_N H36
Wellspring Trackpad/Keyboard
USB_TPAD_P
USB_TPAD_N
BI
8 68
BI
8 68
USB6_P B40
USB6_N C39
Bluetooth
USB_BT_P
USB_BT_N
BI
8 68
BI
8 68
BI
8 68
BI
8 68
External B
USB_EXTB_P
USB7_P H34
J33
USB_EXTB_N
USB7_N
NC BL49
NC BK8
=PP3V3_S5_MCP_GPIO
NC BK56
NC BK52
8.2K
NC BK48
NC BK50
BH6
BH56
BH54
BH52
BH50
BH48
BH46
BH16
NC
NC
R2050
NC BK54
NC BK6
NC
NC
NC
NC
NC
NC
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26
USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO
F24
H24
E25
J23
V3P3_PLL_USB V36
R2051
R2053
8.2K
5%
1/20W
MF
201
R2052
8.2K
8.2K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L
PP3V3_S0_MCP_PLL_USB
7 17 20
IN
IN
IN
IN
22 70
19 mA (A01)
USB_RBIAS_GND A41
68
MCP_USB_RBIAS_GND
R2060 1
E9 SATA_LED#
PP1V05_S0_MCP_PLL_SATA
84 mA (A01)
70 22
AP14
V1P1_PLL_SATA
BK46
BH10
NC
BG9
BG7
22 7
=PP1V05_S0_MCP_SATA_DVDD
43 mA (A01)
AV12
AW13
V1P1_SATA_DVDD1
V1P1_SATA_DVDD1
BG53
BG5
BF8
BF6
BF56
BF54
NC
BF50
BF48
BJ41
PP1V05_S0_MCP_SATA_AVDD
70 22
127 mA (A01)
AR13
AT12
AV10
AW9
67
MCP_SATA_TERMP
V1P1_SATA_AVDD1
AW7 SATA_TERMP
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
AU19
AU25
AU31
AU37
AU43
AU49
AU55
AU61
AU7
AU9
AV14
AV8
AY10
AY4
AY52
AY58
BB12
BB14
BB16
BB18
BC1
BC13
BC19
BC21
BC23
BC25
BC27
BC29
BC31
BC33
806
1%
1/20W
MF
201
R2010
2.49K
1%
1/20W
MF
201
MCP SATA & USB
SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
19
71
OMIT
U1400
=PP3V3R1V5_S0_MCP_HDA
MCP79U
7 20 22
BGA
(9 OF 12)
7 mA (A01)
HDA
V3P3_DUAL_HDA P20
V3P3_DUAL_HDA T20
D
68 35 6
20
20
22 20 7
F14 HDA_SDATA_IN0
Int PD
HDA_SDIN0
IN
J15
MLB_RAM_SIZE_0
IN
HDA_RESET# A11
41
1%
1/20W
MF
201
OUT
IN
R2121
49.9K
HDA_RST_L
OUT
35 68
HDA_SYNC
OUT
6 35 68
5%
1/20W
MF
201
40 39 8
49.9K
22
6 35 68
5%
1/20W
MF
201
R2173
PP3V3_G3_RTC
22
OUT
R2172
1
HDA_SYNC_R
68 20
6 35 68
BIOS Boot Select

HDA_BIT_CLK
HDA_RST_R_L
68 20
HDA_SYNC E13
B12 HDA_PULLDN_COMP
MCP_HDA_PULLDN_COMP
1%
1/20W
MF
201
39
IN
39
IN
B16
D14
MCP_GPIO_4
AUD_I2C_INT_L
SLP_S3# C19
SLP_RMGT# H16
SLP_S5# C17
PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L
GPIO_4
GPIO_5
20 mA
17 mA
AP20
V1P1_PLL_NV_H
V1P1_PLL_SP_SPREF
AP18
C21
J25
=SPI_CS1_R_L_USE_MLB
SMC_ADAPTER_EN
GPIO_1
GPIO_12
TP_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
SMC_RUNTIME_SCI_L
B6
C7
C23
F20
SM_INTRUDER_L
C29 INTRUDER#
THERM_DIODE_P E11
THERM_DIODE_N G11
Int PU
A20GATE
KBRDRSTIN# Int PU
SIO_PME#
Int PU (S5)
EXT_SMI/GPIO_32# Int PU (S5)
MCP_THMDIODE_P
MCP_THMDIODE_N
20
IN
20
OUT
6 34 35 39 56
OUT
57
OUT
34 39 40 56
IN
IN
PM_DPRSLPVR
D12 CPU_DPRSLPVR
39
IN
24
IN
PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
F18 PWRBTN# Int PU (S5)

D18 RSTBTN# Int PU
RTC_RST_L
A29 RTC_RST#
G27 PWRGD_SB
A23 PS_PWRGD
24
IN
PM_RSMRST_L
MCP_PS_PWRGD
24
IN
MCP_CPU_VLD
D20 CPU_VLD
JTAG_MCP_TDI
JTAG_MCP_TDO
JTAG_MCP_TMS
JTAG_MCP_TRST_L
JTAG_MCP_TCK
J21
B22
F22
E21
H22
MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT
B26 XTALIN
C25 XTALOUT
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
B28 XTALIN_RTC
C27 XTALOUT_RTC
39
12 6
12
IN
IN
OUT
12 6
IN
12 6
IN
12
IN
B
24
IN
24
OUT
24
IN
24
OUT
R21511
B8
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
F12
C11
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT#/GPIO_64
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN
FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62
A9
B10
D8
C9
MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT
CPUVDD_EN E19
JTAG_TDI Int PU
JTAG_TDO
JTAG_TMS Int PU
JTAG_TRST#
JTAG_TCK
OUT
45
OUT
45
OUT
20 51
OUT
20 51
OUT
20 51
GPIO_10
GPIO_11
GPIO_8
GPIO_9
OUT
BI
OUT
BI
=PP3V3_S0_MCP
1
E15
C15
SUS_CLK/GPIO_34 H20
BUF_SIO_CLK BD4
6 12 42 68
=PP3V3_S0_MCP_GPIO
5%
1/20W
MF
For EMI Reduction on HDA interface
2 201
HDA_SDOUT_R
HDA_BIT_CLK_R
HDA_RST_R_L
HDA_SYNC_R
C2170
C2172
33PF
10PF
5%
25V
NP0-C0G
201
5%
25V
NPO
201
C2171
10K
R2141
10K
5%
1/20W
MF
2 201
7 21
22
NOTE: MCP79 rev A01 does not support

SPI1 option.
42 68
OUT
20 34
IN
20 39
Frequency
R2181
14.31818 MHz
SPI Frequency Select
20 68
20 68
SPI_DO
SPI_CLK
42 MHz
25 MHz
1 MHz
31 MHz
0
2 MCP_SAFE_MODE
20
OUT
24
OUT
41 68
OUT
41 68
IN
39
5%
1/20W
MF
201
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE
IN
41 68
OUT
41 68
OUT
24 68
NOTE: Straps not provided on this page.
B
=PP3V3_S5_MCP_GPIO
1K
5%
1/20W
MF
201
1%
1/20W
MF
201
1DRAM_4GB
R2190
10K
1DRAM_SPD_2
R2195
R2197
1K
20
MLB_RAM_SIZE_0
20
MLB_RAM_VENDOR_0
1K
5%
1/20W
MF
201
5%
1/20W
MF
2 201
7 17 18
=PP3V3_S3_MCP_GPIO
R2158
5%
1/20W
MF
201
100K
5%
1/20W
MF
2 201
20
20 39
20
34 20
AP_PWR_EN
MCP HDA & MISC
8 20
20 68
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
ARB_DETECT
20
20 51
SYNC_MASTER=M97
20 51
20 51
2
1
C2173
33PF
10PF
5%
25V
NP0-C0G
201
5%
25V
NPO
201
R2147
R2155
R2156
100K
22K
22K
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201

R2157
22K
5%
1/20W
MF
201

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7631
SCALE
SHT
NONE
7 17 19
R2142
AUD_I2C_INT_L
MEM_EVENT_L
MCP_GPIO_4
SMC_IG_THROTTLE_L
20 68
HDA_SYNC
24 MHz
5%
1/20W
MF
201
R2182
R2163
10K
5%
1/20W
MF
201
BUF_SIO_CLK Frequency
5%
1/20W
MF
201
MCP_TEST_MODE_EN
R2143
10K
6 12 42 68
42 68
8 20
PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK
TEST_MODE_EN A21
PKG_TEST H26
R2180
10K
SPI1
Frequency
SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R
G15
A15
R2140
SPI0
10K
MCP_CPUVDD_EN
BOOT_MODE_USER
A17
B18
E23
G23
B24
HDA Output Caps
MCP_SPKR
R2150 1
100K
PCI
NOTE: MCP79 does not support FWH, only

LPC ROMs. So Apple designs will
not use LPC for BootROM override.
MISC
39
65 50
LPC_FRAME#
R1961 and R2160 selects SPI0 ROM by

default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.
A27 LID# Int PU (S5)

B20 LLB# Int PU (S5)
HDA_SDOUT
LPC
BOOT_MODE_SAFE
GPIO_13
GPIO_14
GPIO_15
SPKR H12
TP_MCP_LID_L
PM_BATLOW_L
I/F
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

OUT
PP1V05_S0_MCP_PLL_NV
37 mA (A01)
OUT
5%
1/20W
MF
201
5%
1/20W
MF
201
GPIO_3
Int PD
HDA_SDOUT
22
HDA_BIT_CLK_R
68 20
22
R2171
HDA_BITCLK C13
R2170
HDA_SDOUT_R
68 20
1%
1/20W
MF
201
70 22
R2120 1
5%
1/20W
MF
201
R2110
68
24 21
8.2K
HDA_SDATA_OUT H14
49.9
R2160
GPIO_2
Int PD
B14
MLB_RAM_VENDOR_0
IN
2.3.0
OF
20
71
7
OMIT
OMIT
U1400
22 7
23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)
BGA
BGA
(10 OF 12)
=PPVCORE_S0_MCP
MCP79U
(12 OF 12)
=PP1V05_S0_MCP_FSB
7 8 13 22
AA19
AA49
AA21
AA23
AA53
AC49
AA25
AC53
AA27
AA29
AD50
AD52
AA31
AA33
AE53
AF50
AG43
AH14
AA35
AF52
AT44
AA37
AA39
AG49
AG53
AT46
AT52
AH50
AU21
AJ49
AJ53
AU23
AU27
AK50
AU33
AU35
AD18
AD20
AD24
POWER
AD26
AD28
AD30
AD32
AD34
AD38
AF18
AF20
VDD
AD36
AF24
AF26
V1P2_CPU_VTT
D52
D58
G1
G13
G19
G25
G31
G37
G43
G49
G55
G61
G7
K10
K16
K22
K28
K34
K4
K40
K46
K52
K58
M10
M20
M24
N1
N13
N17
N19
N25
N27
N29
N31
N33
N35
N37
N43
N49
N55
N61
N7
P42
P50
P8
R7
R9
T10
T16
T18
T28
T34
T36
T4
T46
T48
T52
T58
T8
U13
V10
V24
V34
V38
V48
V52
V8
W1
W13
W19
W25
W27
W31
W37
W43
W49
W53
W55
W61
W7
Y14
Y28
Y42
Y48
Y6
1139 mA
1182 mA (A01)
G51
G53
G9
AG41
AK52
AL53
J11
J13
J7
K12
K14
K18
K20
K24
K26
AU39
K30
K32
AM50
AM52
AU41
AU53
AN49
AV16
AP50
AR49
AV18
AV20
AT50
AV24
K44
K48
T50
U49
AV26
K50
K36
K38
K42
AV28
AV30
K54
K6
AF30
AF32
Y50
Y52
AV32
K8
AV34
AV36
L11
L13
BL57
AV38
AV42
L49
L5
L51
V1P2_CPUCLK_VTT
43 mA
AH18
AH20
AH42
AV44
AH24
AH44
AJ13
AV46
AV48
AH26
AH28
AJ41
AH30
AJ43
AK12
AV50
AW37
AH32
AH34
AK42
M14
M16
M18
AW53
M26
M28
AY6
AY8
AL41
AK18
M30
M32
AM14
B56
B58
AK26
AM42
AM44
BA13
BA21
AK28
AK30
AM46
BA37
AK32
AN41
AN43
AK34
AK36
AP24
BG55
BG57
BJ51
AP26
AP28
BJ57
BK10
M50
M52
AM20
AP30
AP32
BK14
BK42
M8
N39
AM24
AM26
AP34
BL11
N45
AM28
AP36
AP38
BL51
BL53
N51
N53
AM30
AM32
AR19
BL55
P12
AR21
BM48
BM50
P14
P16
BM54
P30
BN49
BN51
P44
P46
BN53
BN55
P48
P52
BP50
R53
BP52
BP54
T12
T14
NC AM12
AK20
AK24
AK38
AM18
AM34
=PP3V3_S0_MCP
AM36
AM38
7 20 22
AK14
450 mA (A01)
AU29
V3P3 P18
P36
=PP3V3_S5_MCP
N21
N23
7 22
M38
M42
M44
M46
M48
BR11
U5
BR15
BR17
T24
BR39
U53
U9
V12
P32
P34
266 mA (A01)
V18
V20
V3P3_DUAL_USB T30
BR47
BR5
T32
BR9
V46
BT4
C49
V6
W21
C55
W23
C57
D24
W33
W35
D26
W5
D36
D38
Y16
Y18
D48
D50
Y20
Y24
D54
Y26
F10
F30
Y30
Y32
V44 V3P3_TVDAC_VDD
=PP1V05_S5_MCP_VDD_AUXC
PP3V3_G3_RTC
V1P0_VDD_AUXC
V1P0_VDD_AUXC
V26
V32
7 22
105 mA (A01)
T26
V16
BR41
BR45
250 mA
PP3V3_S0_MCP_DAC
P26 V3P3_VBAT
M34
M36
V3P3_DUAL P24
16 mA
L53
L7
L9
AW43
AW49
AK44
AK46
H10
H30
V50
AH36
AH38
10 uA (G3)
80 uA (S0)
G47
AF28
AF38
24 20
G45
AA43
AF46
AF34
AF36
70 23
A39
A53
AA41
NC
GND
GND
GND
U1400
MCP79U
BGA
(11 OF 12)
BC35
BC37
BC39
BC41
BC43
BC49
BC55
BC61
BC7
BD10
BD46
BE13
BF10
BF16
BF28
BF34
BF4
BF46
BF52
BF58
BH12
BH14
BH42
BH44
BJ1
BJ13
BJ19
BJ25
BJ31
BJ37
BJ43
BJ49
BJ55
BJ61
BJ7
BM10
BM16
BM22
BM28
BM34
BM4
BM40
BM46
BM52
BM58
BR1
BR13
BR19
BR25
BR31
BR37
BR43
BR49
BR55
BR61
BR7
BV10
BV16
BV22
BV28
BV34
BV4
BV40
BV46
BV52
BV58
CA1
CA13
CA19
CA25
CA31
CA37
CA43
CA49
CA55
CA61
CA7
D10
D16
D22
D28
D34
D4
D40
D46
OMIT
U1400
MCP79U
NC
F8
Y34
G33
G35
Y36
Y44
G41
Y46
MCP Power & Ground

SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
21
71
8
MCP Core Power
21 7
23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)
C2500
C2501
C2502
C2503
4.7UF
4.7UF
4.7UF
4.7UF
20%
4V
X5R
402
20%
4V
X5R
402
20%
4V
X5R
402
20%
4V
X5R
402
OMIT
C2504
OMIT
C2505
OMIT
C2506
OMIT
C2507
C2508
C2509
C2510
C2511
C2512
1UF
1UF
1UF
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10%
6.3V
X5R
402-1
10%
6.3V
X5R
402-1
10%
6.3V
X5R
402-1
10%
6.3V
X5R
402-1
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
MCP PCIE (DVDD) Power

7
C2513
0.1UF
10%
6.3V
X5R
201
MCP SATA (DVDD) Power
=PP1V05_S0_MCP_PEX_DVDD
43 mA (A01)
30-OHM-5A
=PP1V05_S0_MCP_AVDD_UF
333 mA (A01)
C2515
4.7UF
20%
4V
X5R
402
OMIT
C2516
1UF
10%
6.3V
X5R
402-1
OMIT
C2517
C2518
C2519
1UF
0.1UF
0.1UF
10%
6.3V
X5R
402-1
10%
6.3V
X5R
201
10%
6.3V
X5R
201
C2520
MCP 1.05V AUX Power
0.1UF
4.7UF
20%
4V
X5R
402
17 7
105 mA (A01)
2
0603
C2525
C2526
MCP FSB (VTT) Power
2 X5R
20%
4V
X5R
402
201
201
0.1UF
2
OMIT
OMIT
1
C2530
OMIT
1
C2531
C2532
OMIT
1
OMIT
1
C2533
C2534
OMIT
1
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
4V
X5R
402
C2575
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
127 mA (A01)
OMIT
C2576
2.2UF
20%
6.3V
CERM
402-LF
13 70
270 mA (A01)
C2581
10%
6.3V
X5R
201
VOLTAGE=1.05V
2
0402
C2540
4.7UF
20%
4V
X5R
402
=PP3V3_S0_MCP
C2574
2.2UF
20%
6.3V
CERM
402-LF
L2582
30-OHM-1.7A
MCP 3.3V Power
C2573
0.1UF
4.7UF
4771 mA (A01, DDR3)
21 20 7
206 mA (A01)
OMIT
2.2UF
20%
6.3V
CERM
402-LF
C2580
MCP Memory Power

66 15 7
C2572
2.2UF
VOLTAGE=1.05V
VOLTAGE=1.05V
2
0402
C2536
2.2UF
2
OMIT
C2535
2.2UF
2
30-OHM-1.7A
=PP1V05_S0_MCP_PLL_UF
562 mA (A01)
20%
6.3V
CERM
402-LF
OMIT
1
L2580
7
1182 mA (A01)
C2571
2.2UF
2.2UF
10%
6.3V
X5R
201
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 7x 2.2uF 0402 (15.4 uF)
=PP1V05_S0_MCP_FSB
OMIT
C2529
4.7uF
10%
6.3V
10%
6.3V
21 13 8 7
C2528
0.1UF
0.1UF
2 X5R
20%
6.3V
CERM
402-LF
OMIT
1
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)
19 70
L2575
30-OHM-5A
131 mA (A01)
C2570
OMIT
1
2.2UF
10%
6.3V
X5R
201
MCP 1.05V RMGT Power
=PP1V05_S5_MCP_VDD_AUXC
OMIT
C2521
7 70
VOLTAGE=1.05V
2
0603
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)
L2570
=PP1V05_S0_MCP_SATA_DVDD
19 7
57 mA (A01)
21 7
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
=PPVCORE_S0_MCP
(No IG vs. EG data)
C2541
C2542
C2543
C2544
C2545
C2546
C2547
C2548
C2549
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

Apple: 4x 2.2uF 0402 (8.8 uF)
450 mA (A01)
19 mA (A01)
OMIT
1
C2550
0402
OMIT
OMIT
C2551
C2552
OMIT
C2553
VOLTAGE=3.3V
1
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
C2583
0.1UF
10%
6.3V
X5R
201
L2584
30-OHM-1.7A
1
VOLTAGE=1.05V
19 mA (A01)
0402
C2584
C2555
2.2UF
2
20%
4V
X5R
402
OMIT
2.2UF
4.7UF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
19 70
L2555
30-OHM-1.7A
=PP3V3_S0_MCP_PLL_UF
C2582
16 70
84 mA (A01)
C2585
0.1UF
4.7UF
20%
4V
X5R
402
19 70
84 mA (A01)
10%
6.3V
X5R
201
B
MCP 3.3V AUX/USB Power
21 7
=PP3V3_S5_MCP
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
17 7
266 mA (A01)
OMIT
1
MCP 3.3V/1.5V HDA Power

20 7
MCP 3.3V Ethernet Power
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
L2586
30-OHM-1.7A
1
83 mA (A01)
1
C2560
OMIT
C2564
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
C2586
C2587
10%
6.3V
X5R
201
L2588
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
30-OHM-1.7A
1
OMIT
C2562
C2588
2.2UF
2
4.7UF
20%
6.3V
CERM
402-LF
20%
4V
X5R
402
20 70
VOLTAGE=1.05V
2
0402
7 mA (A01)
87 mA (A01)
0.1UF
4.7UF
20%
4V
X5R
402
15 70
VOLTAGE=1.05V
2
0402
C2589
C2590
0.1UF
0.1UF
10%
6.3V
X5R
201
10%
6.3V
X5R
201
37 mA (A01)
MCP Standard Decoupling
SYNC_MASTER=M97
L2595
7
30-OHM-1.7A
=PP1V05_ENET_MCP_PLL_MAC
5 mA (A01)
VOLTAGE=1.05V
2
0402
C2595

5 mA (A01)
C2596
0.1UF
4.7UF
20%
4V
X5R
402
17 70
10%
6.3V
X5R
201

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
22
71
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
17 7
PP3V3_S0_MCP_DAC
OMIT
190 mA (A01, 1.8V)

1
C2610
R2650
2.2UF
2
17 7
21 70
20%
6.3V
CERM
402-LF
5%
1/16W
MF-LF
402
=PP1V05_S0_MCP_HDMI_VDD
95 mA (A01)
C2615
4.7UF
20%
4V
X5R
402
67 17
67 17
0.1UF
10%
6.3V
X5R
201
MCP_HDMI_RSET
MCP_HDMI_VPROBE
67 17
67 17
NO STUFF
C2620
10%
6.3V
X5R
201
=PP3V3_S0_MCP_VPLL_UF
16 mA (A01)
NO STUFF
NO STUFF
C2630
1K
1%
1/20W
MF
201
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
R2620
0.1UF
C2616
1K
1%
1/20W
MF
201
0.1UF
10%
6.3V
X5R
201
R2630
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640
Apple: ???
30-OHM-1.7A
PP3V3_S0_MCP_VPLL
17 70
1
VOLTAGE=3.3V
2
0402
C2640
4.7UF
20%
6.3V
CERM
603
16 mA (A01)
C2641
0.1uF
10%
6.3V
X5R
201
MCP Graphics Support
SYNC_MASTER=M97

SYNC FROM M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
23
71
Platform Reset Connections
RTC Power Sources
LPC Reset (Unbuffered)

49 7
=PP3V42_G3H_REG
PP3V3_G3_RTC
R2881
20 21
OMIT
1
IN
PLACEMENT_NOTE=Place close to U1400
LPC_RESET_L
C2860
1UF
68 18
Place near MCP ball A20
10%
6.3V
CERM
402
33
5%
1/20W
MF
201
OUT
41
33
SMC_LRESET_L
OUT
39
BKLT_PLT_RST_L
OUT
62
AIRPORT_RST_L
OUT
6 34
PCA9557D_RESET_L
OUT
25
5%
1/20W
MF
201
RTC Crystal
DEBUG_RESET_L
R2883
PCIE Reset (Unbuffered)
C2810
12pF
20
RTC_CLK32K_XTALOUT
IN
R2810
0
R2892
5%
25V
NP0-C0G
201
16
IN
PCIE_RESET_L
R2891
5%
1/20W
MF
2 201
Y2810
10M
5%
1/16W
MF-LF
402 2
20
7X1.5X1.4-SM
C2811
5%
1/20W
MF
201
32.768K
12pF
1
RTC_CLK32K_XTALIN
OUT
R2871
CRITICAL
R2811
5%
1/20W
MF
201
RTC_CLK32K_XTALOUT_R
NO STUFF1
0
5%
1/20W
MF
201
5%
25V
NP0-C0G
201
MCP 25MHz Crystal

20
C2815
12PF
1
MCP_CLK25M_XTALOUT
IN
5%
25V
NP0-C0G
201
R2870
R2815
18
IN
33
MEM_VTT_EN_R
2
5%
1/20W
MF
201
5%
1/20W
MF
2 201
MEM_VTT_EN
MAKE_BASE=TRUE
=DDRVTT_EN
OUT
54 57
LPC_CLK33M_SMC
OUT
39 68
LPC_CLK33M_LPCPLUS
OUT
41 68
PM_CLK32K_SUSCLK
OUT
39 68
MCP_CLK25M_XTALOUT_R
SM-3.2X2.5MM
20
Y2815
25.0000M
NC
NC
1M
CRITICAL
5%
1/16W
MF-LF
402 2
R2816
NO STUFF
OUT
C2816
12pF
1
MCP_CLK25M_XTALIN
R2825
5%
25V
NP0-C0G
201
68 18
IN
LPC_CLK33M_SMC_R
33
5%
1/20W
MF
201
R2826
1
MCP S0 PWRGD & CPU_VLD

7
33
5%
1/20W
MF
201
=PP3V3_S5_MCPPWRGD
R2829
56 7
68 20
=PP3V3_S0_PWRCTL
IN
22
PM_CLK32K_SUSCLK_R
C2850
0.1UF
1
R2851
1.8K
1%
1/20W
MF
201
10%
6.3V
X5R
201
2
5 TC7SZ08AFEAPE
56 39
50
IN
IN
2
5%
1/20W
MF
201
ALL_SYS_PWRGD
VR_PWRGOOD_DELAY
R2853
SOT665
U2850Y
S0_AND_IMVP_PGOOD
MCP_PS_PWRGD
OUT
20
MCP_CPU_VLD OUT
20
5%
1/20W
MF
201
Reset Button
A
39
IN
PM_SYSRST_L
SB Misc
XDP
R2898
R2850
20
IN
MCP_CPUVDD_EN
12 9 6
IN
XDP_DBRESET_L
0
5%
1/20W
MF
201
5%
1/20W
MF
201
R2899
R2890
0
5%
1/16W
MF-LF
402 2
SYNC FROM M97

CHANGED RTC POWER SOURCE TO DIRECT CONNECTION
ADDED MCPSEQ_SMC LOGIC
NO STUFF
33
5%
1/20W
MF
201
SILK_PART=SYS RST
10K pull-up to 3.3V S0 inside MCP

PM_SYSRST_DEBOUNCE_L
OUT
SYNC_MASTER=M97
20
NO STUFF
1

C2899
1UF
10%
10V
X5R
402-1

SIZE
Place R2890 on BOTTOM of board near edge
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
24
71
Page Notes
MEM A VREF DQ
Power aliases required by this page:

- =PP3V3_S3_VREFMRGN
- =PP3V3_S5_VREFMRGN
- =PPVTT_S3_DDR_BUF
DAC channel
Min DAC code
Max DAC code
Max sink I
Max source I
Nominal Vref
Min Vref
Max Vref
Vref Stepping
(per DAC LSB)
Signal aliases required by this page:

- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
BOM options provided by this page:

VREFMRGN
MEM A VREF CA
A
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
MEM B VREF DQ
B
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
A
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
MEM B VREF CA
B
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
CPU FSB VREF

C
0x00
0x55
-0.91 mA
0.52 mA
0.70 V
0.091 V
1.044 V
11.2 mV
=PPVTT_S3_DDR_BUF
7
10mA max load
R2903
VREFMRGN
200
B1
VREFMRGN
A2
C2900
V+
0.1UF
V-
25
R2901
C2910
0.1UF
100K
10%
2 6.3V
X5R
201
B1
C2
V+
9 A0
ADDR=0x98(WR)/0x99(RD)
10 A1
VREFMRGN_CA_BUF
25
B4
100
27 28 29 30 70
VOLTAGE=0.75V
1%
1/20W
MF
201
C4
V-
PP0V75_S3_MEM_VREFCA
R2906
VREFMRGN_CA_EN
VREFMRGN_VREFDQ
VOUTB 2
VREFMRGN_VREFCA
VOUTC 4
VREFMRGN_CPUFSB
VOUTD 5
CRITICAL
GND
3
R2902
100K
5%
1/20W
MF
201
VREFMRGN
7 SDA
DAC5574
42
6 SCL
=I2C_VREFDACS_SDA
42
BI
=I2C_VREFDACS_SCL
5%
1/20W
MF
201
CRITICAL
C3
VREFMRGN
200
MAX4253
UCSP
C1
VREFMRGN
VREFMRGN
8 U2910
VDD
MSOP VOUTA 1
5%
1/20W
MF
201
U2900
R2905
VREFMRGN
20%
6.3V
CERM
402-LF
100
VOLTAGE=0.75V
2.2UF
IN
VREFMRGN_DQ_EN
VREFMRGN
C2915
27 28 29 30 70
1%
1/20W
MF
201
A4
B4
VREFMRGN
VREFMRGN_DQ_BUF
CRITICAL
A3
PP0V75_S3_MEM_VREFDQ
R2904
MAX4253
UCSP
A1
VREFMRGN
10%
6.3V
2 X5R
201
=PP3V3_S3_VREFMRGN
U2900
5%
1/20W
MF
201
NC
U2903
B1
VREFMRGN
1
NC
C2903
A2
V+
0.1UF
MAX4253
UCSP
A1
VREFMRGN
10%
6.3V
2 X5R
201
CRITICAL
NC
A3
NC
A4
VB4
U2903
B1
V+
VREFMRGN
CRITICAL
C3
R2907
MAX4253
UCSP
C1
VREFMRGN_CPUFSB_BUF
V-
25 VREFMRGN_CPUFSB_EN
B4
R2908
100
CPU_GTLREF
OUT
9 65
1%
1/20W
MF
201
C4
C2
100K
VREFMRGN
5%
1/20W
MF
201
B
VREFMRGN
C2920
16
0.1UF
VREFMRGN
VCC
10%
2 6.3V
X5R
201
QFN
3
ADDR=0x30(WR)/0x31(RD)
A0
4 A1
5 A2
CRITICAL
42
IN
BI
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
SCL
SDA
THRM
17
PAD
P0
P1
P2
P3
P4
P5
P6
P7
NC
VREFMRGN_CPUFSB_EN
25
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
R2903
CRITICAL
NO_VREFMRGN
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
R2905
CRITICAL
NO_VREFMRGN
VREFMRGN_CA_EN
25
VREFMRGN_DQ_EN
10
25
11
NC
NC
NC
NC
12
13
14
RESET* 15
PCA9557D_RESET_L
IN
24
GND
8
42
Required zero ohm resistors when no VREF margining circuit stuffed
U2920
PCA9557
FSB/DDR3 Vref Margining

SYNC_MASTER=BEN

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
25
71
DDR3 RESET Support

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.
=PP1V5_S3_MEMRESET
3.3V input must be stable before
before 1.5V starts to rise to
avoid glitch on MEM_RESET_L.
=PP3V3_S5_MEMRESET
1K
MEMRESET_HW
R3010
R3005
5%
1/20W
MF
201
C
MEM_RESET_L
20K
MEMRESET_HW
R3000 1
MEM_RESET
10K
5%
1/20W
MF
201
MEMRESET_HW
3
R3001 1
MEMRESET_HW
1
20K
IN
Q3005
R3009
0
MMDT3904-X-G
1
27 28 29 30 66
5%
1/20W
MF
201
Q3005
MMDT3904-X-G
SOT-363-LF
MEMRESET_HW
15
MEMRESET_HW
6
2
OUT
MEMRESET_MCP
SOT-363-LF
MEM_RESET_RC_L
5%
1/20W
MF
201
5%
1/20W
MF
201
C3000
0.1UF
2
2
10%
6.3V
X5R
201
MCP_MEM_RESET_L
DDR3 Support
SYNC_MASTER=T18_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
26
71
DQS C3 MEM_A_DQS_P<0>
66 33 28 27 14
MEM_A_A<10>
M3
H7
66 33 28 27 14
MEM_A_A<11>
M7
66 33 28 27 14
MEM_A_A<12>
A12/BC*
66 33 28 27 14
MEM_A_A<13>
K7
N3
66 33 28 27 14
MEM_A_BA<0>
J2
66 33 28 27 14
MEM_A_BA<1>
K8
BA0
BA1
66 33 28 27 14
MEM_A_BA<2>
J3
BA2
66 33 28 27 14
MEM_A_CKE<0> G9
CKE
A9
A10/AP
A11
MEM_A_CLK_P<0>F7
66 33 28 27 14
MEM_A_CLK_N<0>G7
CK
CK*
66 33 28 27 14
MEM_A_CS_L<0> H2
CS*
MEM_A_CS_L<1> H1
66 33 28 27 14
MEM_A_RAS_L
F3
66 33 28 27 14
MEM_A_CAS_L
G3
66 33 28 27 14
MEM_A_WE_L
H3
DM/TDQS B7 MEM_A_DM<0>
MEM_A_A<6>
66 33 28 27 14
MEM_A_A<7>
14 66
66 33 28 27 14
14 66
14 66
14 66
TDQS* A7 NC
A3
NC
NC
N7
J7
RAS*
66 33 28 27 14
MEM_A_A<10>
66 33 28 27 14
MEM_A_A<11>
H7
M7
66 33 28 27 14
N3
A13
MEM_A_BA<0>
BA0
BA1
66 33 28 27 14
MEM_A_BA<1>
J2
K8
66 33 28 27 14
MEM_A_BA<2>
J3
BA2
66 33 28 27 14
MEM_A_CKE<0> G9
CKE
33 28 27 14
66
14 27 28 33 66
66 33 28 27 14
14 27 28 33 66
66 33 28 27 14
WE*
66 33 28 27 14
MEM_A_CLK_P<0>F7
CK
MEM_A_CLK_N<0>G7
CK*
MEM_A_CS_L<0> H2
MEM_A_CS_L<1> H1
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
F3
G3
H3
MEM_A_A<3>
66 33 28 27 14
MEM_A_A<4>
K2
L8
A3
A4
66 33 28 27 14
MEM_A_A<5>
MEM_A_A<6>
L2
M8
A5
66 33 28 27 14
66 33 28 27 14
MEM_A_A<7>
M2
66 33 28 27 14
MEM_A_A<8>
14 66
14 66
NC
14 27 28 33 66
RAS*
J7 NC MEM_A_A<14>
MEM_A_A<9>
MEM_A_A<10>
H7
66 33 28 27 14
MEM_A_A<11>
66 33 28 27 14
MEM_A_A<12>
M7
K7
66 33 28 27 14
MEM_A_A<13>
N3
A12/BC*
A13
66 33 28 27 14
MEM_A_BA<0>
J2
BA0
66 33 28 27 14
MEM_A_BA<1>
66 33 28 27 14
MEM_A_BA<2>
K8
J3
BA1
BA2
66 33 28 27 14
MEM_A_CKE<0> G9
CKE
66 33 28 27 14
MEM_A_CLK_P<0>F7
CK
66 33 28 27 14
MEM_A_CLK_N<0>G7
CK*
66 33 28 27 14
MEM_A_CS_L<0> H2
CS*
B8
B2
N9
L9
N1
E9
C1
E2
B9
M9
K9
M1
K1
G2
G8
D7
A2
A9
E1
J8
VREFCA
VREFDQ
E2
E9
C1
B9
M9
G8
K1
G2
A9
D7
K9
M1
DQ0 B3 MEM_A_DQ<19>
DQ1 C7 MEM_A_DQ<17>
DQ2 C2 MEM_A_DQ<23>
DQ3 C8 MEM_A_DQ<20>
DQ4 E3 MEM_A_DQ<22>
DQ5 E8 MEM_A_DQ<16>
DQ6 D2 MEM_A_DQ<18>
MEM_RESET_L
240
N2
2 MEM_A_ZQ3 H8
ODT
RESET*
ZQ
14 66
66 33 28 27 14
MEM_A_A<0>
14 66
66 33 28 27 14
MEM_A_A<1>
K3
L7
A1
A2
A9
A10/AP
A11
14 66
66 33 28 27 14
MEM_A_A<2>
14 66
66 33 28 27 14
MEM_A_A<3>
14 66
66 33 28 27 14
MEM_A_A<4>
K2
L8
A3
A4
14 66
A5
66 33 28 27 14
MEM_A_A<5>
14 66
66 33 28 27 14
MEM_A_A<6>
L2
M8
14 66
66 33 28 27 14
MEM_A_A<7>
M2
66 33 28 27 14
MEM_A_A<8>
14 66
DQS* D3 MEM_A_DQS_N<2>
14 66
A3 NC
66 33 28 27 14
MEM_A_CS_L<1> H1
NC
MEM_A_RAS_L
F3
RAS*
J7 NC MEM_A_A<14>
66 33 28 27 14
MEM_A_CAS_L
G3
CAS*
66 33 28 27 14
MEM_A_WE_L
H3
WE*
VSS
MEM_A_A<10>
H7
MEM_A_A<11>
66 33 28 27 14
MEM_A_A<12>
M7
K7
66 33 28 27 14
MEM_A_A<13>
N3
A12/BC*
A13
66 33 28 27 14
MEM_A_BA<0>
J2
BA0
66 33 28 27 14
MEM_A_BA<1>
66 33 28 27 14
MEM_A_BA<2>
K8
J3
BA1
BA2
66 33 28 27 14
MEM_A_CKE<0> G9
CKE
66 33 28 27 14
MEM_A_CLK_P<0>F7
CK
MEM_A_CLK_N<0>G7
CK*
MEM_A_CS_L<0> H2
CS*
14 27 28 33 66 33 28 27 14
66
66 33 28 27 14
MEM_A_ZQ2
MEM_A_A<9>
66 33 28 27 14
66 33 28 27 14
66 33 28 27 14
66 33 28 27 14
14 27 28 33 66
H9
N7
OMIT
DQ0 B3 MEM_A_DQ<28>
DQ1 C7 MEM_A_DQ<25>
14 66
14 66
DQ2 C2 MEM_A_DQ<27>
DQ3 C8 MEM_A_DQ<26>
DQ4 E3 MEM_A_DQ<29>
14 66
14 66
14 66
DQ5 E8 MEM_A_DQ<24>
DQ6 D2 MEM_A_DQ<30>
14 66
14 66
DQ7 E7 MEM_A_DQ<31>
14 66
14 66
14 66
A8
A9
A10/AP
A11
14 66
TDQS* A7 NC
A3 NC
NC F1 MEM_A_ODT<1>
F9 MEM_A_CKE<1>
14 27 28 33
66
14 27 28 33
66
66 33 28 27 14
MEM_A_CS_L<1> H1
NC
H9
N7
66 33 28 27 14
MEM_A_RAS_L
F3
RAS*
J7 NC MEM_A_A<14>
66 33 28 27 14
MEM_A_CAS_L
G3
CAS*
66 33 28 27 14
MEM_A_WE_L
H3
WE*
27
14 27 28
33 66
A6
A7
N8
M3
14 66
TDQS* A7 NC
NC F1 MEM_A_ODT<1>
F9 MEM_A_CKE<1>
A0
L3
27
14 27 28 33 66
MEM_A_ODT<0> G1
MF 1% 1/20W 201
A8
VSSQ
L1
J1
J9
R31301
DQ7 E7 MEM_A_DQ<21>
66 33 28 27 14
WE*
F2
F8
A6
A7
66 33 28 27 14
CAS*
D8
A0
N8
M3
14 27 28 33 66
NC
A8
B1
D9
D1
B8
C9
B2
N9
L9
N1
66 33 28 27 14
14 66
H9
N7
VSSQ
L1
J1
J9
F8
D8
F2
A8
B1
MEM_A_A<2>
A1
A2
14 66
TDQS* A7 NC
MEM_A_ZQ1
66 33 28 27 14
L3
14 66
14 66
CS*
MEM_A_A<1>
14 66
NC F1 MEM_A_ODT<1>
F9 MEM_A_CKE<1>
66 33 28 27 14
K3
L7
14 66
14 66
A3
MEM_A_A<0>
14 66
VSS
A1
A2
B9
C1
M1
M9
K9
A11
A12/BC*
MEM_A_A<13>
CAS*
VSS
K7
A10/AP
66 33 28 27 14
66 33 28 27 14
MEM_A_A<12>
DQ7 E7 MEM_A_DQ<15>
A8
A9
66 33 28 27 14
14 27 28 33 66
MEM_A_A<14>
A7
M3
66 33 28 27 14
NC
M2
N8
MEM_A_A<9>
66 33 28 27 14
NC F1 MEM_A_ODT<1>
F9 MEM_A_CKE<1>
H9 MEM_A_ZQ0 27
MEM_A_A<8>
A5
A6
66 33 28 27 14
A13
66 33 28 27 14
66 33 28 27 14
66 33 28 27 14
14 66
L2
M8
66 33 28 27 14
66 33 28 27 14
66 30 29 28 27 26
VSSQ
VSS
MEM_A_ZQ3
27
14 27 28 33 66
VSSQ
D1
D9
MEM_A_A<9>
DQ6 D2 MEM_A_DQ<5>
DQ7 E7 MEM_A_DQ<6>
A7
A8
MEM_A_A<5>
DQ4 E3 MEM_A_DQ<10>
DQ5 E8 MEM_A_DQ<11>
DQ6 D2 MEM_A_DQ<13>
ZQ
MF 1% 1/20W 201
14 66
OMIT
C9
66 33 28 27 14
A6
66 33 28 27 14
L8
RESET*
20%
4V
201
B2
B8
N8
MEM_A_A<4>
2 MEM_A_ZQ2 H8
ODT
0.47UF
U3130
N9
M8
M2
MEM_A_A<8>
66 33 28 27 14
14 66
A3
A4
240
N2
C3132
2 CERM-X5R
MT41J128M8HX-187E
MEM_A_A<7>
66 33 28 27 14
14 66
R31201
DQ0 B3 MEM_A_DQ<8>
DQ1 C7 MEM_A_DQ<14>
DQ2 C2 MEM_A_DQ<9>
DQ3 C8 MEM_A_DQ<12>
MEM_RESET_L
VDDQ
N1
MEM_A_A<6>
66 33 28 27 14
MEM_A_A<3>
14 66
A2
201
4V
128MX8-SDRAM-1066MHZ
66 33 28 27 14
66 33 28 27 14
L3
K2
201
4V
VDD
L1
L9
MEM_A_A<5>
A4
A5
L7
MEM_A_A<2>
20%
J9
66 33 28 27 14
L8
L2
MEM_A_A<1>
66 33 28 27 14
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
F8
J1
MEM_A_A<4>
66 33 28 27 14
14 66
20%
4V
CERM-X5R
201
=PP1V5_S3_MEM_A
F2
66 33 28 27 14
DQ3 C8 MEM_A_DQ<3>
DQ4 E3 MEM_A_DQ<4>
DQ5 E8 MEM_A_DQ<2>
A0
A1
C3131 1
B1
D8
MEM_A_A<3>
A2
A3
ZQ
A1
A8
66 33 28 27 14
K2
14 66
K3
MEM_A_ODT<0> G1
D9
MEM_A_A<2>
A1
MEM_A_A<0>
66 33 28 27 14
66 30 29 28 27 26
D1
66 33 28 27 14
L7
L3
66 33 28 27 14
OMIT
B2
MEM_A_A<1>
2 MEM_A_ZQ1 H8
MF 1% 1/20W 201
14 66
C3130
FBGA
N9
66 33 28 27 14
R31101
DQ0 B3 MEM_A_DQ<7>
DQ1 C7 MEM_A_DQ<1>
DQ2 C2 MEM_A_DQ<0>
240
70 30 29 28 27 25
C3122
0.47UF
VDDQ
N1
A0
RESET*
N2
A1
MEM_A_A<0>
ODT
MEM_RESET_L
K3
MF 1% 1/20W 201
66 33 28 27 14
MEM_A_ODT<0> G1
FBGA
J1
J9
ZQ
66 33 28 27 14
66 30 29 28 27 26
70 30 29 28 27 25
U3120
FBGA
OMIT
F8
H8
G8
K1
D7
G2
A9
U3110
201
4V
VDD
D8
F2
MEM_A_ZQ0
201
4V
=PP1V5_S3_MEM_A
B1
20%
A1
A8
RESET*
N2
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
201
MEM_RESET_L
240
MT41J128M8HX-187E
R31001
ODT
30 29 28 27 26
66
MEM_A_ODT<0> G1
20%
2 4V
CERM-X5R
FBGA
66 33 28 27 14
0.47UF
VDDQ
C3121 1
MT41J128M8HX-187E
201
4V
VDD
L1
L9
201
4V
U3100
C3120
J8
20%
70 30 29 28 27 25
C3112
E1
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
201
VREFCA
20%
4V
2 CERM-X5R
C3111 1
VREFDQ
VDDQ
A2
C3110
0.47UF
J8
C3102
E1
E2
E9
B9
C1
M1
M9
K9
G8
K1
G2
A9
D7
A2
VDD
70 30 29 28 27 25
=PP1V5_S3_MEM_A
B8
C9
MT41J128M8HX-187E
201
4V
70 30 29 28 27 25
VREFCA
201
4V
J8
E1
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
VREFDQ
20%
C3101 1
VREFCA
VREFDQ
C3100
70 30 29 28 27 25
=PP1V5_S3_MEM_A
E9
E2
70 30 29 28 27 25
D9
C9
D1
70 30 29 28 27 25
A14/A15 FOR 2G/4G MONO ONLY

CS1 IS FOR 2G DDP RANK CONTROL
SYNC_DATE=(MASTER)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
27
71
66 33 28 27 14
MEM_A_A<13>
N3
66 33 28 27 14
MEM_A_BA<0>
J2
BA0
66 33 28 27 14
MEM_A_BA<1>
66 33 28 27 14
MEM_A_BA<2>
K8
J3
BA1
BA2
66 33 28 27 14
MEM_A_CKE<0> G9
A11
A12/BC*
A13
MEM_A_CLK_P<0>F7
CK
66 33 28 27 14
MEM_A_CLK_N<0>G7
CK*
66 33 28 27 14
MEM_A_CS_L<0> H2
CS*
A3
MEM_A_CS_L<1> H1
66 33 28 27 14
MEM_A_RAS_L
F3
RAS*
66 33 28 27 14
MEM_A_CAS_L
G3
CAS*
NC
NC
NC
NC
NC
NC F1 MEM_A_ODT<1>
F9 MEM_A_CKE<1>
H9
66 33 28 27 14
14 66
TDQS* A7 NC
CKE
66 33 28 27 14
14 66
NC
MEM_A_ZQ8
66 33 28 27 14
MEM_A_A<10>
66 33 28 27 14
MEM_A_A<11>
M7
66 33 28 27 14
MEM_A_A<13>
K7
N3
66 33 28 27 14
MEM_A_BA<0>
J2
66 33 28 27 14
MEM_A_WE_L
H3
MEM_A_BA<1>
K8
66 33 28 27 14
MEM_A_BA<2>
J3
BA2
66 33 28 27 14
MEM_A_CKE<0> G9
CKE
66 33 28 27 14
MEM_A_CLK_P<0>F7
MEM_A_CLK_N<0>G7
CK
CK*
MEM_A_CS_L<0> H2
CS*
14 27 28 33 66
33 28 27 14
66
14 27 28 33 66
66 33 28 27 14
66 33 28 27 14
MEM_A_A<14>
66 33 28 27 14
14 27 28 33 66
WE*
F3
RAS*
MEM_A_CAS_L
G3
CAS*
H3
A3
A4
66 33 28 27 14
MEM_A_A<5>
66 33 28 27 14
MEM_A_A<6>
L2
M8
A5
A6
A7
14 66
66 33 28 27 14
MEM_A_A<7>
66 33 28 27 14
MEM_A_A<8>
M2
N8
66 33 28 27 14
NC
NC
NC
NC
NC
NC F1 MEM_A_ODT<1>
F9 MEM_A_CKE<1>
H9 MEM_A_ZQ9 28
N7
J7
14 27 28 33 66
DQ4 E3 MEM_A_DQ<48>
DQ5 E8 MEM_A_DQ<53>
DQ6 D2 MEM_A_DQ<54>
DQ7 E7 MEM_A_DQ<52>
A8
A9
MEM_A_A<9>
M3
66 33 28 27 14
MEM_A_A<10>
66 33 28 27 14
MEM_A_A<11>
H7
M7
66 33 28 27 14
MEM_A_A<12>
K7
A11
A12/BC*
66 33 28 27 14
MEM_A_A<13>
N3
A13
66 33 28 27 14
MEM_A_BA<0>
BA0
BA1
A10/AP
66 33 28 27 14
MEM_A_A<0>
K3
14 66
66 33 28 27 14
MEM_A_A<1>
L7
14 66
66 33 28 27 14
MEM_A_A<2>
14 66
66 33 28 27 14
MEM_A_A<3>
L3
K2
14 66
66 33 28 27 14
MEM_A_A<4>
L8
A3
A4
14 66
66 33 28 27 14
MEM_A_A<5>
14 66
66 33 28 27 14
MEM_A_A<6>
L2
M8
A5
A6
14 66
66 33 28 27 14
MEM_A_A<7>
MEM_A_A<8>
M2
N8
A7
66 33 28 27 14
66 33 28 27 14
MEM_A_A<9>
M3
66 33 28 27 14
MEM_A_A<10>
66 33 28 27 14
MEM_A_A<11>
H7
M7
66 33 28 27 14
MEM_A_A<12>
K7
A11
A12/BC*
66 33 28 27 14
MEM_A_A<13>
N3
A13
66 33 28 27 14
MEM_A_BA<0>
BA0
BA1
14 66
14 66
14 66
TDQS* A7 NC
66 33 28 27 14
MEM_A_BA<1>
66 33 28 27 14
MEM_A_BA<2>
J3
BA2
66 33 28 27 14
MEM_A_CKE<0> G9
CKE
66 33 28 27 14
MEM_A_CLK_P<0>F7
CK
66 33 28 27 14
MEM_A_CLK_N<0>G7
CK*
66 33 28 27 14
MEM_A_CS_L<0> H2
CS*
66 33 28 27 14
MEM_A_CS_L<1> H1
NC
H9
N7
66 33 28 27 14
MEM_A_RAS_L
F3
RAS*
J7 NC
66 33 28 27 14
MEM_A_CAS_L
G3
CAS*
66 33 28 27 14
MEM_A_WE_L
H3
WE*
NC
A3
NC
NC
NC
NC
NC
NC F1 MEM_A_ODT<1>
F9 MEM_A_CKE<1>
A2
E9
E2
B9
C1
M9
K1
K9
M1
DQ0 B3 MEM_A_DQ<59>
DQ1 C7 MEM_A_DQ<57>
DQ2 C2 MEM_A_DQ<63>
DQ3 C8 MEM_A_DQ<56>
14 66
14 66
A10/AP
14 66
14 66
14 66
14 66
14 66
TDQS* A7 NC
MEM_A_BA<1>
J3
BA2
66 33 28 27 14
MEM_A_CKE<0> G9
CKE
66 33 28 27 14
MEM_A_CLK_P<0>F7
CK
MEM_A_CLK_N<0>G7
CK*
MEM_A_CS_L<0> H2
CS*
66 33 28 27 14
MEM_A_CS_L<1> H1
NC
H9
N7
66 33 28 27 14
MEM_A_RAS_L
F3
RAS*
J7 NC
14 27 28 33 66
66 33 28 27 14
MEM_A_CAS_L
G3
CAS*
MEM_A_WE_L
H3
WE*
A3
NC
NC
NC
NC
NC
NC F1 MEM_A_ODT<1>
F9 MEM_A_CKE<1>
14 27 28 33 66
14 27 28 33 66
MEM_A_ZQ11 28
MEM_A_A<14>
14 27 28 33
66
VSSQ
VSS
14 66
14 66
MEM_A_BA<2>
66 33 28 27 14
14 66
DQ7 E7 MEM_A_DQ<60>
A8
A9
66 33 28 27 14
14 27 28 33 66 33 28 27 14
66
14 66
DQ4 E3 MEM_A_DQ<58>
DQ5 E8 MEM_A_DQ<61>
DQ6 D2 MEM_A_DQ<62>
66 33 28 27 14
66 33 28 27 14
14 27 28 33 66
MEM_A_A<14>
A0
A1
J2
K8
MEM_A_ZQ10 28
14 27 28 33 66
WE*
ZQ
14 66
J2
K8
14 27 28 33 66
MEM_A_A<14>
DQ0 B3 MEM_A_DQ<50>
DQ1 C7 MEM_A_DQ<49>
DQ2 C2 MEM_A_DQ<55>
DQ3 C8 MEM_A_DQ<51>
MT41J128M8HX-187E
L8
2 MEM_A_ZQ11 H8
MEM_A_A<4>
A2
G8
D7
G2
A9
A2
J8
E1
VREFDQ
VREFCA
E9
C1
E2
B9
M9
M1
K1
K9
G2
G8
D7
A2
A9
J8
E1
E2
E9
B9
M9
K9
M1
K1
G2
G8
A9
D7
A3
VSS
D1
D9
B8
C9
B2
N9
N1
L1
L9
66 33 28 27 14
14 66
14 66
NC
MEM_A_RAS_L
MEM_A_WE_L
L3
K2
14 66
TDQS* A7 NC
VSSQ
J9
F8
J1
D8
F2
A1
A8
B1
VSS
MEM_A_CS_L<1> H1
66 33 28 27 14
MEM_A_A<3>
14 66
28
N7
J7 NC
MEM_A_A<2>
14 66
14 66
66 33 28 27 14
A13
66 33 28 27 14
66 33 28 27 14
A12/BC*
BA0
BA1
66 33 28 27 14
66 33 28 27 14
MEM_A_A<12>
A10/AP
A11
L7
14 66
A9
MEM_A_A<1>
14 66
240
MF 1% 1/20W 201
OMIT
VSSQ
VSS
VSSQ
D9
M7
K7
M3
H7
66 33 28 27 14
14 66
A0
A1
RESET*
C9
D1
MEM_A_A<12>
MEM_A_A<9>
K3
R32301
ODT
N2
B8
H7
MEM_A_A<11>
66 33 28 27 14
66 33 28 27 14
DQ6 D2 MEM_A_DQ<47>
DQ7 E7 MEM_A_DQ<42>
A7
A8
MEM_A_A<0>
20%
FBGA
MEM_A_ODT<0> G1
MEM_RESET_L
B2
MEM_A_A<10>
66 33 28 27 14
14 66
A6
66 33 28 27 14
0.47UF
201
N1
N9
66 33 28 27 14
N8
14 66
C3232
U3230
L9
A9
A10/AP
M8
M2
MEM_A_A<8>
MEM_A_A<6>
DQ3 C8 MEM_A_DQ<45>
DQ4 E3 MEM_A_DQ<43>
DQ5 E8 MEM_A_DQ<40>
ZQ
VDDQ
2 4V
CERM-X5R
J9
L1
MEM_A_A<9>
MEM_A_A<7>
66 33 28 27 14
201
4V
J1
66 33 28 27 14
66 33 28 27 14
66 33 28 27 14
14 66
201
4V
VDD
F2
F8
MEM_A_A<8>
20%
D8
A8
MEM_A_A<7>
66 33 28 27 14
MEM_A_A<5>
20%
=PP1V5_S3_MEM_A
A8
B1
N8
M3
66 33 28 27 14
66 33 28 27 14
14 66
A4
A5
C3231 1
A1
A6
A7
L8
L2
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
66 33 28 27 14
D1
D9
M8
M2
MEM_A_A<4>
14 66
20%
4V
CERM-X5R
201
66 30 29 28 27 26
B2
B8
MEM_A_A<6>
66 33 28 27 14
14 66
C3230
OMIT
N1
N9
66 33 28 27 14
DQ5 E8 MEM_A_DQ<37>
DQ6 D2 MEM_A_DQ<38>
DQ7 E7 MEM_A_DQ<32>
K2
2 MEM_A_ZQ10 H8
A4
A5
MEM_A_A<3>
A2
A3
240
F8
J1
L2
66 33 28 27 14
14 66
A1
70 30 29 28 27 25
U3220
F2
MEM_A_A<5>
L7
L3
C3222
0.47UF
VDDQ
2
MF 1% 1/20W 201
B1
D8
66 33 28 27 14
A3
MEM_A_A<2>
RESET*
A8
K2
L8
MEM_A_A<1>
66 33 28 27 14
ODT
N2
A1
66 33 28 27 14
MEM_A_A<4>
66 33 28 27 14
14 66
A0
R32201
DQ0 B3 MEM_A_DQ<41>
DQ1 C7 MEM_A_DQ<46>
DQ2 C2 MEM_A_DQ<44>
MEM_A_ODT<0> G1
MEM_RESET_L
D9
MEM_A_A<3>
66 33 28 27 14
14 66
K3
MEM_A_A<0>
D1
66 33 28 27 14
DQ2 C2 MEM_A_DQ<34>
DQ3 C8 MEM_A_DQ<35>
DQ4 E3 MEM_A_DQ<36>
ZQ
MF 1% 1/20W 201
14 66
66 33 28 27 14
66 30 29 28 27 26
B8
C9
L3
201
4V
VDD
70 30 29 28 27 25
FBGA
OMIT
B2
MEM_A_A<2>
2 MEM_A_ZQ9 H8
RESET*
N9
66 33 28 27 14
A1
A2
R32101
DQ0 B3 MEM_A_DQ<39>
DQ1 C7 MEM_A_DQ<33>
240
ODT
MT41J128M8HX-187E
MEM_A_A<1>
A0
MEM_RESET_L N2
N1
66 33 28 27 14
K3
L7
MEM_A_ODT<0> G1
MEM_A_A<0>
66 33 28 27 14
66 30 29 28 27 26
J1
J9
MF 1% 1/20W 201
66 33 28 27 14
201
4V
U3210
F8
ZQ
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
201
D8
F2
2 MEM_A_ZQ8H8
RESET*
B1
N2
20%
=PP1V5_S3_MEM_A
FBGA
OMIT
A1
A8
240
ODT
MT41J128M8HX-187E
R32001
MEM_RESET_L
66 30 29 28 27 26
MEM_A_ODT<0> G1
20%
4V
2 CERM-X5R
FBGA
66 33 28 27 14
0.47UF
VDDQ
C3221 1
C9
201
4V
VDD
L1
L9
201
4V
U3200
C3220
MT41J128M8HX-187E
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
201
70 30 29 28 27 25
C3212
J9
20%
2 CERM-X5R
VREFCA
20%
4V
C3211 1
VREFDQ
VDDQ
A2
C3210
0.47UF
J8
C3202
E1
E9
B9
M9
K9
M1
K1
G2
G8
D7
A2
A9
J8
VDD
70 30 29 28 27 25
=PP1V5_S3_MEM_A
C1
L1
L9
201
4V
70 30 29 28 27 25
VREFCA
201
4V
VREFDQ
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
E1
C3201 1
VREFCA
20%
VREFDQ
C3200
70 30 29 28 27 25
=PP1V5_S3_MEM_A
29 28 27 25
70 30
C1
E2
29 28 27 25
70 30


SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
28
71
DQS C3 MEM_B_DQS_P<0>
66 33 30 29 14
MEM_B_A<10>
M3
H7
66 33 30 29 14
MEM_B_A<11>
M7
66 33 30 29 14
MEM_B_A<12>
A12/BC*
66 33 30 29 14
MEM_B_A<13>
K7
N3
66 33 30 29 14
MEM_B_BA<0>
J2
66 33 30 29 14
MEM_B_BA<1>
K8
BA0
BA1
66 33 30 29 14
MEM_B_BA<2>
J3
BA2
66 33 30 29 14
MEM_B_CKE<0> G9
CKE
A9
A10/AP
A11
MEM_B_CLK_P<0>F7
66 33 30 29 14
MEM_B_CLK_N<0>G7
CK
CK*
66 33 30 29 14
MEM_B_CS_L<0> H2
CS*
MEM_B_CS_L<1> H1
66 33 30 29 14
MEM_B_RAS_L
F3
66 33 30 29 14
MEM_B_CAS_L
G3
66 33 30 29 14
MEM_B_WE_L
H3
DM/TDQS B7 MEM_B_DM<0>
MEM_B_A<6>
66 33 30 29 14
MEM_B_A<7>
66 33 30 29 14
14 66
14 66
14 66
TDQS* A7 NC
A3
NC
NC
N7
J7
RAS*
M3
66 33 30 29 14
MEM_B_A<10>
66 33 30 29 14
MEM_B_A<11>
H7
M7
66 33 30 29 14
N3
A13
MEM_B_BA<0>
BA0
BA1
66 33 30 29 14
MEM_B_BA<1>
J2
K8
66 33 30 29 14
MEM_B_BA<2>
J3
BA2
66 33 30 29 14
MEM_B_CKE<0> G9
CKE
14 29 30 33 66
66 33 30 29 14
CAS*
WE*
66 33 30 29 14
VSS
MEM_B_CLK_P<0>F7
CK
MEM_B_CLK_N<0>G7
CK*
MEM_B_CS_L<0> H2
MEM_B_CS_L<1> H1
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
F3
G3
H3
MEM_B_A<3>
66 33 30 29 14
MEM_B_A<4>
K2
L8
A3
A4
66 33 30 29 14
MEM_B_A<5>
MEM_B_A<6>
L2
M8
A5
66 33 30 29 14
66 33 30 29 14
MEM_B_A<7>
M2
66 33 30 29 14
MEM_B_A<8>
14 66
14 66
NC
14 29 30 33 66
RAS*
J7 NC MEM_B_A<14>
MEM_B_A<9>
MEM_B_A<10>
H7
66 33 30 29 14
MEM_B_A<11>
66 33 30 29 14
MEM_B_A<12>
M7
K7
66 33 30 29 14
MEM_B_A<13>
N3
A12/BC*
A13
66 33 30 29 14
MEM_B_BA<0>
J2
BA0
66 33 30 29 14
MEM_B_BA<1>
66 33 30 29 14
MEM_B_BA<2>
K8
J3
BA1
BA2
66 33 30 29 14
MEM_B_CKE<0> G9
CKE
66 33 30 29 14
MEM_B_CLK_P<0>F7
CK
66 33 30 29 14
MEM_B_CLK_N<0>G7
CK*
66 33 30 29 14
MEM_B_CS_L<0> H2
CS*
B8
B2
N9
L9
N1
E9
C1
E2
B9
M9
K9
M1
K1
G2
G8
D7
A2
A9
E1
J8
VREFCA
VREFDQ
E2
E9
C1
B9
M9
G8
K1
G2
A9
D7
K9
M1
DQ0 B3 MEM_B_DQ<16>
DQ1 C7 MEM_B_DQ<22>
DQ2 C2 MEM_B_DQ<21>
DQ3 C8 MEM_B_DQ<20>
DQ4 E3 MEM_B_DQ<19>
DQ5 E8 MEM_B_DQ<18>
DQ6 D2 MEM_B_DQ<17>
MEM_RESET_L
240
N2
2 MEM_B_ZQ3 H8
ODT
RESET*
ZQ
14 66
66 33 30 29 14
MEM_B_A<0>
14 66
66 33 30 29 14
MEM_B_A<1>
K3
L7
A1
A2
A9
A10/AP
A11
14 66
66 33 30 29 14
MEM_B_A<2>
14 66
66 33 30 29 14
MEM_B_A<3>
14 66
66 33 30 29 14
MEM_B_A<4>
K2
L8
A3
A4
14 66
66 33 30 29 14
MEM_B_A<5>
66 33 30 29 14
MEM_B_A<6>
L2
M8
A5
14 66
14 66
66 33 30 29 14
MEM_B_A<7>
M2
66 33 30 29 14
MEM_B_A<8>
14 66
DQS* D3 MEM_B_DQS_N<2>
14 66
A3 NC
MEM_B_CS_L<1> H1
NC
66 33 30 29 14
MEM_B_RAS_L
F3
RAS*
J7 NC MEM_B_A<14>
66 33 30 29 14
MEM_B_CAS_L
G3
CAS*
66 33 30 29 14
MEM_B_WE_L
H3
WE*
VSS
MEM_B_A<10>
H7
66 33 30 29 14
MEM_B_A<11>
66 33 30 29 14
MEM_B_A<12>
M7
K7
66 33 30 29 14
MEM_B_A<13>
N3
A12/BC*
A13
66 33 30 29 14
MEM_B_BA<0>
J2
BA0
66 33 30 29 14
MEM_B_BA<1>
66 33 30 29 14
MEM_B_BA<2>
K8
J3
BA1
BA2
66 33 30 29 14
MEM_B_CKE<0> G9
CKE
66 33 30 29 14
MEM_B_CLK_P<0>F7
CK
MEM_B_CLK_N<0>G7
CK*
MEM_B_CS_L<0> H2
CS*
14 29 30 33 66 33 30 29 14
66
66 33 30 29 14
MEM_B_ZQ2
MEM_B_A<9>
66 33 30 29 14
66 33 30 29 14
66 33 30 29 14
14 29 30 33 66
H9
N7
OMIT
DQ0 B3 MEM_B_DQ<30>
DQ1 C7 MEM_B_DQ<29>
14 66
14 66
DQ2 C2 MEM_B_DQ<24>
DQ3 C8 MEM_B_DQ<28>
DQ4 E3 MEM_B_DQ<27>
14 66
14 66
14 66
DQ5 E8 MEM_B_DQ<25>
DQ6 D2 MEM_B_DQ<31>
14 66
14 66
DQ7 E7 MEM_B_DQ<26>
14 66
14 66
14 66
A8
A9
A10/AP
A11
14 66
TDQS* A7 NC
A3 NC
NC F1 MEM_B_ODT<1>
F9 MEM_B_CKE<1>
14 29 30 33
66
14 29 30 33
66
66 33 30 29 14
MEM_B_CS_L<1> H1
NC
H9
N7
66 33 30 29 14
MEM_B_RAS_L
F3
RAS*
J7 NC MEM_B_A<14>
66 33 30 29 14
MEM_B_CAS_L
G3
CAS*
66 33 30 29 14
MEM_B_WE_L
H3
WE*
29
14 29 30
33 66
A6
A7
N8
M3
14 66
TDQS* A7 NC
NC F1 MEM_B_ODT<1>
F9 MEM_B_CKE<1>
A0
L3
29
14 29 30 33 66
MEM_B_ODT<0> G1
MF 1% 1/20W 201
A8
VSSQ
L1
J1
J9
R33301
DQ7 E7 MEM_B_DQ<23>
66 33 30 29 14
WE*
F2
F8
A6
A7
66 33 30 29 14
CAS*
D8
A0
N8
M3
14 29 30 33 66
NC
A8
B1
D9
D1
B8
C9
B2
N9
L9
N1
66 33 30 29 14
14 66
H9
N7
VSSQ
L1
J1
J9
F8
D8
F2
A8
B1
MEM_B_A<2>
A1
A2
14 66
TDQS* A7 NC
MEM_B_ZQ1
66 33 30 29 14
L3
14 66
14 66
CS*
MEM_B_A<1>
14 66
NC F1 MEM_B_ODT<1>
F9 MEM_B_CKE<1>
66 33 30 29 14
K3
L7
14 66
14 66
A3
MEM_B_A<0>
14 66
VSS
A1
A2
B9
C1
M1
M9
K9
A11
A12/BC*
MEM_B_A<13>
66 33 30 29 14
K7
A10/AP
66 33 30 29 14
14 29 30 33
66 33 30 29 14
66
14 29 30 33 66
66 33 30 29 14
MEM_B_A<14>
MEM_B_A<12>
DQ7 E7 MEM_B_DQ<15>
A8
A9
66 33 30 29 14
66 33 30 29 14
NC
A7
MEM_B_A<9>
66 33 30 29 14
NC F1 MEM_B_ODT<1>
F9 MEM_B_CKE<1>
H9 MEM_B_ZQ0 29
MEM_B_A<8>
M2
N8
66 33 30 29 14
A13
66 33 30 29 14
66 33 30 29 14
66 33 30 29 14
14 66
14 66
A5
A6
66 33 30 29 14
66 33 30 29 14
66 30 29 28 27 26
VSSQ
VSS
MEM_B_ZQ3
29
14 29 30 33 66
VSSQ
D1
D9
MEM_B_A<9>
DQ6 D2 MEM_B_DQ<6>
DQ7 E7 MEM_B_DQ<7>
A7
A8
L2
M8
ZQ
MF 1% 1/20W 201
14 66
OMIT
C9
66 33 30 29 14
A6
MEM_B_A<5>
DQ4 E3 MEM_B_DQ<10>
DQ5 E8 MEM_B_DQ<13>
DQ6 D2 MEM_B_DQ<11>
RESET*
20%
4V
201
B2
B8
N8
66 33 30 29 14
L8
2 MEM_B_ZQ2 H8
ODT
0.47UF
U3330
N9
M8
M2
MEM_B_A<8>
MEM_B_A<4>
240
N2
C3332
2 CERM-X5R
MT41J128M8HX-187E
MEM_B_A<7>
66 33 30 29 14
66 33 30 29 14
14 66
A3
A4
R33201
DQ0 B3 MEM_B_DQ<14>
DQ1 C7 MEM_B_DQ<9>
DQ2 C2 MEM_B_DQ<8>
DQ3 C8 MEM_B_DQ<12>
MEM_RESET_L
VDDQ
N1
MEM_B_A<6>
66 33 30 29 14
14 66
201
4V
66 33 30 29 14
MEM_B_A<3>
14 66
A2
201
4V
VDD
L1
L9
MEM_B_A<5>
66 33 30 29 14
L3
K2
20%
J9
66 33 30 29 14
L8
L2
L7
MEM_B_A<2>
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
F8
J1
MEM_B_A<4>
MEM_B_A<1>
20%
4V
CERM-X5R
201
=PP1V5_S3_MEM_B
F2
MEM_B_A<3>
66 33 30 29 14
66 33 30 29 14
14 66
A0
A1
C3331 1
B1
D8
A4
A5
66 33 30 29 14
66 33 30 29 14
DQ3 C8 MEM_B_DQ<3>
DQ4 E3 MEM_B_DQ<0>
DQ5 E8 MEM_B_DQ<5>
ZQ
A1
A8
A2
A3
K2
14 66
K3
MEM_B_ODT<0> G1
D9
MEM_B_A<2>
A1
MEM_B_A<0>
66 33 30 29 14
66 30 29 28 27 26
D1
66 33 30 29 14
L7
L3
66 33 30 29 14
OMIT
B2
MEM_B_A<1>
2 MEM_B_ZQ1 H8
MF 1% 1/20W 201
14 66
C3330
FBGA
N9
66 33 30 29 14
R33101
DQ0 B3 MEM_B_DQ<1>
DQ1 C7 MEM_B_DQ<4>
DQ2 C2 MEM_B_DQ<2>
240
70 30 29 28 27 25
C3322
0.47UF
VDDQ
N1
A0
RESET*
N2
A1
MEM_B_A<0>
ODT
MEM_RESET_L
K3
MF 1% 1/20W 201
66 33 30 29 14
MEM_B_ODT<0> G1
FBGA
J1
J9
ZQ
66 33 30 29 14
66 30 29 28 27 26
70 30 29 28 27 25
U3320
FBGA
OMIT
F8
H8
G8
K1
D7
G2
A9
U3310
201
4V
VDD
D8
F2
MEM_B_ZQ0
201
4V
=PP1V5_S3_MEM_B
B1
20%
A1
A8
RESET*
N2
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
201
MEM_RESET_L
240
MT41J128M8HX-187E
R33001
ODT
30 29 28 27 26
66
MEM_B_ODT<0> G1
20%
2 4V
CERM-X5R
FBGA
66 33 30 29 14
0.47UF
VDDQ
C3321 1
MT41J128M8HX-187E
201
4V
VDD
L1
L9
201
4V
U3300
C3320
J8
20%
70 30 29 28 27 25
C3312
E1
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
201
VREFCA
20%
4V
2 CERM-X5R
C3311 1
VREFDQ
VDDQ
A2
C3310
0.47UF
J8
C3302
E1
E2
E9
B9
C1
M1
M9
K9
G8
K1
G2
A9
D7
A2
VDD
70 30 29 28 27 25
=PP1V5_S3_MEM_B
B8
C9
MT41J128M8HX-187E
201
4V
70 30 29 28 27 25
VREFCA
201
4V
J8
E1
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
VREFDQ
20%
C3301 1
VREFCA
VREFDQ
C3300
70 30 29 28 27 25
=PP1V5_S3_MEM_B
E9
E2
70 30 29 28 27 25
D9
C9
D1
70 30 29 28 27 25

SYNC_DATE=(MASTER)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
29
71
MEM_B_A<13>
N3
66 33 30 29 14
MEM_B_BA<0>
J2
BA0
66 33 30 29 14
MEM_B_BA<1>
K8
J3
BA1
BA2
MEM_B_BA<2>
66 33 30 29 14
MEM_B_CKE<0> G9
A12/BC*
A13
14 66
14 66
TDQS* A7 NC
A3
NC
66 33 30 29 14
MEM_B_A<10>
66 33 30 29 14
MEM_B_A<11>
M7
66 33 30 29 14
MEM_B_A<13>
K7
N3
66 33 30 29 14
MEM_B_BA<0>
J2
66 33 30 29 14
MEM_B_CLK_P<0>F7
CK
66 33 30 29 14
MEM_B_CLK_N<0>G7
CK*
66 33 30 29 14
MEM_B_CS_L<0> H2
CS*
MEM_B_BA<1>
K8
66 33 30 29 14
MEM_B_BA<2>
J3
BA2
66 33 30 29 14
MEM_B_CKE<0> G9
CKE
H9
66 33 30 29 14
MEM_B_CS_L<1> H1
66 33 30 29 14
MEM_B_RAS_L
F3
RAS*
66 33 30 29 14
MEM_B_CAS_L
G3
CAS*
NC
MEM_B_ZQ8
14 29 30 33
66 33 30 29 14
66
14 29 30 33 66
66 33 30 29 14
N7
J7 NC
66 33 30 29 14
MEM_B_WE_L
H3
MEM_B_A<14>
66 33 30 29 14
14 29 30 33 66
WE*
66 33 30 29 14
CK
CK*
MEM_B_CS_L<0> H2
CS*
F3
RAS*
MEM_B_CAS_L
G3
CAS*
H3
A3
A4
66 33 30 29 14
MEM_B_A<5>
66 33 30 29 14
MEM_B_A<6>
L2
M8
A5
A6
A7
14 66
66 33 30 29 14
MEM_B_A<7>
66 33 30 29 14
MEM_B_A<8>
M2
N8
66 33 30 29 14
NC
NC F1 MEM_B_ODT<1>
F9 MEM_B_CKE<1>
H9 MEM_B_ZQ9 30
N7
J7
14 29 30 33 66
DQ4 E3 MEM_B_DQ<50>
DQ5 E8 MEM_B_DQ<51>
DQ6 D2 MEM_B_DQ<54>
DQ7 E7 MEM_B_DQ<52>
A8
A9
MEM_B_A<9>
M3
66 33 30 29 14
MEM_B_A<10>
66 33 30 29 14
MEM_B_A<11>
H7
M7
66 33 30 29 14
MEM_B_A<12>
K7
A11
A12/BC*
66 33 30 29 14
MEM_B_A<13>
N3
A13
66 33 30 29 14
MEM_B_BA<0>
BA0
BA1
A10/AP
66 33 30 29 14
MEM_B_BA<1>
J2
K8
66 33 30 29 14
MEM_B_BA<2>
J3
BA2
66 33 30 29 14
MEM_B_CKE<0> G9
CKE
66 33 30 29 14
MEM_B_A<0>
K3
14 66
66 33 30 29 14
MEM_B_A<1>
L7
14 66
66 33 30 29 14
MEM_B_A<2>
14 66
66 33 30 29 14
MEM_B_A<3>
L3
K2
14 66
66 33 30 29 14
MEM_B_A<4>
L8
A3
A4
14 66
66 33 30 29 14
MEM_B_A<5>
66 33 30 29 14
MEM_B_A<6>
L2
M8
A5
A6
66 33 30 29 14
MEM_B_A<7>
MEM_B_A<8>
M2
N8
A7
66 33 30 29 14
14 66
14 66
14 66
14 66
A3
NC
MEM_B_CLK_P<0>F7
CK
MEM_B_CLK_N<0>G7
CK*
66 33 30 29 14
MEM_B_CS_L<0> H2
CS*
66 33 30 29 14
MEM_B_CS_L<1> H1
NC
H9
N7
66 33 30 29 14
MEM_B_RAS_L
F3
RAS*
J7 NC
66 33 30 29 14
MEM_B_CAS_L
G3
CAS*
66 33 30 29 14
MEM_B_WE_L
H3
WE*
NC F1 MEM_B_ODT<1>
F9 MEM_B_CKE<1>
WE*
E9
E2
B9
C1
M9
K1
K9
M1
DQ0 B3 MEM_B_DQ<61>
DQ1 C7 MEM_B_DQ<57>
DQ2 C2 MEM_B_DQ<58>
DQ3 C8 MEM_B_DQ<56>
MEM_B_A<9>
M3
MEM_B_A<10>
H7
M7
66 33 30 29 14
MEM_B_A<12>
K7
A11
A12/BC*
66 33 30 29 14
MEM_B_A<13>
N3
A13
66 33 30 29 14
MEM_B_BA<0>
BA0
BA1
14 66
14 66
A10/AP
14 66
14 66
14 66
14 66
14 66
TDQS* A7 NC
MEM_B_BA<1>
66 33 30 29 14
MEM_B_BA<2>
J3
BA2
66 33 30 29 14
MEM_B_CKE<0> G9
CKE
66 33 30 29 14
MEM_B_CLK_P<0>F7
CK
MEM_B_CLK_N<0>G7
CK*
MEM_B_CS_L<0> H2
CS*
66 33 30 29 14
MEM_B_CS_L<1> H1
NC
H9
N7
66 33 30 29 14
MEM_B_RAS_L
F3
RAS*
J7 NC
14 29 30 33 66
66 33 30 29 14
MEM_B_CAS_L
G3
CAS*
MEM_B_WE_L
H3
WE*
A3
NC
NC F1 MEM_B_ODT<1>
F9 MEM_B_CKE<1>
14 29 30 33 66
14 29 30 33 66
MEM_B_ZQ11 30
MEM_B_A<14>
14 29 30 33
66
VSSQ
VSS
14 66
14 66
66 33 30 29 14
66 33 30 29 14
14 66
DQ7 E7 MEM_B_DQ<63>
J2
K8
14 29 30 33 66 33 30 29 14
66
14 66
DQ4 E3 MEM_B_DQ<59>
DQ5 E8 MEM_B_DQ<60>
DQ6 D2 MEM_B_DQ<62>
A8
A9
MEM_B_A<11>
66 33 30 29 14
14 29 30 33 66
MEM_B_A<14>
A2
66 33 30 29 14
MEM_B_ZQ10 30
14 29 30 33 66
A0
A1
66 33 30 29 14
66 33 30 29 14
14 66
TDQS* A7 NC
66 33 30 29 14
NC
ZQ
14 66
66 33 30 29 14
14 29 30 33 66
MEM_B_A<14>
DQ0 B3 MEM_B_DQ<49>
DQ1 C7 MEM_B_DQ<53>
DQ2 C2 MEM_B_DQ<55>
DQ3 C8 MEM_B_DQ<48>
MT41J128M8HX-187E
L8
2 MEM_B_ZQ11 H8
MEM_B_A<4>
A2
G8
D7
G2
A9
A2
J8
E1
VREFDQ
VREFCA
E9
C1
E2
B9
M9
M1
K1
K9
G2
G8
D7
A2
A9
J8
E1
E2
E9
B9
M9
K9
M1
K1
G2
G8
A9
D7
A3
VSS
D1
D9
B8
C9
B2
N9
N1
L1
L9
66 33 30 29 14
14 66
14 66
NC
MEM_B_RAS_L
MEM_B_WE_L
L3
K2
14 66
TDQS* A7 NC
VSSQ
J9
F8
J1
D8
F2
A1
A8
B1
VSS
MEM_B_CLK_N<0>G7
MEM_B_CS_L<1> H1
66 33 30 29 14
MEM_B_A<3>
14 66
30
66 33 30 29 14
66 33 30 29 14
MEM_B_CLK_P<0>F7
MEM_B_A<2>
14 66
14 66
66 33 30 29 14
A13
66 33 30 29 14
66 33 30 29 14
NC F1 MEM_B_ODT<1>
F9 MEM_B_CKE<1>
A12/BC*
BA0
BA1
CKE
66 33 30 29 14
MEM_B_A<12>
A10/AP
A11
L7
14 66
A9
MEM_B_A<1>
14 66
240
MF 1% 1/20W 201
OMIT
VSSQ
VSS
VSSQ
D9
66 33 30 29 14
A11
M3
H7
66 33 30 29 14
14 66
A0
A1
RESET*
N2
C9
D1
M7
K7
MEM_B_A<9>
K3
R34301
ODT
MEM_RESET_L
B8
MEM_B_A<12>
66 33 30 29 14
DQ6 D2 MEM_B_DQ<46>
DQ7 E7 MEM_B_DQ<40>
A7
A8
MEM_B_A<0>
20%
FBGA
MEM_B_ODT<0> G1
B2
H7
MEM_B_A<11>
66 33 30 29 14
14 66
A6
66 33 30 29 14
0.47UF
201
N1
N9
MEM_B_A<10>
66 33 30 29 14
N8
14 66
C3432
U3430
L9
66 33 30 29 14
66 33 30 29 14
A9
A10/AP
M8
M2
MEM_B_A<8>
MEM_B_A<6>
DQ3 C8 MEM_B_DQ<47>
DQ4 E3 MEM_B_DQ<44>
DQ5 E8 MEM_B_DQ<45>
ZQ
VDDQ
2 4V
CERM-X5R
J9
L1
MEM_B_A<9>
MEM_B_A<7>
66 33 30 29 14
201
4V
J1
66 33 30 29 14
66 33 30 29 14
66 33 30 29 14
14 66
201
4V
VDD
F2
F8
MEM_B_A<8>
20%
D8
A8
MEM_B_A<7>
66 33 30 29 14
MEM_B_A<5>
20%
=PP1V5_S3_MEM_B
A8
B1
N8
M3
66 33 30 29 14
66 33 30 29 14
14 66
A4
A5
C3431 1
A1
A6
A7
L8
L2
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
66 33 30 29 14
D1
D9
M8
M2
MEM_B_A<4>
14 66
20%
4V
CERM-X5R
201
66 30 29 28 27 26
B2
B8
MEM_B_A<6>
66 33 30 29 14
14 66
C3430
OMIT
N1
N9
66 33 30 29 14
DQ5 E8 MEM_B_DQ<36>
DQ6 D2 MEM_B_DQ<34>
DQ7 E7 MEM_B_DQ<39>
K2
2 MEM_B_ZQ10 H8
A4
A5
MEM_B_A<3>
A2
A3
240
F8
J1
L2
66 33 30 29 14
14 66
A1
70 30 29 28 27 25
U3420
F2
MEM_B_A<5>
L7
L3
C3422
0.47UF
VDDQ
2
MF 1% 1/20W 201
B1
D8
66 33 30 29 14
A3
MEM_B_A<2>
RESET*
N2
A8
K2
L8
MEM_B_A<1>
66 33 30 29 14
ODT
MEM_RESET_L
A1
66 33 30 29 14
MEM_B_A<4>
66 33 30 29 14
14 66
A0
R34201
DQ0 B3 MEM_B_DQ<43>
DQ1 C7 MEM_B_DQ<41>
DQ2 C2 MEM_B_DQ<42>
MEM_B_ODT<0> G1
D9
MEM_B_A<3>
66 33 30 29 14
14 66
K3
MEM_B_A<0>
D1
66 33 30 29 14
DQ2 C2 MEM_B_DQ<35>
DQ3 C8 MEM_B_DQ<32>
DQ4 E3 MEM_B_DQ<37>
ZQ
MF 1% 1/20W 201
14 66
66 33 30 29 14
66 30 29 28 27 26
B8
C9
L3
201
4V
VDD
70 30 29 28 27 25
FBGA
OMIT
B2
MEM_B_A<2>
2 MEM_B_ZQ9 H8
RESET*
N9
66 33 30 29 14
A1
A2
R34101
DQ0 B3 MEM_B_DQ<38>
DQ1 C7 MEM_B_DQ<33>
240
ODT
MT41J128M8HX-187E
MEM_B_A<1>
A0
MEM_RESET_L N2
N1
66 33 30 29 14
K3
L7
MEM_B_ODT<0> G1
MEM_B_A<0>
66 33 30 29 14
66 30 29 28 27 26
J1
J9
MF 1% 1/20W 201
66 33 30 29 14
201
4V
U3410
F8
ZQ
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
201
D8
F2
2 MEM_B_ZQ8H8
RESET*
B1
N2
20%
=PP1V5_S3_MEM_B
FBGA
OMIT
A1
A8
240
ODT
MT41J128M8HX-187E
R34001
MEM_RESET_L
66 30 29 28 27 26
MEM_B_ODT<0> G1
20%
4V
2 CERM-X5R
FBGA
66 33 30 29 14
0.47UF
VDDQ
C3421 1
C9
201
4V
VDD
L1
L9
201
4V
U3400
C3420
MT41J128M8HX-187E
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
201
70 30 29 28 27 25
C3412
J9
20%
2 CERM-X5R
VREFCA
20%
4V
C3411 1
VREFDQ
VDDQ
A2
C3410
0.47UF
J8
C3402
E1
E9
B9
M9
K9
M1
K1
G2
G8
D7
A2
A9
J8
VDD
70 30 29 28 27 25
=PP1V5_S3_MEM_B
C1
L1
L9
201
4V
70 30 29 28 27 25
VREFCA
201
4V
VREFDQ
20%
0.47UF 2 0.47UF 2
CERM-X5R
CERM-X5R
E1
C3401 1
VREFCA
20%
VREFDQ
C3400
70 30 29 28 27 25
=PP1V5_S3_MEM_B
29 28 27 25
70 30
C1
E2
29 28 27 25
70 30


SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
30
71
33 31 28 27 7
=PP1V5_S3_MEM_A
33 31 28 27 7
OMIT
1
C3500
2.2UF
2.2UF
OMIT
C3541
C3551
2.2UF
20%
6.3V
2 CERM
402-LF
20%
6.3V
2 CERM
402-LF
OMIT
C3512
2.2UF
2 CAPS ALONG PACKAGE EDGE
2.2UF
2.2UF
20%
6.3V
2 CERM
402-LF
C3550
20%
6.3V
2 CERM
402-LF
OMIT
C3531
OMIT
1
20%
6.3V
2 CERM
402-LF
2.2UF
20%
6.3V
2 CERM
402-LF
C3540
2.2UF
OMIT
1
2.2UF
20%
6.3V
2 CERM
402-LF
C3530
20%
6.3V
2 CERM
402-LF
C3521
OMIT
OMIT
2.2UF
OMIT
C3511
2.2UF
20%
6.3V
2 CERM
402-LF
C3520
20%
6.3V
2 CERM
402-LF
OMIT
C3501
D
OMIT
2.2UF
20%
6.3V
2 CERM
402-LF
OMIT
1
C3510
2.2UF
20%
6.3V
2 CERM
402-LF
=PP1V5_S3_MEM_A
OMIT
OMIT
C3542
2.2UF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
C
OMIT
1
OMIT
C3504
2.2UF
2.2UF
20%
2 6.3V
CERM
402-LF
2.2UF
2.2UF
OMIT
C3545
2.2UF
20%
6.3V
2 CERM
402-LF
C3554
20%
2 6.3V
CERM
402-LF
OMIT
C3535
C3555
2.2UF
20%
6.3V
2 CERM
402-LF
OMIT
1
20%
2 6.3V
CERM
402-LF
2.2UF
20%
6.3V
2 CERM
402-LF
C3544
2.2UF
OMIT
1
2.2UF
20%
6.3V
2 CERM
402-LF
20%
2 6.3V
CERM
402-LF
C3525
OMIT
OMIT
C3534
2.2UF
OMIT
C3515
2.2UF
20%
6.3V
2 CERM
402-LF
20%
2 6.3V
CERM
402-LF
OMIT
C3505
OMIT
C3524
2.2UF
20%
2 6.3V
CERM
402-LF
OMIT
1
OMIT
C3514
20%
6.3V
2 CERM
402-LF
OMIT
C3516
2.2UF
C3546
2.2UF
20%
6.3V
2 CERM
402-LF
20%
6.3V
2 CERM
402-LF
COLUMN OF THREE CAPS BETWEEN PACKAGES
B
APPROXIMATE CAP ARRANGEMENT
TWO 0402 CAPS ALONG PACKAGE EDGE
DDR BYPASSING 1
SYNC_MASTER=MEMORY

SIZE
DRAWING NUMBER
COLUMN OF THREE 0402 CAPS BETWEEN PACKAGES
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
31
71
33 32 30 29 7
=PP1V5_S3_MEM_B
33 32 30 29 7
OMIT
OMIT
C3600
20%
6.3V
CERM
402-LF
20%
6.3V
2 CERM
402-LF
2.2UF
OMIT
1
2.2UF
2.2UF
C3620
20%
6.3V
2 CERM
402-LF
C3650
2.2UF
20%
6.3V
2 CERM
402-LF
OMIT
C3641
2.2UF
C3651
2.2UF
20%
6.3V
2 CERM
402-LF
20%
6.3V
2 CERM
402-LF
OMIT
C3612
2.2UF
OMIT
C3631
OMIT
1
C3640
20%
6.3V
2 CERM
402-LF
2.2UF
20%
6.3V
2 CERM
402-LF
OMIT
2.2UF
OMIT
C3621
2.2UF
20%
6.3V
2 CERM
402-LF
C3630
20%
6.3V
2 CERM
402-LF
OMIT
C3611
OMIT
2.2UF
20%
6.3V
2 CERM
402-LF
2.2UF
20%
6.3V
2 CERM
402-LF
D
OMIT
2.2UF
OMIT
C3601
=PP1V5_S3_MEM_B
OMIT
C3610
C3642
2.2UF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
C
OMIT
1
OMIT
C3604
2.2UF
2.2UF
20%
2 6.3V
CERM
402-LF
2.2UF
OMIT
C3645
C3655
2.2UF
20%
6.3V
2 CERM
402-LF
OMIT
1
2.2UF
2.2UF
20%
6.3V
2 CERM
402-LF
C3654
20%
2 6.3V
CERM
402-LF
OMIT
C3635
2.2UF
20%
6.3V
2 CERM
402-LF
20%
2 6.3V
CERM
402-LF
OMIT
C3625
OMIT
C3644
2.2UF
20%
2 6.3V
CERM
402-LF
2.2UF
20%
6.3V
2 CERM
402-LF
OMIT
C3634
2.2UF
OMIT
C3615
2.2UF
20%
6.3V
2 CERM
402-LF
20%
2 6.3V
CERM
402-LF
OMIT
C3605
OMIT
C3624
2.2UF
20%
2 6.3V
CERM
402-LF
OMIT
1
OMIT
C3614
20%
6.3V
2 CERM
402-LF
OMIT
C3616
2.2UF
C3646
2.2UF
20%
6.3V
2 CERM
402-LF
20%
6.3V
2 CERM
402-LF
APPROXIMATE CAP ARRANGEMENT
TWO 0402 CAPS ALONG PACKAGE EDGE
DDR BYPASSING 2
SYNC_MASTER=MEMORY

COLUMN OF THREE 0402 CAPS BETWEEN PACKAGES
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
32
71
JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
MEM CLOCK TERMINATION

Place RC end termination after last DRAM
Place Source Cterm at neckdown at first DRAM
R3700
3.3PF
5%
25V
CERM 2
201
66 28 27 14
C3700
2
MEM_A_CLK_TERM_R
=PP1V5_S3_MEM_A
30
0.1UF
10%
66 28 27 14
X5R
201
6.3V
R3704
3.3PF
5%
25V
CERM 2
201
C3702
2 MEM_B_CLK_TERM_R
=PP1V5_S3_MEM_B
7 29 30 32
30
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
0.1UF
10%
X5R
201
6.3V
R3705
MEM_B_CLK_P<0>
IN
VOLTAGE=0V
5%
1/20W
MF
201
C3706 1
66 30 29 14
30
MEM_B_CLK_N<0>
IN
5%
1/20W
MF
201
66 30 29 14
IN
66 28 27 14
R3701
MEM_A_CLK_P<0>
IN
66 28 27 14
7 27 28 31
VOLTAGE=0V
5%
1/20W
MF
201
C3704 1
30
MEM_A_CLK_N<0>
66 28 27 14
66 28 27 14
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
66 28 27 14
66 28 27 14
5%
1/20W
MF
201
66 28 27 14
66 28 27 14
Unused Clock Termination
IN
IN
IN
IN
IN
IN
IN
14
66 28 27 14
MEM_A_CLK_N<1>
1
R3706
75
5%
1/20W
MF
2 201
C
14
MEM_A_CLK_P<1>
14
MEM_B_CLK_N<1>
IN
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
IN
66 28 27 14
IN
RP3702
RP3702
RP3706
RP3702
RP3701
RP3701
MEM_A_WE_L
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_RAS_L
MEM_A_CAS_L
RP3702
RP3707
RP3704
R3792
RP3707
R3793
RP3703
RP3704
RP3703
RP3704
RP3706
RP3703
RP3703
RP3704
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
R3790
R3791
RP3706
RP3706
RP3701
RP3701
RP3707
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_A<14>
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
=PP0V75_S0_MEM_VTT_A
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
0.47UF
20%
2 4V
CERM-X5R
201
1
4
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/20W
201
5% 1/32W
4X0201
5% 1/20W
7
6
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
36
36
36
36
36
36
36
201
201
5% 1/20W
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
D
1
0.47UF
C3714
0.47UF
20%
4V
2 CERM-X5R
201
C3716
0.47UF
20%
4V
2 CERM-X5R
201
1
5% 1/20W
C3712
20%
2 4V
CERM-X5R
201
201
5% 1/32W
C3710
C3713
0.47UF
20%
2 4V
CERM-X5R
201
C3715
0.47UF
20%
4V
2 CERM-X5R
201
C3717
0.47UF
20%
4V
2 CERM-X5R
201
C3718
0.47UF
20%
2 4V
CERM-X5R
201
C3720
0.47UF
20%
2 4V
CERM-X5R
201
R3707
75
5%
1/20W
MF
2 201
14
=PP0V75_S0_MEM_VTT_B
7
MEM_B_CLK_P<1>
66 30 29 14
IN
66 30 29 14
IN
MEM_B_WE_L
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
MEM_B_RAS_L
MEM_B_CAS_L
66 30 29 14
IN
MEM_B_A<0>
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
66 30 29 14
IN
IN
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
66 30 29 14
IN
RP3715
RP3715
RP3711
RP3709
RP3715
RP3715
RP3709
RP3710
RP3708
RP3709
RP3711
RP3709
RP3711
RP3708
RP3711
RP3708
RP3713
RP3710
RP3710
RP3708
RP3710
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
RP3714
RP3714
RP3713
RP3713
RP3714
RP3714
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_ODT<0>
MEM_B_ODT<1>
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
0.47UF
1
3
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
C3722
20%
4V
2 CERM-X5R
201
C3724
0.47UF
20%
4V
2 CERM-X5R
201
C3726
0.47UF
20%
4V
2 CERM-X5R
201
C3728
0.47UF
20%
4V
2 CERM-X5R
201
C3727
0.47UF
20%
4V
2 CERM-X5R
201
C3729
0.47UF
20%
4V
2 CERM-X5R
201
C3730
0.47UF
20%
2 4V
CERM-X5R
201
C3732
0.47UF
20%
4V
2 CERM-X5R
201
C3733
0.47UF
20%
4V
2 CERM-X5R
201
Memory Active Termination

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
33
71
CRITICAL
Q4101
M93 WIRELESS
AIRPORT & BT CONNECTOR
L4104
FDC638P_G
SM
FERR-120-OHM-1.5A
6
34 7
PP3V3_S3_AP_AUX
70
VOLTAGE=3.3V
PP3V3_S3_AP_AUX_F
VOLTAGE=3.3V
5%
1/20W
MF
201
1 C4108 1 C4107 1 C4109 1 C4110

1
0.1UF
10%
Q4102
D 3
10%
2 25V
CERM
402
10UF
0.1UF
10%
2 6.3V
X5R
201
5%
1/20W
MF
201
20%
6.3V
X5R
603
0.1UF
10%
2 6.3V
X5R
201
OMIT
=PP3V3_S3_BT
PM_WLAN_EN_L_SS
0.01UF
10V
201
10%
X5R
SSM6N15FEAPE
SOT563
6.3V
X5R
201
C4112
1
R4105
D 6
SSM6N15FEAPE
C4111
33NF
100K 2
Q4102
70 6
PM_WLAN_EN_L 2 100K 1
=PP3V3_S5_AIRPORT_AUX
R4104
34 7
0402-LF
4
=PP3V3_S5_AIRPORT_AUX
SOT563
CRITICAL
2 G
56 39 35 20 6
PM_SLP_S3_L
5 G
S 1
L4101
S 4
PM_WLAN_EN_L2
SMC_ADAPTER_PRESENT
34
OUT PCIE_E_D2R_N
PCIE_E_D2R_P
90-OHM-100MA
DLP11S
SYM_VER-2
CRITICAL
J4100
Q4103
D 6
34
SSM6N15FEAPE
OUT
CPB6330-0101F
31
F-ST-SM
32
SOT563
CRITICAL
2 G
L4100
S 1
67 16
PCIE_CLK100M_MINI_P
IN
90-OHM-100MA
DLP11S
SYM_VER-2
6
6
PCIE_E_D2R_N_F
PCIE_E_D2R_P_F
PM_WLAN_EN_L1
AP_PWR_EN
67 16
Q4103
SOT563
5 G
S 4
8
B
56 40 39 20
BI
BI
=USB2_BT_P
12
14
CRITICAL
15
16
L4103
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
90-OHM-100MA
DLP11S
SYM_VER-2
PCIE_CLK100M_MINI_P_F
PCIE_CLK100M_MINI_N_F
USB2_BT_P_F
USB2_BT_N_F
MINI_CLKREQ_L
PCIE_WAKE_L
AIRPORT_RST_L
=SMB_AIRPORT_CLK
=SMB_AIRPORT_DATA
16
OUT
IN
6 16
IN
6 24
BI
6 42
BI
6 42
PM_SLP_S4_L
CRITICAL
L4102
C4100
34
IN
PCIE_E_R2D_C_N
34
IN
PCIE_E_R2D_C_P
2
X5R
10%
0.1UF
201
6.3V
PCIE_MINI_D2R_N
67 16 PCIE_MINI_D2R_P
67 16 PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_C_P
67 16
PCIE_E_D2R_N
PCIE_E_D2R_P
PCIE_E_R2D_C_N
PCIE_E_R2D_C_P
2
X5R
10%
PCIE_E_R2D_N 4
PCIE_E_R2D_P 1
C4101
67 16
13
=USB2_BT_N
10
D 3
SSM6N15FEAPE
PCIE_CLK100M_MINI_N
IN
11
6
20
90-OHM-100MA
DLP11S
SYM_VER-2
36
PCIE_E_R2D_C_N_F
26
PCIE_E_R2D_C_P_F
0.1UF
201
6.3V
PLACE FILTERS NEAR CONNECTOR
PLACE C4100,C4101 < 250 MILS FROM MCP
34
MAKE_BASE=TRUE
APN:516S0580
34
MAKE_BASE=TRUE
34
MAKE_BASE=TRUE
34
MAKE_BASE=TRUE
Wireless M93 Connector

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
34
71
Micro-DisplayPort / USB to RIO Hatch Assembly

CRITICAL
J4200
54102-8640
67 61
67 61
67 61
67 61
67 61
67 61
67 61
67 61
67 61 60 6
67 61 60 6
37 6
37 6
DP_ML_F_P<0>
DP_ML_F_N<0>
DP_ML_F_P<3>
DP_ML_F_N<3>
DP_ML_F_P<1>
DP_ML_F_N<1>
DP_ML_F_P<2>
DP_ML_F_N<2>
DP_AUX_CH_C_P
DP_AUX_CH_C_N
USB2_EXTA_F_P
USB2_EXTA_F_N
F-ST-SM
1
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Audio Connector
DP_CA_DET_Q
6 61
7 6
HDMI_CEC
=PPVIN_S0_AUDIO
CRITICAL
J4260
6 61
QT500166-L020
DP_HPD_Q 6
PP3V3_S0_DPPWR 6
68 20 6
IN
68 20 6
IN
68 20
IN
61
61 70
56 39 34 20 6
PP5V_S3_USB2_EXTA_F
IN
M-ST-SM
2
1
3
4
5
6
7
8
10
9
11
12
13
14
15
16
HDA_SYNC
HDA_SDOUT
HDA_RST_L
PM_SLP_S3_L
HDA_SDIN0
OUT
AUD_MIC_CLK
AUD_MIC_DATA
HDA_BIT_CLK
6 20 68
IN
6 59
OUT
6 59
IN
6 20 68
6 37 70
516S0350
B
516S0710
Hatch and Audio Connectors
SYNC_DATE=(MASTER)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
35
71
SATA HDD PORT

CRITICAL
L4500
FERR-120-OHM-1.5A
70 6
PP3V3_S0_HDD_F
VOLTAGE=3.3V
=PP3V3_S0_HDD
C4501
0.1UF
C4502
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4500

PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4500
0.1UF
10%
2 6.3V
X5R
201
0402-LF
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
10%
2 6.3V
X5R
201
CRITICAL
FL4501
3
90-OHM-100MA
DLP11S
SYM_VER-2
PLACEMENT_NOTE=Place C4510 close to MCP79

PLACEMENT_NOTE=Place C4511 next to C4510
67
C4510
SATA_HDD_R2D_UF_P
J4500
54167-0201
67
C4511
SATA_HDD_R2D_UF_N
X7R
X7R
IN
19 67
IN
19 67
201
SATA_HDD_R2D_C_N
10% 10V
4700PF
PLACEMENT_NOTE=Place FL4501 close to J4501
SATA_HDD_R2D_C_P
10% 10V
4700PF
CRITICAL
201
F-ST-SM
67 6
10
67 6
12
11
14
13
16
15
67 6
18
17
67 6
20
19
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
CRITICAL
FL4502
C4515
10% 10V
4700PF
C4516
4700PF
67
X7R
2
10% 10V
90-OHM-100MA
DLP11S
SYM_VER-2
SATA_HDD_D2R_N
OUT
19 67
SATA_HDD_D2R_P
OUT
19 67
201
67
X7R
SATA_HDD_D2R_UF_N
SATA_HDD_D2R_UF_P
201
PLACEMENT_NOTE=Place FL4502 close to MCP79
PLACEMENT_NOTE=Place C4515 next to C4516

PLACEMENT_NOTE=Place C4516 close to J4501
516S0678
SATA Connectors
SYNC_MASTER=CHANGZHANG

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
36
71
USB 2.0 CONNECTOR

CRITICAL
L4602
FERR-120-OHM-3A
PP5V_S3_USB2_EXTA_F
CONNECT TO 5V S5 or S3 PER LAYOUT
0603
VOLTAGE=5V
CRITICAL
C4610 1
ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS

CRITICAL
100UF
20%
6.3V 2
POLY-TANT
CASE-B2-SM
L4600
90-OHM-100MA
DLP11S
PP5V_S3_USB2_EXTA_F
USB2_EXTA_F_N
USB2_EXTA_F_P
SYM_VER-1
=PP5V_S3_EXTUSB
68 37
USB_EXTA_MUXED_N
68 37
USB_EXTA_MUXED_P
OMIT
1
C4613 1 C4612
10uF
CRITICAL
0.1UF
20%
2 6.3V
X5R
U4600
10%
6.3V
X5R
201
603
VOLTAGE=5V
CRITICAL
C4602
0.01UF
10%
10V
2 X5R
201
D4600
SC-75
RCLAMP0502B
DUAL SWITCH HAS GANGED OUTPUT

BOTH SWITCHES WILL TRIP TOGETHER AT 1.5A-2.2A
56
TPAD
CONNECT TO RIO CONNECTOR J4200
6
35
PP5V_S3_USB2_EXTA
GND
70
TPS2052B
2 IN
7
OUT1
MSOP
8
OC1*
3 EN1
OUT2 6
5 OC2*
4 EN2
6 635 37 70
35 37 70
6 35
LAYOUT NOTE:C4602 IS AN EMC BY-PASS CAP FOR J4200
=USBPWR_EN
R4650
2
EXTAUSB_OC_F_L
1K
5%
1/16W
MF-LF
402
=EXTAUSB_OC_L
C4650 1
0.47UF
10%
6.3V
CERM-X5R 2
402
USB/SMC MUX
B
7
USB_EXTA_MUXED_P 37 68
USB_EXTA_MUXED_N 37 68
=PP3V42_G3H_SMCUSBMUX
R4675
100
70
PP3V42_G3H_SMCUSBMUX_R
5%
1/20W
MF
201
C4675
VOLTAGE=3.42V
R4677
0.1UF
PLACE C4675 NEAR U4675
10K
10%
6.3V
2 X5R
201
5%
1/20W
MF
2 201
VCC
SMC_RX_L
40 39 SMC_TX_L
5 M+
4 M-
41 40 39
41
CRITICAL
U4675
Y+ 1
Y- 2
PI3USB102ZLE
8
8
=USB2_EXTA_P
=USB2_EXTA_N
7 D+
6 D-
TQFN
USB_DEBUGPRT_EN_L 39
SEL 10
8 OE*
GND
3
SEL=0 CHOOSE SMC

SEL=1 CHOOSE USB
USB EXTERNAL CONNECTORS
SYNC_MASTER=M70
R4678
1
5%
1/20W
MF
201
SIGNAL_MODEL=EMPTY
NOSTUFF
PLACE NEAR U4675

NOSTUFF
R4679
1
2
SIZE
5%
1/20W
MF
201
SIGNAL_MODEL=EMPTY
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
37
71
IPD Connector
PP5V_S3_TOPCASE_F
6 38 70
OMIT
1
C4801
0.1UF
70 38
2.2UF
20%
6.3V
2 CERM
402-LF
10%
6.3V
2 X5R
201
6 PP3V42_G3H_IPD_F
C4800
CRITICAL
70 38 6
PP5V_S0_KBDLED_F
J4800
51338-0249
F-ST-SM
25
26
39 6
42 6
BI
42 6
BI
SMC_SYS_LED
=I2C_TPAD_SCL
=I2C_TPAD_SDA
R4831
LSOC_PRESS_H
49 40
10K
5%
1/20W
MF
201
1
6
40 39 38 6
LSOC_PRESS_H_R
SMC_ONOFF_L
C4831
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
SMC_LID
SMC_SYS_KBDLED
6 39 40
6 39
=USB2_IR_N
=USB2_IR_P
=USB2_TPAD_N
=USB2_TPAD_P
BI
6 8
BI
6 8
BI
6 8
BI
6 8
0.1UF
10%
6.3V
2 X5R
201
516S0591
PLACE R4800,R4801 UNDER L4800

TPAD_GND_F
NO STUFF
R4800
0
38
5%
1/10W
MF-LF
603
CRITICAL
L4800
470UH-0.3A-80V
ZCYS9480-SM-HF
SYM_VER-1
=PP5V_S3_TOPCASE
PP5V_S3_TOPCASE_F
1
2
MIN_LINE_WIDTH=0.3mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=5V
10%
2 10V
X5R
201
NO STUFF
38 7
TPAD_GND_F
R4801
0
Power Button Inverter
C4810
0.01UF
B
1
6 38 70
MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=0V
=PP3V42_G3H_IPD
38
R4830
1M
5%
1/20W
MF
201 2
5%
1/10W
MF-LF
603
SMC_ONOFF_H 40
Q4830
SSM3K15FV
CRITICAL
D 3
49
Inverted to drive SMC_RESET logic
SOD-VESM-HF
L4812
600-OHM-300MA
7
=PP5V_S0_KBDLED
PP5V_S0_KBDLED_F 6
VOLTAGE=5V
0402
1
38 70
S 2
C4812
0.01UF
40 39 38 6
10%
10V
2 X5R
201
SMC_ONOFF_L
CRITICAL
L4813
600-OHM-300MA
38
7 =PP3V42_G3H_IPD
PP3V42_G3H_IPD_F 6
VOLTAGE=3.42V
0402
IPD Connector
38 70
C4813
0.01UF
10%
10V
2 X5R
201

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
38
71
NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
70 40
40 7
PP3V3_S5_AVREF_SMC
=PP3V42_G3H_SMC
D
C4902
22UF
20%
6.3V
X5R-CERM
603
U4900
ESTARLDO_EN
D13
C12
D10
NC
NC
NC
8
SMC_P24
SMC_P26
BI
BI
68 41 18
BI
68 41 18
BI
68 41 18
IN
24
IN
68 24
41 18
IN
BI
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
42
BI
OUT
C8
B7
A8
D8
D7
D6
OUT
38 6
OUT
41 40 39 37
OUT
(OC)
41 40 39 37
42
IN
BI
B4
A1
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
D4
A5
NC
NC
8
E10
D9
47
E12
A9
NC
SMC_P41
SMB_MGMT_DATA
SMS_PWRDN
F11
F13
NC
68 41 18
D12
E13
NC
8
E11
C2
B2
C1
C3
G2
F3
(OC)
E4
P20
P21
P22
P23
P24
P25
P26
P27
P70
P71
P72
P73
P74
P75
P76
P77
N10
L12
SMC_CPU_ISENSE
SMC_ACIN_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_PBUS_ISENSE
P30
P31
P32
P33
P34
P35
P36
P37
P80
P81
P82
P83
P84
P85
P86
A7
SMC_WAKE_SCI_L
P90
P91
P92
P93
P94
P95
P96
P97
J4
SMC_ADAPTER_EN
K13
J10
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
H12
M11
L10
N11
N12
M13
N13
B6
40
IN
IN
50
IN
43
IN
IN
43
IN
58
IN
43
IN
58
IN
44
OUT
20
5%
1/16W
MF-LF
402
8 20 40
IN
4.7
70
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
C4907
C4920
P40
P41
P42
P43
P44
P45
P46
P47
(OC)
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
(OC)
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA
D5
A6
B5
G3
H2
G1
H4
G4
F4
F1
10%
6.3V
CERM-X5R
402
0.1UF
10%
6.3V
X5R
201
VCC
AVCC
VCL AVREF
R4909 1
U4900
NC
HS82117
40
40
E5
NC
LGA-HF
(3 OF 3)
OMIT
IN
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
41 40
0.47UF
SMC_RESET_L
D3
RES*
SMC_XTAL
SMC_EXTAL
A3
XTAL
EXTAL
A2
MD1
MD2
D1
NMI
E3
ETRST
H3
AVSS
L9
R4901
10K
10K
5%
1/20W
MF
201 2
5%
1/20W
MF
2 201
SMC_MD1
IN
41
SMC_NMI
IN
41
SMC_TRST_L
IN
41
SMC_KBC_MDE
H1
NC
C7
C6
OUT
NC
J11
SMC_VCL
R4999
1
L11
OUT
OUT
20
J12
56
E1
OUT
50
68 41 18
D11
C13
OUT
K11
OUT
NC
NC
NC
H10
NC
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
20
(1 OF 3)
OMIT
10%
6.3V
X5R
201
M1
B13
B1
A12
K12
0.1UF
10%
6.3V
X5R
201
OUT
18 41
IN
18 41
OUT
37 39 40 41
IN
37 39 40 41
BI
IN
42
6 38 40
IN
40 49 58
IN
6 40 49
IN
6 20 34 35 56
IN
20 34 40 56
IN
40
IN
24 68
BI
XW4900
SM
2
NOTE: P94 and P95 are shorted, P95 could be spare.
NO STUFF
1
VSS
C5
IN
L13
LGA-HF
0.1UF
2
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
SMC_PM_G2_EN
P60
P61
P62
P63
P64
P65
P66
P67
HS82117
10%
6.3V
X5R
201
C4906
B11
IN
56
P10
P11
P12
P13
P14
P15
P16
P17
0.1UF
10%
6.3V
X5R
201
F10
56 24
A13
C4905
M12
B12
0.1UF
C4904
L3
OUT
D2
SMC_P10
SMC_EXCARD_PWR_EN
ALL_SYS_PWRGD
RSMRST_PWRGD
8
8
C4903
R4902
R4998
10K
10K
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
R4903
0
5%
1/20W
MF
2 201
GND_SMC_AVSS
40 43 44 58
42
P50
P51
P52
U4900
(DEBUG_SW_1)
(DEBUG_SW_2)
24
OUT
37
OUT
20
BI
B
49 40
20
BI
OUT
SMC_PA0
SMC_PA1
PM_SYSRST_L
USB_DEBUGPRT_EN_L
MEM_EVENT_L
SMC_PA5
8
SYS_ONEWIRE
PM_BATLOW_L
8
N3
N1
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
M3
M2
N2
L1
K3
L2
B8
NC
20
OUT
40
IN
OUT
IN
IN
IN
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
ISENSE_CAL_EN
SMC_EXCARD_CP
C9
B9
A10
C10
B10
NC
46
OUT
OUT
OUT
OUT
46
IN
IN
IN
IN
47
IN
47
IN
47
IN
IN
44
IN
IN
IN
IN
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
C11
A11
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
G11
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
ALS_LEFT
ALS_RIGHT
M10
G13
F12
H13
G10
G12
H11
J13
N9
K10
L8
M9
N8
K9
L7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
HS82117
LGA-HF
(2 OF 3)
OMIT
PE0
PE1
PE2
PE3
PE4
PF0
K1
PF1
PF2
PF3
PF4
PF5
PF6
PF7
N5
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
M8
PH0
PH1
PH2
PH3
PH4
PH5
E2
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
J3
K2
J1
K4
K5
M5
M4
K7
K6
N6
M7
L6
40 41
SMC_SYS_LED
SMC_LID
OUT
6 38
MCP_SAFE_MODE
OUT
IN
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
IN
B
6 38 40
20
A4
BI
42
BI
42
BI
42
BI
42
BI
42
BI
SMC_PROCHOT
SMC_THRMTRIP
SMC_FWE
ALS_GAIN
J2
C4
40 41
IN
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
F2
B3
40 41
OUT
NC
NC
N7
K8
40 41
IN
NC
NC
N4
L4
40
IN
NC
M6
L5
IN
OUT
OUT
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
42
40
40
IN
OUT
NC
NC
SMC
SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
39
71
SMC 1.05V to 3.3V Level Shifting
SMC Reset Button / Brownout Detect

40 39 7
=PP3V42_G3H_SMC
7
C5000
R5000
0.1UF
10%
6.3V 2
X5R
201
SOT23-5-HF
5
NC
NOSTUFF
1
Silk: "SMC RST"

Place R5001 on bottom side
near board edge
R5001
0
C5001
CRITICAL
OUT
CD
NC
IN
GND
SMC_RESET_L
OUT
39 41
10%
10V 2
X5R
201
40 39 38 6
41 39
41 39
Q5030
D 3
LSOC_PRESS_H
=PP3V3_S3_SMC
10K
5%
1/20W
MF
2 201
39
SMC_PROCHOT_3_3_L
41 39
SMC_TX_L
SMC_RX_L
R5095
R5080
R5081
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
R5097
R5085
R5086
R5087
SYS_ONEWIRE
R5082 1
R5083 1
R5049 1
R50841
SMC_ONOFF_L
D 6
41 39
100K
1
1
2
2
10K
100K
1
1
1
1
2
2
2
2
10K
10K
10K
10K
2.0K
470K
CPU_PROCHOT_BUF
Q5077
BC847BV-X-F
SOT563-HF
R5071
65 50 40 13 9
CPU_PROCHOT_L
3.3K 2
5%
1/20W
MF
201
6
2
Q5077
BC847BV-X-F
SOT563-HF
CPU_PROCHOT_L_R
1
SMC_MANUAL_RST_L1
49 39
SSM6N15FEAPE
SOT563
49 39 6
39
5 G
49 38
R5098
SMC_SMS_INT_L
SOT563
49 38
5%
1/20W
MF
2 201
3.3K
0.01UF
5%
1/10W
MF-LF
2 603
470
SSM6N15FEAPE
S 1
R5078
R5070
41 39 37
2 G
41 39 37
Q5030
=PP1V05_S0_SMC_LS
7 39 40
5%
1/20W
MF
2 201
NCP303LSN
SMC_MANUAL_RST_L
=PP3V42_G3H_SMC
1K
U5000
=PP3V3_S0_SMC_LS
S 4
Q5030 will pull down

SMC_MANUAL_RST_L in the event
of a keyboard SMC Reset
generated when left shift,option,and control
and the power button is depressed.
SMC_ONOFF_H
58 49 39
39 38 6
SMC_BS_ALRT_L
SMC_ODD_DETECT
SMC_BC_ACOK
R5073
SMC_LID
10K
10K
100K
R5092
10K
SMC_CASE_OPEN
39
R5096
10K
SMC_ADAPTER_EN
8 20 39
SMC Crystal Circuit

Debug Power Button
C5020
15PF
R5010
0
5%
1/8W
MF-LF
2 805
2
39
R5011
Y5020
20MHZ
SM-2.5X2.0MM
Silk: "PWR BTN"
PM_SLP_S5_L
PM_SLP_S4_L
20 34 39 56
MAKE_BASE=TRUE
5%
25V
NPO
201
CRITICAL
5%
1/16W
MF-LF
2 402
6 38 39 40
2 4
OUT
SMC_XTAL
C5021
NOSTUFF
SMC_ONOFF_L
NOSTUFF
39
15PF
39
SMC_EXTAL
SMC 3.3V to 1.05V Level Shifting
5%
25V
NPO
201
APN: 197S0231
Place R5011 on top side

Place R5010 on bottom side
Place both near board edge
CPU_PROCHOT_L
Q5001
D 6
Q5001
SSM6N15FEAPE
2 G
9 13 65
D 3
SSM6N15FEAPE
SOT563
39
PM_THRMTRIP_L
9 13 40 50 65
SOT563
5 G
S 1
39
SMC_PROCHOT
S 4
SMC_THRMTRIP
SMC AVREF Supply

VR5065
7
REF3333
=PP3V42_G3H_SMCVREF
PP3V3_S5_AVREF_SMC 39
SOT23-3
IN
OUT
CRITICAL
VOLTAGE=3.3V
70
GND
C5067
0.01UF
OMIT
1
C5065 C5066 1
0.47UF
10%
2 6.3V
CERM-X5R
402
10%
2 10V
X5R
201
10uF
SMC SUPPORT
20%
6.3V 2
X5R
603
GND_SMC_AVSS
SYNC_MASTER=M70
39 43 44 58
VOLTAGE=0V

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
40
71
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
MCP79 SPI Frequency Select
Frequency
SPI_MOSI
SPI_CLK
31 MHz
42 MHz
55909-0374
7
68 39 18
BI
68 39 18
BI
41
IN
41
OUT
1 MHz
68 39 18
25MHz is selected with R5190 and R5191
IN
39 18
OUT
40 39
OUT
24
IN
40 39
OUT
39
IN
39
OUT
40 39 37
41 7
48 41 7
R5192
68 41 20
IN
SPI_MOSI_R
R51911
R5190
4
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
24 68
IN
18 39 68
BI
18 39 68
BI
OUT
41
IN
41
IN
41
18 39
BI
IN
18 39
OUT
39 40
OUT
39 40
OUT
39 40
OUT
39
OUT
37 39 40
OUT
17
C5114
2 6.3V
X5R
MCP79 Internal SPI MUX Support
516S0573
201
VCC
2
1 Y+
2 Y-
LPCPLUS
U5110
Not supported in Rev A01 MCP79 silicon
SPI_ALT_CLK
SPI_ALT_MOSI
M+ 5
M- 4
OUT
41
OUT
41
OUT
41 48 68
OUT
41 48 68
MCP SPI Override Options
PI3USB102ZLE
TQFN
R5193
10K
3
5
D
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
10%
10K
5%
1/20W
MF
201
NO STUFF1
10K
CRITICAL
10 SEL
=PP3V3_S0_LPCPLUS
=PP3V42_G3H_LPCPLUS
Internal MUX in rev B01 does not work as intended.

Now MCP_CS1_YES and MCP_CS1_NO determines external MUX option.
OE* 8
R5140 1
100K
5%
1/20W
MF
201 2
41
SPIROM_USE_MLB
GND
MCP_CS1_YES
LPC_FRAME_PU
5%
1/20W
MF
201 2
SPI_CLK_MUX
SPI_MOSI_MUX
D+ 7
D- 6
5%
1/20W
MF
201 2
0.1UF
10K
5%
1/20W
MF
201
SPI_CLK_R
LPCPLUS
1
NO STUFF1
IN
IN
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
=PP3V42_G3H_LPCPLUS
=PP3V3_S5_ROM
68 41 20
LPC_AD<0>
LPC_AD<1>
25 MHz
Any of the 4 frequencies can be

selected w/ R5190,R5191,R5192,R5193
M-ST-SM
31
32
=PP3V42_G3H_LPCPLUS
=PP5V_S0_LPCPLUS
41 7
MCP_CS1_YES
R5141 1
Q5140
470
5%
1/20W
MF
201 2
SSM3J16FV
SOD-VESM-HF
MCP_CS1_NO
=PP3V42_G3H_LPCPLUS
7
41
SPIROM_USE_MLB
SEL HIGH WILL OUTPUT TO D (ON BOARD ROM)
SEL LOW WILL OUTPUT TO M (FRANKCARD ROM)
41
68 20
OUT
IN
From Frank Card
C5124
0.1UF
1 Y+
2 Y-
VCC
LPCPLUS
U5120
201
M+ 5
M- 4
SPI_ALT_MISO
TQFN
1
SPI_ALT_CS_L_MUX
1/20W
D+ 7
D- 6 SPI_MLB_CS_L_MUX
CRITICAL
10 SEL
OE* 8
IN
SPI_CS1_R_L_USE_MLB
IN
To Frank Card
41 48 68
MCP_CS1_NO
1/20W
0
5%
MF
R5126
201
GND
SPI_MLB_CS_L
MCP_CS1_NO
1
R5144
OUT
=SPI_CS1_R_L_USE_MLB
BI
20
R5143
1
SPI_MISO_MUX
18
MAKE_BASE=TRUE
MCP_CS1_YES
Pull-up on debug card

R5127 SPI_ALT_CS_L OUT 41
201
5%
MF
OUT
41
MCP_CS1_NO
PI3USB102ZLE
5% PLACEMENT_NOTE=Place near J5100

1/20W
MF
201
10%
SPI_MISO
SPI_CS0_R_L
2 6.3V
X5R
9
68 41 20
LPC_FRAME_R_L
R5142
LPCPLUS
2
5% PLACEMENT_NOTE=PLACE NEAR R5147
1/20W
MF
201
48 68
=PP3V3_S5_ROM
7 41 48
20K
5%
1/20W
MF
201 2
MCP_CS1_YES&LPCPLUS_NOT
R5146
0
5%
PLACEMENT_NOTE=PLACE NEXT TO U1400
1/20W
MF
201
SPI MUX BYPASS

LPCPLUS_NOT
R5156
68 48 41
OUT
SPI_CLK_MUX
5%
1/20W
MF
201
68 48 41
OUT
SPI_MOSI_MUX
R5158
IN
SPI_MISO_MUX
0
1
IN
20 41 68
SPI_MOSI_R
IN
20 41 68
OUT
20 41 68
R5157
LPCPLUS_NOT
68 48 41
SPI_CLK_R
LPCPLUS_NOT
2
5%
1/20W
MF
201
SPI_MISO
LPC+SPI Debug Connector
5%
1/20W
MF
201

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
41
71
SMC "A" SMBus Connections
SMC "Management" SMBus Connections
SMC "0" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
7
R5200
SMC
U4900
(MASTER)
39
SMB_A_S3_CLK
The bus formerly known as "Battery B"
=PP3V3_S3_SMBUS_SMC_A_S3
69
R5201
4.7K
4.7K
5%
1/20W
MF
201
5%
1/20W
MF
201
SMBUS_SMC_A_S3_SCL
TRACKPAD
SMC
J4800
(Write: 0x92 Read: 0x93)
U4900
(MASTER)
=I2C_TPAD_SCL
6 38
39
R5220
SMB_0_S0_CLK
69
MAKE_BASE=TRUE
39
SMB_A_S3_DATA
69
=PP3V3_S0_SMBUS_SMC_0_S0
R5221
4.7K
4.7K
5%
1/20W
MF
201
5%
1/20W
MF
201
U4900
(MASTER)
EMC1403-5: U5515
=I2C_CPUTHMSNS_SCL
39
SMB_MGMT_CLK
69
39
SMB_MGMT_DATA
69
SMBUS_SMC_A_S3_SDA
=I2C_TPAD_SDA
6 38
39
SMB_0_S0_DATA
69
SMBUS_SMC_0_S0_SDA
=I2C_CPUTHMSNS_SDA
R5241
2.2K
2.2K
5%
1/20W
MF
201
5%
1/20W
MF
201
Vref DACs
U2900
SMBUS_SMC_MGMT_SCL
=I2C_VREFDACS_SCL
25
=I2C_VREFDACS_SDA
25
MAKE_BASE=TRUE
45
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R5240 1
SMC
CPU Temp
SMBUS_SMC_0_S0_SCL
=PP3V3_S3_SMBUS_SMC_MGMT
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
45
MAKE_BASE=TRUE
Front Edge Temp
M93 Wireless Card
=SMB_AIRPORT_CLK
Margin Control
TMP102: U5570
J4100
U2901
THRM_FRONT_SMB_CLK
45
=I2C_PCA9557D_SCL
25
THRM_FRONT_SMB_DATA
45
=I2C_PCA9557D_SDA
25
6 34
=SMB_AIRPORT_DATA
6 34
ALS
SMC "B" SMBus Connections

7
=PP3V3_S0_SMBUS_SMC_B_S0
R5210 1
SMC
U4900
(MASTER)
39
SMB_B_S0_CLK
69
39
SMB_B_S0_DATA
69
R5211
4.7K
4.7K
5%
1/20W
MF
201
5%
1/20W
MF
201
SMBUS_SMC_B_S0_SCL
J9000
SMC "Battery A" SMBus Connections
Air Vent Temp
=PP3V42_G3H_SMBUS_SMC_BSA
R5230 1
SMC
TMP102: U5560
U4900
(MASTER)
THRM_VENT_SMB_CLK
45
39
SMB_BSA_CLK
THRM_VENT_SMB_DATA
45
39
SMB_BSA_DATA
R5231
2.2K
2.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
J6950
(See Table)
6 59
MCP79 SMBUS "0" CONNECTIONS
=SMBUS_BATT_SCL
49
=SMBUS_BATT_SDA
49
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
6 59
=I2C_ALS_SDA
Battery
SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
=I2C_ALS_SCL
=PP3V3_S0_SMBUS_MCP_0
MAKE_BASE=TRUE
TMP102: U5550
THRM_PS_SMB_CLK
45
THRM_PS_SMB_DATA
R5250 1
MCP79
Power Supply Temp
Battery Charger
U1400
(MASTER)
ISL6258A - U7900
Battery
Battery Manager - (Write: 0x?? Read: 0x??)
Battery Temp - (Write: 0x?? Read: 0x??)
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
45
68 20 12 6
SMBUS_MCP_0_CLK
68 20 12 6
SMBUS_MCP_0_DATA
R5251
10K
10K
5%
1/20W
MF
201 2
5%
1/20W
MF
2 201
MAKE_BASE=TRUE
58
MAKE_BASE=TRUE
58
MCP79 SMBUS "1" CONNECTIONS

7
=PP3V3_S5_SMBUS_MCP_1
R5260 1
MCP79
U1400
(MASTER?)
68 20
SMBUS_MCP_1_CLK
68 20
SMBUS_MCP_1_DATA
R5261
10K
10K
5%
1/20W
MF
201 2
5%
1/20W
MF
2 201
MAKE_BASE=TRUE
MAKE_BASE=TRUE
M97 SMBUS CONNECTIONS
SYNC_MASTER=BEN

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
42
71
ACIN VOLTAGE SENSE
70 58
PPVDCIN_G3H_PRE
MAX 16.5V + 10% ACIN = 3.0V SMC_ACIN_VSENSE

R5300 and R5301 VALUES CHOSEN FOR RC FILTER @ 4.53KOHM THEVENIN RESISTANCE
1
R5300
27.4K
1%
1/20W
MF
2 201
SMC_ACIN_VSENSE 39
1
R5301
5.36K
1%
1/20W
MF
2 201
C5300
0.22UF
10%
2 6.3V
CERM-X5R
402
GND_SMC_AVSS
39 40 43 44 58
PLACE C5300 NEAR SMC
MCP VOLTAGE SENSE

R5310
7
4.53K2
=PPVCORE_S0_MCP_VSENSE
SMC_GPU_VSENSE
1%
1/20W
MF
201
39
C5310
0.22UF
10%
2 6.3V
CERM-X5R
402
GND_SMC_AVSS
39 40 43 44 58
PLACE R5310.C5310 NEAR SMC
PBUS VOLTAGE SENSE

B
Q5315
NTUD3127CXXG
PBUSISENSE_EN_L OUT TO PBUS CURRENT SENSOR
SOT-963
N-CHANNEL
PBUSVSENS_EN_L
R5316 1
56
IN
=PBUSVSENS_EN
Enables PBUS VSense

divider when high.
100K
1
3
D
5
7
1%
1/20W
MF
201
2
70
PPBUS_G3HRS5_VSENSE
VOLTAGE=18.5V
R5385 1
12.7K
1%
1/20W
MF
201
=PPBUS_G3HRS5
4
RTHEVENIN = 4573 OHMS
P-CHANNEL
SMC_PBUS_VSENSE
OUT
39
R53151
100K
1%
1/16W
MF-LF
402
R5386
1
1
6.98K
1%
1/20W
MF
201
PBUSVSENS_EN_L_DIV
C5385
0.22UF
2
2
20%
6.3V
X5R
402
GND_SMC_AVSS
39 40 43 44 58
Voltage Sensors
Place RC close to SMC
SYNC_MASTER=M70

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
43
71
MCP VCore Current Sense

MCP VCore Current Sense Filter
R5416
51
IN
MCPCORE_IOUT
4.53K
SMC_NB_CORE_ISENSE
1%
1/20W
MF
201
OUT
39
C5472
0.22UF
20%
6.3V
X5R
402
GND_SMC_AVSS
39 40 43 44 58
Place RC close to SMC
PBUS Current Sense

=PPBUSB_G3H
R5481
58 7
21
1%
1/16W
MF-LF
402
10%
16V
2 X5R
U5480
LTC6102AP
C5480
0.1UF
V+
402
DFN
58 7
43
=PPBUSA_G3H
-INF
-INS
+IN
VREG
CRITICAL
6
4
SHDN
V-
THM
PAD
PBUS_ISENSE_VREG
PLACE C CLOSE TO SMC
OUT
PBUS_ISENSE_IN_NEG
SMC_PBUS_ISENSE
1
R5489
C5489
0.22UF
4.53K
1%
1/20W
MF
2 201
39
20%
6.3V
X5R
402
GND_SMC_AVSS 39
40 43 44 58
PBUSISENSE_EN_L
LTC6102 DISABLED WHEN SHDN=1
LTC6102 ENABLED WHEN SHDN=0
Current Sensing
SYNC_MASTER=YUNWU

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
44
71
CPU/MCP T-Diode Thermal Sensor
LOCAL TEMP NEAR FRONT EDGE
INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE

45 7
R5515
=PP3V3_S0_THRM_SNR
47
1
70
=PP3V3_S0_THRM_SNR
PP3V3_S0_CPUTHMSNS_R
VDD
9
BI
C5521
DETECT CPU DIE TEMPERATURE
BI
DFN
DP1
R5516 1
10K
5%
1/20W
MF
201
10%
6.3V
X5R
201
R5517
C5570 1
10K
0.1UF
5%
1/20W
MF
201
10%
6.3V 2
X5R
201
THERM*
CPUTHMSNS_THERM_L
ALERT*
CPUTHMSNS_ALERT_L
SMDATA
=I2C_CPUTHMSNS_SDA
BI
42
SMCLK
=I2C_CPUTHMSNS_SCL
BI
42
V+
2.2NF
10%
10V
X5R
201
EMC1403-1
SIGNAL_MODEL=EMPTY
C5515
0.1uF
U5515
CPU_THERMD_P
7 45
VOLTAGE=3.3V
5%
1/20W
MF
201
DN1
U5570
DP2
CPU_THERMD_N
DN2
CRITICAL
GND
HPA00330AI
42
THRM_PAD
42
BI
BI
THRM_FRONT_SMB_DATA
THRM_FRONT_SMB_CLK
SOT563
6
1
SDA
ADD0
CRITICAL
SCL
ALERT
4
3
GND
20
BI
MCP_THMDIODE_P
SIGNAL_MODEL=EMPTY
C5520
2.2NF
DETECT MCP DIE TEMPERATURE
20
BI
PLACEMENT NOTE: PLACE U5515 NEAR CPU
10%
10V
X5R
201
MCP_THMDIODE_N
LOCAL TEMP NEAR AIR VENT

=PP3V3_S0_THRM_SNR
7 45
C5560 1
0.1UF
10%
6.3V 2
X5R
201
5
V+
U5560
HPA00330AI
SOT563
42
42
BI
BI
THRM_VENT_SMB_DATA
THRM_VENT_SMB_CLK
6 SDA
ADD0
1 SCL CRITICAL
3
ALERT
GND

B
LOCAL TEMP NEAR POWER SUPPLIES

=PP3V3_S0_THRM_SNR 7
45
C5550 1
0.1UF
10%
6.3V 2
X5R
201
5
V+
U5550
HPA00330AI
SOT563
42
42
THRM_PS_SMB_DATA6
BI
THRM_PS_SMB_CLK 1
BI
SDA
ADD0
CRITICAL
SCL
ALERT
4
3
TEMPERATURE SENSORS
GND
SYNC_MASTER=M70

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
45
71
FAN CONNECTOR
C
C
7 6
=PP5V_S0_FAN
=PP3V3_S0_FAN
CRITICAL
1
J5600
R5660SM04B-SURKHF-GAN-TF-LF-SN
47K
5%
1/20W
MF
201
R5665
39
1 47K2
SMC_FAN_0_TACH
NC
2
F-RT-SM
5
FAN_RT_TACH
2
3
5%
1/20W
MF
201
NC
5V DC
TACH
MOTOR CONTROL
GND
R5661 1
Q5660
39
FAN_RT_PWM
SOD-VESM-HF
2
SMC_FAN_0_CTL
518S0658
SSM3K15FV
2
S
1/20W
MF
201
100K
5%
Fan
SYNC_MASTER=M70

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
46
71
SUDDEN MOTION SENSOR
=PP3V3_S3_SMS
14
R59211
10K
5%
1/20W
MF
201 2
C5922
0.1UF
10%
6.3V
2 X5R
201
VDD
U5900
C5900
10UF
20%
4V
Desired orientation when
603
placed on board top-side:
2 X5R
AP344ALH
LGA
39
IN
1 FS
5 PD
2 ST
SMS_PWRDN
SMS_SELFTEST
VOUTX 12
SMS_X_AXIS
OUT
39
VOUTY 10
SMS_Y_AXIS
OUT
39
SMS_Z_AXIS
OUT
39
CRITICAL
VOUTZ 8
R5922
10K
NC
NC
NC
3 NC
6 NC
9 NC
+X
Front of system
+Z (up)
NC 11 NC
NC 13 NC
NC 16 NC
GND
C5923
0.01UF
10%
10V
2 X5R
201
5%
1/20W
MF
201
2
NC
15 RES
4 RES
+Y
C5924
0.01UF
10%
10V
2 X5R
201
C5925
0.01UF
10%
10V
2 X5R
Circle indicates pin 1 location when placed

in correct orientation
201
Sudden Motion Sensor (SMS)
SYNC_MASTER=M76_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
47
71
41 7
=PP3V3_S5_ROM
R61001
3.3K
5%
1/20W
MF
201 2
R6101
3.3K
C6100 1
5%
1/20W
MF
2 201
0.1UF
10%
6.3V 2
X5R
201
R6152
68 41
IN
SPI_MOSI_MUX
68 41
IN
SPI_CLK_MUX
5%
1/20W
MF
201
68
IN
SPI_MLB_CS_L
8
VCC
R6105
CRITICAL
5 D
R6150
1
68 41
SPI_MOSI
5%
1/20W
MF
201
68
SPI_CLK
6 C
U6100
Q2
SPI_MISO_R
SPI_MISO_MUX
OUT
41 68
5%
1/16W
MF-LF
402
M25P32
VFQFPN
1 S*
68
OMIT
SPI_WP_L
3 W*/VPP
SPI_HOLD_L
7 HOLD*
VSS
4
THM
PAD
9
SPI ROM

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
48
71
DC-JACK INTERFACE
CRITICAL
D6901
47
70 6
J6980
WTB-PWR-M82
PP18V5_DCIN
VOLTAGE=18.5V
M-RT-SM
58 49
2 X7R
BATT_POS_F1
R6940
5%
1/8W
MF-LF
805
10
1206-1
D6900
SC-75
518S0507
NO STUFF
R6902
2
58 40 39
SMC_BC_ACOK1
R6904
CRITICAL
C6907
0.001UF
10%
ADAPTER_SENSE
5 G
50V
2 CERM
402
=PPDCIN_G3H
PPVBATT_G3H_R
VOLTAGE=18.5V
=PP18V5_G3H_CHGR
7 58
5%
2 1/16W
MF-LF
5%
1/16W
MF-LF
402
SMC_BC_ACOK_ONEWIRE_R
47K
SSM6N15FEAPE
R6911
D 3 100K
SOT563
RCLAMP2402B
6
Q6910
5%
1/16W
MF-LF
402
ONEWIRE_PWR_EN_L1
1K
6AMP-24V
F6900
PPDCIN_G3H_R
CRITICAL
402
SOT-363
=PPVIN_G3H_DCIN
C6902
10%
25V
5%
1/8W
MF-LF
805
2
VOLTAGE=18.5V
0.01UF
HN2S02FUAPE
R6905
CRITICAL
402
SOT-723-HF
SSM3J15FVAPZE
ONEWIRE_PWR_EN_L_DIV
Q6940
S 4
D
3
SSM6N15FEAPE
SOT563
70
G 5
Q6920
1
SYS_ONEWIRE_BILAT
3 D
SYS_ONEWIRE6
4 S
40 39
Q6920
SSM6N15FEAPE
SOT563
OneWire OVP
R6932
1
R6903
200K
5%
1/16W
MF-LF
2 402
ONEWIRE_OV
1
100K
10%
2 25V
X5R
402
2 S
10%
2 50V
CERM
402
R6906
R6933
BATTERY INTERFACE
100K
5%
1/20W
MF
201
ONEWIRE_DCIN_DIV
V+
4
1
ONEWIRE_ESD
V-
CRITICAL
R6931
100K
J6900
5%
1/20W
MF
2 201
U6990 2
LM397
5%
1/16W
MF-LF
2 402
G 1
CRITICAL
200K
C6903
0.001UF
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
C6930
0.1UF
SSM3K15FV 3 D
SOD-VESM-HF
R6901
24.3K
1%
1/16W
MF-LF
2 402
Q6980
R6900
24.3K
ONEWIRE_EN
PP18V5_DCIN_ONEWIRE
VOLTAGE=18.5V
SOT23-5-HF
CRITICAL
L6900
WTB-PWR-M82
FERR-50-OHM
M-RT-SM
1
BATT_POS
C6900
BATT_POS_F
49 58
SM-LF
0.01UF
10%
1 25V
X7R
402
6
7
8
9
SMC_BS_ALRT_L
=SMBUS_BATT_SDA
=SMBUS_BATT_SCL
6 39 40
42
42
518S0540
3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator
=PPVIN_G3H_P3V42G3H
P3V42G3H_BOOST
100K
C6991
NC
0.22UF
2
GND
5
10%
6.3V
CERM-X5R
402
7 NC
CRITICAL
10%
SW 4
70
PP3V42G3H_SW
VOLTAGE=3.42V
200mA max output
S 1
C6995
22PF
2 50V
CERM
LSOC_PRESS_H
P3V42G3H_SHDN_L1
D 3
C6999
22UF
20%
6.3V
2 CERM
DC-In & Battery Connectors
805
200K
20%
25V
POLY-TANT
CASE-B2-SM
1
2
<Rb>
R69961
5.6UF
SOT563
1%
1/20W
MF
201
P3V42G3H_FB
C6990
SSM6N15FEAPE
348K
201
CRITICAL
Q6990
(Switcher limit)
<Ra>
R69951
5%
40 38
Vout = 3.425V
CDPH4D19FHF-SM
(PP3V42_G3H_REG)
FB 1
THRM
PAD
7 24
33UH
402
BIAS 2
=PP3V42_G3H_REG
L6995
2 6.3V
CERM-X5R
8 SHDN*
C6994
0.22UF
U6900
DFN
P3V42G3H_SHDN_L
D 6
VIN
BOOST
CRITICAL
5%
1/20W
MF
201 2
Q6990 will pull down

P3V42G3H_SHDN_L in the event
Q6990
of a keyboard SMC Reset
generated when left shift,option,and controlSSM6N15FEAPE
SOT563
and the power button is depressed.
R69901
LTC3470A
SYNC_MASTER=M70
1%
1/20W
MF
201 2
S 4

Vout = 1.25V * (1 + Ra / Rb)

40 38
SMC_ONOFF_H

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
49
71
OMIT
VOLTAGE=5V
70
OMIT
R7101
1UF
R7102
5%
1/16W
MF-LF
402
PM_DPRSLPVR
IN
IMVP6 CPU VCORE REGULATOR

D
70
PPVIN_S5_IMVP6_VIN
C7102
VOLTAGE=18.5V
0.22UF
65 20
10%
6.3V
CERM
402
=PPVIN_S5_CPU_IMVP
PP5V_S0_IMVP6_VDD
5%
1/16W
MF-LF
402
VOLTAGE=5V
C7101
0
5%
1/16W
MF-LF
402
50 7
1UF
10%
6.3V
CERM
402
C7100
R7100
=PP5V_S0_CPU_IMVP
2 50 IMVP6_PVCC
10%
16V
X7R
603
VOLTAGE=3.3V
7
=PP3V3_S0_IMVP
PP3V3_S0_IMVP6_3V3
70
OMIT
R7103
C7103
1UF
50 7
PLACE R7110 WITH NO STUB

ON PM_DPRSLPVR
R7111
R7110
65 11 10
CPU_VID<6>
65 11 10
CPU_VID<5>
65 11 10
CPU_VID<4>
65 11 10
CPU_VID<3>
65 11 10
CPU_VID<2>
499
499
1%
1/20W
1%
1/20W
65 11 10
CPU_VID<1>
MF
MF
65 11 10
CPU_VID<0>
2 201
2 201
65 13 9 8
65
IN
CPU_DPRSTP_L
IMVP_DPRSLPVR
27
GND_IMVP6_SGND
50
VIN
VDD
VCCP
VID6
VID5
VID4
VID3
VID2
VID1
VID0
37
36
1
DPRSTP*
39
NC 38
24
R7116
C7111
147K
0.015uF
35
IN
40
OUT VR_PWRGOOD_DELAY
IMVP6_VR_TT
4
NC 5
IMVP_VR_ON
39 FROM SMC
1%
1/20W
MF
201
10%
16V
X7R
402
R7104
LGATE 50 26
SOFT
50
IMVP6_RBIAS
RBIAS
180PF
R7124
5%
50V
CERM
402
1K
R7120
1%
1/20W
MF
201
IMVP6_PHASE
1
IMVP6_CPU_ISENSE
VSUM 50 17
OCSET 7 50
VO 50 16
DROOP 50 14
NC
TPAD
65
(IMVP6_VO)
R7140
C7130
1000PF
65
1%
1/20W
MF
201
1/20W
MF
201
1%
X7R
201
C7140
330PF
10%
R7142
16V
20K
X7R
201
2
1
1
C7142
0.12UF
0.01UF
10%
10.0V
CERM-X5R
402
10%
10V
X5R
201
C7143
R7145
1%
1/20W
MF
201
C7121
C7132
50
C7122
C7123
56PF
1000PF
5%
25V
NP0-C0G
201
10%
16V
X7R
201
R7123
R7134
100 2
1
6.04K
1%
1/20W
MF
201
1%
1/20W
MF
201
10%
50V
X7R-CERM
402
OMIT
0603-LF
2
ERT-J1VR103J
(IMVP6_VO)
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
R7131
R7132
0.1UF
10KOHM-5%
5%
1/20W
MF
201
5%
1/20W
MF
2 201
CPU_VCCSENSE_P
10 65
CPU_VCCSENSE_N
10 65
MIN_LINE_WIDTH
50
50
50
50
50
50
50
MIN_LINE_WIDTH
50
CRITICAL
(IMVP6_VSUM)
C7133
50
MIN_NECK_WIDTH
1.5 MM
0.20 MM
50
0.25 MM
0.20 MM
50
1.5 MM
0.20 MM
50
1.5 MM
IMVP6_VO_R
330PF
10%
6.3V
X5R
201
1%
1/16W
MF-LF
402
10%
16V
X7R
201
R7144
50
50
1%
1/20W
MF
201
4.53K
1%
1/20W
MF
2 201
(IMVP6_VW)
NOTE 1: C7132,C7133 = 27.4 OHM FOR VALIDATING CPU ONLY.
IMVP6_PHASE
IMVP6_BOOT
IMVP6_UGATE
IMVP6_LGATE
R7146
7.68K
R7143
3.57K
1000PF
SM
50
1%
1/20W
MF
201
(IMVP6_VO)
C7131
VOLTAGE=0 V
1 2 3
16V
8.66K
806
10%
16V
X7R
201
LFPAK-HF
10%
RJK0328DPB
1000PF
IMVP6_DFB
Q7151
C7141
10%
16V
X7R
201
GND_IMVP6_SGND
XW7100
50
NO STUFF
270PF
2
CRITICAL
IMVP6_DROOP
374K
IMVP6_VO
12
13
VSEN
RTN
R7121
IMVP6_FB_RC
50
0.20 MM
50
50
50
IMVP6_OCSET
IMVP6_VSUM
GND_IMVP6_SGND
IMVP6_VO
IMVP6_DROOP
IMVP6_DFB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB
IMVP6_COMP
IMVP6_VW
IMVP6_PVCC
IMVP6_COMP_R
IMVP6_FB_RC
IMVP6_VDIFF_RC
MIN_NECK_WIDTH
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.50 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
0.25 MM
0.20 MM
IMVP6 CPU VCore Regulator

SYNC_MASTER=POWER

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7631
SCALE
SHT
NONE
C
7
PWM FREQ. = 300kHz

MAX CURRENT = 30A
0.22UF
20%
6.3V
X5R
201
100
1%
1/20W
MF
201
39
IMVP6_OCSET
R7130
R7141
0.01UF
(IMVP6_FB)
0.36UH-30A-1.05M-OHM
=PPVCORE_S0_CPU_REG
C7190
IMVP6_VSUM
1
1
SMC_CPU_ISENSE
R7190
FB
COMP
VW
4.53K
VSS
50
CRITICAL
L7100
1%
1/20W
MF
201
C7124
10%
10V
X5R
201
LFPAK-HF
(IMVP6_PHASE)
R7122
15K
1%
1/20W
MF
201
2 3
PCMB103T
PMON
2.21K
50 IMVP6_COMP_R 1
50
IMVP6_UGATE
VDIFF
1%
1/20W
MF
201
IMVP6_VDIFF_RC
1
21
CRITICAL
IMVP6_VSEN_P
IMVP6_VW
C7153
1UF
10%
25V
X5R
603-1
RJK0305DPB
IMVP6_VSEN_N
IMVP6_COMP
50
Q7100
PHASE 50 24
19
50
20%
2 10V
2
POLY-TANT
CASE-B2-SM
C7152
1UF
10%
25V
X5R
603-1
0.22UF
10%
16V
X7R
603
41
C7120
10
9
8
47UF
C7104
IMVP6_LGATE
IMVP6_FB
C7151
25
(GND)
DFB 50 15
50
IMVP6_BOOT_RC
2.2
5%
1/16W
MF-LF
402
VSSP
3V3
CLK_EN*
VR_ON
PGOOD
VR_TT*
NTC
11
FDE
IMVP6_SOFT
IMVP6_VDIFF
DPRSLPVR
50
50
IMVP6_BOOT
QFN
20%
2 10V
POLY-TANT
CASE-B2-SM
UGATE 50 23
5%
1/20W
MF
201
C7150
=PPVIN_S5_CPU_IMVP
CRITICAL
47UF
BOOT 50 22
U7100
R7115
CPU_PROCHOT_L
CRITICAL
34
33
32
31
30
29
28
NO STUFF
65
40
13
9
CRITICAL
20
ISL6261A
5%
1/20W
MF
201
10%
6.3V
X5R
402-1
18
2.3.0
OF
50
71
MCP CORE POWER SUPPLY

R7260
2.2
=PP5V_S3_MCPREG
OMIT
C7297
1UF
20
20
MCP_VID<0>
IN
20
IN
MCP_VID<1>
20
IN
MCP_VID<2>
R7292
1
1 RBIAS
5%
1/20W
MF
201
44
OUT MCPCORE_IOUT
56
OUT
CONNET OFFSET0 TO 3V3 FOR +12.5MV

CONNET OFFSET1 TO 3V3 FOR +25.0MV
56
R7293
0
5%
1/20W
MF
2 201
R7294
5%
1/20W
MF
2 201
=PPMCPCORE_S0_REG
31
25
26
27
MCPCORES0_PGOOD
MCP_VID0_R
MCP_VID1_R
MCP_VID2_R
MCPCORES0_OFFSET0
MCPCORES0_OFFSET1
=MCPCORES0_EN
IN
MCPCORES0_FDE
23
24
29
30
32
8
9
22
PGOOD
VID0
VID1
VID2
OFFSET0
OFFSET1
VR_ON
AF_EN
FDE
VSEN
RTN
OMIT
20
C7270
MCPCORES0_COMP
6 FB
MCPCORES0_VDIFF
7 VDIFF
R7271
C7276 1
C7266 1
L7200
10UF
20%
4V
X5R 2
603
0.68UH-3.9MOHM
2
1
IHLP4040CZ-SM
(=PPMCPCORE_S0_REG)
2 OMIT
20%
2 2.5V
POLY-TANT
CASE-C2-SM
OMIT
OMIT
C7267 1
C7265
10UF
330UF
20%
4V
X5R 2
603
20%
2 2.5V
POLY-TANT
CASE-C2-SM
C7269 1
10UF
20%
4V
X5R 2
603
OMIT
XW7202
XW7260
SM
Q7265
(MCPCORES0_LGATE) 4
SM
1
RJK0328DPB
LFPAK-HF
GATE_NODE=TRUE
MCPCORES0_ISP_R
R72641
R7265
1%
1/20W
MF
201 2
MCPCORES0_OCSET
0603-LF
1
ISP 13 MCPCORES0_ISP
ISN 11 MCPCORES0_ISN
VSS
R7269
THRM_PAD
R7270
MCPCORES0_ISN_R
10KOHM-5%
R7267
10K
1K
1%
1/20W
MF
2 201
10%
2 16V
X7R
402
1%
1/20W
MF
2 201
1%
1/20W
MF
2 201
C7273
0.047UF
4.99K
150K
1%
1/20W
MF
2 201
(MCPCORES0_VO)
1
R7273
10K
XW7261
SM
51
CRITICAL
11.3K
R7272
10%
2 16V
X7R
201
1%
1/20W
MF
2 201
CRITICAL
OMIT
CRITICAL
CRITICAL
LGATE 21 MCPCORES0_LGATE
10%
16V 2
X7R
402
C7299
1000PF
100
C7268
330UF
C7264
0.22UF
ICOMP 10 MCPCORES0_ICOMP
PGND
10%
16V 2
X7R
201
0.015UF
1%
1/20W
MF
201
LFPAK-HF
OCSET 3
MCPCORES0_FB
1000PF
10%
2 16V
X7R
201
CRITICAL
RJK0305DPB
2
2 MCPCORES0_BOOT_R 1
1 2 3
0.25 MM
0.2 MM
CERM-X7R
10V
603
5%
MCPCORES0_PHASE
(MCPCORES0_PHASE)
SWITCHNODE
5 COMP
C7298 1
1000PF
R7268
MCPCORES0_RSEN_L 1
51
1%
1/20W
MF
201
Q7260
5%
1/10W
BOOT 17 MCPCORES0_BOOT
0.2 MM MF-LF
0.25 MM 603
PHASE 19
33
XW7263
20
F = 300 KHZ
CRITICAL
4
R7274
UGATE 18 MCPCORES0_UGATE
15
PLACE XW NEAR THE MCP, OMIT

CONNECT SENSE LINES TO CLOSEST
MCPCORE AND GND BALL
OF MCP
SM
1
2
MAX CURRENT: 20A
10%
2 25V
X5R
603-1
1 2 3
1%
1/20W
MF
2 201
R7266
MCPCORES0_RSEN_H
1UF
47UF
20%
10V
POLY-TANT 2
CASE-B2-SM
D
7 51
SWITCH_NODE=TRUE
20
C7261
4 VW
MCPCORES0_VW
GND_MCPCORES0_AGND
100
VO 12 MCPCORES0_VO
R7263
XW7262
SM
1UF
C7260
GATE_NODE=TRUE
=PPMCPCORE_S0_REG 1
20%
10V
POLY-TANT 2
CASE-B2-SM
C7272
(MCPCORES0_UGATE)
VIN 14
QFN
28 IMON
MCPCORES0_VSEN
MCPCORES0_RTN
U7200
2 SOFT
MCPCORES0_SOFT
5%
1/20W
MF
201
51 7
VDD
PVCC
CRITICAL
MCPCORES0_RBIAS
R7291
0.1UF
GND_MCPCORES0_AGND
1%
1/20W
MF
2 201
5%
1/20W
MF
201
51
C7255
10%
10%
2 25V
2 25V
X5R
X5R
603-1
402
PLACE AT U7200.14
10%
2 16V
X5R
402
16
10%
16V 2
X5R
402
R7261
47UF
=PPMCPCORE_S0_REG
Vout = See below
CRITICAL
1
C7262
C7296
R7290
CRITICAL
1UF
=PP3V3_S3_MCPREG
=PPVIN_S0_MCPCORES0
5V_S3_MCPREG_VIN
VOLTAGE=5V
OMIT
0.6 mm
0.2 MM
1
ISL6263D
5%
1/10W
MF-LF
603
GND_MCPCORES0_AGND
VOLTAGE=0V
OMIT
(MCPCORES0_ISP)
(MCPCORES0_ISN)
1%
1/20W
MF
2 201
C7277
0.1UF
C7278
0.1UF
10%
2 6.3V
X5R
201
10%
2 6.3V
X5R
201
R7275
10K
1%
1/20W
MF
2 201
(MCPCORES0_ICOMP)
C7279 1
C7280
1000PF
10%
25V 2
X7R
402
68PF
R7276
6.98K
5%
25V
CERM
201
R7277
1
1%
1/20W
MF
2 201
C7281
374K 2 MCPCORES0_COMP_C180PF
1
2
1%
1/20W
MF
201
5%
50V
CERM
402
NEED NEW TABLE?
4.99K2 MCPCORES0_VDIF_C 560PF

1
2
Rev A01P Production

Voltage
Voltage
000
+1.224V
+1.355V
+1.060V
001
+1.158V
+1.243V
+0.994V
010
+1.101V
+1.216V
+0.937V
011
+1.047V
+1.124V
+0.885V
100
+0.996V
+1.065V
+0.830V
101
+0.952V
+0.994V
+0.789V
110
+0.913V
+0.977V
+0.752V
111
+0.876V
+0.917V
+0.719V
VID<2:0>
1%
1/20W
MF
201
Rev A01
Voltage
C7282
R7278
R7279
10%
50V
CERM
402
2.21K2
1
1%
1/20W
MF
201
MCP CORE REGULATOR

SYNC_MASTER=MINGJING

(Also A01Q)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
51
71
1.8V S0
LDO
U7360
7
=PPVIN_S0_P1V8S0
TPS79918
6 IN
SON
=PP1V8_S0_REG
OUT 1
CRITICAL
OMIT
1
56
=P1V8S0_EN
C7360
4 EN
5 NC
1UF
GND
10%
2 6.3V
CERM
402
THRML
PAD
7
MAX CURRENT = 200MA
NR 2 P1V8S0_NR
1
OMIT
1
C7361
C7362
2.2UF
0.01UF
20%
2 6.3V
CERM
402-LF
10%
2 10V
X5R
201
1.8V LDO Supply

SYNC_MASTER=
SYNC_DATE=

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
52
71
1V05 S5 POWER SUPPLY
supply for MCP1V05 AUX, FSB (CPU & MCP) VTT, 1V05 S0
53 7
=PPVIN_S5_1V05
(1V05S5_VLDO)
VOLTAGE=5V
C7451
1UF
10%
25V
X5R 2
603-1
CRITICAL
CRITICAL
R7440
130K
1%
1/20W
MF
201 2
SC417
MLPQ
TON
VOUT
1V05S5_VLDO7
VLDO
VIN0
VIN1
VIN2
VIN3
VIN4
BST
DH
R7490
1V05S5_FBL 2
1V05S5_EN 29
63.4K
C7492
1%
1/20W
MF
201
26
EN/PSV
PGOOD
OMIT
FBL
R7491
C7430
=PP1V05_S5_REG 7
CRITICAL
1V05S5_ILIM
R7420
1/20W
MF
201
1
XW7400
R7412
PGND
XW7402
SM
10K
1%
1/20W
MF
201
2
1V05S5_FB_C
PP1V05_S5_REG_XW
C7411
C7402
0.01UF
10%
2 10V
X5R
201
C7410
R7410
12.1K
MAX CURRENT = 12A
R7411
11.5K
1%
1/20W
MF
201
2
C7412
10%
16V
2 X7R
201
20%
4V
CERM-X5R 2
201
20%
2 4V
X5R
603
0.01UF
330PF
0.47UF
10UF
1%
1/20W
MF
2 201
10%
2 10V
X5R
201
2
1
C7401
5%
2 50V
CERM
402
1V05S5_ENL
OMIT
1
180PF
XW7401
1V05S5_LL_XW
20%
2 2.5V
POLY-TANT
CASE-C2-SM
NO STUFF
1
14 NC
32
C7400
330UF
12.1K
1%
1
SM-IHLP
27
15
16
17
18
19
20
21
22
4
30
34
1V05S5_VBST 1
0.22UF
10%
10V
CERM
402
2
1
2
1V05S5_VBST_R
12 NC
ILIM
ENL
AGND
1V05S5_LL
DL
C7420
R7421
5%
1/16W
MF-LF
402
LX0
LX1
LX2
LX3
LX4
LX5
11K
1%
1/20W
MF
201
1.0UH-22A-10M-OHM
13
23
24
25
28
33
10%
10V 2
X5R
402
1UF
L7400
6
9
10
11
35
1V05S5_TON 31
U7400
FB
SM
SM
20%
10V
POLY-TANT
CASE-B2-SM
47UF
V5V
C7450
CRITICAL
PWM FREQ = 400KHZ
1V05S5_FB
GND_1V05S5_SGND
R7432
1K
5%
1/20W
MF
201
R7430
1
2
0
5%
1/20W
MF
201
5V LDO ENABLE EITHER FROM S5 CONTROL OR PBUS POWER
NO STUFF
53 7
=PPVIN_S5_1V05
R7431
1
2
100K
5%
1/20W
MF
201
1V05 S5 Power Supply
SYNC_MASTER=RXU_K20
56
IN
56
OUT
=P1V05_S5_EN
P1V05_S5_PGOOD

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
53
71
1.5V/0.75V POWER SUPPLY

State
Vout = 0.75V * (1 + Ra / Rb)

NO
<Rb>
1
R7522
<Ra>
1%
1/20W
MF
201
20K
1%
20K
PP0V75_S0
S0
HIGH
HIGH
1.5V
0.75V
S3
HIGH
LOW
1.5V
0.0V
S5/G3Hot
LOW
LOW
0.0V
0.0V
C7503
100PF
R7521
1/20W
MF
201
PM_SLP_S3_L PP1V5_S3
STUFF
1V5S3_VDDQSET
PM_S4_STATE_L
5%
25V
CERM
201
MEMVTT_VREF
C7540
0.033UF
10%
16V
X5R
402
1
OMIT
2
1V5S3_V5FILT
C7502
PLACE XW7502 NEAR L7520
10UF
1/16W
MF-LF
402
10%
10V
X5R
402-1
=PP0V75_S3_VTTREF
OMIT
1
4.7
5%
1UF
=PP5V_S3_1V5S30V75S0
R7507
C7500
XW7502
SM
20%
6.3V
X5R
603
1V5S3_VDDQSNS
=PP0V75_S0_REG
15
22
14
24
23
1%
1/20W
MF
2 201
VDDQSET VTTREF VLDOIN VTT V5FILT
C7511
2.2UF
9.76K
20%
2 6.3V
CERM
402-LF
VBST V5IN VDDQSNS VTTSNS
C7509
10%
16V
X5R
402
CONNECT VTTSNS TO C7507 PIN1

using separate trace.
56
=DDRVTT_EN
=DDRREG_EN
10
11
S3
S5
PGOOD
13
DRVH
LL
21
20
CRITICAL
U7500
SYM (1 OF 2)
6
16
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
CS
Routing Note:
DRVL
19
MODE
NC0
NC1
Connect CS_GND to
Q7521 PIN1,2.3
using Kelvin connection.
7
12
1V5S3_DRVL
(inductor limited)
1.0UH-22A-10M-OHM
1
VOLTAGE=1.8V
22UF
CRITICAL
CRITICAL
CRITICAL
SI7108DN
PWRPK-1212-8-HF
OMIT
1
C7542
C7541
20%
2.5V
POLY-TANT
CASE-C2-SM1
C7543
330UF
10UF
330UF
Q7521
VTTGND
=PP1V5_S3_REG
SM-IHLP
20%
2 6.3V
X5R
603
20%
2.5V
POLY-TANT
CASE-C2-SM1
1 2 3
Placement Note:
C7508
20%
2 6.3V
X5R-CERM
603
PGND
18
GND
3
22UF
17
C7507
20%
2 6.3V
X5R-CERM
603
PLACE C7507,C7508 GND NEAR PIN 1
25
Placement Note:
CS_GND
L7520
1 2 3
THRM_PAD
PWM FREQ. = 400 kHz

MAX CURRENT = 11A
CRITICAL
mm
mm
mm
mm
1UF
PWRPK-1212-8-HF
(1V5S3_VDDQSNS)
NC
NC
C7531
10%
2 25V
X5R
603-1
20%
2 10V
POLY-TANT
CASE-B2-SM
SI7110DN
TPS51116
COMP
QFN
1V5S3_CS
Q7520
C7532
47UF
20%
2 10V
POLY-TANT
CASE-B2-SM
CRITICAL
1V5S3_DRVH
1V5S3_LL
C7530
47UF
1
2
=PPVIN_S5_1V5S30V75S0
CRITICAL
CRITICAL
1
0.1uF
Routing Note:
57 24
1V5S3_VBST_RC
5%
1/16W
MF-LF
OMIT 402
R7510
R7500
1
2
1V5S3_VBST
PLACE C7543 NEAR NB

(GND)
GND_1V5S3_SGND
Routing Note:
put 6 vias under the thermal pad
Placement Note:
DDRREG_PGOOD
XW7500
SM
R7599
GND_1V5S3_CSGND
1.5V/0.75V Supplies
100K
PLACE XW7500, NEAR C7542 PIN 2
56
2
1
1%
1/20W
MF
201
SYNC_MASTER=M70
2
=PP3V3_S3_DDRREG
XW7501
SM

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
54
71
5V_S3 / 3V3_S5 POWER SUPPLY

D
D
55 7
=PP5V_S3_REG
2
XW7608
SM
PLACEMENT_NOTE=PLACE XW7608 NEXT TO C7691.
P5VP3V3_V5SW
=PPVIN_S3_5VS3
=PPVIN_S5_3V3S5
P5VP3V3_VREG5
CRITICAL
C7681
3.3UH
20%
6.3V 2
POLY-TANT
CASE-B2-SM
SI7904BDN
PWRPK-1212-8
XW7602
SM
20%
6.3V 2
X5R
603
P5VS3_DRVL
Q7660
10UF
XW7607
SM
PLACEMENT_NOTE=PLACE XW7602 AND XW7607 NEXT TO L7660.
1
10%
16V
X5R
402
55
G 4
XW7603
SM
1.24K2
R76561
4.87K
R76201
22
29
23
13
VREF2
P3V3S5_LL
SWITCH_NODE=TRUE
P3V3S5_DRVL
DRVL2 27
1%
1/20W
MF
201
RF 3
VFB2 16
COMP2 15
1%
1/20W
MF
201 2
XW7601
SM
R7699
5%
1/20W
MF
2 201 PLACEMENT_NOTE=Place
40.2K
1%
1/20W
MF
201 2
Q7620
10%
16V 2
X5R
402
mm
mm
mm
mm
mm
mm
mm
mm
CRITICAL
L7620
3.3UH
R7637
6.04K
1%
1/20W
MF
2 201
(Q7620 limit)
2
IHLP
CRITICAL
Q7620
OMIT
XW7605
SM
SI7904BDN
PWRPK-1212-8
G
S
CRITICAL
C7652
150UF
20%
2 6.3V
X5R
603
20%
2 6.3V
POLY-TANT
CASE-B2-SM
C7651
150UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
XW7606
SM
1
XW7604
SM
1.24K2
1
1%
1/20W
MF
2 201
R7646
1%
1/20W
MF
201
CRITICAL
C7650
10UF
1
4
4A MAX OUTPUT
PLACEMENT_NOTE=PLACE XW7605 AND XW7606 NEXT TO L7620 .
Vout = 3.3V
10%
25V
X5R
402
332K
F=300KHZ
C7688
R7606
5%
1/20W
MF
201 2
PWRPK-1212-8
0.1UF
R76981
SI7904BDN
D
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
P3V3S5_VFB2
P3V3S5_COMP2
THRM_PAD
P5VS3_CSP1-R
P3V3S5_RF
EN2 21
PGOOD2 20 P5VS3_PGOOD2
GND
6.04K
P3V3S5_CSP2
P3V3S5_CSN2
CSP2 18
CSN2 17
FUNC
VFB1
COMP1
R76361
1%
1/20W
MF
201 2
P5VS3_VFB1-R
GATE_NODE=TRUE
SW2 25
4 EN1
P5VS3_PGOOD1 5 PGOOD1
R7647
PLACEMENT_NOTE=PLACE XW7603 NEXT TO L7660
P3V3S5_DRVH
DRVH2 24
7 CSP1
8 CSN1
P5VP3V3_VREG3 11
P5VS3_VFB1 9
P5VS3_COMP1 10
CRITICAL
0.1UF
=PP3V3_S5_REG
GATE_NODE=TRUE
0.1UF
C7664 1
20%
2 6.3V
X5R
603
P3V3S5_VBST
VBST2 26
30 DRVL1
P5VS3_CSP1
P5VS3_CSN1
C7618
10UF
GATE_NODE=TRUE
C7690 1
28
20%
6.3V 2
POLY-TANT
CASE-B2-SM
CRITICAL
OMIT
150UF
32 SW1
10%
6.3V 2
CERM
402
C7605
10%
2 10V
CERM
402
EN 12
LLP
SWITCH_NODE=TRUE
CRITICAL
U7600
1 DRVH1
P5VS3_LL
IHLP
C7692 1 C7691 1
150UF
C7601
0.22UF
CRITICAL
31 VBST1
P5VS3_DRVH
GATE_NODE=TRUE
L7660
1
NO STUFF
CRITICAL
P5VS3_VBST
CRITICAL
(Q7660 limit)
1UF
G 2
Vout = 5.0V
4A MAX OUTPUT
10%
25V
2 X5R
603-1
=PP5V_S3_REG
1UF
C7641
20%
10V 2
POLY-TANT
CASE-B2-SM
OMIT
OMIT
C7603 1
33
55 7
6 SKIPSEL1
19 SKIPSEL2
14 TRIP
VREG3
10%
16V 2
X5R
402
VREG5
0.1UF
F=300KHZ
C7624 1
6
PWRPK-1212-8
TPS51220
Q7660
SI7904BDN
V5SW
CRITICAL
VIN
10%
25V 2
X5R
603-1
55
P5VP3V3_VREF2
1UF
C7600 1
10%
2 25V
X5R
603-1
20%
10V 2
POLY-TANT
CASE-B2-SM
C7640 1
47UF
1UF
47UF
CRITICAL
P5VP3V3_VREG3
55
C7680 1
R7616
PLACEMENT_NOTE=PLACE XW7604 NEXT TO L7620
4.87K
1%
1/20W
MF
2 201
P3V3S5_VFB2-R
1
R7660
P3V3S5_CSP2-R
XW7601 between U7600 pins 28 and 33.
23.2K
1%
1/20W
MF
2 201
R7661
R76211
10K
10K
1%
1/20W
MF
201 2
55
P5VP3V3_VREF2
P5VP3V3_VREF2
1%
1/20W
MF
2 201
55
GND_P5VP3V3_SGND
VOLTAGE=0V
One master PGOOD for both 5V and 3V3

56
OUT
P5V3V3_PGOOD
56
IN
=P5VS3_EN
56
IN
=P3V3S5_EN
5V / 3.3V Power Supply
SYNC_MASTER=RXU_K20

.
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
55
71
S5 ENABLE
Power Control Signals
R7702
2
10K
P3V3S5_EN
=P3V3S5_EN
OUT
55
MAKE_BASE=TRUE
5%
1/20W
MF
201
NO STUFF
C7702
0.068UF
10%
10V
CERM
402
39
SMC_PM_G2_EN
IN
S0 ENABLE
1
R7700
100K
R7701
5.1K
C7758
56 7 =PP3V3_S5_PWRCTL
0.1UF
1 PM_G2_P1V05S5_EN
=P1V05_S5_EN
MAKE_BASE=TRUE
5%
1/20W
MF
201
OUT
53
0.47UF
2
1
10%
6.3V
X5R
201
C7701
20%
4V
CERM-X5R
201
5
2
TC7SZ08AFEAPE
SOT665
U7759
39 35 34 20 6
IN
(PM_SLP_S3_L)
PM_SLP_S3_L
4 (PM_SLP_S3_L_BUF)
PM_SLP_S3_L_BUF
R7785
S3 ENABLE
R7779
R7780
22K
R7782
5%
1/20W
MF
201
5%
1/20W
MF
201
22K
R7783
5.1K
R7784
5%
1/20W
MF
201
5%
1/20W
MF
201
=P5VS3_EN
OUT
MAKE_BASE=TRUE
5%
1/20W
MF
201
55
P3V3S0_EN
57
P1V05S0_EN
OUT
=P1V8S0_EN
OUT
52
=MCPDDR_EN
OUT
57
=MCPCORES0_EN
OUT
51
=DPPWR_EN
OUT
61
2
MAKE_BASE=TRUE
10%
6.3V
CERM-X5R
402
MCPDDR_EN
MAKE_BASE=TRUE
MCPCORES0_EN
IN
43
0.47UF
5%
1/20W
MF
201
40 39 34 20
57
OUT
MAKE_BASE=TRUE
P1V8S0_EN
OUT
=PBUSVSENS_EN
4.7K
C7712
R7712
1K
=P3V3S0_EN
PM_SLP_S4_L
MAKE_BASE=TRUE
P3V3S3_EN
MAKE_BASE=TRUE
=P3V3S3_EN
OUT
MAKE_BASE=TRUE
57
DPPWR_EN
MAKE_BASE=TRUE
R7710
5%
1/20W
MF
201
1K
0.47UF
NO STUFF
2
1
5%
1/20W
MF
201
10%
6.3V
CERM-X5R
402
C7785
C7782
NO STUFF
1
C7783
C7784
0.47UF
0.47UF
0.47UF
10%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
CERM-X5R
CERM-X5R
402
CERM-X5R
402
CERM-X5R
402
CERM-X5R
402
C7781
0.47UF
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
DDRREG_EN
=DDRREG_EN
OUT
54
=USBPWR_EN
OUT
37
MAKE_BASE=TRUE
C7714
R7714
5.1K
0.47UF
0.47UF
5%
1/20W
MF
201
C7780
C7711
R7711
1
0.47UF
402
5.1K
C7713
R7713
100K
57
5%
1/20W
MF
201
NO STUFF
OUT
R7781
5%
1/20W
MF
201
100K
P5VS3_EN
=P5VS0_EN
MAKE_BASE=TRUE
5%
1/20W
MF
201
0.47UF
5%
1/20W
MF
201
10%
6.3V
CERM-X5R
402
USBPWR_EN
MAKE_BASE=TRUE
56 7 =PP3V3_S5_PWRCTL
C7740
1
1
0.1uF
100K
VDD
5 SENSE
U7740
R7740
10%
6.3V
X5R
201
RESET* 1
5%
1/20W
MF
201
RSMRST_PWRGD
39
P1V05_S5_PGOOD
53
TPS3808G33DBVRG4
CT
SOT23-6
MR* 3
CRITICAL
GND
TPS3808 MR* HAS INTERNAL PULLUP
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
4 CT
C7741
7 =PP3V3_S0_VMON
1000PF
C7770
10%
16V
X7R
201
0.1uF
10%
6.3V
X5R
201
OTHER S0 RAILS PGOOD
24 7
=PP3V3_S0_PWRCTL
VCC
R7720
10K
LTC2909
NC
SEL
8
7
ADJ1
ADJ2
U7770
REF
CRITICAL
DFN
TMR
RST*
TIE TMR TO GND

TRST = 200MS
201
=PP1V05_S0_VMON
GND
S0PGOOD_PWROK
THRM_PAD
IN
MCPCORES0_PGOOD
POWER SEQUENCING
Unused PGOOD signal
R7721
51
TP_DDRREG_PGOOD
DDRREG_PGOOD
SYNC_MASTER=YUAN.MA
54

R7722
LTC2909 THRESHOLD IS 95% (3.136V)
1.5V 1.05V COMPARED TO 0.5V
55
IN
P5V3V3_PGOOD
MAKE_BASE=TRUE
5%
1/20W
MF
201
=PP1V5_S0_VMON
5%
1/20W
MF

5%
1/20W
MF
201
ALL_SYS_PWRGD
OUT
24 39
MAKE_BASE=TRUE
R7723
1
SIZE
DRAWING NUMBER
5%
1/20W
MF
201
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
56
71
1.5V S0 FET
(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
7 =PP1V5_S3_P1V5S0FET
CRITICAL
3.3V S3 FET
Q7810
C7802
FDC638P_G
SM
=PP3V3_S5_P3V3S3FET
=PP3V3_S3_FET
MOSFET
FDC638P
CHANNEL
P-TYPE
C7811
33000PF
10K
RDS(ON)
10%
6.3V
5%
1/20W
10K
201
2
P3V3S3_SS
Q7803
10%
MF
10V
SSM3K15FV
PWRPK-1212-8-HF
Q7871
1 2
=PP1V5_S0_FET
R7871
1
1
C7803
10%
10V
CERM
402
2
5%
1/20W
MF
201
56
56
=MCPDDR_EN
IN
3.3V RMGT FET
FDC606P_G
5 6
5V S0 FET
C7841
MOSFET
FDC606P
CHANNEL
P-TYPE
LOADING
X5R
MF
201
2
=PP3V3_RMGT_FET
2
P5VS0_SS
5%
1/20W
MF
201
10V
201
X5R
C7821
0.033UF
10K
10%
MF
R7820 1
5%
1/20W
Q7845
0.562 A (EDP)
0.01UF
33K
1
SOT-23-HF
26 MOHM @4.5V
C7840
R7840
P5VS0_EN_L
Q7820
NTR4101P
=PP3V3_S5_P3V3RMGTFET
RDS(ON)
CRITICAL
10%
6.3V
5%
1/20W
@ 2.5V Vgs:
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)
33000PF
100K
201
=PP5V_S0_FET
=PP5V_S3_P5VS0FET
5.027A (EDP)
Q7840
SOT-6
R7842
6 MOHM @3.5V VGS
CRITICAL
5V S0 FET
7
N-TYPE
LOADING
S 2
=P3V3S3_EN
IN
SI7108DNS
CHANNEL
RDS(ON)
SOT563
MOSFET
MCPDDR_EN_L_RC
SSM6N15FEAPE
1.5V S0 FET
0.068UF
47K
Q7871
SOT563
MCPDDR_EN_L
SOD-VESM-HF
SSM6N15FEAPE
201
D 3
SI7108DN
X5R
201
Q7801
5%
1/20W
100K
5%
1/20W
MF
201
CRITICAL
MCPDDR_SS
2
5%
1/20W
MF
201
R7803 1
0.315 A (EDP)
0.01UF
47K
1
LOADING
C7810
R7810
P3V3S3_EN_L
48 mOhm @4.5V
X5R
MF
201
10%
6.3V
X5R
201
R7801
=PP5V_S3_MCPDDRFET
1
1
R7812
0.1UF
3.3V S3 FET
R7821
100K
P3V3RMGT_EN_L
10%
16V
X5R
402
C7820
0.01UF
P3V3RMGT_SS
201
SSM3K15FV
D 3
5%
1/20W
MF
201
SOD-VESM-HF
Q7821
10%
16V
CERM
402
SSM6N15FEAPE
SOT563
1
56
S 2
=P5VS0_EN
IN
CRITICAL
Q7830
3.3V S0 FET
5 6
SOT-6
FDC606P
CHANNEL
P-TYPE
RDS(ON)
X5R
2
C7830
P3V3S0_SS
=PP3V3_S5_P1V05RMGTFET
10K
26 MOHM @4.5V
2.046 A (EDP)
R7864
1%
1/20W
MF
201
10V
MF
X5R
201
SI2312BDS
SOT23
Q7861
=PP1V05_RMGT_FET
SSM6N15FEAPE
R7861
P1V05RMGT_EN_L
1
1
1
56
S 2
1.05V S0 FET
=P3V3S0_EN
IN
P1V05S0_SS
5
5%
1/20W
MF
201
NO STUFF
C7852
R7854
0.1UF
=PP3V3_S5_P1V05FET
P1V05S0_RC 1
N-TYPE
Q7853
RDS(ON)
6.1 MOHM @4.5V VGS
SI7108DN
LOADING
8.25A (EDP)
=PPVTT_S0_VTTCLAMP
3
7
=PP1V05_S0_FET
R7851
P1V05_EN_L
1
1
5%
1/20W
MF
201
5%
1/20W
MF
201
IN
90mA max load @ 0.9V

81mW max power
C7853
10%
10V
CERM
402
SSM6N15FEAPE
SOT563
POWER FETS
SYNC_MASTER=YUAN.MA
VTTCLAMP_EN
Q7875
NO STUFF
C7876
SSM6N15FEAPE
4
5
54 24
IN

1000PF
10%
16V
X7R
201
P1V05S0_EN

2

=DDRVTT_EN
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
REV.
051-7631
SHT
NONE
SOT563
56
PM_SLP_RMGT_L
CKT FROM T18
R7876 1
SOT563
VTTCLAMP_L
Q7875
P1V05_EN_L_RC
SSM6N15FEAPE
=PP5V_S3_VTTCLAMP
0.068UF
100K 2
10
100K
IN
5%
1/10W
MF-LF
603
SOT563
57 20
R7875
PWRPK-1212-8-HF
SSM6N15FEAPE
10K
SI7108DN
CHANNEL
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
WILL EXIT SELF-REFRESH PREMATURELY.
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
LOW THROUGH VTT TERMINATION RESISTORS.
Q7851
R7853 1
Q7851
5%
1/20W
MF
201
10%
6.3V
X5R
201
5%
1/20W
MF
201
510
MOSFET
CRITICAL
NO STUFF
P1V05RMGT_EN_L_RC
SOT563
=PP1V05_S5_P1V05S0FET
1.05V S0 FET
220K 2
10%
10V
CERM
402
SSM6N15FEAPE
R7852
=PP5V_S3_P1V05S0FET
Q7861
1%
1/20W
MF
201
C7861
0.068UF
15K
1
MCP79 DDRVTT FET
SOT563
201
D 3
@ 1.8V Vgs:
Rds(on) = 47mOhm max
I(max) = 3.1A (70C)
CRITICAL
Q7860
1
1%
1/20W
MF
201
SOD-VESM-HF
P1V05RMGT_SS
69.8K
10%
1/20W
Q7805
20%
10V
CERM
402
R7860
5%
SSM3K15FV
0.1UF
0.01UF
47K
P3V3S0_EN_L
LOADING
201
R7830
10%
6.3V
MF
C7860
33000PF
1/20W
=PP1V05_RMGT_P1V05RMGTFET
MOSFET
C7831
5%
201
=PP3V3_S0_FET
100K
3.3V S0 FET
=PP3V3_S5_P3V3S0FET
R7832
1.05V RMGT FET
PM_SLP_RMGT_L
IN
FDC606P_G
57 20
2.3.0
OF
57
71
PBUS SUPPLY / BATTERY CHARGER

CRITICAL
CRITICAL
Q7900
Q7901
HAT1127H
HAT1127H
0.1UF
10%
25V
X5R
402
58 7
S
1
=PP3V42_G3H_CHGR
R7962
1
CHGR_AMON 1
4
CRITICAL
0.1UF
10%
25V 2
X5R
402
U7960
TL331
1.82K
1
CHGR_LOWCURRENT_GATE
GND
R79611
1%
1/20W
MF
201
SOT23-5
R7923
R7901
CHGR_SGATE
R7910
30.1K
OMIT
R7940
4.7
C7941
=PP3V42_G3H_CHGR
C7947
(CHGR_ACIN)
10%
10V
X5R
402-1
VDD
58
58
12 VHST
11 SCL
10 SDA
CHGR_SCL
CHGR_SDA
NC
CHGR_ACIN
R7945
C7944
0.01UF
10%
10V
201
2 X5R
29 THRM_PAD
C7943
56.2K
0.1UF
1%
1/16W
MF-LF
402 2
2
10%
16V
X5R
402
CHGR_VCOMP_R
C7945 1
AGATE 1
28
CSIN 27
CHGR_AGATE
CHGR_CSIP
CHGR_CSIN
16
58
BGATE
DCIN 2
CHGR_BGATE
CHGR_DCIN 58
BOOT 25
UGATE 24
PHASE 23
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
LGATE 21
CHGR_LGATE
10%
25V
X5R
402
AMON 9
BMON 15
ACOK 14
R7920
0.02
XW7921
SM
1
PPVDCIN_G3H_PRE_R
10%
25V
X5R
402
C7920
20%
25V
POLY-TANT
CASE-D2-SM
C7921
20%
25V
2
POLY-TANT
CASE-D2-SM
GND_CHGR_SGND
C7922 1
1UF
10%
25V
X5R
603-1
CRITICAL
FDMC8296
POWER33
CHGR_VNEG_R
4.7UH-7.5A
2
1
IHLP4040CZ-SM
10%
50V
CERM 2
402
58
42
=SMBUS_CHGR_SDA
CHGR_SDA
58
CHGR_ACOK
58
R7930
0.01
0.5%
1W
MF
0612
70
PPVBAT_G3H_CHGR_REG
PPVBAT_G3H_CHGR_OUT
CRITICAL CRITICAL
1
CRITICAL
C7930
47UF
20%
2 10V
POLY-TANT 2
CASE-B2-SM
FDMC8296
POWER33
10%
2 25V
X5R
603-1
47UF
20%
10V
POLY-TANT
CASE-B2-SM 2
XW7930
2
SM
C7926
XW7931
1000PF
PWM FREQ. = 400 kHz

MAX CURRENT = 5.35A??
10%
16V
2 X7R
201
58 70
C7935
1UF
C7931
(CHGR_CSOP)
SM
PPVBAT_G3H_CHRGR_REG_0 70
R79311
10
5%
1/20W
MF
201 2
(AC adapter limited?)
GND_CHGR_SGND
58
470PF
CHGR_SCL
CRITICAL
7AMP-24V
C7946 1
=SMBUS_CHGR_SCL
=PPBUSB_G3H
1206
L7900
Q7921
3.01K
1%
1/16W
MF-LF
402 2
TO SYSTEM
F7900
CRITICAL
2
7 44
XW7900
SM
R79461
=PPBUSA_G3H
1%
1/4W
MF-LF
1206
42
0.0022
CRITICAL
Q7920
CHGR_AMON 58
CHGR_BMON 58
CHGR_ACOK 58
R7980
1
0.1UF
10%
25V
X5R
402
CRITICAL
10%
25V
X5R
603-1
58
C7925
C7923
1UF
22UF
22UF
G
1
C
KELVIN CONNECTION
TO CURRENT SENSOR U5480
70 PP18V5_S5_CHGR_SW_R
CRITICAL
CRITICAL
0.1UF
10%
50V
CERM 2
402
GND_CHGR_SGND
0.5%
1W
MF
2 0612
0.001UF
58
CRITICAL
1
C7996
1
NC
TRKL* 13
26
6 AGND
ICOMP
VCOMP
VNEG
CSOP
CSON
20
QFN
SM
C7995
U7900 CSIP
4 VREF
3 ACIN
CHGR_ICOMP 5
CHGR_VCOMP 7
CHGR_VNEG 8
CHGR_CSOP 18
CHGR_CSON 17
33000PF
10%
6.3V
X5R 2
201
VDDP
OMIT
1UF
PGND
pullups offpage
5%
1/20W
MF
201
10%
2 10V
X5R
402-1
CRITICAL
XW7920
1
R7921
10
C7940
0.1UF
1%
1/20W
MF
201 2
C7942
ISL6258
9.76K
OMIT
10%
16V
CERM
402
PPVDCIN_G3H_PRE_0
5% MIN_LINE_WIDTH=0.2MM
1/20W MIN_NECK_WIDTH=0.2MM
MF
201
0.047UF 1
OMIT
1UF
10%
6.3V 2
X5R
402-1
R79111
C7924
5%
1/20W
MF
201
CHGR_VDDP
5%
1/16W
MF-LF
402
1UF
10
2
70
22
58 7
2CHGR_VDD
19
1%
1/20W
MF
201 2
62K
44
58
5%
1/20W
MF
201
VCC
3
CHGR_LOWCURRENT_REF
CHGR_DCIN
100K
5%
1/20W
MF
201 2
10%
2 25V
X5R
402
1%
1/20W
MF
201 2
62K
C7960
0.1UF
57.6K
C7910
R7999
CHGR_SGATE_DIV
5%
1/20W
MF
201 2
2
1
100K
R79601
58
R79001
C7900 1
PPVDCIN_G3H_PRE
B0530WS-X-G
70 43
D7910
SOD-323
PPVDCIN_G3H_PRE2
70
CRITICAL
LFPAK-SM
49
7 =PP18V5_G3H_CHGR
LFPAK-SM
70 PPVBAT_G3H_CHRGR_REG_R
R79471
10
5%
1/20W
MF
201 2
(CHGR_CSOP)
(CHGR_CSON)
ACOK pullup/down on SMC page

49 40 39
SMC_BC_ACOK
AMON PULLDOWN LOGIC
MAKE_BASE=TRUE
CHGR_AMON
BATTERY CHARGING
58
CRITICAL
PLACE RC CLOSE TO SMC
CHGR_BMON
58
SMC_BATT_ISENSE
Q7950
39
R7971
0
58 7
5%
1/16W
MF-LF
402
R7974
10%
6.3V
58
CHGR_AMON
39 40 43 44 58
SMC_DCIN_ISENSE
R7970
5%
1/16W
MF-LF
402
39
C7971
Q7970
R79731SSM6N15FEAPE
10%
6.3V
CERM
402
GND_SMC_AVSS
70 58
100K
C7950
10%
2 10V
X5R
201
S 1
BATT_POS_F 49
PBUS Supply/Battery Charger
C7951
SYNC_MASTER=M70
0.1UF
10%
2 16V
X5R
402

D 3 CHGR_VDD_L
SOT563
5%
1/20W
MF
201 2
39 40 43 44 58
PPVBAT_G3H_CHGR_OUT
0.01UF
58 CHGR_VDD
0.68UF
2
5%
1/20W
MF
201 2
PLACE RC CLOSE TO SMC

1
Q7970
D
1MSSM6N15FEAPE
SOT563
402
5%
1/20W
MF
2 201
TO BATTERY
SO-8
1M
2 CERM
GND_SMC_AVSS
FDS6681Z
R7975
C7972
0.68UF
1NO STUFF
=PP3V42_G3H_CHGR
CHGR_BGATE 58

5
S 4
SIZE
CHGR_VDD_R
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
58
71
R9002
FDC638P_G
=PP3V3_S5_LCD
CRITICAL
100K
10%
6.3V 2
X5R
201
SSM3K15FV D
70
CRITICAL
OMIT
1
C9011
10%
2 6.3V
X5R
201
LCDVDD_PWREN_L_R
SOD-VESM-HF
PP3V3_LCDVDD_SW
VOLTAGE=3.3V
0.1UF
5%
1/20W
MF
201
Q9004
0.1UF
10K
6
5
2
1
R9023
LCDVDD_PWREN_L
LCD + CAMERA CONNECTOR
SM
5%
1/20W
MF
2 201
C9040
90-OHM-100MA
10UF
1210-4SM1
SYM_VER-1
20%
2 6.3V
X5R
603
3300PF
1
1 G
IN
S 2
=USB2_CAMERA_N
BI
=USB2_CAMERA_P
CRITICAL
BI
L9052
42 6
=I2C_ALS_SDA
240-OHM-0.2A-0.8-OHM
1
2
I2C_ALS_SDA_F
=I2C_ALS_SCL
240-OHM-0.2A-0.8-OHM
1
2
I2C_ALS_SCL_F
0201
L9051
L9005
10%
10V
X5R
201
LVDS_IG_PANEL_PWR
L9007
C9012
C9013
17
Q9003
FERR-120-OHM-1.5A
2
=PP5V_S3_CAMERA 1
42 6
0201
0402-LF
R9014
C9016
100K
2 NPO
1000PF
5%
1/20W
MF
2 201
10%
16V
X7R
201
CRITICAL
L9004
C9052
10PF C9051
5%
J9000
20347-130E-11
5%
25V
NPO
201
201
FERR-120-OHM-1.5A
1
CRITICAL
1
10PF
25V
F-RT-SM
38
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0402-LF
C9015
10%
16V
X7R
201
1000PF
PLACE FILTERS AND CAPS NEAR PINS ON CONNECTOR
VOLTAGE=5V
70 6
120-OHM-0.3A-EMI
=PP3V3_S0_LCD
L9008
(LVDS DDC POWER)
PP5V_S3_CAMERA_F
USB2_CAMERA_F_P
USB2_CAMERA_F_N
VOLTAGE=3.3V
70 6
PP3V3_LCDVDD_SW_F
VOLTAGE=3.3V
70 6
PP3V3_S0_LCD_F
0402-LF
C9010
LVDS_IG_A_DATA_F_N<0>
67 LVDS_IG_A_DATA_F_P<0>
67 LVDS_IG_A_DATA_F_N<1>
67 LVDS_IG_A_DATA_F_N<2>
67 6 LVDS_IG_A_CLK_F_N
67 6 LVDS_IG_A_CLK_F_P
67
1000PF
10%
16V
X7R
201
62 6
1
R9008 R9009
10K
62 6
10K
17 6
BI
17 6
BI
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
62 6
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
62 6
62 6
62 6
62 6
70
LCDBKLT_RTN<1>
LCDBKLT_RTN<2>
LCDBKLT_RTN<3>
LCDBKLT_RTN<4>
LCDBKLT_RTN<5>
LCDBKLT_RTN<6>
PPVOUT_S0_LCDBKLT
BI
67 17 6
BI
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
L9010
2
SYM_VER-2
1210-4SM1
90-OHM-100MA
BI
67 17 6
BI
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
L9011
2
MIC CONNECTOR
VOLTAGE=3.3V
PP3V3_S0_MIC_F
NC
NC
67 17 6
BI
L9012
2
1
7
SYM_VER-2
1210-4SM1
90-OHM-100MA
CRITICAL
L9006
600-OHM-300MA
1
2 AUD_MIC_DATA 6
0402
CRITICAL
AUD_MIC_DATA_F
AUD_MIC_CLK_F
35
67 17
BI
67 17
BI
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_P
600-OHM-300MA
1
2 AUD_MIC_CLK
CRITICAL
L9053
90-OHM-100MA
1210-4SM1
SYM_VER-2
LVDS,Camera Conn. and ALS Conn.

SYNC_MASTER=GPU
6 35
2
0402
0.01UF
10%
16V
CERM
402
APN:518S0536
0402
600-OHM-300MA
L9031
GND_MIC_F
C9050
0402
L9050
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
L9030
5
6
BI
CRITICAL
CRITICAL
67 17 6
600-OHM-300MA
1
2 =PP3V3_S0_MIC
J9050
GS03067-11131-7F
CRITICAL
CRITICAL
F-RT-SM
7
NO STUFF 1
C9030
C9053
10PF
0.01UF
10%
16V
CERM
402
5%
25V
NPO
201
1 NO STUFF
C9031
10PF
2
5%
25V
SIZE
201
2 NPO
APPLE INC.
DRAWING NUMBER
REV.
051-7631
SCALE
SHT
NONE
518S0433
SYM_VER-2
1210-4SM1
90-OHM-100MA
39
CRITICAL
67 17 6
LCD I/F
31
32
33
34
35
36
37
CRITICAL
67 17 6
CAMERA I/F
2.3.0
OF
59
71
17
17
17
17
17
17
17
17
17
17
17
=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>
=MCP_HDMI_HPD
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
DP_ML_P<3>
DP_ML_N<3>
DP_ML_P<2>
DP_ML_N<2>
DP_ML_P<1>
DP_ML_N<1>
DP_ML_P<0>
DP_ML_N<0>
DP_HPD
61 67
MAKE_BASE=TRUE
61 67
MAKE_BASE=TRUE
61 67
MAKE_BASE=TRUE
61 67
MAKE_BASE=TRUE
61 67
MAKE_BASE=TRUE
61 67
MAKE_BASE=TRUE
61 67
MAKE_BASE=TRUE
61 67
MAKE_BASE=TRUE
61
MAKE_BASE=TRUE
DP_IG_DDC_CLK
DP_IG_DDC_DATA
60
MAKE_BASE=TRUE
60
MAKE_BASE=TRUE
DP_AUX_CH_C_N
R9300
60
BI
DP_IG_DDC_DATA
33
5%
1/20W
MF
201
BI
33
5%
1/20W
MF
201
6 35 61 67
BI
6 35 61 67
C9300
0.1UF
1
67
DP_AUX_CH_SW_N
10%
6.3V
X5R
201
R9301
DP_IG_DDC_CLK
60
BI
DP_AUX_CH_C_P
C9301
0.1UF
1
67
DP_AUX_CH_SW_P
10%
6.3V
X5R
201
Q9300
SSM6N15FEAPE
SOT563
Q9300
D 6
SSM6N15FEAPE
SOT563
G 5
S 1
DP_IG_AUX_CH_P
67 17
BI
67 17
BI
DP_IG_AUX_CH_N
=PP5V_S0_DP_AUX_MUX
1
R9306
1K
5%
1/20W
MF
2 201
R9302
100K
5%
1/20W
MF
2 201
DDC_CA_DET_LS5V_L
B
Q9301
3
SSM3K15FV
SOD-VESM-HF
G 1
DP_CA_DET
61
IN
DP_IG_CA_DET
OUT
17
DISPLAYPORT SUPPORT
SYNC_MASTER=NMARTIN

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
60
71
61 7
CRITICAL
=PP3V3_S0_DPCONN
U9450
C9451
TPS2051
MSOP
0.1UF
10%
6.3V
X5R
201
IN
OUT
IN
OUT 7
56
IN
=DPPWR_EN
EN
GND
OUT
OC*
THRML
L9400
NC
FERR-120-OHM-3A
PAD
70
NO STUFF1
C9450
0603
1
DP_ESD
CRITICAL
22UF
20%
6.3V
X5R-CERM
603
70
35 6
PP3V3_S0_DPFUSE
VOLTAGE=3.3V
PP3V3_S0_DPPWR
VOLTAGE=3.3V
0.01UF
D9411
C9400
RCLAMP0524P
10%
10V
X5R
201
DP_ESD
CRITICAL
SLP2510P8
D9410
5 IO
IO
NC
R9420 1
SLP2510P8
7
GND
6 NC
RCLAMP0524P
5 IO
6 NC
IO 4
NC 7
5%
1/20W
MF
201
67 60
IN
DP_ML_P<0>
IN
DP_ML_N<0>
C9410
0.1uF
67 60
C9411
0.1uF
DP_ML_C_P<0>
67 6
10%
6.3V
X5R
DP_ML_C_N<0>
10%
6.3V
X5R
TCM1210-4SM
SYM_VER-2
GND
100K
FL9400
12-OHM-100MA
FL9410
201
12-OHM-100MA
TCM1210-4SM
SYM_VER-2
FL9420
12-OHM-100MA
C9414
DP_ML_P<2>
IN
2
10%
DP_ML_C_P<2>
2
10%
DP_ML_C_N<2>
0.1uF
67 60
C9415
DP_ML_N<2>
IN
0.1uF
6.3V
X5R
X5R
TCM1210-4SM
SYM_VER-2
DP_ML_F_P<0>
DP_ML_F_N<0>
BI
67 60 35 6
BI
35 67
201
DP_ML_F_P<1>
DP_ML_F_N<1>
67 35
67 35
DP_ML_F_P<2> 35
DP_ML_F_N<2> 35
DP_CA_DET_Q
DP_AUX_CH_C_P
DP_AUX_CH_C_N
DP_ML_C_N<1>
C9413
12-OHM-100MA
TCM1210-4SM
SYM_VER-2
67 6
DP_ML_C_P<3>
DP_ML_P<1>
10%
6.3V
DP_ML_N<1>
10%
6.3V
2
10%
DP_ML_P<3>
DP_ML_N<3>
10%
6.3V
C9416
67
67
35 6
DP_ML_F_P<3>
DP_ML_F_N<3>
HDMI_CEC
35 6
DP_HPD_Q
67 35
201
6 35
0.1uF
2
67 6
DP_ML_C_N<3>
C9417
0.1uF
X5R
X5R
201
201
IN
60 67
IN
60 67
IN
60 67
IN
60 67
6.3V
X5R
X5R
201
201
R9425
1M
These nets connect to

RIO connector @ J4200
R9440
R9421 1
100K
100K
5%
1/20W
MF
201 2
5%
1/20W
MF
201
R9441
DP_CA_DET
DP_ESD
CRITICAL
DP_ESD
CRITICAL
D9410
D9411
RCLAMP0524P
RCLAMP0524P
SLP2510P8
SLP2510P8
5%
1/20W
MF
201
100K
Q9440
5%
1/20W
MF
201 2
2N7002DW-X-G
Q9440 must have Drain to Gate leakage of <500nA
2 IO
IO
NC
9 NC
SOT-363
2 DP_CA_DET_L
Q9440
SOT-363
5
2 IO
10
9 NC
DP_ESD
CRITICAL
IO
NC
1
10
D9400
2N7002DW-X-G
and Gate to Source resistance of >5MOhm
GND
OUT
RCLAMP0504F
(DP_CA_DET_Q)
SC70-6-1
R9422
1M
5%
1/20W
MF
201
61 7
FL9430
=PP3V3_S0_DPCONN
60
0.1uF
35 67
67 35
67 60 35 6
C9412
GND
61 7
6.3V
DP_ML_C_P<1>
0.1uF
C
67 60
201
DP to DVI/HDMI
Cable Adapter
(CA) has 100k
pullup to DP_PWR.
4
3
=PP3V3_S0_DPCONN
R94451
10K
5%
1/20W
MF
201 2
60
OUT
R94441
DP_HPD
10K
5%
1/20W
MF
201 2
R94461
100K
1%
1/20W
MF
201 2
Q9441
2N7002DW-X-G
SOT-363
S
1
A
MCP requires pull
down HPD input with
100K if DP_HPD is used.
2DP_HPD_DET_L
DisplayPort Connector
Q9441
SOT-363
5
SYNC_MASTER=M98_MLB
2N7002DW-X-G
(DP_HPD_Q)
R94231
100K
1%
1/20W
MF
201 2

DP Source must pull

down HPD input with
greater than or equal
to 100K (DPv1.1a).

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
61
71

D
CRITICAL
CRITICAL
L9750
70 63
D9750
22UH-1.7A
PPBUS_S0_LCDBKLT_PWR
=PP3V3_S0_LCDBKLT
63 17
24
IN
LVDS_IG_BKL_ON
IN
BKLT_PLT_RST_L
C9740
U9740Y
63
LCDBKLT_ENA
1 NO STUFF
R9740
10K
C9741
0.1UF
100K
C9751
1UF
10%
16V
X5R 2
402
5%
1/20W
MF
2 201
10%
6.3V 2
X5R
201
C9750
10UF
10%
25V
2 X5R
603-1
10%
25V
X5R
1206-1
U9750
LCDBKLT_ENA_RC
f=500KHz
C9756
C9757
4.7UF
4.7UF
4.7UF
10%
50V
X7R-CERM
1206
10%
50V
X7R-CERM
1206
10%
50V
X7R-CERM
1206
C9758
4.7UF
10%
50V
X7R-CERM
1206
QFN
1 ENA
R97551
1M
1%
1/20W
MF
201 2
SW 18
>2V = ON, <1V = OFF

IN
C9755
VIN
CRITICAL
OZ9956ALN
63
5%
1/20W
MF
201
0.1UF
PD3S140XF
6 59 70
VOLTAGE=35V
R9741
SOT665
SWITCH_NODE=TRUE
IHLP2020CZ11-SM
5 TC7SZ08AFEAPE
PPVOUT_S0_LCDBKLT_SW
PPVOUT_S0_LCDBKLT
SM
70
BKLT_PWM
20 PWM
ISEN1 10
100Hz - 20KHz
LCDBKLT_ISET
8 ISET
ISEN2 11
LCDBKLT_RT
5 RT
ISEN3 12
9 SSTCMP
ISEN4 14
LCDBKLT_SSTCMP
LCDBKLT_RTN_RC<3>
R9762
10K
1%
1/20W
MF
201 2
1%
1/20W
MF
2 201
C9763
LCDBKLT_VREF
10%
50V
CERM
402
OMIT
100K
1%
1/20W
MF
2 201
ISEN6 16
C9762
0.01UF
20%
16V
CERM
402
OVP 6
19 NC4
THRML
PAD
GNDA
C9760
1UF
LCDBKLT_RTN_RC<5>
10%
10V
X5R
402-1
GND_LCDBKLT_GNDA
VOLTAGE=0V
LCDBKLT_OVP
LCDBKLT_RTN<2>
6 59
OVP Threshold: 37.9V
R97561
78.7K
LCDBKLT_RTN<3>
6 59
5%
1/20W
MF
201
R9774
1%
1/20W
MF
201 2
SM
LCDBKLT_RTN<4>
6 59
5%
1/20W
MF
201
XW9750
1
R9773
LCDBKLT_RTN_RC<6>
7 NC2
17 NC3
13
R9764
ISEN5 15
2 NC1
6 59
5%
1/20W
MF
201
NC
NC
NC
NC
LCDBKLT_SSTCMP_RC
1
3 VREF
0.001UF
21
75K
LCDBKLT_RTN_RC<4>
R97661
LCDBKLT_RTN<1>
R9772
FOP[Mhz] = 50000/R9764
5%
1/20W
MF
201
LCDBKLT_RTN_RC<2>
ILED[A] = 1500/R9766
R9771
LCDBKLT_RTN_RC<1>
R9775
1
LCDBKLT_RTN<5>
6 59
5%
1/20W
MF
201
R9776
1
5%
1/20W
MF
201
C9771
1000PF
10%
16V
X7R 2
201
C9772
1000PF
10%
16V
X7R 2
201
C9773
1000PF
10%
16V
X7R 2
201
C9774
1000PF
10%
16V
X7R 2
201
C9775
1000PF
10%
16V
X7R 2
201
C9776
LCDBKLT_RTN<6>
6 59
1000PF
10%
16V
X7R 2
201
Place R9771-R9776,C9771-C9776 close to J9000

SYNC_DATE=(MASTER)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
62
71
CRITICAL
Q9806
FDC638APZ_SBMS001
SSOT6-HF
CRITICAL
F9800
2
0402-HF
70 PPBUS_S0_LCDBKLT_FUSED
VOLTAGE=12.6V
R9808
301K
1/16W
MF-LF
402
C9802
0.1UF
1%
VOLTAGE=12.6V
=PPBUS_S0_LCDBKLT
IN
2 5
2AMP-32V
7
10%
16V
X5R
402
70 PPBUS_S0_LCDBKLT_EN_DIV
R9809
147K
1%
1/16W
MF-LF
70 PPBUS_S0_LCDBKLT_EN_L
402
Q9807
SSM3K15FV
D 3
SOD-VESM-HF
62
IN
S 2
62 70
OUT
62
LCDBKLT_ENA
63 17
OUT
VOLTAGE=12.6V
R9840
100K
5%
1/20W
MF
2 201
LVDS_IG_BKL_ON
17 62
LVDS_IG_BKL_PWM
17 63
IN
LVDS_IG_BKL_PWM
BKLT_PWM
MAKE_BASE=TRUE
R9841
100K
5%
1/20W
MF
2 201
LCD Backlight Support
SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
63
71
ADDITIONAL CPU VCORE HF DECOUPLING

40x 2.2uF 0402
11 10 7
=PPVCORE_S0_CPU
LAYOUT NOTE:
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C9900
C9901
C9902
C9903
C9904
C9905
C9906
C9907
C9908
C9909
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
2.2UF
LAYOUT NOTE:
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C9910
C9911
C9912
C9913
C9914
C9915
C9916
C9917
C9918
C9919
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C9920
C9921
C9922
C9923
C9924
C9925
C9926
C9927
C9928
C9929
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
LAYOUT NOTE:
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
C
LAYOUT NOTE:
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C9930
C9931
C9932
C9933
C9934
C9935
C9936
C9937
C9938
C9939
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
20%
6.3V
CERM OMIT
402-LF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
Additional CPU/GPU Decoupling
SYNC_MASTER=
SYNC_DATE=

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
64
71
FSB (Front-Side Bus) Constraints
CPU / FSB Net Properties

TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FSB_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADSTB0
FSB_50S
FSB_ADSTB
FSB_ADDR_GROUP1
FSB_50S
FSB_ADDR
FSB_ADSTB1
FSB_50S
FSB_ADSTB
FSB_1X
FSB_50S
FSB_1X
FSB_BREQ0_L
FSB_50S
FSB_1X
FSB_BREQ1_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_CPURST_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_BSEL
CPU_50S
CPU_AGTL
CPU_FERR_L
CPU_50S
CPU_8MIL
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_INIT_L
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_PROCHOT_L
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
FSB_CPUSLP_L
CPU_50S
CPU_AGTL
CPU_FROM_SB
CPU_50S
CPU_AGTL
CPU_DPRSTP_L
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
CPU_IERR_L
CPU_50S
PM_DPRSLPVR
CPU_50S
CPU_AGTL
(See above)
CPU_50S
CPU_AGTL
CPU_GTLREF
CPU_50S
CPU_GTLREF
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
XDP_TDI
CPU_50S
CPU_ITP
XDP_TDO
CPU_50S
CPU_ITP
XDP_TMS
CPU_50S
CPU_ITP
XDP_TCK
CPU_50S
CPU_ITP
XDP_TRST_L
CPU_50S
CPU_ITP
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_L5
CPU_50S
CPU_ITP
(FSB_CPURST_L)
CPU_50S
CPU_ITP
CPU_50S
CPU_8MIL
CPU_50S
CPU_8MIL
CPU_27P4S
CPU_VCCSENSE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
TABLE_SPACING_RULE_ITEM
FSB_DATA
=2x_DIELECTRIC
FSB_DSTB
=3x_DIELECTRIC
FSB_DATA
TOP,BOTTOM
=4x_DIELECTRIC
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
FSB_ADDR
=STANDARD
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
FSB_ADSTB
=2x_DIELECTRIC
FSB_ADSTB
TOP,BOTTOM
=4x_DIELECTRIC
FSB_1X
=STANDARD
FSB 4X Signal Groups
FSB_DSTB_50S
FSB_1X
TOP,BOTTOM
=3x_DIELECTRIC
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 2X
Signals
FSB 4X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
FSB 1X Signals
Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CPU_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CPU_27P4S
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
CPU_AGTL
=STANDARD
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
CPU_8MIL
8 MIL
?
CPU_COMP
25 MIL
?
CPU_GTLREF
25 MIL
SR DG recommends at least 25 mils, >50 mils preferred
?
CPU_ITP
=2:1_SPACING
CPU_VCCSENSE
25 MIL
Most CPU signals with impedance requirements are 55-ohm single-ended.

Some signals require 27.4-ohm single-ended impedance.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MCP_50S
=50_OHM_SE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_FSB_COMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
FSB Clock Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
CLK_FSB
=3x_DIELECTRIC
CLK_FSB
TOP,BOTTOM
=4x_DIELECTRIC
FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>
FSB_A_L<35..17>
FSB_ADSTB_L<1>
FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L
CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DPWR_L
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N
CPU_IERR_L
=100_OHM_DIFF
SPACING_RULE_SET
FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
8 9 13
13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
9 13
8 9 12 13
9 13
9 13
9 13
8 9
9 13
9 13
9 13
8 9 13
8 9 13
9 13 40 50
9 12 13
9 13
9 13
9 13 40
9 13
9 13
8 9 13 50
9 13
13
13
13
13
9 13
9 13
6 12 13
6 12 13
13
13
PM_DPRSLPVR
IMVP_DPRSLPVR
20 50
50
DIFFPAIR NECK GAP

CLK_FSB_100D
FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
9 25
9
9
9
9
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
(CPU_VCCSENSE)
(CPU_VCCSENSE)
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CPURST_L
CPU_VID<6..0>
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
6 9 12
9 12
6 9 12
6 9 12
6 9 12
6 9 12
6 9 12
6 12
10 11 50
CPU/FSB Constraints
11
10 50
SYNC_MASTER=M97
10 50
50
50

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
65
71
Memory Bus Constraints

Memory Net Properties
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MEM_50S
=50_OHM_SE
=50_OHM_SE
0.110 MM
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MEM_50S_VDD
=50_OHM_SE
=50_OHM_SE
0.110 MM
=50_OHM_SE
=STANDARD
=STANDARD
MEM_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
MEM_90D_VDD
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
MEM_A_CLK
MEM_90D
MEM_CLK
MEM_A_CLK
MEM_90D
MEM_CLK
MEM_A_CNTL
MEM_50S
MEM_CTRL
MEM_A_CNTL
MEM_50S
MEM_CTRL
MEM_A_CNTL
MEM_50S
MEM_CTRL
MEM_A_CMD
MEM_50S
MEM_CMD
MEM_A_CMD
MEM_50S
MEM_CMD
MEM_A_CMD
MEM_50S
MEM_CMD
MEM_A_CMD
MEM_50S
MEM_CMD
MEM_A_CMD
MEM_50S
MEM_CMD
MEM_A_DQ_BYTE0
MEM_50S
MEM_DATA
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
14 27 28 33
14 27 28 33
MEM_A_CKE<1..0>
MEM_A_CS_L<1..0>
MEM_A_ODT<1..0>
14 27 28 33
14 27 28 33
14 27 28 33
SPACING_RULE_SET
LAYER
WEIGHT
MEM_CLK2MEM
=2.28:1_SPACING
?
MEM_CTRL2CTRL
=1.1:1_SPACING
?
MEM_CTRL2MEM
=2.28:1_SPACING
MEM_CMD2CMD
=1.1:1_SPACING
MEM_CMD2MEM
=2.28:1_SPACING
MEM_A_A<14..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
14 27 28 33
14 27 28 33
14 27 28 33
14 27 28 33
14 27 28 33
MEM_A_DQ_BYTE1
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE0
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_50S
MEM_DATA
MEM_A_DQS0
MEM_90D
MEM_DQS
MEM_A_DQS0
MEM_90D
MEM_DQS
MEM_A_DQS1
MEM_90D
MEM_DQS
MEM_A_DQS1
MEM_90D
MEM_DQS
MEM_A_DQS2
MEM_90D
MEM_DQS
MEM_A_DQS2
MEM_90D
MEM_DQS
MEM_A_DQS3
MEM_90D
MEM_DQS
MEM_A_DQS3
MEM_90D
MEM_DQS
MEM_A_DQS4
MEM_90D
MEM_DQS
MEM_A_DQS4
MEM_90D
MEM_DQS
MEM_A_DQS5
MEM_90D
MEM_DQS
MEM_A_DQS5
MEM_90D
MEM_DQS
MEM_A_DQS6
MEM_90D
MEM_DQS
MEM_A_DQS6
MEM_90D
MEM_DQS
MEM_A_DQS7
MEM_90D
MEM_DQS
MEM_A_DQS7
MEM_90D
MEM_DQS
MEM_B_CLK
MEM_90D
MEM_CLK
MEM_B_CLK
MEM_90D
MEM_CLK
MEM_B_CNTL
MEM_50S
MEM_CTRL
MEM_B_CNTL
MEM_50S
MEM_CTRL
MEM_B_CNTL
MEM_50S
MEM_CTRL
MEM_B_CMD
MEM_50S
MEM_CMD
MEM_B_CMD
MEM_50S
MEM_CMD
MEM_B_CMD
MEM_50S
MEM_CMD
MEM_B_CMD
MEM_50S
MEM_CMD
MEM_B_CMD
MEM_50S
MEM_CMD
MEM_B_DQ_BYTE0
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE0
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_50S
MEM_DATA
MEM_B_DQS0
MEM_90D
MEM_DQS
MEM_B_DQS0
MEM_90D
MEM_DQS
MEM_DATA2DATA
=1.1:1_SPACING
?
MEM_DATA2MEM
=2.28:1_SPACING
?
MEM_DQS2MEM
=2.28:1_SPACING
?
MEM_2OTHER
25 MIL
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
MEM_CLK2MEM
MEM_CMD
MEM_CLK
MEM_CMD2MEM
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_CLK
MEM_CMD
MEM_CLK2MEM
MEM_CMD
MEM_CMD
MEM_CLK
MEM_DATA
MEM_CLK2MEM
MEM_CLK
MEM_DQS
MEM_CLK2MEM
MEM_CMD
MEM_DATA
MEM_CMD2MEM
MEM_CMD
MEM_DQS
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
MEM_CTRL2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
MEM_DATA2MEM
MEM_CTRL
MEM_CTRL
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
MEM_CTRL2MEM
MEM_DATA
MEM_CTRL
MEM_DATA2MEM
MEM_DATA
MEM_CMD
MEM_DATA2MEM
MEM_CTRL
MEM_DATA
MEM_CTRL2MEM
MEM_DATA
MEM_DATA
MEM_DATA2DATA
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
MEM_DATA
MEM_DQS
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
MEM_DQS2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_2OTHER
MEM_CTRL
MEM_DQS2MEM
MEM_CTRL
MEM_2OTHER
MEM_DQS
MEM_CMD
MEM_DQS2MEM
MEM_DQS
MEM_DATA
MEM_DQS2MEM
MEM_CMD
MEM_2OTHER
MEM_DATA
MEM_2OTHER
MEM_DQS
NET_SPACING_TYPE2
MEM_DQS2MEM
AREA_TYPE
MEM_DQS
MEM_2OTHER
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
GND
GND_P2MM
MEM_CLK
PWR
BUS2PWR_GND
MEM_CMD
GND
GND
MEM_CLK
GND
BUS2PWR_GND
GND_P2MM
MEM_CTRL
PWR
BUS2PWR_GND
MEM_DATA
GND
GND_P2MM
MEM_CTRL
GND
BUS2PWR_GND
MEM_DQS
GND
GND_P2MM
MEM_CMD
PWR
BUS2PWR_GND
MEM_CLK
PP1V5_MEM
PWR_P2MM
MEM_CTRL
PP1V5_MEM
PWR_P2MM
MEM_CMD
GND
BUS2PWR_GND
MEM_DATA
PWR
BUS2PWR_GND
MEM_DATA
PP1V5_MEM
PWR_P2MM
MEM_DQS
PP1V5_MEM
PWR_P2MM
MEM_DATA
GND
BUS2PWR_GND
MEM_DQS
PWR
BUS2PWR_GND
PP1V5_MEM
PWR_P2MM
MEM_DQS
GND
BUS2PWR_GND
DDR3:
MEM_B_DQS1
MEM_90D
MEM_DQS
MEM_B_DQS1
MEM_90D
MEM_DQS
MEM_B_DQS2
MEM_90D
MEM_DQS
MEM_B_DQS2
MEM_90D
MEM_DQS
MEM_B_DQS3
MEM_90D
MEM_DQS
MEM_B_DQS3
MEM_90D
MEM_DQS
MEM_B_DQS4
MEM_90D
MEM_DQS
MEM_B_DQS4
MEM_90D
MEM_DQS
MEM_B_DQS5
MEM_90D
MEM_DQS
MEM_B_DQS5
MEM_90D
MEM_DQS
DQ signals should be matched within 5 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps.
CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
14 28
14 28
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
14 27
14 27
14 27
14 27
14 28
14 28
14 28
14 28
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 28
14 28
14 28
14 28
14 28
14 28
14 28
14 28
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
14 29 30 33
14 29 30 33
MEM_B_CKE<1..0>
MEM_B_CS_L<1..0>
MEM_B_ODT<1..0>
14 29 30 33
14 29 30 33
14 29 30 33
MEM_B_A<14..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
14 29 30 33
14 29 30 33
14 29 30 33
14 29 30 33
14 29 30 33
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
14 29
14 29
14 29
14 29
14 30
14 30
14 30
14 30
MEM_CMD
14 28
GND_P2MM
MEM_CTRL
14 28
NET_SPACING_TYPE1
14 27
MEM_DQS
14 27
MEM_DQS
14 27
MEM_CMD2CMD
14 27
Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
MEM_B_DQS6
MEM_90D
MEM_DQS
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MEM_B_DQS6
MEM_90D
MEM_DQS
MEM_B_DQS7
MEM_90D
MEM_DQS
MCP MEM COMP Signal Constraints
MEM_B_DQS7
MEM_90D
MEM_DQS
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
14 29
14 29
14 29
14 29
14 30
14 30
14 30
14 30
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
14 29
14 29
14 29
14 29
14 29
14 29
14 29
14 29
14 30
14 30
Memory Constraints
14
30
14 30
SYNC_MASTER=M97
14 30
14 30
14 30
14 30

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
7 MIL
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_MEM_COMP
7 MIL
=STANDARD
=STANDARD
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
=STANDARD
15
VOLTAGE=0V
15
VOLTAGE=1.5V
MEM_CLK
MEM_RESET_L
30
26 27
28 29

SIZE
SPACING_RULE_SET
LAYER
WEIGHT
8 MIL
NET_SPACING_TYPE=PP1V5_MEM
GND
NET_SPACING_TYPE=GND
22
7
15
DRAWING NUMBER
MCP_MEM_COMP
APPLE INC.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
66
71
NET_TYPE
PCI-Express
PHYSICAL
SPACING
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_FC_D2R
PCIE_90D
PCIE
PCIE_90D
PCIE
MCP_PE0_REFCLK
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
PEG_R2D
CLK_PCIE_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
PEG_D2R
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
PCIE
=3X_DIELECTRIC
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
CLK_PCIE
20 MIL
?
MCP_PEX_COMP
8 MIL
PCIE_MINI_R2D
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

PCIE_MINI_D2R
Analog Video Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
CRT_50S
=50_OHM_SE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
PCIE_FW_R2D
PCIE_FW_D2R
SPACING_RULE_SET
LAYER
WEIGHT
CRT
=4:1_SPACING
?
CRT_2CRT
=STANDARD
?
CRT_2CLK
50 MIL
?
PCIE_EXCARD_R2D
CRT_2SWITCHER
250 MIL
?
CRT_SYNC
16 MIL
PCIE_EXCARD_D2R
?
MCP_DAC_COMP
=2:1_SPACING
CRT signal single-ended impedence varies by location:

- 37.5-ohm from MCP to first termination resistor.
- 50-ohm from first to second termination resistor.
- 75-ohm from output of three-pole filter to connector (if possible).
R/G/B signals should be matched as close as possible and < 10 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.
PCIE_FC_R2D
MCP_PE1_REFCLK
Digital Video Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MCP_PE4_REFCLK
DP_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LVDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_PE2_REFCLK
MCP_DV_COMP
20 MIL
20 MIL
=STANDARD
=STANDARD
MCP_PE3_REFCLK
=STANDARD
CLK_PCIE_100D
CLK_PCIE
TMDS_IG_TXC
DP_100D
DISPLAYPORT
TMDS_IG_TXC
DP_100D
DISPLAYPORT
TMDS_IG_TXD
DP_100D
DISPLAYPORT
TMDS_IG_TXD
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_100D
DISPLAYPORT
MCP_HDMI_RSET
MCP_DV_COMP
MCP_HDMI_VPROBE
MCP_DV_COMP
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA3
LVDS_100D
LVDS
LVDS_IG_A_DATA3
LVDS_100D
LVDS
LVDS_IG_B_CLK
LVDS_100D
LVDS
LVDS_IG_B_CLK
LVDS_100D
LVDS
LVDS_IG_B_DATA
LVDS_100D
LVDS
LVDS_IG_B_DATA
LVDS_100D
LVDS
LVDS_IG_B_DATA3
LVDS_100D
LVDS
LVDS_IG_B_DATA3
LVDS_100D
LVDS
MCP_IFPAB_RSET
MCP_DV_COMP
MCP_PEX_CLK_COMP
SPACING_RULE_SET
LAYER
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
=3x_DIELECTRIC
LVDS
=3x_DIELECTRIC
MCP_PEX_COMP
WEIGHT
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
SATA Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SATA_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SATA_100D_HDD
=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
SATA
=4x_DIELECTRIC
SATA
TOP,BOTTOM
=3x_DIELECTRIC
SATA_TERMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
SATA_HDD_D2R
MCP_SATA_TERMP
DP_ML_C_P<3..0>
DP_ML_C_N<3..0>
DP_ML_F_P<3..0>
DP_ML_F_N<3..0>
DP_ML_P<3..0>
DP_ML_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
DP_AUX_CH_C_P
DP_AUX_CH_C_N
DP_AUX_CH_SW_P
DP_AUX_CH_SW_N
MCP_HDMI_RSET
MCP_HDMI_VPROBE
LVDS_IG_A_CLK_F_P
LVDS_IG_A_CLK_F_N
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_F_P<2..0>
LVDS_IG_A_DATA_F_N<2..0>
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<2..0>
LVDS_IG_B_DATA_N<2..0>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
MCP_IFPAB_VPROBE
SATA_HDD_R2D
PEG_R2D_P<15..0>
PEG_R2D_N<15..0>
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
PEG_D2R_C_P<15..0>
PEG_D2R_C_N<15..0>
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_N
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
PCIE_FC_R2D_P
PCIE_FC_R2D_N
PCIE_FC_R2D_C_P
PCIE_FC_R2D_C_N
PCIE_FC_D2R_P
PCIE_FC_D2R_N
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FC_P
PCIE_CLK100M_FC_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
MCP_PEX_CLK_COMP
TMDS_IG_TXC_P
TMDS_IG_TXC_N
TMDS_IG_TXD_P<2..0>
TMDS_IG_TXD_N<2..0>
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_TERMP
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_UF_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_UF_N
MCP_SATA_TERMP
16 34
16 34
16 34
16 34
8 16
8 16
16 34
16 34
16
6 61
6 61
35 61
35 61
60 61
60 61
17 60
17 60
6 35 60 61
6 35 60 61
60
60
17 23
17 23
6 59
6 59
17 59
17 59
59
59
6 17 59
6 17 59
8 17
8 17
8 17
8 17
8 17
8 17
8 17
8 17
17 23
17 23
19 36
19 36
6 36
MCP Constraints 1
6 36
36
SYNC_MASTER=M97
36
19 36
19 36

6 36
6 36
36
36
19
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
67
71
PCI Bus Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MCP_DEBUG
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD24
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_C_BE_L
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_REQ0_L
PCI_55S
PCI
PCI_GNT0_L
PCI_55S
PCI
PCI_REQ1_L
PCI_55S
PCI
PCI_GNT1_L
PCI_55S
PCI
PCI_INTW_L
PCI_55S
PCI
PCI_INTX_L
PCI_55S
PCI
PCI_INTY_L
PCI_55S
PCI
PCI_INTZ_L
PCI_55S
PCI
MCP_PCI_CLK2
CLK_PCI_55S
CLK_PCI
CLK_PCI_55S
CLK_PCI
LPC_AD
LPC_55S
LPC
LPC_FRAME_L
LPC_55S
LPC
LPC_RESET_L
LPC_55S
LPC
MCP_LPC_CLK0
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
CLK_PCI_55S
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
WEIGHT
PCI
=STANDARD
?
CLK_PCI
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LPC Bus Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
6 MIL
LPC
CLK_LPC
8 MIL
USB 2.0 Interface Constraints

LAYER
ALLOW ROUTE
ON LAYER?
6 12 18
D
18
18
PHYSICAL_RULE_SET
MCP_DEBUG<7..0>
PCI_AD<23..8>
PCI_AD<24>
PCI_AD<31..25>
PCI_PAR
PCI_C_BE_L<3..0>
PCI_IRDY_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L
PCI_REQ0_L
PCI_GNT0_L
PCI_REQ1_L
PCI_GNT1_L
PCI_INTW_L
PCI_INTX_L
PCI_INTY_L
PCI_INTZ_L
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCI_CLK33M_MCP_R
PCI_CLK33M_MCP
LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L
18
18
18 39 41
18 39 41
18 24
MCP_USB_RBIAS
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
USB_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
SPACING_RULE_SET
LAYER
WEIGHT
=4x_DIELECTRIC
USB
USB_EXTA
USB
TOP,BOTTOM
SMBus Interface Constraints
USB_MINI
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
=55_OHM_SE
=55_OHM_SE
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

USB_EXTD
SMB_55S
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_CAMERA
SPACING_RULE_SET
LAYER
WEIGHT
SMB
=2x_DIELECTRIC
?
USB_BT
HD Audio Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
USB_TPAD
DIFFPAIR NECK GAP

HDA_55S
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_IR
WEIGHT
HDA
=2x_DIELECTRIC
USB_EXTB
MCP_HDA_COMP
8 MIL

USB_EXCARD
SIO Signal Constraints
USB_EXTC
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
CONN_USB_EXTA_P
CONN_USB_EXTA_N
USB_MINI_P
USB_MINI_N
USB_EXTD_P
USB_EXTD_N
USB_CAMERA_P
USB_CAMERA_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
CONN_USB2_BT_P
CONN_USB2_BT_N
USB_TPAD_P
USB_TPAD_N
CONN_TPAD_USB_P
CONN_TPAD_USB_N
USB_IR_P
USB_IR_N
USB_EXTB_P
USB_EXTB_N
CONN_USB_EXTB_P
CONN_USB_EXTB_N
USB_EXCARD_P
USB_EXCARD_N
USB_EXTC_P
USB_EXTC_N
18 24
24 39
24 41
8 19
8 19
37
37
8 19
8 19
8 19
8 19
8 19
8 19
8 19
8 19
8 19
8 19
8 19
8 19
8 19
8 19
8
8
8
8
CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
MCP_USB_RBIAS_GND
MCP_USB_RBIAS
MCP_USB_RBIAS
SMBUS_MCP_0_CLK
SMB_55S
SMB
SMBUS_MCP_0_DATA
SMB_55S
SMB
SMBUS_MCP_1_CLK
SMB_55S
SMB
SMBUS_MCP_1_DATA
SMB_55S
SMB
HDA_BIT_CLK
HDA_55S
HDA
HDA_55S
HDA
SPI Interface Constraints
HDA_SYNC
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDIN_CODEC
HDA_SDOUT
HDA_SDOUT_R
MCP_HDA_COMP
MCP_HDA_PULLDN_COMP
CLK_SLOW_55S
CLK_SLOW
CLK_SLOW_55S
CLK_SLOW
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPACING_RULE_SET
LAYER
WEIGHT
CLK_SLOW
8 MIL
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
HDA_RST_L
HDA_SDIN0
SPACING_RULE_SET
LAYER
WEIGHT
HDA_SDOUT
SPI
8 MIL
?
MCP_HDA_PULLDN_COMP
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
19
6 12 20 42
6 12 20 42
20 42
20 42
6 20 35
20
6 20 35
20
20
20 35
6 20 35
6 20 35
20
20

MCP_SUS_CLK
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS0
SPI_55S
SPI
SPI_55S
SPI
SPI_CLK
SPI_55S
SPI
SPI_MOSI
SPI_55S
SPI
SPI_MISO
SPI_55S
SPI
SPI_CS0
SPI_55S
SPI
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_MISO_R
SPI_CS0_R_L
SPI_CS0_L
SPI_CLK_MUX
SPI_MOSI_MUX
SPI_MISO_MUX
SPI_MLB_CS_L
20 24
24 39
MCP Constraints 2
20 41
48
SYNC_MASTER=M97
20 41
48
20 41

48
20 41

41 48
41 48
41 48
SIZE
41 48
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
68
71
SMC SMBus Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
NET_TYPE
PHYSICAL
SPACING
SMBUS_SMC_A_S3_SCL
SMB_55S
SMB
SMBUS_SMC_A_S3_SDA
SMB_55S
SMB
SMBUS_SMC_B_S0_SCL
SMB_55S
SMB
SMBUS_SMC_B_S0_SDA
SMB_55S
SMB
SMBUS_SMC_0_S0_SCL
SMB_55S
SMB
SMBUS_SMC_0_S0_SDA
SMB_55S
SMB
SMBUS_SMC_BSA_SCL
SMB_55S
SMB
SMBUS_SMC_BSA_SDA
SMB_55S
SMB
SMBUS_SMC_MGMT_SCL
SMB_55S
SMB
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
42
42
42
42
42
42
6 42
6 42
42
42
SMBus Charger Net Properties

NET_TYPE
PHYSICAL
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
SPACING
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSO_P
CHGR_CSO_N
SMC Constraints
SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
69
71
8
I1
I2
I3
I4
I5
I6
I7
I8
I10
I9
I12
I11
I13
I14
I16
I15
I18
I17
I19
I21
I20
I23
I100
I101
I22
I24
I25
I26
I28
I27
I30
I29
I31
I33
I32
I35
I34
I36
I38
I37
I39
I41
I40
I43
I42
I44
I46
I45
I48
I47
I49
I50
I52
I51
I54
I53
I55
I57
I56
I59
I58
I72
I71
I73
I74
I76
I75
I78
I77
I79
I81
I80
I83
I82
I84
I86
I85
I102
I103
I104
I105
I106
I108
I109
I107
I110
I112
I113
I111
I114
PP0V75_S0
PP0V75_S3
PP18V5_DCIN
PP18V5_DCIN_ONEWIRE
PP18V5_G3H
PP18V5_S5_CHGR_SW_R
PP1V05_RMGT
PP1V05_S0
PP1V05_S0_MCP_PEX_AVDD_R
PP1V05_S0_MCP_PEX_DVDD_R
PP1V05_S5
PP1V2_S0_FC_VDD
PP1V5_S0
PP1V5_S0_FC_AVDDL_F
PP1V5_S0_FC_AVDDT_F
PP1V5_S3
PP1V8_S0
PP2V_S0_MCPREG_REF
PP3V3_LCDVDD_SW
PP3V3_LCDVDD_SW_F
PP3V3_RMGT
PP3V3_S0
PP3V3_S0_CPUTHMSNS_R
PP3V3_S0_DPFUSE
PP3V3_S0_DPPWR
PP3V3_S0_FC_AVDD_F
PP3V3_S0_HDD_F
PP3V3_S0_IMVP6_3V3
PP3V3_S0_LCD_F
PP3V3_S0_MCPREG_VREF3
PP3V3_S0_MCP_DAC
PP3V3_S0_MCP_VPLL
PP3V3_S3
PP3V3_S3_AP_AUX
PP3V3_S3_AP_AUX_F
PP3V3_S0_MIC_F
PP3V3_S5
PP3V3_S5_AVREF_SMC
PP3V3_S5_MCP
PP3V3_S5_SMC_AVCC
PP3V42G3H_SW
PP3V42_G3H
PP3V42_G3H_IPD_F
PP3V42_G3H_SMCUSBMUX_R
PP5V_S0
PP5V_S0_IMVP6_VDD
PP5V_S0_KBDLED_F
PP5V_S0_MCPREG_VCC
PP5V_S3
PP5V_S3_CAMERA_F
PP5V_S3_MCPREG_LDO
PP5V_S3_TOPCASE_F
PP5V_S3_USB2_EXTA
PP5V_S3_USB2_EXTA_F
PPBUS_G3H
PPBUS_G3HRS5_VSENSE
PPBUS_R_G3H
PPBUS_S0_LCDBKLT_EN_DIV
PPBUS_S0_LCDBKLT_EN_L
PPBUS_S0_LCDBKLT_FUSED
PPDCIN_G3H
PPDCIN_G3H_R
PPMCPCORE_S0
PPVBATT_G3H_R
PPVBAT_G3H_CHGR_OUT
PPVBATT_G3H_R
PPVBAT_G3H_CHGR_OUT
PPVBAT_G3H_CHGR_REG
PPVBAT_G3H_CHRGR_REG_0
PPVBAT_G3H_CHRGR_REG_R
PPVCORE_S0_CPU
PPVDCIN_G3H_PRE
PPVDCIN_G3H_PRE2
PPVDCIN_G3H_PRE_0
PPVDCIN_G3H_PRE_R
PPVIN_S5_IMVP6_VIN
PPVOUT_S0_LCDBKLT
PPVOUT_S0_LCDBKLT_SW
7
NET_SPACING_TYPE=PWR 6 7
NET_SPACING_TYPE=PWR 7
NET_SPACING_TYPE=PWR 25 27 28 29
NET_SPACING_TYPE=PWR 25 27 28 29
NET_SPACING_TYPE=PWR
NET_SPACING_TYPE=PP1V5_MEM 6 7
NET_SPACING_TYPE=PP1V5_MEM 6 7
NET_SPACING_TYPE=PWR 6 35 61
NET_SPACING_TYPE=GND 21 23
30
30
SPACING_RULE_SET
WEIGHT
PWR
LAYER
*
=STANDARD
BUS2PWR_GND
0.228 MM
M96 Power and Ground Nets
SYNC_DATE=(MASTER)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
70
71
M96 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,ISL12,ISL13,BOTTOM
NO_TYPE,BGA_P1MM
MM
15.2
SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
DEFAULT
0.1 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
DEFAULT
=50_OHM_SE
0.200 MM
30 MM
0 MM
0 MM
BGA_P1MM
STANDARD
=DEFAULT
BGA_P1MM
=DEFAULT
BGA_P2MM
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
BGA_P1MM
BGA_P2MM
CLK_FSB
BGA_P1MM
BGA_P2MM
BGA_P3MM
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=DEFAULT
WEIGHT
TOP,BOTTOM
STANDARD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
CLK_LPC
BGA_P1MM
BGA_P2MM
CLK_PCI
BGA_P1MM
BGA_P2MM
CLK_PCIE
BGA_P1MM
BGA_P2MM
CLK_SLOW
BGA_P1MM
BGA_P2MM
DIFFPAIR NECK GAP
SPACING_RULE_SET
55_OHM_SE
BGA_P1MM
=DEFAULT
PHYSICAL_RULE_SET
MEM_50S
PHYSICAL_RULE_SET
BGA_P1MM
MEM_CLK
STANDARD
AREA_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
SPACING_RULE_SET
0.210 MM
LAYER
0.200 MM
55_OHM_SE
ISL2,ISL13
0.075 MM
0.075 MM
=STANDARD
=STANDARD
=STANDARD
55_OHM_SE
0.066 MM
0.066 MM
=STANDARD
=STANDARD
=STANDARD
1.5:1_SPACING
0.15 MM
2:1_SPACING
0.2 MM
FSB_DSTB
FSB_DSTB
BGA_P1MM
BGA_P3MM
2.5:1_SPACING
0.25 MM
3:1_SPACING
0.3 MM
4:1_SPACING
0.4 MM
4:1_SPACING
0.4 MM
2.28:1_SPACING
0.228 MM
1.1:1_SPACING
0.110 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
50_OHM_SE
TOP,BOTTOM
0.250 MM
0.200 MM
50_OHM_SE
ISL2,ISL13
0.085 MM
0.085 MM
=STANDARD
=STANDARD
=STANDARD
50_OHM_SE
0.066 MM
0.066 MM
=STANDARD
=STANDARD
=STANDARD
LAYER
ALLOW ROUTE
ON LAYER?
PHYSICAL_RULE_SET
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

40_OHM_SE
TOP,BOTTOM
0.350 MM
0.200 MM
40_OHM_SE
ISL2,ISL13
0.122 MM
0.122 MM
SPACING_RULE_SET
=STANDARD
=STANDARD
=STANDARD
WEIGHT
2X_DIELECTRIC
TOP,BOTTOM
LAYER
0.230 MM
3X_DIELECTRIC
TOP,BOTTOM
0.345 MM
4X_DIELECTRIC
TOP,BOTTOM
0.460 MM
5X_DIELECTRIC
TOP,BOTTOM
0.575 MM
2X_DIELECTRIC
ISL2,ISL13
0.110 MM
3X_DIELECTRIC
ISL2,ISL13
0.165 MM
4X_DIELECTRIC
ISL2,ISL13
0.220 MM
5X_DIELECTRIC
ISL2,ISL13
0.275 MM
2X_DIELECTRIC
0.120 MM
3X_DIELECTRIC
0.180 MM
4X_DIELECTRIC
0.240 MM
5X_DIELECTRIC
0.300 MM
WEIGHT
*
40_OHM_SE
LAYER
ALLOW ROUTE
ON LAYER?
0.110 MM
0.110 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

27P4_OHM_SE
TOP,BOTTOM
0.215 MM
0.200 MM
27P4_OHM_SE
0.215 MM
0.215 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
70_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
70_OHM_DIFF
ISL2,ISL4,ISL5,ISL10,ISL11,ISL13
0.132 MM
0.132 MM
0.200 MM
0.200 MM
70_OHM_DIFF
TOP,BOTTOM
0.180 MM
0.180 MM
0.150 MM
0.150 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

90_OHM_DIFF
=STANDARD
=STANDARD
90_OHM_DIFF
0.085 MM
90_OHM_DIFF
TOP,BOTTOM
0.205 MM
=STANDARD
=STANDARD
=STANDARD
0.085 MM
0.250 MM
0.250 MM
0.200 MM
0.160 MM
0.160 MM
SPACING_RULE_SET
LAYER
GND
=STANDARD
PP1V5_MEM
=STANDARD
WEIGHT
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

100_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
0.065 MM
0.065 MM
=STANDARD
0.280 MM
0.280 MM
100_OHM_DIFF
TOP,BOTTOM
0.179 MM
0.179 MM
0.200 MM
0.200 MM
SPACING_RULE_SET
LAYER
GND_P2MM
0.2 MM
1000
PWR_P2MM
0.2 MM
1000
WEIGHT
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
100_OHM_DIFF_HDD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
MCP_STATIC
100_OHM_DIFF_HDD
0.065 MM
0.065 MM
0.280 MM
0.280 MM
100_OHM_DIFF_HDD
TOP,BOTTOM
0.179 MM
0.179 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
40_OHM_SE_MEM
TOP,BOTTOM
0.170 MM
0.110 MM
10 MM
40_OHM_SE_MEM
ISL2,ISL13
0.122 MM
0.066 MM
170 MM
=STANDARD
=STANDARD
40_OHM_SE_MEM
0.110 MM
0.066 MM
170 MM
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1:1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
M96 RULE DEFINITIONS
SYNC_MASTER=M97

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7631
2.3.0
OF
71
71

Apple Macbook Air A1304 (MLB M96)

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Apple Macbook Air A1304 (MLB M96)

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8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

System Block Diagram

Power Block Diagram

Acoustic Cap BOM Config Tables

Functional Test and No-Tests

SIGNAL ALIAS /RESET

CPU Power & Ground

CPU Decoupling & VID

eXtended Debug Port (XDP)

MCP CPU Interface

MCP Memory Interface

MCP Memory Misc

MCP PCIe Interfaces

MCP Ethernet & Graphics

MCP PCI & LPC

MCP SATA & USB

MCP HDA & MISC

MCP Power & Ground

MCP Standard Decoupling

MCP Graphics Support

FSB/DDR3 Vref Margining

DDR3 DRAM Channel A (0-31)

DDR3 DRAM Channel A (32-63)

DDR3 DRAM Channel B (0-31)

DDR3 DRAM Channel B (32-63)

Memory Active Termination

Wireless M93 Connector

M97 SMBUS CONNECTIONS

Sudden Motion Sensor (SMS)

DC-In & Battery Connectors

IMVP6 CPU VCore Regulator

MCP CORE REGULATOR

1.8V LDO Supply

1V05 S5 Power Supply

5V / 3.3V Power Supply

PBUS Supply/Battery Charger

LVDS,Camera Conn. and ALS Conn.

LED Backlight Driver

LCD Backlight Support

Additional CPU/GPU Decoupling

M96 Power and Ground Nets

M96 RULE DEFINITIONS

Hatch and Audio Connectors

USB EXTERNAL CONNECTORS

LPC+SPI Debug Connector

DIMENSIONS ARE IN MILLIMETERS

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

MINI XDP CONN

DDR3 - Dual Channel

CPU/MCP T-Diode Thermal Sensor

Local TEMP near power supplies

Local TEMP near Air Vent

Local TEMP near Front Edge

LVDS Int Disp

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

M96 POWER SYSTEM ARCHITECTURE

(200 mA MAX CURRENT)

(25 A MAX CURRENT)