DESIGN AND SIMULATION OF 8 BIT

MICROPROCESSOR USING VHDL

This project deals with the design and simulation of 8 bit microprocessor using VHDL for general
computation purpose.
The top level architecture iSs modeled with five components (ALU, RAM, PC (Program Counter),
IR (Instruction Decoder Register). TIM (Timing and Control Unit). The PC has the address of instruction.
After the instruction fetching, the IR decodes the instruction as opcode and data. Depending upon the
opcode the TIM unit generate the control signals. The corresponding operation is performed in ALU and
RAM as per the instruction.
The functionality of the processor is tested with various programs and simulations. The hardware
equivalent code for microprocessor is developed in VHDL. The simulation is performed in the EDA
(Electronic Design Automation) Tool Active VHDL.

8
Sbus-alu-0
Sbus-RAMProg

Sbus-pc0

PC-bus

Load-pc

Inc-pc

PC

RAM

Load-mdr

IR

Load-mar
Load-Ir

CS
r-nw

Sbus-pc-1
O

OP

TIM
Load-Acc
ALU-acc

ACC

ALU-add

Sbus-ir-0

ALU-sub

ALU

ALU-and
ALU-or
HLT

Zflag

Zflag

Sbus-alu-0

Cloc
Rese

Figure 8 bit Microprocessor simplified block diagram