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5 4 3 2 1 MS-7548 Ver: 10 (Aspen) Title Page MSI Cover Sheet 1
5
4
3
2
1
MS-7548 Ver: 10
(Aspen)
Title
Page
MSI
Cover Sheet
1
D
D
CPU:
Block Diagram
2
AMD M2 Athlon 64/Athlon 64 FX AM2R2
GPIO Configuration
3
Clock Distribution
4
System Chipset:
Power Deliver Chart
5
AMD/ATI RS780
AMD AMr2 940
6 ~ 9
AMD/ATI SB700
FIRST LOGICAL DDR DIMM
10
On Board Chipset:
SECOND LOGICAL DDR DIMM
11
Winbond Super I/O -- W83202G-C
LAN -- RTL8111C/D
HD Codec -- ALC888S
BIOS -- SPI ROM 8M
DDR Terminatior
12
AMD/ATI RS780
13
~ 17
AMD/ATI SB700
18
~ 22
1394 -- JMB381
C
C
PCI EXPRESS X16 & X 1 SLOT
23
Main Memory:
Clock-Gen Realtek RTM880T794
24
DDR II X 4 (Max 16GB)
USB
connectors
25
Azalia Codec-ALC888S
26
Expansion Slots:
VGA CONN
27
PCI-E X 16 *1
PCI-E X 1 *3
DVI
CONNECTOR
28
LAN
- Realtek 8111C
29
1394 Controller - JMB381
30
Clock Generator:
LPC-W83202G-C / FDD
31
Controller--Realtek RTM880T794
FAN
32
PWM:
VRM--Intersil ISL6323
33
B
B
Controller -- Intersil ISL6323
VCC_DDR & VCC1_1 NB
34
ACPI by UPI
35
ATX/Front Panel/KB/EMI
36
BOM - Option Parts
37
POWER OK MAP
38
RESET MAP
39
History
40
A
A
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7548
MS-7548
MS-7548
MSI
MSI
MSI
Size
Size
Size
Document Description
Document Description
Document Description
Rev
Rev
Rev
Custom
Custom
Custom
10
10
10
Cover Sheet
Cover Sheet
Cover Sheet
Date:
Date:
Date:
Wednesday, October 01, 2008
Wednesday, October 01, 2008
Wednesday, October 01, 2008
Sheet
Sheet
Sheet
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1
1
of
of
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40
40
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4

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1

D

C

5 4 3 2 1 D C B A D C Project RS-780 BLOCK DIAGRAM DDRII

B

A

D

C

5 4 3 2 1 D C B A D C Project RS-780 BLOCK DIAGRAM DDRII

Project RS-780 BLOCK DIAGRAM

DDRII 400,533,667,800 UNBUFFERED UNBUFFERED DDRII DIMM1 DDRII DIMM3 128bit DDRII 400,533,667,800 UNBUFFERED
DDRII 400,533,667,800
UNBUFFERED
UNBUFFERED
DDRII DIMM1
DDRII DIMM3
128bit
DDRII 400,533,667,800
UNBUFFERED
UNBUFFERED
DDRII DIMM2
DDRII DIMM4
128bit
DDRII FIRST LOGICAL DIMM
DDRII SECOND LOGICAL DIMM
AMD AM2/AM2g2 AM2 SOCKET HyperTransport LINK 16x16 2.6GHZ(HT3) DVI CON TMDS ATI NB - RS780
AMD
AM2/AM2g2
AM2 SOCKET
HyperTransport LINK
16x16 2.6GHZ(HT3)
DVI CON
TMDS
ATI NB - RS780
D-SUB
RGB
HyperTransport LINK0 CPU I/F
1 16X PCIE VIDEO I/F
1 4X PCIE I/F WITH SB
PCIE GFX x16
PCIE x16
2 1X PCIE I/F
5X1 PCIE INTERFACE
JMB381
Realtek
PCIE x1 SLOT1
IEEE1394
8111C/8111D
|
A-LINK
SLOT3
4X PCIE
HD AUDIO HDR
USB-5
USB-4
USB-3
USB-2
USB-1
USB-0
ATI SB - SB700
REAR
REAR
REAR
REAR
Front
Front
USB 2.0
LAN
LAN
1394
1394
AZALIA
USB2.0 (12)
AZALIA CODEC
SATA2 (6 PORTS)
USB-11
USB-10
USB-9
USB-8
USB-7
USB-6
AZALIA
Front
Front
Front
Front
Front
Front
HD AUDIO 1.0
ACPI 1.1
SERIAL ATA 2.0
SATA#0
SATA#1
SATA#2
SATA#3
SATA#4
SATA#5
SPI I/F
PCI/PCI BRIDGE
SPI Bus
SPI ROM 8M
CPU CORE POWER
NB CORE POWER
ISL6323
OUT
LPC BUS
IN

CPU VLDT Power

RS780 CORE POWER PCIE & SB POWER DUAL POWER

DDR2 DRAM POWER

ATX CON

Winbond SIO

W83202G-C

FLOPPY

KBD

MOUSE

MSI MSI MSI
MSI
MSI
MSI

40

40

40

10

10 10

B

A

ACPI CONTROLLER

uPI

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-7548

MS-7548

MS-7548

Size

Size

Size

Custom

Custom

Custom

Document Description

Document Description

Document Description

Block Diagram

Block Diagram

Block Diagram

Rev

Rev

Rev

5

4

3

2

1

Date:

Date:

Date:

Wednesday, October 01, 2008

Wednesday, October 01, 2008

Wednesday, October 01, 2008

Sheet

Sheet

Sheet

2 2

2

of

of

of

D

C

D C B A D C B A

B

A

D

C

D C B A D C B A

B

A

5 4
5
4
MSI MSI MSI Size Size Size C C C Date: Date: Date:
MSI
MSI
MSI
Size
Size
Size
C
C
C
Date:
Date:
Date:

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-7548

MS-7548

MS-7548

Document Description

Document Description

Document Description

GPIO Configuration

GPIO Configuration

GPIO Configuration

Rev

Rev

Rev

10

10 10

Wednesday, October 01, 2008

Wednesday, October 01, 2008

Wednesday, October 01, 2008

Sheet

Sheet

Sheet

3 3

3

of

of

of

40

40

40

3

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1

5 4 3
5
4
3
2 1
2
1
5 4 3 2 1 DIMM3 DIMM4 D D CPU_HT_CLK DIMM1 DIMM2 PCI CLK0 NB_HT_CLK
5
4
3
2
1
DIMM3
DIMM4
D
D
CPU_HT_CLK
DIMM1
DIMM2
PCI CLK0
NB_HT_CLK
33MHZ
PCI CLK1
25M_48M_66M_OSC
33MHZ
AMD/ATI SB
PCI CLK2
SB700
33MHZ
PCI CLK3
AMD/ATI NB
HT REFCLK
100MHz DIFF RS780
NB_DISP_CLK
33MHZ
RS780
AM2/AM2g2 CPU
1 PAIR CPU CLK
200MHZ
PCI CLK4
AM2 SOCKET
SUPER IO W83202G-C
33MHZ
NB-OSCIN
33MHz
GPP_CLK3
14.318MHZ
PCIE_RCLK/
NB ALINK PCIE CLK
PCI CLK5
NB_LNK_CLK
C
C
100MHZ
33MHZ
SB ALINK PCIE CLK
100MHZ
LPC_CLK0
EXTERNAL
33MHZ
CLK GEN.
NB GFX PCIE CLK
100MHZ
LPC CLK1
NB GPP PCIE CLK
100MHZ (RX780)
33MHZ
PCIE GFX CLK
SLT_GFX_CLK
100MHZ
PCIE GFX SLOT 1 - 16 LANES
SB_BITCLK
HD AUDIO
PCIE GPP CLK
GPP_CLK0
48MHZ
ALC 888S
100MHZ
PCIE GPP SLOT 1 - 3 LANE
25MHz
LAN
PCIE GPP CLK
25MHZ
GPP_CLK1
100MHZ
PCIE IEEE1394
OSC
INPUT
PCIE GPP CLK
GPP_CLK2
100MHZ
PCIE GBE
B
B
USB CLK
USB_CLK
48MHZ
SIO CLK
48MHZ
25MHz SATA
32.768KHz
14.31818MHz
External clock mode
A
A
Internal clock mode
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7548
MS-7548
MS-7548
MSI
MSI
MSI
Size
Size
Size
Document Description
Document Description
Document Description
Rev
Rev
Rev
Custom
Custom
Custom
10
10
10
Clock Distribution
Clock Distribution
Clock Distribution
Date:
Date:
Date:
Wednesday, October 01, 2008
Wednesday, October 01, 2008
Wednesday, October 01, 2008
Sheet
Sheet
Sheet
4
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4
of
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40
40
40
5
4
3
2
1
3 PAIR MEM CLK
3
PAIR MEM CLK
3
PAIR MEM CLK
3
PAIR MEM CLK
25MHz
5 4 3 2 1 Power Deliver Chart AMD AM2r2 CPU VDDA25 (S0, S1) 2.5V
5
4
3
2
1
Power Deliver Chart
AMD AM2r2 CPU
VDDA25 (S0, S1)
2.5V Shunt
VDDA 2.5V
0.2A
Regulator
VDDCORE
110A
0.8-1.55V
VRM SW
VCCP (S0, S1) / VCC_NB (S0, S1)
CPU
REGUALTOR
ATX P/S WITH 1A STBY CURRENT
D
PW
D
VCC_DDR (S0, S1, S3)
5VSB
5V
3.3V
12V
-12V
12V
DDR2 MEM I/F
VDD MEM 1.8V
10A
VTT_DDR (S0, S1, S3)
+/-5%
+/-5%
+/-5%
+/-5%
+/-5%
+/-5%
VTT MEM 0.9V
2A
DDRII DIMMX4
VLDT 1.2V
0.5A
VDD MEM
12A
5VDIMM Linear
1.8V VDD SW
VTT_DDR
2A
REGULATOR
REGULATOR
NB_VCC1P1 (S0, S1)
NB RS780
VDDHT/RX 1.1V
1.2A
VDDHTTX 1.2V
0.5A
VCC1_2 (S0, S1)
1.2V VCC SW
REGULATOR
VDDPCIE 1.1V
2.5A
NB CORE VDDC
10A
1.1V
VDDA18PCIEPLL 1.8V
0.12A
+1.8V_S0 (S0, S1)
1.8V VCC Linear
REGULATOR
VDDA18PCIE 1.8V
0.9A
PLLs 1.8V
0.1A
VDD18/VDD18_MEM
0.025A
1.8V
VDD_MEM 1.8V/1.5V
0.5A
AVDD 3.3V
0.135A
C
C
SB700
X4 PCI-E
0.8A
VCC3_SB Linear
REGULATOR
ATA I/O
0.5A
ATA PLL
0.01A
VCC3_SB (S0, S1, S3, S5)
PCI-E PVDD
80mA
SB CORE
0.6A
CLOCK
+1.2VSB (S0, S1)
1.2V_SB Linear
1.2V S5 PW
REGULATOR
0.22A
VCC3_SB (S0, S1, S3, S5)
3.3V S5 PW
0.01A
USB CORE I/O
0.2A
VCC3 (S0, S1)
3.3V I/O
0.45A
+5VA Linear
REGULATOR
B
B
AUDIO CODEC
5VDUAL Linear
3.3V CORE
REGULATOR
0.1A
+5VA (S0, S1)
5V ANALOG
0.1A
SUPER I/O
VCC3_SB (S0, S1, S3, S5)
+3.3VDUAL (S3)
0.01A
+3.3V (S0, S1)
0.01A
+5V (S0, S1)
0.1A
X1 PCIE per
X16 PCIE per
USB X8 FR
USB X4 RL
2XPS/2
ENTHENET
IEEE-1394 x1
3.3V
3.0A
3.3V
3.0A
VDD
VDD
5VDual
3.3V (S3)
0.1A
3.3V (S0, S1)
0.1A
A
A
12V
0.5A
12V
5.5A
5VDual
5VDual
0.5A
3.3V (S0, S1)
0.5A
12V (S0, S1) 1.1A
3.3Vaux
0.1A
3.3VDual 0.1A
4.0A
2.0A
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7548
MS-7548
MS-7548
MSI
MSI
MSI
Size
Size
Size
Document Description
Document Description
Document Description
Rev
Rev
Rev
C
C
C
10
10
10
Power Deliver Chart
Power Deliver Chart
Power Deliver Chart
Date:
Date:
Date:
Wednesday, October 01, 2008
Wednesday, October 01, 2008
Wednesday, October 01, 2008
Sheet
Sheet
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5 4 3 2 1 HT_CADIN_H[15 0] 13 HT_CADIN_H[15 0] 33 VID5 HT_CADIN_L[15 0] VDDA_25
5
4
3
2
1
HT_CADIN_H[15 0]
13
HT_CADIN_H[15 0]
33
VID5
HT_CADIN_L[15 0]
VDDA_25
VDDA25
13
HT_CADIN_L[15 0]
33
VID4
33
VID3/SVC
HT_CADOUT_H[15 0]
13
HT_CADOUT_H[15 0]
33
VID2/SVD
33
VID1/SEL
HT_CADOUT_L[15 0]
47nH/300mA/8
47nH/300mA/8
13
HT_CADOUT_L[15 0]
33
VID0/VFIXEN
2
1
L1
L1
D
D
VDDA25
VCC_DDR
VCC_DDR
C133
C133
C121
C121
C125
C125
C115
C115
R177
R177
R163
R163
R164
R164
CPU1D
CPU1D
24
CPU_CLK
C0.22u16X
C0.22u16X
C3300p50X0402
C3300p50X0402
MISC
MISC
1KR1%0402
1KR1%0402
C3900P25X
C3900P25X
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
C10
H22
VDDA1
KEY/VSS1
R169
R169
D10
AE9
X_300/4
X_300/4
1KR/4
1KR/4
VDDA2
KEY/VSS2
169R1%
169R1%
C137
C137
CPUCLKIN
A8
F2
CPU_PLATFORM_TYPE
TP19TP19
CLKIN_H
PLATFORM_TYPE
CPU1A
CPU1A
CPUCLKIN#
B8
G5
CPU_CORE_TYPE
R178
R178
300/4
300/4
24
CPU_CLK#
CLKIN_L
CORE_TYPE
C3900P25X
C3900P25X
LDT_PWRGD
C9
D2
VID5
HYPERTRANSPORT
HYPERTRANSPORT
18
LDT_PWRGD
PWROK
VID(5)
VCC_DDR
N6
AD5
LDT_STOP#
D8
D1
VID4
13
HT_CLKIN_H1
L0_CLKIN_H(1)
L0_CLKOUT_H(1)
HT_CLKOUT_H1
13
15,18
LDT_STOP#
LDTSTOP_L
VID(4)
P6
AD4
LDT_RST#
C7
C1
VID3/SVC
13
HT_CLKIN_L1
L0_CLKIN_L(1)
L0_CLKOUT_L(1)
HT_CLKOUT_L1
13
15,18
LDT_RST#
RESET_L
SVC/VID(3)
N3
AD1
R213
R213
R233
R233
E3
VID2/SVD
13
HT_CLKIN_H0
L0_CLKIN_H(0)
L0_CLKOUT_H(0)
HT_CLKOUT_H0
13
SVD/VID(2)
X_1KR1%0402
X_1KR1%0402
N2
AC1
E2
VID1/SEL
13
HT_CLKIN_L0
L0_CLKIN_L(0)
L0_CLKOUT_L(0)
HT_CLKOUT_L0
13
PVIEN/VID(1)
R232
R232
1KR1%0402
1KR1%0402
CPU_PRESENT_L
AL3
E1
VID0/VFIXEN
VCC_DDR
CPU_PRESENT_L
VID(0)
V4
Y6
390R0402
390R0402
13
HT_CTLIN_H1
L0_CTLIN_H(1)
L0_CTLOUT_H(1)
HT_CTLOUT_H1
13
V5
W6
THERM_SIC
AL6
AG9
13
HT_CTLIN_L1
L0_CTLIN_L(1)
L0_CTLOUT_L(1)
HT_CTLOUT_L1
13
SIC
THERMDC
THERMDC_CPU
31
U1
W2
THERM_SID
AK6
AG8
R108
R108
13
HT_CTLIN_H0
L0_CTLIN_H(0)
L0_CTLOUT_H(0)
HT_CTLOUT_H0
13
SID
THERMDA
THERMDA_CPU
31
V1
W3
1KR1%0402
1KR1%0402
R215
R215
ALERT_L
AL4
AK7
CPU_THRIP_L#
X_300/4
X_300/4
13
HT_CTLIN_L0
VCC_DDR
L0_CTLIN_L(0)
L0_CTLOUT_L(0)
HT_CTLOUT_L0
13
ALERT_L
THERMTRIP_L
1KR1%0402
1KR1%0402
R222
R222
CPU_SA0
AK4
AL7
CPU_HOT
SA0
PROCHOT_L
HT_CADIN_H15
U6
Y5
HT_CADOUT_H15
L0_CADIN_H(15)
L0_CADOUT_H(15)
HT_CADIN_L15
V6
Y4
HT_CADOUT_L15
CPU_TDI
AL10
AK10
CPU_TDO
L0_CADIN_L(15)
L0_CADOUT_L(15)
TDI
TDO
HT_CADIN_H14
T4
AB6
HT_CADOUT_H14
CPU_TRST_L
AJ10
L0_CADIN_H(14)
L0_CADOUT_H(14)
TRST_L
HT_CADIN_L14
T5
AA6
HT_CADOUT_L14
CPU_TCK
AH10
L0_CADIN_L(14)
L0_CADOUT_L(14)
TCK
HT_CADIN_H13
R6
AB5
HT_CADOUT_H13
CPU_TMS
AL9
R214
R214
300/4
300/4
VCC_DDR
L0_CADIN_H(13)
L0_CADOUT_H(13)
TMS
HT_CADIN_L13
T6
AB4
HT_CADOUT_L13
L0_CADIN_L(13)
L0_CADOUT_L(13)
HT_CADIN_H12
P4
AD6
HT_CADOUT_H12
CPU_DBREQ_L
A5
B6
CPU_DBRDY
L0_CADIN_H(12)
L0_CADOUT_H(12)
DBREQ_L
DBRDY
CPU_HOT
18
HT_CADIN_L12
P5
AC6
HT_CADOUT_L12
L0_CADIN_L(12)
L0_CADOUT_L(12)
HT_CADIN_H11
M4
AF6
HT_CADOUT_H11
COREFB_H
G2
AK11
CPU_VDDIOFB_H
L0_CADIN_H(11)
L0_CADOUT_H(11)
33
COREFB_H
VDD_FB_H
VDDIO_FB_H
CPU_VDDIOFB_H
34
VCC_DDR
HT_CADIN_L11
M5
AE6
HT_CADOUT_L11
COREFB_L
G1
AL11
CPU_VDDIOFB_L
L0_CADIN_L(11)
L0_CADOUT_L(11)
33
COREFB_L
C
VDD_FB_L
VDDIO_FB_L
CPU_VDDIOFB_L
34
C
HT_CADIN_H10
L6
AF5
HT_CADOUT_H10
G4
L0_CADIN_H(10)
L0_CADOUT_H(10)
VDDNB_FB_H
HT_CADIN_L10
M6
AF4
HT_CADOUT_L10
G3
L0_CADIN_L(10)
L0_CADOUT_L(10)
VDDNB_FB_L
HT_CADIN_H9
K4
AH6
HT_CADOUT_H9
L0_CADIN_H(9)
L0_CADOUT_H(9)
CPU_VDDNB_FB_H
33
VCC1_2
HT_CADIN_L9
AG6
HT_CADOUT_L9
R217
R217
TP17TP17
K5
CPU_VTT_SENSE
E12
F1
CPU_PSI_L
L0_CADIN_L(9)
L0_CADOUT_L(9)
VTT_SENSE
PSI_L
TP21TP21
CPU_VDDNB_FB_L
33
CPU_M_VREF
HT_CADIN_H8
J6
AH5
HT_CADOUT_H8
39.2R1%
39.2R1%
L0_CADIN_H(8)
L0_CADOUT_H(8)
HT_CADIN_L8
K6
AH4
HT_CADOUT_L8
F12
V8
HTREF1
R220
R220
44.2R1%
44.2R1%
L0_CADIN_L(8)
L0_CADOUT_L(8)
M_VREF
HTREF1
CPU_STRAP_HI_E11
AH11
V7
HTREF0
R221
R221
44.2R1%
44.2R1%
M_ZN
HTREF0
HT_CADIN_H7
U3
Y1
HT_CADOUT_H7
CPU_STRAP_LO_F11
AJ11
L0_CADIN_H(7)
L0_CADOUT_H(7)
M_ZP
HT_CADIN_L7
U2
W1
HT_CADOUT_L7
L0_CADIN_L(7)
L0_CADOUT_L(7)
HT_CADIN_H6
R1
AA2
HT_CADOUT_H6
510R
510R
R167
R167
CPU_TEST25_H
A10
C11
CPU_TEST29_H
C281
C281
C280
C280
VCC_DDR
L0_CADIN_H(6)
L0_CADOUT_H(6)
TEST25_H
TEST29_H
HT_CADIN_L6
T1
AA3
HT_CADOUT_L6
R218
R218
510R
510R
R166
R166
CPU_TEST25_L
B10
D11
CPU_TEST29_L
C1000P50X0402
C1000P50X0402
C1000P50X0402
C1000P50X0402
L0_CADIN_L(6)
L0_CADOUT_L(6)
TEST25_L
TEST29_L
HT_CADIN_H5
R3
AB1
HT_CADOUT_H5
R171
R171
300/4
300/4
39.2R1%
39.2R1%
F10
L0_CADIN_H(5)
L0_CADOUT_H(5)
TEST19
HT_CADIN_L5
R2
AA1
HT_CADOUT_L5
R170
R170
300/4
300/4
E9
R168
R168
L0_CADIN_L(5)
L0_CADOUT_L(5)
TEST18
HT_CADIN_H4
N1
AC2
HT_CADOUT_H4
AJ7
80.6R1%
80.6R1%
L0_CADIN_H(4)
L0_CADOUT_H(4)
TEST13
HT_CADIN_L4
P1
AC3
HT_CADOUT_L4
F6
L0_CADIN_L(4)
L0_CADOUT_L(4)
TEST9
HT_CADIN_H3
L1
AE2
HT_CADOUT_H3
L0_CADIN_H(3)
L0_CADOUT_H(3)
HT_CADIN_L3
M1
AE3
HT_CADOUT_L3
D6
AK8
L0_CADIN_L(3)
L0_CADOUT_L(3)
TP18TP18
TEST17
TEST24
TP27TP27
HT_CADIN_H2
L3
AF1
HT_CADOUT_H2
E7
AH8
L0_CADIN_H(2)
L0_CADOUT_H(2)
TP20TP20
TEST16
TEST23
TP24TP24
HT_CADIN_L2
L2
AE1
HT_CADOUT_L2
F8
AJ9
L0_CADIN_L(2)
L0_CADOUT_L(2)
TP22TP22
TEST15
TEST22
VCC_DDR
VCC_DDR
HT_CADIN_H1
J1
AG2
HT_CADOUT_H1
C5
AL8
L0_CADIN_H(1)
L0_CADOUT_H(1)
TP16TP16
TEST14
TEST21
HT_CADIN_L1
K1
AG3
HT_CADOUT_L1
AH9
AJ8
L0_CADIN_L(1)
L0_CADOUT_L(1)
TP23TP23
TEST12
TEST20
TP25TP25
HT_CADIN_H0
J3
AH1
HT_CADOUT_H0
R226
R226
R225
R225
L0_CADIN_H(0)
L0_CADOUT_H(0)
HT_CADIN_L0
J2
AG1
HT_CADOUT_L0
E5
J10
300/4
300/4
300/4
300/4
R234
R234
L0_CADIN_L(0)
L0_CADOUT_L(0)
TEST7
TEST28_H
VCC_DDR
AJ5
H9
R224
R224
TEST6
TEST28_L
M2_1
M2_1
TP26TP26
AK9
300/4
300/4
TEST27
AK5
R223
R223
300/4
300/4
4.7KR0402
4.7KR0402
TEST26
AH7
G7
TEST3
TEST10
AJ6
D4
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
TEST2
TEST8
Q36
Q36
CPU_THRIP_L#
CPU_THRIP#
20
VCC_DDR
B
N12-9400050-L06
B
15u
R165
R165
VCC_DDR
XDP1
XDP1
1
2
300/4
300/4
3
4
VCC_DDR
CPU_M_VREF
LDT_RST#
5
6
VCC3
R159
R159
CPU_DBREQ_L
7
8
VCC3
15R1%0402-RH
15R1%0402-RH
CPU_DBRDY
9
10
CPU_TCK
11
12
CPU_TMS
13
14
VCC_DDR
CPU_TDI
15
16
X_D1x2-BK
X_D1x2-BK
R131
R131
CPU_TRST_L
R276
R276
17
18
X_4.7KR0402
X_4.7KR0402
R162
R162
C119
C119
CPU_TDO
19
20
X_220/4
X_220/4
21
22
JCPU_RST1
JCPU_RST1
V
V
R115
R115
15R1%0402-RH
15R1%0402-RH
C127
C127
C1000P16X/X7R/6
C1000P16X/X7R/6
23
24
6
1
LDT_RST#
X_10KR0402
X_10KR0402
26
G
G
KEY
KEY
Q16
Q16
C356
C356
X_N-MMBT3904_NL_SOT23
X_N-MMBT3904_NL_SOT23
0.1uF/16VX7R/6
0.1uF/16VX7R/6
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
VCC_DDR
LDT_PWRGD
E
C
PWROK_PWM
X_HDR_K8_HDT_B
X_HDR_K8_HDT_B
FOR AMD HT DEBUG
18
LDT_PWRGD
PWROK_PWM
33
RN3
RN3
U13A
U13A
1
2
Solder side
X_NC7WZ07_SC70-6
X_NC7WZ07_SC70-6
3
4
LDT_STOP#
R125
R125
0R0402
0R0402
LDT_PWRGD
5
6
15,20,35
SYS_PWRGD
7
8
LDT_RST#
8P4R-300R-RH
8P4R-300R-RH
A
A
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7548
MS-7548
MS-7548
MSI
MSI
MSI
Size
Size
Size
Document Description
Document Description
Document Description
Rev
Rev
Rev
Custom
Custom
Custom
K9 M2 HT I/F,CTRL&DEBUG
K9 M2 HT I/F,CTRL&DEBUG
K9 M2 HT I/F,CTRL&DEBUG
10
10
10
Date:
Date:
Date:
Wednesday, October 01, 2008
Wednesday, October 01, 2008
Wednesday, October 01, 2008
Sheet
Sheet
Sheet
6
6
6
of
of
of
40
40
40
5
4
3
2
1
B
52
12
   

5

4

3

2

1

 
   

10,11

MEM_MB_DQS_L[7 0]

 

10,11

MEM_MA_DQS_L[7 0]

 
 

10,11

MEM_MB_DQS_H[7 0]

 
 

10,11

MEM_MA_DQS_H[7 0]

 
 

10,11

MEM_MB_DM[7 0]

 

10,11

MEM_MA_DM[7 0]

 

D

 

CPU1B

CPU1B

D

   

CPU1C

CPU1C

 

10,12

10,12

10,12

10,12

10,12

10,12

MEM_MA0_CLK_H2

MEM_MA0_CLK_L2

MEM_MA0_CLK_H1

MEM_MA0_CLK_L1

MEM_MA0_CLK_H0

MEM_MA0_CLK_L0

 

MEM_MA0_CLK_H2

AG21

MEMORY INTERFACE A

MEMORY INTERFACE A

AE14

MEM_MA_DATA63

MEM_MA_DATA[63

0]

10,11

   
AG21 MEMORY INTERFACE A MEMORY INTERFACE A A E 1 4 MEM_MA_DATA63 MEM_MA_DATA[63 0] 10,11  

10,11

 

MEM_MA0_CLK_L2

AG20

MA0_CLK_H(2)

MA0_CLK_L(2)

MA0_CLK_H(1)

MA0_CLK_L(1)

MA0_CLK_H(0)

MA0_CLK_L(0)

MA0_CS_L(1)

MA0_CS_L(0)

MA_DATA(63)

MA_DATA(62)

MA_DATA(61)

MA_DATA(60)

MA_DATA(59)

MA_DATA(58)

MA_DATA(57)

MA_DATA(56)

MA_DATA(55)

AG14

MEM_MA_DATA62

 

10,12

10,12

10,12

10,12

10,12

10,12

MEM_MB0_CLK_H2

MEM_MB0_CLK_L2

MEM_MB0_CLK_H1

MEM_MB0_CLK_L1

MEM_MB0_CLK_H0

MEM_MB0_CLK_L0

MEM_MB0_CLK_H2

MEMORY INTERFACE B

MEMORY INTERFACE B

AJ19

AH13

MEM_MB_DATA63

 

MEM_MB_DATA[63

0]

 

MEM_MA0_CLK_H1

G19

AG16

MEM_MA_DATA61

MEM_MB0_CLK_L2

AK19

A18

A19

U31

U30

MB0_CLK_H(2)

MB0_CLK_L(2)

MB0_CLK_H(1)

MB0_CLK_L(1)

MB0_CLK_H(0)

MB0_CLK_L(0)

MB_DATA(63)

MB_DATA(62)

MB_DATA(61)

MB_DATA(60)

MB_DATA(59)

MB_DATA(58)

MB_DATA(57)

MB_DATA(56)

AL13

MEM_MB_DATA62

 
 

MEM_MA0_CLK_L1

H19

AD17

MEM_MA_DATA60

MEM_MB0_CLK_H1

AL15

MEM_MB_DATA61

 

MEM_MA0_CLK_H0

U27

AD13

MEM_MA_DATA59

MEM_MB0_CLK_L1

AJ15

MEM_MB_DATA60

 

MEM_MA0_CLK_L0

U26

AE13

MEM_MA_DATA58

MEM_MB0_CLK_H0

AF13

MEM_MB_DATA59

 

AG15

MEM_MA_DATA57

MEM_MB0_CLK_L0

AG13

MEM_MB_DATA58

10,12

10,12

MEM_MA0_CS_L1

MEM_MA0_CS_L0

 

MEM_MA0_CS_L1

AC25

AE16

MEM_MA_DATA56

AL14

MEM_MB_DATA57

 

MEM_MA0_CS_L0

AA24

AG17

MEM_MA_DATA55

10,12

10,12

MEM_MB0_CS_L1

MEM_MB0_CS_L0

MEM_MB0_CS_L1

AE30

AC31

MB0_CS_L(1)

AK15

MEM_MB_DATA56

 

AE18

MEM_MA_DATA54

MEM_MB0_CS_L0

AL16

MEM_MB_DATA55

 

10,12

MEM_MA0_ODT0

 

MEM_MA0_ODT0

AC28

MA0_ODT(0)

MA1_CLK_H(2)

MA1_CLK_L(2)

MA1_CLK_H(1)

MA1_CLK_L(1)

MA1_CLK_H(0)

MA1_CLK_L(0)

MA1_CS_L(1)

MA1_CS_L(0)

MA1_ODT(0)

MA_CAS_L

MA_DATA(54)

MA_DATA(53)

MA_DATA(52)

MA_DATA(51)

MA_DATA(50)

MA_DATA(49)

MA_DATA(48)

MA_DATA(47)

MA_DATA(46)

MA_DATA(45)

MA_DATA(44)

MA_DATA(43)

MA_DATA(42)

MA_DATA(41)

MA_DATA(40)

MA_DATA(39)

MA_DATA(38)

AD21

MEM_MA_DATA53

MB0_CS_L(0)

MB_DATA(55)

MB_DATA(54)

MB_DATA(53)

MB_DATA(52)

MB_DATA(51)

MB_DATA(50)

MB_DATA(49)

MB_DATA(48)

MB_DATA(47)

MB_DATA(46)

MB_DATA(45)

MB_DATA(44)

MB_DATA(43)

MB_DATA(42)

MB_DATA(41)

MB_DATA(40)

MB_DATA(39)

AL17

MEM_MB_DATA54

 
 

AG22

MEM_MA_DATA52

10,12

MEM_MB0_ODT0

MEM_MB0_ODT0

AD29

MB0_ODT(0)

AK21

MEM_MB_DATA53

 

11,12

MEM_MA1_CLK_H2

MEM_MA1_CLK_H2

AE20

AE17

MEM_MA_DATA51

AL21

MEM_MB_DATA52

MEM_MA1_CLK_L2

AE19

AF17

MEM_MA_DATA50

11,12

11,12

11,12

11,12

11,12

11,12

MEM_MB1_CLK_H2

MEM_MB1_CLK_L2

MEM_MB1_CLK_H1

MEM_MB1_CLK_L1

MEM_MB1_CLK_H0

MEM_MB1_CLK_L0

MEM_MB1_CLK_H2

AL19

AL18

C19

D19

W29

W28

MB1_CLK_H(2)

MB1_CLK_L(2)

MB1_CLK_H(1)

MB1_CLK_L(1)

MB1_CLK_H(0)

MB1_CLK_L(0)

AH15

MEM_MB_DATA51

11,12

11,12

MEM_MA1_CLK_L2

MEM_MA1_CLK_H1

 

MEM_MA1_CLK_H1

G20

AF21

MEM_MA_DATA49

MEM_MB1_CLK_L2

AJ16

MEM_MB_DATA50

MEM_MA1_CLK_L1

G21

AE21

MEM_MA_DATA48

MEM_MB1_CLK_H1

AH19

MEM_MB_DATA49

11,12

11,12

MEM_MA1_CLK_L1

MEM_MA1_CLK_H0

MEM_MA1_CLK_H0

V27

AF23

MEM_MA_DATA47

MEM_MB1_CLK_L1

AL20

MEM_MB_DATA48

MEM_MA1_CLK_L0

W27

AE23

MEM_MA_DATA46

MEM_MB1_CLK_H0

AJ22

MEM_MB_DATA47

11,12

MEM_MA1_CLK_L0

 

AJ26

MEM_MA_DATA45

MEM_MB1_CLK_L0

AL22

MEM_MB_DATA46

11,12

11,12

MEM_MA1_CS_L1

MEM_MA1_CS_L0

 

MEM_MA1_CS_L1

AD27

AG26

MEM_MA_DATA44

AL24

MEM_MB_DATA45

MEM_MA1_CS_L0

AA25

AE22

MEM_MA_DATA43

11,12

11,12

MEM_MB1_CS_L1

MEM_MB1_CS_L0

MEM_MB1_CS_L1

AE29

AB31

MB1_CS_L(1)

MB1_CS_L(0)

AK25

MEM_MB_DATA44

 

AG23

MEM_MA_DATA42

MEM_MB1_CS_L0

AJ21

MEM_MB_DATA43

11,12

MEM_MA1_ODT0

 

MEM_MA1_ODT0

AC27

AH25

MEM_MA_DATA41

AH21

MEM_MB_DATA42

 

AF25

MEM_MA_DATA40

11,12

MEM_MB1_ODT0

MEM_MB1_ODT0

AD31

MB1_ODT(0)

AH23

MEM_MB_DATA41

 

AJ28

MEM_MA_DATA39

AJ24

MEM_MB_DATA40

C

 

10,11,12

MEM_MA_CAS_L

MEM_MA_CAS_L

MEM_MA_WE_L

AB25

AB27

AJ29

AF29

MEM_MA_DATA38

MEM_MA_DATA37

   

MEM_MB_CAS_L

AC29

AL27

AK27

MEM_MB_DATA39

MEM_MB_DATA38

C

10,11,12

10,11,12

MEM_MA_WE_L

MEM_MA_RAS_L

 

MEM_MA_RAS_L

AA26

MA_WE_L

MA_RAS_L

MA_BANK(2)

MA_BANK(1)

MA_BANK(0)

MA_CKE(1)

MA_CKE(0)

MA_ADD(15)

MA_ADD(14)

MA_ADD(13)

MA_ADD(12)

MA_ADD(11)

MA_DATA(37)

MA_DATA(36)

MA_DATA(35)

MA_DATA(34)

MA_DATA(33)

MA_DATA(32)

MA_DATA(31)

MA_DATA(30)

MA_DATA(29)

MA_DATA(28)

MA_DATA(27)

MA_DATA(26)

MA_DATA(25)

MA_DATA(24)

MA_DATA(23)

AE26

MEM_MA_DATA36

 

10,11,12

10,11,12

10,11,12

MEM_MB_CAS_L

MEM_MB_WE_L

MEM_MB_RAS_L

MEM_MB_WE_L

AC30

AB29

MB_CAS_L

MB_WE_L

MB_RAS_L

MB_DATA(38)

MB_DATA(37)

MB_DATA(36)

MB_DATA(35)

MB_DATA(34)

MB_DATA(33)

MB_DATA(32)

MB_DATA(31)

MB_DATA(30)

MB_DATA(29)

MB_DATA(28)

MB_DATA(27)

MB_DATA(26)

MB_DATA(25)

MB_DATA(24)

AH31

MEM_MB_DATA37

 

AJ27

MEM_MA_DATA35

MEM_MB_RAS_L

AG30

MEM_MB_DATA36

10,11,12

10,11,12

10,11,12

MEM_MA_BANK2

MEM_MA_BANK1

MEM_MA_BANK0

 

MEM_MA_BANK2

N25

AH27

MEM_MA_DATA34

AL25

MEM_MB_DATA35

MEM_MA_BANK1

Y27

AG29

MEM_MA_DATA33

10,11,12

10,11,12

10,11,12

MEM_MB_BANK2

MEM_MB_BANK1

MEM_MB_BANK0

MEM_MB_BANK2

N31

AA31

AA28

MB_BANK(2)

MB_BANK(1)

MB_BANK(0)

AL26

MEM_MB_DATA34

MEM_MA_BANK0

AA27

AF27

MEM_MA_DATA32

MEM_MB_BANK1

AJ30

MEM_MB_DATA33

 

E29

MEM_MA_DATA31

MEM_MB_BANK0

AJ31

MEM_MB_DATA32

11,12

10,12

MEM_MA_CKE1

MEM_MA_CKE0

 

MEM_MA_CKE1

L27

E28

MEM_MA_DATA30

E31

MEM_MB_DATA31

MEM_MA_CKE0

M25

D27

MEM_MA_DATA29

 

11,12

10,12

MEM_MB_CKE1

MEM_MB_CKE0

MEM_MB_CKE1

M31

M29

MB_CKE(1)

MB_CKE(0)

E30

MEM_MB_DATA30

 

C27

MEM_MA_DATA28

MEM_MB_CKE0

B27

MEM_MB_DATA29

 

MEM_MA_ADD15

M27

G26

MEM_MA_DATA27

A27

MEM_MB_DATA28

MEM_MA_ADD14

N24

F27

MEM_MA_DATA26

 

MEM_MB_ADD15

N28

N29

AE31

N30

P29

MB_ADD(15)

MB_ADD(14)

MB_ADD(13)

MB_ADD(12)

F29

MEM_MB_DATA27

MEM_MA_ADD13

AC26

C28

MEM_MA_DATA25

MEM_MB_ADD14

F31

MEM_MB_DATA26

MEM_MA_ADD12 N26 E 2 7 MEM_MA_DATA24 MEM_MB_ADD13 A 2 9 MEM_MB_DATA25  

MEM_MA_ADD12

N26

E27

MEM_MA_DATA24

MEM_MB_ADD13

A29

MEM_MB_DATA25

 
MEM_MA_ADD12 N26 E 2 7 MEM_MA_DATA24 MEM_MB_ADD13 A 2 9 MEM_MB_DATA25  

MEM_MA_ADD11

MEM_MA_ADD10

P25

Y25

F25

E25

MEM_MA_DATA23

MEM_MA_DATA22

MEM_MB_ADD12

MEM_MB_ADD11

A28

A25

MEM_MB_DATA24

MEM_MB_DATA23

   

MEM_MA_ADD9

N27

MA_ADD(10)

MA_ADD(9)

MA_ADD(8)

MA_ADD(7)

MA_ADD(6)

MA_ADD(5)

MA_ADD(4)

MA_ADD(3)

MA_ADD(2)

MA_ADD(1)

MA_ADD(0)

MA_DQS_H(7)

MA_DQS_L(7)

MA_DATA(22)

MA_DATA(21)

MA_DATA(20)

MA_DATA(19)

MA_DATA(18)

MA_DATA(17)

MA_DATA(16)

MA_DATA(15)

MA_DATA(14)

MA_DATA(13)

MA_DATA(12)

MA_DATA(11)

MA_DATA(10)

MA_DATA(9)

E23

MEM_MA_DATA21

MEM_MB_ADD10

AA29

P31

R29

R28

R31

R30

T31

T29

U29

U28

AA30

MB_ADD(11)

MB_ADD(10)

MB_ADD(9)

MB_ADD(8)

MB_ADD(7)

MB_ADD(6)

MB_ADD(5)

MB_ADD(4)

MB_ADD(3)

MB_ADD(2)

MB_ADD(1)

MB_ADD(0)

MB_DATA(23)

MB_DATA(22)

MB_DATA(21)

MB_DATA(20)

MB_DATA(19)

MB_DATA(18)

MB_DATA(17)

MB_DATA(16)

MB_DATA(15)

MB_DATA(14)

MB_DATA(13)

MB_DATA(12)

MB_DATA(11)

MB_DATA(10)

A24

MEM_MB_DATA22

MEM_MA_ADD8

R24

D23

MEM_MA_DATA20

MEM_MB_ADD9

C22

MEM_MB_DATA21

MEM_MA_ADD7

P27

E26

MEM_MA_DATA19

MEM_MB_ADD8

D21

MEM_MB_DATA20

MEM_MA_ADD6

R25

C26

MEM_MA_DATA18

MEM_MB_ADD7

A26

MEM_MB_DATA19

MEM_MA_ADD5

R26

G23

MEM_MA_DATA17

MEM_MB_ADD6

B25

MEM_MB_DATA18

MEM_MA_ADD4

R27

F23

MEM_MA_DATA16

MEM_MB_ADD5

B23

MEM_MB_DATA17

MEM_MA_ADD3

T25

E22

MEM_MA_DATA15

MEM_MB_ADD4

A22

MEM_MB_DATA16

MEM_MA_ADD2

U25

E21

MEM_MA_DATA14

MEM_MB_ADD3

B21

MEM_MB_DATA15

10,11,12

MEM_MA_ADD[15 0]

 

MEM_MA_ADD1

T27

F17

MEM_MA_DATA13

MEM_MB_ADD2

A20

MEM_MB_DATA14

MEM_MA_ADD0

W24

G17

MEM_MA_DATA12

10,11,12

MEM_MB_ADD[15 0]

 

MEM_MB_ADD1

C16

MEM_MB_DATA13

 

G22

MEM_MA_DATA11

MEM_MB_ADD0

D15

MEM_MB_DATA12

 

MEM_MA_DQS_H7

AD15

F21

MEM_MA_DATA10

 

C21

MEM_MB_DATA11

MEM_MA_DQS_L7

AE15

G18

MEM_MA_DATA9

 

MEM_MB_DQS_H7

AK13

AJ13

MB_DQS_H(7)

A21

MEM_MB_DATA10

MEM_MA_DQS_H6

AG18

E17

MEM_MA_DATA8

MEM_MB_DQS_L7

A17

MEM_MB_DATA9

B

MEM_MA_DQS_L6

MEM_MA_DQS_H5

AG19

AG24

MA_DQS_H(6)

MA_DQS_L(6)

MA_DATA(8)

MA_DATA(7)

G16

E15

MEM_MA_DATA7

MEM_MA_DATA6

MEM_MB_DQS_H6

MEM_MB_DQS_L6

AK17

AJ17

MB_DQS_L(7)

MB_DQS_H(6)

MB_DATA(9)

MB_DATA(8)

A16

B15

MEM_MB_DATA8

MEM_MB_DATA7

B

MEM_MA_DQS_L5

AG25

MA_DQS_H(5)

MA_DQS_L(5)

MA_DQS_H(4)

MA_DQS_L(4)

MA_DQS_H(3)

MA_DQS_L(3)

MA_DQS_H(2)

MA_DQS_L(2)

MA_DATA(6)

MA_DATA(5)

MA_DATA(4)

MA_DATA(3)

MA_DATA(2)

MA_DATA(1)

MA_DATA(0)

G13

MEM_MA_DATA5

MEM_MB_DQS_H5

AK23

AL23

AL28

AL29

D31

C31

C24

C23

MB_DQS_L(6)

MB_DQS_H(5)

MB_DQS_L(5)

MB_DQS_H(4)

MB_DQS_L(4)

MB_DQS_H(3)

MB_DQS_L(3)

MB_DQS_H(2)

MB_DATA(7)

MB_DATA(6)

MB_DATA(5)

MB_DATA(4)

MB_DATA(3)

MB_DATA(2)

MB_DATA(1)

MB_DATA(0)

A14

MEM_MB_DATA6

MEM_MA_DQS_H4

AG27

H13

MEM_MA_DATA4

MEM_MB_DQS_L5

E13

MEM_MB_DATA5

MEM_MA_DQS_L4

AG28

H17

MEM_MA_DATA3

MEM_MB_DQS_H4

F13

MEM_MB_DATA4

MEM_MA_DQS_H3

D29

E16

MEM_MA_DATA2

MEM_MB_DQS_L4

C15

MEM_MB_DATA3

MEM_MA_DQS_L3

C29

E14

MEM_MA_DATA1

MEM_MB_DQS_H3

A15

MEM_MB_DATA2

MEM_MA_DQS_H2

C25

G14

MEM_MA_DATA0

MEM_MB_DQS_L3

A13

MEM_MB_DATA1

 

MEM_MA_DQS_L2

MEM_MA_DQS_H1

D25

E19

J28

MEM_MB_DQS_H2

MEM_MB_DQS_L2

D13

MEM_MB_DATA0

 

MEM_MA_DQS_L1

F19

MA_DQS_H(1)

MA_DQS_L(1)

MA_DQS_H(0)

MA_DQS_L(0)

MA_DQS_H(8)

MA_DQS_L(8)

J27

MEM_MB_DQS_H1

D17

C17

C14

C13

MB_DQS_L(2)

MB_DQS_H(1)

MB_DQS_L(1)

MB_DQS_H(0)

MB_DQS_L(0)

MB_DQS_H(8)

MB_DQS_L(8)

J31

 

MEM_MA_DQS_H0

F15

MEM_MB_DQS_L1

J30

MEM_MA_DQS_L0

G15

MA_DM(8)

J25

MEM_MB_DQS_H0

 

MEM_MA_DM7

AF15

K25

MEM_MB_DQS_L0

MB_DM(8)

J29

 

MEM_MA_DM6

MEM_MA_DM5

AF19

AJ25

MA_DM(7)

MA_DM(6)

MA_CHECK(7)

MA_CHECK(6)

J26

G28

MEM_MB_DM7

MEM_MB_DM6

AJ14

AH17

MB_DM(7)

MB_CHECK(7)

K29

K31

 

MEM_MA_DM4

AH29

MA_DM(5)

MA_DM(4)

MA_DM(3)

MA_DM(2)

MA_DM(1)

MA_CHECK(5)

MA_CHECK(4)

MA_CHECK(3)

MA_CHECK(2)

MA_CHECK(1)

G27

MEM_MB_DM5

AJ23

AK29

C30

A23

B17

MB_DM(6)

MB_DM(5)

MB_DM(4)

MB_DM(3)

MB_DM(2)

MB_CHECK(6)

MB_CHECK(5)

MB_CHECK(4)

MB_CHECK(3)

MB_CHECK(2)

G30

MEM_MA_DM3

B29

L24

MEM_MB_DM4

G29

MEM_MA_DM2

E24

K27

MEM_MB_DM3

L29

MEM_MA_DM1

E18

H29

MEM_MB_DM2

L28

MEM_MA_DM0

H15

H27

MEM_MB_DM1

H31

 

MA_DM(0)

MA_CHECK(0)

MEM_MB_DM0

B13

MB_DM(1)

MB_DM(0)

MB_CHECK(1)

MB_CHECK(0)

G31

A

 

A

 
MSI MSI MSI
MSI
MSI
MSI
 

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

 
 

MS-7548

MS-7548

MS-7548

 

Size

Size

Size

Custom

Custom

Custom

Document Description

Document Description

Document Description

K9 M2 DDR MEMORY I/F

K9 M2 DDR MEMORY I/F

K9 M2 DDR MEMORY I/F

Rev

Rev

Rev

10

10

10

 

Date:

Date:

Date:

Wednesday, October 01, 2008

Wednesday, October 01, 2008

Wednesday, October 01, 2008

 

Sheet

Sheet

Sheet

7

7

7

of

of

of

40

40

40

 

5

   

4

 

3

 

2

   

1

 
5 4 3 2 1 VDD_NB CPU1F CPU1F VCORE CPU1I CPU1I VCORE VCC1_2 VDD1 VDD1
5
4
3
2
1
VDD_NB
CPU1F
CPU1F
VCORE
CPU1I
CPU1I
VCORE
VCC1_2
VDD1
VDD1
CPU1G
CPU1G
CPU1H
CPU1H
A4
A3
VDDIO
VDDIO
VDDNB1
VSS1
A6
A7
VDD2
VDD3
VDD3
VLDT_RUN_B
VDD2
AJ4
H6
VDDNB2
VSS2
VLDT_A1
VLDT_B1
B5
A9
L14
AK20
AA20
N17
AJ3
H5
VDDNB3
VSS3
VDD1
VSS1
VDD1
VSS1
VLDT_A2
VLDT_B2
C154
C154
C167
C167
C156
C156
C157
C157
B7
A11
L16
AK22
AA22
N19
AJ2
H2
VDDNB4
VSS4
VDD2
VSS2
VDD2
VSS2
VLDT_A3
VLDT_B3
VTT_DDR
VTT_DDR
C6
AA4
L18
AK24
AB13
N21
AJ1
H1
VDDNB5
VSS5
VDD3
VSS3
VDD3
VSS3
VLDT_A4
VLDT_B4
C4.7U10Y0805
C4.7U10Y0805
C8
AA5
M2
AK26
AB15
N23
VDDNB6
VSS6
VDD4
VSS4
VDD4
VSS4
D7
AA7
M3
AK28
AB17
P2
D12
AK12
VDDNB7
VSS7
VDD5
VSS5
VDD5
VSS5
VTT1
VTT5
X_C10000P50Y5
X_C10000P50Y5
X_C10000P50Y5
X_C10000P50Y5
D9
AA9
M7
AK30
AB19
P3
C12
AJ12
VDDNB8
VSS8
VDD6
VSS6
VDD6
VSS6
VTT2
VTT6
VCC_DDR
X_C10000P50Y5
X_C10000P50Y5
E8
AA11
M9
AL5
AB21
P8
B12
AH12
VDDNB9
VSS9
VDD7
VSS7
VDD7
VSS7
VTT3
VTT7
D
E10
AA13
M11
B4
AB23
P10
A12
AG12
D
VDDNB10
VSS10
VDD8
VSS8
VDD8
VSS8
VTT4
VTT8
F9
AA15
M13
B9
AC12
P12
AL12
VDDNB11
VSS11
VDD9
VSS9
VDD9
VSS9
VTT9
F11
AA17
M15
B11
AC14
P14
AB24
VDDNB12
VSS12
VDD10
VSS10
VDD10
VSS10
VDDIO1
G10
AA19
M17
B14
AC16
P16
AB26
K24
VDDNB13
VSS13
VDD11
VSS11
VDD11
VSS11
VDDIO2
VSS1
VCORE
G12
AA21
M19
B16
AC18
P18
AB28
K26
VDDNB14
VSS14
VDD12
VSS12
VDD12
VSS12
VDDIO3
VSS2
AA23
N8
B18
AC20
P20
AB30
K28
VSS15
VDD13
VSS13
VDD13
VSS13
VDDIO4
VSS3
AA8
AB2
N10
B20
AC22
P22
AC24
K30
VDD3
VSS16
VDD14
VSS14
VDD14
VSS14
VDDIO5
VSS4
AA10
AB3
N12
B22
AD11
R7
AD26
L7
VDD4
VSS17
VDD15
VSS15
VDD15
VSS15
VDDIO6
VSS5
C169
C169
C161
C161
AA12
AB8
N14
B24
AD23
R9
AD28
L9
VDD5
VSS18
VDD16
VSS16
VDD16
VSS16
VDDIO7
VSS6
AA14
AB10
N16
B26
AE12
R11
AD30
L11
VDD6
VSS19
VDD17
VSS17
VDD17
VSS17
VDDIO8
VSS7
180pf/50V/NPO/4
180pf/50V/NPO/4
180pf/50V/NPO/4
180pf/50V/NPO/4
AA16
AB12
N18
B28
AF11
R13
AF30
L13
VDD7
VSS20
VDD18
VSS18
VDD18
VSS18
VDDIO9
VSS8
AA18
AB14
P7
B30
L20
R15
M24
L15
VDD8
VSS21
VDD19
VSS19
VDD19
VSS19
VDDIO10
VSS9
AB7
AB16
P9
C3
L22
R17
M26
L17
VDD9
VSS22
VDD20
VSS20
VDD20
VSS20
VDDIO11
VSS10
AB9
AB18
P11
D14
M21
R19
M28
L19
VDD10
VSS23
VDD21
VSS21
VDD21
VSS21
VDDIO12
VSS11
AB11
AB20
P13
D16
M23
R21
M30
L21
VDD11
VSS24
VDD22
VSS22
VDD22
VSS22
VDDIO13
VSS12
AC4
AB22
P15
D18
N20
R23
P24
L23
VDD12
VSS25
VDD23
VSS23
VDD23
VSS23
VDDIO14
VSS13
AC5
AC7
P17
D20
N22
T8
P26
M8
VDD13
VSS26
VDD24
VSS24
VDD24
VSS24
VDDIO15
VSS14
AC8
AC9
P19
D22
P21
T10
P28
M10
VDD14
VSS27
VDD25
VSS25
VDD25
VSS25
VDDIO16
VSS15
AC10
AC11
R4
D24
P23
T12
P30
M12
VDD15
VSS28
VDD26
VSS26
VDD26
VSS26
VDDIO17
VSS16
AD2
AC13
R5
D26
R22
T14
T24
M14
VDD16
VSS29
VDD27
VSS27
VDD27
VSS27
VDDIO18
VSS17
AD3
AC15
R8
D28
T23
T16
T26
M16
VDD17
VSS30
VDD28
VSS28
VDD28
VSS28
VDDIO19
VSS18
AD7
AC17
R10
D30
U22
T18
T28
M18
VDD18
VSS31
VDD29
VSS29
VDD29
VSS29
VDDIO20
VSS19
AD9
AC19
R12
E11
V23
T20
T30
M20
VDD19
VSS32
VDD30
VSS30
VDD30
VSS30
VDDIO21
VSS20
AE10
AC21
R14
F4
W22
T22
V25
M22
VDD20
VSS33
VDD31
VSS31
VDD31
VSS31
VDDIO22
VSS21
AF7
AC23
R16
F14
Y23
U4
V26
N4
VDD21
VSS34
VDD32
VSS32
VDD32
VSS32
VDDIO23
VSS22
AF9
AD8
R18
F16
U5
V28
N5
VDD22
VSS35
VDD33
VSS33
VSS33
VDDIO24
VSS23
AG4
AD10
R20
F18
U7
V30
N7
VDD23
VSS36
VDD34
VSS34
VSS34
VDDIO25
VSS24
AG5
AD12
T2
F20
U9
Y24
N9
VDD24
VSS37
VDD35
VSS35
VSS35
VDDIO26
VSS25
AG7
AD14
T3
F22
U11
Y26
N11
VDD25
VSS38
VDD36
VSS36
VSS36
VDDIO27
VSS26
AH2
AD16
T7
F24
U13
Y28
N13
VDD26
VSS39
VDD37
VSS37
VSS37
VDDIO28
VSS27
AH3
AD20
T9
F26
5
U15
Y29
N15
VDD27
VSS40
VDD38
VSS38
GND
VSS38
VDDIO29
VSS28
C
B3
AD22
T11
F28
6
U17
C
VDD28
VSS41
VDD39
VSS39
GND
VSS39
C2
AD24
T13
F30
7
U19
VDD31
VSS42
VDD40
VSS40
GND
VSS40
C4
AE4
T15
G9
8
U21
VDD32
VSS43
VDD41
VSS41
GND
VSS41
D3
AE5
T17
G11
U23
VDD35
VSS44
VDD42
VSS42
VSS42
D5
T19
H8
V2
VDD36
VDD43
VSS43
VSS43
E4
AE11
T21
H10
V3
VDD39
VSS46
VDD44
VSS44
VSS44
E6
AF2
U8
H12
V10
VDD40
VSS47
VDD45
VSS45
VSS45
F5
AF3
U10
H14
V12
VDD43
VSS48
VDD46
VSS46
VSS46
F7
AF8
U12
H16
1
V14
VDD44
VSS49
VDD47
VSS47
GND
VSS47
G6
AF10
U14
H18
2
V16
VDD47
VSS50
VDD48
VSS48
GND
VSS48
G8
AF12
U16
3
V18
VDD48
VSS51
VDD49
GND
VSS49
H7
AF14
U18
H24
V20
VDD51
VSS52
VDD50
VSS50
VSS50
H11
AF16
U20
H26
V22
VDD52
VSS53
VDD51
VSS51
VSS51
H23
AF18
V9
H28
W9
VDD53
VSS54
VDD52
VSS52
VSS52
J8
AF20
V11
H30
W11
VDD54
VSS55
VDD53
VSS53
VSS53
J12
AF22
V13
J4
W13
VDD55
VSS56
VDD54
VSS54
VSS54
J14
AF24
V15
J5
W15
VDD56
VSS57
VDD55
VSS55
VSS55
J16
AF26
V17
J7
W17
VDD57
VSS58
VDD56
VSS56
VSS56
J18
AF28
V19
J9
W19
VDD58
VSS59
VDD57
VSS57
VSS57
J20
AG10
V21
J11
W21
VDD59
VSS60
VDD58
VSS58
VSS58
J22
AG11
W4
J13
W23
VDD60
VSS61
VDD59
VSS59
VSS59
J24
AH14
W5
J15
Y8
VDD61
VSS62
VDD60
VSS60
VSS60
K7
AH16
W8
J17
Y10
VDD62
VSS63
VDD61
VSS61
VSS61
K9
AH18
W10
J19
Y12
VDD63
VSS64
VDD62
VSS62
VSS62
K11
AH20
W12
J21
W7
VDD64
VSS65
VDD63
VSS63
VSS63
K13
AH22
W14
J23
Y20
VDD65
VSS66
VDD64
VSS64
VSS64
K15
AH24
W16
K2
Y22
VDD66
VSS67
VDD65
VSS65
VSS65
K17
AH26
W18
K3
VDD67
VSS68
VDD66
VSS66
K19
AH28
W20
K8
VDD68
VSS69
VDD67
VSS67
K21
AH30
Y2
K10
VDD69
VSS70
VDD68
VSS68
K23
AK2
Y3
K12
VDD70
VSS71
VDD69
VSS69
B
B
L4
AK14
Y7
K14
VDD71
VSS72
VDD70
VSS70
L5
AK16
Y9
K16
VDD72
VSS73
VDD71
VSS71
L8
AK18
Y11
K18
VDD73
VSS74
VDD72
VSS72
L10
Y14
Y13
K20
VDD74
VSS240
VDD73
VSS73
L12
Y16
Y15
K22
VDD75
VSS241
VDD74
VSS74
Y17
Y21
Y18
VDD150
VDD75
VSS75
Y19
VDD151
A
A
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7548
MS-7548
MS-7548
MSI
MSI
MSI
Size
Size
Size
Document Description
Document Description
Document Description
Rev
Rev
Rev
Custom
Custom
Custom
K9 M2 PWR & GND
K9 M2 PWR & GND
K9 M2 PWR & GND
10
10
10
Date:
Date:
Date:
Wednesday, October 01, 2008
Wednesday, October 01, 2008
Wednesday, October 01, 2008
Sheet
Sheet
Sheet
8
8
8
of
of
of
40
40
40
5
4
3
2
1
5 4 3 2 1 VCC_DDR-Decoupling VCC_DDR VCC1_2HTC-Decoupling X_0.22uf/16V/X7R/6 X_0.22uf/16V/X7R/6
5
4
3
2
1
VCC_DDR-Decoupling
VCC_DDR
VCC1_2HTC-Decoupling
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
VTT_DDR-Decoupling
VCC_DDR
VCC1_2
VCC_DDR
C166
C166
C105
C105
C103
C103
C114
C114
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
180pf/50V/NPO/4
180pf/50V/NPO/4
VTT_DDR
C309
C309
C276
C276
C308
C308
C323
C323
C301
C301
C312
C312
2.2uF/6.3V/X5R/6
2.2uF/6.3V/X5R/6
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
C94
C94
C51
C51
X_180pf/50V/NPO/4
X_180pf/50V/NPO/4
180pf/50V/NPO/4
180pf/50V/NPO/4
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
VCC_DDR
C343
C343
C337
C337
C102
C102
C322
C322
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
D
D
VCC_DDR
102pf/50V/X7R/6
102pf/50V/X7R/6
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
2.2uF/6.3V/X5R/6
2.2uF/6.3V/X5R/6
X_180pf/50V/NPO/4
X_180pf/50V/NPO/4
102pf/50V/X7R/6
102pf/50V/X7R/6
C101
C101
C391
C391
C251
C251
C96
C96
C90
C90
2.2uF/6.3V/X5R/6
2.2uF/6.3V/X5R/6
C307
C307
X_0.1uf/25V/Y5V/6
X_0.1uf/25V/Y5V/6
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
VCC1_2
C346
C346
X_0.1uf/25V/Y5V/6
X_0.1uf/25V/Y5V/6
VTT_DDR
4.7uf/16V/X7R/8
4.7uf/16V/X7R/8
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
X_180pf/50V/NPO/4
X_180pf/50V/NPO/4
180pf/50V/NPO/4
180pf/50V/NPO/4
VCC_DDR
C113
C113
C350
C350
C98
C98
C296
C296
180pf/50V/NPO/4
180pf/50V/NPO/4
180pf/50V/NPO/4
180pf/50V/NPO/4
C285
C285
C398
C398
C289
C289
C298
C298
C317
C317
C432
C432
C355
C355
102pf/50V/X7R/6
102pf/50V/X7R/6
C274
C274
C259
C259
C163
C163
C315
C315
10uf/6.3V/X5R/1206
10uf/6.3V/X5R/1206
X_0.22uf/16V/X7R/6
X_0.22uf/16V/X7R/6
X_180pf/50V/NPO/4
X_180pf/50V/NPO/4
X_102pf/50V/X7R/6
X_102pf/50V/X7R/6
0.22uf/16V/X7R/6
0.22uf/16V/X7R/6
180pf/50V/NPO/4
180pf/50V/NPO/4
180pf/50V/NPO/4
180pf/50V/NPO/4
180pf/50V/NPO/4
180pf/50V/NPO/4
Block is AMD Layout Requestd
VCC1_2
C
C
C362
C362
X_10uf/10V/Y5V/1206
X_10uf/10V/Y5V/1206
2pcs(10uF)---Top
2pcs(22uF)---Bottom
C357
C357
X_4.7uf/16V/X7R/8
X_4.7uf/16V/X7R/8
VCORE-Decoupling
1pcs(4.7uF)---Top
2pcs(0.01uF)---Bottom
C366
C366
X_0.1uf/25V/Y5V/6
X_0.1uf/25V/Y5V/6
2pcs(0.22uF)---Top
1pcs(0.01uF)---T