library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity freqdiv is
port( CLKin : in std_logic;
reset : in std_logic;
CLKout: out std_logic);
end freqdiv;
architecture arch of freqdiv is
signal counter: integer:=0;
signal temp: std_logic :='1';
begin
process(CLKin,counter,reset)
begin
if(reset='0') then counter <= 0; temp <='1';
elsif (CLKin'event and CLKin='1') then counter<=counter+1;
if (counter= 25000000) then
temp<=NOT temp;
counter<= 0;
end if;
end if;
CLKout<=temp;
end process;
end arch