Encoder vi FPGA

Hnh 3. Hai knh A v B lch pha trong encoder (trch t [1])

Hnh trn cng trong hnh 3 th hin s b tr ca 2 cm bin knh A v B lch
pha nhau. Khi cm bin A bt u b che th cm bin B hon ton nhn c hng
ngoi xuyn qua, v ngc li. Hnh thp l dng xung ng ra trn 2 knh. Xt
trng hp motor quay cng chiu kim ng h, tn hiu i t tri sang phi.
Bn hy quan st lc tn hiu A chuyn t mc cao xung thp (cnh xung) th
knh B ang mc thp. Ngc li, nu ng c quay ngc chiu kim ng h,
tn hiu i t phi qua tri. Lc ny, ti cnh xung ca knh A th knh B ang
mc cao. Nh vy, bng cch phi hp 2 knh A v B chng ta khng nhng xc
nh c gc quay (thng qua s xung) m cn bit c chiu quay ca ng c
(thng qua mc ca knh B cnh xung ca knh A).

The pins are usually A, B and GND. There may also be two extra pins for a switch function
(spindle can be pushed down to select different function in the code i.e course or fine resolution)

rotary encoder waveform

I connected the A and B channels to +5V on the GPIO header through a couple of 10k resistors
and then connected these to configured inputs on the GPIO header. The middle pin of the
encoder (usually GND)

rotary encoder connection to GPIO on Altera DE2 board

I built this rotary encoder control box- LEDS show bar display of level

Quadrature encoder VHDL code

outputs a 7 bit value with min and max limits

Library IEEE;
Use IEEE.Std_Logic_1164.all;
Use IEEE.Std_Logic_unsigned.all;
Use IEEE.numeric_std.all;
Use IEEE.std_logic_arith.all;
entity rotaryencoder is port
(
CLK : in std_logic;
B : in std_logic;
A : in std_logic;
valueout : out std_logic_vector(6 downto 0) 7 bit value out
);
end rotaryencoder;
architecture struct of rotaryencoder is
signal A_INT : std_logic := 0;
signal B_INT : std_logic := 0;
signal A_INT_P : std_logic := 0;
signal B_INT_P : std_logic := 0;
signal count : std_logic_vector(6 downto 0):=0111111;
signal count : integer range 0 to 2**7 := 1;
begin

main:process(CLK) is
begin
valueout <= conv_std_logic_vector(count,7);
if rising_edge(CLK) then
A_INT_p <= A_INT;
B_INT_p <= B_INT;
A_INT <= A;
B_INT <= B;
if (A_INT = 1 and A_INT_P = 0) then A rising
if (B=0 and count /= 127) then INC
count <= count + 1;
elsif (B=1 and count /= 0) then DEC
count <= count 1;
end if;
elsif (B_INT = 1 and B_INT_P = 0) then B rising
if (A=1 and count /= 127) then INC
count <= count + 1;
elsif (A=0 and count /= 0) then DEC
count <= count 1;
end if;
elsif (A_INT = 0 and A_INT_P = 1) then A falling
if (B=1 and count /= 127) then INC
count <= count + 1;
elsif (B=0 and count /= 0) then DEC
count <= count 1;
end if;
elsif (B_INT = 0 and B_INT_P = 1) then B falling
if (A=0 and count /= 127) then INC
count <= count + 1;
elsif (A=1 and count /= 0) then DEC
count <= count 1;
end if;
else
count<= count;
end if;
end if;
end process;
end struct;