Video

Simple Analog-to-Digital converter
using ADC0808
A project report submitted as a partial fulfillment of

the requirement for the award of
Bachelor of Engineering
degree in
Electronics and Instrumentation Engineering
By
Raghuveer Varahagiri
Roll No. 99726
AU Regd. No. 2012326
4/4 Electronics and Instrumentation
Engineering
Srikanth Mallajyosula
Roll No. 99748
AU Regd. No. 2012347
4/4 Electronics and Instrumentation
Engineering
Department of Electronics, Communication and Instrumentation Engineering,
College of Engineering, GITAM

(Affiliated to Andhra University)
Visakhapatnam - 530045
COLLEGE OF ENGINEERING
GANDHI INSTITUTE OF TECHNOLOGY AND MANAGEMENT
VISAKHAPATNAM
DEPARTMENT OF ELECTRONICS, COMMUNICATION AND

INSTRUMENTATION ENGINEERING
Certificate
This is to certify that Mr. Raghuveer Varahagiri bearing Roll No.99726
(A.U. Regd. No. 2012326) has carried out the project work entitled Simple
Analog-to-Digital Converter using ADC0808 and submitted in the partial
fulfillment of the requirements for the award of the degree of Bachelor of
Engineering during the academic year 2002-2003.
V. Malleswara Rao, M.E.

Associate Professor, Dept. of Electronics,
Communication & Instrumentation Engineering.
Contents
Introduction
Project Objective
Analog-to-Digital Conversion
Successive Approximation A-to-D Conversion
The ADC0808
Astable Multivibrator using 7404 inverter gates
Circuit Diagram
Circuit Description
Result
Bibliography
Introduction
Project Objective
The objective of this project is to construct a simple analog-to-digital converter
circuit using the ADC0808 IC.
The ADC0808 is an 8-bit Analog-to-Digital converter IC which uses the
successive approximation technique for the conversion. It has a total
unadjusted error of LSB. It is capable of converting one of the eight analog
input signals, selected with the help of an 8-channel multiplexer. The clock
signal required by the IC is generated using an astable multivibrator circuit
constructed using 7404 inverter gates. The digital output is displayed using an
array of eight LEDs.
Analog-to-Digital conversion
The function of an analog-to-digital converter is to produce a digital word
which represents the magnitude of some analog voltage or current. The
following are some specifications of an Analog-to-digital converter.
Resolution
The resolution of an Analog-to-Digital converter refers to the number of bits in
the output binary word. For example, ADC0808 which produces an 8-bit
binary word as output, has a resolution of 1 part in 256 (= 28) or 0.39 percent.
Accuracy
The accuracy specification of an Analog-to-Digital converter is a comparison
between the actual output and the expected output. It is specified as a
percentage of the full-scale output. Ideally the maximum error for a converter
should be no more than the value of LSB.
Linearity
Linearity is a measure of how much the output of the converter deviates from
an ideal straight line transfer curve as the input varies from the minimum to
the maximum.
Conversion Time
It is the time taken by the converter to produce a valid output binary code for
an applied input voltage. A converter is said to be high-speed if it has a short
conversion time.
Many different types of analog-to-digital converters are available. Differing
ADC types offer varying resolution, accuracy and speed specifications. The
most popular techniques used for Analog-to-Digital conversion are
1. Parallel (Flash) conversion
2. Successive Approximation ADC
3. Integrating or Dual-Slope ADC
Since the ADC0808 uses the Successive Approximation technique for the
conversion, this technique will be discussed in detail.
Successive Approximation A-to-D conversion
Successive Approximation is a very effective and relatively inexpensive method
of analog-to-digital conversion. This is an electronic implementation of a
technique called binary regression.
A successive approximation ADC employs a digital-to-analog converter (DAC)
and a single comparator. A special shift register called a SuccessiveApproximation Register (SAR) is used to control the DAC. The ADC effectively
makes a bisection or binomial search by beginning with an output of zero. It
provisionally sets each bit of the DAC, beginning with the most significant bit.
The search compares the output of the DAC to the voltage being measured. If
setting a bit to one causes the DAC output to rise above the input voltage,
that bit is set to zero. Otherwise, that bit is left unaltered. This process is
continued for all the bits of the SAR.
A Start Conversion (SC) signal is provided, which when pulsed, initiates the
conversion cycle. An N-bit ADC requires N clock cycles for the conversion of
an analog input. When the conversion is complete, the binary result is placed
on the parallel outputs of the SAR, and the SAR sends out an End-OfConversion (EOC) signal. For continuous conversion, the EOC signal may be
connected to the SC signal.
For an 8-bit ADC whose input range is 0-5V, The output of the DAC is given
by
VDAC = VREF ( ) + (VREF ( + ) VREF ( ) ) D7 2 1 + D6 2 2 + ... + D0 2 8
) Volts
The sequence of operations carried out for the conversion of an input of 3.2V
is shown below.
Iteration
SAR
DAC output Analog Input Comparator
D7 D6 D5 D4 D3 D2 D1 D0 VDAC (Volts)
Vin (Volts)
Output
1 0 0 0 0 0 0 0
2.5
3.2
1 1 0 0 0 0 0 0
3.75
3.2
1 0 1 0 0 0 0 0
3.125
3.2
1 0 1 1 0 0 0 0
3.4375
3.2
1 0 1 0 1 0 0 0
3.28125
3.2
1 0 1 0 0 1 0 0
3.203125
3.2
1 0 1 0 0 0 1 0
3.1640625
3.2
1 0 1 0 0 0 1 1
3.18359375
3.2
This process of approximation can be graphically depicted as shown below.
Fig.1: The process of Successive Approximation

Thus, an input of 3.2V is represented by the binary value 10100011 i.e,
3.18359375 V with an error of 0.51%.
The ADC0808
The ADC0808 is a monolithic CMOS device with an 8-bit analog-to-digital
converter, 8-channel multiplexer and microprocessor compatible control logic.
The 8-bit A/D converter uses successive approximation as the conversion
technique. The converter features a high impedance chopper stabilized
comparator, a 256R voltage divider with analog switch tree and a successive
approximation register. The 8-channel multiplexer can directly access any of 8single-ended analog signals. It has a total unadjusted error of LSB and a
conversion time of 100s.
The device contains an 8-channel single-ended analog signal multiplexer. A

particular input channel is selected by using the address decoder. The address
is latched into the decoder on the low-to-high transition of the address latch
enable (ALE) signal.
The 256R ladder network has inherent monotonicity, which guarantees no
missing digital codes. Additionally, the 256R network does not cause load
variations on the reference voltage.
The A/D converters successive approximation register (SAR) is reset on the
positive edge of the start conversion (SC) pulse. The conversion is begun on
the falling edge of the start conversion pulse. A conversion in process will be
interrupted by receipt of a new start conversion pulse. When used in the
continuous conversion mode by tying the end-of-conversion (EOC) output to
the SC input, an external start conversion pulse should be applied after power
up. The EOC signal will go low between 0 and 8 clock pulses after the rising
edge of start conversion.
Refer to Appendix A for the datasheet of National Semiconductor's ADC0808
Analog-to-Digital converter.
For its operation, the ADC0808 requires a clock signal in the frequency range
of 10 kHz to 1280 kHz. This signal can be generated using an Astable
Multivibrator circuit constructed employing 7404 inverter gates.
Astable Multivibrator using 7404 inverter gates
The basic operation of an inverter gate is given by the truth table shown
below. An inverter gate, in its simplest form, can be represented by the
following equivalent circuit.
Fig.2: A simple Transistor Inverter

When a logic LOW input i.e., 0V is applied at the base terminal, both the
junctions are reverse biased, and thus the transistor is driven to cut-off. The
voltage at the output i.e, the collector terminal is given by
VCE = VCC I C RC
The collector current in cut-off is negligible (IC = hFE IE; IE = 0 in cut-off) and
thus the collector terminal is at logic HIGH i.e., VCC.
When a logic HIGH input (VCC) is applied at the base terminal, both the
junctions are forward-biased and the transistor is driven to saturation. The
output terminal is at a potential of VCE = VCE
SAT
= 0.3V which can be
considered as ground potential. Thus the output of the circuit is logic LOW.
An astable multivibrator or a free-running oscillator circuit has two quasistable states and makes periodic transitions between the two states. A
collector-coupled astable multivibrator circuit is shown below.
Fig.3: A collector-coupled astable multivibrator

Let us consider that, initially, the transistor Q1 is OFF i.e., in cut-off and
transistor Q2 is ON i.e, in saturation. Thus, their outputs are at logic HIGH and
logic LOW respectively. In this state, VCE1 = VCC which is applied to the base of
Q2 through the capacitor C2. Thus Q2 is maintained in saturation. The
capacitor C1 is across VCC and ground (Logic LOW output of Q2) through the
resistor R1. So, it gets charged and the voltage across C1 is applied to the base
of Q1. As the capacitor gets charged to a voltage of VCC, Q1 is driven to
saturation and it's output becomes logic LOW. This immediately drives Q2 to
cut-off and the capacitor C2 now starts charging. When this capacitor charges
to VCC, Q2 is turned ON and Q1 is turned OFF. The cycle repeats itself. If
R1=R2 and C1=C2, then the output of any one transistor is a square wave,
whose amplitude is VCC.
An output waveform with vertical edges may be obtained by including a
diode in the charging path of each capacitor. The transistor inverters can be
replaced by 7404 NOT gates as shown below.
Fig.4: Astable Multivibrator using 7404 inverter gates

In this case, the condition for the output of an inverter to be HIGH is that the
voltage at its input should be greater than the threshold voltage VT. 74LS04
has a threshold voltage between 0.7 and 1.4V. Its internal circuit is as shown
below. Refer to Appendix B for the datasheet of 74LS04 inverters.
Fig.5: 74LS04 Schematic
The frequency of the output waveform may be calculated as follows

Capacitor C1 charges according to the relation
VC = VCC e
RC
The time required for the capacitor to charge from 0V to the threshold voltage
VT is given by
V
t = RC ln T
VCC
This corresponds to half the time period of the square wave output (i.e., t =
T/2). Thus, the frequency of the output waveform is given by
f =
1
=
T
1
V
2 RC ln T
VCC
For the present application, we design an astable multivibrator circuit to

provide a square wave output of 640 kHz.
Assuming a threshold voltage of VT = 1.4V and taking C1=C2=1nF, the value
of the resistors can be calculated as
R=
1
V
2 fC ln T
VCC
= 613.72
Taking R1=R2=680, we obtain a frequency of 577.62 kHz, which is within

the range of clock frequency required for the operation of ADC0808.
Circuit Diagram
Circuit Description
As shown in the circuit diagram, the power supply and the eight single-ended
analog inputs are given to the circuit through a 10-pin connector. The input
signal to be converted is selected through a DIP switch. In the OFF state of the
switches, the address lines are pulled HIGH by 100k pull-up resistors. When
the switches are in the ON state, the address lines are grounded. The large
value of the pull-up resistors prevents excessive flow of current from the
power supply.
The ADC0808 is connected to provide continuous conversion by connecting
the EOC signal (Pin 7) to the SC input (Pin 6). The SC signal for the first
conversion after power-up may be provided manually through the pushbutton provided. The address available on the address lines is latched into the
decoder during the low-to-high transition of the ALE signal. The ALE (Pin 22)
has also been connected to the pushbutton to facilitate the latching of a new
address selected through the DIP switch. In the OFF state of the pushbutton,
the SC input is pulled LOW by the 100k pull-down resistor. The large value of
the pull-down resistor prevents excessive currents when the pushbutton is
pressed or when the EOC signal becomes HIGH. Moreover, since the EOC
signal is also connected to the ALE input, the address available on the address
lines is loaded into the address latch at the beginning of each conversion.
When an analog input in the range VREF(+) (5V) and VREF(-) (0V) is given to one
of the input terminals, and the corresponding address is selected using the
DIP switch, the ADC0808 converts the analog input into an 8-bit binary word
which is displayed by the array of LEDs. Since the ADC has been connected in
the continuous conversion mode, the selected input is continuously sampled
and converted, and the output follows the variations in the input.
Result
The above Analog-to-Digital converter circuit has been constructed, with the
clock signal being provided by the astable multivibrator employing 7404
inverter gates. The circuit has been found to provide accurate and continuous
digital output for input voltage in the entire range of VREF(-) through VREF(+),
applied at the selected input terminal.
Bibliography
1. Simple Analog-to-Digital Converter - B. P. Ladgaonkar, Electronics for
You, September 1999.
2. Microprocessors and Interfacing : Programming and Hardware, 2nd Ed.
Douglas V. Hall, Tata McGraw-Hill Publishing Company Limited, 1999.
3. Modern Electronic Instrumentation and Measurenment Techniques
Albert D. Helfrick and William D. Cooper, Prentice Hall of India Private
Limited, 1997.
4. Microprocessor Architecture, Programming and Applications With the
8085 Ramesh S. Gaonkar, Penram International Publishing (India),
1997.
5. ADC0808/ADC0809 8-Bit Microprocessor Compatible A/D Converters
with 8-channel Multiplexer : Datasheet National Semiconductors.
6. Pulse, Digital and Switching waveforms Jacob Millman and Herbert
Taub, Tata McGraw-Hill Publishing Company Limited, 1991.
7. Pulse, Digital Circuits and Computer Fundamentals R. Venkataraman,
Dhanpat Rai Publications, 1994.
Appendix A
National Semiconductor
ADC0808/ADC0809
8-Bit P Compatible A/D Converters

with 8-Channel Multiplexer
ADC0808/ADC0809
8-Bit P Compatible A/D Converters with 8-Channel
Multiplexer
General Description
Features
The ADC0808, ADC0809 data acquisition component is a

monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible
control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can
directly access any of 8-single-ended analog signals.
The device eliminates the need for external zero and
full-scale adjustments. Easy interfacing to microprocessors
is provided by the latched and decoded multiplexer address
inputs and latched TTL TRI-STATE outputs.
The design of the ADC0808, ADC0809 has been optimized
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0808, ADC0809 offers high
speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes
minimal power. These features make this device ideally
suited to applications from process and machine control to
consumer and automotive applications. For 16-channel multiplexer with common output (sample/hold port) see
ADC0816 data sheet. (See AN-247 for more information.)
n Easy interface to all microprocessors

n Operates ratiometrically or with 5 VDC or analog span
adjusted voltage reference
n No zero or full-scale adjust required
n 8-channel multiplexer with address logic
n 0V to 5V input range with single 5V power supply
n Outputs meet TTL voltage level specifications
n Standard hermetic or molded 28-pin DIP package
n 28-pin molded chip carrier package
n ADC0808 equivalent to MM74C949
n ADC0809 equivalent to MM74C949-1
Key Specifications
n
n
n
n
n
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
8 Bits
12 LSB and 1 LSB

5 VDC
15 mW
100 s
Block Diagram
DS005672-1
See Ordering
Information
TRI-STATE is a registered trademark of National Semiconductor Corp.
1999 National Semiconductor Corporation
DS005672
www.national.com
ADC0808/ADC0809 8-Bit P Compatible A/D Converters with 8-Channel Multiplexer
October 1999
ADC0808/ADC0809
Connection Diagrams
Molded Chip Carrier Package
Dual-In-Line Package
DS005672-12
Order Number ADC0808CCV or ADC0809CCV

See NS Package V28A
DS005672-11
Order Number ADC0808CCN or ADC0809CCN

See NS Package J28A or N28A
Ordering Information
TEMPERATURE RANGE
Error
12 LSB Unadjusted
1 LSB Unadjusted
Package Outline
www.national.com
40C to +85C
ADC0808CCN
ADC0808CCV
ADC0809CCN
ADC0809CCV
N28A Molded DIP
V28A Molded Chip Carrier
55C to +125C
ADC0808CCJ
ADC0808CJ
J28A Ceramic DIP
J28A Ceramic DIP
Dual-In-Line Package (ceramic)

Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
ESD Susceptibility (Note 8)
Supply Voltage (VCC) (Note 3)

6.5V
Voltage at Any Pin
0.3V to (VCC+0.3V)
Except Control Inputs
Voltage at Control Inputs
0.3V to +15V
(START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)
Storage Temperature Range
65C to +150C
875 mW
Package Dissipation at TA = 25C
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
260C
Operating Conditions
300C
215C
220C
400V
(Notes 1, 2)
TMINTATMAX
40CTA+85C
40C TA +85C
4.5 VDC to 6.0 VDC
Temperature Range (Note 1)

ADC0808CCN,ADC0809CCN
ADC0808CCV, ADC0809CCV
Range of VCC (Note 1)
Electrical Characteristics
Converter Specifications: VCC = 5 VDC = VREF+, VREF() = GND, TMINTATMAX and fCLK = 640 kHz unless otherwise stated.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
12
34
LSB
1
114
LSB
VCC+0.10
VDC
ADC0808
25C
(Note 5)
TMIN to TMAX
LSB
ADC0809
VREF(+)
0C to 70C
(Note 5)
TMIN to TMAX
Input Resistance
From Ref(+) to Ref()
1.0
Analog Input Voltage Range
(Note 4) V(+) or V()
GND0.10
Voltage, Top of Ladder
Measured at Ref(+)
Voltage, Center of Ladder
VREF()
Voltage, Bottom of Ladder
IIN
Comparator Input Current
VCC/2-0.1
Measured at Ref()
fc = 640 kHz, (Note 6)
LSB
2.5
VCC
VCC+0.1
VCC/2
VCC/2+0.1
0.1
0.5
Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75VCC5.25V,
40CTA+85C unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
10
200
nA
1.0
ANALOG MULTIPLEXER
IOFF(+)
OFF Channel Leakage Current
VCC = 5V, VIN = 5V,

TA = 25C
IOFF()
OFF Channel Leakage Current
TMIN to TMAX
VCC = 5V, VIN = 0,
TA = 25C
200
TMIN to TMAX
1.0
10
nA
A
CONTROL INPUTS
VIN(1)
Logical 1 Input Voltage
VIN(0)
Logical 0 Input Voltage
IIN(1)
Logical 1 Input Current
VCC1.5
VIN = 15V
1.5
1.0
(The Control Inputs)

IIN(0)
Logical 0 Input Current
VIN = 0
1.0
(The Control Inputs)

ICC
Supply Current
fCLK = 640 kHz
0.3
3.0
mA
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ADC0808/ADC0809
Absolute Maximum Ratings (Notes 2, 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ADC0808/ADC0809
(Continued)
Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75VCC5.25V,
40CTA+85C unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DATA OUTPUTS AND EOC (INTERRUPT)

VOUT(1)
Logical 1 Output Voltage
VOUT(0)
Logical 0 Output Voltage
VOUT(0)
Logical 0 Output Voltage EOC
IOUT
TRI-STATE Output Current
VCC = 4.75V
IOUT = 360A
IOUT = 10A
IO = 1.6 mA
2.4
4.5
V(min)
V(min)
0.45
IO = 1.2 mA
VO = 5V
VO = 0
0.45
Timing Specifications VCC = VREF(+) = 5V, VREF() = GND, tr = tf = 20 ns and TA = 25C unless otherwise noted.
Typ
Max
Units
tWS
Symbol
Minimum Start Pulse Width
Parameter
(Figure 5)
Conditions
MIn
100
200
ns
tWALE
Minimum ALE Pulse Width
(Figure 5)
100
200
ns
ts
Minimum Address Set-Up Time
(Figure 5)
25
50
ns
tH
Minimum Address Hold Time
25
50
ns
tD
Analog MUX Delay Time
(Figure 5)
RS = 0 (Figure 5)
2.5
CL = 50 pF, RL = 10k (Figure 8)

CL = 10 pF, RL = 10k (Figure 8)
fc = 640 kHz, (Figure 5) (Note 7)
125
250
ns
125
250
ns
90
100
116
10
640
1280
kHz
From ALE
tH1, tH0
OE Control to Q Logic State
t1H, t0H
OE Control to Hi-Z
tc
Conversion Time
fc
Clock Frequency
tEOC
EOC Delay Time
(Figure 5)
8+2 S
Clock
Periods
CIN
Input Capacitance
At Control Inputs
10
15
pF
COUT
TRI-STATE Output
At TRI-STATE Outputs
10
15
pF
Capacitance
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless othewise specified.
Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater
than the VCCn supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more
than 100 mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900 VDC
over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust. However, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages
can be adjusted to achieve this. See Figure 13.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little
temperature dependence (Figure 6). See paragraph 4.0.
Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 8: Human body model, 100 pF discharged through a 1.5 k resistor.
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Multiplexer. The device contains an 8-channel single-ended

analog signal multiplexer. A particular input channel is selected by using the address decoder. Table 1 shows the input
states for the address lines to select any channel. The address is latched into the decoder on the low-to-high transition
of the address latch enable signal.
The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter.
Figure 2 shows a typical example of a 3-bit converter. In the
ADC0808, ADC0809, the approximation technique is extended to 8 bits using the 256R network.
TABLE 1.
SELECTED
ADDRESS LINE
ANALOG
CHANNEL
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
The A/D converters successive approximation register

(SAR) is reset on the positive edge of the start conversion
(SC) pulse. The conversion is begun on the falling edge of
the start conversion pulse. A conversion in process will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the
end-of-conversion (EOC) output to the SC input. If used in
this mode, an external start conversion pulse should be applied after power up. End-of-conversion will go low between
0 and 8 clock pulses after the rising edge of start conversion.
The most important section of the A/D converter is the comparator. It is this section which is responsible for the ultimate
accuracy of the entire converter. It is also the comparator
drift which has the greatest influence on the repeatability of
the device. A chopper-stabilized comparator provides the
most effective method of satisfying all the converter requirements.
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its
8-bit analog-to-digital converter. The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3
major sections: the 256R ladder network, the successive approximation register, and the comparator. The converters
digital outputs are positive true.
The 256R ladder network approach (Figure 1) was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback
control systems. A non-monotonic relationship can cause oscillations that will be catastrophic for the system. Additionally,
the 256R network does not cause load variations on the reference voltage.
The chopper-stabilized comparator converts the DC input

signal into an AC signal. This signal is then fed through a
high gain AC amplifier and has the DC level restored. This
technique limits the drift component of the amplifier since the
drift is a DC component which is not passed by the AC amplifier. This makes the entire A/D converter extremely insensitive to temperature, long term drift and input offset errors.
Figure 4 shows a typical error curve for the ADC0808 as

measured using the procedures outlined in AN-179.
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ADC0808/ADC0809
The bottom resistor and the top resistor of the ladder network in Figure 1 are not the same value as the remainder of
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached +12 LSB
and succeeding output transitions occur every 1 LSB later up
to full-scale.
Functional Description
ADC0808/ADC0809
Functional Description
(Continued)
DS005672-2
FIGURE 1. Resistor Ladder and Switch Tree
DS005672-13
DS005672-14
FIGURE 2. 3-Bit A/D Transfer Curve
FIGURE 3. 3-Bit A/D Absolute Accuracy Curve
DS005672-15
FIGURE 4. Typical Error Curve
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ADC0808/ADC0809
Timing Diagram
DS005672-4
FIGURE 5.
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ADC0808/ADC0809
Typical Performance Characteristics
DS005672-16
FIGURE 6. Comparator IIN vs VIN

(VCC = VREF = 5V)
DS005672-17
FIGURE 7. Multiplexer RON vs VIN

(VCC = VREF = 5V)
TRI-STATE Test Circuits and Timing Diagrams

t1H, CL = 10 pF
t1H, tH1
DS005672-18
tH1, CL = 50 pF
DS005672-19
t0H, CL = 10 pF
t0H, tH0
DS005672-22
DS005672-21
DS005672-20
tH0, CL = 50 pF
DS005672-23
FIGURE 8.
DX = Data point being measured
DMAX = Maximum data limit
DMIN = Minimum data limit
A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the wiper is directly proportional to the output voltage which is a ratio of the
full-scale voltage across it. Since the data is represented as
a proportion of full-scale, reference requirements are greatly
reduced, eliminating a large source of error and cost for
many applications. A major advantage of the ADC0808,
ADC0809 is that the input voltage range is equal to the supply range so the transducers can be connected directly
across the supply and their outputs connected directly into
the multiplexer inputs, (Figure 9).
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however,
many types of measurements must be referred to an absolute standard such as voltage or current. This means a sys-
Applications Information
OPERATION
1.0 RATIOMETRIC CONVERSION
The ADC0808, ADC0809 is designed as a complete Data
Acquisition System (DAS) for ratiometric conversion systems. In ratiometric systems, the physical variable being
measured is expressed as a percentage of full-scale which is
not necessarily related to an absolute standard. The voltage
input to the ADC0808 is expressed by the equation
(1)
VIN = Input voltage into the ADC0808
Vfs = Full-scale voltage
VZ = Zero voltage
www.national.com
The top of the ladder, Ref(+), should not be more positive

than the supply, and the bottom of the ladder, Ref(), should
not be more negative than ground. The center of the ladder
voltage must also be near the center of the supply because
the analog switch tree changes from N-channel switches to
P-channel switches. These limitations are automatically satisfied in ratiometric systems and can be easily met in ground
referenced systems.
(Continued)
tem reference must be used which relates the full-scale voltage to the standard volt. For example, if VCC = VREF = 5.12V,
then the full-scale range is divided into 256 standard steps.
The smallest standard step is 1 LSB which is then 20 mV.
2.0 RESISTOR LADDER LIMITATIONS
The voltages from the resistor ladder are compared to the
selected into 8 times in a conversion. These voltages are
coupled to the comparator via an analog switch tree which is
referenced to the supply. The voltages at the top, center and
bottom of the ladder must be controlled to maintain proper
operation.
Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply must be
trimmed to match the reference voltage. For instance, if a
5.12V is used, the supply should be adjusted to the same
voltage within 0.1V.
DS005672-7
FIGURE 9. Ratiometric Conversion System

The top and bottom ladder voltages cannot exceed VCC and
ground, respectively, but they can be symmetrically less than
VCC and greater than ground. The center of the ladder voltage should always be near the center of the supply. The sensitivity of the converter can be increased, (i.e., size of the
LSB steps decreased) by using a symmetrical reference system. In Figure 13, a 2.5V reference is symmetrically centered about VCC/2 since the same current flows in identical
resistors. This system with a 2.5V reference allows the LSB
bit to be half the size of a 5V reference system.
The ADC0808 needs less than a milliamp of supply current

so developing the supply from the reference is readily accomplished. In Figure 11 a ground referenced system is
shown which generates the supply from the reference. The
buffer shown can be an op amp of sufficient drive to supply
the milliamp of supply current and the desired bus drive, or if
a capacitive bus is driven by the outputs a large capacitor will
supply the transient supply current as seen in Figure 12. The
LM301 is overcompensated to insure stability when loaded
by the 10 F output capacitor.
www.national.com
ADC0808/ADC0809
ADC0808/ADC0809
(Continued)
DS005672-24
FIGURE 10. Ground Referenced

Conversion System Using Trimmed Supply
DS005672-25
FIGURE 11. Ground Referenced Conversion System with

Reference Generating VCC Supply
www.national.com
10
ADC0808/ADC0809
(Continued)
DS005672-26
FIGURE 12. Typical Reference and Supply Circuit
DS005672-27
RA = RB
*Ratiometric transducers
FIGURE 13. Symmetrically Centered Reference

The output code N for an arbitrary input are the integers
within the range:
3.0 CONVERTER EQUATIONS

The transition between adjacent codes N and N+1 is given
by:
(4)
Where: VIN = Voltage at comparator input
VREF(+) = Voltage at Ref(+)
VREF() = Voltage at Ref()
VTUE = Total unadjusted error voltage (typically
VREF(+)512)
(2)
The center of an output code N is given by:
(3)
11
www.national.com
ADC0808/ADC0809
If no filter capacitors are used at the analog inputs and the

signal source impedances are low, the comparator input current should not introduce converter errors, as the transient
created by the capacitance discharge will die out before the
comparator output is strobed.
If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted conventionally.
(Continued)
4.0 ANALOG COMPARATOR INPUTS

The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances. These are
connected alternately to the output of the resistor ladder/
switch tree network and to the comparator input as part of
the operation of the chopper stabilized comparator.
The average value of the comparator input current varies directly with clock frequency and with VIN as shown in
Figure 6.
Typical Application
DS005672-10
*Address latches needed for 8085 and SC/MP interfacing the ADC0808 to a microprocessor
TABLE 2. Microprocessor Interface Table

PROCESSOR
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READ
WRITE
INTERRUPT (COMMENT)
8080
MEMR
MEMW
INTR (Thru RST Circuit)
8085
RD
WR
INTR (Thru RST Circuit)
Z-80
RD
WR
INT (Thru RST Circuit, Mode 0)
SC/MP
NRDS
NWDS
SA (Thru Sense A)
6800
VMA 2 R/W
VMA R/W
IRQA or IRQB (Thru PIA)
12
ADC0808/ADC0809
Physical Dimensions
inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)

Order Number ADC0808CCN or ADC0809CCN
NS Package Number N28B
Molded Chip Carrier (V)

Order Number ADC0808CCV or ADC0809CCV
NS Package Number V28A
13
www.national.com
ADC0808/ADC0809 8-Bit P Compatible A/D Converters with 8-Channel Multiplexer
Notes
LIFE SUPPORT POLICY

NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
Europe
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Franais Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
2. A critical component is any component of a life

support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: sea.support@nsc.com
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Appendix B
Texas Instruments
SN7404, SN74LS04, SN74S04
HEX INVERTERS
SN5404, SN54LS04, SN54S04,

SN7404, SN74LS04, SN74S04
HEX INVERTERS
SDLS029B DECEMBER 1983 REVISED FEBRUARY 2002
Dependable Texas Instruments Quality and

Reliability
description
These devices contain six independent inverters.
SN5404 . . . J PACKAGE
SN54LS04, SN54S04 . . . J OR W PACKAGE
SN7404 . . . D, N, OR NS PACKAGE
SN74LS04 . . . D, DB, N, OR NS PACKAGE
SN74S04 . . . D OR N PACKAGE
(TOP VIEW)
1A
1Y
2A
2Y
3A
3Y
GND
14
13
12
11
10
VCC
6A
6Y
5A
5Y
4A
4Y
SN5404 . . . W PACKAGE
(TOP VIEW)
1A
2Y
2A
14
13
12
VCC
3A
3Y
4A
11
10
1Y
6A
6Y
GND
5Y
5A
4Y
1Y
1A
NC
VCC
6A
SN54LS04, SN54S04 . . . FK PACKAGE

(TOP VIEW)
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
6Y
NC
5A
NC
5Y
3Y
GND
NC
4Y
4A
2A
NC
2Y
NC
3A
NC No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN5404, SN54LS04, SN54S04,

SN7404, SN74LS04, SN74S04
HEX INVERTERS
ORDERING INFORMATION
PDIP N
0C to 70C
ORDERABLE
PART NUMBER
PACKAGE
TA
SOIC D
SOP NS
SSOP DB
CDIP J
55C to 125C
CFP W
LCCC FK
TOP-SIDE
MARKING
Tube
SN7404N
SN7404N
Tube
SN74LS04N
SN74LS04N
Tube
SN74S04N
SN74S04N
Tube
SN7404D
7404
Tube
SN74LS04D
Tape and reel
SN74LS04DR
Tube
SN74S04D
Tape and reel
SN74S04DR
Tape and reel
SN7404NSR
SN7404
Tape and reel
SN74LS04NSR
74LS04
Tape and reel
SN74LS04DBR
LS04
Tube
SN5404J
SN5404J
Tube
SNJ5404J
SNJ5404J
Tube
SN54LS04J
SN54LS04J
Tube
SN54S04J
SN54S04J
Tube
SNJ54LS04J
SNJ54LS04J
Tube
SNJ54S04J
SNJ54S04J
Tube
SNJ5404W
SNJ5404W
Tube
SNJ54LS04W
SNJ54LS04W
Tube
SNJ54S04W
SNJ54S04W
Tube
SNJ54LS04FK
SNJ54LS04FK
Tube
SNJ54S04FK
LS04
S04
SNJ54S04FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
DALLAS, TEXAS 75265
SN5404, SN54LS04, SN54S04,

SN7404, SN74LS04, SN74S04
HEX INVERTERS
logic diagram (positive logic)

1A
1Y
2A
2Y
3A
3Y
4A
4Y
5A
5Y
6A
6Y
Y=A
DALLAS, TEXAS 75265
SN5404, SN54LS04, SN54S04,

SN7404, SN74LS04, SN74S04
HEX INVERTERS
schematics (each gate)

04
VCC
4 k
130
1.6 k
Input A
Output Y
1 k
GND
LS04
S04
VCC
20 k
120
8 k
Input
A
VCC
4 k
2.8 k
Output
Y
50
900
Input
A
3.5 k
Output
Y
12 k
500
250
3 k
1.5 k
GND
GND
Resistor values shown are nominal.
DALLAS, TEXAS 75265
SN5404, SN54LS04, SN54S04,

SN7404, SN74LS04, SN74S04
HEX INVERTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: 04, S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions

SN7404
SN5404
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
TA
Low-level output current
High-level input voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5.5
4.75
5.25
High-level output current

55
V
V
0.8
0.8
0.4
0.4
mA
16
mA
70
16
Operating free-air temperature
UNIT
125
electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN5404
MIN TYP
TEST CONDITIONS
PARAMETER
VIK
VOH
VCC = MIN,
VCC = MIN,
II = 12 mA
VIL = 0.8 V,
VOL
II
VCC = MIN,
VCC = MAX,
VIH = 2 V,
VI = 5.5 V
IIH
IIL
VCC = MAX,
VCC = MAX,
VI = 2.4 V
VI = 0.4 V
IOS
ICCH
VCC = MAX
VCC = MAX,
MAX
SN7404
MIN TYP
1.5
IOH = 0.4 mA
IOL = 16 mA
2.4
3.4
0.2
1.5
2.4
0.4
3.4
0.2
20
MAX
UNIT
V
V
0.4
1
V
mA
40
40
1.6
1.6
mA
55
mA
12
mA
ICCL
VCC = MAX,
18
33
18
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25C.
Not more than one output should be shorted at a time.
33
mA
VI = 0 V
VI = 4.5 V
55
6
18
12
switching characteristics, VCC = 5 V, TA = 25C (see Figure 1)

PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
SN5404
SN7404
TEST CONDITIONS
MIN
RL = 400
,
CL = 15 pF
F
DALLAS, TEXAS 75265
UNIT
TYP
MAX
12
22
15
ns
SN5404, SN54LS04, SN54S04,

SN7404, SN74LS04, SN74S04
HEX INVERTERS

SN74LS04
SN54LS04
VCC
VIH
Supply voltage
VIL
IOH
IOL
TA
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5.5
4.75
5.25

55
V
V
0.7
0.8
0.4
0.4
mA
mA
70
UNIT
125

otherwise noted)
VIK
VOH
SN54LS04
MIN TYP
MAX
TEST CONDITIONS
PARAMETER
VCC = MIN,
VCC = MIN,
II = 18 mA
VIL = MAX,
VOL
VCC = MIN
MIN,
VIH = 2 V
II
IIH
VCC = MAX,
VCC = MAX,
VI = 7 V
VI = 2.7 V
IIL
IOS
VCC = MAX,
VCC = MAX
VI = 0.4 V
ICCH
ICCL
VCC = MAX,
VCC = MAX,
VI = 0 V
VI = 4.5 V
SN74LS04
MIN TYP
MAX
1.5
IOH = 0.4 mA
IOL = 4 mA
2.5
3.4
0.25
1.5
2.7
3.4
0.4
0.25
0.5
0.1
0.1
mA
20
20
0.4
20
V
V
0.4
IOL = 8 mA
UNIT
100
20
0.4
mA
100
mA
1.2
2.4
1.2
2.4
mA
3.6
6.6
3.6
6.6
mA
Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second.

PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN54LS04
SN74LS04
MIN
RL = 2 k
k,
CL = 15 pF
F
DALLAS, TEXAS 75265
UNIT
TYP
MAX
15
10
15
ns
SN5404, SN54LS04, SN54S04,

SN7404, SN74LS04, SN74S04
HEX INVERTERS

SN74S04
SN54S04
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5.5
4.75
5.25
UNIT
VCC
VIH
Supply voltage
VIL
IOH
0.8
0.8
mA
IOL
TA
20
mA
70
20
55
125

otherwise noted)
SN54S04
MIN TYP
MAX
TEST CONDITIONS
PARAMETER
VIK
VOH
VCC = MIN,
VCC = MIN,
II = 18 mA
VIL = 0.8 V,
VOL
II
VCC = MIN,
VCC = MAX,
VIH = 2 V,
VI = 5.5 V
IIH
IIL
VCC = MAX,
VCC = MAX,
VI = 2.7 V
VI = 0.5 V
IOS
ICCH
VCC = MAX
VCC = MAX,
SN74S04
MIN TYP
MAX
1.2
IOH = 1 mA
IOL = 20 mA
2.5
3.4
40
1.2
2.7
3.4
UNIT
V
V
0.5
0.5
V
mA
50
50
mA
100
mA
15
24
mA
ICCL
VCC = MAX,
30
54
30
Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second.
54
mA
VI = 0 V
VI = 4.5 V
100
15
40
24

FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
RL = 280
,
CL = 15 pF
F
tPLH
tPHL
RL = 280
,
CL = 50 pF
F
PARAMETER
SN54S04
SN74S04
TEST CONDITIONS
MIN
DALLAS, TEXAS 75265
UNIT
TYP
MAX
4.5
4.5
5
ns
ns
SN5404, SN54LS04, SN54S04,

SN7404, SN74LS04, SN74S04
HEX INVERTERS
PARAMETER MEASUREMENT INFORMATION

SERIES 54/74 AND 54S/74S DEVICES
VCC
Test
Point
VCC
RL
(see Note B)
From Output
Under Test
CL
(see Note A)
High-Level
Pulse
1.5 V
S2
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3V
Timing
Input
1.5 V
1 k
Test
Point
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
S1
(see Note B)
CL
(see Note A)
RL
CL
(see Note A)
RL
From Output
Under Test
VCC
From Output
Under Test
Test
Point
1.5 V
0V
tw
Low-Level
Pulse
1.5 V
tsu
Data
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V
1.5 V
In-Phase
Output
(see Note D)
tPHL
VOH
1.5 V
Out-of-Phase
Output
(see Note D)
0V
1.5 V
1.5 V
Waveform 1
(see Notes C
and D)
tPLZ
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
1.5 V
VOL
tPZH
tPLH
1.5 V
0V
tPZL
VOL
tPHL
1.5 V
3V
Output
Control
(low-level
enabling)
0V
tPLH
3V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
th
Waveform 2
(see Notes C
and D)
VOL + 0.5 V
tPHZ
VOH
1.5 V
VOH 0.5 V
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 ; tr and tf 7 ns for Series
54/74 devices and tr and tf 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
DALLAS, TEXAS 75265
SN5404, SN54LS04, SN54S04,

SN7404, SN74LS04, SN74S04
HEX INVERTERS
PARAMETER MEASUREMENT INFORMATION

SERIES 54LS/74LS DEVICES
VCC
Test
Point
VCC
RL
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
High-Level
Pulse
1.3 V
S2
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3V
Timing
Input
1.3 V
5 k
Test
Point
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
S1
(see Note B)
CL
(see Note A)
RL
(see Note B)
RL
From Output
Under Test
VCC
From Output
Under Test
Test
Point
1.3 V
0V
tw
Low-Level
Pulse
1.3 V
tsu
0V
In-Phase
Output
(see Note D)
3V
1.3 V
1.3 V
0V
tPZL
tPLZ
tPHL
VOH
1.3 V
1.3 V
Waveform 1
(see Notes C
and D)
VOL
tPZH
tPLH
VOH
1.3 V
1.3 V
VOL
Waveform 2
(see Notes C
and D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
1.3 V
VOL
tPHL
Out-of-Phase
Output
(see Note D)
1.3 V
0V
Output
Control
(low-level
enabling)
1.3 V
tPLH
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.3 V
3V
Data
Input
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
th
VOL + 0.5 V
tPHZ
VOH
1.3 V
VOH 0.5 V
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 , tr 1.5 ns, tf 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
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Simple Analog-to-Digital converter

A project report submitted as a partial fulfillment of

Department of Electronics, Communication and Instrumentation Engineering,

College of Engineering, GITAM

DEPARTMENT OF ELECTRONICS, COMMUNICATION AND

V. Malleswara Rao, M.E.

VDAC = VREF ( ) + (VREF ( + ) VREF ( ) ) D7 2 1 + D6 2 2 + ... + D0 2 8

DAC output Analog Input Comparator

This process of approximation can be graphically depicted as shown below.

Fig.1: The process of Successive Approximation

The device contains an 8-channel single-ended analog signal multiplexer. A

Fig.2: A simple Transistor Inverter

= 0.3V which can be

Fig.3: A collector-coupled astable multivibrator

Fig.4: Astable Multivibrator using 7404 inverter gates

Fig.5: 74LS04 Schematic

The frequency of the output waveform may be calculated as follows

For the present application, we design an astable multivibrator circuit to

Taking R1=R2=680, we obtain a frequency of 577.62 kHz, which is within

8-Bit P Compatible A/D Converters

The ADC0808, ADC0809 data acquisition component is a

n Easy interface to all microprocessors

12 LSB and 1 LSB

TRI-STATE is a registered trademark of National Semiconductor Corp.

1999 National Semiconductor Corporation

ADC0808/ADC0809 8-Bit P Compatible A/D Converters with 8-Channel Multiplexer

Molded Chip Carrier Package

Order Number ADC0808CCV or ADC0809CCV

Order Number ADC0808CCN or ADC0809CCN

N28A Molded DIP

V28A Molded Chip Carrier

J28A Ceramic DIP

J28A Ceramic DIP

Dual-In-Line Package (ceramic)

Supply Voltage (VCC) (Note 3)

Temperature Range (Note 1)

Total Unadjusted Error

From Ref(+) to Ref()

Analog Input Voltage Range

(Note 4) V(+) or V()

Voltage, Top of Ladder

Voltage, Center of Ladder

Voltage, Bottom of Ladder

Comparator Input Current

OFF Channel Leakage Current

VCC = 5V, VIN = 5V,

OFF Channel Leakage Current

Logical 1 Input Voltage

Logical 0 Input Voltage

Logical 1 Input Current

(The Control Inputs)

Logical 0 Input Current

(The Control Inputs)

fCLK = 640 kHz

Absolute Maximum Ratings (Notes 2, 1)

DATA OUTPUTS AND EOC (INTERRUPT)

Logical 1 Output Voltage

Logical 0 Output Voltage

Logical 0 Output Voltage EOC

TRI-STATE Output Current

Minimum Start Pulse Width

Minimum ALE Pulse Width

Minimum Address Set-Up Time

Minimum Address Hold Time