Rach 3gpp Ds629

0
3GPP RACH Preamble

Detector v1.0
DS629 August 8, 2007
Product Specification
Introduction
System Overview
The 3GPP RACH Preamble Detector core provides an

optimal solution for implementing RACH detection in
a 3GPP uplink. The core includes all of the logic
required for scramble-code generation, correlation and
preamble detection. The RACH Preamble Detector
combines an optimal core and a flexible wrapper
design, allowing custom implementation of detection
algorithms and easy integration with a DSP or microprocessor.
Figure 1 shows a typical use of the 3GPP RACH

Preamble Detector core. The core is designed to act as a
co-processor attached to a microprocessor or DSP
across a system bus. The open core protocol (OCP)
interfaces allow easy adaptation to other bus protocols.
Features
Device families supported: Virtex-4, Virtex-5,
Spartan-3A DSP
Scalable solution for femto-cells up to macro-cells
Algorithm Features
- Compact, scalable correlation unit
- Streamed correlation calculations, allowing
minimal hardware use for femto and pico
applications
- Coherent and non-coherent result generation in
parallel with correlation.
- Sorted and filtered PDP results
During operation, the RACH runs on every antenna on

every slot. The processor can configure the RACH core
over the OCP-compatible bus to determine the size of
the cell being processed and the nature of the algorithm
used to combine the RACH correlation data to form a
decision. The antenna data stream can come directly
from a radio interface, but could also be streamed via
DMA across the system bus.
At the end of each slot, the RACH core produces a
power delay profile (PDP) for each of the possible
RACH preambles. These PDPs can then be read by the
DSP. The core also produces an AICH recommendation
based on the PDPs. This recommendation can be used
by the processor, or it can interpret the PDPs to form its
own decision. The PDPs are also required to initialize
the searcher (see the 3GPP Searcher v1.0 data sheet,
DS628).
Figure Top x-ref 1
Design scales with following parameters to

minimize resource utilization, based on:
DSP Processor
- Search window size

- Coherent accumulation window size
System Bus
- Number of antenna
- Oversample rate
RACH
Configurations
- Quantization
Easy integration to microprocessor/DSP via
OCP-compatible interfaces
- Pipelined read of RACH results for improved
performance
Antenna
Data
For use with Xilinx CORE Generator software

v9.2i or later
RACH
Results
3GPP RACH
Core
xmp002_01_062007
Figure 1: Typical Application
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makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly
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3GPP RACH Preamble Detector v1.0
Background
RACH Detection
The 3GPP RACH Preamble Detector is used to detect a RACH preamble transmission from user
equipment (UE). The RACH transmission from the UE is one of 16 possible preambles, consisting of
256 repetitions of one of the Hadamard code sequences listed in Table 1.
Table 1: Hadamard Code

Value of n
Preamble
Signature
10
11
12
13
14
15
P0(n)
P1(n)
P2(n)
P3(n)
P4(n)
P5(n)
P6(n)
P7(n)
P8(n)
P9(n)
P10(n)
P11(n)
P12(n)
P13(n)
P14(n)
P15(n)
Each preamble of 4096 chips long is transmitted from the UE after scrambling, using the scrambling
code assigned to the PRACH channel. The base station (BS) receives the antenna data, where it is
descrambled by the RACH preamble detector and correlated against the preamble sequences.
Detection is achieved when a peak is found in the correlation results exceeding a detection threshold.
Figure 2 illustrates a simple radio channel environment. In this environment, the received RACH
preamble is offset by the channel delays associated with each path. The offset is determined by the
round trip time from the BS to the UE. Figure 3 shows the effect of path delays on the transmitted
preamble. When a signal appears at the BS, it is delayed relative to the start of the slot by a delay equal
to twice the path delay to the UE. In the RACH, the amount of this delay becomes the search window.
To correlate for the full RACH preamble, the RACH has to perform a correlation over 4096 samples,
beginning at every sample within the search window, and compare the result against the 16 possible
preamble sequences. The RACH preamble detection is, therefore, performed over a period of the search
window + 4096 chips.
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According to the 3GPP W-CDMA specification, section 6 of the 3GPP specification TS25.214 V6.11.0
Physical Layer Procedures (FDD) (Release 6)), the RACH must respond to a detected preamble with an
AICH response. Failure to receive a response causes the UE to increase its transmission power and
resend the RACH preamble.
Figure Top x-ref 2
4
Path
Pat
h
UE
BS
Path 2
th 3
Pa
ds629_02_062107
Figure 2: Simple Radio Channel Environment
Figure Top x-ref 3
1.5 Access Slots = 7680 Chips

1 Access Slot = 5120 Chips
4096 Chips
Transmitted
Sequence at
Chip Rate
Recevied
Data at
Sample Rate
Path Delay
Path Delay
Search Window
(4096 + Window) Chips
AICH
Response Time
ds629_03_062707
Figure 3: Transmitted Preamble Delay

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The received RACH preamble is generally subjected to multipath delays and has multiple correlation
peaks in the received stream (Figure 4), producing a power delay profile (PDP). The RACH has to
identify each of these individual peaks and pass the power and delay information associated with each
to the Searcher, providing the Searcher with an initial estimate of the channel in which it is trying to
track transmitted data.
Figure Top x-ref 4
Power
Path 1
Path 3
Path 2
Path 4
Delay
Window Delay
Search Window
ds629_04_062107
Figure 4: Simple Radio Channel Power Delay Profile
System Operation
Overview
The RACH consists of two parts: a RACH core, available through CORE Generator software, and a
reference design incorporating the RACH core into a post-processing algorithm for the correlation
results produced by the core. The RACH reference design is delivered as VHDL source code along with
the RACH core.
The RACH 's overall structure is illustrated in Figure 5, showing the VHDL source files comprising the
reference design, and the RACH core generated by the CORE Generator software.
The RACH core performs the correlations operation on the received antenna data. The core is designed
to process these correlations in the most efficient manner possible.
The RACH reference designs role is to reduce the load on the DSP by filtering and sorting the results
from the core. The reference design is also responsible for calculating the non-coherent and coherent
power in the RACH correlation results. Furthermore, the reference design produces an AICH recommendation for the processor to use in determining the next AICH signal to send.
The further role of the RACH reference design is to act as a bridge between the RACH core and the DSP.
Therefore, the reference design uses OCP-compatible interfaces for connecting with the system bus.
The user can edit the reference design source code to change the system bus the RACH uses to connect
to the DSP. It is also possible to change the AICH decision algorithm and allow the possibility of implementing a proprietary selection algorithm.
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Figure Top x-ref 5
RACH
Config
Interface
rach_3gpp_config
_regs.vhd
RACH Preamble
Detector Core
Antenna
Interface
rach_3gpp_non_coh_add.vhd
Bypass if
c_min_coh_win_len = 256
rach_3gpp_non_coh_ram.vhd
rach_3gpp_sorter.vhd
rach_3gpp
_aich.vhd
AICH
recommendation
rach_3gpp_ocp
_result_rd.vhd
rach_3gpp_preamble_sort.vhd
RACH
Result
Interface
ds629_05_072607
Figure 5: RACH Inner and Outer Core Structure
RACH Reference Design

The RACH reference design is supplied as unencrypted VHDL files, allowing the user to implement
proprietary versions of the RACH detection algorithm. The supplies, standard reference design takes
the raw correlation results from the RACH core and compares them to a finger threshold to determine
if the correlation peak is large enough to be considered as a matching finger. Matching fingers are then
sorted on a per preamble basis, along with the offset associated with them.
The sorted fingers are then combined to generate a figure for the total power contained in each
preamble. This power estimate is then compared to an AICH detection threshold to determine if the
preamble contains enough power to be considered as being a detected preamble. Detected preambles
are then indicated to the DSP. The DSP also has access to the n largest fingers for each preamble via the
OCP RACH Result (RR) interface. This access allows the processor to access the size of each finger and
its offset. The offset can then be used to set up the searcher.

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The VHDL blocks provided for the reference design are listed in Table 2 and shown in Figure 5.
Table 2: Reference Design Blocks
Block
Description
rach_3gpp_ref_v1_0_main.vhd
Top-level reference design.
rach_3gpp_sorter.vhd
Implements the sorting of all of the results from the RACH core.
rach_3gpp_preamble_sort.vhd
Performs RACH result sorting for each preamble. One instance is used
per preamble. This block is instantiated from within
rach_3gpp_sorter.vhd.
rach_3gpp_non_coh_add.vhd:
Implements non-coherent accumulation of the coherent sub-windows

generated by the RACH core. If the RACH core is selected without
non-coherent accumulation enabled, this block is not necessary. This
block incorporates the I2 + Q2 calculation.
rach_3gpp_non_coh_ram.vhd
RAM required to store the partial non-coherent results during

non-coherent accumulation.
rach_3gpp_power_calc.vhd
Performs the I2 + Q2 calculation for the power calculation.
rach_3gpp_aich.vhd
Implements the AICH recommendation.
rach_3gpp_ocp_result_rd.vhd
Decodes the OCP reads of the RACH results.
rach_3gpp_config_regs.vhd
Decodes the OCP writes of the RACH configuration registers
The interface to the RACH reference design is shown in Figure 6. Connection to the reference design is
achieved using OCP-compatible interfaces. The reference VHDL can be edited to implement alternative bus architectures.
When the RACH reference design is generated via CORE Generator software, the parameters which
apply to the reference design are created as a package of constants and are included in the reference
design. Adjusting the parameters requires the core to be regenerated.
Port Descriptions
The 3GPP RACH Preamble Detector is designed to be used as co-processor to a general purpose
processor or DSP. OCP-compatible interfaces are used to provide a consistent interface adaptable to
many system bus types (refer to Register and Memory Maps for details on data transferred across the
OCP data and address signals).
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Port Diagrams
Figure 6 shows the top-level interface to the reference design (fields within the OCP port are shown in
brackets).
Figure Top x-ref 6
CLK
CE
RC_MCMD
3GPP
RACH
Preamble
Detector
Reference
Design
RC_MADDR
RC_MDATA
RC_SCMDACCEPT
RC_SINTERRUPT
RR_MCMD
RR_MADDR
RR_SDATA
RR_SDATAINFO
RR_SRESP
Host Result
OCP Interface
Host Configuration
OCP Interface
MRESET
Antenna Interface
RR_SCMDACCEPT
A_MCMD
RR_SINTERRUPT
A_MDATA
A_MDATAINFO
A_SCMDACCEPT
A_SINTERRUPT
ds629_06_072407
Figure 6: 3GPP RACH Preamble Detector Reference Ports

Port Descriptions and Definitions
Clocks and Reset
Table 3 lists the clock and reset for the 3GPP RACH Preamble Detector core.
Table 3: Clock and Reset(1)
Port Name
I/O
Width
Description
CLK
Chip Rate Processing Clock. Used to synchronize all

OCP-compatible interfaces
CE
Clock Enable (optional). Clock Enable halts all internal

clocks when asserted.(2)
RESET
Reset Active High Synchronous Reset.(3)
Notes:
1. Clock and Reset is common to all blocks.
2. CE is not defined in OCP specification. Asserting CE during OCP accesses could lead to the block not
complying with OCP specification.
3. OCP reset is specified as being active Low. Active High reset is adopted to be compatible with other LogiCORE
modules. Place an inverter before reset if using OCP reset signal.

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RACH Configuration Interface
The core OCP interface port definitions are listed Table 4.
Table 4: RACH Configuration OCP Interface Ports(1)

Port Name
RC_MCMD
I/O
Width
Description
OCP Master Command. Only supports the following
commands:
0xb000: Idle
0xb001: Write
RC_ADDR
OCP Master Address.(2)
RC_MDATA
32
OCP Master Data.(2)
RC_SCMDACCEPT
OCP Slave Command Accept. Indicates Slave has accept

command from master.
RC_SINTERRUPT
OCP Slave Interrupt. Bit 0 indicates that core is ready for

another configuration to be written.
Notes:
1. OCP Interface for writing RACH configuration registers.
2. See "Antenna Interface Register Map" on page 15.
Antenna Data Interface
Table 5 defines the antenna data OCP interface ports for the core.
Table 5: Antenna Data OCP Interface Ports(1)

Port Name
A_MCMD
I/O
Width
Description
OCP Master Command. Only supports the following
commands:
0xb000: Idle
0xb001: Write
A_MDATA
16
Antenna Data. Consists of I/Q data components.(2)
A_MDATAINFO
OCP Master Data Info. Bit 0 is set when sample data is

synchronized to global sync signal. Only set for data on
antenna 0.
A_SCMDACCEPT
OCP Slave Command Accept. Indicates Slave has accept

command from master.
A_SINTERRUPT
OCP Slave Interrupt. Indicates that slave is expecting

sample synchronized to global sync signal. Cleared when
data written with A_MDATAINFO[0] is set.
Notes:
1. Antenna data is time-interleaved on the interface.
2. See "Antenna Interface Register Map" on page 15.
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RACH Results Interface
Table 6 defines the RACH results OCP interface ports.
Table 6: RACH Results OCP Interface Ports

Port Name
RR_MCMD
I/O
Width
Description
OCP Master Command. Valid commands are:
0b000: Idle
0b010: Read
RR_MADDR
23
OCP Master Address.(1)
RR_SDATA
18
OCP Data.(1)
RR_SDATAINFO
OCP Data Information. Bit 0 indicates that saturation has

occurred.
RR_SRESP
OCP Slave Response. Valid values are:

0b00: null response
0b01: data valid response
RR_SCMDACCEPT
OCP Command Accept.
RR_SINTERRUPT
OCP Slave Interrupt. Indicates Completion of a RACH

search and results can be read from results memory. Cleared
by reading memory.
Note:
1. See "RACH Results Memory Map" on page 15.
RACH Core
Internal to the RACH Preamble Detector is the RACH core. The RACH is a CORE Generator core
implementing the scrambling-code generation, correlation, and preamble detection. This core is configurable using a subset of the parameters listed in Generation and Customization. Variation of the
parameters controls the size of the search window that the core is designed to process and the number
of sub-windows which the correlation can be broken down into, allowing for non-coherent accumulation across the window (see Coherent and Non-Coherent Processing for details on non-coherent
processing). Changes to this core can only be achieved by adjusting the parameters in the CORE
Generator GUI.
The architecture of this core is based on a fully streamed correlation of the incoming antenna data. This
architecture is ideally suited to femto- and pico-cell RACH implementations, as it minimizes the
amount of hardware resources required to perform the RACH detection.
Preamble detection is achieved using a fully streamed fast-Hadamard transform (FHT). The FHT is the
optimal method of decoding the RACH correlation into the original RACH preambles. To enable
non-coherent accumulation, the FHT can access the correlation results throughout the correlation
window. Thus, a set of preamble results can be produced for a sub-window. These correlation results
can be accumulated externally to the core to produce a non-coherent accumulation. This non-coherent
accumulation takes place within the reference design.
The RACH core is based on an implementation for a single antenna with an oversample rate of two
samples per chip. This combination provides the optimal use of hardware within the core. To achieve
higher oversample rates and additional antennas, multiple instances of the RACH core are instantiated

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inside the RACH reference design. Using separate instances per antenna enables the user to alter the
algorithm used to combine the antenna results to form a RACH detection decision.
Coherent and Non-Coherent Processing
There are two modes of correlation:
Coherent. For coherent processing, all of the repetitions of the preamble are added across the full
4096 bits prior to decoding with the FHT and calculating the magnitude. Coherent processing is the
simplest method to implement since the partial result just accumulates until all the bits are seen.
Non-coherent: For non-coherent processing, the 4096-bit preamble is split into equally sized
windows (size selected by the DSP). Each of these windows is coherently summed, and the
magnitude of the results taken. These magnitudes are then summed to produce the final power
density spectrum. This method uses the same hardware as coherent detection. However, after each
coherence window is completed, the partial result stored is reset, and the FHT is applied to the
correlation results in that window. The magnitudes of each preamble produced at the end of the
window is stored and accumulated in RAM following the FHT. After all the windows are
correlated, the threshold is compared against the non-coherent results stored in the RAM.
Port Descriptions
The RACH core produced by CORE Generator software has the interface shown in Figure 7.
Knowledge of the interface is only required if the user is intending to edit the outer reference design. If
the standard RACH detection algorithm is used, the interface to this core is made via that reference
wrapper.
Core Port Diagram
Figure Top x-ref 7
CLK
MRESET
CE
scramble_code_init
coherence_win_len
Configuration Interface
Config values driven by
registers in the
reference design
3GPP
RACH Preamble
Detector
Core
fht_data_out_q
fht_data_out_i
fht_data_out_valid
fht_data_out_sync
Result Interface
Returns the
correlation results
from the RACH
last_fht_running
sample_write
Antenna Interface
I/Q Data Supplied
from the Antenna
antenna_data_Q
antenna_data_I
slot_sync
sample_accept
ds629_14_072407
Figure 7: 3GPP RACH Preamble Detector Core Ports Diagram
10
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Core Port Names and Descriptions
Table 7: Core Port Names and Descriptions
Port Name
I/O
Width
Description
CLK
Chip Rate Processing Clock. Same as Reference Design Clock.
CE
Clock Enable (optional). Clock Enable halts all internal clocks when
asserted.(2)
Sclr
Reset Active High Synchronous Reset.(3)
Scramble_code_init
25
Scramble Code initialization: Connects to the register in the

reference design configuration interface to pass the scramble code
initialization to the RACH core.
Coherence_win_len
Coherence Window Length: Connects to the Coherence Window

Length register in the RACH reference design to pass the
dynamically selected coherent window length to the RACH core. The
value passed to the core is 1/16th of the value in the reference
register.
Sample_write
Sample Write Strobe: Indicates new antenna data samples.

Equivalent to A_mcmd in the reference design.
Antenna_data_q
4-8
Antenna Data input: Antenna sample for Q-channel. Extracted

from Antenna OCP interface in the reference interface.
Antenna_data_i
4-8
Antenna Data input: Antenna sample for I-channel. Extracted from

Antenna OCP interface in the reference interface.
Slot_sync
Slot Synchronization: Indicates the start of a RACH slot and

initiates RACH processing.
Sample_accept
Sample Accept: Acknowledgement of antenna sample. Used to

generate the A_SCMDACCEPT signal in the reference designs
OCP interface.
Fht_data_out_valid
FHT Data Valid: Indicates that the RACH core is outputting a valid
PDP. The RACH core produces an unfiltered PDP.
Fht_data_out_sync
FHT Data Sync: Indicates that the RACH core is outputting the first
preamble result of a PDP.
Fht_data_out_q
16-20
FHT Data Q: The Q-channel output of the RACH core. I2 + Q2

combination of the PDP is performed in the RACH reference design.
Fht_data_out_i
16-20
FHT Data I: The I-channel output of the RACH core. I2 + Q2

combination of the PDP is performed in the RACH reference design.
Last_fht_running

Last PDP Output: Indicates that the PDP being output is the final
one for the current search window. Used by the reference design
during non-coherent processing to complete non-coherent
processing.
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11
Generation and Customization

The 3GPP RACH Preamble Detector can be generated and parameterized through the customize
option in the CORE Generator software.
XCO Parameters
Table 8: XCO Parameters
XCO Parameter
Clock_Enable
true, false
Description
true = component has CE pin
false = component does not have CE pin
Oversample_Rate
1, 2, 4
Number of samples per chip in antenna data stream. The

number of samples per chip times the search window size
is restricted to a maximum of 1024.
Antennae
1 ...16
Number of Antennae. Must be smaller or equal to number

of clocks per sample, for example, Clock_Rate divided by
Oversample_Rate.
Quantization
48
Number of bits used to represent samples.
Maximum_Search_Window
_Size
1-512
Sets the maximum number of chips over which a RACH

search can be performed. Effectively sets the operating
radius for the cell. Targeted at pico and femto applications.
Clock_Rate
Minimum_Coherent_Window
_Size
Number_of_Results_Per
_Preamble
Power_Shift
12
Values
32 128
Number of clock cycles available to process one chip.
32, 64, 128, 256,

512, 1024, 2048,
4096
Sets the number of chips involved in the coherent portion

of a non-coherent summation. Selecting 4096 chips
generates a fully coherent correlator.
1-32
Selects the number of sorted peaks which are available at

the results interface for the DSP.
0-18
Determines the output power scaling of the RACH PDP

fingers.
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Register and Memory Maps

RACH Configuration Interface Map
The RACH core is controlled by a configuration interface. The RC_MADDR input is used to access the
configuration registers via the OCP-compatible interface. The interface register map is defined in
Table 9.
Table 9: RACH Configuration Register Map

Address
Description
0x00
RACH Search Window Length Register. Defines the dynamic length of the search
window used in the RACH.
0x04
RACH Coherence Window Length Register. Defines the Length the coherent window
uses in non-coherent operation.
0x08
RACH Scrambling Code Register. Configures scrambling code used in the RACH
receiver.
0x0C
RACH Preamble Mask Register. Register to mask out certain Preamble results from
the AICH recommendation.
0x10
AICH Threshold Register. Configures Threshold which must be passed to qualify for
recommendation for an AICH.
0x14
Finger Threshold Register. Configures Threshold which must be passed to count as a

finger, and hence contribute to the AICH.
Table 10: RACH Window Length Register (RC_MADDR = 0x00)
Range
Field
31:10
RSVD
9:0
SEARCH_WIN
Description
Reserved. Set to 0.
Search Window Length. This field dynamically controls the
number of chips the RACH search is performed over and is
restricted to between 1 and the
Maximum_Search_Window_Size XCO parameter.
Table 11: RACH Coherence Window Length Register (RC_MADDR = 0x04)
Range
Field
31:13
RSVD
12:0

COH_WIN
Description
Reserved. Set to 0.
Coherence Window Length. This field dynamically controls the
number of chips combined in the coherent portion of a
non-coherent search. Valid values are 32, 64, 128, 256, 512,
1024, 2048, 4096. This value must be greater than the minimum
defined in the Minimum_Coherent_Window_Size XCO
parameter. 4096 indicates a fully coherent operation.
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13
Table 12: RACH Scrambling Code Register (RC_MADDR = 0x08)
Range
Field
31:25
RSVD
24:0
SCRAM_CODE
Description
Reserved. Set to 0.
Scrambling Code. Defines the 25-bit scrambling code
initialization value used to generate the de-scrambling code
internally.
Table 13: RACH Preamble Mask Register (RC_MADDR = 0x0C)
range
field
31:16
RSVD
15:0
PRMBL_MSK
Description
Reserved. Set to 0.
Preamble Mask. 15-bit register defining valid preambles in the
sector. Only enabled preambles are considered for AICH
recommendation.
Table 14: RACH AICH Threshold Register (RC_ADDR = 0x10)
Range
Field
31:16
RSVD
15:0
AICH_THRSH
Description
Reserved. Set to 0.
AICH Threshold. Defines the power which a RACH PDP must
contain in order to be considered for an AICH recommendation.
The total power is the sum of all the fingers in the PDP. If the PDP
is larger than this threshold, the preamble is marked as detected.
Table 15: RACH Finger Threshold Register (RC_ADDR = 0x14)
range
Field
31:16
RSVD
15:0
14
FNGR_THRSH
Description
Reserved. Set to 0.
FNGR Threshold. Defines the power which a finger must have
to be included in the RACH PDP. Only fingers exceeding this
threshold are included in the total power calculation to determine
AICH.
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Antenna Interface Register Map

Table 16: Antenna Data (A_MDATA[15:0])
Range
Field
Description
15
QDATA
Q Component of Sample(1). Valid values are 2Quantization to

+2Quantization-11.
IDATA
I Component of Sample(1). Valid values are 2Quantization to

+2Quantization-11.
Note:
1. I and Q antenna data is written in parallel to the RACH.
RACH Results Memory Map

The fingers comprising the RACH PDPs generated by the core are filtered and sorted in the reference
design. The set of largest fingers are stored in the RACH result memory, where the number of fingers in
each set is determined by the XCO parameter, Number_of_Results_Per_Preamble. This memory can be
accessed via the RACH result interface, giving the processor access to the data used in forming the
AICH recommendation.
Table 17: RACH Results Address: RR_MADDR[10:0](1)
Range
10
Field
Width
Description
PREAMBLE
RACH Preamble Identifier. Specifies

which of the 16 Preambles the results are
being requested for.
DLY
10
RACH Finger Identifier. Specifies which

Preamble finger is being requested.
Fingers are sorted in descending order,
with the largest finger appearing at
address 0x00.
WORD
ALLIGNMENT
OCP Word Alignment. Bits set to 0.
Note:
1. Address space is configured for the maximum number of fingers per preamble. Unused bits for smaller designs
should be set to 0.
Table 18: RACH Results Data: RR_MDATA[25:0](1)
Range
Field
Width
Description
25
10
POWER
16
Power of Result Finger. Maximum value is determined by

the power-shift XCO parameter, which also determines
saturation value for power calculation.
DLY
10
Delay Offset of Result. Maximum value is

Maximum_Search_Window_Size Oversample_Rate 1
up to a maximum of 1023.
Notes:
1. Returns power and delay for each finger in a given PDP.

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15
Timing Diagrams
The 3GPP RACH Preamble Detector uses OCP-v2.0-compatible interfaces for each of the main interfaces, allowing the interfaces to be easily adapted to a variety of bus protocols.
RACH Reference Timing

The Reference design has three OCP-compatible ports. The timing diagrams for these ports are shown
in Figure 8 through Figure 14.
RACH Configuration Interface Timing
The RACH configuration interface is a write-only, OCP-compatible interface used to write to the RACH
control registers. These registers can be updated at any time. However, the change only takes effect at
the start of the next slot on antenna 0. The registers are written with configuration data as specified in
the register map (see "RACH Configuration Interface Map" on page 13).
Figure 8 shows the timing when updating a control register value in the RACH.
Figure Top x-ref 8
CLK
RC_MCMD
WR
WR
WR
WR
0X00
0X04
0X08
0X0C
IDLE
RC_MADDR
IDLE
IDLE
WR
WR
WR
WR
IDLE
0X00
0X04
0X08
0X0C
RC_MDATA
RC_SCMDACCEPT
ds629_07_062607
Figure 8: RACH Configuration Timing
Antenna Interface Timing

The antenna interface is a write-only, OCP-compatible interface. Data is written as a block starting with
the smallest number antenna, repeating every sample period (Figure 9). The signal A_SCMDACCEPT
indicates when antenna data is expected.
The timing is dependent on a number of the core parameters. The number of antennas specifies the
length of the burst transferred. The sample period is determined by the core's clock rate divided by the
oversample rate. In this example (Figure 9), the number of antennas is 4, the clock rate is 20, and the
oversample rate is 2, giving a sample period of 10 clock cycles.
Figure Top x-ref 9
CLK
A_MCMD
A_MDATA
A_SCMDACCEPT
IDLE
WR
WR WR WR
A0
A1
A2
IDLE
A3
WR WR WR WR IDLE
A0
A1
A2
A3
Sample Period
ds629_08_062607
Figure 9: Antenna Interface Basic Transfer
16
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The signal A_SCMDACCEPT forces master data transfers to synchronize to the internal processing rate of
the RACH (Figure 10). If the master writes data to the core early, then A_SCMDACCEPT is not asserted
until the cycle count reaches the correct value, thus throttling the master data transfer rate.
Figure Top x-ref 10
CLK
A_MCMD
IDLE
A_MDATA
WR
WR
WR
WR
A0
A1
A2
A3
IDLE
A_SCMDACCEPT
ds629_09_062607
Figure 10: Core Throttling Master Transfer Rate

Figure Top x-ref 11
Figure 10 illustrates the case of the master throttling the core processing rate. In this case, the master
does not supply data on the expected clock cycle and the core is stalled. Because processing in the core
is stalled, additional clock cycles are required to meet the real-time processing requirement of the core.
Figure 11 shows the synchronization of the core to the 3GPP framing references. The signal
A_MDATAINFO is asserted when writing the first sample of antenna 0 when the frame sync occurs. The
signal A_SINTERRUPT indicates that the core is expecting the frame synchronization on A_MDATAINFO
and occurs at the same time the core is synchronized.
Figure Top x-ref 12
CLK
A_MCMD
A_MDATA
IDLE
WR
WR
WR
WR
A0
A1
A2
A3
IDLE
WR
WR
WR
WR
A0
A1
A2
A3
IDLE
A_SCMDACCEPT
A_MDATAINFO
A_SINTERRUPT
ds629_10_062607
Figure 11: Antenna Data Frame Synchronization

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17
RACH Results Interface Timing

The RACH results interface is a pipelined read-only, OCP-compatible interface. The signal
RR_SINTERRUPT is used to indicate when a RCH detection completes and the results can be read. The
first read from the memory clears the interrupt.
The results are read for each PDP using the address specified in the memory map (see "RACH Results
Memory Map" on page 15). After issuing an OCP read command, there is a three-clock latency from
RR_SCMDACCEPT being asserted to the data valid as indicated via the signal RR_SRESP. See Figure 12.
Figure Top x-ref 13
CLK
RR_SINTERRUPT
RR_MCMD
IDLE
RR_MADDR
RD
RD
RD
RD
A0
A1
A2
A3
IDLE
RR_SCMDACCEPT
3 Clock Latency
RR_SRESP
RR_SDATA
NULL
VALID VALID NULL VALID VALID
D0
D1
D2
NULL
D3
ds629_11_062607
Figure 12: RACH Results Timing
RACH Core Timing

Antenna Interface Timing
The RACH core has two interfaces that the reference design wraps around. Knowledge of these interfaces is required when altering the RACH reference design to ensure correct data transfer data to the
core.
Each RACH core is responsible for processing a single antennas worth of data. The interface to the core
is similar to the interface for the RACH reference antenna, except that the antenna data is no longer a
block of time-multiplexed antenna data, but rather the demultiplexed data for a single antenna.
Furthermore, the write instruction has been reduced to a single bit write flag (Figure 13).
18
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Figure Top x-ref 14
CLK
Sample Period
SAMPLE_WRITE
ANTENNA_DATA_Q
ANTENNA_DATA_I
SLOT_SYNC
SAMPLE_ACCEPT
ds629_12_062607
Figure 13: RACH Core Basic Antenna Data Transfer

Figure Top x-ref 15
RACH Results Interface Timing

The RACH core produces a correlation result for each of the 16 possible preambles, for every sample in
the search window, and for both I and Q data channels. This data is streamed out of the RACH
(Figure 14) with results appearing for preamble 0 through preamble 15 in a burst of 16 clock cycles. The
blocks of preamble data follow the order: P0, P1, P2 ... Pn, where P0 is the RACH search result starting
at sample 0, and where Pn consists of the In result and Qn result.
Figure Top x-ref 16
CLK
FHT_DATA_OUT
P0
P1
P15
P0
P1
P15
P0
P1
P15
FHT_DATA_OUT_VALID
FHT_DATA_OUT_SYNC
FINAL_FHT_OUT
ds629_13_062607
Figure 14: RACH Core Results Interface

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19
Performance Characteristics
Table 19 through Table 21 show the performance of the 3GPP RACH Preamble Detector core in terms of
resource usage and maximum achieved operating frequency for different device families. The resource
count and speed of the core can change depending on the surrounding circuitry of the user design.
Therefore, these figures should be taken only as a guide.
The tool settings to achieve these results were as follows and were obtained with ISE v9.2i tools:
map -c 1 -ol high
par -ol high
Note: Tool settings can have a significant effect on area use and speed. The Xilinx Xplorer script can be
used to find the optimal settings.
Table 19: Spartan3A-DSP Engine Resource Utilization
XCO Parameter
Case 1 Femto Cell
Case 2 Pico Cell
Clock_Enable
False
False
Minimum_Coherent_Window_Size
4096
512
Maximum_Search_Window_Size
16
128
Quantization
XC3SD3400A
XC3SD3400A
Slices(1)
663
1193
LUTs
881
1376
FFs
772
1742
Block RAMs (18k)
DSP blocks
155
145
Utilization
Xilinx device
Maximum clock
frequency(2)
Notes:
1. Area and maximum clock frequencies are provided as a guide and can vary with new releases of the Xilinx
implementation tools.
2. Maximum clock frequencies are shown in MHz for -4 parts. Clock frequency does not take jitter into account
and should be de-rated by an amount appropriate to the clock source jitter specification.
20
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Table 20: Virtex-4 Engine Resource Utilization
XCO Parameter
Case 1 Femto Cell
Case 2 Pico Cell
Clock_Enable
False
False
4096
512
32
128
Quantization
XC4VLX15
XC4VLX15
Utilization
Xilinx device
Slices(1)
417
588
LUTs
507
740
FFs
608
873
Block RAMs (18k)

DSP blocks
Maximum clock frequency(2)
283/310
266/310
Notes:
1. Area and maximum clock frequencies are provided as a guide and can vary with new releases of the Xilinx
2. Maximum clock frequencies are shown in MHz for -10/-12 parts. Clock frequency does not take jitter into
account and should be de-rated by an amount appropriate to the clock source jitter specification.
Table 21: Virtex-5 SP Engine Resource Utilization
XCO Parameter
Case 1 Femto Cell
Case 2 Pico Cell
Clock_Enable
False
False
4096
512
32
128
Quantization
XC5VLX30
XC5VLX30
796
1128
532
726
610
871
Utilization
Xilinx device
LUT/FF
Pairs(1)
LUTs
FFs
Total Block
RAMs(3)
Block RAMs (36k)
Block RAMs (18k)
DSP blocks
297/310
251/320
Maximum clock
frequency(1,2)
Notes:
1. Area and maximum clock frequencies are provided as a guide. They may vary with new releases of the Xilinx
2. Maximum clock frequencies are shown in MHz for -1/-3 parts. Clock frequency does not take jitter into account
and should be derated by an amount appropriate to the clock-source jitter specification.
3. Represents the total number of 36k block RAMs used when map is run. In reality, two 18k block RAM primitives
can usually be packed together, giving an absolute minimum total block RAM usage of block RAMs (36k) +
(block RAMs (18k) /2) (rounded up).

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21
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
The 3GPP RACH Preamble Detector core is provided under the SignOnce IP Site License and can be
generated using the Xilinx CORE Generator software v9.2i or higher. The CORE Generator software is
shipped with Xilinx ISE Foundation Series Development software.
After purchase, the core may be downloaded from the Xilinx IP Center for use with the Xilinx CORE
Generator software v9.2i and higher. The Xilinx CORE Generator software is bundled with the ISE
Foundation software at no additional charge.
Contact your local Xilinx sales representative for pricing and availability of additional Xilinx
LogiCORE modules and software. Information about additional Xilinx LogiCORE modules is
available on the Xilinx IP Center.
Revision History
22
Date
Version
08/08/07
1.1
Revision
Initial Xilinx release
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Rach 3gpp Ds629

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3GPP RACH Preamble

The 3GPP RACH Preamble Detector core provides an

Figure 1 shows a typical use of the 3GPP RACH

During operation, the RACH runs on every antenna on

Design scales with following parameters to

- Search window size

For use with Xilinx CORE Generator software

Figure 1: Typical Application

DS629 August 8, 2007

3GPP RACH Preamble Detector v1.0

Table 1: Hadamard Code

DS629 August 8, 2007

3GPP RACH Preamble Detector v1.0

Figure 2: Simple Radio Channel Environment

Figure Top x-ref 3

1.5 Access Slots = 7680 Chips

Figure 3: Transmitted Preamble Delay

DS629 August 8, 2007

3GPP RACH Preamble Detector v1.0

Figure 4: Simple Radio Channel Power Delay Profile

DS629 August 8, 2007

3GPP RACH Preamble Detector v1.0

Figure Top x-ref 5

Figure 5: RACH Inner and Outer Core Structure

RACH Reference Design

DS629 August 8, 2007

3GPP RACH Preamble Detector v1.0

Top-level reference design.

Implements non-coherent accumulation of the coherent sub-windows

RAM required to store the partial non-coherent results during

Performs the I2 + Q2 calculation for the power calculation.

Implements the AICH recommendation.

Decodes the OCP reads of the RACH results.

Decodes the OCP writes of the RACH configuration registers

DS629 August 8, 2007

3GPP RACH Preamble Detector v1.0

Figure 6: 3GPP RACH Preamble Detector Reference Ports

Chip Rate Processing Clock. Used to synchronize all

Clock Enable (optional). Clock Enable halts all internal

Reset Active High Synchronous Reset.(3)

DS629 August 8, 2007

3GPP RACH Preamble Detector v1.0

RACH Configuration Interface

The core OCP interface port definitions are listed Table 4.

Table 4: RACH Configuration OCP Interface Ports(1)

OCP Master Address.(2)

OCP Master Data.(2)

OCP Slave Command Accept. Indicates Slave has accept

OCP Slave Interrupt. Bit 0 indicates that core is ready for

Table 5: Antenna Data OCP Interface Ports(1)

Antenna Data. Consists of I/Q data components.(2)

OCP Master Data Info. Bit 0 is set when sample data is

OCP Slave Command Accept. Indicates Slave has accept

OCP Slave Interrupt. Indicates that slave is expecting

DS629 August 8, 2007

3GPP RACH Preamble Detector v1.0

RACH Results Interface

Table 6 defines the RACH results OCP interface ports.

Table 6: RACH Results OCP Interface Ports

OCP Master Address.(1)

OCP Data Information. Bit 0 indicates that saturation has

OCP Slave Response. Valid values are:

OCP Command Accept.