Strain Review

ANRV380-MR39-09
ARI
ANNUAL
REVIEWS
27 May 2009
15:5
Further
Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

Access provided by Indian Institute of Technology - Kanpur on 10/11/15. For personal use only.
Click here for quick links to

Annual Reviews content online,
including:
Other articles in this volume
Top cited articles
Top downloaded articles
Our comprehensive search
Strain: A Solution for Higher

Carrier Mobility in Nanoscale
MOSFETs
Min Chu, Yongke Sun, Umamaheswari Aghoram,
and Scott E. Thompson
Department of Electrical and Computer Engineering, University of Florida, Gainesville,
Florida; email: chumin1@u.edu, yksun@tec.u.edu, uma@u.edu, thompson@ece.u.edu
Corresponding author
Annu. Rev. Mater. Res. 2009. 39:20329
Key Words
The Annual Review of Materials Research is online at

matsci.annualreviews.org
stress, uniaxial, biaxial, band structure, effective mass, scattering
This articles doi:

10.1146/annurev-matsci-082908-145312
Abstract
c 2009 by Annual Reviews.

Copyright
All rights reserved
1531-7331/09/0804-0203$20.00
Metal-oxide-semiconductor eld-effect transistors (MOSFETs) have shown

impressive performance improvements over the past 10 years by incorporating strained silicon (Si) technology. This review gives an overview of the
impact of strain on carrier mobility in Si n- and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier
repopulation, and altered conductivity effective mass and scattering rate.
Different surface orientations, channel directions, and gate electric elds
are included for a fully theoretical understanding. The results are used to
predict strain-enhanced silicon-on-insulator (SOI) and multigate device performance, mainly focusing on potential 22-nm and beyond device options
such as double-gate and trigate n eld-effect transistor (FinFET) structures.
Insights into strain-enhanced potential future channel materials (SiGe, Ge,
and GaAs) are also summarized. Finally, recent technology nodes with strain
engineering are reviewed, and the future developing trend is given.
203
ANRV380-MR39-09
ARI
27 May 2009
15:5
STRAIN ENGINEERING IN STATE-OF-THE-ART MOSFETs

SCE: short-channel
effect

MOSFET: metaloxide-semiconductor
eld-effect transistor
Introduction: Why Strain?

In the past three decades, scaling of MOSFETs has resulted in new technology generations every two to three years with doubled logic device density, lowered cost per logic function, and
increased chip performance (1, pp. 18; 2, 3). However, as device dimension enters into the deepsubmicrometer regime, many physical phenomena such as short-channel effect (SCE), velocity
saturation, high leakage current, and dielectric breakdown limit the benets of conventional scaling (48). To continuously improve device performance, new device structures, new materials, and
strain engineering have been proposed and investigated. Among all these new technologies, strain
engineering during the past decade has been the dominant technique to enhance device performance while providing a low-cost and low-risk technique by maintaining the traditional metaloxide-semiconductor eld-effect transistor (MOSFET) fabrication process. It has been conrmed
both experimentally and theoretically that strain has the potential to enable drive current enhancement of 4.5 in Si pMOSFETs and 2 in nMOSFETs (910) without a signicant increase
in leakage current. With the fourth generation (11) of strained-Si technology now in commercial
production, strain-enhanced performance and power saving are present in nearly all VLSI logic
chips manufactured today. The goal of this review is to provide a brief introduction on strain and
its role in the semiconductor industry and an in-depth discussion and physical insights into the
effect of stress on electron and hole mobility.
Brief History of Strained Semiconductors

Strain has been a topic of interest in semiconductor research since the 1950s. Bardeen & Shockley
(12) developed deformation potential theory, which models the coupling between acoustic waves
and electrons in solids, to calculate the components of the relaxation-time tensor in terms of
the effective mass, elastic constants, and a set of deformation-potential constants. In deformation
potential theory, the strain-induced band edge shift is proportional to the strain tensor: E =

i j i j e i j , where ij are the deformation potentials. Herring & Vogt (13) generalized this theory
in 1956 to model carrier transport in strained multivalley semiconductors and summarized a set of
independent deformation potentials, d , u , and p , to characterize the conduction band valleys.
Their work ascribed the electron mobility change to electron transfer and the altered intervalley
scattering rate caused by valley energy shift. The picture of strain-enhanced hole mobility is more
complicated, owing to strong valence band warping. Thus, the hole transport under strain cannot
be simply explained by band edge shift. Band calculation methods such as the k p method (14, 15)
give more accurate valence band structure by constructing a strain Hamiltonian (16) in terms of
the angular momentum derived by symmetry consideration. In 1963, Hasegawa (17) and Hensel
& Feher (18) used this method to systematically study the valence band effective masses and
deformation potentials in strained Si. They revealed the key factors that affect the hole mobility in
semiconductorsband splitting and warping, mass change, and consequently the change of DOS,
which alters band occupation and phonon scattering. To date, deformation potential theory is still
the primary method of modeling the strained semiconductor and has proved to be successful in
explaining experimentally observed changes in device behavior under mechanical stress.
The most effective empirical method to predict device behavior under strain is by measuring
piezoresistance coefcients (-coefcients) (19). The rst experimental data on -coefcients for
n- and p-type bulk Si and Ge were obtained by Smith in 1954 (20). These data have been used
by the industry to model and predict MOSFET current enhancement under stress. However, it
is inappropriate to use them to analyze MOSFET behavior in some cases because Smiths sample
204
Chu et al.
ANRV380-MR39-09
ARI
27 May 2009
15:5
is bulk material without any surface connement effect. In 1968, Colman et al. (21) measured the
-coefcients in p-type inversion layers for the rst time. Two decades later, the rst Si n- and
pMOSFETs with biaxial stress induced by a Si1x Gex buffer layer (Figure 1a) were demonstrated
by Wesler et al. (22) in 1992 and by Nayak et al. (23, 24) in 1993, respectively. A 2.2-times
enhancement in electron mobility and a 1.5-times enhancement in hole mobility were reported.

Uniaxial stress
Tensile nitride
Compressive nitride
Gate
Gate
Stress
Stress
NMOS
Strained Si
STI
PMOS
Biaxial stress
Gate
Source
Drain
Relaxed SiGe
Substrate
Relaxed SiGe
Uniaxial stress
Biaxial stress
Figure 1
(a) Illustration of process-induced uniaxial stress on MOSFETs with a nitride capping layer and biaxial stress
with a relaxed SiGe layer. (b) Four-point and concentric ring wafer bending setup for applying uniaxial and
biaxial stress on the upper surface of the wafer.
www.annualreviews.org Strain-Enhanced MOSFETs
205
ANRV380-MR39-09
ARI
27 May 2009
15:5
Rim et al. (25) investigated pMOSFET drive current enhancement versus Ge content in Si1x Gex
layers in 1995 and measured the current enhancement for short-channel nMOSFETs in 1998 (26).
In 2005, Lee et al. (27) published a review of the history of and progress in high-mobility biaxially
strained Si, SiGe, and Ge channel MOSFETs.
Even though the predominant focus of the industry in the 1980s and 1990s was on biaxially
stressed devices, the current focus has shifted to uniaxial stress. Uniaxial stress has several advantages over biaxial stress, such as larger mobility enhancements and a smaller shift in threshold
voltage (28). Incorporating uniaxial stress to enhance MOSFET performance was rst introduced
by Ito et al. (29) and Shimizu et al. (30), who used etch-stop nitride (Figure 1a), and by Gannavaram et al. (31), who used SiGe source/drain (S/D) regions, in the early 2000s. Starting at the
90-nm technology node (32), uniaxial stress was successfully integrated into the mainstream MOSFET process ow to improve device performance (3336). Encouraged by the strain-enhanced
planar MOSFETs, researchers recently applied uniaxial stress to multigate devices (3742) with
metal gate and high-k dielectric (43, 44) as a performance booster.
These studies demonstrate that strain achieves higher device performance with extensive industrial application. In the future, the viability of novel structures and channel materials will depend
on their ability to provide device enhancement comparable to strained-Si planar MOSFETs. Thus,
strain will remain a necessary enhancement option even in these devices.

FinFET: n eldeffect transistor
Strain Definition and Piezoresistance Coefficient

To obtain insights into the underlying physics of the strain-enhanced device, it is necessary to rst
understand strain, of which the effect on current drivability is quantied as a -coefcient.
Strain and stress. Strain is dened as the percentage change of materials lattice constant. Strain
can result from phonon-induced lattice vibrations, lattice-mismatched lm growth, and applied
external mechanical stress (45). Advantageous strain reduces crystal symmetry, thus lifting band
degeneracy and causing band warping. Any strain can be decomposed into a hydrostatic strain and
two types of shear strain (46). One type of shear strain is related to the change of lengths along
the three axes, and the other is related to the rotation of the axes of an innitesimal cube. For
cubic crystals such as Si and Ge, hydrostatic strain does not break crystal symmetry and, hence,
only shifts energy levels without lifting band degeneracy. Thus, it is not important for carrier
mobility enhancement. Large hydrostatic strain is undesirable owing to band-gap narrowing,
strain relaxation, and MOSFET threshold voltage shifts. It is the shear component of strain that
causes subband splitting and affects semiconductor transport property.
Strain is introduced into the device channel preferably by applying uniaxial stress. The uniaxial stress is longitudinal when parallel to the channel and transverse when perpendicular to
the channel. Large magnitudes of uniaxial channel stress (1 GPa) are being incorporated in
p-channel devices of the 65-nm technology node (33, 34), and an even higher stress level is applied
in the 32-nm technology node, as is evident from the signicantly large saturated drive current
(1.55 mA m1 for NMOS and 1.21 mA m1 for PMOS, from Reference 11). However, because many process ow parameters are changed when fabricating strained MOSFETs, there is
some uncertainty as to whether strain alone is responsible for the performance enhancement (for
example, reduced external resistance likely plays some role). To gain condence in the effect of
strain, external mechanical stress is applied using the four-point or concentric-ring wafer bending
setup (Figure 1b). The drive current enhancement under both uniaxial and biaxial stress is studied using these setups to predict the strained device performance of MOSFETs, n eld-effect
transistors (FinFETs), and nanotubes.
206
Chu et al.
ANRV380-MR39-09
ARI
27 May 2009
15:5
Piezoresistance coefficients. The -coefcient gives straightforward experimental information

about strain-enhanced carrier mobility in semiconductors. This coefcient is dened as the normalized change in resistivity with stress, = /( ), where is the external stress and is the
resistivity, which can be calculated by = 1/(q n n + q p p). For MOSFETs under steady state,
the electron and hole densities are approximately constant; thus, the -coefcient is determined
by the change in carrier mobility with stress. The -coefcient gives us a straightforward idea
about how much drive current enhancement can be achieved under particular stress, and it has
therefore been widely used in industry to predict strained device performance (4749).
DOS: density of state

INSIGHTS INTO THE PHYSICS OF STRAINED CLASSICAL Si MOSFETs

Strain has a larger effect on the current conduction in a semiconductor than does a metal, owing to
the fact that not only do the physical dimensions change under strain but the carrier mobility can
also be enhanced. Strain effect on carrier mobility in Si MOSFETs has been intensively studied
over the past 10 years. Vogelsang & Hofmann (50, 51) divided the reasons for strained mobility
enhancement into two parts: (a) the reduction in average conductivity effective mass caused by
carrier repopulation and band warping and (b) the suppression of intervalley scattering rate caused
by subband splitting and change in density of state (DOS). This section gives an overview of how
strain affects carrier mobility, followed by a methodical discussion of the above factors.
Overview of How Strain Affects Carrier Mobility

A simple qualitative picture to explain how strain affects electron and hole mobility is developed
below. Both bulk Si and Si MOSFETs are discussed, and the difference between their strain
behaviors is explained.
n-type devices. For a bulk Si conduction band, there are six degenerate valleys with the minimum
energy located near the X point. The applied external stress shifts and splits these subbands, which
(46), where d and u are the dilation
can be calculated by ECi = d (Tr(i j )) + u (k i j k)
and shear deformation potential of the conduction band, respectively; i refers to one of the six
valleys; Tr(i j ) is the trace of the strain tensor i j ; and k is a unit vector in the reciprocal space.
For example, the <110> longitudinal tensile stress causes the energy of the 2 subband to shift
down and the energy of the 4 to shift up (using the above equation, the separation between
2 and 4 is calculated to be 40 meV under 1 GPa), resulting in electrons repopulating from
the 4 valley to the 2 valley, as shown in Figure 2a. Because the conductivity effective mass
in the 2 valley (0.19 m0 ) is smaller than that of the 4 valley (0.315 m0 , calculated using the
method in Reference 52), the repopulation into 2 causes the average effective mass to decrease
and carrier mobility to increase. The band splitting also causes the scattering rate to change.
The dominant scattering mechanisms in strained Si devices are intervalley phonon scattering (53)
and surface roughness scattering (54). As the six-folded conduction band splits, the intervalley
scattering rate becomes lower owing to the smaller DOS (45), thus resulting in a higher mobility.
A more complete discussion of phonon-limited electron mobility enhancement is provided by
Takagi et al. (55).
Strained nMOSFETs have different mobility enhancement factors from those of bulk Si. Because of the electric eld connement, 2 and 4 valleys are nondegenerated even for unstrained
Si. The energy splitting between these valleys depends on the magnitude of the electric eld and
the difference in their out-of-plane connement effective mass. For example, the (100)-surface
unstrained nMOSFET under a high electric eld, as shown in Figure 2a, electrons predominantly
207
ANRV380-MR39-09
ARI
27 May 2009
Unstrained
15:5
<110> uniaxial tension
<110> uniaxial
compression
Bulk p-type Si
Bulk n-type Si
Unstrained
4
E Light hole like

k
Heavy holes
Light holes
Split-off holes
<110> uniaxial tension
<110> uniaxial
compression
Unstrained
E
4
2
2
Si pMOSFET
e
Si nMOSFET

Unstrained
Heavy holes
E
k
Light hole like

k
Light holes
Split-off holes
Figure 2
(a) Simplied conduction band structure change under <110> uniaxial tensile stress for bulk n-type Si and Si (100)-nMOSFETs.
(b) Simplied valence band structure change under <110> uniaxial compressive stress for bulk p-type Si and Si (100)-pMOSFETs. In
the <110> direction, the heavy-hole band (top band ) becomes light-hole like around the point, and the light-hole band (bottom band )
becomes heavy-hole like. The top band is lower in energy and has smaller conductivity effective mass (0.11 m0 for 1 GPa), whereas the
bottom band is higher in energy and has larger conductivity effective mass (0.2 m0 for 1 GPa). Most of the holes repopulate into the top
band, and the mobility is thus enhanced.
occupy the lower-energy 2 valley. Thus, the effective mass change under stress is smaller than
that for bulk Si. Furthermore, surface roughness scattering dominates under typical commercialuse conditions for two-dimensional (2-D) carrier transport, which makes the current transport
in nMOSFETs more difcult to predictably model (56, 57). As a result, the electron mobility
enhancement in strained nMOSFETs is often signicantly different from that in bulk Si.
p-type devices. For unstrained bulk Si, the valence band minimum is located at the point, where
the heavy-hole and light-hole bands are degenerated. The spin-orbit split-off band is located
44 meV below and is thus not important for hole transport (46). In unstressed Si, 80% of the
holes occupy the heavy-hole band, which has an effective mass of 0.59 m0 along the <110>
direction (versus 0.15 m0 for the light-hole band). Under <110> uniaxial compression, which
can be theoretically shown to have the largest enhancement, the degeneracy is lifted, and band
warping occurs, as shown in Figure 2b. At room temperature, band warpinginduced effective
mass reduction is the dominant factor for mobility enhancement in p-type Si under uniaxial
stress (<1 GPa) (9) because the splitting between the top band and the bottom band is small
compared with the Si optical phonon energy (61.3 meV). Thus, the phonon-scattering rate change
is negligible (58).
For unstrained pMOSFETs, however, the degeneracy of the heavy hole and the light hole
is lifted by the surface electric eld connement, as shown in Figure 2b. The splitting between
the heavy-hole band and the light-hole band increases with an increasing gate eld. With typical
device operation (surface effective eld E eff 1 MV cm1 ), the summation of connement-induced
band splitting and strain-induced band splitting can be larger than the optical phonon energy. As
208
Chu et al.
ANRV380-MR39-09
ARI
27 May 2009
15:5
a result, the optical phonon-scattering reduction under strain becomes signicant and must be
considered. A detailed study on the stress-altered scattering rate is discussed further below.

Subband Splitting Under Confinement and Strain for Different Surface

Orientations and Channel Directions
The relative shift between subband energies is the dominant mechanism for the carrier repopulation and scattering rate variation in Si. As mentioned in the above subsection (Overview of How
Strain Affects Carrier Mobility), the degeneracy of conduction and valence bands is lifted owing to
the vertical electric eld. The band with the larger out-of-plane effective mass is lower in energy
according to the wave nature of electrons in conning electric potential. For example, for (100)surface nMOSFETs, the energy of 2 (mz = 0.92m0 ) is lower than that of 4 (mz = 0.19m0 ),
whereas for (110)-surface nMOSFETs, the energy of 4 (mz = 0.315m0 ) is lower than that of
2 (mz = 0.19m0 ). The band splitting between 2 and 4 is larger for a (100)-oriented device
than for a (110)-oriented device. This is shown schematically in Figure 3. For valence bands, the
top band of (100)-surface pMOSFETs has larger out-of-plane effective mass and larger in-plane
effective mass than the bottom band, whereas for (110)-surface pMOSFETs, the top band has
larger out-of-plane effective mass and smaller in-plane effective mass. In addition, the band splitting between the top band and the bottom band is larger for the (110) device than for the (100)
device (58).
The band edges also shift under applied external stress. The strain-induced band edge shift
can be either additive or subtractive to the connement-induced splitting. For conduction bands,
both biaxial tension and <110> uniaxial tension stress cause splitting that is additive to the (100)
(001) surface Si MOSFETs

<100> uniaxial
tension
<110> uniaxial
compression
(110) surface Si MOSFETs
<100> uniaxial
tension
Biaxial tension
<110> uniaxial
compression
Biaxial tension
Ec
Ec
Ev
Ev
1 Bulk Si without strain

2 Band splitting caused by electric field confinement
3 Band splitting caused by strain and electric field confinement
Figure 3
(a) (100)-oriented Si MOSFET band edge split under electric eld connement and uniaxial/biaxial stress. (b) (110)-oriented Si
MOSFET band edge split under electric eld connement and uniaxial/biaxial stress.
209
ANRV380-MR39-09
ARI
27 May 2009
15:5
connement-induced splitting, whereas the <100> uniaxial tension is more complicated because
the 4 valley splits into two energy levels, as shown in Figure 3a. For valence bands, the splitting
due to <110> uniaxial compression is additive to the (100) connement effect, and biaxial tension
is subtractive.
If the stress-induced splitting is subtractive to connement-induced splitting, the mobility
enhancement for MOSFETs is lower than for bulk Si. Thus, for MOSFETs operating under a
high electric eld to benet from strain, it is critical that the chosen stress produce splitting that
is additive to the connement effect.

Strain-Induced Band Warping

Strain breaks crystal symmetry, which not only causes the band edge energy to shift but also alters the band structure away from the energy minimum. Applying stress along a low-symmetry
axis causes more destruction of crystal symmetry and results in greater band warping than does
stress along a high-symmetry axis (45). Electron transport under strain was often analyzed by only
considering band splitting without warping (55). This treatment explains the electron mobility enhancement under <100> uniaxial stress and biaxial stress. Under <110> uniaxial stress, however,
the resulting strain contains both types of shear strain (as introduced in the section entitled Strain
and Stress), which signicantly breaks crystal symmetry. As a result, conduction band warping under <110> uniaxial stress cannot be ignored. In 1965, Hensel et al. (59) derived an expression for
the band energy of the [001] Si conduction valley with an orthorhombic strain exy by considering
the symmetry reduction by the <110> uniaxial stress:

2
h 2 (kz k0 )2 h kx2 k2y
E (k) =
+
+ h 2 e xy kx ky .
2ml
2mt
Here = (86.8 5.0)/m0 is determined experimentally. Under the distortion by the last
term, the energy surface warps, and the effective mass along <110> changes according to
m110 = mt /(1 + e xy mt ). As shown in Figure 4a, m110 decreases and m110 increases with <110>
tensile stress. Together with electron repopulation, band warping changes the average conduction effective mass, as shown in Figure 4b. Neglecting the band warping, <110> longitudinal
and transverse stresses should have the same effective mass change because both stresses cause
the same band splitting. The effective mass reduction under <110> longitudinal stress is larger
only when the band warping effect is included, which is consistent with the data from experiment
(19).
Band structure calculation shows that stress causes valence band warping, which is the primary
factor for hole mobility enhancement under <1-GPa uniaxial stress (58). Applying stress results
in the holes predominantly occupying the top band, as long as the DOS of the top band is not
signicantly smaller than that of the second band. For advantageous stress, the effective mass of
the top band decreases and thus increases mobility. The band structure change can be calculated by
the k p method (58, 60, 61). Figure 5 shows the top valence band structure under <110> uniaxial
compressive stress as provided by Sun (58). The stress effect on the valence band is anisotropic.
Also, the stress affects the band structure only near the point. Away from the center, the band
curvature is the same as for unstrained Si. With increasing stress, a greater region around the
center warps. However, unlike the case of the Si conduction band, in which the 2 effective
mass keeps decreasing with <110> stress, the valence band effective mass near the point rarely
changes with increasing stress (58). The average effective mass change of the system arises from
the fact that a greater region of the band is warped by the stress.
210
Chu et al.
ANRV380-MR39-09
ARI
27 May 2009
15:5
b
0.28
0.22
0.2
0.19
0.18
ky
0.17
0.15
m110
110
0.16
0
<110> transverse
tension
0.24
0.5
1.5
<110> uniaxial tension (GPa)
Band warping
not considered
0.22
0.2
0.18
<110> longitudinal
tension
0.16
kx
0.14
0.5
1.5
Figure 4
(a) The longitudinal and transverse effective mass of conduction band 2 valley as a function of <110> uniaxial tension. The
intersection shows the 2 subband warping under this stress, which is the reason for the change of effective mass. (b) Conduction band
average transport effective mass change under uniaxial <110> and <110> stress. The blue curve is calculated without the band
warping effect. In this case, both the longitudinal and the transverse stresses cause the same effective mass change.
Self-Consistent Simulation Procedure

Band structure is the basis on which one calculates effective mass, carrier population, and scattering rate. For accurate prediction of mobility enhancement, we need to properly calculate the band
structure. For Si MOSFETs, the gate electric eld connement restricts carrier transport in the
vertical direction, and the carriers are treated quantum mechanically as a 2-D electron/hole gas
conned in the potential well formed by the conduction/valence bands and the Si/SiO2 interface
(1). The potential in the quantum well is simulated by solving the Schrodinger
and Poisson equations self-consistently (62). Figure 6 shows the procedure. First, a reasonable starting potential
such as triangular potential is assumed. This potential is then substituted in the Schrodinger
equation to solve for the wave functions and energy levels, which are used to calculate carrier density.
The resulting carrier density is incorporated into the Poisson equation to get the potential. If the
difference between the calculated potential and the original potential is within a specic criterion,
0.05
Energy (meV)

0.26
m110
Effective mass, m0
Effective mass, m0
0.21
Channel direction
<110>
<110>
0 MPa
0.05
Greater region around

the point bends
under higher stress
500 MPa
1 GPa
0.1
1.5 GPa
<110> uniaxial compression
0.15
0.1
Wave vector (k A1)
0.1
Figure 5
Valence band ground-state warping under <110> uniaxial compressive stress. The curves have been
normalized to align at the point for easy comparison of their difference.
211
ANRV380-MR39-09
ARI
27 May 2009
15:5
h2
2mx*
n(x) =
n

No
d2
+ Hstrain + qV(x) n(x) = Enn(x)
dx2
m*d kB T
h 2
In[1 + exp(EF En / kbT)] |n(x)|2
q
d2
V(x) =
[p(x) n(x) + ND(x)]
dx2
si
n(x), V'(x)
V = V(x) V'(x) acceptable?

Yes
Final result
Figure 6
Introduction of the self-consistence calculation procedure. This method can be used to calculate with greater
accuracy the connement potential, carrier energy level, wave function, and carrier density.
the calculation is nished. If not, the calculated potential is set as the new starting potential, and
the whole process repeats. We use the self-consistent simulation procedure here to produce the
results of the following subsections.
Scattering Mechanisms
As mentioned above (see subsection: Overview of How Strain Affects Carrier Mobility), phonon
scattering and surface roughness scattering are the major scattering mechanisms in strained Si.
Phonon scattering can be categorized to acoustic phonon scattering and optical phonon scattering
based on the phase of the vibration of the two different atoms in one primitive cell. Acoustic phonon
energy is negligible compared with carrier energy, whereas optical phonon energy is approximately
61.3 meV for Si. When strain is applied, the interband optical phonon scattering reduces owing to
band splitting, and the mobility is enhanced. Surface roughness scattering represents the collision
between carriers and the interface. This interaction depends heavily on the roughness of the
interface and is proportional to the square of the vertical electric eld.
The phonon-scattering and surface roughness scattering rates can be calculated from the band
structure obtained by the self-consistent simulation introduced above. Equipartition approximation (63) and two surface roughness assumptions (64) are applied to reduce the complexity of
modeling. Figure 7 shows the dependence of these scattering rates in pMOSFETs on (a) the applied <110> uniaxial compressive stress and (b) the lattice temperature. Optical phonon scattering
dominates at room temperature and signicantly reduces under high stress beyond 1 GPa. At low
temperature, however, surface roughness scattering becomes more important. The existing surface
roughness model works well for pMOSFETs alone (64). For nMOSFETs, only the assumption
212
Chu et al.
ANRV380-MR39-09
ARI
27 May 2009
15:5

b
3.0E+13
3.0E+13
2.5E+13
2.5E+13
Scattering rate (s1)
Scattering rate (s1)
2.0E+13
1.5E+13
1.0E+13
5.0E+12
0.0E+00
2.0E+13
1.5E+13
1.0E+13
5.0E+12
0.0E+00
77
127
177
227
Temperature (K)
277
Optical phonon scattering

Acoustic phonon scattering
Surface roughness scattering
Figure 7
Dependence of acoustic phonon scattering, optical phonon scattering, and surface roughness scattering in pMOSFETs on (a) <110>
uniaxial compressive stress and (b) temperature. The curves are calculated at an inversion carrier density of 1013 cm2 .
of increasing smoother interfaces with increasing strain seems to explain the experimental data
(65). An accurate model for the surface roughness scattering in nMOSFETs is still a complex issue
needing resolution.
Mobility Enhancement of (100) nMOSFETs

On the basis of the above discussions about band splitting, band warping, effective mass and
scattering rate, and mobility enhancement, data for strained Si nMOSFETs can be explained
theoretically. Chu et al. (19) show that (110)-oriented nMOSFETs have less enhancement
than do (100)-surface devices under both uniaxial and biaxial stress, mainly because electron
repopulation does not result in as much effective mass change for (110)-oriented nMOSFETs
as for (100) devices. Figure 8a shows the electron mobility enhancement factor versus applied
stress for (100) nMOSFETs, including <100> and <110> uniaxial tension as well as biaxial
tension. The gure shows that under low stress (<500 MPa), biaxial stress causes the largest
enhancement, followed by <100> uniaxial stress and then <110> uniaxial stress. However, the
enhancement under both biaxial and <100> uniaxial stress saturates quickly because the majority
of electrons are already located in the lower-energy 2 valley and additional stress (>1 GPa)
does not further reduce average effective mass. In contrast, the enhancement under <110> stress
increases signicantly up to 2 GPa. This is because the subband splitting under <110> uniaxial
stress is lower than that under <100> uniaxial stress and biaxial stress of the same magnitude,
and thus electron repopulation occurs up to higher stress, as shown in Figure 8b. In addition,
the 2 band warping under <110> stress allows for a further decrease in average effective mass.
The experimental data by Suthram et al. (10) conrm this enhancement trend under 1.5-GPa
stress. As a conclusion, biaxial stress is better than uniaxial stress for nMOSFETs under low stress
(<500 MPa), whereas at higher stress levels <110> uniaxial tension provides higher device
performance.
213
ANRV380-MR39-09
ARI
27 May 2009
15:5
b
Occupation of
two-fold valleys (%)
Electron mobility
enhancement
0.7
0.6
0.5
Reference 61
0.4
0.3
0.2
400
100
350
80
300
250
60
200
40
150
100
20
0.1
0
0.5
Stress (GPa)
1.5
Suband splitting (meV)
0.8

450
120
0.9
500
140
50
0
0.5
Stress (GPa)
1.5
Biaxial tension
<100> uniaxial
<110> uniaxial
Figure 8
(a) Mobility enhancement factors for (100)-surface nMOSFETs under <100> longitudinal, <110> longitudinal, and biaxial tensile
stress. The solid curves represent simulated results from Reference 66. (b) Stress effect on conduction band edge splitting and
ground-state subband occupation. The stress effect determines how fast the enhancement saturation is.
Mobility Enhancement of (100) and (110) pMOSFETs

It has been theoretically and experimentally proven that <110> uniaxial compression is more
benecial for enhancing hole mobility than are other stresses (28). In this subsection, we focus
on how and why there is a difference between (100)- and (110)-oriented pMOSFET enhancement under <110> uniaxial stress. Figure 9a shows the simulated hole mobility versus stress for
(100)/<110> and (110)/<110> pMOSFETs. Uniaxial compression increases the mobilities of
both devices to a comparable saturation level at high stress (3 GPa). The maximum hole mobility
enhancement factor is 4.5 for (100)/<110> pMOSFETs and 2 for (110)/<110> pMOSFETs. The ground-state subband warping, subband splitting between the top band and the bottom
band, 2-D DOS of the ground state, and ground-state subband occupation for (100) and (110)
pMOSFETs are also plotted in Figure 9.
Ground-state subband warping is the major reason for the different enhancement factor
in (100)- and (110)-surface devices. As shown in Figure 9b, (100)-oriented pMOSFET has a
larger change of effective mass in the <110> direction than does (110) pMOSFET and thus has
larger mobility enhancement. In addition, the larger connement-induced band splitting for (110)
pMOSFETs (Figure 9c) causes most holes to occupy the ground state. Thus, stress does not cause
as much hole repopulation as in the (100) device. At the same time, the point DOS for (110)
pMOSFETs does not change much with stress, whereas the DOS for (100) pMOSFETs increases
signicantly (Figure 9d ), allowing more holes to occupy the ground state, as shown in Figure
9e. As a result, <110> uniaxial compression has more effect on (100) pMOSFETs. Because the
original mobility for the (110) surface is two times that for (100) devices, the saturation mobility
is almost the same.
In 2008, Packan et al. (67) reported the performance impact of (110) Si substrates on high-k
metal gate strained 45-nm-node MOSFETs. Record pMOSFET drive currents of 1.2 mA m
214
Chu et al.
ANRV380-MR39-09
ARI
Hole mobility
(cm2 Vs1)
400
27 May 2009
15:5
300
(110)/<110> uniaxial
(001)/<110> pMOSFET
200
0.15
100
<110> uniaxial compression (GPa)
0.15
0.15
kx
0.15
0.15
No stress
<110>
0.15
<110>
ky
60
40
ky
20
0.15
0.15
kx
Uniaxial compression
3E+14
1
2E+14
1E+14
5E+13
0.15
0.15
kx
Uniaxial compression
2E+14
0E+00
kx
0.15
No stress
80
<111>
ky
100
<110>
Subband occupation
Subband splitting
(meV)
120
2-D density of state

(eV1 cm1)

(110)/<110> pMOSFET
0.15
ky
0
<110>
0.8
0.6
0.4
Figure 9
(a) Hole mobility as a function of <110> uniaxial compression. (b) Stress effect on valence band ground-state subband structure.
(c) Stress effect on valence band splitting between the ground state and the second subband. (d ) Stress effect on the two-dimensional
density of state of the valence band ground-state subband at the point. (e) Stress effect on valence band ground-state subband
occupation for (100)-surface and (110)-surface pMOSFETs.
were presented. The authors results for long-channel-device enhancement match the theoretical
expectation given above. They also concluded that as the channel length is reduced, 2-D S/D electrostatics lead to a reduction in charge connement in the channel. This reduction in connement
reduces the valley splitting at shorter channel lengths, lowering the anisotropy and reducing the
differences between (110) and (100) substrates.
215
ANRV380-MR39-09
ARI
27 May 2009
15:5
b
4
80
<100> uniaxial
Mobility enhancement
factor /
Piezoresistance coefficients
(1012 dyne cm2)

90
70
60
50
Biaxial tension
40
30
<110> uniaxial
20
10
0
pinv = 6 1012 cm2

pinv = 1 1013 cm2
pinv = 1.2 1013 cm2
pinv = 1.5 1013 cm2
pinv = 2 1013 cm2
0.5
0.6
0.7
0.8
0.9
Effective field (MV cm2)
1.1
1.2
3
2
1
0
Figure 10
(a) Effective eld dependence of (100)-oriented nMOSFET piezoresistance coefcients. (b) Inversion layer carrier density dependence
of (100)/<110> hole mobility under uniaxial compression.
Electric Field Dependence of Piezoresistance Coefficients

As discussed above, because electric eld connement causes subband splitting and carrier repopulation, it is expected that the -coefcients for MOSFETs will be different from the bulk Si
value and will depend on the magnitude of the eld. Figure 10a shows the experiment result for
-coefcients of (100) nMOSFETs under biaxial tension and <100> and <110> uniaxial tension.
Strong electric eld dependence is observed only under <100> uniaxial stress. This is mainly due
to the further subband splitting of the 4 valley into two two-fold valleys, as shown in Figure 3a.
A more detailed explanation can be found in Reference 19. Figure 10b shows the simulated hole
mobility enhancement factor under <110> uniaxial compression for different inversion carrier
densities. The enhancement does not vary signicantly for relatively low densities (from 6
1012 cm2 to 1.2 1013 cm2 ) but has a large change beyond 1.2 1013 cm2 . Because normal
device operation has an inversion carrier density of approximately 1 1013 cm2 , we expect the
-coefcient to be approximately constant for <110> longitudinal compression measurements
on different devices.
Section Summary
This section presents strain effects on Si band structure, effective mass, and scattering mechanism.
On the basis of this understanding, strain-induced carrier mobility enhancement for both n- and
pMOSFETs with different surface orientations and channel directions was studied. The results
show that (100)/<110> uniaxial stress is the most promising stress for n/pMOSFETs operating
under a high stress level.
STRAIN EFFECTS ON NONCLASSICAL MOSFETs

As Si CMOS technology scales down to the sub-100-nm regime, device performance is limited
by SCEs, and conventional scaling cannot achieve further improvement. With the application of
high-k dielectric and a novel doping prole, the scaling limit for planar MOSFET is extended to
20 nm (68). To further scale down device dimensions while maintaining good performance, new
216
Chu et al.
ANRV380-MR39-09
ARI
27 May 2009
15:5
Gate
Source
Drain
Si substrate

Bulk MOSFET
Gate
Source
Si
Source
Gate
Drain
Oxide
Si substrate
Drain
SOI MOSFET
FinFET
Figure 11
Si MOSFETs with different device structures: (a) classical bulk MOSFET; (b) SOI MOSFET; (c) 3-D
FinFET.
device structures and channel materials are being considered as possible solutions. In this section,
we focus on the effect of stress on novel devices such as ultrathin body silicon-on-insulator (UTB
SOI) transistors, multigate FinFETs, and Ge and GaAs channel MOSFETs.
Devices with New Structures

To improve SCEs and to continue scaling devices in the 22-nm technology node and beyond,
devices with novel structures have been proposed and demonstrated. These new structures are
combined with strain engineering to enable additional performance enhancement. In this subsection, we discuss the stress effects on SOI and multigate MOSFETs as they relate to strained bulk
Si devices.
Stress effects on SOI MOSFETs. The UTB SOI transistor architecture (Figure 11b), proposed
since the late 1970s (6973), shows good scalability down to the sub-20-nm scale. To combine
the strain-induced transport property enhancements and their scaling advantages, stress has been
applied to SOI devices in recent years (7479). In 2004, Uchida et al. (78) reported the carrier
mobility enhancement for n- and p-type UTB SOI MOSFETs under small uniaxial stress and
biaxial stress and compared the results with those for bulk Si MOSFETs. Their results show similar
enhancement factors between SOI devices and corresponding classical devices under uniaxial
stress, although the benet of biaxial stress vanishes.
Sun (58) simulated hole mobility enhancement versus <110> uniaxial stress for different
buried-oxide thicknesses. His results also show good agreement between SOI and bulk devices
UTB SOI: ultrathin

body silicon-oninsulator
217
ANRV380-MR39-09
ARI
27 May 2009
15:5
under low stress, but he observed a larger enhancement for UTB SOI devices under large stress.
At low stress, (100)-oriented pMOSFET mobility is enhanced owing mainly to band warping
induced effective mass lowering, which is the same for SOI and bulk devices. At high stress,
however, phonon-scattering rate reduction caused by increasing subband splitting plays the major
role. Because the additional geometrical connement in UTB SOI devices results in extra subband
splitting, there is larger carrier mobility enhancement than for the classical bulk device at high
stress.

Stress effects on multigate FinFETs. Although SOI technology has better scalability than do
classical bulk Si MOSFETs, it is still impractical to scale the SOI device to the deep sub-20-nm
regime because the lateral electric eld at the drain penetrates into the channel (1, 80, 81). To
improve gate control, multigate FinFETs (Figure 11c) have been investigated as perhaps the most
promising candidates for sub-20-nm technology (8284). Recently, strain effects on double-gate
(DG) and trigate (TG) FinFETs have been studied (8587). Collaert and coworkers (39, 8890)
demonstrated performance enhancement of TG FinFET devices, using supercritical strained
SOI (SC-SSOI) and CESL. Irisawa et al. (37, 42, 91) pointed out the difference between top-gate
and side-wall transport and proposed the optimal strain congurations for n- and p-type FinFETs.
Shin and colleagues (43) and Suthram et al. (41), using wafer bending experiments, studied stress
effects on TG FinFET and DG FinFET, respectively.
Both Sun (58) and Suthram et al. (41) show that for DG FinFETs with large n width (>20 nm),
the mobility enhancement is similar to that for bulk devices with the same surface orientation. For
very narrow FinFETs (<20 nm), the bulk inversion effect (92, 93) caused by geometry connement
becomes signicant, and a strong subband modulation is observed, as illustrated in Figure 12.
This gures shows that in FinFETs, band bending at the Si/SiO2 interface is very small and
that the ground-state subband is much closer to the Fermi level than it is in the bulk device.
Furthermore, the second subband is very close to the ground state, which acts like an increasing
DOS of the ground-state subband. As a result, the amount of carriers that can be affected by
the strain increases, which results in a higher enhancement factor (see Reference 58 for a more
detailed discussion). For strained TG FinFETs, contributions from the top gate and the side walls
should be studied separately because the top gate and side walls have different surface orientations,
but the underlying physics is the same. We expect the TG FinFET with small n width to have
similar behavior as DG FinFET and those with large n widths to have similar behavior as the
bulk device.
Etop
Ev
Etop
Esecond
Ethird
Esecond
Ev
(110) SG MOSFET
DG MOSFET
Figure 12
Comparison between the connement-induced subband splitting of double-gate (DG) and single-gate (SG)
MOSFETs.
218
Chu et al.
ANRV380-MR39-09
ARI
27 May 2009
15:5
Table 1 Band and transport parameters for Si, Ge, and some III-V semiconductors. Produced with permission from
Reference 45

Eg (eV)
mn
(cm2 /V s)
mhh /mlh
(cm2 /V s)
gmm (norm.)
EL c
ml /mt
(eV)
(L)a
Si
1.12
0.92/0.19
1450
0.53/0.15
500
Ge
0.67
1.59/0.082
3900
0.33/0.043
2270
0.92
InSb
0.17
0.014
7.7 104
0.45/0.016
850
1.9
0.51
1.56/0.094
InAs
0.35
0.024
23.3 104
0.41/0.026
100450
1.29
0.72
1.56/0.094
GaSb
0.73
0.041
3750
0.40/0.05
680
0.28
0.084
0.95/0.11
InP
1.34
0.08
5370
0.6/0.089
150
0.77
0.59
1.9/0.15
GaAs
1.42
0.063
9200
0.5/0.076
400
1.03
0.29
1.9/0.075
Strained
Si
1.08
2900b
2200c
a
These two columns list the L valley data for selected III-V semiconductors. The other data in the table are taken from Reference 96 and from
http://www.ioffe.rssi.ru/SVA/NSM/Semicond/.
b
See Reference 94.
c
See Reference 95.
Devices with New Channel Material

Although strain introduced into Si CMOS technology improves carrier mobility, strain can also
be applied to other possible channel materials with high mobility such as Ge and III-V semiconductors. Compared with strained Si, most of these semiconductors with similar band gaps have
a much smaller electron mass and light-hole effective mass (13). Table 1 lists the mobilities and
effective masses for Si, Ge, and several direct band-gap III-V semiconductors (9496).
Ge pMOSFETs. Ge has been a topic of interest in high-speed CMOS technology since the late
1980s (97). In 1989, Martin et al. (98) demonstrated a Ge pMOSFET with high hole mobility
(770 cm2 /V s), using a SiO2 gate dielectric. Since then, more and more work has been done on
Ge or SiGe channel pMOSFETs (99103). With the progress of strained Si technology in recent
years, strain effect on Ge MOSFETs has also been investigated experimentally (104110) and
theoretically (58, 111113).
Sun (58) studied in detail the strain-induced hole mobility change of Ge and Si1x Gex in the
pMOS inversion layer. Under biaxial stress, a similar enhancement factor is observed for both Si
and Ge channel devices. Under <110> uniaxial compression, Ge channel MOSFETs on the (100)
surface have a similar enhancement as does Si, but the enhancement factor saturates at much larger
stress, as shown in Figure 13. The reason is that the Ge valence band effective mass change does
not saturate under stress (>3 GPa), whereas the effective mass change for Si normally saturates at
2 or 3 GPa. Ge and Si1x Gex pMOSFETs have higher unstrained hole mobility than and similar
strain-induced enhancement as do Si pMOSFETs. As a result, with proper gate dielectrics (105,
114, 115), strained Ge channel pMOS is expected to show better performance.
III-V MOSFETs. Narrow-band-gap, high-mobility III-V materials are candidates for substituting the Si channel in CMOS devices beyond the 22-nm node (116119). Chau and coworkers (118)
discussed in detail the opportunities and challenges of III-V nanoelectronics for high-speed, lowpower logic applications. Recently, high-In-content Inx Ga1x As quantum wells have been of special interest in terms of electron mobility and a band gap ranging from 0.55 to 0.74 eV, depending
219
ANRV380-MR39-09
ARI
27 May 2009
15:5
Hole mobility (cm2 Vs1)
1800
Ge
1500
1200
Si0.25Ge0.75
900
Si0.5Ge0.5
Si0.75Ge0.25
600
Si
300
0

pinv = 1 1013 cm2
Figure 13
Ge, Si, and Si1x Gex hole mobility enhancement of a (100)-oriented device under <110> uniaxial
compressive stress.
on the In mole fraction (120, 121). Because the valence and conduction bands for GaAs, InAs, and
InGaAs are very similar, this subsection focuses on the stress effect on bulk GaAs MOSFETs.
Suthram et al. (121) applied uniaxial and biaxial stress on GaAs n- and pMOSFETs and extracted
the corresponding -coefcients. Their results show that the enhancement of uniaxially stressed
nMOS saturates at very low stress (with a maximum of 6% enhancement in drive current at
75 MPa), whereas a linear trend is seen under biaxial stress (6% enhancement in drive current
per 100 MPa). This phenomenon can be explained by stress-induced electron repopulation among
different valleys (107). GaAs has energetically adjacent multivalley conduction bands: , L, and
X valleys. Electron mobility in the valley is much higher than that in the L valley or X valley.
Under applied biaxial stress, the conduction band valleys shift as shown in Figure 14a, and the
splitting between the and L valleys increases, causing more electrons to repopulate to the loweffective-mass valley and thus enhance mobility. Uniaxial strain, however, splits the L valleys
into two groups, as shown in Figure 14b. The lower L valleys shift faster downward with the
uniaxial stress than does the valley. Thus, valley occupation turns lower. But the splitting of
the L valley also lowers the DOS of each group to one-half of the original value. As a result, the
band shift and DOS reduction of the lower L valley render a saturation of electron occupation
in the valley at a specic stress. Beyond that value, the occupation of valley decreases. As a
summary, we see a monotonic increase in electron mobility with biaxial stress, whereas we see an
increase, a saturation, and then a decrease in electron mobility with uniaxial stress.
GaAs valence bands have a similar structure to that of Si valence bands. The self-consistent
simulation that uses the k p method shows a similar hole mobility enhancement factor for both
GaAs and Si under <110> uniaxial compression (12), as shown in Figure 15. However, data from
experiment (121) show a two-times-larger enhancement in GaAs than in Si. The discrepancy may
be due to the surface quality of the GaAs MOSFETs, for which the simulation assumes an interface
quality comparable to that of Si/SiO2 .
Section Summary
This section reviews strain effects on the carrier mobility of nonclassical MOSFETs. The major
conclusions are as follows:
1. Carrier mobility in UTB SOI devices has a similar enhancement under low stress as bulk Si
devices and a larger enhancement under high stress than bulk Si devices owing to the fact
220
Chu et al.
ANRV380-MR39-09
ARI
27 May 2009
15:5
a Biaxial tension
b Uniaxial tension
hydro
hydro
hydro
shear
hydro
shear
hydro
80
80
valley
valley
Subband population (%)
Subband population (%)
60
40
Ninv = 1013 cm2
L valley
20
60
Ninv = 1013 cm2

40
L valley
20
X valley
X valley
0
0.1
0.5
0.5
Biaxial stress (GPa)
1.5
0
0.1
0.5
0.5
Uniaxial stress (GPa)
1.5
Figure 14
Theoretical estimation of the effect of (a) biaxial stress, (b) uniaxial stress on a GaAs conduction band and the predicted carrier
population changes in the , L, and X valleys.
400
Hole mobility (cm2 Vs1)

hydro
shear
Si
300
200
GaAs
100
Figure 15
Hole mobilities of Si and GaAs as a function of <110> uniaxial compressive stress. Both devices show a
similar mobility enhancement factor.
221
ARI
27 May 2009
15:5
that the extra subband splitting caused by geometrical connement in UTB SOI results in
a larger phonon-scattering rate reduction.
2. Wide FinFETs have a similar mobility enhancement as bulk Si devices with the same surface
orientation, whereas narrow FinFETs have a larger enhancement. This is because of the
strong subband modulation caused by geometry connement increasing the amount of
carriers that can be affected by the strain.
3. Ge and Si1x Gex pMOSFETs have the same strained behavior as Si MOSFETs, but the
enhancement saturates at higher stress.
4. n-type GaAs MOSFETs benet from biaxial stress owing to the monotonic increase in
splitting between the and L valleys under biaxial stress. As with the k p method, p-type
GaAs devices have a similar enhancement factor under <110> uniaxial compression to that
of Si channel MOSFETs.

ANRV380-MR39-09
STATE-OF-THE-ART STRAINED Si MOSFETs

Recent Strained Technology Nodes
With continued scaling of gate pitch at 0.7 per technology node, the industry has adopted
strained Si and high-k dielectric technology to maintain and improve circuit performance. This
trend in scaling is illustrated in Figure 16. In the 90-nm node (32), uniaxial strain in nMOS devices were achieved by a SiN capping layer and in pMOS devices by SiGe S/D regions with 17%
Ge content. This resulted in record-breaking high drive currents of 800 A m1 in pMOS and
1.45 mA m1 in nMOS. For the 65-nm technology, researchers obtained performance enhancements higher than the 90-nm technology by increasing the strain in the device channel. In pMOSFETs, the Ge content in SiGe S/D was increased to 23%, resulting in a 60% enhancement in
channel strain, and an enhanced process ow was adopted for the SiN capping layer of nMOSFETs to increase channel strain by 80% (122). With the successful integration and performance of
strained devices in 90- and 65-nm nodes, third-generation strained Si technology was incorporated
into the 45-nm logic technology (123). In this technology, pMOS device performance is achieved
Current
technology node
Future
technology node
90-nm node
2003
65-nm node
2005
50-nm length
IEDM 2002
30-nm length
IEDM 2002
Technology nodes for Intel nanotransistors.

Chu et al.
32-nm node
2009
22-nm node
2011
Figure 16
222
45-nm node
2007
20-nm length
VLSI 2001
15-nm length
IEDM 2001
10-nm length
ITJ 2002
ANRV380-MR39-09
ARI
27 May 2009
15:5
by the combination of strain technology with high-k dielectric and a metal gate. Recently, even
35-nm pMOSFETs with strained Si channels have been demonstrated (124).

Future Generations of Strain Technology

The industry has adopted uniaxial strain over biaxial strain because of the formers larger performance improvement (9). Uniaxial strain is introduced via process by capping layers and epitaxial
SiGe S/D regions. Lately, tensile strained nMOSFETs with silicon carbide (SiC) S/D regions
have attracted interest. The lattice mismatch between SiC and Si results in longitudinal tensile
strain and vertical compressive strain in the channel. Both types of strain enhance electron mobility. Also, the offset between the conduction band of the SiC source and the strained channel
results in higher carrier injection velocity. In 2008, Yang et al. (125) reported a 35-nm gate length
nMOSFET with epitaxial SiC S/D. Their device shows 9% drain current enhancement over
the 45-nm-node strained nMOSFET with 1.2-GPa tensile liner.
However, as device dimensions successively reduce, the volume of SiGe in S/D also reduces,
making it difcult to strain in short-channel devices. To date, strain has been an effective performance booster even for the 22-nm technology. However, the effectiveness of strain as a performance booster below the 22-nm node remains to be seen.
Theoretical research proves that strain Si technology provides performance improvement even
in ballistic-regime MOSFETs (126). Strain-induced reduction in carrier mass results in increasing
source carrier injection velocity and thus leads to drive current enhancements in ballistic transistors. This ensures the scalability of strain technology, but the real technical challenge will be to
effectively incorporate high levels of stress in these nanodevices.
CONCLUSION
During the past decade, strain has been the dominant technique to successfully enhance device
performance. With its high performance gain and low cost, strain has been introduced into different devices to achieve further improvements in drivability. In this article, we focus on the physical
insights of strain-enhanced carrier mobility and provide key results. We thus demonstrate that
with proper strain, the performance of MOSFETs with different device structures and channel materials can be boosted. On the basis of this knowledge, incorporating high-level strain to improve
novel devices with ultrashort channels is proposed to be the future mission in this eld.
SUMMARY POINTS
1. Owing to surface electric eld connement, the carrier mobility enhancement in
MOSFETs can signicantly differ from that in bulk Si material depending on whether
connement-induced subband splitting and stress-induced subband splitting are additive
or subtractive.
2. For (100)-oriented nMOSFETs under high stress, <110> uniaxial tension yields the
highest mobility enhancement, owing mainly to 2 subband warping.
3. For (100)-oriented pMOSFETs, <110> uniaxial compression is the best stress conguration. (110) pMOSFETs have less enhancement than do (100)-surface devices because
of the smaller change in conductivity effective mass.
223
ANRV380-MR39-09
ARI
27 May 2009
15:5
4. Compared with classical bulk MOSFETs, UTB SOI devices and FinFETs have a similar
or larger enhancement under stress. A smaller device geometry results in a larger increase
in mobility.
5. Ge and GaAs channel pMOSFETs have similar strained behavior as their Si counterparts.
Electron mobility in GaAs nMOSFETs increases only under biaxial tensile stress.
FUTURE ISSUES
1. How should stress be incorporated effectively into ultrashort-channel devices?

2. How should the surface roughness scattering of electron transport in nMOSFETs be
modeled?
3. What are the stress effects on other device congurations, such as memory and power
devices?
DISCLOSURE STATEMENT
The authors are not aware of any afliations, memberships, funding, or nancial holdings that
might be perceived as affecting the objectivity of this review.
LITERATURE CITED
12. An in-depth study of

the physics of stress
effect on MOSFETs.
224
1. Taur Y, Ning TH. 1998. Fundamentals of Modern VLSI Devices. Cambridge, UK: Cambridge Univ. Press.
469 pp.
2. Thompson SE, Parthasarathy S. 2006. Moores law: the future of Si microelectronics. Mater. Today 9:20
25
3. Moore GE. 1975. Progress in digital integrated electronics. Int. Elec. Dev. Meet. 1113
4. Taur Y, Buchanan DA, Chen W, Frank DJ, Khalid EI, et al. 1997. CMOS scaling into the nanometer
regime. Proc. IEEE 85:486504
5. Wong HSP, Frank DJ, Solomon PM, Wann CHJ, Wesler JJ. 1999. Nanoscale CMOS. Proc. IEEE
87:53770
6. Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong HSP. 2001. Device scaling limits of Si
MOSFETs and their application dependencies. Proc. IEEE 89:25988
7. Keyes RW. 2001. Fundamental limits of silicon technology. Proc. IEEE 89:22739
8. Plummer JD, Grifn PB. 2001. Material and process limits of silicon VLSI technology. Proc. IEEE
89:24058
9. Sun G, Sun Y, Nishida T, Thompson SE. 2007. Hole mobility in silicon inversion layers: stress and
surface orientation. J. Appl. Phys. 102:084501
10. Suthram S, Ziegert JC, Nishida T, Thompson SE. 2007. Piezoresistance coefcients of (100) silicon
nMOSFETs measured at low and high (1.5 GPa) channel stress. IEEE Elec. Dev. Lett. 28:5861
11. Natarajan S, Armstrong M, Bost M, Brain R, Brazier M, et al. 2008. A 32 nm logic technology featuring
2nd generation high-k + metal-gate transistors, enhanced channel strain and 0.171 m2 SRAM cell size
in a 291 Mb array. Int. Elec. Dev. Meet. 13
12. Bardeen J, Shockley W. 1950. Deformation potentials and mobilities in nonpolar crystals. Phys.
Rev. 80:7280
13. Herring C, Vogt E. 1956. Transport and deformation-potential theory for many-valley semiconductors
with anisotropic scattering. Phys. Rev. 101:94461
Chu et al.

ANRV380-MR39-09
ARI
27 May 2009
15:5
14. Shockley W. 1950. Energy band structures in semiconductors. Phys. Rev. 78:17374
15. Luttinger JM, Kohn W. 1955. Motion of electrons and holes in perturbed periodic elds. Phys. Rev.
97:86983
16. Bir GL, Pikus GE. 1974. Symmetry and Strain-Induced Effects in Semiconductors. New York: Wiley.
484 pp.
17. Hasegawa H. 1963. Theory of cyclotron resonance in strained silicon crystals. Phys. Rev. 129:102940
18. Hensel JC, Feher G. 1963. Cyclotron resonance experiments in uniaxially stressed silicon: valence band
inverse mass parameters and deformation potentials. Phys. Rev. 129:104162
19. Chu M, Nishida T, Lu X, Mohta N, Thompson SE. 2008. Comparison between high-eld piezoresistance coefcients of Si metal-oxide-semiconductor eld-effect transistors and bulk Si under uniaxial and
biaxial stress. J. Appl. Phys. 103:113704
20. Smith CS. 1954. Piezoresistance effect in germanium and silicon. Phys. Rev. 94:4249
21. Colman D, Bate RT, Mize JP. 1968. Mobility anisotropy and piezoresistance in silicon p-type inversion
layers. J. Appl. Phys. 39:192331
22. Wesler J, Hoyt JL, Gibbons JF. 1992. NMOS and PMOS transistors fabricated in strained silicon/relaxed
silicon-germanium structures. Int. Elec. Dev. Meet. 10002
23. Nayak DK, Woo JCS, Park JS, Wang KL, MacWilliams KP. 1993. High-mobility p-channel
metal-oxide-semiconductor field-effect transistor on strained Si. J. Phys. Phys. 33:241214
24. Nayak DK, Goto A, Yutani A, Muruta YJ, Shiraki Y. 1996. High-mobility strained-Si pMOSFETs. IEEE
Trans. Elec. Dev. 43:170916
25. Rim K, Wesler J, Hoyt JL, Gibbons JF. 1995. Enhanced hole mobilities in surface-channel
strained-Si p-MOSFETs. Int. Elec. Dev. Meet. 51720
26. Rim K, Hoyt JL, Gibbons JF. 1998. Transconductance enhancement in deep submicron strained-Si
n-MOSFETs. Int. Elec. Dev. Meet. 70710
27. Lee ML, Fitzgerald EA, Bulsara MT, Currie MT, Lochtefeld A. 2005. Strained Si SiGe and Ge channels
for high-mobility metal-oxide-semiconductor eld-effect transistors. J. Appl. Phys. 97:011101
28. Thompson SE, Sun G, Wu K, Lim J, Nishida T, et al. 2004. Key differences for process-induced uniaxial
vs substrate-induced biaxial stressed Si and Ge channel MOSFETs. Int. Elec. Dev. Meet. 22124
29. Ito S, Namba H, Yamaguchi K, Hirata T, Ando K, et al. 2000. Mechanical stress effect of etch stop
nitride and its impact on deep micron transistor design. Int. Elec. Dev. Meet. 24750
30. Shimizu A, Hachimine K, Okhi N, Ohta H, Koguchi M, et al. 2001. Local mechanical-stress control
(LMC): a new technique for CMOS-performance enhancement. Int. Elec. Dev. Meet. 43336
31. Gannavaram S, Pesovic N, Ozturk MC. 2000. Low temperature recessed junction selective silicongermanium source/drain technology for sub70 nm CMOS. Int. Elec. Dev. Meet. 43740
32. Thompson S, Anand N, Armstrong M, Auth C, Arcot B, et al. 2002, A 90 nm logic technology featuring
50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 m2 SRAM
cell. Int. Elec. Dev. Meet. 6164
33. Jan CH, Bai P, Choi J, Curello G, Jacobs S, et al. 2005. A 65 nm ultra low power logic platform technology
using uni-axially strained silicon transistors. Int. Elec. Dev. Meet. 6063
34. Steegen A, Mo R, Mann R, Sun MC, Eller M, et al. 2005. 65 nm CMOS technology for low power
applications. Int. Elec. Dev. Meet. 6467
35. Ghani T, Armstrong M, Auth C, Bost M, Charavat C, et al. 2003. A 90 nm high volume manufacturing
logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. Int. Elec. Dev.
Meet. 97880
36. Chan V, Rengarajan R, Rovedo N, Jin W, Hook T, et al. 2003. High speed 45 nm gate length CMOSFETs
integrated into a 90 nm bulk technology incorporating strain engineering. Int. Elec. Dev. Meet. 7780
37. Irisawa T, Numata T, Tezuka T, Usuda K, Nakaharai S, et al. 2005. High performance multi-gate
pMOSFETs using uniaxial-strained SGOI channels. Int. Elec. Dev. Meet. 70912
38. Kavalieros J, Doyle B, Datta S, Dewey G, Doczy M, et al. 2006. Tri-gate transistor architecture with
high-k gate dielectrics, metal gates and strain engineering. VLSI Symp. Tech. Dig. 5051
39. Collaert N, Rooyackers R, Clemente F, Zimmerman P, Cayrefourcq I, et al. 2006. Performance enhancement of MuGFET devices using super critical strained-SOI (SC-SSOI) and CESL. VLSI Symp.
Tech. Dig. 5253
23. Presents the

detailed six-band k p
calculation procedure
for inversion hole
mobility.
25. Provides complete

tables of piezoresistance
coefficients for n- and
pMOSFETs.
225

ANRV380-MR39-09
ARI
27 May 2009
46. The highest

mechanical stress
applied to MOSFETs to
date.
226
15:5
40. Shin K, Xiong W, Cho CY, Cleavelin CR, Schulz T, et al. 2006. Study of bending-induced strain effects
on MuGFET performance. IEEE Elec. Dev. Lett. 27:67173
41. Suthram S, Hussain MM, Harris HR, Smith C, Tseng HH, et al. 2008. Comparison of uniaxial wafer
bending and contact-etch-stop-liner stress induced performance enhancement on double-gate FinFETs.
IEEE Elec. Dev. Lett. 29:48082
42. Irisawa T, Numata T, Tezuka T, Usuda K, Sugiyama N, Takagi SI. 2008. Device design and electron
transport properties of uniaxially strained-SOI tri-gate nMOSFETs. IEEE Trans. Elec. Dev. 55:64954
43. Xiang Q, Goo JS, Pan J, Yu B, Ahmed S, et al. 2003. Strained silicon NMOS with nickel-silicide metal
gate. VLSI Symp. Tech. Dig. 1012
44. Datta S, Dewey G, Doczy M, Doyle BS, Jin B, et al. 2003. High mobility Si/SiGe strained channel MOS
transistors with HfO2 /TiN gate stack. Int. Elec. Dev. Meet. 65356
45. Sun Y, Thompson SE, Nishida T. 2007. Physics of strain effects in semiconductors and metal-oxidesemiconductor eld-effect transistors. J. Appl. Phys. 101:104503
46. Yu PY, Cardona M. 2001. Fundamentals of Semiconductors: Physics and Materials Properties. Berlin:
Springer. 639 pp. 3rd ed.
47. Thompson SE, Armstrong M, Auth C, Cea S, Chau R, et al. 2004. A logic nanotechnology featuring
strained-silicon. IEEE Elec Dev. Lett. 25:19193
48. Bradley AT, Jaeger RC, Suhling JC, OConnor KJ. 2001. Piezoresistive characteristics of short-channel
MOSFETs on (100) silicon. IEEE Trans. Elec. Dev. 48:200915
49. Steegen A, Stucchi M, Lauwers A, Maex K. 1999. Silicide induced pattern density and orientation
dependent transconductance in MOS transistors. Int. Elec. Dev. Meet. 497500
50. Vogelsang TH, Hofmann KR. 1992. Electron mobilities and high-eld drift velocities in strained silicon
on silicon-germanium substrates. IEEE Trans. Elec. Dev. 39:264142
51. Vogelsang TH, Hofmann KR. 1993. Electron transport in strained Si layers on Si1x Gex substrates.
Appl. Phys. Lett. 63:18688
52. Rahman A, Lundstrom MS, Ghosh AW. 2005. Generalized effective-mass approach for n-type metaloxide-semiconductor eld-effect transistors on arbitrarily oriented wafers. J. Appl. Phys. 97:053702
53. Long D. 1960. Scattering of conduction electrons by lattice vibrations in silicon. Phys. Rev. 120:202432
54. Fischetti MV, Ren Z, Solomon PM, Yang M, Rim K. 2003. Six-band k p calculation of the hole mobility
in silicon inversion layers: dependence on surface orientation, strain, and silicon thickness. J. Appl. Phys.
94:107995
55. Takagi S, Hoyt JL, Welser JJ, Gibbons JF. 1996. Comparative study of phonon-limited mobility of twodimensional electrons in strained and unstrained Si metal-oxide-semiconductor eld-effect transistors.
J. Appl. Phys. 80:156777
56. Goodnic SM, Ferry DK, Wilmsen CW. 1985. Surface roughness at the Si(100)-SiO2 interface. Phys.
Rev. B 32:817186
57. Yamakawa S, Ueno H, Taniguchi K, Hamaguchi C, Miyatsuji K, et al. 1996. Study of interface roughness
dependence of electron mobility in Si inversion layers using the Monte Carlo method. J. Appl. Phys.
79:91116
58. Sun G. 2007. Strain effects on hole mobility of silicon and germanium p-type metal-oxide-semiconductor eld-effect
transistors. PhD thesis. Univ. Fla.
59. Hensel JC, Hasegawa H, Nakayama M. 1965. Cyclotron resonance in uniaxially stressed silicon. II.
Nature of the covalent bond. Phys. Rev. 138:A22538
60. Bastard G. 1992. Wave Mechanics Applied to Semiconductor Heterostructures. New York: Wiley-InterSci.
357 pp.
61. Chuang SL. 1995. Physics of Optoelectronic Devices. New York: Wiley-Intersci. 736 pp.
62. Stern F. 1972. Self-consistent results for n-type Si inversion layers. Phys. Rev. B 5:489199
63. Ridley BK. 1999. Quantum Processes in Semiconductors. Oxford: Oxford Univ. Press. 456 pp.
64. Gamiz F, Roldan JB, Lopez-Villanueva JA, Cartujo-Cassinello P, Carceller JE. 1999. Surface roughness
at the Si/SiO2 interfaces in fully depletion silicon-on-insulator inversion layers. J. Appl. Phys. 86:685463
65. Fischetti MV, Gamiz F, Hansch W. 2002. On the enhanced electron mobility in strained-silicon inversion
layers. J. Appl. Phys. 92:732024
Chu et al.

ANRV380-MR39-09
ARI
27 May 2009
15:5
66. Uchida K, Krishnamohan T, Saraswat KC, Nishi Y. 2005. Physical mechanisms of electron mobility
enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime.
Int. Electron Dev. Meet. 12932
67. Packan P, Cea S, Deshpande H, Ghani T, Giles M, et al. 2008. High performance hi-k + metal gate
strain enhanced transistors on (110) silicon. Int. Elec. Dev. Meet. 14
68. Taur Y. 2002. CMOS design near the limit of scaling. IBM J. Res. Dev. 46:21322
69. Izumi K, Doken M, Ariyoshi H. 1978. CMOS devices fabricated on buried SiO2 layer formed by oxygen
implantation into silicon. Electron Lett. 14:59394
70. Sano E, Kasai R, Ohwada K, Ariyoshi H. 1980. A two-dimensional analysis for MOSFETs fabricated on
buried SiO2 layer. IEEE Trans. Elec. Dev. 27:204350
71. Worley ER. 1980. Theory of the fully depleted SOS/MOS transistor. Solid State Electron 23:110711
72. Lim HK, Fossum JG. 1983. Threshold voltage of thin-lm silicon-on-insulator (SOI) MOSFETs. IEEE
Trans. Elec. Dev. 30:124451
73. Lim HK, Fossum JG. 1984. Current-voltage characteristics of thin-lm SOI MOSFETs in strong inversion. IEEE Trans. Elec. Dev. 31:4018
74. Takagi S. 2002. Strained-Si- and SiGe-on-insulator (strained-SOI and SGOI) MOSFETs for high performance/low power CMOS application. Device Res. Conf. 3740
75. Mizuno T, Sugiyama N, Tezuka T, Numata T, Maeda T, Takagi S. 2002. Design for scaled thin-lm
strained-SOI CMOS devices with higher carrier mobility. Int. Elec. Dev. Meet. 3134
76. Uchida K, Watanabe H, Kinoshita A, Koga I, Numata T, Takagi S. 2002. Experimental study on carrier
transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm. Int.
Elec. Dev. Meet. 4750
77. Aberg I, Olubuyide OO, Chleirigh CN, Lauer I, Antoniadis DA, et al. 2004. Electron and hole mobility
enhancements in sub10 nm-thick strained silicon directly on insulator fabricated by a bond and etch-band
technique. VLSI Symp. Tech. Dig. 5253
78. Uchida K, Zednik R, Lu C, Jagannathan H, McVittie J, et al. 2004. Experimental study of biaxial and
uniaxial strain effects on carrier mobility in bulk and UTB SOI MOSFETs. Int. Elec. Dev. Meet. 22932
79. Aberg I, NiChleirigh C, Hoyt JL. 2006. Ultrathin-body strained-Si and SiGe heterostructure-oninsulator MOSFETs. IEEE Trans. Elec. Dev. 53:102129
80. Yan RH, Ourmazd A, Lee KF, Jeon DY. 1991. Scaling the Si metal-oxide-semiconductor eld-effect
transistor into the 0.1-m regime using vertical doping engineering. Appl. Phys. Lett. 59:331517
81. Su LT, Jacobs JB, Chung JE, Antoniadis DA. 1994. Deep-submicrometer channel design in silicon-oninsulator (SOI) MOSFETs. IEEE Elec. Dev. Lett. 15:18385
82. Yu B, Chang L, Ahmed S, Wang H, Kyser D, et al. 2002. FinFET scaling to 10 nm gate length. Int. Elec.
Dev. Meet. 25154
83. Kedzierski J, Ieong M, Nowak E, Kanarsky T, Zhang Y, et al. 2003. Extension and source/drain design
for high performance FinFET devices. IEEE Trans. Elec. Dev. 50:95258
84. Fossum JG, Chowdhury MM, Trivedi VP, King TJ, Choi YK, et al. 2003. Physical insights on design
and modeling of nanoscale FinFETs. Int. Elec. Dev. Meet. 67982
85. Kavalieros J, Doyle B, Datta S, Dewey G, Doczy M, et al. 2006. Tri-gate transistor architecture with
high-k gate dielectrics, metal gates and strain engineering. VLSI Symp. Tech. Dig. 5051
86. Liow TY, Tan KM, Lee RTP, Tung CH, Samudra GS, et al. 2007. N-channel (110)-sidewall strained
FinFETs with silicon-carbon source and drain stressors and tensile capping layer. IEEE Elec. Dev. Lett.
28:101417
87. Tezuka T, Toyoda E, Nakaharai S, Irisawa T, Hirashita N, et al. 2007. Observation of mobility enhancement in strained Si and SiGe tri-gate MOSFETs with multi-nanowire channels trimmed by hydrogen
thermal etching. Int. Elec. Dev. Meet. 88790
88. Collaert N, De Keersgieter A, Anil KG, Rooyackers R, Eneman G, et al. 2005. Performance improvement
of tall triple gate devices with strained SiN layers. IEEE Elec. Dev. Lett. 26:82022
89. Verheyen P, Collaert N, Rooyackers R, Loo R, Shamiryan D, et al. 2005. 25% drive current improvement
for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si0.8 Ge0.2 in the source
and drain regions. VLSI Symp. Tech. Dig. 19495
227
ARI
27 May 2009
15:5
90. Collaert N, Rooyackers R, De Keersgieter A, Leys FE, Cayrefourcq I, et al. 2007. Stress hybridization for
multigate devices fabricated on supercritical strained-SOI (SC-SSOI). IEEE Elec. Dev. Lett. 28:64648
91. Irisawa T, Numata T, Tezuka T, Sugiyama N, Takagi S. 2006. Electron transport properties of ultrathinbody and tri-gate SOI nMOSFETs with biaxial and uniaxial strain. Int. Elec. Dev. Meet. 14
92. Kim SH, Fossum JG, Trinedi VP. 2005. Bulk inversion in FinFETs and implied insights on effective
gate width. IEEE Trans. Elec. Dev. 52:199397
93. Colinge JP. 2007. Quantum-wire effect in trigate SOI MOSFETs. Solid State Electron 51:115360
94. Welser J, Hoyt JL, Takagi SI, Gibbons JF, et al. 1994. Strain dependence of the performance enhancement
in strained-Si n-MOSFETs. Int. Electron Dev. Meet. 37376
95. Thompson SE, Sun G, Choi YS, Nishida T. 2006. Uniaxial-process-induced strained-Si: extending the
CMOS roadmap. IEEE Trans. Elec. Dev. 53:101020
96. Madelung O. 1991. Data in Science and Technology: Semiconductors-Group IV Elements and III-V Compounds.
Berlin: Springer. 164 pp.
97. Rosenberg JJ, Martin SC. 1988. Self-aligned germanium MOSFETs using a nitride native oxide gate
insulator. IEEE Elec. Dev. Lett. 9:63940
98. Martin SC, Hitt LM, Rosenberg J. 1989. p-channel germanium MOSFETs with high channel mobility.
99. Jackson TN, Ransom CM, DeGelormo JF. 1991. Gate-self-aligned p-channel germanium MISFETs.
100. Kesan VP, Subbanna S, Restle PJ, Tejwani MJ, Altken JM, et al. 1991. High performance 0.25 m
p-MOSFETs with silicon-germanium channels for 300 K and 77 K operation. Int. Elec. Dev. Meet. 2528
101. Murakami E, Nakagawa K, Nishida A, Miyao M. 1994. Fabrication of a strain-controlled SiGe/Ge
MODFET with ultrahigh hole mobility. IEEE Trans. Elec. Dev. 41:85761
102. Schafer F. 1997. High-mobility Si and Ge structures. Semicond. Sci. Technol. 12:151549
103. Reinking D, Kammler M, Hoffmann N, Hoegen MH, Hofmann KR. 1999. Fabrication of high-mobility
Ge p-channel MOSFETs on Si substrates. IEEE Elec. Lett. 35:5034
104. Yeo Y, Lu Q, King T, Hu C, Kawashima T, et al. 2000. Enhanced performance in sub100 nm CMOSFETs
using strained epitaxial silicon-germanium. Int. Elec. Dev. Meet. 75356
105. Ritenour A, Yu S, Lee ML, Lu N, Bai W, et al. 2003. Epitaxial strained germanium p-MOSFETs with
HfO2 gate dielectric and TaN gate electrode. Int. Elec. Dev. Meet. 43336
106. Shang H, Okorn-Schimdt H, Ott J, Kozlowski P, Steen S. 2003. Electrical characterization of germanium
p-channel MOSFETs. IEEE Elec. Dev. Lett. 24:24244
107. Datta S, Dewey G, Doczy M, Doyle BS, Jin B, et al. 2003. High mobility Si/SiGe strained channel MOS
transistors with HfO2 /TiN gate stack. Int. Elec. Dev. Meet. 65356
108. Tezuka T, Nakaharai S, Moriyama Y, Sugiyama N, Takagi S. 2005. High-mobility strained SiGe-oninsulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique. IEEE
Elec. Dev. Lett. 26:24345
109. Weber O, Bogumilowicz Y, Ernst T, Hartmann JM, Ducroquet F, et al. 2005. Strained Si and Ge
MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS. Int. Elec. Dev. Meet.
13740
110. Suthram S, Majhi P, Sun G, Kalra P, Harris HR, et al. 2007. High performance pMOSFETs using
Si/Si1x Gx /Si quantum wells with high-k/metal gate stacks and additive uniaxial strain for 22 nm technology node. Int. Elec. Dev. Meet. 72730
111. Xia ZL, Du G, Liu X, Kang J, Han R. 2005. Carrier effective mobilities in germanium MOSFET
inversion layer investigated by Monte Carlo simulation. Solid State Electron 49:194246
112. Ghosh B, Wang X, Fan X, Register LF, Banerjee SK. 2005. Monte Carlo study of germanium n- and
pMOSFETs. IEEE Trans. Elec. Dev. 52:54753
113. Ghosh B, Wang X, Fan X, Register LF, Banerjee SK. 2006. Monte Carlo study of strained germanium
nanoscale bulk pMOSFETs. IEEE Trans. Elec. Dev. 53:53337
114. Chui CO, Kim H, Chi D, Triplett BB, McIntyre PC, et al. 2002. A sub400 C germanium MOSFET
technology with high-k dielectric and metal gate. Int. Elec. Dev. Meet. 43740
115. Maeda T, Ikeda K, Nakaharai S, Tezuka T, Sugiyama N, et al. 2005. High mobility Ge-on-insulator
p-channel MOSFETs using Pt germanide Schottky S/D. IEEE Elec. Dev. Lett. 26:1024

ANRV380-MR39-09
228
Chu et al.

ANRV380-MR39-09
ARI
27 May 2009
15:5
116. Ashley T, Barnes AR, Buckle L, Datta S, Dean AB, et al. 2004. Novel InSb-based quantum well transistors
for ultrahigh speed, low power logic applications. Int. Solid State Integr. Circuits Technol. 3:225356
117. Chau R, Datta S, Doczy M, Doyle B, Jin B, et al. 2005. Benchmarking nanotechnology for highperformance and low-power logic transistor applications. IEEE Trans. Nanotechnol. 4:15358
118. Chau R, Datta S, Majumdar A. 2005. Opportunities and challenges of III-V nanoelectronics for future
high-speed, low-power logic applications. Compound Semicond. Integr. Circuit Symp. 1720
119. Datta S, Ashley T, Brask J, Buckle, Doczy M, et al. 2005. 85 nm gate length enhancement and depletion
mode InSb quantum well transistors for ultra high speed and very low power digital logic applications.
Int. Elec. Dev. Meet. 76366
120. Hudait MK, Dewey G, Datta S, Fastenau JM, Kavalieros J, et al. 2007. Heterogeneous integration
of enhancement mode In0.7 Ga0.3 As quantum well transistor on silicon substrate using thin (2 um)
composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications. Int. Elec. Dev.
Meet. 62528
121. Suthram S, Sun Y, Majhi P, Ok I, Kim H, et al. 2008. Strain additivity in III-V channels for CMOSFETs
beyond 22 nm technology node. VLSI Symp. Tech. Dig. 18283
122. Bai P, Auth C, Balakrishnan S, Bost M, Brain R, et al. 2004. A 65 nm logic technology featuring 35 nm
gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 m2 SRAM cell.
Int. Elec. Dev. Meet. 65760
123. Mistry K, Allen C, Auth C, Beattie B, Bergstrom D, et al. 2007. A 45 nm logic technology with highk+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100%
Pb-free packaging. Int. Elec. Dev. Meet. 24750
124. Xu Q, Duan X, Liu H, Han Z, Ye T. 2007. Low-cost and highly manufacturable strained-Si channel
technique for strong hole mobility enhancement on 35-nm gate length pMOSFETs. IEEE Trans. Elec.
Dev. 54:1394401
125. Yang B, Takalkar R, Ren Z, Black L, Dube A, et al. 2008. High-performance nMOSFET with in-situ
phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor. Int. Elec. Dev. Meet. 14
126. Mohta N, Thompson SE. 2005. Mobility enhancement: the next vector to extend Moores law. IEEE
Dev. Mag. 1823
229
AR380-FM
ARI
27 May 2009
16:16
Annual Review of
Materials Research
Contents

Volume 39, 2009
Materials Advances for Next-Generation Microelectronics

Molecular Electronics
James R. Heath p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 1
Phase Change Materials
Simone Raoux p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p25
Porous pSiCOH Ultralow-k Dielectrics for Chip Interconnects
Prepared by PECVD
Alfred Grill p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p49
Thin-Film Organic Electronic Devices
Howard E. Katz and Jia Huang p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p71
Immersion Lithography: Photomask and Wafer-Level Materials
Roger H. French and Hoang V. Tran p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p93
Materials for Optical Lithography Tool Application
Harry Sewell and Jan Mulkens p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 127
Nanoimprint Lithography Materials Development for Semiconductor
Device Fabrication
Elizabeth A. Costner, Michael W. Lin, Wei-Lun Jen, and C. Grant Willson p p p p p p p p p p p 155
High-/Metal Gate Science and Technology
Supratik Guha and Vijay Narayanan p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 181
Strain: A Solution for Higher Carrier Mobility in Nanoscale
MOSFETs
Min Chu, Yongke Sun, Umamaheswari Aghoram, and Scott E. Thompson p p p p p p p p p p p p p 203
Size-Dependent Resistivity in Nanoscale Interconnects
Daniel Josell, Sywert H. Brongersma, and Zsolt Tokei p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 231
Carbon Nanotube Interconnects
Azad Naeemi and James D. Meindl p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 255
Materials for Magnetoresistive Random Access Memory
J.M. Slaughter p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 277
viii
AR380-FM
ARI
27 May 2009
16:16
Current Interest
Chameleon Coatings: Adaptive Surfaces to Reduce Friction and Wear
in Extreme Environments
C. Muratore and A.A. Voevodin p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 297

Doped Oxides for High-Temperature Luminescence and Lifetime

Thermometry
M.D. Chambers and D.R. Clarke p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 325
Plasticity of Micrometer-Scale Single Crystals in Compression
Michael D. Uchic, Paul A. Shade, and Dennis M. Dimiduk p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 361
Recent Progress in the Study of Inorganic Nanotubes and
Fullerene-Like Structures
R. Tenne and G. Seifert p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 387
Recent Progress in Theoretical Prediction, Preparation, and
Characterization of Layered Ternary Transition-Metal Carbides
Jingyang Wang and Yanchun Zhou p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 415
Shape Memory Polymer Research
Patrick T. Mather, Xiaofan Luo, and Ingrid A. Rousseau p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 445
Solid-Surface Characterization by Wetting
Abraham Marmur p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p 473
Index
Cumulative Index of Contributing Authors, Volumes 3539 p p p p p p p p p p p p p p p p p p p p p p p p p p p 491
Errata
An online log of corrections to Annual Review of Materials Research articles may be
found at http://matsci.annualreviews.org/errata.shtml
Contents
ix

Strain Review

Transféré par

Informations du document

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Strain Review

Transféré par

Droits d'auteur :

Formats disponibles

ANRV380-MR39-09

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

Click here for quick links to

Strain: A Solution for Higher

Annu. Rev. Mater. Res. 2009. 39:20329

The Annual Review of Materials Research is online at

stress, uniaxial, biaxial, band structure, effective mass, scattering

This articles doi:

c 2009 by Annual Reviews.

Metal-oxide-semiconductor eld-effect transistors (MOSFETs) have shown

STRAIN ENGINEERING IN STATE-OF-THE-ART MOSFETs

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

Introduction: Why Strain?

Brief History of Strained Semiconductors

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

FinFET: n eldeffect transistor

Strain Definition and Piezoresistance Coefficient

Piezoresistance coefficients. The -coefcient gives straightforward experimental information

DOS: density of state

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

INSIGHTS INTO THE PHYSICS OF STRAINED CLASSICAL Si MOSFETs

Overview of How Strain Affects Carrier Mobility

<110> uniaxial tension

E Light hole like

<110> uniaxial tension

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

Light hole like

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

Subband Splitting Under Confinement and Strain for Different Surface

(001) surface Si MOSFETs

(110) surface Si MOSFETs

1 Bulk Si without strain

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

Strain-Induced Band Warping

<110> uniaxial tension (GPa)

<110> uniaxial tension (GPa)

Self-Consistent Simulation Procedure

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

Greater region around

Wave vector (k A1)

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

In[1 + exp(EF En / kbT)] |n(x)|2

V = V(x) V'(x) acceptable?

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

Scattering rate (s1)

Scattering rate (s1)

<110> uniaxial tension (GPa)

Optical phonon scattering

Mobility Enhancement of (100) nMOSFETs

Suband splitting (meV)

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

Mobility Enhancement of (100) and (110) pMOSFETs

<110> uniaxial compression (GPa)

<110> uniaxial compression (GPa)

<110> uniaxial compression (GPa)

2-D density of state

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

<110> uniaxial compression (GPa)

Annu. Rev. Mater. Res. 2009.39:203-229. Downloaded from www.annualreviews.org

pinv = 6 1012 cm2

Effective field (MV cm2)

<110> uniaxial compression (GPa)

Electric Field Dependence of Piezoresistance Coefficients