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PD60240 revA
IRS20124S(PbF)
DIGITAL AUDIO DRIVER WITH DISCRETE DEAD-TIME AND PROTECTION
Features
Product Summary
VSUPPLY
200V max.
IO+/-
1A / 1.2A typ.
70ns typ.
Bi-directional Over
Current Sensing
Package
14-Lead SOIC
SD
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IN
NC
OCSET1
NC
DT/SD
VB
OCSET2
HO
OC
VS
COM
NC
LO
VCC
IRS 20124
IRS20124S(PbF)
Description
The IRS20124S is a high voltage, high speed power MOSFET driver with internal dead-time and shutdown
functions specially designed for Class D audio amplifier applications.
The internal dead time generation block provides accurate gate switch timing and enables tight dead-time
settings for better THD performances.
In order to maximize other audio performance characteristics, all switching times are designed for immunity
from external disturbances such as VCC perturbation and incoming switching noise on the DT pin. Logic
inputs are compatible with LSTTL output or standard CMOS down to 3.0V without speed degradation. The
output drivers feature high current buffers capable of sourcing 1.0A and sinking 1.2A. Internal delays are
optimized to achieve minimal dead-time variations. Proprietary HVIC and latch immune CMOS technologies
guarantee operation down to Vs= 4V, providing outstanding capabilities of latch and surge immunities with
rugged monolithic construction.
Symbol
Definition
Min.
Max.
Units
VB
Vs
-0.3
VB-20
220
VB+0.3
V
V
VHO
VCC
VLO
VIN
Vs-0.3
-0.3
-0.3
-0.3
VB+0.3
20
Vcc+0.3
Vcc+0.3
V
V
V
V
VOC
-0.3
-0.3
-0.3
-
Vcc+0.3
Vcc+0.3
Vcc+0.3
50
V
V
V
V/ns
-55
1.25
100
150
150
W
C/W
C
C
300
VOCSET1
VOCSET2
dVs/dt
Pd
RthJA
TJ
TS
TL
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IRS20124S(PbF)
Symbol
Definition
Min.
Max.
Units
Vs+10
Note 1
Vs
10
Vs+18
200
VB
18
V
V
V
V
VB
VS
VHO
VCC
VLO
VIN
VOC
VOCSET1
0
0
0
0
VCC
VCC
VCC
VCC
V
V
V
V
VOCSET2
TA
0
-40
VCC
125
V
C
Note 1: Logic operational for VS equal to -8V to 200V. Logic state held for VS equal to -8V to -VBS.
Symbol
Definition
Min. Typ.
ton
60
80
VS=0V
toff
tr
tf
tsd
60
25
15
140
80
40
35
200
VS=200V
toc
280
OCSET1=3.22V
OCSET2=1.20V
OC pulse width
OC input filter time
100
200
15
40
VDT>VDT1
25
50
VDT1>VDT> VDT2
10
35
60
VDT2>VDT> VDT3
15
45
70
VDT3>VDT> VDT4
twoc min
toc filt
DT1
DT2
DT3
DT4
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nsec
IRS20124S(PbF)
Symbol
Min.
Typ.
2.5
Vcc=10~20V
VIL
VOH
VOL
UVCC+
8.3
9.0
1.2
1.2
0.1
9.7
Io=0A
Io=0A
UVCCUVBS+
UVBSIQBS
7.5
8.3
7.5
8.2
9.0
8.2
8.9
9.7
8.9
1
IQCC
ILK
IIN+
IIN-
3
0
4
50
10
1.0
Io+
IoVDT1
VDT2
1.0
1.2
VIH
Definition
VDT3
VDT4
VSOC+
VSOC-
Negative OC threshold in Vs
-1.0
-0.75
mA
VDT =Vcc
VB=VS =200V
VIN =3.3V
VIN =0V
Vo=0V, PW<10S
Vo=15V, PW<10S
OCSET1=3.22V
OCSET2=1.20
OCSET1=3.22V
OCSET2=1.20V
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IRS20124S(PbF)
Lead Definitions
Symbol Description
VCC
VB
HO
VS
IN
DT/SD
COM
LO
OC
OC SET1
OC SET2
IN
NC 14
OCSET1 NC 13
DT/SD
VB 12
OCSET2
HO 11
OC
VS 10
COM
NC
LO
VCC
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IRS20124S(PbF)
Block Diagram
VB
UV
DETECT
UV
Q
LEVEL
SHIFTER
IN
DEAD
TIME
S
R
HO
SD
VS
CURRENT
SENSING
DT/SD
Vcc
UV
DETECT
LO
DELAY
OCSET2
OCSET1
OC
COM
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IRS20124S(PbF)
50%
IN
50%
ton(L)
toff(L)
toff(H)
ton(H)
90%
HO
10%
DTLO-HO
DTHO-LO
90%
LO
10%
DT/SD
VSD
HO
LO
90%
TSD
Figure 2. Shutdown Waveform Definitions
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IRS20124S(PbF)
LO
COM
VS
toc filt
VS
VSoc+
COM
VSoc-
Vsoct
COM
OC
HIGH
OC
tdoc
COM
twoc
Figure 4. OC Waveform Definitions
IN
NC
OCSET1 NC
DT/SD
10k
VB
OCSET2 HO
__
OC
VS
15V
COM
Vsoc+
Vsoc-
LO
NC
VCC
15V
OC
Vsoc+
VS
COM
Vsoc-
OC
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IRS20124S(PbF)
200
Turn-on Delay Time (ns)
200
160
120
80
40
0
160
120
80
40
0
-50
-25
25
50
75
100
125
10
12
Temperature ( C)
120
120
150
18
20
18
20
150
Max.
60
Typ.
30
0
-50
16
90
14
Max.
90
60
Typ.
30
0
-25
25
50
75
Temperature (oC)
Figure 7A. Turn-Off Time
vs. Temperature
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100
125
10
12
14
16
IRS20124S(PbF)
60
Turn-On Rise Time (ns)
60
50
40
30
20
10
-50
50
40
30
20
10
-25
25
50
75
100
125
10
Temperature ( oC)
16
18
20
50
50
Turn-Off Fall Time (ns)
14
40
30
20
10
0
40
30
20
10
0
-50
-25
25
50
75
100
Temperature ( C)
Figure 9A. Turn-Off Fall Tim e
vs. Tem perature
10
12
125
10
12
14
16
18
20
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IRS20124S(PbF)
3
Min.
3
2
Min.
1
-50
-25
25
50
75
100
10
125
12
2
Max.
1
25
50
75
100
Temperatre ( C)
Figure 11A. Logic "0" Input Voltage
vs. Temperature
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18
20
-25
16
Temperature (oC)
0
-50
14
125
2
Max.
1
0
10
12
14
16
18
20
11
IRS20124S(PbF)
3
2
Max.
1
0
-1
-50
-25
25
50
75
100
4
3
2
Max.
1
0
10
125
12
18
20
0.25
0.25
Low Level Output Voltage (V)
16
Temperature (oC)
0.20
0.15
Max.
0.10
0.05
0.00
-50
-25
25
50
75
100
Temperature ( C)
Figure 13A. Low Level Output
vs.Temperature
12
14
125
0.20
0.15
Max.
0.10
0.05
0.00
10
12
14
16
18
20
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300
250
200
150
100
50
Max.
0
-50
-25
25
50
75
100
125
IRS20124S(PbF)
110
90
70
Max.
50
30
Typ.
10
-10
50
80
Temperature ( oC)
140
170
200
3
)
2.5
2.0
V BS Supply Current (
V BS Supply Current (
110
1.5
1.0
0.5
2
2
1
1
0
0.0
-50
-25
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25
50
75
100
125
10
12
14
16
18
Temperature (oC)
20
13
IRS20124S(PbF)
10
V cc Supply Current ()
10
8
6
4
Max.
2
0
-50
8
6
Max.
4
2
0
-25
25
50
75
100
10
125
12
18
20
30
)
30
24
16
Temperature (oC)
14
18
12
6
0
-50
-25
25
50
75
100
Temperature (oC)
Figure 17A. Logic "1" Input Current
vs. Tem perature
14
125
24
18
12
6
0
10
12
14
16
18
20
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5
Logic "0" Input Current ()
IRS20124S(PbF)
4
3
2
Max.
1
0
-50
-25
25
50
75
100
4
3
2
Max.
1
0
125
10
12
Temperature (oC)
16
18
20
11
10
V cc Supply Current ()
11
V cc Supply Current ()
14
10
Max.
9
Typ.
Min.
7
6
-50
-25
25
50
75
100
Temperature (oC)
Figure 19. V CC Undervoltage Threshold (+)
vs. Temperature
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125
Max.
Typ.
Min.
7
6
-50
-25
25
50
75
100
125
Temperature ( oC)
Figure 20. V CC Undervoltage Threshold (-)
vs. Temperature
15
IRS20124S(PbF)
11
)
11
V BS Supply Current (
V BS Supply Current (
10
9
8
7
10
9
8
7
6
6
-50
-25
25
50
75
100
-50
125
-25
100
125
1.5
Output Sink Current ()
1.5
Output Source Current ()
75
Temperature ( C)
1.3
1.1
0.9
Typ.
0.5
1.3
1.1
0.9
Typ.
0.7
0.5
10
12
14
16
18
16
50
o
Temperature (oC)
0.7
25
20
10
12
14
16
18
20
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-5
16
Typ.
-7
Max.
15
VDT 1(V)
IRS20124S(PbF)
-9
-11
-13
14
Typ.
13
Min.
12
-15
10
12
14
16
18
11
-50
20
-25
125
8
7
Max.
VDT 3(V)
VDT 2(V)
100
11
75
Temperature ( C)
50
o
10
25
Typ.
Min.
6
-50
-25
25
50
75
100
125
Temperature ( C)
Figure 27. DT mode select Threshold (2)
vs. Temperature
Max.
Typ.
5
4
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Min.
3
-50
-25
25
50
75
100
125
Temperature ( C)
Figure 28. DT mode select Threshold (3)
vs. Temperature
17
4.5
60
4.0
52
DTLO-HO (nsec)
VDT 4(V)
IRS20124S(PbF)
3.5
3.0
2.5
2.0
-50
-25
25
50
75
100
44
36
Typ.
28
20
-50
125
-25
2.0
-0.3
1.6
-0.6
Max.
1.2
Typ.
Min.
0.4
0.0
-25
25
50
75
100
125
Temperature ( oC)
Figure 31. Positive OC Threshold(+) in VS
vs. Tem perature
18
75
100
125
Negative OC TH(V)
Positive OC TH(V)
-50
50
Temperature ( C)
Temperature ( C)
0.8
25
Max.
-0.9
Typ.
-1.2
Min.
-1.5
-1.8
-50
-25
25
50
75
100
125
Temperature ( C)
Figure 32. Negative OC Threshold(-) in VS
vs. Temperature
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65
65
55
55
45
140V
70V
0V
35
25
Temperature (oC)
Temperature (oC)
IRS20124S(PbF)
140v
70v
0v
45
35
25
15
15
1
10
100
1000
100
Figure 333.
4 . IRS20124s vs. Frequency (IRFBC30)
Rgate=22 , V CC=12V
Figure 32.
33. IRS20124s vs. Frequency (IRFBC20)
Rgate=33 , VCC=12V
65
75
140V
140V
70V
0V
45
35
25
Temperature (oC)
65
55
1000
Frequency (KHZ)
Frequency (KHZ)
Temperature (oC)
10
70V
0V
55
45
35
25
15
15
1
10
100
1000
Frequency (KHZ)
5. IRS20124s vs. Frequency (IRFBC40)
Figure 334.
Rgate=15 , V CC=12V
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10
100
1000
Frequency (KHZ)
6. IRS20124s vs. Frequency (IRFPE50)
Figure 335.
Rgate=10 , V CC=12V
19
IRS20124S(PbF)
Functional description
90%
Effective dead-time
Programmable Dead-time
The IRS20124 has an internal dead-time generation
block to reduce the number of external components
in the output stage of a Class D audio amplifier.
Selectable dead-time through the DT/SD pin voltage is an easy and reliable function, which requires only two external resistors. The dead-time
generation block is also designed to provide a
constant dead-time interval, independent of Vcc
fluctuations. Since the timings are critical to the
audio performance of a Class D audio amplifier,
the unique internal dead-time generation block is
designed to be immune to noise on the DT/SD
pin and the Vcc pin. Noise-free programmable
dead-time function is available by selecting deadtime from four preset values, which are optimized
and compensated.
How to Determine Optimal Dead-time
Please note that the effective dead-time in an actual
application differs from the dead-time specified in
this datasheet due to finite fall time, tf. The deadtime value in this datasheet is defined as the time
period from the starting point of turn-off on one
side of the switching stage to the starting point of
turn-on on the other side as shown in Fig.5. The
fall time of MOSFET gate voltage must be subtracted from the dead-time value in the datasheet
to determine the effective dead time of a Class D
audio amplifier.
(Effective dead-time)
= (Dead-time in datasheet) (fall time, tf)
20
HO (or LO)
10%
tf
LO (or HO)
Deadtime
10%
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IRS20124S(PbF)
DT/SD pin
DT/SD pin provides two functions: 1) setting deadtime and 2) shutdown. The IRS20124 determines
its operation mode based on the voltage applied
to the DT/SD pin. An internal comparator
translates which mode is being used by comparing
internal reference voltages. Threshold voltages for
each mode are set internally by a resistive voltage
divider off Vcc, negating the need of using a precise
absolute voltage to set the mode.
The relationship between the operation mode and
the voltage at DT/SD pin is illustrated in the Fig.7.
Operational Mode
15nS
25nS
Dead-time
35nS
Deadtime
mode
DT1
DT2
DT3
DT4
R1
R2
DT/SD
voltage
<10k
3.3k
5.6k
8.2k
Open
8.2k
4.7k
3.3k
1.0 x Vcc
0.71 x Vcc
0.46 x Vcc
0.29 x Vcc
Shutdown
Since IRS20124 has internal dead-time generation, independent inputs for HO and LO are no
longer provided. Shutdown mode is the only way
to turn off both MOSFETs simultaneously to protect them from over current conditions. If the DT/
SD pin detects an input voltage below the threshold, VDT4, the IRS20124 will output 0V at both HO
and LO outputs, forcing the switching output node
to go into a high impedance state.
45nS
Shutdown
0.23xVcc
0.36xVcc
0.57xVcc
0.89xVcc Vcc
VDT
Design Example
Table 1 shows suggested values of resistance for
setting the deadIRS20124
time. Resistors with
>0.5mA
Vcc
up to 5% tolerance
can be used if these
R1
listed values are folDT/SD
lowed.
R2
COM
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Application
In a Class D audio amplifier, the direction of the
load current alternates according to the audio input signal. An over current condition can therefore
happen during either a positive current cycle or a
negative current cycle. Fig.9 shows the rela21
IRS20124S(PbF)
Load Current
+
OC SET1
OR
OCSET2
AND
OC
+
-
vs
~
~
~
~
~
~
~
~
~ ~
~
~
~
~ ~
~
~
~
~
~
~
~
Vsoc+
COM
Vsoc-
(a ) Normal Operation
Condition
(b ) Over- Current in
Positive Load Current
(c ) Over- Current in
Negative Load Current
22
As shown in Fig.11, bi-directional current sensing block has an internal 2.0V level shifter feeding
the signal to the comparator. OCSET1 sets the positive side threshold, and is given a trip level at VSOC+,
which is OCSET1 - 2.0V. In same way, for a given
OCSET2, VSOC- is set at OCSET2 2.0V
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IRS20124S(PbF)
>0.5mA
Vcc
R3
OCSET1
R4
OCSET2
R5
COM
IRS20124S(PbF)
Voltage in Vs
OC Output Signal
The OC pin is a 20V open drain output. The OC
pin is pulled down to ground when an over current
condition is detected. A single external pull-up
resistor can be shared by multiple IRS20124 OC
pins to form the ORing logic. In order for a microprocessor to read the OC signal, this information
is buffered with a mono stable multi vibrator to
ensure 100ns minimum pulse width.
Because of unpredictable logic status of the OC
pin, the OC signal should be ignored during power
up/down.
Limitation from Body Diode in MOSFET
When a Class D stage outputs a positive current,
flowing from the Class D amp to the load, the body
diode of the MOSFET will turn on when the Drain
to Source voltage of the MOSFET become larger
than the diode forward drop voltage. In such a
case, the sensing voltage at the Vs pin of the
IRS20124 is clamped by the body diode. This
means that the effective Rds(on) is now much
lower than expected from Rds(on) of the MOSFET,
and the Vs node my not able to reach the threshold to turn the OC output on before the MOSFET
fails. Therefore, the region where body diode
clamping takes a place should be avoided when
setting VSOC-.
Load
Current
Vsoc- should be
set in this region
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 322 3331
Data and specifications subject to change without notice.
9/21/2005
24
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