29 de enero

EXAMEN PARCIAL 1 – MICROPROCESADORES SOLUCIÓN

de 2009

1. Describir en VHDL, por el modelo de comportamiento, la función lógica dada

por el siguiente Karnaugh.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity prob1 is
Port ( sal : out STD_LOGIC:='0';
X1,X2,X3,X4 : in STD_LOGIC);
end prob1;

architecture Behavioral of prob1 is

signal x:std_logic_vector(1 to 4);
begin
x <= X1&X2&X3&X4;
process(x)

begin
case x is
when "0001" | "0010" | "0100" | "0101" | "1010" | "1011" | "1100" => sal <= '1';
when others => sal <= '0';
end case;
end process;
end Behavioral;

2. Confeccionar el Karnaugh representativo del siguiente código. Luego

rescribirlo utilizando la sentencia if-else.

1
 29 de enero
EXAMEN PARCIAL 1 – MICROPROCESADORES SOLUCIÓN
de 2009

entity karnaugh is
port (x: in bit_vector(0 to 3); z: out bit);
end;

architecture beh of karnaugh is

signal w1, w2, w3, w4: bit;
begin
process(x)
begin
case x is
when "0100" | "0101" | "1100" | "1010" | "1011" | "0010"
=> z <= '1';
when others => z <= '0';
end case;
end process;
end;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity prob2 is
Port ( x : in bit_vector (0 to 3);
z : out bit);
end prob2;

architecture Behavioral of prob2 is

begin
process(x)
begin
if (x = "0010") then
z <= '1';
else
if (x = "0100") then
z <= '1';
else
if (x = "0101") then
z <= '1';
else
if (x = "1010") then
z <= '1';
else

2
 29 de enero
EXAMEN PARCIAL 1 – MICROPROCESADORES SOLUCIÓN
de 2009

if (x = "1011") then
z <= '1';
else
if (x = "1100") then
z<= '1';
else
z <= '0';
end if;
end if;
end if;
end if;
end if;
end if;
end process;

end Behavioral;

3. Empleando en combinación las estructuras IF.. THEN.. ELSE y CASE.. WHEN..

WHEN OTHERS describa el decodificador de la figura. Emplee la primera
estructura para determinar si hay o no habilitación y la segunda para
resolver las salidas en habilitación.
Use la entidad:

ENTITY Decoder IS PORT(

E: IN std_logic;
A: IN std_logic_vector(2 DOWNTO 0);
Y: OUT std_logic_vector(7 DOWNTO 0));
END Decoder;

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 29 de enero
EXAMEN PARCIAL 1 – MICROPROCESADORES SOLUCIÓN
de 2009

Utilice el estado ‘Z’ para indicar alta impedancia para Y en el caso de no

habilitación (E =’0’). Emplee en WHEN OTHERS la asignación NULL.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity prob3 is
Port ( E : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0));
end prob3;

architecture Behavioral of prob3 is

begin
Process(E,A) is
begin
if E='0' then
Y <= "ZZZZZZZZ";
else
case A is
when "000" => Y <= X"01";
when "001" => Y <= X"02";
when "010" => Y <= X"04";
when "011" => Y <= X"08";
when "100" => Y <= X"10";
when "101" => Y <= X"20";
when "110" => Y <= X"40";
when "111" => Y <= X"80";
when others => null;
end case;
end if;
end process;

end Behavioral;

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 29 de enero
EXAMEN PARCIAL 1 – MICROPROCESADORES SOLUCIÓN
de 2009

4. Diseñe un decodificador BCD a 7 segmentos usando el bloque de proceso

(process block) de VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity prob4_tb is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
sal : out STD_LOGIC_VECTOR (6 downto 0));
end prob4_tb;

architecture Behavioral of prob4_tb is

begin
process(A) is
begin
case A is ; gfedcba
when "0000" => sal <= "1000000";
when "0001" => sal <= "1111001";
when "0010" => sal <= "0100100";
when "0011" => sal <= "0110000";
when "0100" => sal <= "0011001";
when "0101" => sal <= "0010010";
when "0110" => sal <= "0000010";
when "0111" => sal <= "1111000";
when "1000" => sal <= "0000000";
when "1001" => sal <= "0010000";
when others => sal <= "1111111";
end case;
end process;

end Behavioral;