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Computer System Architecture Processor Part I Chalermek Intanagonwiwat Slides courtesy of John Hennessy and David Patterson The Big Picture (cont.) + Processor design (datapath and control) will determine: ~ Clock cycle time ~ Clock cycles per instruction + Today: - Single cycle processor: + Advantage: One clock cycle per instruction + Disadvantage: long cycle time FEST Wi mw The Big Picture: The —keputee. Performance Perspective camsyipacn cewmncan 3 + Performance of a machine is determined by: va) q. Instruction count ©-Clock cycle time ——tnst. Count cycle Time © -Clock cycles per instruction How to Design a Processor: step- by-step a 1. Analyze instruction set => datapath requirements - the meaning of each instruction is given by the Register Transfer Language (RTL) - datapath must include storage element for ISA registers + possibly more - datapath must support each register transfer How to Design a Processor i (CONT) 7 stern e 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting the requirements “icons oles 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic The MIPS Instruction Formats (cont.) + The different fields are: the instruction ‘ource and destination register = rs, rt, rd: specifiers ~ shamt: shift amount - funct: selects the variant of the operation in the “op" field sienna opt - address / immediate: address offset or immediate value ~ target address: target address of the jump instruction The MIPS Instruction Formats + All MIPS instructions are 32 bie pons: The three instuctien formats: « ie aE Sia (acer faa eee oa wnt “Type Ca ee he Pee may ‘T-type eons 26 bits Step 1a: The MIPS-lite Subset + ADD and SUB (ype? - addU rd) rs, rt | ~ subU rd, rs, rt | mow oa 6 6 © (ep [ee aha [fone] Gbire Shoe Bbta Site Sore obits Cate + OR Immediate: ~ = - ori rt.rs,immi6 se inn ftshuct ean erm Shs ot nate @ [= [a Gone bts Stine 16 bite venta wiy mtr soa lod stn lysF 8 rey Step la: The MIPS-lite Subset Logical Register Transfers (cont.) STeeT | ured en + LOAD and STORE Word + RTL gives the meaning of the ~ Iwrt, rs, imm16 instructions ~ sw rt, rs, imm16 4 sage a? tae ee 4 + All start by fetching the Se ee i i = tine “Sbis Sb ‘ebre instruction | + BRANCH: 1 | = beq rs, rt, imml6 | L \ L Note; opeietion Wuuwe 32 bit — ivi Logical Register Transfers Step 1! Requirements of the a (cont.) Instruction Set Jan f Combes Let Ld | shar | fet = MEM P soniye En sur ec Ye regi! + Memory paplestet | Inme eMC PC} . ; ate 7 anew enn is sr ~instruction & data inst Register Transfers ee t | . i: sooo Wey «pe « be wpe +8 | Registers (32 x 32) ‘SUBU — ‘Rird) <- Rirs) - R[rt); Pe - Get] «soem: PE read RS 1 swesnemiste 2 LOAD — fet] MEME Rirs] + signext(lmml6}}: | PC «PC A -read RT STORE MEME Rirs) + sign_ext(mml6)] <- Rirt); PC PC +4 - Write RT or RD iritinreor rin BEQ if ( Rips} == Rfrt) ) then ‘ ‘ PC <- PC + sign_ext(Emmi6)} 11/00) 3 : — eal © PC —rregemn camter else PC PC 4 ; ons broindn enuuriven jump tu de dingteuckion Finda gece ee eahy eure instwotionth ybytes