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Features

Figure 1-1. Block Diagram ofthe ADC Module

I System I High-speed I .... SYSCLKOUT I C28x I
control block prescaler J t

ADCENCLK HALT HSPClK
Analog Result Registers
MUX
r---- Result Reg 0 70A8h
ADCINAO
· Result Reg 1
· S/H-A
• ·
ADCINA7"-. •
•
...._
12-Bit k Result Reg 7 70AFh
ADC -I Result Reg 8 70BOh
r---- module
ADCINBO"

•
• ·
· SIH-B ·
•
ADCINB7"> Result Reg 15 70B7h
T
J t
srw__._ ADC Control Registers [-04- srw
ePWMx SOC A ____...... SOC Sequencer 1 Sequencer 2 SOC ~ ePWMx
GPlo/xINT;~
ADCSOC SOCB

Address(2)

Table 1-1. ADC Registers

Description

Name

Address(1)

Size (x16)

ADCTRl1 ADCTRl2 ADCMAXCONV ADCCHSELSEQ1 ADCCHSElSEQ2 ADCCHSELSEQ3 ADCCHSELSEQ4 ADCASEQSR ADCRESULTO ADCRESULT1 ADCRESULT2 ADCRESULT3 ADCRESULT4 ADCRESULT5 ADCRESULT6 ADCRESULT7 ADCRESULT8

ADCRESULT9

Ox71 00 Ox7101 Ox71 02 0)(7103 Ox71 04 Ox71 05 Ox71 06 Ox71 07 Ox71 08 Ox7109 Ox710A Ox710B Ox710C Ox71 00 Ox710E Ox71 OF Ox7110 Ox7111

~yc> 1

LNb-~tStJ;-.Q,j 1 . 1

OxOBOO

OxOB01

OxOB02

OxOB03

OxOB04

OxOB05

OxOB06

OxOB07

OxOBOO

/J"3" . '\_..,,, ~!\}J() (1)

r? __ Pf..V" (2)

ADC Control R.egister 1 ADC Control Register 2

ADC Maximum Conversion Channels Register

AbC Channel Select SequenCing Control Register 1 Abc Channel Select Sequencing Control Register 2 ADC Channel Select Sequencing Control Register 3 AOC Channel Select SequenCing Control Register 4 ADC Auto-Sequence Status Register

AbC Conversion Result Buffer Register 0

ADC Conversion Result Buffer Register 1

ADC Conversion Result Buffer Register 2

ADC Conversion Result Buffer Register 3

ADC Conversion Result Buffer Register 4

ADC Conversion Result Buffer Register 5

ADC Conversion Result Buffer Register 6

ADC Conversion Result Buffer Register 7

ADC Conversion Result Buffer Register 8

ADC Conversion Result Buffer Register 9

The registers in this column are Peripheral Frame 2 registers.

The ADC result registers are dual mapped in the device. Locations in Peripheral Frame 2 (Ox7108-0x7117) are 2 wait states and left justified. Locations in Peripheral Frame 0 space (OxOBOO-OxOBOF) are 0 wait states and right justified. During high speed/continu s conversion use of the ADC, use the 0 wait state locations to avoid missing ADC conversions.

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Autoconversion Sequencer Principle of Operation

A C Registers (continued)
Name Address (1 I Size (xi6) Description
ADCRESUL T10 Ox7112 OxOBOA 1 ADC Conversion Result Buffer Register 10
ADCRESUL T11 Ox7113 OxOBOB ADC Conversion Result Buffer Register 11
ADCRESUL T12 Ox7114 OxOBOC ADC Conversion Result Buffer Register 12
ADCRESUL T13 Ox7115 OxOBOD ADC Conversion Result Buffer Register 13
ADCRESUL T14 Ox7116 OxOBOE ADC Conversion Result Buffer Register 14
ADCRESUL T15 Ox7117 OxOBOF ADC Conversion Result Buffer Register 15
ADCTRL3 Ox7118 ADC Control Register 3
ADCST Ox7119 ADC Status Register
Reserved Ox711A 2
Ox711B
ADCREFSEL Ox711C ADC Reference Select Register
ADCOFFTRIM Ox711D ADC Offset Trim Register
Reserved Ox711E 2 ADC Status Register
Ox711F To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCINxx pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins from the digital supply.

1.2 Autoconversion Sequencer Principle of Operation

The ADC sequencer consists of two independent 8-state sequencers (SEQ1 and SEQ2) that can also be cascaded together to form one 16-state sequencer (SEQ). The word "state" represents the number of autoconversions that can be performed with the sequencer. Block diagrams of the single (16-state, cascaded) and dual (two 8-state, separated) sequencer modes are shown in Figure 1-4 and Figure 1-5, respectively.

In both cases, the ADC has the ability to autosequence a series of conversions. This means that each time the ADC receives a start-of-conversion request, it can perform multiple conversions automatically. For every conversion, anyone of the available 16 input channels can be selected through the analog MUX. After conversion, the digital value of the selected channel is stored in the appropriate result register (ADCRESUL Tn), (The first result is stored in ADCRESUL TO, the second result in ADCRESUL T1, and so on). It is also possible to sample the same channel multiple times, allowing the user to perform "over-sampling", which gives increased resolution over traditional single-sampled conversion results.

Note: In the sequential sampling dual-sequencer mode, a pending SOC request from either sequencer is taken up as soon as the sequence initiated by the currently active sequencer is finished. For example, assume that the AID converter is busy catering to SEQ2 when an SOC request from SEQ1 occurs. The AID converter will start SEQ1 immediately after completing the request in progress on SEQ2. If SOC requests are pending from both SEQ1 and SEQ2, the SOC for SEQ1 has priority. For example, assume that the AID converter is busy catering to SEQ1. During that process, SOC requests from both SEQ1 and SEQ2 are made. When SEQ1 completes its active sequence, the SOC request for SEQ1 will be taken up immediately. The SOC request for SEQ2 will remain pending.

The ADC can also operate in simultaneous sampling mode or sequential sampling mode. For each conversion (or pair of conversions in simultaneous sampling mode), the current CONVxx bit field defines the pin (or pair of pins) to be sampled and converted. In sequential sampling mode, all four bits of CONVxx define the input pin. The MSB defines which sample-and-hold buffer the input pin is associated with, and the three LSBs define the offset. For example, if CONVxx contains the value 0101b, ADCINA5 is the selected input pin. If it contains the value 1011b, ADCINB3 is the selected input pin. In simultaneous

12

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Autoconversion Sequencer Principle of Operation

Figure 1-4. Block Diagram of Autosequenced ADC in Cascaded Mode

ResultMUX

· · ·

select

12-bit analog-to-digital converter (AOG)

12

AOCINA? -----jl>-

.____,

•

•

AOCIN80 -----jl>-

•

AOCINB1 -----jl>- MUX

AOCRESULTl

Result select

EOG

soc

·

• select

·

AOCINB? -----jl>-

MAX_GONV1

State

Ch Sel (CONVOO) pointer
Ch Sel (CONV01)

Ch Sel (CONV02) MUX
Ch Sel (CONV03) select
•
•
•
Ch Sel (CONV15) 4

4

Autosequencer state machine

Note: Possible values are:

Channel select = 0 to 15 AOCMAXCONV :: 0 to 15

Software ePWMxSOCA

Start-of-sequence trigger

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Features

1.1 Features

The ADC module has 16 channels, configurable as two independent 8-channel modules to service the ePWM modules. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 1-1 shows the block diagram of the AOC module.

The two 8-channel modules can autosequence a series of conversions; each module has the choice of selecting anyone of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is completed, the selected channel value is stored in its respective ADCRESUL T register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This oversampllng gives increased resolution over traditional single-sampled conversion results.

Functions of the AOC module include:

• 12-bit AOC core with built-in dual sample-and-hold (S/H)

• Simultaneous sampling or sequential sampling modes

• Analog input: 0 V to 3 V

• Fast conversion time runs at 12.5 MHz; AOC clock, or 6.25 MSPS

• 16-channel, multiplexed inputs

• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion can be programmed to select any 1 of 16 input channels.

• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers).

• Sixteen result registers (individually addressable) to store conversion values - The digital value of the input analog voltage is derived by:

Digital Value = 0,

O· 't I V I 4096 Input Analog Voltage

Igi a aue = x 3

Digital Value = 4095,

when input s 0 V

when 0 V < input < 3 V

A All fractional values are truncated.

• Multiple triggers as sources for the start-of-conversion (SOC) sequence - SIW - software immediate start

- ePWM 1-6

- GPIOXINT2

when input ~ 3 V

• Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS

• Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronize conversions.

• ePWM triggers can operate independently in dual-sequencer mode.

• Sample-and-hold (StH) acquisition tlme window has separate prescale control.

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10 Ana/og-tq-Digital Converter (ADC)

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,11 TLC5615C, TLC56151

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SlAS142E-OCTOBER 1996-REVlSED JUNE 2007

APPLICATION INFORMATION

GENERAL FUNCTION

The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digital data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the same polarity as the reference input (see Table 1).

An internal circuit resets the DAC register to aU zeros on power up.

Figure 9. TLC5615 Typical Operating Circuit

Table 1. Binary Code Table (OV to 2VREFINOutPut), Gain = 2

INPUT(1) OUTPUT
1111 1111 11(00) ( ) 1023
2 VREFIN 1024
1000 0000 01(00} ( ) 513
2 VREFIN 1024
1000 0000 00(00) ( ) 512
2 VREFIN 1024 .. VREFIN
0111 1111 11(00) ( ) 511
2 VREFIN 1024
0000 0000 01(00) 2(VREFIN) 1d24
0000 0000 00(00) OV (1) A 10·bit data word with two bits below the LSB bit (sub-LSB) with 0 values must be written since the DAC input latch is 12 bits wide,

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TLC5615C, TLC56151

SLAS142E-OCTOBER 1996-AEVISED JUNE 2007

OPERATING CHARACTERISTICS

over recommended operating free-air temperature range. Vee = 5V :1:5%. Vref = 2.048V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT DYNAMIC PERFORMANCE
SR Output slew rate CL= 100pF, RL= 10kQ, 0.3 0.5 Vlf'.S
TA=+25°C
ts Output setUing time ToO.5LSB, CL = 100pF. (1) 12.5 ILS
RL= 10kO.
Glitch energy DIN = All Os to alils 5 nV-s
REFERENCE INPUT (REFIN)
Reference feedthrough REAN = 1Vpp at 1kHz + 2.048Vdc (2) -80 dB
Reference input REFIN = 0.2Vpp + 2.048Vdc 30 kHz
bandwidth (f-adB) (1) Settling time is the time for the output signal to remain Within zO.5LSB of the final measured value for a digital input code change of 000 hex to 3FF hex or 3FF hex to 000 hex.

(2) Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048Vdc + 1Vpp at 1kHz.

PARAMETER MEASUREMENT INFORMATION

cs
~CSHO) I ... ~4 III tau(CSS)
I I tw(CH) loll tJ4 III twcCL) th(CSH1)--1
I I I I I
SCLK J '}_

!+- Iw(CS) -JII

loll tJ lsu(CS1)

I

I

I I

tau(DS) 14 1114 tI th(oH)

~J II

DIN~ x ~

ipd(OOUT) _..L.--.t.1

DOUT~~ __ ~~_e_VI_OU_S_LS __ B -J>< -J

See Note B

:

X X X:
MSB X LSB NOTES: A. The input clock, applied at the SCLl< terminal, should be inhibited low when CS is high to minimize clock feedthrough.

B. Data input from precesding conversion cycle.

C. Sixteenth SCLK falling edge

Figure 1. Timing Diagram

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TLC5615C, TLC56151

SlAS142E-OCTOBER 1996- REVISED JUNE 2007

-- -----------------

BUFFER-A"M-P[lFlE-A The output buffer has a rail-to-rejl output with short circuit protection and can drive a 2kO load with a 100pF load capacitance. Settling time is 12.S!AS typical to within O.SLSB of final value.

EXTERNAL REFERENCE

The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore, the REFIN input resistance is 10MO and the REFIN input capacitance is typically SpF independent of input code. The reference voltage determines the DAC full-scale output.

LOGIC INTERFACE

The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic levels.

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the TlC5615 timing. The maximum serial clock rate is:

f - 1

(SClK)max - tw(CH) + tw(Cl)

or approximately 14MHz. The digital update rate is limited by the chip-select period, which is: tp(GS) = 16 x (tW(CH) + tW(CL)) + tw(CS)

and is equal to 820ns which is a 1.21MHz update rate. However, the DAC settling time to 10 bits of 12.S,...s limits the update rate to 80kHz for full-scale input step transitions.

SERIAL INTERFACE

When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most significant bit first. The rising edge of the SlCK input shifts the data into the input register.

The rising edge of ~ then transfers the data to the DAC register. When CS' is high, input data cannot be clocked into the input r ister. All CS tranSitions should occur when the SClK in ut is low.

If the alsy chain (cascading) function (see daisy·chaining devices section) is not used, a 12-bit input data sequence with the MSS first can be used as shown in Figure 10:

4-----------------12Blts ----------------_...,

II

x II x I

2 Extra (Sub-LSB) B0

10 Data Bits

MSB

LSB

x= don't care

Figure 10. 12wBIt Input Data Sequence

or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first.

4-----------------16B~---------------------__.

4 Upper Dummy BHs

II

x

II

II

10DataBHs

x

MSB

LSB

2 Extra (Sub-LSB) Bits

x e dont care

Figure 11. 16-Bit Input Data Sequence

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