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  • Axi4 Protocol Specification Slave

    Transféré par

    Vilas Kumar K
    42 vues4 pages
    This document describes an AXI4 protocol specification for a slave device. It includes a block diagram showing the write and read channels between the slave and master with associated signal names. It also provides a state diagram showing the states and transitions for the slave during read and write address, data and response phases.

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    Titre original

    AXI4

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    © Attribution Non-Commercial (BY-NC)

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    This document describes an AXI4 protocol specification for a slave device. It includes a block diagram showing the write and read channels between the slave and master with associated signal names. It also provides a state diagram showing the states and transitions for the slave during read and write address, data and response phases.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme DOCX, PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    42 vues4 pages

    Axi4 Protocol Specification Slave

    Transféré par

    Vilas Kumar K
    This document describes an AXI4 protocol specification for a slave device. It includes a block diagram showing the write and read channels between the slave and master with associated signal names. It also provides a state diagram showing the states and transitions for the slave during read and write address, data and response phases.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme DOCX, PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 4

    AXI4

    PROTOCOL
    SPECIFICATION SLAVE
    INTRODUCTION :

    SPECIFICATION :

    FEATURES :
    BLOCK DIAGRAM (BLACK BOX):

    AWADDR[31:0] AWREADY

    AWVALID WREADY WRITE

    WDATA[31:0] CHANNEL
    BID

    WVALID BRESP

    BREADY SLAVE BVALID

    ARADDR[31:0]

    RDATA[31:0]

    ARVALID

    ARREADY READ

    RREADY CHANNEL
    RVALID

    RRESP
    STATE DIAGRAM :
    ARADDR,ARVALID,ARREADY are asserted
    SLAVE
    IDLE AWREADY,AWADDR,A
    WVALID are asserted

    WREADY=1

    RREADY=0
    WRITE
    READ ADDRESS
    ADDRESS
    WVALID=1

    READY=1 WREADY=1 d

    WLAST=0
    WRITE
    RLAST=0
    DATA
    READ
    DATA

    WLAST=1

    RLAST=1

    BRESP=0,BVALID=0,BREADY=0

    DATA DATA
    OUT

    BRESP=1
    BVALID=1
    BREADY=1

    WRITE
    RESPONS
    E

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