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UNIT - I
Unit-I Introduction
• Number representation DIGITAL
– Fixed and floating point number representation LOGIC
DESIGN
– IEEE standard for floating point
representation.
– Error detection and correction codes:
Hamming code.
• Digital computer
– Generation
– Computer types and classifications,
COMPUTER
– Functional units and their interconnections CONCEPTS
– Buses, bus architecture, types of buses and &C
bus arbitration. PROGRAMMING
• Register, bus and memory transfer.
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– Microprocessor concept - Motorola, Texas Instruments were the major Peripheral (IO) interface control unit
companies
– Parallelism, Pipelining , Cache , Virtual Memories evolved to produce
high performance
– Computing systems of today
System Bus
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Operation (c) Processing from/to storage Operation (d) Processing from storage to I/O
Input Control
Output Unit
Communication
lines
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Most important to the system bus model, the communications among the
components are by means of a shared pathway called the system bus , which
is made up of the data bus (which carries the information being transmitted),
the address bus (which identifies where the information is being sent), and
the control bus (which describes aspects of how the information is being
sent, and in what manner).
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Application
Application
High-level language
High-level language
Assembly language
Assembly language
Operating System machine
Operating System machine
Conventional machine level
Conventional machine level
Microarchitecture
Microarchitecture
Digital Logic
Digital Logic
Levels, abstractions and virtual machines Levels, abstractions and virtual machines
Add A=2 and B=3 Application Add 2 and 3 Application C, C++, BASIC,
C:=A+B; High-level language PASCAL, Java,
etc..
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Levels, abstractions and virtual machines Levels, abstractions and virtual machines
Add 2 and 3 Application ldc num1 Add A=2 and B=3 Application
C:=A+B; ldc num2 C:=A+B;
High-level language add
High-level language Pentium MMX,
ldc num1 ldc num1 SPARC, etc…
ldc num2
add Assembly language ldc 100 ldc num2
add Assembly language
stnl 0
… system calls Operating System machine
Levels, abstractions and virtual machines Levels, abstractions and virtual machines
Add A=2 and B=3 Application Add A=2 and B=3 Application
C:=A+B; High-level language C:=A+B; High-level language
ldc num1 ldc num1
ldc num2
add Assembly language ldc num2
add Assembly language
system calls Operating System machine system calls Operating System machine
1s and 0s Conventional machine level 1s and 0s Conventional machine level
Arrays & flow Microarchitecture
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UNIT - I
• Combinational and sequential circuits can be used to create simple digital • The operations on the data in registers are called
systems. microoperations.
• These are the low-level building blocks of a digital computer. • The functions built into registers are examples of
• Registers + Operations performed on the data stored in them = Digital Module microoperations
• Modules are interconnected with common data and control paths to form a digital – Shift
computer system – Load
• Simple digital systems are frequently characterized in terms of – Clear
– the registers they contain, and – Increment
– the operations that they perform. – …
• Typically, • The result of the operation may replace the previous binary
– What operations are performed on the data in the registers information of a register or may be transferred to another
– What information is passed between registers register.
Shift Right Operation
101101110011 010110111001
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Microoperation MICROOPERATION
• Definition of the (internal) organization of a computer The microoperations performed on the information stored in
registers depend on the type of data that reside in the
-Set of registers and their functions registers. The binary information commonly found in registers
of digital computers can be classified into three categories:
-Information stored in these registers 1. Numerical data such as binary numbers or binary-coded
-Can be binary, BCD, Alphanumeric characters or control info
decimal numbers used in arithmetic computations.
- Microoperations set 2. Nonnumerical data such as alphanumeric characters or other
binary-coded symbols used for special applications.
•Set of allowable microoperations provided by the organization of the
computer 3. Instruction codes, addresses, and other control information
used to specify the data-processing requirements in the
•Depend on the type of information encountered system.
- Control signals that initiate the sequence of microoperations
(to perform the functions)
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UNIT - I
• Viewing a computer, or any digital system, • Rather than specifying a digital system in words, a specific notation
is used, register transfer language
in this way is called the register transfer
level • For any function of the computer, the register transfer language
can be used to describe the (sequence of) microoperations
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R2 ← R1
• Common ways of drawing the block diagram of a register
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Register Transfer
Load
Transfer occurs here
• The same clock controls the circuits that generate the control function
and the destination register
• Registers are assumed to use positive-edge-triggered flip-flops
1 2
Register Transfer
Illegal Simultaneous Transfers BASIC SYMBOLS FOR REGISTER
TRANSFERS
• Example of an illegal operation, since A must be
loaded with two different values simultaneously.
Symbols Description Examples
Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
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Register Transfer
Connecting Registers with Multiplexers CONNECTING REGISTRS
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• The number of wires will be excessive if separate lines are used • A more efficient scheme for transferring information between
between each register and all other registers in the system ! registers in a multiple-register configuration is a common bus
system
P1 P2 P1 P2
P6 P3 P6 P3
P5 P4 P5 P4
To connect n items with direct connections, you To connect n items with bus connections, you need
need n(n-1)/2 connections. only n connections.
8 D3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0
bus
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Register D Register C Register B Register A
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• The transfer of information from a bus into one of • A three-state gate is a digital circuit that exhibits three states.
many destination registers can be accomplished by Two of the states are signals equivalent to logic 1 and 0 as in a
conventional gate.
connecting the bus lines to the inputs of all
• The third state is called high impedance state
destination registers and activating the load control of
• The high impedance state behaves like an open circuit which
the particular destination register selected. means that the output is disconnected and does not have a logic
• The symbolic statement for a bus transfer may significance.
mention the bus or its presence may be implied in the
statement. When bus is included in the statement we
write:
Output Y=A if C=1
BUS C, R1 BUS (however it is R1 C) Normal Input A
High-impedance if C=0
Control Input C
Bus and Memory Transfers: Three-State Bus Buffers cont. Connecting registers with 3-state buffers
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• External circuitry enables at most one of the tri-state buffers to pass its
data through to the inputs of the registers. The data is made available • Depending on whether the bus is to be mentioned explicitly or
to all registers, but only one actually loads the data. The load signals not, register transfer can be indicated as either
for the four registers are exactly the same as in the previous example.
This makes sense since the registers only know that they are to read in
data from the bus. They don’t care how the data got onto the bus in the R2 ← R1
first place. or
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UNIT - I
• Memory read : Transfer from memory • To read a value from a location in memory and load it into a
register, the register transfer language notation looks like this:
• Memory write : Transfer to memory
• Data being read or wrote is called a memory word R1 ← M[MAR]
(called M) • This causes the following to occur
• It is necessary to specify the address of M when writing – The contents of the MAR get sent to the memory address lines
/reading memory – A Read (= 1) gets sent to the memory unit
• This is done by enclosing the address in square brackets – The contents of the specified address are put on the memory’s
output data lines
following the letter M – These get sent over the bus to be loaded into register R1
• Example: M[0016] : the memory contents at address
0x0016
R1 R1
100 66
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• The binary adder is constructed with full-adder circuits • Operations can be combined into one common circuit by including an
connected in cascade, with the output carry from one full-adder EXOR gate with each full adder. If M=0 B⊕0=B adds, If M=1 B⊕1=B’
connected to the input carry of the next full-adder and C0=1 subtracts
• n-bit binary adder requires n full adders
B3 A3 B2 A2 B1 A1 B0 A0
M
B3 A3 B2 A2 B1 A1 B0 A0
C3 C2 C1 C0
Full adder Full adder Full adder Full adder C3 C2 C1 C0
Full adder Full adder Full adder Full adder
C4 S3 S2 S1 S0
C4 S3 S2 S1 S0
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C3 1, if overflow
V= C4 S3 S2 S1 S0
C4 0, if no overflow
• Binary Incrementer can also be implemented using a
Overflow detector for signed numbers counter
• A binary decrementer can be implemented by adding
1111 to the desired register each time!
Arithmetic Microoperations
M
• By controlling the data inputs of the adder, it is
possible to obtain different types of arithmetic
operations
C3 C2 C1 C0
FA FA FA FA
• This circuit performs seven distinct arithmetic
C4 S3 S2 S1 S0 operations and the basic component of it is the
Binary Incrementer A3 A2 A1 A0 1 parallel adder
x y x y x y x y
• The output of the binary adder is calculated from the
C
HA
S C
HA
S C
HA
S C
HA
S
following arithmetic sum:
• D = A + Y + Cin
C4 S3 S2 S1 S0
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UNIT - I
Logic Microoperations
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OR Microoperation
AND Microoperation
• Symbol: ∨, +
• Gate: • Symbol: ∧
• Gate:
• Example: 1001102 ∨ 10101102 = 11101102
OR OR
• Example: 1001102 ∧ 10101102 = 00001102
P+Q: R1←R2+R3, R4←R5 ∨R6
ADD
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UNIT - I
THE FOUR BASIC MICROOPERATIONS cont. THE FOUR BASIC MICROOPERATIONS cont.
− • Symbol: ⊕
• Symbol:
• Gate:
• Gate:
NOR Microoperation
NAND Microoperation
• Symbols: ∧ and
−
• Symbols: ∨ and
−
• Gate:
• Gate:
• Example: 1001102 ∧ 10101102 = 11110012
• Example: 1001102 ∨ 10101102 = 00010012
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UNIT - I
Set (Preset) Microoperation • Sets to 1 the bits in register A where there are
• Force all bits into 1’s by ORing them with a value in corresponding 1’s in register B
which all its bits are being assigned to logic-1 • It does not affect bit positions that have 0’s in B
• Example: 1001102 ∨ 1111112 = 1111112 • OR microoperation can be used to implement
Clear (Reset) Microoperation
• Force all bits into 0’s by ANDing them with a value in A 1010 (Register)
which all its bits are being assigned to logic-0 B 1100 (Logic operand)
• Example: 1001102 ∧ 0000002 = 0000002 --------------------
A 1110 (Result)
• Complements bits in A where there are • Clears to 0 the bits in register A only where there are
corresponding 1’s in B corresponding 1’s in register B
• It does not affect bit positions that have 0’s in B • It does not affect bit positions that have 0’s in B
• EXOR microoperation can be used to implement • AND microoperation can be used to implement
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Logic Microoperations
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Logic Microoperations
**Note that the bit ri is the bit at position (i) of the register
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• In a logical shift the serial input to the shift is a 0. • In a circular shift the serial input is the bit that is shifted out of the
other end of the register.
Shift Microoperations
Vs = Rn-1 ⊕ Rn-2
• A right arithmetic shift operation:
sign
bit
Rn-1 1 overflow
• A left arithmetic shift operation: Vs =
Rn-2 0 no overflow
0
sign
bit
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UNIT - I
Shift Microoperations
Before the shift, if the leftmost two – Arithmetic shift right twice : R1 = 11110011
V bits differ, the shift will result in an
overflow
– Arithmetic shift left once : R1 = 10011100
– Arithmetic shift left twice : R1 = 00111000
• In a RTL, the following notation is used
– ashl for an arithmetic shift left – Logical shift right once : R1 = 01100111
– ashr for an arithmetic shift right
– Examples:
• R2 ← ashr R2 – Logical shift left once : R1 = 10011100
• R3 ← ashl R3
– Circular shift right once : R1 = 01100111
– Circular shift left once : R1 = 10011101
Shift Microoperations
A3
common operational unit called an
S
0
1
MUX H2 Arithmetic Logic Unit (ALU)
S
MUX H3
0
1
Serial
input (IL)
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UNIT - I
Shift Microoperations
Arithmetic D i
Circuit
Select
Ci+1
0 4x1 Fi
1 MUX
2
Bi
Logic
Circuit
Ei
3
BUSES
Ai
Ai-1 shr
Ai+1 shl
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• Strip connectors on
• Parallel lines on circuit mother boards (PC104)
boards (ISA or PCI) • External cabling (USB or
• Ribbon cables (IDE) Firewire)
Buses – Structure
Buses – Common Characteristics
• Multiple devices communicating over a single set of • Serial versus parallel
wires • Around 50-100 lines although it's possible
• Only one device can talk at a time or the message to have as few as 3 or 4
is garbled • Lines can be classified into one of four
• Each line or wire of a bus can at any one time groups
contain a single binary digit. Over time, however, a – Data lines
sequence of binary digits may be transferred – Address Lines
• These lines may and often do send information in – Control Lines
parallel – Power
• A computer system may contain a number of
different buses
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UNIT - I
134
Buses – Structure (continued) Data Bus
• Bus lines (parallel) • Carries data
– Data – Remember that there is no difference between
– Address “data” and “instruction” at this level
– Control
– Power
• Width is a key determinant of performance
• Bus lines (serial) – 8, 16, 32, 64 bit
– Data, address, and control are sequentially sent down
single wire
– There may be additional control lines
– Power
135 136
Address bus Control Bus
• Identify the source or destination of data
• Control and timing information
• e.g. CPU needs to read an instruction – Memory read/write signal
(data) from a given location in memory – I/O read/write signal
• Bus width determines maximum memory – Transfer ACK
capacity of system – Bus Request
– e.g. 8080 has 16 bit address bus giving 64k – Bus Grant
address space – Interrupt request
– Interrupt Acknowledge
– Clock signals
– Reset
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144
Computer Buses Traditional (ISA) - (with cache)
– Some devices that attach to a bus are active
and can initiate bus transfers. They are called
masters.
– Some devices are passive and wait for
requests. They are called slaves.
– Some devices may act as slaves at some
times and masters at others.
– Memory can never be a master device.
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145 146
Elements of Bus Design
High Performance Bus
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• Devices must have certain tolerances to • In asynchronous buses, there is no clock signal.
Instead, they use four-way handshaking to perform a
provide responses to signal stimuli bus transaction. This handshaking is facilitated by two
synchronization signals: master synchronization
• More flexible allowing slower devices to (MSYN) and slave synchronization (SSYN). We can
communicate on same bus with faster summarize the operation as follows:
1. Typically, the master places all the required data to initiate a
devices. bus transaction and asserts the master synchronization signal
MSYN.
• Performance of faster devices, however, is 2. Asserting MSYN indicates that the slave can receive the data
and initiate the necessary actions on its part. When the slave is
limited to speed of bus ready with its reply, it asserts SSYN.
3. The master receives the reply and then removes the MSYN
signal to indicate receipt. For example, in a memory read
transaction, the CPU reads the data supplied by the memory.
4. Finally, in response to the master deasserting MSYN, the slave
removes its own synchronization signal SSYN to terminate the
bus transaction.
• Then it indicates to all devices that it • Then it indicates to all devices that it
has done so by activating the Master- has done so by activating the Master-
ready line. ready line.
• This causes all devices on the bus to • This causes all devices on the bus to
decode the address. decode the address.
• The selected slave performs the • The selected slave performs the
required operation and informs the required operation and informs the
processor it has done so by activating processor it has done so by activating
the Slave-ready line. the Slave-ready line.
• The master waits for Slave-ready to • The master waits for Slave-ready to
become asserted before it removes its become asserted before it removes its
signals from the bus. signals from the bus.
• In the case of a read operation, it also • In the case of a read operation, it also
strobes the data into its input buffer. strobes the data into its input buffer.
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– Arbitration mechanisms can be centralized or • In dynamic bus arbitration, bus allocation is done in response to a request
decentralized. from a bus master. To implement dynamic arbitration, each master should
have a bus request and grant lines. A bus master uses the bus request line
to let others know that it needs the bus to perform a bus transaction. Before
it can initiate the bus transaction, it should receive permission to use the
bus via the bus grant line. Dynamic arbitration consists of bus allocation and
release policies.
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Bus Arbitration
Centralized Vs Decentralized Arbitration
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• The bus grant signals are chained through the masters Each master can
pass the incoming bus grant signal to its neighbor in the chain if it does not
want to use the bus.
• If a master wants to use the bus, it grabs the bus grant signal and will not
pass it on to its neighbor. This master can then use the bus for its bus
transaction.
• Daisy chaining is simple to implement and requires only three control lines
independent of the number of hosts.
• Disadvantages
– It implements a fixed priority policy
– The bus arbitration time varies and is proportional to the number of masters
– This scheme is not fault tolerant
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• When a master wants the bus, it sends its request through its own bus
request line. Once the arbiter receives the bus requests from the masters, it
uses the allocation policy to determine which master should get the bus
next.
• Since the bus requests are received on separate lines, the arbiter can
implement a variety of allocation policies: a rotating priority policy, a fair
policy, or even a hybrid policy.
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173
Data Transfer Types Problem 4.1
Show the Block Diagram of the H/w that
implements the following register
transfer statement
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S1
S0
4X1 4X1 4X1 4X1
(R1R3) D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0
R2
P : R1
D3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0
R3
P’Q : R1 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Register D Register C Register B Register A
D3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Register D Register C Register B Register A
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Solution
a) 4 Selection lines to select one of the 16 registers
b) 16 x 1 Multiplexers
c) 32 Multiplexers, one for each bit of the registers.
a) R2 M[AR]
The following transfer statements specify – This statement would transfer the contents of Memory
word that has the address specified by AR into R2
a memory. Explain the memory register.
operation in each case? b) M[AR] R3
a) R2 M[AR] – WRITE the value in register R3 into the Memory Word
that has the address specified in AR.
b) M[AR] R3 M[R5]
c) R5
– It will firstly READ the Memory Word specified by R5
c) R5 M[R5] and then transfer the value into the same register R5,
this is mostly used in Indirect Addressing.
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xyT0 + T1 + y’T2 : AR AR + 1
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x: R1 R1 + R2
x’y : R1 R1 + 1
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A 0 0111 0110
values of S3, S2, S1, S0 AND C4 for the B 0 1000 1001 C3 C2 C1 C0
C 1 1100 1000
C4 S3 S2 S1 S0
0 0111 0110
A E 1 0000 0001
B 0 1000 1001 B3 A3 B2 A2 B1 A1 B0 A0
C 1 1100 1000
D 1 0101 1010
C3 C2 C1 C0
FA FA FA FA
E 1 0000 0001
C4 S3 S2 S1 S0
4-bit adder-subtractor
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• An 8-bit register holds the value 10011100. What is the register Starting from an initial value of R=11011101, determine the
value after an arithmetic shift right? Starting from the initial no. sequence of binary values in R after a logical shift left, followed
10011100 determine the register value after an arithmetic shift by a circular shift right followed by a logical shift right and a
left, and state whether there is an overflow. circular shift left.
A3 2. yT: R1 R2, R1 R3
= 1 and IL = 0? S
0 MUX
1
H2
S
H3
0 MUX
1
Serial
input (IL)
3. zT: PC AR, PC PC + 1
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Floating-Point
• What can be represented in N bits?
FLOATING POINT –Example(8-bits)
• Unsigned
0 to 2N
0 t0 255
• 2’s Complement
- 2N-1 to 2N-1 - 1
- 2N-1+1 to 2N-1 -1
-127 t0 127
• BCD:
0N/4 to 10 – 1
0 t0 9
Floating-Point Floating-Point
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4. Zero. 5. +ve
3. -ve
5. Small positive numbers with magnitudes less than 0.100 × 10−99. Underflow Underflow
6. Positive numbers between 0.100×10−99 and 0.999 × 1099.
7. Large positive numbers greater than 0.999 × 1099.
-∞ 0 ∞
+∞
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Relative Error
Effects of Changes in the System
• The “space” between adjacent expressible numbers in regions 2
and 6 is not constant. • Changing the number of digits in the fraction or exponent shifts the
boundaries of regions 2 and 6 and changes the number of
expressible points in them.
• The separation between +0.998 × 1099 and +0.999×1099 is very
different than that between +0.998 × 100 and +0.999 × 100
• Increasing the number of digits in the fraction increases the
density of points and therefore improves the accuracy of
• However, when separation between a number and its successor is approximations.
expressed as a percentage of that number, there is no systematic
variation throughout region 2 or 6.
• Increasing the number of digits in the exponent increases the size
of regions 2 and 6 by shrinking regions 1, 3, 5, and 7.
• The relative error introduced by rounding is approximately the
same for small numbers as large numbers.
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Floating Point Number Representation Single Precision Floating Point (FP) Numbers
Exponent Mantissa • where s is the sign of the number, e represents the biased
exponent (8 bits) and m represents the mantissa or significand (23
Sign Value Sign Value
bits)
0 100 0 1001111
• 32-bit values range in magnitude from 10-38 to 1038.
31 30 . . . 20 19 ... 0
s exponent Significand (Mantissa/Fraction)
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(-1)s x (1 + Fraction) x 2E 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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si g n exponent f r a c t io n
s ê f1f2 . . . f52
0 1 11 12 63
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UNIT - I
Floating-Point Addition
• Example: 0.5 + -0.4375
1. Binary normalized versions of the two numbers
• 0.5 = 1.000 x 2–1
• -0.4375 = -1.110 x 2–2
2. Shift the number with less exponent right until its exponent
matches the larger number
• -1.110 x 2–2 = -0.111 x 2–1
3. Add the significands
• (1.000 x 2–1) + (-0.111 x 2–1) = -0.001 x 2–1
4. Normalize the sum
• -0.001 x 2–1 = -1.000 x 2–4
• Biased exponent = (-4 + 127) = 123
5. Round the sum if needed
• Number is already fits in the given bits
6. Result in decimal
• -1.000 x 2–4 = 0.0625
© MANISH MAHAJAN