* SPICE export by: SEDIT 13.

00
* Export time: Thu Mar 31 15:58:05 2011
* Design: adderfull
* Cell: adderfull
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: D:\ece3b345\adderfull
* Exclude global pins: no
* Control property name: SPICE

********* Simulation Settings - General section *********

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

MNMOS_3 Cobar Ci N_4 Gnd NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_4 N_4 B Gnd Gnd NH W=0.45u L=0.15u AS=0.3375p PS=2.4u AD=0.3375p
PD=2.4u
MNMOS_5 N_4 A Gnd Gnd NH W=0.45u L=0.15u AS=0.3375p PS=2.4u AD=0.3375p
PD=2.4u
MNMOS_6 Co Cobar Gnd N_5 NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_7 Sbar A N_10 N_9 NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_8 N_10 B N_12 N_11 NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_9 N_12 Ci Gnd N_13 NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_10 N_16 Cobar Gnd N_15 NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_11 Sbar A N_16 N_17 NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_12 Sbar B N_16 N_18 NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_13 Sbar Ci N_16 N_19 NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_14 S Sbar Gnd N_20 NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_1 Cobar A N_3 Gnd NH W=0.45u L=0.15u AS=0.3375p PS=2.4u
AD=0.3375p PD=2.4u
MNMOS_2 N_3 B Gnd Gnd NH W=0.45u L=0.15u AS=0.3375p PS=2.4u AD=0.3375p
PD=2.4u
MPMOS_10 N_8 A N_7 N_7 PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_11 S Sbar Vdd N_21 PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_14 N_14 B N_8 N_7 PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_15 Sbar Ci N_14 N_7 PH W=0.9u L=0.15u AS=0.6750p PS=3.3u
AD=0.6750p PD=3.3u
MPMOS_16 Sbar Cobar N_7 N_7 PH W=0.9u L=0.15u AS=0.6750p PS=3.3u
AD=0.6750p PD=3.3u
MPMOS_1 N_1 A Vdd Vdd PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_2 N_2 A N_1 N_1 PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_3 N_1 B Vdd Vdd PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_4 Cobar Ci N_1 N_1 PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_5 Cobar B N_2 N_1 PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_6 Co Cobar Vdd N_6 PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_7 N_7 A Vdd Vdd PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_8 N_7 B Vdd Vdd PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
MPMOS_9 N_7 Ci Vdd Vdd PH W=0.9u L=0.15u AS=0.6750p PS=3.3u AD=0.6750p
PD=3.3u
VVoltageSource_1 A Gnd BIT({0101} pw=50n on=1 off=0 rt=0.1n ft=0.1n delay=0
ht=50n lt=50n)
VVoltageSource_2 B Gnd BIT({1010} pw=50n on=1 off=0 rt=0.1n ft=0.1n delay=0
ht=50n lt=50n)
VVoltageSource_3 Ci Gnd BIT({0011} pw=50n on=1 off=0 rt=0.1n ft=0.1n delay=0
ht=50n lt=50n)
.include"C:\Documents and Settings\VLSI9\Desktop\dual.md"
Vdd Vdd Gnd 1
.tran .1n 200n
.print A B Ci Co Cobar S Sbar

********* Simulation Settings - Analysis section *********

********* Simulation Settings - Additional SPICE commands *********

.end

* T-Spice 13.00 Simulation Thu Mar 31 16:02:33 2011

C:\DOCUME~1\VLSI9\LOCALS~1\Temp\adderfull.sp
* Command line: tspice -o C:\DOCUME~1\VLSI9\LOCALS~1\Temp\adderfull.out
C:\DOCUME~1\VLSI9\LOCALS~1\Temp\adderfull.sp
* T-Spice Win32 13.00.20080321.01:01:33
* Warning : "dual.md" line 7 Invalid binned model NH
 1.991306e-007 1.0000e+000 0.0000e+000 1.0000e+000 1.0000e+000 2.4164e-006
7.7414e-007 9.9999e-001
1.993306e-007 1.0000e+000 0.0000e+000 1.0000e+000 1.0000e+000 2.4430e-006
7.7534e-007 9.9999e-001
1.995306e-007 1.0000e+000 0.0000e+000 1.0000e+000 1.0000e+000 2.4012e-006
7.7410e-007 9.9999e-001
1.997306e-007 1.0000e+000 0.0000e+000 1.0000e+000 1.0000e+000 2.4267e-006
7.7538e-007 9.9999e-001
1.999306e-007 1.0000e+000 0.0000e+000 1.0000e+000 1.0000e+000 2.3861e-006
7.7407e-007 9.9999e-001
2.000000e-007 1.0000e+000 0.0000e+000 1.0000e+000 1.0000e+000 2.3721e-006
7.7361e-007 9.9999e-001
* Parsing 0.03 seconds
* Setup 0.26 seconds
* DC operating point 0.01 seconds
* Transient Analysis 0.95 seconds
* Overhead 2.85 seconds
* -----------------------------------------
* Total 4.11 seconds

* Simulation completed with 13 Warnings

* End of T-Spice output file