Dell Inspiron N5010-Intel

5 4 3 2 1
D D
Berry DG15 Discrete/UMA Schematics Document

Arrandale
C
Intel PCH C
2010-02-03
REV : A00
B
DY :None Installed B
UMA:UMA platform installed

PARK:DIS PARK platform installed
M96:DIS M96 platform installed
VRAM_1G:VRAM 128M*16 installed
Colay :Manual modify BOM
A <Core Design> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number

Cover Page Rev
A3
Berry A00
Date: W ednesday, February 10, 2010 Sheet 1 of 92
5 4 3 2 1
5 4 3 2 1
##OnMainBoard
Berry Block Diagram INPUTS
CPU DC/DC
ISL62883
OUTPUTS
47
1.Park-XT;512MB
(Discrete/UMA co-lay) +PWR_SRC
SYSTEM DC/DC
+VCC_CORE 39,
VRAM TPS51218 49
(64Mx16b*4)
1GB/512MB
Project code : 91.4HH01.001 INPUTS OUTPUTS
Dell P/N:9TGTN$AA HYNIX 4
D
Dell P/N:C995R$AA SAMSUNG

85,86,87,88
PCB P/N : 48.4HH01.0SA +PWR_SRC +1.05V_VTT
D
4
2.Park-XT;1GB (128Mx16b*4) DDR3 Revision : 09909-1 SYSTEM DC/DC

Dell P/N:PXFYJ$AA HYNIX RT8205B 46
Dell P/N:C09DT$AA SAMSUNG
800MHz Intel CPU INPUTS OUTPUTS
(1 and 2 co-lay) DDRIII 800/1066 Channel A DDRIII Slot 0 +5V_ALW2 4
+3.3V_RTC_LDO
18 +PWR_SRC +5V_ALW
800/1066
Clock Generator AMD Graphic PCIe x 16
Arrandale +3.3V_ALW
+15V_ALW
SLG8SP585
7 Park-XT (Discrete only)
DDRIII 800/1066 Channel B DDRIII Slot 1 SYSTEM DC/DC
19 50
(Discrete only) 800/1066 TPS51116
INPUTS OUTPUTS
+1.5V_SUS 4
80,81,82,83,84 8,9,10,11,12,13,14 +PWR_SRC +0.75V_DDR_VTT
+V_DDR_REF
PCIE x 1 Mini-Card
USB x 1 802.11a/b/g SYSTEM DC/DC
FDIx4x2 TPS51611 53
C
Discreet/UMA Co-lay (UMA only) DMIx4 INPUTS OUTPUTS C
PCIE x 1 10/100 NIC RJ45 +PWR_SRC +CPU_GFX_CORE

4
Realtek CONN
HDMI Level 57 RTL8103T-VB
VGA
HDMI shifter 89
57 RT8208B
Intel
I/O Board
Connector
SATAx1 / USB2.0x1
INPUTS OUTPUTS
LVDS(Dual Channel) ESATA/USB
LCD PCIE x 3 +PWR_SRC +VGA_CORE
54
PCH HM57 Combo
RGB CRT TI CHARGER 5
BQ24745 45
PCIE x 1,USB x 1 Mini-Card
14 USB 2.0/1.1 ports SATA x 1 INPUTS OUTPUTS
CRT SIM
ETHERNET (10/100/1000Mb) WWAN +DC_IN +PWR_SRC
+PBATT
CRT Board High Definition Audio 26
Left Side: 77 SATA ports (6) USB 2.0 x 4 SYSTEM DC/DC
USB 2.0 x 1 51 4
USB x 2 PCIE ports (8)
Right Side: APL5930
76 USB x 1
INPUTS OUTPUTS
Bluetooth USB2.0 x 4 LPC I/F
73 +3.3V_ALW +1.8V_RUN
B ACPI 1.1 +1.8V_RUN_VGA B
PCI/PCI BRIDGE SYSTEM DC/DC

CAMERA CardReader SD/MMC+/MS/ APL5930 90
3
54 USB 2.0 x 1
20,21,22,23,24,25,26,27,28 Realtek 78
MS Pro/xD INPUTS
26 OUTPUTS
AZALIA RTS5159 +1.5V_SUS +1.0V_RUN_VGA
Switches
INPUTS OUTPUTS
SPI
SATA x 2 HDD +1.5V_SUS +1.5V_RUN

Azalia
LPC Bus
Internal Analog MIC +5V_ALW +5V_RUN

59 +3.3V_ALW +3.3V_RUN
CODEC
HP1
IDT
Flash ROM LPC debug port ODD PCB LAYER
70 59 L1:Top
4MB 62
92HD79B1 L2:VCC
MIC IN 30 L3:Signal
KBC L4:Signal
SPI SMBus L5:GND
NUVOTON L6:Bottom
A <Core Design> A
NPCE781BA0DX 37
2CH SPEAKER Wistron Corporation
Title
Thermal Block Diagram
Flash ROM Touch Int. Main:G7922 Fan Size Document Number Rev
256kB 62 PAD KB Sec.EMC2102 58 A3
68 68 2539 Berry A00
5 4 3 2 1
5 4 3 2 1
+1.0V_RUN_VGA APL5930KAI
RT8208B +VGA_CORE For Discrete
D D
+PWR_SRC TPS51116
Adapter
ISL62883 TPS51218 TPS51611

AO4407A +V_DDR_REF +0.75V_DDR_VTT +1.5V_SUS
Charger
BQ24745 +VCC_CORE +1.05V_VTT +CPU_GFX_CORE
For UMA
AO4468
Battery +PBATT
RT8205B +1.5V_RUN
For Discrete
C +1.5V_RUN_CPU C
+3.3V_RTC_LDO
+3.3V_ALW
+15V_ALW +5V_ALW2 +5V_ALW
UP7534BRA8 AO4468 UP7534BRA8 AO4468 PA102FMG

SI2301CDS APL5930KAI
+5V_USB1 +5V_RUN +5V_USB2 +3.3V_RUN +3.3V_RUN_VGA +3.3V_LAN

+KBC_PWR +1.8V_RUN
For Discrete
I/O Board USB Power CRT Board USB Power
RT9198-33PBG
APL5930KAI SI3456BD RTS5159 RTL8103T-VB
B B
+3.3V_CRT_LDO
+1.8V_RUN_VGA +LCDVDD +3.3V_RUN_CARD +1.2V_LOM
For Discrete
Power Shape
Regulator LDO Switch

A <Core Design> A
Wistron Corporation
Title
Size
Power Block Diagram
Document Number Rev
A3
Berry A00
5 4 3 2 1
A B C D E
PCH SMBus Block Diagram +3.3V_ALW +3.3V_RUN KBC SMBus Block Diagram
‧ ‧ +5V_RUN
+3.3V_RUN ‧
SRN2K2J-1-GP
‧ SRN2K2J-1-GP
DIMM 1
‧ ‧
SRN10KJ-5-GP
‧ ‧
SMBCLK PCH_SMB_CLK PCH_SMBCLK
TouchPad Conn.
‧
SCL
1 SMBDATA PCH_SMB_DATA PCH_SMBDATA 1
‧
SDA PSDAT1 TPDATA TPDATA TPDATA
+3.3V_ALW
PSCLK1 TPCLK TPCLK TPCLK
SMBus Address:A0
‧ 2N7002SPT
+KBC_PWR
‧
SRN2K2J-8-GP
SML1CLK KBC_SCL1
SRN4K7J-8-GP
To KBC DIMM 2
‧
SML1DATA KBC_SDA1
2N7002DW-1-GP
Battery Conn.
‧
PCH_SMBCLK
+3.3V_ALW SCL SRN100J-3-GP
‧
SML0CLK SML0_CLK PCH_SMBDATA SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB
SDA
SML0DATA SML0_DATA SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB SMBus address:16
SMBus Address:A4
SRN2K2J-1-GP
+3.3V_RUN Clock BQ24745
‧ XDP ‧ Generator KBC SCL
‧
PCH_SMBCLK
SCLK SDA SMBus address:12
PCH SRN2K2J-1-GP
PCH_SMBDATA
SDATA NPCE781BA0DX
UMA SMBus address:D2 +3.3V_RUN
2
SDVO_CTRLCLK PCH_HDMI_CLK Level PCH_HDMI_CLK
Minicard
‧ 2
SDVO_CTRLDATA PCH_HDMI_DATA
Shift PCH_HDMI_DATA
+3.3V_RUN
UMA
‧ WLAN ‧ SRN4K7J-8-GP
‧
PCH_SMBCLK
+3.3V_RUN
SMB_CLK
Thermal
‧
PCH_SMBDATA
SMB_DATA
‧ ‧
THERM_SCL
THERM_SDA
SCL
SDA
SMBus address:7A
SRN2K2J-1-GP Minicard GPIO73/SCL2 KBC_SCL1

2N7002DW-1-GP
UMA SRN0J-6-GP
PCH_SMBCLK
W-WAN
SMB_CLK
GPIO74/SDA2 KBC_SDA1
L_DDC_CLK LDDC_CLK_PCH
PCH_SMBDATA
SMB_DATA
L_DDC_DATA LDDC_DATA_PCH
UMA
+3.3V_RUN_VGA
CRT_DDC_CLK PCH_CRT_DDCCLK
CRT_DDC_DATA PCH_CRT_DDCDATA
‧
SRN2K2J-1-GP
DIS
3 DDC1CLK 3
DDC1DATA LCD CONN

SRN0J-6-GP
DDC2CLK VGA_CRT_DDCCLK
DDC2DATA VGA_CRT_DDCDATA
+3.3V_RUN DIS +5V_RUN
VGA ‧ ‧
+3.3V_RUN
SRN0J-6-GP
UMA SRN2K2J-1-GP
UMA
‧ SRN2K2J-1-GP
CRT_DDCCLK_CON
CRT_DDCDATA_CON
CRT CONN
+3.3V_RUN_VGA +5V_RUN
UMA
‧ ‧ 2N7002DW-1-GP
+5V_RUN SRN2K2J-1-GP
SRN2K2J-1-GP
4 4
DIS
IFPC_AUX_I2CW_SCL GPU_HDMI_CLK
TSCBTD3305CPWR
IFPC_AUX_I2C_SDA# GPU_HDMI_DATA
HDMI CONN <Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
SMBUS Block Diagram

Size Document Number Rev
A2 Berry A00
Date: Wednesday, February 10, 2010 Sheet 4 of 92
A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
SPKR_PORT_D_L-
SPKR_PORT_D_R+ SPEAKER
Codec
DP1 EMC2102_DP1
92HD79B1
SC470P50V3JN-2GP
MMBT3904-3-GP HP1_PORT_B_L HP
HP1_PORT_B_R
2
DN1 EMC2102_DN1
OUT 2
Place near CPU

Thermal PWM CORE
G7922R61U
DP2 THRMDA
VGA_THERMDA
VGA HP0_PORT_A_L MIC
DN2 THRMDC HP0_PORT_A_R
VGA_THERMDC VREFOUT_A_OR_F IN
Place near GPU(DISCRETE only).
MMBT3904-3-GP
3 3
DMIC_CLK/GPIO1
System Sensor(UMA only) DMIC0/GPIO2
DP3 EMC2102_DP3
MMBT3904-3-GP
SC470P50V3JN-2GP
DN3 EMC2102_DN3
PORTC_L
Put under CPU(T8 HW shutdown) Analog
PORTC_R
VREFOUT_C MIC
4 4
<Core Design>
Wistron Corporation
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
Berry A00
A B C D E
A B C D E
PCH Strapping Processor Strapping

Calpella Schematic Checklist Rev.0_7 Calpella Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ Embedded DisplayPort.
DisplayPort
4 - 10-kΩ weak pull-up resistor.
Presence 0: Enabled - An external Display Port device is
4
INIT3_3V# Weak internal pull-down. Do not pull high. connected to the Embedded Display Port.
GNT3#/ Default Mode: Internal pull-up. CFG[3] PCI-Express Static 1: Normal Operation. 1
GPIO55 Low (0) = Top Block Swap Mode (Connect to ground with 4.7-kΩ weak Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
pull-down resistor).
CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
INTVRMEN High (1) = Integrated VRM is enabled Configuration 0: Bifurcation enabled
Low (0) = Integrated VRM is disabled Select
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1#/GPIO51 required. CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0
Temporarily used Connect to GND with 3.01K Ohm/5% resistor
Boot from PCI: Connect GNT1# to ground with 1-kΩ pull-down
resistor. Leave GNT0# Floating. for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-kΩ samples. MoW and sighting report].
pull-down resistor. For a common motherboard design (for AUB and CFD),
GNT2#/ Default - Internal pull-up. the pull-down resistor should be used. Does not
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers impact AUB functionality.
only. Not for mobile/desktops).
GPIO33 Default: Do not pull low.

Disable ME in Manufacturing Mode: Connect to ground with 1-kΩ
pull-down resistor.
3 3
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-kΩ weak pull-up resistor.
Disable iTPM: Left floating, no pull-down required.
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-kΩ weak pull-up
resistor.
Disable Danbury: Connect to ground with 4.7-kΩ weak pull-down
resistor.
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.
/GPIO[33] High (1) : Flash Descriptor Security will be in effect.
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC Weak internal pull-down. Do not pull high.
GPIO15 Weak internal pull-down. Do not pull high.
GPIO8 Weak internal pull-up. Do not pull low.
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
2 2
PCIE Routing USB Table SATA Table

USB SATA
Pair Device Pair Device
LANE1 RESERVED 0 USB2 (CRT Board)
0 HDD
LANE2 MiniCard WLAN 1 USB3 (CRT Board)
1 ODD
2 WLAN (I/O Board)
LANE3 LAN 2 HM55 no support
3 RESERVED
3 HM55 no support
LANE4 W-WAN 4 CARD READER
4 ESATA
5 BLUETOOTH
LANE5 RESERVED 5 RESERVED
6 HM55 no support
LANE6 RESERVED 7 HM55 no support
8 USB1 (I/O Board)
1 LANE7 H55/HM55 no support
<Core Design>
1
9 USB0 (I/O Board ESATA)
LANE8 H55/HM55 no support 10 RESERVED Wistron Corporation
11 W-WAN (I/O Board) Taipei Hsien 221, Taiwan, R.O.C.
12 RESERVED Title
13 CAMERA
Table of Content Rev
A3
Berry A00
5 4 3 2 1
SSID = CLOCK
+3.3V_RUN
X02-20091222
+3.3V_RUN_SL585 +1.05V_VTT X02-20091222
D D
R701 +1.05V_RUN_SL585_IO
1 2 R702
0R0603-PAD 1 2
0R0603-PAD
1
1
C702 C708 C709 C710 C711
SC1U6D3V2KX-GP
DY C701 C703 C704 C705 C706 C707 DY
DY
SC1U6D3V2KX-GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
x01 change tolerant 20091117 x01 change tolerant 20091117
+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO
+3.3V_RUN
R703
1 2 CPU_STOP#
C 2K2R2J-2-GP C
24
17
29
15
18
1
5
U701
VDD_27
VDD_SRC_IO
VDD_CPU_IO
VDD_CPU
VDD_SRC
VDD_REF
VDD_DOT
X01-20091116
X02-20091222 DIS
4 6 CLK_VGA_27M_NSS_R 1 2 CLK_VGA_27M_NSS 82
23 CLK_DREF# DOT_96# 27MHZ CLK_VGA_27M_SS_R R708 1
3 DOT_96 27MHZ_SS 7 2 33R2J-2-GP CLK_VGA_27M_SS 82
RN702 23 CLK_DREF R709 33R2J-2-GP
DY
1
23 CLKIN_DMI# 2 3 CLKIN_DMI#_C 14
CLKIN_DMI_C SRC_2# CPU_STOP# EC701 EC702
23 CLKIN_DMI 1 4
0R4P2R-PAD
13 SRC_2 CPU_STOP# 16
25 CK_PW RGD R704 DY SC4D7P50V2CN-1GP DY SC4D7P50V2CN-1GP
2
CKPWRGD/PD#
23 CLK_PCIE_SATA# 2 RN703 3 CLK_PCIE_SATA#_C 11 SRC_1/SATA# REF_0/CPU_SEL 30 FSC 2 1 CLK_PCH_14M 23
RN
23 CLK_PCIE_SATA 1 4 CLK_PCIE_SATA_C 10 SRC_1/SATA

33R2J-2-GP
0R4P2R-PAD
1
CLK_XTAL_IN
23 CLK_CPU_BCLK# 22 CPU_0# XTAL_IN 28
DY
RN
23 CLK_CPU_BCLK 23 27 CLK_XTAL_OUT EC703

CPU_0 XTAL_OUT
2
19 31 SC4D7P50V2CN-1GP
CPU_1# SDA
20 CPU_1 SCL 32
VSS_SATA
VSS_CPU
VSS_SRC
VSS_DOT
VSS_REF
VSS_27
PCH_SMBDATA 18,19,23,76 +3.3V_RUN_SL585
GND
PCH_SMBCLK 18,19,23,76
2
B SLG8SP585VTR-GP B
33
26
21
12
R705
10KR2J-3-GP
1
CK_PW RGD
+1.05V_VTT
FSC 0 1
D
2
. Q701
133MHz X701 R706 2N7002E-1-GP
SPEED 100MHz CLK_XTAL_IN 1 2 CLK_XTAL_OUT
DY 4K7R2J-2-GP .
.
(Default) . .
X-14D31818M-37GP
1
1
82.30005.901
S
C712 C713
SC12P50V2JN-3GP SC12P50V2JN-3GP FSC
2
47 VR_CLKEN#
2
R707
10KR2J-3-GP
1
A <Core Design> A
Wistron Corporation
Title
Clock Generator SLG8SP585

Berry A00
Date: Monday, March 29, 2010 Sheet 7 of 92
5 4 3 2 1
5 4 3 2 1
SSID = CPU
D D
CPU1A 1 OF 9
PEG_ICOMPI B26 PEG_IRCOMP_R R801 1 2 49D9R2F-GP
A26 R802 1 2 750R2F-GP
PEG_ICOMPO
22 DMI_PTX_CRXN0 A24 DMI_RX#0 PEG_RCOMPO B27
22 DMI_PTX_CRXN1 C23 A25 EXP_RBIAS
DMI_RX#1 PEG_RBIAS PEG_RXN[0..15]
22 DMI_PTX_CRXN2 B22 DMI_RX#2 PEG_RXN[0..15] 80
A21 K35 PEG_RXN15
CLARKSFIELD
22 DMI_PTX_CRXN3 DMI_RX#3 PEG_RX#0
J34 PEG_RXN14
PEG_RX#1 PEG_RXN13
22 DMI_PTX_CRXP0 B24 DMI_RX0 PEG_RX#2 J33
22 DMI_PTX_CRXP1 D23 G35 PEG_RXN12
DMI_RX1 PEG_RX#3
DMI
22 DMI_PTX_CRXP2 B23 G32 PEG_RXN11
DMI_RX2 PEG_RX#4 PEG_RXN10
22 DMI_PTX_CRXP3 A22 DMI_RX3 PEG_RX#5 F34
F31 PEG_RXN9
PEG_RX#6 PEG_RXN8
22 DMI_CTX_PRXN0 D24 DMI_TX#0 PEG_RX#7 D35
22 DMI_CTX_PRXN1 G24 E33 PEG_RXN7
DMI_TX#1 PEG_RX#8 PEG_RXN6
22 DMI_CTX_PRXN2 F23 DMI_TX#2 PEG_RX#9 C33
22 DMI_CTX_PRXN3 H23 D32 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN4
PEG_RX#11 B32
22 DMI_CTX_PRXP0 D25 C31 PEG_RXN3
DMI_TX0 PEG_RX#12 PEG_RXN2
22 DMI_CTX_PRXP1 F24 DMI_TX1 PEG_RX#13 B28
22 DMI_CTX_PRXP2 E23 B30 PEG_RXN1
DMI_TX2 PEG_RX#14 PEG_RXN0
22 DMI_CTX_PRXP3 G23 DMI_TX3 PEG_RX#15 A31
PEG_RXP[0..15]
PEG_RXP[0..15] 80
J35 PEG_RXP15
PEG_RX0 PEG_RXP14
PEG_RX1 H34
C 22 FDI_TXN0 E22
PEG_RX2 H33
F35
PEG_RXP13
PEG_RXP12 C
FDI_TX#0 PEG_RX3 PEG_RXP11
22 FDI_TXN1 D21 FDI_TX#1 PEG_RX4 G33
22 FDI_TXN2 D19 E34 PEG_RXP10
22 FDI_TXN3 D18 FDI_TX#3 PEG_RX6 F32
22 FDI_TXN4 G21 D34 PEG_RXP8
22 FDI_TXN5 E19 FDI_TX#5 PEG_RX8 F33
22 FDI_TXN6 F21 B33 PEG_RXP6
FDI_TX#6 PEG_RX9
Intel(R) FDI
22 FDI_TXN7 G18 D31 PEG_RXP5
PEG_RX11 A32
PCI EXPRESS -- GRAPHICS

C30 PEG_RXP3
PEG_RX12 PEG_RXP2
22 FDI_TXP0 D22 FDI_TX0 PEG_RX13 A28
22 FDI_TXP1 C21 B29 PEG_RXP1
FDI_TX1 PEG_RX14 PEG_RXP0 PEG_TXN[0..15]
22 FDI_TXP2 D20 FDI_TX2 PEG_RX15 A30 PEG_TXN[0..15] 80
22 FDI_TXP3 C18 FDI_TX3
22 FDI_TXP4 G22 L33 PEG_C_TXN15 C816 1DIS 2 SCD1U10V2KX-5GP PEG_TXN15
FDI_TX4 PEG_TX#0 PEG_C_TXN14 C815 SCD1U10V2KX-5GP PEG_TXN14
22 FDI_TXP5 E20 FDI_TX5 PEG_TX#1 M35 1DIS 2
22 FDI_TXP6 F20 M33 PEG_C_TXN13 C814 1DIS 2 SCD1U10V2KX-5GP PEG_TXN13
FDI_TX6 PEG_TX#2 PEG_C_TXN12 C813 SCD1U10V2KX-5GP PEG_TXN12
22 FDI_TXP7 G19 FDI_TX7 PEG_TX#3 M30 1DIS 2
L31 PEG_C_TXN11 C812 1DIS 2 SCD1U10V2KX-5GP PEG_TXN11
PEG_TX#4 PEG_C_TXN10 C811 SCD1U10V2KX-5GP PEG_TXN10
22 FDI_FSYNC0 F17 FDI_FSYNC0 PEG_TX#5 K32 1DIS 2
E17 M29 PEG_C_TXN9 C810 1DIS 2 SCD1U10V2KX-5GP PEG_TXN9
22 FDI_FSYNC1 FDI_FSYNC1 PEG_TX#6 PEG_C_TXN8 C809 SCD1U10V2KX-5GP PEG_TXN8
PEG_TX#7 J31 1DIS 2
C17 K29 PEG_C_TXN7 C808 1DIS 2 SCD1U10V2KX-5GP PEG_TXN7
22 FDI_INT FDI_INT PEG_TX#8 PEG_C_TXN6 C807 SCD1U10V2KX-5GP PEG_TXN6
PEG_TX#9 H30 1DIS 2
F18 H29 PEG_C_TXN5 C806 1DIS 2 SCD1U10V2KX-5GP PEG_TXN5
22 FDI_LSYNC0 FDI_LSYNC0 PEG_TX#10 PEG_C_TXN4 C805 SCD1U10V2KX-5GP PEG_TXN4
22 FDI_LSYNC1 D17 FDI_LSYNC1 PEG_TX#11 F29 1DIS 2
E28 PEG_C_TXN3 C804 1DIS 2 SCD1U10V2KX-5GP PEG_TXN3
PEG_TX#12 PEG_C_TXN2 C803 SCD1U10V2KX-5GP PEG_TXN2
PEG_TX#13 D29 1DIS 2
D27 PEG_C_TXN1 C802 1DIS 2 SCD1U10V2KX-5GP PEG_TXN1
B PEG_TX#14 B
1
8
7
6
5
C26 PEG_C_TXN0 C801 1DIS 2 SCD1U10V2KX-5GP PEG_TXN0

R804 PEG_TX#15 PEG_TXP[0..15]
1KR2J-1-GP PEG_C_TXP15 C832 SCD1U10V2KX-5GP PEG_TXP15 PEG_TXP[0..15] 80
1DIS
DIS
DIS RN801 PEG_TX0 L34
M34 PEG_C_TXP14 C831 1DIS
2
2 SCD1U10V2KX-5GP PEG_TXP14
PEG_TX1 PEG_C_TXP13 C830 SCD1U10V2KX-5GP PEG_TXP13
M32 1DIS 2
2
SRN1KJ-4-GP PEG_TX2 PEG_C_TXP12 C829 SCD1U10V2KX-5GP PEG_TXP12

L30 1DIS 2
1
2
3
4

PEG_TX4 M31 1DIS 2
K31 PEG_C_TXP10 C827 1DIS 2 SCD1U10V2KX-5GP PEG_TXP10
PEG_TX6 M28 1DIS 2
H31 PEG_C_TXP8 C825 1DIS 2 SCD1U10V2KX-5GP PEG_TXP8
PEG_TX8 K28 1DIS 2
G30 PEG_C_TXP6 C823 1DIS 2 SCD1U10V2KX-5GP PEG_TXP6
PEG_TX10 G29 1DIS 2
F28 PEG_C_TXP4 C821 1DIS 2 SCD1U10V2KX-5GP PEG_TXP4
PEG_TX12 E27 1DIS 2
D28 PEG_C_TXP2 C819 1DIS 2 SCD1U10V2KX-5GP PEG_TXP2
PEG_TX14 C27 1DIS 2
C25 PEG_C_TXP0 C817 1DIS 2 SCD1U10V2KX-5GP PEG_TXP0
PEG_TX15
x01 change tolerant 20091117

CLARKUNF
62.10055.341
SEC. 62.10053.561
A <Core Design>
A
Wistron Corporation
Title
CPU (PCIE/DMI/FDI)
Berry A00
5 4
SSID = CPU X02-20091222
3 2 1
Processor Compensation Signals
RN
+1.05V_VTT CPU1B 2 OF 9
Processor Pullups H_COMP3
1 2 AT23
COMP3
R902 20R2F-GP A16 BCLK_CPU_C_P 1 RN901 4 BCLK_CPU_P 25
BCLK
MISC
R901 1 2 49D9R2F-GP H_CATERR# 1 2 H_COMP2 AT24 B16 BCLK_CPU_C_N 2 3
COMP2 BCLK# BCLK_CPU_N 25
R903 20R2F-GP 0R4P2R-PAD S3_RST_GATE# 25
H_COMP1 BCLK_ITP_P
CLOCKS
1 2 G16 AR30
COMP1 BCLK_ITP
RN
R907 1 2 68R2-GP H_PROCHOT# R904 49D9R2F-GP AT30 BCLK_ITP_N +1.5V_SUS
CLARKSFIELD
H_COMP0 BCLK_ITP#
R905
1 2
49D9R2F-GP
AT26
COMP0
E16 CLK_EXP_C_P 1 RN902 4
X01 20091117
CLK_EXP_P 23
1
R906 1 H_CPURST# PEG_CLK CLK_EXP_C_N
2 68R2-GP D16 2 3
DY TPAD14-GP TP901 1 SKTOCC#_R AH24
PEG_CLK# 0R4P2R-PAD
CLK_EXP_N 23
Q901 R908
SKTOCC# 1KR2J-1-GP
A18
DPLL_REF_SSCLK
A17 G
. .
H_CATERR# DPLL_REF_SSCLK#
AK14
2
CATERR#
THERMAL
D DDR3_DRAMRST# 18,19
.
.
.
D F6 SM_DRAMRST# S
D
1
SM_DRAMRST#
25 H_PECI AT15
PECI SM_RCOMP_0 2N7002E-1-GP C903
AL1
SM_RCOMP0 SM_RCOMP_1 SCD1U10V2KX-5GP
AM1 PM_EXTTS#0_C 53
2
SM_RCOMP1 SM_RCOMP_2
AN1
47 H_PROCHOT# AN26
SM_RCOMP2 RN903 +1.05V_VTT 1
DY 2
PROCHOT# PM_EXTTS#0_C R909 0R2J-2-GP
AN15 4 1
PM_EXT_TS#0 PM_EXTTS#1_C
PM_EXT_TS#1
AP15 3 2 x01 change tolerant 20091117
RN
SRN10KJ-5-GP
DDR3
MISC
25,37,42,82 H_THERMTRIP# AK15
THERMTRIP#
XDP_PRDY#
1 4 PM_EXTTS#0 18 DDR3 Compensation Signals
AT28 2 3 PM_EXTTS#1 19
PRDY# XDP_PREQ# RN904 SM_RCOMP_0 R913 1
AP27 2 100R2F-L1-GP-U
PREQ# 0R4P2R-PAD
AN28 XDP_TCLK X03-20100118 SM_RCOMP_1 R914 1 2 24D9R2F-L-GP
H_CPURST# TCK XDP_TMS
AP26 AP28
RESET_OBS# TMS
PWR MANAGEMENT
AT27 XDP_TRST# SM_RCOMP_2 R916 1 2 130R2F-1-GP
TRST#
JTAG & BPM

AL15 AT29 XDP_TDI_R
22 H_PM_SYNC PM_SYNC TDI
AR27 XDP_TDO_R X02-20091222
TDO XDP_TDI_M
AR29
TDI_M XDP_TDO_M
X02-20091222 AN14
VCCPWRGOOD_1 TDO_M
AP29
+1.05V_VTT
AN25 H_DBR#_R 1 R911 2 XDP_DBRESET#
VCCPWRGOOD DBR# XDP_TMS
1 R910 0R0402-PAD
25,42 H_PWRGD 2
0R0402-PAD
AN27
VCCPWRGOOD_0 R919
1
DY 2 51R2J-2-GP
XDP_OBS0 XDP_TDI_R
22 PM_DRAM_PWRGD 1 R912 2 VDDPWRGOOD_R AK13
BPM#0
AJ22
AK22 XDP_OBS1 +1.5V_RUN_CPU R920
1
DY 2 51R2J-2-GP
0R0402-PAD SM_DRAMPWROK BPM#1 XDP_OBS2 XDP_PREQ#
AK24 1
BPM#2
AJ24 XDP_OBS3 R922 DY 2 51R2J-2-GP
1
BPM#3 XDP_OBS4
X01 20091121 49 H_VTTPWRGD AM15
VTTPWRGOOD BPM#4
AJ25
XDP_OBS5 R915 XDP_TCLK
VTTPWRGOOD signal must be clean BPM#5
AH22
AK23 XDP_OBS6 1KR2J-1-GP R923
1
DY 2 51R2J-2-GP
H_PWRGD_XDP AM26
BPM#6
AH23 XDP_OBS7 DY
TAPPWRGOOD BPM#7
and close to CPU
2
PLT_RST#_R
For EMI 21,37,70,76,78,80 PLT_RST# 1 2 AL14
RSTIN# SM_DRAMRST#
X01 20091111
1
R917
XDP_RST#_R 1K54R2F-GP R918
VCCPWRGOOD 750R2F-GP CLARKUNF
C C
1
VDDPWRGOOD_R
H_VTTPWRGD +3.3V_RUN R921
2
PLT_RST#_R 100KR2J-1-GP
XDP_DBRESET#
EC906
C906 EC905
C905 EC904
C904 EC903
C903 EC902
C902 EC901
C901 A00-20100226
2
2E
2E
2E
2E
2E
2E
DY DY DY DY DY U901
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
1 5
A VCC
50 0D75V_EN 2
B VTT_PWRGD_C
3 4
GND Y
1
XDP_TDI_R XDP_TDI
x01 change tolerant 20091117 XDP1 NL17SZ08DFT2G-GP R927
1
R928 DY 2 0R2J-2-GP
NP1 1K54R2F-GP XDP_TRST#
XDP_TDO_M XDP_TDO
1
61
2 R941
1
R929 DY 2
0R2J-2-GP
1
+1.5V_SUS +1.5V_RUN_CPU 62 VDDPWRGOOD_R 1 2
XDP_PREQ# 3 4
DY
1K54R2F-GP
VDDPWRGOOD_KBC 37
R931
1
XDP_PRDY# 5 6 X02-20091224 0R0402-PAD
1
7 8 R930 R932
R924 R925 XDP_OBS0 9 10 750R2F-GP
DY
51R2J-2-GP
2
2
1K1R2F-GP 1K1R2F-GP XDP_OBS1 11 12 XDP_TDI_M 1
DY 13 14 R933 DY 2 0R2J-2-GP
2
XDP_OBS2 15 16
2
XDP_OBS3 17 18 XDP_TDO_R 1 R934 2

VDDPWRGOOD_R 19 20 0R0402-PAD X02-20091222
21 22 +1.05V_VTT
1
R926 23 24 Scan Chain Stuff --> R928, R931, R934 JTAG MAPPING
3KR2F-GP
X01 20091112 XDP_OBS4
25 26 x01 change tolerant 20091117 (Default) No Stuff --> R929, R933
DY XDP_OBS5
27
29
28
30 CPU Only Stuff --> R928, R929
31
DY 32
2
No Stuff --> R931, R934, R933

1
XDP_OBS6 33 34 C901
XDP_OBS7 SCD1U10V2KX-5GP GMCH Only Stuff --> R933, R934
35 36 DY
1
37 38
2
+1.05V_VTT H_PWRGD 1 2 H_CPUPWRGD_XDP 39 40 BCLK_ITP_P R936 No Stuff --> R928, R929, R931
R935 1 DY 2 1KR2J-1-GP PM_PWRBTN#_XDP 41 42 BCLK_ITP_N 51R2J-2-GP
22 PM_PWRBTN#_R R937 DY 0R2J-2-GP 43 44
H_PWRGD_XDP 1 2 PCIE_CLK_XDP_P 45 46 XDP_RST#_R 1 2H_CPURST#
DY DY
2
R938 0R2J-2-GP 47 48 R939 1KR2J-1-GP XDP_DBRESET# 22,23

B 49 50
B
1
C902 XDP_TDO
SCD1U10V2KX-5GP
DY 23 SML0_DATA 51 52
XDP_TRST#
23 SML0_CLK 53 54
55 56 XDP_TDI
2
XDP_TCLK 57 58 XDP_TMS
x01 change tolerant 20091117 59 60
63
64
NP2 XDP_RST#_R 1 2
R940 DY0R2J-2-GP PLT_RST# 21,37,70,76,78,80
PAD-60P-GP
A00-20100208
A A
<Core Design>
Wistron Corporation
Title
CPU (THERMAL/CLOCK/PM )
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU CPU1D 4 OF 9
CPU1C 3 OF 9
SB_CK0 W8 M_CLK_DDR2 19
M_B_DQ[63..0] W9
19 M_B_DQ[63..0] M_CLK_DDR#2 19
CLARKSFIELD
M_B_DQ0 SB_CK#0
SA_CK0 AA6 M_CLK_DDR0 18 B5 SB_DQ0 SB_CKE0 M3 M_CKE2 19
AA7 M_CLK_DDR#0 18 M_B_DQ1 A5
SA_CK#0 SB_DQ1
CLARKSFIELD
M_A_DQ[63..0] P7 M_B_DQ2 C3
18 M_A_DQ[63..0] SA_CKE0 M_CKE0 18 SB_DQ2
M_A_DQ0 A10 M_B_DQ3 B3 V7 M_CLK_DDR3 19
M_A_DQ1 SA_DQ0 M_B_DQ4 SB_DQ3 SB_CK1
D C10 SA_DQ1 E4 SB_DQ4 SB_CK#1 V6 M_CLK_DDR#3 19 D
M_A_DQ2 C7 M_B_DQ5 A6 M2 M_CKE3 19
M_A_DQ3 SA_DQ2 M_B_DQ6 SB_DQ5 SB_CKE1
A7 SA_DQ3 SA_CK1 Y6 M_CLK_DDR1 18 A4 SB_DQ6
M_A_DQ4 B10 Y5 M_CLK_DDR#1 18 M_B_DQ7 C4
M_A_DQ5 SA_DQ4 SA_CK#1 M_B_DQ8 SB_DQ7
D10 SA_DQ5 SA_CKE1 P6 M_CKE1 18 D1 SB_DQ8
M_A_DQ6 E10 M_B_DQ9 D2
M_A_DQ7 SA_DQ6 M_B_DQ10 SB_DQ9
A8 SA_DQ7 F2 SB_DQ10 SB_CS#0 AB8 M_CS#2 19
M_A_DQ8 D8 M_B_DQ11 F1 AD6 M_CS#3 19
M_A_DQ9 SA_DQ8 M_B_DQ12 SB_DQ11 SB_CS#1
F10 SA_DQ9 SA_CS#0 AE2 M_CS#0 18 C2 SB_DQ12
M_A_DQ10 E6 AE8 M_CS#1 18 M_B_DQ13 F5
M_A_DQ11 SA_DQ10 SA_CS#1 M_B_DQ14 SB_DQ13
F7 SA_DQ11 F3 SB_DQ14
M_A_DQ12 E9 M_B_DQ15 G4 AC7 M_ODT2 19
M_A_DQ13 SA_DQ12 M_B_DQ16 SB_DQ15 SB_ODT0
B7 SA_DQ13 H6 SB_DQ16 SB_ODT1 AD1 M_ODT3 19
M_A_DQ14 E7 AD8 M_ODT0 18 M_B_DQ17 G2
M_A_DQ15 SA_DQ14 SA_ODT0 M_B_DQ18 SB_DQ17
C6 SA_DQ15 SA_ODT1 AF9 M_ODT1 18 J6 SB_DQ18
M_A_DQ16 H10 M_B_DQ19 J3
G8 SA_DQ17 G1 SB_DQ20
M_A_DQ18 K7 M_B_DQ21 G5 D4 M_B_DM0
M_A_DQ19 SA_DQ18 M_B_DQ22 SB_DQ21 SB_DM0 M_B_DM1
J8 SA_DQ19 J2 SB_DQ22 SB_DM1 E1
M_A_DQ20 G7 M_B_DQ23 J1 H3 M_B_DM2
M_A_DQ21 SA_DQ20 M_B_DQ24 SB_DQ23 SB_DM2 M_B_DM3
G10 SA_DQ21 J5 SB_DQ24 SB_DM3 K1
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ25 K2 AH1 M_B_DM4
M_A_DQ23 SA_DQ22 SA_DM0 M_A_DM1 M_B_DQ26 SB_DQ25 SB_DM4 M_B_DM5
J10 SA_DQ23 SA_DM1 D7 L3 SB_DQ26 SB_DM5 AL2 M_B_DM[7..0] 19
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ27 M1 AR4 M_B_DM6
M_A_DQ25 SA_DQ24 SA_DM2 M_A_DM3 M_B_DQ28 SB_DQ27 SB_DM6 M_B_DM7
M6 SA_DQ25 SA_DM3 M7 K5 SB_DQ28 SB_DM7 AT8 M_B_DQS#[7..0] 19
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ29 K4
M_A_DQ27 SA_DQ26 SA_DM4 M_A_DM5 M_B_DQ30 SB_DQ29
L9 SA_DQ27 SA_DM5 AM7 M_A_DM[7..0] 18 M4 SB_DQ30
M_A_DQ28 L6 AN10 M_A_DM6 M_B_DQ31 N5 M_B_DQS[7..0] 19
M_A_DQ29 SA_DQ28 SA_DM6 M_A_DM7 M_B_DQ32 SB_DQ31
K8 SA_DQ29 SA_DM7 AN13 M_A_DQS#[7..0] 18 AF3 SB_DQ32
C M_A_DQ30 N8 M_B_DQ33 AG1 M_B_A[15..0] 19
C
M_A_DQ31 SA_DQ30 M_B_DQ34 SB_DQ33 M_B_DQS#0
P9 SA_DQ31 AJ3 SB_DQ34 SB_DQS#0 D5
M_A_DQ32 AH5 M_A_DQS[7..0] 18 M_B_DQ35 AK1 F4 M_B_DQS#1
M_A_DQ33 SA_DQ32 M_B_DQ36 SB_DQ35 SB_DQS#1 M_B_DQS#2
AF5 SA_DQ33 AG4 SB_DQ36 SB_DQS#2 J4
M_A_DQ34 AK6 C9 M_A_DQS#0 M_A_A[15..0] 18 M_B_DQ37 AG3 L4 M_B_DQS#3
M_A_DQ35 SA_DQ34 SA_DQS#0 M_A_DQS#1 M_B_DQ38 SB_DQ37 SB_DQS#3 M_B_DQS#4
AK7 SA_DQ35 SA_DQS#1 F8 AJ4 SB_DQ38 SB_DQS#4 AH2
M_A_DQ36 AF6 J9 M_A_DQS#2 M_B_DQ39 AH4 AL4 M_B_DQS#5
SA_DQ36 SA_DQS#2 SB_DQ39 SB_DQS#5
DDR SYSTEM MEMORY A
M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ40 AK3 AR5 M_B_DQS#6

SA_DQ37 SA_DQS#3 SB_DQ40 SB_DQS#6
DDR SYSTEM MEMORY - B

M_A_DQ38 AJ7 AH7 M_A_DQS#4 M_B_DQ41 AK4 AR8 M_B_DQS#7
M_A_DQ39 SA_DQ38 SA_DQS#4 M_A_DQS#5 M_B_DQ42 SB_DQ41 SB_DQS#7
AJ6 SA_DQ39 SA_DQS#5 AK9 AM6 SB_DQ42
M_A_DQ40 AJ10 AP11 M_A_DQS#6 M_B_DQ43 AN2
M_A_DQ41 SA_DQ40 SA_DQS#6 M_A_DQS#7 M_B_DQ44 SB_DQ43
AJ9 SA_DQ41 SA_DQS#7 AT13 AK5 SB_DQ44
M_A_DQ42 AL10 M_B_DQ45 AK2
AK12 SA_DQ43 AM4 SB_DQ46
M_A_DQ44 AK8 M_B_DQ47 AM3
M_A_DQ45 SA_DQ44 M_B_DQ48 SB_DQ47 M_B_DQS0
AL7 SA_DQ45 AP3 SB_DQ48 SB_DQS0 C5
M_A_DQ46 AK11 C8 M_A_DQS0 M_B_DQ49 AN5 E3 M_B_DQS1
M_A_DQ47 SA_DQ46 SA_DQS0 M_A_DQS1 M_B_DQ50 SB_DQ49 SB_DQS1 M_B_DQS2
AL8 SA_DQ47 SA_DQS1 F9 AT4 SB_DQ50 SB_DQS2 H4
M_A_DQ48 AN8 H9 M_A_DQS2 M_B_DQ51 AN6 M5 M_B_DQS3
AM10 SA_DQ49 SA_DQS3 M9 AN4 SB_DQ52 SB_DQS4 AG2
M_A_DQ50 AR11 AH8 M_A_DQS4 M_B_DQ53 AN3 AL5 M_B_DQS5
AL11 SA_DQ51 SA_DQS5 AK10 AT5 SB_DQ54 SB_DQS6 AP5
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ55 AT6 AR7 M_B_DQS7
M_A_DQ53 SA_DQ52 SA_DQS6 M_A_DQS7 M_B_DQ56 SB_DQ55 SB_DQS7
AN9 SA_DQ53 SA_DQS7 AR13 AN7 SB_DQ56
M_A_DQ54 AT11 M_B_DQ57 AP6
AP12 SA_DQ55 AP8 SB_DQ58
M_A_DQ56 AM12 M_B_DQ59 AT9
AN12 SA_DQ57 AT7 SB_DQ60
M_A_DQ58 AM13 Y3 M_A_A0 M_B_DQ61 AP9
B M_A_DQ59 SA_DQ58 SA_MA0 M_A_A1 M_B_DQ62 SB_DQ61 B
AT14 SA_DQ59 SA_MA1 W1 AR10 SB_DQ62
M_A_DQ60 AT12 AA8 M_A_A2 M_B_DQ63 AT10 U5 M_B_A0
M_A_DQ61 SA_DQ60 SA_MA2 M_A_A3 SB_DQ63 SB_MA0 M_B_A1
AL13 SA_DQ61 SA_MA3 AA3 SB_MA1 V2
M_A_DQ62 AR14 V1 M_A_A4 T5 M_B_A2
M_A_DQ63 SA_DQ62 SA_MA4 M_A_A5 SB_MA2 M_B_A3
AP14 SA_DQ63 SA_MA5 AA9 SB_MA3 V3
V8 M_A_A6 R1 M_B_A4
SA_MA6 M_A_A7 SB_MA4 M_B_A5
SA_MA7 T1 19 M_B_BS0 AB1 SB_BS0 SB_MA5 T8
Y9 M_A_A8 19 M_B_BS1 W5 R2 M_B_A6
SA_MA8 M_A_A9 SB_BS1 SB_MA6 M_B_A7
18 M_A_BS0 AC3 SA_BS0 SA_MA9 U6 19 M_B_BS2 R7 SB_BS2 SB_MA7 R6
18 M_A_BS1 AB2 AD4 M_A_A10 R4 M_B_A8
SA_BS1 SA_MA10 M_A_A11 SB_MA8 M_B_A9
18 M_A_BS2 U7 SA_BS2 SA_MA11 T2 SB_MA9 R5
U3 M_A_A12 19 M_B_CAS# AC5 AB5 M_B_A10
SA_MA12 M_A_A13 SB_CAS# SB_MA10 M_B_A11
SA_MA13 AG8 19 M_B_RAS# Y7 SB_RAS# SB_MA11 P3
T3 M_A_A14 19 M_B_W E# AC6 R3 M_B_A12
SA_MA14 M_A_A15 SB_WE# SB_MA12 M_B_A13
18 M_A_CAS# AE1 SA_CAS# SA_MA15 V9 SB_MA13 AF7
18 M_A_RAS# AB3 P5 M_B_A14
SA_RAS# SB_MA14 M_B_A15
18 M_A_W E# AE9 SA_WE# SB_MA15 N1
CLARKUNF
A CLARKUNF <Core Design> A
Wistron Corporation
Title
CPU (DDR)
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1E 5 OF 9
AJ13
RSVD#AJ13
D AJ12 D
RSVD#AJ12
AP25
RSVD#AP25
CLARKSFIELD
AL25 AH25
RSVD#AL25 RSVD#AH25
AL24 AK26
RSVD#AL24 RSVD#AK26
AL22
RSVD#AL22
AJ33 AL26
RSVD#AJ33 RSVD#AL26
AG9 AR2
RSVD#AG9 RSVD_NCTF_37
M27
CFG0 RSVD#M27
L28 AJ26
RSVD#L28 RSVD#AJ26
PCI-Express Configuration Select J17
SA_DIMM_VREF RSVD#AJ27
AJ27
1
H17
R1101 SB_DIMM_VREF
G25
3KR2F-GP RSVD#G25
DY 1:Single PEG G17
RSVD#G17
CFG0 0:Bifurcation enabled E31
RSVD#E31
E30
2
RSVD#E30
AL28
CFG0 RSVD#AL28
AM30 AL29
TPAD14-GP TP1101 CFG1 CFG0 RSVD#AL29
1 AM28 AP30
TPAD14-GP TP1102 CFG2 CFG1 RSVD#AP30
1 AP31 AP32
TPAD14-GP TP1103 CFG3 CFG2 RSVD#AP32
1 AL32 AL27
CFG3 CFG4 CFG3 RSVD#AL27
AL30 AT31
TPAD14-GP TP1104 CFG5 CFG4 RSVD#AT31
CFG3 - PCI-Express Static Lane Reversal 1 AM31
CFG5 RSVD#AT32
AT32
1
TPAD14-GP TP1105 1 CFG6 AN29 AP33

R1104 CFG7 CFG6 RSVD#AP33
DIS 3KR2J-2-GP 1 :Normal Operation TPAD14-GP TP1106 1 CFG8
AM32
AK32
CFG7 RSVD#AR33
AR33
CFG8
CFG3 0 :Lane Numbers Reversed TPAD14-GP TP1107 1 CFG9 AK31
RESERVED
TPAD14-GP TP1108 CFG10 CFG9
C 1 AK28 C
2
CFG10
15 -> 0, 14 -> 1, ... TPAD14-GP
TPAD14-GP
TP1109
TP1110
1
1
CFG11
CFG12
AJ28
AN30
CFG11
AR32
TPAD14-GP TP1111 CFG13 CFG12 RSVD#AR32
1 AN32
1 AJ32
1 AJ29 E15
TPAD14-GP TP1114 CFG16 CFG15 RSVD_TP#E15
1 AJ30 F15
TPAD14-GP TP1115 CFG17 CFG16 RSVD_TP#F15
1 AK30 A2
CFG17 KEY
H16 D15
RSVD_TP_86 RSVD#D15
C15
RSVD#C15
AJ15
RSVD#AJ15
AH15
CFG4 RSVD#AH15
CFG4 - Display Port Presence B19
1
RSVD#B19
A19
R1105 RSVD#A19
3KR2F-GP 1:Disabled; No Physical Display Port
DY CFG4
A20
B20
RSVD#A20
attached to Embedded Display Port RSVD#B20
AA5
2
0:Enabled; An external Display Port SA_CK2

U9 AA4
RSVD#U9 SA_CK#2
device is connected to the Embedded T9
RSVD#T9 SA_CKE2
R8
AD3
Display Port AC9
SA_CS#2
AD2
RSVD#AC9 SA_ODT2
AB9 AA2
RSVD#AB9 SA_CK3
AA1
SA_CK#3
R9
SA_CKE3
AG7
SA_CS#3
AE3
SA_ODT3
CFG7 V4
SB_CK2
CFG7(Reserved) - Temporarily used for early V5
1
SB_CK#2
N2
R1106 Clarksfield samples. SB_CKE2
B
3KR2F-GP
J29
RSVD#J29 SB_CS#2
AD5 VSS (AP34) can be left NC is B
DY CFG7 Clarksfield (only for early samples pre-ES1) -

J28
RSVD#J28 SB_ODT2
AD7
W3 CRB implementation; EDS/DG
SB_CK3
Connect to GND with 3.01K Ohm/5% resistor. W2 recommendation to GND.
2
SB_CK#3
N3
SB_CKE3
AE5
SB_CS#3
Note: Only temporary for early CFD sample SB_ODT3
AD9
(rPGA/BGA) [For details please refer to the R1107
WW33 MoW and sighting report]. AP34 RSVD_VSS 1 2
VSS 0R0402-PAD
For a common M/B design (for AUB and CFD),
the pull-down resistor shouble be used. Does
not impact AUB functionality. X02-20091224
CLARKUNF
A A
<Core Design>
Wistron Corporation
Title
Size
CPU (RESERVED)
Document Number Rev
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU CPU1F 6 OF 9
+VCC_CORE
CLARKSFIELD
+1.05V_VTT
PROCESSOR CORE POWER
AG35 AH14
VCC VTT0
AG34 AH12
1
VCC VTT0 C1209 C1202 C1210 C1211 C1212 C1203 C1204 C1213 C1214
AG33 AH11
+VCC_CORE
x01 change tolerant 20091117 48A AG32
VCC
VCC
VTT0
VTT0
AH10
DY DY DY DY DY
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AG31 J14
2
VCC VTT0
D AG30 J13 D
VCC VTT0
AG29 H14
C1201 C1205 C1206 C1207 C1215 C1208 VCC VTT0
AG28 H12
VCC VTT0
1
1
DY DY AG27
VCC VTT0
G14
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AG26 G13
VCC VTT0
AF35 G12
2
2
VCC VTT0
AF34 G11
VCC VTT0
AF33 F14
VCC VTT0
AF32 F13
VCC VTT0 +1.05V_VTT
AF31
VCC VTT0
F12 x01 change tolerant 20091117
AF30 F11
VCC VTT0
AF29
VCC VTT0
E14
C1216 C1217 C1218
The decoupling capacitors, filter
x01 change tolerant 20091117 AF28
VCC VTT0
E12
recommendations and sense resistors on the
1
AF27 D14
VCC VTT0
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5MX-3GP
AF26
VCC VTT0
D13
DY CPU/PCH Rails are specific to the CRB
1.1V RAIL POWER

C1219 C1220 C1221 C1222 C1223 C1224 AD35 D12
2
VCC VTT0 Implementation. Customers need to follow the
1
DY DY 1DY AD34
VCC VTT0
D11
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AD33
VCC VTT0
C14 recommendations in the Calpella Platform
AD32 C13
2
AD31
VCC VTT0
C12 Design Guide.
VCC VTT0
AD30 C11
VCC VTT0
AD29 B14
VCC VTT0
AD28 B12
VCC VTT0
AD27 A14
VCC VTT0
AD26 A13
VCC VTT0
AC35 A12
VCC VTT0
x01 change tolerant 20091117 AC34
VCC VTT0
A11
AC33
C1226 C1228 C1229 C1230 C1231 C1232 VCC +1.05V_VTT
AC32
VCC x01 change tolerant 20091117
1
C1225 C1227 DY DY AC31

VCC
SC10U6D3V5KX-1GP
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5MX-3GP
DY DY DY DY AC30
AC29
VCC VTT0
AF10
AE10
2
VCC VTT0 C1234

AC28 AC10
VCC VTT0
1
CPU CORE SUPPLY
C AC27 AB10 C1233 C
VCC VTT0
SC10U6D3V5MX-3GP
AC26 Y10
VCC VTT0
SC10U6D3V5KX-1GP
AA35 W10
DY
2
VCC VTT0
AA34 U10
VCC VTT0
AA33 T10
VCC VTT0
x01 change tolerant 20091117 AA32
VCC VTT0
J12
AA31 J11
VCC VTT0
AA30 J16
C1235 C1236 C1237 C1238 C1239 C1240 C1241 C1242 VCC VTT0
AA29 J15
1
VCC VTT0
DY DY AA28
VCC
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
DY AA27
AA26
VCC
2
VCC
Y35
Y34
VCC Please note that the VTT Rail
VCC
Y33
Y32
VCC Values are Auburndale
VCC
Y31 VTT=1.05V; Clarksfield
1
C1243 VCC
Y30
VCC
DY Y29
VCC VTT=1.1V
Y28
2
VCC
SC22U6D3V5MX-2GP
Y27
VCC
Y26
VCC
V35 AN33 PSI# 47
VCC PSI#
V34
VCC
V33 H_VID[6..0] 47
VCC H_VID0
V32 AK35
VCC VID
V31
V30
V29
VCC
VCC
POWER VID
VID
AK33
AK34
AL35
H_VID1
H_VID2
H_VID3
VCC VID
V28
VCC CPU VIDS VID
AL33 H_VID4
V27 AM33 H_VID5
VCC VID H_VID6
V26 AM35
VCC VID
U35 AM34 PM_DPRSLPVR 47
VCC PROC_DPRSLPVR
B U34 B
VCC
U33
VCC
U32
VCC H_VTTVID1 TP1201 TPAD14-GP
U31 G15 1
VCC VTT_SELECT
U30
VCC
U29
VCC H_VTTVID1 = Low, 1.1V
U28
U27
VCC H_VTTVID1 = High, 1.05V
VCC +VCC_CORE
U26
VCC
R35
VCC
R34
1
VCC
R33
VCC R1201
R32 AN35 IMVP_IMON 47
VCC ISENSE 100R2F-L1-GP-U
R31
VCC
R30
VCC
R29
2
VCC
SENSE LINES
R28 AJ34 VCC_SENSE 47

VCC VCC_SENSE
R27 AJ35 VSS_SENSE 47
VCC VSS_SENSE
R26
1
VCC
P35
VCC R1202
P34 B15 VTT_SENSE 49
VCC VTT_SENSE TP_VSS_SENSE_VTT 1 100R2F-L1-GP-U
P33 A15
VCC VSS_SENSE_VTT TP1202 TPAD14-GP
P32
VCC
P31
2
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC
A A
<Core Design>
CLARKUNF
Wistron Corporation
Title

CPU (VCC_CORE) Rev
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
+CPU_GFX_CORE
22A CPU1G 7 OF 9
AT21 VAXG
D AT19 VAXG VAXG_SENSE AR22 VCC_AXG_SENSE 53 D
1
C1301 C1302 C1303 C1304 C1305 C1306 C1307 C1308
SENSE
LINES
AT18 VAXG VSSAXG_SENSE AT22 VSS_AXG_SENSE 53
1
1
AT16 VAXG
CLARKSFIELD
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
R1302
DY DY DY DY UMA UMA UMA UMA DIS AR21
AR19
VAXG
2
2
VAXG
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
0R3J-0-U-GP AR18
2
VAXG
SC10U6D3V5MX-3GP
AR16 VAXG GFX_VID AM22 GFX_VID0 53
AP21 VAXG GFX_VID AP22 GFX_VID1 53
GRAPHICS VIDs
AP19 VAXG GFX_VID AN22 GFX_VID2 53
AP18 VAXG GFX_VID AP23 GFX_VID3 53
AP16 VAXG GFX_VID AM23 GFX_VID4 53
AN21 VAXG GFX_VID AP24 GFX_VID5 53
GRAPHICS
AN19 VAXG GFX_VID AN24 GFX_VID6 53
AN18 VAXG
AN16 R1305 2 UMA 1 4K7R2J-2-GP
VAXG
AM21 VAXG GFX_VR_EN AR25 GFX_VR_EN 53
AM19 VAXG GFX_DPRSLPVR AT25 GFX_DPRSLPVR 53
AM18 AM24 GFX_IMON_C 1 DY 2
VAXG GFX_IMON R1304 0R2J-2-GP GFX_IMON 53
AM16 VAXG
AL21 +1.5V_RUN_CPU
VAXG
AL19
AL18
VAXG 1
R1303 DIS 1KR2J-1-GP
2
AL16
AK21
VAXG
VAXG
AJ1
3A
VAXG VDDQ
AK19 VAXG VDDQ AF1
1
C1309 C1310 C1311 C1312 C1313 C1314 C1315 TC1301
Please note that the VTT Rail AK18 AE7
- 1.5V RAILS
VAXG VDDQ
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC22U6D3V5MX-2GP
AK16 VAXG VDDQ AE4
+1.5V_SUS
SC1U6D3V2KX-GP
SC22U6D3V5MX-2GP
Values are: Auburndale VTT=1.05V AJ21 AC1
DY SE330U2D5VDM-2GP
2
VAXG VDDQ
C
AJ19 VAXG VDDQ AB7 x01 change tolerant 20091117 C
Clarksfield VTT=1.1V AJ18
AJ16
VAXG VDDQ AB4
Y1
S3 Reduction
VAXG VDDQ
AH21 VAXG VDDQ W7
AH19 VAXG VDDQ W4
1
AH18 U1 C1331 C1332 C1333 C1334
VAXG VDDQ
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AH16 T7 DY DY DY DY
POWER
VAXG VDDQ
T4
2
VDDQ
VDDQ P1
VDDQ N7
+1.05V_VTT N4
VDDQ
DDR3
VDDQ L1
J24 VTT1 VDDQ H1 x01 change tolerant 20091117
FDI
J23 VTT1
C1317 H25 VTT1
1
C1316
SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP +1.05V_VTT
P10
2
VTT0
N10
VTT0
VTT0 L10
K10
2.6A
VTT0
1
C1318 C1319
+1.05V_VTT
x01 change tolerant 20091117 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
18A
2
1.1V
VTT1 J22
K26 VTT1 VTT1 J20
J27 VTT1 VTT1 J18
+1.05V_VTT
PEG & DMI

C1321 C1322 C1323 J26 VTT1 VTT1 H21 x01 change tolerant 20091117
1
C1320 DY J25 H20

B VTT1 VTT1 B
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP H27 H19

VTT1 VTT1
G28
2
VTT1
1
G27 C1324 C1325
VTT1 SC10U6D3V5KX-1GP SC4D7U6D3V3KX-GP
G26 VTT1 DY
F26
2
VTT1
E26 VTT1 VCCPLL L26
1.8V
E25 L27
VTT1 VCCPLL
VCCPLL M26 1.35A +1.8V_RUN
1
C1328 C1329 C1330
SC4D7U6D3V3KX-GP
C1326 C1327
SC2D2U6D3V3KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP SC10U6D3V5MX-3GP
2
CLARKUNF
A <Core Design> A
Wistron Corporation
Title

CPU (VCC_GFXCORE) Rev
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1H 8 OF 9 CPU1I 9 OF 9
AT20 VSS VSS AE34

AT17 VSS VSS AE33
AR31 VSS VSS AE32 K27 VSS
CLARKSFIELD
CLARKSFIELD
D AR23 VSS VSS AE28 J32 VSS D
AR20 VSS VSS AE27 J30 VSS
AR12 VSS VSS AD10 H35 VSS
AR9 VSS VSS AC8 H32 VSS
AP20 VSS VSS AB35 H24 VSS
AN34 VSS VSS AB28 H5 VSS
AN31 VSS VSS AB27 H2 VSS
AN23 VSS VSS AB26 G34 VSS
AN20 VSS VSS AB6 G31 VSS
AN17 VSS VSS AA10 G20 VSS
AM29 VSS VSS Y8 G9 VSS
AM20 VSS VSS W35 F30 VSS
C AM2 W29 E35 C
VSS VSS VSS
AL34 W28 E32
AL31
AL23
VSS
VSS
VSS
VSS VSS
VSS
VSS
W27
W26
E29
E24
VSS
VSS
VSS
VSS
AL20 VSS VSS W6 E21 VSS
AL17 VSS VSS V10 E18 VSS
AL12 VSS VSS U8 E13 VSS
AL3 VSS VSS T35 E5 VSS
AK29 VSS VSS T34 E2 VSS
AK27 VSS VSS T33 D33 VSS
AK25 VSS VSS T32 D30 VSS VSS_NCTF AR34
AK20 VSS VSS T31 D26 VSS VSS_NCTF B34
AK17 T30 D9 B2
NCTF
VSS VSS VSS VSS_NCTF
AJ31 VSS VSS T29 D6 VSS
AJ23 VSS VSS T28 D3 VSS
A35,AT1,AT35,B1,A3,A33,A34,
AJ20 T27 C34 A35 TP_MCP_VSS_NCTF1 1 TP1401
AP1,AP35,AR1,AR35,AT2,AT3,
VSS VSS VSS VSS_NCTF#A35 TP_MCP_VSS_NCTF2 TP1402
AJ17 VSS VSS T26 C32 VSS VSS_NCTF#AT1 AT1 1
AJ14 T6 C29 AT35 TP_MCP_VSS_NCTF3 1 TP1403
VSS VSS VSS VSS_NCTF#AT35 TP_MCP_VSS_NCTF4 TP1404
AJ11 VSS VSS R10 C28 VSS VSS_NCTF#B1 B1 1
AJ8 P8 C24 A3
AT33,AT34,C1,C35,B35
VSS VSS VSS RSVD_NCTF#A3
AJ5 VSS VSS P4 C22 VSS RSVD_NCTF#A33 A33
AJ2 VSS VSS P2 C20 VSS RSVD_NCTF#A34 A34
AH35 VSS VSS N35 C19 VSS RSVD_NCTF#AP1 AP1
AH34 VSS VSS N34 C16 VSS RSVD_NCTF#AP35 AP35
NCYF TEST PIN:

AH33 VSS VSS N33 B31 VSS RSVD_NCTF#AR1 AR1
AH32 VSS VSS N32 B25 VSS RSVD_NCTF#AR35 AR35
AH31 VSS VSS N31 B21 VSS RSVD_NCTF#AT2 AT2
B B
AH27 VSS VSS N27 B11 VSS RSVD_NCTF#C1 C1
AH26 VSS VSS N26 B8 VSS RSVD_NCTF#C35 C35
AH20 VSS VSS N6 B6 VSS RSVD_NCTF#B35 B35
AH17 VSS VSS M10 B4 VSS
AH13 VSS VSS L35 A29 VSS
AG10 VSS VSS L5
AF8 VSS VSS L2
AF4 VSS VSS K34
AF2 VSS VSS K33
AE35 VSS VSS K30
CLARKUNF CLARKUNF
A <Core Design> A
Wistron Corporation
Title
CPU (VSS)
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = MEMORY M_A_DM[7..0] 10
M_A_DQS#[7..0] 10
M_A_DQS[7..0] 10
DM1
M_A_A[15..0] 10
M_A_A0 98 NP1 Note:
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2 If SA0 DIM0 = 0, SA1_DIM0 = 0
96
M_A_A3 A2 SA0_DIM0
95 110 M_A_RAS# 10 SO-DIMMA SPD Address is 0xA0
M_A_A4 A3 RAS#
92 113 M_A_WE# 10
A4 WE#
M_A_A5 91
A5 CAS#
115 M_A_CAS# 10
SA1_DIM0 SO-DIMMA TS Address is 0x30
M_A_A6 90
M_A_A7 A6
86 114 M_CS#0 10
1
A7 CS0#
M_A_A8 89
A8 CS1#
121 M_CS#1 10 If SA0 DIM0 = 1, SA1_DIM0 = 0
D M_A_A9 85 R1803 R1804 D
M_A_A10 107
A9
73 10KR2J-3-GP 10KR2J-3-GP SO-DIMMA SPD Address is 0xA2
A10/AP CKE0 M_CKE0 10
M_A_A11 84 74 SO-DIMMA TS Address is 0x32
A11 CKE1 M_CKE1 10
M_A_A12 83
2
M_A_A13 A12
119 101 M_CLK_DDR0 10
M_A_A14 A13 CK0
80 103 M_CLK_DDR#0 10
M_A_A15 A14 CK0#
78
A15
79 102 M_CLK_DDR1 10
10 M_A_BS2 A16/BA2 CK1
104 M_CLK_DDR#1 10
CK1#
109
10 M_A_BS0 BA0 M_A_DM0
108 11
10 M_A_BS1 BA1 DM0 M_A_DM1
10 M_A_DQ[63..0] 28
M_A_DQ0 DM1 M_A_DM2
5 46
M_A_DQ1 DQ0 DM2 M_A_DM3
7 63
15 136
17 153
4 170
6 187
M_A_DQ6 DQ5 DM7
16
M_A_DQ7 DQ6
18 200 PCH_SMBDATA 7,19,23,76
M_A_DQ8 DQ7 SDA
21 202 PCH_SMBCLK 7,19,23,76
M_A_DQ9 DQ8 SCL
23
M_A_DQ10 DQ9 +3.3V_RUN
33 198 PM_EXTTS#0 9
M_A_DQ11 DQ10 EVENT#
35
M_A_DQ12 DQ11
22 199
M_A_DQ13 DQ12 VDDSPD
24
M_A_DQ14 DQ13 SA0_DIM0
34 197 x01 change tolerant 20091117
1
M_A_DQ15 DQ14 SA0 SA1_DIM0 C1802
36 201
M_A_DQ16 DQ15 SA1 C1801
M_A_DQ17
39
41
DQ16
77 SCD1U10V2KX-5GP DY SC2D2U6D3V3KX-GP
2
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 +1.5V_SUS
53 125
M_A_DQ20 DQ19 NC#/TEST
40
M_A_DQ21 DQ20
42 75
M_A_DQ22 DQ21 VDD1
M_A_DQ23
50
DQ22 VDD2
76
+1.5V_SUS SODIMM A DECOUPLING
52 81
M_A_DQ24 DQ23 VDD3
57 82
M_A_DQ25 DQ24 VDD4
59
DQ25 VDD5
87 x01 change tolerant 20091117
M_A_DQ26 67 88
M_A_DQ27 DQ26 VDD6
69 93
M_A_DQ28 DQ27 VDD7
56 94
M_A_DQ29 DQ28 VDD8 TC1801 C1803 C1804 C1805 C1806 C1807 C1808 C1809 C1810
C 58 99 C
1
DQ29 VDD9
SE330U2D5VDM-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
M_A_DQ30 68 100
M_A_DQ31 DQ30 VDD10 DY
M_A_DQ32
70
129
DQ31 VDD11
105
106
DY DY DY
DY
2
M_A_DQ33 DQ32 VDD12
131 111
M_A_DQ34 DQ33 VDD13
141 112
M_A_DQ35 DQ34 VDD14
143 117
+V_DDR_REF M_A_DQ36 DQ35 VDD15
x01 change tolerant 20091118 130
DQ36 VDD16
118
M_A_DQ37 132 123
M_A_DQ38 DQ37 VDD17
140 124
M_A_DQ39 DQ38 VDD18
142
1
C1812 M_A_DQ40 DQ39

147 2
C1811 C1813 M_A_DQ41 DQ40 VSS C1814 C1815 C1816 C1817
DY 149 3 x01 change tolerant 20091117
1
SCD1U10V2KX-5GP SC2D2U6D3V3KX-GP SCD1U10V2KX-5GP M_A_DQ42 DQ41 VSS
157 8 Layout Note:
2
DQ42 VSS
SCD1U10V2KX-5GP
M_A_DQ43 159 9
DQ43 VSS Place these Caps near
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_A_DQ44 146 13
2
M_A_DQ45 DQ44 VSS
148 14 SO-DIMMA.
M_A_DQ46 DQ45 VSS
158 19
M_A_DQ47 DQ46 VSS
160 20
M_A_DQ48 DQ47 VSS
163 25
M_A_DQ49 DQ48 VSS
165 26
M_A_DQ50 DQ49 VSS
175 31
M_A_DQ51 DQ50 VSS
177 32
M_A_DQ52 DQ51 VSS
164 37
M_A_DQ53 DQ52 VSS
166 38
M_A_DQ54 DQ53 VSS
174 43
M_A_DQ55 DQ54 VSS
176 44
M_A_DQ56 DQ55 VSS
181 48
M_A_DQ57
M_A_DQ58
M_A_DQ59
183
191
DQ56
DQ57
DQ58
VSS
VSS
VSS
49
54
2 S3 Power Reduction
193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ61 DQ60 VSS
182 61
M_A_DQ62 DQ61 VSS +0.75V_DDR_VTT
192 65
M_A_DQ63 DQ62 VSS
194 66
DQ63 VSS
71
1
M_A_DQS#0 VSS
10 72
+0.75V_DDR_VTT M_A_DQS#1 DQS0# VSS R1806
27 127
M_A_DQS#2 DQS1# VSS 22R2J-2-GP
45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
135 134
2
1
B M_A_DQS#5 DQS4# VSS B

152 138
DQS5# VSS
DISCHARGE_0D75V
C1818 M_A_DQS#6
DY SC10U6D3V5KX-1GP M_A_DQS#7
169
186
DQS6# VSS
139
144
2
DQS7# VSS
145
M_A_DQS0 VSS
12 150
M_A_DQS1 DQS0 VSS
29 151
M_A_DQS2 DQS1 VSS
47 155
M_A_DQS3 DQS2 VSS
64 156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
Place these caps 188 168
D
+0.75V_DDR_VTT DQS7 VSS Q1801
172
close to VTT1 and VSS
10 M_ODT0
116
ODT0 VSS
173 .
VTT2. 120 178
10 M_ODT1 ODT1 VSS
VSS
179 .
.
+V_DDR_REF 126
VREF_CA VSS
184 . .
1 185
VREF_DQ VSS
C1819
C1820
C1821
C1822
189 2N7002E-1-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
S
VSS
1
30 190
9,19 DDR3_DRAMRST# RESET# VSS
DY DY VSS
195
84.2N702.D31
196
2
VSS 42,50 PS_S3CNTRL

+0.75V_DDR_VTT 203 205
VTT1 VSS
204 206
VTT2 VSS
H =4mm DDR3-204P-47-GP
62.10017.P31
SEC. 62.10017.P11
A A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM1
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = MEMORY DM2
M_B_A0 98 NP1 M_B_DM[7..0] 10

M_B_A1 A0 NP1 +3.3V_RUN
97 NP2
M_B_A2 A1 NP2
96 M_B_DQS#[7..0] 10
M_B_A3 A2
95 110 M_B_RAS# 10
M_B_A4 A3 RAS#
92 113 M_B_WE# 10
1
M_B_A5 A4 WE#
91 115 M_B_CAS# 10 M_B_DQS[7..0] 10
M_B_A6 A5 CAS# R1902
90
M_B_A7 A6 10KR2J-3-GP
86 114 M_CS#2 10 M_B_A[15..0] 10
M_B_A8 A7 CS0#
89 121 M_CS#3 10
M_B_A9 A8 CS1#
85
2
M_B_A10 A9
M_B_A11
107
A10/AP CKE0
73 M_CKE2 10 Note:
84 74 M_CKE3 10
M_B_A12 A11 CKE1 SA1_DIM1 If SA0 DIM0 = 0, SA1_DIM0 = 0
83
M_B_A13 A12
119 101 M_CLK_DDR2 10 SO-DIMMA SPD Address is 0xA0
M_B_A14 A13 CK0 SA0_DIM1
80 103 M_CLK_DDR#2 10
A14 CK0#
M_B_A15 78
A15
SO-DIMMA TS Address is 0x30
D 79 102 M_CLK_DDR3 10 D
A16/BA2 CK1
1
10 M_B_BS2
104 M_CLK_DDR#3 10
CK1#
10 M_B_BS0
109
BA0
R1903 If SA0 DIM0 = 1, SA1_DIM0 = 0
108 11 M_B_DM0 10KR2J-3-GP
10 M_B_BS1 BA1 DM0
28 M_B_DM1 SO-DIMMA SPD Address is 0xA2
10 M_B_DQ[63..0] DM1
M_B_DQ0 5 46 M_B_DM2 SO-DIMMA TS Address is 0x32
2
M_B_DQ1 DQ0 DM2 M_B_DM3
7 63
15 136
17 153
4 170
6 187
M_B_DQ6 DQ5 DM7
16
M_B_DQ7 DQ6
18 200 PCH_SMBDATA 7,18,23,76
M_B_DQ8 DQ7 SDA
21 202 PCH_SMBCLK 7,18,23,76
M_B_DQ9 DQ8 SCL
23
M_B_DQ10 DQ9 +3.3V_RUN
33 198 PM_EXTTS#1 9
M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11
22 199
M_B_DQ13 DQ12 VDDSPD
24
1
M_B_DQ14 DQ13 SA0_DIM1 C1902
34 197
M_B_DQ15 DQ14 SA0 SA1_DIM1 C1901
36 201
M_B_DQ16 39
DQ15 SA1 SCD1U10V2KX-5GP DY SC2D2U6D3V3KX-GP
2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1
51 122
M_B_DQ19 DQ18 NC#2 +1.5V_SUS
53 125
M_B_DQ20 DQ19 NC#/TEST
40
DQ20 x01 change tolerant 20091118
M_B_DQ21 42 75
M_B_DQ22 DQ21 VDD1
50 76
M_B_DQ23 DQ22 VDD2
52 81
M_B_DQ24 DQ23 VDD3
57 82
M_B_DQ25 DQ24 VDD4
59 87
M_B_DQ26 DQ25 VDD5
67 88
M_B_DQ27 DQ26 VDD6
69 93
M_B_DQ28 DQ27 VDD7
56 94
M_B_DQ29 DQ28 VDD8
58 99
M_B_DQ30 DQ29 VDD9
68 100
M_B_DQ31 DQ30 VDD10
70 105
M_B_DQ32 DQ31 VDD11
129 106
M_B_DQ33 DQ32 VDD12
131 111
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
C 130 118 C
M_B_DQ37 DQ36 VDD16
132 123
M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18
142
M_B_DQ40 DQ39
147 2
M_B_DQ41 DQ40 VSS
M_B_DQ42
149
DQ41 VSS
3 SODIMM B DECOUPLING
157 8
M_B_DQ43 DQ42 VSS +1.5V_SUS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148
DQ45 VSS
M_B_DQ46 158 19
M_B_DQ47 DQ46 VSS
160 20
M_B_DQ48 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS C1903 C1904 C1905 C1906 C1907 C1908 C1909 C1910
165 26
1
DQ49 VSS
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
M_B_DQ50 175 31
M_B_DQ51 DQ50 VSS DY
177
DQ51 VSS
32
DY DY
SC10U10V5ZY-1GP
M_B_DQ52 164 37
DY
2
M_B_DQ53 DQ52 VSS
166 38
M_B_DQ54 DQ53 VSS
174 43
M_B_DQ55 DQ54 VSS
176 44
M_B_DQ56 DQ55 VSS
181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
M_B_DQ60
193
180
DQ59 VSS
55
60
M_B_DQ61 DQ60 VSS C1911 C1912 C1913 C1914
182 61
1
M_B_DQ62 DQ61 VSS
192 65
DQ62 VSS
SCD1U10V2KX-5GP
M_B_DQ63 194 66
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DQ63 VSS
71 Layout Note:
2
M_B_DQS#0 VSS
10 72
M_B_DQS#1 DQS0# VSS Place these Caps near
27 127
M_B_DQS#2 DQS1# VSS
45 128 SO-DIMMB.
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
M_B_DQS2 DQS1 VSS
47 155
B M_B_DQS3 DQS2 VSS B
64 156
+V_DDR_REF M_B_DQS4 DQS3 VSS
x01 change tolerant 20091118 137
DQS4 VSS
161
M_B_DQS5 154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
1
C1916 DQS7 VSS

172
C1915 C1917 VSS
SCD1U10V2KX-5GP DY SC2D2U6D3V3KX-GP SCD1U10V2KX-5GP 10 M_ODT2
116
120
ODT0 VSS
173
178
2
10 M_ODT3 ODT1 VSS

179
VSS
+V_DDR_REF 126 184
VREF_CA VSS
1 185
VREF_DQ VSS
189
+0.75V_DDR_VTT VSS
30 190
9,18 DDR3_DRAMRST# RESET# VSS
195
VSS
196
VSS
203 205
VTT1 VSS
204 206
VTT2 VSS
Place these caps

C1918
C1919
C1920
C1921
H = 8mm
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1
close to VTT1 and DDR3-204P-55-GP

VTT2. DY DY
2
62.10017.Q31

SEC. 62.10017.N71
Note:
SO-DIMMB SPD Address is 0xA4 SO-DIMMB is placed farther from
SO-DIMMB TS Address is 0x34 the Processor than SO-DIMMA
A A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM2
Berry A00
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
U2001D 4 OF 10
4
3
55 PCH_VGA_BLEN T48 L_BKLTEN SDVO_TVCLKINN BJ46
55 PCH_LCDVDD_EN T47 BG46 RN2006
L_VDD_EN SDVO_TVCLKINP
55 PCH_LBKLT_CTL Y48 BJ48
UMASRN2K2J-1-GP
RN2001 L_BKLTCTL SDVO_STALLN
D
SDVO_STALLP BG48 D
54,82 GPU_LVDS_CLK 1 4 LDDC_CLK_PCH AB48
1
2
LDDC_DATA_PCH L_DDC_CLK
54,82 GPU_LVDS_DATA 2
UMA 3 Y45 L_DDC_DATA SDVO_INTN BF45
BH45
SRN0J-6-GP LCTRL_CLK SDVO_INTP
AB46 L_CTRL_CLK
LCTRL_DATA V48 L_CTRL_DATA
LIBG AP39 T51
LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK 57
TPAD14-GP TP2001 1LVDS_VBG AP41 T53
LVD_VBG SDVO_CTRLDATA PCH_HDMI_DATA 57
1
RN2004
R2002 R2001 1 4 LVD_VREFH AT43 LVD_VREFH
1 PCH_LCDVDD_EN Place near PCH 2K37R2F-GP 3 LVD_VREFL AT42
2
DY 2
UMA LVD_VREFL DDPB_AUXN BG44
BJ44
100KR2J-1-GP SRN0J-6-GP DDPB_AUXP
UMA AU38
2
DDPB_HPD HDMI_PCH_DET 57
LVDS
55 PCH_LVDSA_TXC# AV53 LVDSA_CLK#
55 PCH_LVDSA_TXC AV51 BD42 HDMI_DATA2#_C UMA1 2 C2001 SCD1U10V2KX-5GP HDMI_PCH_DATA2# 57,82
LVDSA_CLK DDPB_0N HDMI_DATA2_C C2002 SCD1U10V2KX-5GP
DDPB_0P BC42
HDMI_DATA1#_C
UMA1 2
C2003 SCD1U10V2KX-5GP
HDMI_PCH_DATA2 57,82
55 PCH_LVDSA_TX0# BB47 LVDSA_DATA#0 DDPB_1N BJ42
HDMI_DATA1_C
UMA1 2
HDMI_PCH_DATA1# 57,82
55 PCH_LVDSA_TX1# BA52 BG42 UMA1 2 HDMI_PCH_DATA1 57,82
Digital Display Interface

LVDSA_DATA#1 DDPB_1P HDMI_DATA0#_C C2005 SCD1U10V2KX-5GP
55 PCH_LVDSA_TX2# AY48 LVDSA_DATA#2 DDPB_2N BB40
HDMI_DATA0_C
UMA1 2
HDMI_PCH_DATA0# 57,82
+3.3V_RUN
AV47 LVDSA_DATA#3 DDPB_2P BA40
HDMI_CLK#_C
UMA1 2
HDMI_PCH_DATA0 57,82
DDPB_3N AW38
HDMI_CLK_C
UMA1 2
HDMI_PCH_CLK# 57,82
55 PCH_LVDSA_TX0 BB48 LVDSA_DATA0 DDPB_3P BA38 UMA1 2 HDMI_PCH_CLK 57,82
55 PCH_LVDSA_TX1 BA50 LVDSA_DATA1
Impedance:85 ohm 55 PCH_LVDSA_TX2 AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
AB49
Close to VGA
DDPC_CTRLDATA
4
3
2
1
RN2002 55 PCH_LVDSB_TXC# AP48

C LVDSB_CLK# C
UMA SRN2K2J-4-GP 55 PCH_LVDSB_TXC AP47 LVDSB_CLK DDPC_AUXN BE44
BD44
DDPC_AUXP
55 PCH_LVDSB_TX0# AY53
AT49
LVDSB_DATA#0 DDPC_HPD AV40 Impedance:85 ohm Impedance:100 ohm
55 PCH_LVDSB_TX1#
5
6
7
8
LCTRL_DATA LVDSB_DATA#1
55 PCH_LVDSB_TX2# AU52 LVDSB_DATA#2 DDPC_0N BE40
LCTRL_CLK AT53 BD40
LDDC_CLK_PCH LVDSB_DATA#3 DDPC_0P
DDPC_1N BF41
LDDC_DATA_PCH 55 PCH_LVDSB_TX0 AY51 BH41
LVDSB_DATA0 DDPC_1P
55 PCH_LVDSB_TX1 AT48 LVDSB_DATA1 DDPC_2N BD38
55 PCH_LVDSB_TX2 AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36
Close to ball <600mil
77 PCH_CRT_BLUE AA52 CRT_BLUE DDPD_CTRLCLK U50
77 PCH_CRT_GREEN AB53 CRT_GREEN DDPD_CTRLDATA U52
77 PCH_CRT_RED AD53 CRT_RED
Need Level Shift BC46
DDPD_AUXN
77 PCH_CRT_DDCCLK V51 CRT_DDC_CLK DDPD_AUXP BD46
5
6
7
8
77 PCH_CRT_DDCDATA V53 CRT_DDC_DATA DDPD_HPD AT38

RN2005
SRN150F-1-GP BJ40
UMA 77 PCH_CRT_HSYNC Y53 CRT_HSYNC
DDPD_0N
DDPD_0P BG40
77 PCH_CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
BG38
4
3
2
1
DDPD_1P
CRT
2.5V Tolerance CRT_IREF AD48 DDPD_2N BF37
BH37
DAC_IREF DDPD_2P
AB51 CRT_IRTN DDPD_3N BE36
1
B B
DDPD_3P BD36
R2007
IBEXPEAK-M-GP-NF
1KR2J-1-GP
2
<Core Design>
A A
Wistron Corporation
Title
PCH (LVDS/CRT/DDI)
Berry A00
5 4 3 2 1
5 4 3 2 1
RN2101
PCI_TRDY#
PCI_DEVSEL#
1
2
10
9 PCI_FRAME#
+3.3V_RUN SSID = PCH H40
U2001E
AD0
5 OF 10
NV_CE#0 AY9
INT_PIRQA# 3 8 PCI_REQ2# N34 BD1 +V_NVRAM_VCCQ
PCI_IRDY# INT_PIRQD# AD1 NV_CE#1
4 7 C44 AD2 NV_CE#2 AP15
+3.3V_RUN 5 6 PCI_SERR# A38 AD3 NV_CE#3 BD8 DMI Termination Voltage
1
C36 AD4
SRN8K2J-2-GP-U J34 AD5 NV_DQS0 AV9 NV_CLE Set to Vss when low. R2102
A40
D45
AD6 NV_DQS1 BG8 Set to Vcc when high. DY1KR2J-1-GP
AD7
E36 AP7
2
RN2103 AD8 NV_DQ0/NV_IO0
H48 AD9 NV_DQ1/NV_IO1 AP6
INT_PIRQH# 1 10 +3.3V_RUN E40 AT6 NV_CLE
INT_PIRQB# PCI_REQ1# AD10 NV_DQ2/NV_IO2
D 2 9 C40 AD11 NV_DQ3/NV_IO3 AT9 D
INT_PIRQF# 3 8 PCI_PLOCK# M48 BB1
PCI_REQ3# PCI_PERR# AD12 NV_DQ4/NV_IO4
4 7 M45 AD13 NV_DQ5/NV_IO5 AV6
+3.3V_RUN 5 6 PCI_REQ0# F53 BB3
AD14 NV_DQ6/NV_IO6
M40 AD15 NV_DQ7/NV_IO7 BA4
SRN8K2J-2-GP-U
NVRAM
M43 AD16 NV_DQ8/NV_IO8 BE4
J36 BB6 +V_NVRAM_VCCQ
+3.3V_RUN AD17 NV_DQ9/NV_IO9
K48 AD18 NV_DQ10/NV_IO10 BD6
+3.3V_RUN F40 BB7
AD19 NV_DQ11/NV_IO11
1
RN2102 C42 AD20 NV_DQ12/NV_IO12 BC8 Danbury Technology:
1 8 PCI_STOP# K46 BJ8 Disabled when Low. R2103
INT_PIRQE# AD21 NV_DQ13/NV_IO13
2
3
7
6 INT_PIRQC#
U2101 M51
J52
AD22 NV_DQ14/NV_IO14 BJ6
BG6
Enable when High. DY1KR2J-1-GP
INT_PIRQG# AD23 NV_DQ15/NV_IO15
4 5 5 1 K51
2
VCC A PCI_PLTRST# AD24 NV_ALE
SRN8K2J-4-GP 9,37,70,76,78,80 PLT_RST# 4
DY B 2
3
L34
F42
AD25 NV_ALE BD3
AY6 NV_CLE NV_ALE
Y GND AD26 NV_CLE
J40 AD27
G46 AD28
NL17SZ08DFT2G-GP F44 AU2 NV_RCOMP 1 TP2105 TPAD14-GP
AD29 NV_RCOMP
M47 AD30
PCI
1 2 H36 AD31 NV_RB# AV7
R2101 0R0402-PAD
1
J50 C/BE0# NV_WR#0_RE# AY8
BOOT BIOS Strap C2101
DY SC220P50V2KX-3GP
G42
H47
C/BE1# NV_WR#1_RE# AY5
2
C/BE2#
PCI_GNT#1 PCI_GNT#0 BOOT BIOS Location G34 C/BE3# NV_WE#_CK0 AV11 USB
NV_WE#_CK1 BF5
0 0 LPC INT_PIRQA# G38 PIRQA# Pair Device
INT_PIRQB# H51 PIRQB#
C 0 1 Reserved INT_PIRQC# B37 PIRQC# USBP0N H18 USB_PN0 77 0 USB2 (CRT Board) C
INT_PIRQD# A44 J18 USB_PP0 77
PIRQD# USBP0P
1 0 PCI USBP1N A18 USB_PN1 77 1 USB3 (CRT Board)
PCI_REQ0# F51 C18 USB_PP1 77
REQ0# USBP1P
1 1 SPI(Default) PCI_REQ1# A46 REQ1#/GPIO50 USBP2N N20 USB_PN2 76 2 WLAN (I/O Board)
PCI_REQ2# B45 P20 USB_PP2 76
REQ2#/GPIO52 USBP2P
PCI_REQ3# M53 REQ3#/GPIO54 USBP3N J20 3 X
USBP3P L20
TPAD14-GP TP2102 1 PCI_GNT0# F48 GNT0# USBP4N F20 USB_PN4 78 4 CARD READER
TPAD14-GP TP2103 1 PCI_GNT1# K45 G20 USB_PP4 78
GNT1#/GPIO51 USBP4P
RN2104 TPAD14-GP TP2104 1 PCI_GNT2# F36 GNT2#/GPIO53 USBP5N A20 USB_PN5 73 5 BLUETOOTH
USB_OC#2_3 1 10 PCI_GNT3# H53 C20 USB_PP5 73
+3.3V_ALW GNT3#/GPIO55 USBP5P
SMC_W AKE_SCI#_R 2 9 USB_OC#12_13
USBP6N M22 6 X
USB_OC#6_7 3 8 USB_OC#8_9 INT_PIRQE# B41 N22
PIRQE#/GPIO2 USBP6P
USB_OC#0_1 4 7 USB_OC#10_11 INT_PIRQF# K53 PIRQF#/GPIO3 USBP7N B21 7 X
5 6 USB_OC#4_5 INT_PIRQG# A36 D21
+3.3V_ALW PIRQG#/GPIO4 USBP7P
INT_PIRQH# A48 PIRQH#/GPIO5 USBP8N H22 USB_PN8 76 8 USB1 (I/O Board)
SRN8K2J-2-GP-U J22 USB_PP8 76
USBP8P
USB
TPAD14-GP TP2110 1 PCIRST# K6 PCIRST# USBP9N E22 USB_PN9 76 9 ESATA (I/O Board COMBO)
USBP9P F22 USB_PP9 76
R2105 PCI_SERR# E44 SERR# USBP10N A22 10 X
PCI_GNT3# PCI_PERR#
1
DY 2 E50 PERR# USBP10P C22
G24 USB_PN11 76 11 W-WAN (I/O Board)
4K7R2J-2-GP USBP11N
USBP11P H24 USB_PP11 76
PCI_IRDY# A42 IRDY# USBP12N L24 12 X
H44 PAR USBP12P M24
PCI_DEVSEL# F46 DEVSEL# USBP13N A24 USB_PN13 54 13 CAMERA
PCI_FRAME# C46 C24 USB_PP13 54
FRAME# USBP13P
B PCI_PLOCK# B
D49 PLOCK#
A16 swap override Strap/Top-Block B25 USB_RBIAS_PN 1 2
PCI_STOP# USBRBIAS# R2106
Swap Override jumper D41 STOP#
PCI_TRDY# C48 D25 22D6R2F-L1-GP
TRDY# USBRBIAS
PCI_GNT#3 Low = A16 swap TPAD14-GP TP2115 1 PCH_PME# M7 PME# USB_OC#0_1
override/Top-Block OC0#/GPIO59 N16 USB_OC#0_1 63
Swap Override enabled PCI_PLTRST# D5 J16 USB_OC#2_3
PLTRST# OC1#/GPIO40 USB_OC#4_5
High = Default OC2#/GPIO41 F16
70 PCLK_FW H 1 2 PCLK_FW H_R N52 L16 USB_OC#6_7
R2107 CLKOUT_PCI0 OC3#/GPIO42
23 CLK_PCI_FB 1 2 22R2J-2-GP CLK_PCI_FB_R P53 CLKOUT_PCI1 OC4#/GPIO43 E14 USB_OC#8_9 USB_OC#8_9 63
37 PCLK_KBC R2108 1 2 22R2J-2-GP PCLK_KBC_R P46 G16 USB_OC#10_11
R2109 22R2J-2-GP CLKOUT_PCI2 OC5#/GPIO9 USB_OC#12_13
P51 CLKOUT_PCI3 OC6#/GPIO10 F12
P48 T15 SMC_W AKE_SCI#_R
CLKOUT_PCI4 OC7#/GPIO14
2
EC2101
IBEXPEAK-M-GP-NF
DY SC4D7P50V2CN-1GP
1
KBC CLK EMI
A <Core Design> A
Wistron Corporation
Title
PCH (PCI/USB/NVRAM)
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
RN2201
FDI_PCH_TXP3 1 8 FDI_TXP3 8
FDI_PCH_TXN3 2 7 FDI_TXN3 8
FDI_PCH_TXN1
U2001C 3 OF 10 FDI_PCH_TXP1
3
4
UMA 6
5
FDI_TXN1
FDI_TXP1
8
8
BA18 FDI_PCH_TXN0
FDI_RXN0 FDI_PCH_TXN1 SRN0J-7-GP
8 DMI_CTX_PRXN0 BC24 DMI0RXN FDI_RXN1 BH17
8 DMI_CTX_PRXN1 BJ22 BD16 FDI_PCH_TXN2 RN2202
DMI1RXN FDI_RXN2 FDI_PCH_TXN3 FDI_PCH_TXN4
8 DMI_CTX_PRXN2 AW20 DMI2RXN FDI_RXN3 BJ16 1 8 FDI_TXN4 8
8 DMI_CTX_PRXN3 BJ20 BA16 FDI_PCH_TXN4 FDI_PCH_TXP4 2 7 FDI_TXP4 8
DMI3RXN FDI_RXN4 FDI_PCH_TXN5 FDI_PCH_TXP0
D
8 DMI_CTX_PRXP0 BD24
FDI_RXN5 BE14
BA14 FDI_PCH_TXN6 FDI_PCH_TXN0
3
4
UMA 6
5
FDI_TXP0
FDI_TXN0
8
8
D
DMI0RXP FDI_RXN6 FDI_PCH_TXN7
8 DMI_CTX_PRXP1 BG22 DMI1RXP FDI_RXN7 BC12
8 DMI_CTX_PRXP2 BA20 SRN0J-7-GP
DMI2RXP FDI_PCH_TXP0
8 DMI_CTX_PRXP3 BG20 BB18 RN2203
DMI3RXP FDI_RXP0 FDI_PCH_TXP1 FDI_PCH_TXP6
FDI_RXP1 BF17 1 8 FDI_TXP6 8
FDI_PCH_TXP2 FDI_PCH_TXN6
8
8
DMI_PTX_CRXN0
DMI_PTX_CRXN1
BE22
BF21
DMI0TXN FDI_RXP2 BC16
BG16 FDI_PCH_TXP3 FDI_PCH_TXN2
2
3
UMA 7
6
FDI_TXN6
FDI_TXN2
8
8
DMI1TXN FDI_RXP3 FDI_PCH_TXP4 FDI_PCH_TXP2
8 DMI_PTX_CRXN2 BD20 DMI2TXN FDI_RXP4 AW16 4 5 FDI_TXP2 8
8 DMI_PTX_CRXN3 BE18 BD14 FDI_PCH_TXP5
DMI3TXN FDI_RXP5 FDI_PCH_TXP6 SRN0J-7-GP
FDI_RXP6 BB14
8 DMI_PTX_CRXP0 BD22 BD12 FDI_PCH_TXP7 RN2204
DMI0TXP FDI_RXP7 FDI_PCH_TXN7
8 DMI_PTX_CRXP1 BH21 DMI1TXP 1 8 FDI_TXN7 8
R2201 FDI_PCH_TXP7
8
8
DMI_PTX_CRXP2
DMI_PTX_CRXP3
BC20
BD18
DMI2TXP
BJ14 FDI_INT_C 1 UMA 0R2J-2-GP
2 FDI_INT 8 FDI_PCH_TXP5
2
3
UMA 7
6
FDI_TXP7
FDI_TXP5
8
8
DMI3TXP FDI_INT FDI_PCH_TXN5 4 5 FDI_TXN5 8
DMI
FDI
BF13 FDI_FSYNC0_C
+1.05V_VTT FDI_FSYNC0 SRN0J-7-GP
BH25 DMI_ZCOMP
R2202 BH13 FDI_FSYNC1_C
DMI_IRCOMP_R FDI_FSYNC1
1 2 BF25 DMI_IRCOMP
BJ12 FDI_LSYNC0_C RN2205
49D9R2F-GP FDI_LSYNC0 FDI_LSYNC1_C 1 8 FDI_LSYNC1 8
FDI_LSYNC1_C FDI_FSYNC1_C
FDI_LSYNC1 BG14
FDI_LSYNC0_C
2
3
UMA 7
6
FDI_FSYNC1
FDI_LSYNC0
8
8
FDI_FSYNC0_C 4 5 FDI_FSYNC0 8
SRN0J-7-GP
C C
9,23 XDP_DBRESET# T6 SYS_RESET# WAKE# J12 PCIE_W AKE# 76
X02-20091222 +3.3V_ALW
M6 SYS_PWROK CLKRUN#/GPIO32 Y1 PM_CLKRUN# 37
R2204 RN2206
System Power Management

37 PM_PW ROK 1 2 PM_PW RGD X02-20091222 B17 PWROK
PM_BATLOW #_R 1 8
0R0402-PAD PM_RI# 2 7
TP2201 AC_PRESENT_EC 3 6
1 R2206 2 MEPW ROK K5 MEPWROK SUS_STAT#/GPIO61 P8 PM_SUS_STAT# 1 TPAD14-GP SUS_PW R_ACK 4 5
RN2207 0R0402-PAD
3 2
A00-20100204 SRN10KJ-6-GP
LAN_RST#1 PCH_SUSCLK
4 1 X02-20091224 A10 LAN_RST# SUSCLK/GPIO62 F3 1
R2209
2
0R0402-PAD
PCH_SUSCLK_2102 39
PCIE_W AKE# 1 2
SRN10KJ-5-GP 1 1 2 PCH_SUSCLK_KBC 37 R2210 1KR2J-1-GP
9 PM_DRAM_PW RGD X02-20091222
TPAD14-GP TP2206 D9 DRAMPWROK SLP_S5#/GPIO63 E4 PCH_SLP_S5# 1 R2211 10R2J-2-GP
TP2202
R2213 TPAD14-GP
37 PCH_RSMRST# 1 2 PM_RSMRST#_R C16 H7 PM_SLP_S4#_R 1 2 PM_SLP_S4# 37,50
0R0402-PAD RSMRST# SLP_S4# R2214 0R0402-PAD
R2215 R2217
37 SUS_PW R_DN_ACK 1 2 SUS_PW R_ACK M1 P12 PM_SLP_S3#_R 1 2 PM_SLP_S3# 37,42,47,50,51,89 PCH_RSMRST# 1 2
0R0402-PAD SUS_PWR_DN_ACK/GPIO30 SLP_S3# R2216 0R0402-PAD
9 PM_PW RBTN#_R
R2218 10KR2J-3-GP
37 PM_PW RBTN# 1 2 PM_PW RBTN#_R P5 PWRBTN# SLP_M# K8 SIO_SLP_M#_R 1 X02-20091222
0R0402-PAD TP2203TPAD14-GP
R2219
37 AC_PRESENT_EC 1 2 AC_PRESENT P7 N2 PM_SLP_DSW # 1
B 0R0402-PAD ACPRESENT/GPIO31 TP23 TP2204TPAD14-GP B
PM_BATLOW #_R A6 BJ10 H_PM_SYNC

BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 9
PM_RI# F14 F6 PM_SLP_LAN# 1

RI# SLP_LAN#/GPIO29 TP2205TPAD14-GP +3.3V_RUN
IBEXPEAK-M-GP-NF
PM_CLKRUN# 1 2
1
Option to " Disable " clkrun. R2221
DY R2220
10KR2J-3-GP 10KR2J-3-GP
Pulling it down will keep the clks running.
2
A <Core Design> A
Wistron Corporation
Title
PCH (DM I/FDI/PM)

Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
+3.3V_ALW
+3.3V_ALW
U2001B 2 OF 10
1
2
BG30 B9 PCH_GPIO11 25 TPM_ID1 2 1 RN2302
PERN1 SMBALERT#/GPIO11 R2305 10KR2J-3-GP
BJ30 PERP1 SRN2K2J-1-GP
BF29 H14 PCH_SMB_CLK
PETN1 SMBCLK LPD_SPI_INTR#
BH29 PETP1 2 1
C8 PCH_SMB_DATA R2311 10KR2J-3-GP
4
3
SMBDATA
D 76 PCIE_RXN2 AW30 PERN2 D
76 PCIE_RXP2
C2301 SCD1U10V2KX-5GP 1 2 PCIE_C_TXN2
BA30
BC30
PERP2 WLAN J14 TPM_ID1 PCH_SMB_CLK
76 PCIE_TXN2 C2302 SCD1U10V2KX-5GP 1 PCIE_C_TXP2 PETN2 SML0ALERT#/GPIO60
76 PCIE_TXP2 2 BD30 PETP2
C6 SML0_CLK PCH_SMB_DATA
SML0CLK SML0_CLK 9
AU30
SMBus
76 PCIE_RXN3 PERN3 +3.3V_ALW
AT30 G8 SML0_DATA
76 PCIE_RXP3 PERP3 SML0DATA SML0_DATA 9
C2303 SCD1U10V2KX-5GP 1 PCIE_C_TXN3
76 PCIE_TXN3 C2306 SCD1U10V2KX-5GP 1
2
2 PCIE_C_TXP3
AU32
AV32
PETN3 LAN
76 PCIE_TXP3 PETP3 LPD_SPI_INTR#
SML1ALERT#/GPIO74 M14
BA32 +3.3V_ALW
76 PCIE_RXN4 PERN4
4
3
4
3
BB32 E10 KBC_SCL1
76 PCIE_RXP4 PERP4 SML1CLK/GPIO58 KBC_SCL1 37
C2304 SCD1U10V2KX-5GP 1 PCIE_C_TXN4 RN2309 RN2301
76 PCIE_TXN4 2 BD32 PETN4 W-WAN
1
C2305 SCD1U10V2KX-5GP 1 2 PCIE_C_TXP4 BE32 G12 KBC_SDA1 SRN2K2J-1-GP SRN2K2J-1-GP
76 PCIE_TXP4 PETP4 SML1DATA/GPIO75 KBC_SDA1 37
R2308
PCI-E*
BF33 PERN5 UMA 10KR2J-3-GP
x01 change tolerant 20091117 BH33 T13 CL_CLK 1
1
2
1
2
PERP5 CL_CLK1
Controller
BG32 TP2302 TPAD14-GP
2
PETN5 CL_DATA 1 PEG_CLKREQ#_C
BJ32 PETP5 CL_DATA1 T11
TP2303 TPAD14-GP SML0_DATA KBC_SCL1
Link
1
BA34 T9 CL_RST# 1
PERN6 CL_RST1# TP2304 TPAD14-GP SML0_CLK KBC_SDA1 R2309
AW34 PERP6
BC34 PETN6 DIS 10KR2J-3-GP
BD34 PETP6 PEG_CLKREQ#_C
DY
H1 1 2 PEG_CLKREQ# 82
2
PEG_A_CLKRQ#/GPIO47 R2310 0R2J-2-GP
AT34 PERN7
AU34 PERP7
AU36 AD43 CLK_PCIE_VGA# CLK_PCIE_VGA# 80
PETN7 CLKOUT_PEG_A_N CLK_PCIE_VGA
AV36 PETP7 CLKOUT_PEG_A_P AD45 CLK_PCIE_VGA 80
C C
BG34 AN4 CLK_EXP_N +3.3V_RUN
PERN8 CLKOUT_DMI_N CLK_EXP_N 9
PEG
BJ34 AN2 CLK_EXP_P CLK_EXP_P 9
PERP8 CLKOUT_DMI_P RN2303
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. BG36 PETN8
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN BJ36 PETP8 2 3
CLKOUT_DP_N/CLKOUT_BCLK1_N AT1 1 4
CLKOUT_DP_P/CLKOUT_BCLK1_P AT3
AK48 SRN2K2J-1-GP
CLKOUT_PCIE0N
AK47 CLKOUT_PCIE0P
From CLK BUFFER

AW24 CLKIN_DMI# CLKIN_DMI# 7
PCIE_CLK_RQ0# CLKIN_DMI_N CLKIN_DMI
P9 PCIECLKRQ0#/GPIO73 CLKIN_DMI_P BA24 CLKIN_DMI 7
Q2301
AM43 AP3 CLK_CPU_BCLK# CLK_CPU_BCLK# 7 PCH_SMB_DATA 6 1
CLKOUT_PCIE1N CLKIN_BCLK_N PCH_SMBDATA 7,18,19,76
AM45 AP1 CLK_CPU_BCLK CLK_CPU_BCLK 7
CLKOUT_PCIE1P CLKIN_BCLK_P
5 2
PCIE_CLK_RQ1# U4 PCIECLKRQ1#/GPIO18
CLKIN_DOT_96N F18 CLK_DREF# 7 4 3
CLKIN_DOT_96P E18 CLK_DREF 7
76 CLK_PCIE_W LAN# AM47 2N7002EDW -GP
CLKOUT_PCIE2N
76 CLK_PCIE_W LAN AM48 CLKOUT_PCIE2P
AH13 CLK_PCIE_SATA# 7
84.27002.F3F
CLKIN_SATA_N/CKSSCD_N PCH_SMBCLK 7,18,19,76
76 W LAN_CLKREQ# N4 PCIECLKRQ2#/GPIO20 CLKIN_SATA_P/CKSSCD_P AH12 CLK_PCIE_SATA 7
PCH_SMB_CLK
76 CLK_PCIE_LAN# AH42 P41 CLK_PCH_14M CLK_PCH_14M 7

CLKOUT_PCIE3N REFCLK14IN
76 CLK_PCIE_LAN AH41 CLKOUT_PCIE3P
2 1 PCIE_CLK_RQ3# A8 J42 CLK_PCI_FB CLK_PCI_FB 21
B R2304 10KR2J-3-GP PCIECLKRQ3#/GPIO25 CLKIN_PCILOOPBACK B
DIS uses 0ohm 63.R0034.1DL

76 CLK_PCIE_W W AN# AM51 AH51 XTAL25_IN
AM53
CLKOUT_PCIE4N XTAL25_IN
AH53 XTAL25_OUT UMA uses 12pF 78.12034.1FL
76 CLK_PCIE_W W AN CLKOUT_PCIE4P XTAL25_OUT
76 W W AN_CLKREQ# M9 PCIECLKRQ4#/GPIO26 XCLK_RCOMP AF38 XCLK_RCOMP R2306 1 2 90D9R2F-1-GP +1.05V_VTT C2308 X01 2009/11/06
XTAL25_IN
AJ50 T45 CLK_PCH_GPIO64 1 TP2301 TPAD14-GP
2
COLAY
1
CLKOUT_PCIE5N CLKOUTFLEX0/GPIO64
2
AJ52 CLKOUT_PCIE5P SC12P50V2JN-3GP
R2303 X2301
PCIE_CLK_RQ5# H6 P43
UMA 1M1R2J-GP
UMA XTAL-25MHZ-96GP
Clock Flex
PCIECLKRQ5#/GPIO44 CLKOUTFLEX1/GPIO65
C2307
1
X01 20091118
1
XTAL25_OUT
AK53
AK51
CLKOUT_PEG_B_N CLKOUTFLEX2/GPIO66 T42 2
UMA
1
+3.3V_ALW CLKOUT_PEG_B_P
PEG_B_CLKRQ# CLK48_GPIO TP2307 TPAD14-GP SC12P50V2JN-3GP
P13 PEG_B_CLKRQ#/GPIO56 CLKOUTFLEX3/GPIO67 N50 1
RN2307 X01 2009/11/05
1 8 W W AN_CLKREQ#
2 7 PCIE_CLK_RQ0# IBEXPEAK-M-GP-NF
3 6 PEG_B_CLKRQ#
4 5 PCIE_CLK_RQ5#
SRN10KJ-6-GP
A
+3.3V_RUN <Core Design> A
RN2308
XDP_DBRESET#
4
3
5
6 W LAN_CLKREQ#
XDP_DBRESET# 9,22
Wistron Corporation
2 7 INT_SERIRQ 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
INT_SERIRQ 24,37
1 8 PCIE_CLK_RQ1# Taipei Hsien 221, Taiwan, R.O.C.
SRN10KJ-6-GP Title
PCH (PCI-E/SMBUS/CLOCK/CL)
Berry A00
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1 +RTC_CELL
SSID = PCH
1 2 PCH_RTCX2 R2401
R2402 10MR2J-L-GP 1 2
INTVRMEN- Integrated SUS
20KR2J-L2-GP
X2401 1.1V VRM Enable
1
C2402
SC1U6D3V2KX-GP High - Enable internal VRs
1 4
2
SC15P50V2JN-2-GP
1
1
U2001A 1 OF 10 LPC_LAD[0..3]
C2403
D LPC_LAD[0..3] 37,70 D
2 3 C2401
SC15P50V2JN-2-GP PCH_RTCX1 B13 D33 LPC_LAD0
2
2
+RTC_CELL PCH_RTCX2 RTCX1 FWH0/LAD0 LPC_LAD1
D13 RTCX2 FWH1/LAD1 B33
X-32D768KHZ-65-GP C32 LPC_LAD2
R2403 FWH2/LAD2 LPC_LAD3
FWH3/LAD3 A32
PCH_RTCRST#
82.30001.A41 1 2 C14 RTCRST#
C34
FWH4/LFRAME# LPC_LFRAME# 37,70
2
20KR2J-L2-GP SRTCRST# D17 SRTCRST#
1
C2404 G2401 R2407
X01 X01 A34
RTC
LPC
SC1U6D3V2KX-GP SM_INTRUDER# LDRQ0#
GAP-OPEN 2 1 A16 INTRUDER# LDRQ1#/GPIO23 F34
1M1R2J-GP
2
+RTC_CELL 1 2 PCH_INTVRMEN A14 AB9 INT_SERIRQ 23,37
1
R2404 330KR2F-L-GP INTVRMEN SERIRQ
ACZ_BIT_CLK A30
x01 Change tolerant 20091117
HDA_BCLK
SATA0RXN AK7 SATA_RXN0_C 59
ACZ_SYNC_R
X01 20091118 layout swap D29 HDA_SYNC SATA0RXP AK6
AK11 SATA_TXN0_C C2409 1 2 SCD01U16V2KX-3GP
SATA_RXP0_C 59
HDD
SATA0TXN SATA_TXN0 59
P1 AK9 SATA_TXP0_C C2410 1 2 SCD01U16V2KX-3GP SATA_TXP0 59
30 ACZ_SPKR SPKR SATA0TXP
RN2403
1 4 ACZ_SYNC_R ACZ_RST#_R C30
30 PCH_AZ_CODEC_SYNC ACZ_SDATAOUT_R HDA_RST#
30 PCH_SDOUT_CODEC 2 3 SATA1RXN AH6 SATA_RXN1_C 59
AH5
SRN33J-5-GP-U 30 PCH_SDIN_CODEC G30 HDA_SDIN0
SATA1RXP
SATA1TXN AH9 SATA_TXN1_C C2405 1
SATA_TXP1_C C2406 1
2 SCD01U16V2KX-3GP
SATA_RXP1_C 59
SATA_TXN1 59 ODD
SATA1TXP AH8 2 SCD01U16V2KX-3GP SATA_TXP1 59
F30 HDA_SDIN1
RN2402 AF11
C SRN33J-5-GP-U SATA2RXN C
E32 AF9
IHDA
ACZ_RST#_R HDA_SDIN2 SATA2RXP
30 PCH_AZ_CODEC_RST# 1 4 SATA2TXN AF7
2 3 ACZ_BIT_CLK F32 AF6
30 PCH_AZ_CODEC_BITCLK HDA_SDIN3 SATA2TXP
SATA3RXN AH3
ACZ_SDATAOUT_R B29 AH1
HDA_SDO SATA3RXP
SATA3TXN AF3
SATA3TXP AF1
37 ME_UNLOCK# H32
SATA
HDA_DOCK_EN#/GPIO33
SATA4RXN AD9 SATA_RXN4_C 76
J30 AD8
HDA_DOCK_RST#/GPIO13 SATA4RXP
SATA4TXN AD6 SATA_TXN4_C C2407 1
SATA_TXP4_C C2408 1
2 SCD01U16V2KX-3GP
SATA_RXP4_C 76
SATA_TXN4 76 ESATA
NO REBOOT STRAP SATA4TXP AD5 2 SCD01U16V2KX-3GP SATA_TXP4 76
+3.3V_RUN
No Reboot Strap R23 TPAD14-GP TP2404 1 PCH_JTAG_TCK M3 AD3
JTAG_TCK SATA5RXN
SATA5RXP AD1
2 ACZ_SPKR Low = Default TPAD14-GP TP2405 PCH_JTAG_TMS
1
R2410 DY 1KR2J-1-GP HDA_SPKR High = No Reboot
1 K3 JTAG_TMS SATA5TXN AB3
AB1
TPAD14-GP TP2406 PCH_JTAG_TDI SATA5TXP +1.05V_VTT
1 K1 JTAG_TDI
JTAG
TPAD14-GP TP2407 1 PCH_JTAG_TDO J2 AF16
JTAG_TDO SATAICOMPO R2412
TPAD14-GP TP2408 1 PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2
TRST# SATAICOMPI +3.3V_RUN
37D4R2F-GP
For EMI PCH_SPI_CLK R2413 1 2 15R2J-GP SPI_CLK_R BA2
62 PCH_SPI_CLK SPI_CLK
4
3
PCH_AZ_CODEC_BITCLK 62 PCH_SPI_CS0# PCH_SPI_CS0# R2414 1 2 15R2J-GP SPI_CS#0_R AV3 RN2401
B PCH_AZ_CODEC_RST# SPI_CS0# B
SRN10KJ-5-GP
SPI_CS1#
R2415
1
DY 2
0R2J-2-GP
AY3 SPI_CS1# SATALED# T3 SATA_LED# 66
1
2
2
EC2402 DY 62 PCH_SPI_DO PCH_SPI_DO R2416 1 2 15R2J-GP SPI_MOSI_R AY1 Y9 SATA_DET#0_R

SCD1U10V2KX-5GP EC2401 SPI_MOSI SATA0GP/GPIO21
DY
SPI
SC22P50V2JN-4GP 62 PCH_SPI_DI PCH_SPI_DI AV1 V1 SATA_DET#1_R
1
SPI_MISO SATA1GP/GPIO19
IBEXPEAK-M-GP-NF
A <Core Design> A
Wistron Corporation
Title
PCH (SPI/RTC/LPC/SATA/IHDA)
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
U2001F 6 OF 10
S_GPIO Y3 AH45
BMBUSY#/GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
37 SIO_EXT_SCI# SIO_EXT_SCI# C38 TACH1/GPIO1
PCH_GPIO6 D37 TACH2/GPIO6
D
CLKOUT_PCIE7N AF48 D
MISC
SIO_EXT_W AKE# J32 AF47
37 SIO_EXT_W AKE# TACH3/GPIO7 CLKOUT_PCIE7P
SIO_EXT_SMI# F10
37 SIO_EXT_SMI# GPIO8
1
C2501 PCH_GPIO12
SC47P50V2JN-3GP DY K9 LAN_PHY_PWR_CTRL/GPIO12 A20GATE U2 SIO_A20GATE 37
2
HOST_ALTERT#1 T7 GPIO15
DGPU_HOLD_RST# AA2 AM3 BCLK_CPU_N 9
SATA4GP/GPIO16 CLKOUT_BCLK0_N/CLKOUT_PCIE8N +1.05V_VTT
PCH_GPIO17 F38 AM1 BCLK_CPU_P 9
TACH0/GPIO17 CLKOUT_BCLK0_P/CLKOUT_PCIE8P
2
PCH_GPIO22 Y7 BG10
SCLOCK/GPIO22 PECI H_PECI 9
GPIO
R2504
1
PCH_GPIO24 H10 T1 SIO_RCIN# 37 56R2J-4-GP
C2502 GPIO24 RCIN#
SC47P50V2JN-3GP DY TPAD14-GP TP2502 1 PCH_GPIO27 AB12 BE10 H_PW RGD 9,42
1
GPIO27 PROCPWRGD
CPU
+3.3V_RUN PCH_GPIO28 V13 BD10 PCH_THERMTRIP_R 1 2
GPIO28 THRMTRIP# H_THERMTRIP# 9,37,42,82
RN2502 R2506 54D9R2F-L1-GP
PCH_GPIO22 1 10 STP_PCI# M11 STP_PCI#/GPIO34
PCH_GPIO37 2 9 PCH_GPIO38 Placed Within 2" from PCH
PCH_GPIO36 3 8 DGPU_HOLD_RST# CLK_SATA_OE# V6
PCH_GPIO48 S_GPIO SATACLKREQ#/GPIO35
4 7
2
5 6 PCH_TEMP_ALERT#_C PCH_GPIO36 AB7 SATA2GP/GPIO36 TP1 BA22
SRN10KJ-L3-GP R2508 PCH_GPIO37 AB13 AW22

+3.3V_RUN 10KR2J-3-GP SATA3GP/GPIO37 TP2
C PCH_GPIO38 V3 BB22 C
1
SLOAD/GPIO38 TP3
PCH_GPIO39 P3 AY45
SDATAOUT0/GPIO39 TP4
PCH_GPIO45 H3 AY46
PCIECLKRQ6#/GPIO45 TP5
9 S3_RST_GATE# F1 PCIECLKRQ7#/GPIO46 TP6 AV43

1 2
C2503 SCD047U16V2KX-1-GP PCH_GPIO48 AB6 AV45
+3.3V_RUN SDATAOUT1/GPIO48 TP7
37 PCH_TEMP_ALERT# 1 R2510 2 PCH_TEMP_ALERT#_C AA4 SATA5GP/GPIO49 TP8 AF13
0R0402-PAD
RN2503 PCH_GPIO57 F8 M18
GPIO57 TP9
PCH_GPIO39 4 1 X02-20091222
STP_PCI# 3 2 N18
SRN100KJ-6-GP TP10
A4 VSS_NCTF_1 TP11 AJ24
A49
NCTF
VSS_NCTF_2
RSVD
TPAD14-GP TP2503 1 PCH_NCTF_1 A5 AK41
VSS_NCTF_3 TP12
RN2504 A50
PCH_GPIO17 VSS_NCTF_4
1 8 A52 VSS_NCTF_5 TP13 AK42
PCH_GPIO6 2 7 A53
SIO_EXT_SCI# VSS_NCTF_6
3 6 B2 VSS_NCTF_7 TP14 M32
SIO_EXT_W AKE# 4 5 B4 VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32
SRN10KJ-6-GP B53 VSS_NCTF_10
BE1 VSS_NCTF_11 TP16 M30
BE53 VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
B +3.3V_ALW B
BF53 VSS_NCTF_14
BH1 VSS_NCTF_15 TP18 H12
BH2 VSS_NCTF_16
PCH_GPIO24 2
R2515 DY 1
100KR2J-1-GP
BH52
BH53
VSS_NCTF_17 TP19 AA23
VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
RN2501 BJ49
PCH_GPIO12 TPAD14-GP TP2504 PCH_NCTF_2 VSS_NCTF_22
1 10 1 BJ5 VSS_NCTF_23 NC_3 AB42
SIO_EXT_SMI# 2 9 S3_RST_GATE# BJ50
PCH_GPIO28 PCH_GPIO45 TPAD14-GP TP2505 PCH_NCTF_3 VSS_NCTF_24
3 8 1 BJ52 VSS_NCTF_25 NC_4 AB41
HOST_ALTERT#1 4 7 PCH_GPIO11 23 BJ53
PCH_GPIO57 VSS_NCTF_26
5 6 D1 VSS_NCTF_27 NC_5 T39
D2 VSS_NCTF_28
SRN10KJ-L3-GP D53 VSS_NCTF_29 INIT3_3V# TP2506TPAD14-GP
E1 VSS_NCTF_30 INIT3_3V# P6 1
+3.3V_ALW TPAD14-GP TP2507 1 PCH_NCTF_4 E53 VSS_NCTF_31
TP24 C10
IBEXPEAK-M-GP-NF
A <Core Design> A
Wistron Corporation
Title
PCH (GPIO/CPU)
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH +3.3V_RUN
1
DIS 2
R2601 0R2J-2-GP
+1.05V_VTT
U2001G POWER 7 OF 10 69mA
1.524A AB24 VCCCORE VCCADAC AE50 +VCCA_DAC_1_2
1
AB26 C2603 C2604 C2605 +3.3V_CRT_LDO
VCCCORE
SCD01U16V2KX-3GP
SCD1U10V2KX-5GP
C2602 C2601 AB28 VCCCORE VCCADAC AE52
UMA
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP DY SC1U6D3V2KX-GP
D AD26
UMA UMA UMA2 D
2
VCCCORE
CRT
AD28 AF53 1 2 1
2
VCCCORE VSSA_DAC L2602 HCB1608KF-181-GP R2602 0R2J-2-GP
AF26 VCCCORE
VCC CORE
AF28 VCCCORE VSSA_DAC AF51
x01 change tolerant 20091117 AF30
AF31
VCCCORE
VCCCORE
AH26 VCCCORE
AH28 +3.3V_RUN
VCCCORE +3VS_VCCA_LVD
AH30
AH31
VCCCORE
AH38 2
UMA1 300mA
VCCCORE VCCALVDS C2606 R2603 0R3J-0-U-GP
AJ30 VCCCORE DIS
+1.05V_VTT
AJ31 VCCCORE VSSA_LVDS AH39 1
R2604
2
0R2J-2-GP
1
DY
2
+1.8V_RUN
SCD1U10V2KX-5GP
AP43 +1.8VS_VCCTX_LVDS 1
UMA2 59mA
VCCTX_LVDS
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
AP45 R2611 0R5J-5-GP
VCCTX_LVDS
1
AT46 R2605 C2607 C2608
LVDS
VCCTX_LVDS
AK24 VCCIO VCCTX_LVDS AT45
DY C2609 X01 Change location-20091116
SC10U6D3V5MX-3GP
DIS 3.3V CRT LDO
0R2J-2-GP
2
TP2602
UMA UMA
1 TPAD14-GP VCCAPLLEXP BJ24
1
VCCAPLLEXP +5V_RUN +3.3V_CRT_LDO
VCC3_3 AB34
U2601
AN20 AB35 +3.3V_RUN
VCCIO VCC3_3
AN22 3 4
357mA
HVCMOS
VCCIO VIN VOUT
AN23
AN24
VCCIO VCC3_3 AD35 2
1
GND DY 5
VCCIO EN NC#5
1
AN26 C2611
VCCIO
1
+1.05V_VTT SCD1U10V2KX-5GP C2613
C
AN28 VCCIO C2612 DY RT9198-33PBG-GP SC1U6D3V2KX-GP C
3.208A x01 change tolerant 20091117 BJ26 DY
2
VCCIO SC1U10V2KX-1GP
BJ28
2
VCCIO
AT26 VCCIO Second 74.09091.H3F
1
C2614 C2615 C2616 C2617 C2618 AT28 VCCIO

SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
UMA UMA AU26 VCCIO +1.8V_RUN

SC10U6D3V5KX-1GP
AU28 x01 change tolerant 20091117

2
VCCIO
AV26
AV28
VCCIO
VCCIO VCCVRM AT24 35mA
AW26 VCCIO X02-20091222
AW28 VCCIO +1.05V_VTT
DMI
BA26 VCCIO VCCDMI AT16 R2606
BA28 +1.05VS_VCC_DMI
BB26
BB28
VCCIO
VCCIO VCCDMI AU16 1 2 61mA +1.8V_RUN +3.3V_RUN
VCCIO
1
BC26 C2619 0R0402-PAD
VCCIO
1
PCI E*
BC28 VCCIO A00-20100204
SC1U6D3V2KX-GP R2607
BD26
DY R2608
2
+3.3V_RUN VCCIO
x01 change tolerant 20091117 BD28 VCCIO +V_NVRAM_VCCQ
0R0402-PAD 0R2J-2-GP
BE26 VCCIO VCCPNAND AM16
BE28 AK16
156mA
2
VCCIO VCCPNAND
BG26 VCCIO VCCPNAND AK20
1
C2621 BG28 AK19

VCCIO VCCPNAND
1
SCD1U10V2KX-5GP BH27 AK15 C2620
VCCIO VCCPNAND SCD1U10V2KX-5GP
AK13
2
VCCPNAND
AN30 AM12
2
VCCIO VCCPNAND
NAND / SPI
AN31 VCCIO VCCPNAND AM13

VCCPNAND AM15
+3.3V_RUN
B
357mA AN35 VCC3_3 X02-20091222 B
1
VCCAFDI_VRM AT22 VCCVRM[1] R2609
+1.05V_VTT TP2601 1 VCCFDIPLL
TPAD14-GP
BJ18 VCCFDIPLL VCCME3_3 AM8
AM9
85mA 0R0402-PAD
VCCME3_3
FDI
AM23 AP11
2
VCCIO VCCME3_3 PCH_VCCME3_3
VCCME3_3 AP9
1
C2623
SCD1U10V2KX-5GP
IBEXPEAK-M-GP-NF
2
X02-20091222
+1.8V_RUN
R2610
VCCAFDI_VRM 1 2
0R0402-PAD
A <Core Design> A
Wistron Corporation
Title
PCH (POWER1)
Berry A00
5 4 3 2 1
5 4 3 2 1
+1.05V_VTT SSID = PCH

U2001J POWER 10 OF 10
TP2701 1 VCCACLK AP51 V24

TPAD14-GP VCCACLK VCCIO
VCCIO V26
1
AP53 Y24 C2705
VCCACLK VCCIO SC1U6D3V2KX-GP
VCCIO Y26 DY
2
AF23 V28 +3.3V_ALW
VCCLAN VCCSUS3_3
VCCSUS3_3 U28
D
AF24 VCCLAN VCCSUS3_3 U26
U24
x01 change tolerant 20091117 D
VCCSUS3_3
VCCSUS3_3 P28
1
DCPSUSBYP Y20 P26 C2706
DCPSUSBYP VCCSUS3_3 SCD1U10V2KX-5GP
VCCSUS3_3 N28
1
C2703 N26
2
SCD1U10V2KX-5GP VCCSUS3_3
AD38 VCCME VCCSUS3_3 M28
M26
2
VCCSUS3_3
x01 change tolerant 20091117 AD39 L28
USB
VCCME VCCSUS3_3
VCCSUS3_3 L26
AD41 VCCME VCCSUS3_3 J28
+1.05V_VTT J26
1.998A AF43 VCCME
VCCSUS3_3
VCCSUS3_3 H28
H26
VCCSUS3_3
AF41 VCCME VCCSUS3_3 G28
1
SC1U6D3V2KX-GP
C2707 C2704 C2708 G26
SC10U6D3V5KX-1GP VCCSUS3_3 +3.3V_ALW
DY AF42 F28
SC10U6D3V5MX-3GP
VCCME VCCSUS3_3
F26
2
VCCSUS3_3 +3.3V_ALW
V39 VCCME VCCSUS3_3 E28
E26
Clock and Miscellaneous

VCCSUS3_3
V41 VCCME VCCSUS3_3 C28
C26
VCCSUS3_3
2
V42 B27 C2709 +3.3V_RUN
VCCME VCCSUS3_3 SCD1U10V2KX-5GP D2701
VCCSUS3_3 A28
X01 20091121 Y39 A26 CH751H-40PT-GP
2
VCCME VCCSUS3_3
1
C2710
+1.05V_VTT SC1U6D3V2KX-GP DY Y41 U23 +1.05V_VTT
L2702
1
VCCME VCCSUS3_3
2
2
1 2 +1.05VS_VCCA_A_DPL Y42 V23 +5V_ALW D2702
IND-10UH-218-GP VCCME VCCIO
CH751H-40PT-GP
1
C +5VALW _PCH_VCC5REFSUS C
C2711 C2712
x01 change tolerant V5REF_SUS F24
R2702
1 2
10R2J-2-GP
DY
1
1
SC10U6D3V5MX-3GP SC1U6D3V2KX-GP 20091118 +VCCRTCEXT V9
2
DCPRTC C2713 +5V_RUN

1
C2714 +1.8V_RUN SC1U10V2KX-1GP
2
SCD1U10V2KX-5GP K49 +5VS_PCH_VCC5REF 1 2
L2703 V5REF
AU24 R2701 10R2J-2-GP
2
VCCVRM
PCI/GPIO/LPC
1 2 +1.05VS_VCCA_B_DPL
1
IND-10UH-218-GP J38
VCC3_3
1
BB51 C2715
C2716
DY C2717 72mA +1.05VS_VCCA_A_DPL BB53
VCCADPLLA
L38 SC1U10V2KX-1GP
2
SC10U6D3V5MX-3GP VCCADPLLA VCC3_3 +3.3V_RUN
SC1U6D3V2KX-GP
2
M36
73mA +1.05VS_VCCA_B_DPL BD51
BD53
VCCADPLLB
VCC3_3
N36
VCCADPLLB VCC3_3
1
C2718
+1.05V_VTT AH23 P36 SCD1U10V2KX-5GP
VCCIO VCC3_3
x01 change tolerant 20091117 AJ35
2
VCCIO
AH35 VCCIO VCC3_3 U35
+3.3V_RUN
1
C2720 C2721 C2722

SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP
AF34 VCCIO
AD13
VCC3_3
AH34
2
VCCIO
1
C2719
AF32 SCD1U10V2KX-5GP
VCCIO VCCSATAPLL TP2702
AK3 1
2
VCCSATAPLL TPAD14-GP
V12 DCPSST VCCSATAPLL AK1
+VCCSST
B +1.05V_VTT B
+1.05VALW _INT_VCCSUS
x01 change tolerant 20091117 Y22 DCPSUS
AH22
VCCIO
1
C2726
1
C2725 SCD1U10V2KX-5GP +1.8V_RUN C2727
SCD1U10V2KX-5GP P18 AT20 SC1U6D3V2KX-GP
2
VCCSUS3_3 VCCVRM
2
U19
SATA
+3.3V_ALW VCCSUS3_3
PCI/GPIO/LPC
AH19
163mA U20 VCCSUS3_3
VCCIO
AD20
VCCIO
1
C2728 U22
SCD1U10V2KX-5GP VCCSUS3_3
VCCIO AF22
+3.3V_RUN
2
VCCIO AD19
V15 VCC3_3 VCCIO AF20
VCCIO AF19
1
C2729 V16 AH20

SCD1U10V2KX-5GP VCC3_3 VCCIO
Y16 AB19
2
VCC3_3 VCCIO
VCCIO AB20
+1.05V_VTT
x01 change tolerant 20091117 VCCIO AB22
AD22 +1.05V_VTT
1mA AT18 V_CPU_IO
VCCIO
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AA34
CPU
VCCME
1
C2730 C2731 C2732 Y34

SC10U6D3V5KX-1GP VCCME
AU18 V_CPU_IO VCCME Y35
AA35 X02-20091222
2
VCCME
A
+RTC_CELL
6mA <Core Design> A
RTC
A12 L30 +VCCSUSHDA 1 R2703 2 +3.3V_ALW

VCCRTC VCCSUSHDA
HDA
0R0402-PAD
2mA Wistron Corporation
1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
IBEXPEAK-M-GP-NF C2733 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1
C2734 C2735 Taipei Hsien 221, Taiwan, R.O.C.

SC1U6D3V2KX-GP
2
Title
2
PCH (POWER2)
x01 change tolerant 20091117 Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH U2001I 9 OF 10

AY7 VSS VSS H49
B11 VSS VSS H5
B15 VSS VSS J24
B19 VSS VSS K11
B23 VSS VSS K43
B31 VSS VSS K47
B35 VSS VSS K7
B39 VSS VSS L14
B43 VSS VSS L18
B47 VSS VSS L2
D B7 VSS VSS L22 D
U2001H 8 OF 10 BG12 L32
VSS VSS
AB16 VSS BB12 VSS VSS L36
BB16 VSS VSS L40
AA19 VSS VSS AK30 BB20 VSS VSS L52
AA20 VSS VSS AK31 BB24 VSS VSS M12
AM19 VSS VSS AK34 BB34 VSS VSS M20
AA24 VSS VSS AK35 BB38 VSS VSS N38
AA31 VSS VSS AK49 BC10 VSS VSS M46
AA32 VSS VSS AK5 BC14 VSS VSS M49
AB11 VSS VSS AK8 BC18 VSS VSS M5
AB15 VSS VSS AL2 BC2 VSS VSS M8
AB23 VSS VSS AL52 BC22 VSS VSS N24
AB30 VSS VSS AM11 BC32 VSS VSS P11
AB31 VSS VSS BB44 BC36 VSS VSS AD15
AB32 VSS VSS AD24 BC40 VSS VSS P22
AB47 VSS VSS AM24 BH9 VSS VSS P34
AB5 VSS VSS AM26 BD48 VSS VSS P42
AB8 VSS VSS AM28 BD49 VSS VSS P45
AC2 VSS VSS BA42 BD5 VSS VSS P47
AC52 VSS VSS AM30 BE12 VSS VSS R2
AD11 VSS VSS AM31 BE16 VSS VSS R52
AD12 VSS VSS AM32 BE20 VSS VSS T12
C AD16 AM34 BE24 T41 C
VSS VSS VSS VSS
AD34 VSS VSS AU20 BE46 VSS VSS U30
AU22 VSS VSS AM46 BE48 VSS VSS U31
AD42 VSS VSS AV22 BE50 VSS VSS U32
AD46 VSS VSS AM49 BE6 VSS VSS U34
AD49 VSS VSS AM7 BE8 VSS VSS P38
AD7 VSS VSS AA50 BF3 VSS VSS V11
AE2 VSS VSS BB10 BF49 VSS VSS P16
AE4 VSS VSS AN32 BF51 VSS VSS V19
AF12 VSS VSS AN50 BG18 VSS VSS V20
Y13 VSS VSS AN52 BG24 VSS VSS V22
AH49 VSS VSS AP12 BG4 VSS VSS V30
AU4 VSS VSS AP42 BG50 VSS VSS V31
AF35 VSS VSS AP46 BH11 VSS VSS V32
AP13 VSS VSS AP49 BH15 VSS VSS V34
AN34 VSS VSS AP5 BH19 VSS VSS V35
AF45 VSS VSS AP8 BH23 VSS VSS V38
AF46 VSS VSS AR2 BH31 VSS VSS V43
AF49 VSS VSS AR52 BH35 VSS VSS V45
AF5 VSS VSS AT11 BH39 VSS VSS V46
AF8 VSS VSS BA12 BH43 VSS VSS V47
AG2 VSS VSS AH48 BH47 VSS VSS V49
AG52 VSS VSS AT32 BH7 VSS VSS V5
AH11 VSS VSS AT36 C12 VSS VSS V7
AH15 VSS VSS AT41 C50 VSS VSS V8
B B
AH16 VSS VSS AT47 D51 VSS VSS W2
AH24 VSS VSS AT7 E12 VSS VSS W52
AH32 VSS VSS AV12 E16 VSS VSS Y11
AV18 VSS VSS AV16 E20 VSS VSS Y12
AJ19 VSS VSS AV34 E38 VSS VSS Y28
AJ28 VSS VSS AV8 F49 VSS VSS Y46
AJ32 VSS VSS AW14 F5 VSS VSS P49
AJ34 VSS VSS AW18 G10 VSS VSS Y5
AT5 VSS VSS AW2 G14 VSS VSS Y6
AJ4 VSS VSS BF9 G18 VSS VSS Y8
AK12 VSS VSS AW32 G2 VSS VSS P24
AM41 VSS VSS AW36 G22 VSS VSS T43
AN19 VSS VSS AW40 G32 VSS VSS AD51
AK26 VSS VSS AW52 G36 VSS VSS AT8
AK22 VSS VSS AY11 G40 VSS VSS AD47
AK23 VSS VSS AY43 G44 VSS VSS Y47
AK28 VSS VSS AY47 G52 VSS VSS AT12
AF39 VSS VSS AM6
IBEXPEAK-M-GP-NF H16 AT13
VSS VSS
H20 VSS VSS AM5
A H30 VSS VSS AK45 <Core Design> A
H34 VSS VSS AK39
H38 VSS VSS AV14
H42 VSS Wistron Corporation
IBEXPEAK-M-GP-NF Title
PCH (VSS)
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = AUDIO
+AVDD +5V_RUN
X02-20091222
D +3.3V_RUN D
+3.3V_RUN Close to codec R3002
1 2
Close to codec 0R0603-PAD X02-20091222
AUD_DVDDCORE C3005 +5V_RUN
+PVDD
SCD1U10V2KX-5GP
1
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C3001 R3003
2
C3002
C3003
C3004
SC10U6D3V5MX-3GP C3006 1 2
0R0603-PAD
2
U3001
SC1U10V2KX-1GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-5GP
SC1U10V2KX-1GP
C3009
C3008
C3010
1 27 R3004
DVDD_CORE AVDD
38 1 2
AVDD AUD_AGND 0R0603-PAD
9
2
PCH_AZ_CODEC_BITCLK DVDD
39
PVDD
3 45
DVDD_IO PVDD
13 AUD_SENSE_A
SENSE_A
1
PCH_AZ_CODEC_BITCLK 6 14 AUD_SENSE_B AUD_AGND

C3007 24 PCH_AZ_CODEC_BITCLK HDA_BITCLK SENSE_B
DY X01 Change 0603 part-20091116
SC4D7P50V2CN-1GP R3001 1 2 33R2J-2-GP PCH_SDIN_CODEC_C0 8
2
24 PCH_SDIN_CODEC HDA_SDI AUD_EXT_MIC_L C3021

28 2 1 SC1U10V3KX-3GP MIC_IN_L 60
PCH_SDOUT_CODEC HP0_PORT_A_L AUD_EXT_MIC_R C3022
5 29 2 1 SC1U10V3KX-3GP MIC_IN_R 60
24 PCH_SDOUT_CODEC HDA_SDO HP0_PORT_A_R AUD_VREFOUT_B
23 AUD_VREFOUT_B 60
PCH_AZ_CODEC_SYNC VREFOUT_A_OR_F
10
24 PCH_AZ_CODEC_SYNC HDA_SYNC AUD_HP1_JACK_L R3005 1
31 2 60D4R2F-GP
PCH_AZ_CODEC_RST# HP1_PORT_B_L AUD_HP1_JACK_R R3006 1 AUD_HP1_JACK_L2 60
11 32 2 60D4R2F-GP
+3.3V_RUN 24 PCH_AZ_CODEC_RST# HDA_RST# HP1_PORT_B_R AUD_HP1_JACK_R2 60
close to audio jack
19 AUD_INT_MIC_R_L 1 2
PORT_C_L INT_MIC_L_R 60
20 C3011 SC1U10V3KX-3GP Check
PORT_C_R AUD_VREFOUT_C
VREFOUT_C
24 1 2 x01 change tolerant 20091117
1
TPAD14-GP TP3001 1 AUD_DMIC_CLK 2 R3007 2K2R2J-2-GP

R3008 TPAD14-GP TP3002 AUD_DMIC_IN0 DMIC_CLK/GPIO1 AUD_SPK_L+ R3009
1 4 DMIC0/GPIO2 SPKR_PORT_D_L+ 40 AUD_SPK_L+ 60 From SB
10KR2J-3-GP 41 AUD_SPK_L- C3012 120KR2J-L-GP
SPKR_PORT_D_L- AUD_SPK_L- 60 SB_SPKR_R
46 2 1 SCD1U10V2KX-5GP 1 2 ACZ_SPKR 24
DMIC1/GPIO0/SPDIF_OUT_1 AUD_SPK_R-
C 43 C
2
SPKR_PORT_D_R- AUD_SPK_R+ AUD_SPK_R- 60 KBC_BEEP_R 1

48 44 2 1 SCD1U10V2KX-5GP 2 KBC_BEEP 37
AMP_MUTE# SPDIF_OUT_0 SPKR_PORT_D_R+ AUD_SPK_R+ 60 R3010
2
AMP_MUTE# 47 15 C3013 470KR2J-2-GP From EC
37 AMP_MUTE# EAPD PORT_E_L G3001
16
PORT_E_R
DUMMY-C2
AUD_VREFOUT_B PUMP_CAPN 17
PORT_F_L AUD_PC_BEEP
35 CAP- PORT_F_R 18
1
C3014
1
SC2D2U10V3KX-1GP
PC_BEEP 12 AUD_PC_BEEP
1
36
2
CAP+
C3023
SC1U10V2KX-1GP
PUMP_CAPP
MONO_OUT
25 Trace width>15 mils
2
X01 20091117 7
DVSS
33 22 AUD_CAP2
AVSS CAP2
30
AVSS AUD_VREFFLT
26 21
AVSS VREFFILT
42 34 AUD_V_B
PVSS V-
49 37 AUD_VREG
GND VREG
SC4D7U6D3V3KX-GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC1U6D3V2KX-GP
C3016
92HD79B1A5NLGXTAX-GP C3017
1
C3018
C3015
AUD_AGND
X01 will change to 92HD79B1
2
P/N:71.92H79.003
AUD_AGND AUD_AGND AUD_AGND AUD_AGND
Azalia I/F EMI Close to codec

B B
PCH_SDOUT_CODEC
1
X02-20091222
R3015
47R2J-2-GP
DY +AVDD R3016 +AVDD
20KR2F-L-GP
2
1 2 2 R3014 1
AUD_HP1_JD# 60
1
1
PCH_AZ_CODEC_SDOUT1
R3018 R3019 0R0603-PAD

2K49R2F-GP 2K49R2F-GP
2 R3017 1
2
2
AUD_SENSE_A AUD_SENSE_B
0R0603-PAD
1
1
C3019 R3021
SC1000P50V3JN-GP-U R3022 20KR2F-L-GP
39K2R2F-L-GP 2 R3020 1
2
2 1
2
EXT_MIC_JD# 60
1
0R0603-PAD
C3020 AUD_AGND
DY SCD1U10V2KX-5GP AUD_AGND
2
Close to Pin13 AUD_AGND

Close to Pin14
A A
<Core Design>
Wistron Corporation
Title
Audio Codec 92HD81B1
Custom A00
Date:
Berry
Monday, March 29, 2010 Sheet 30 of 92
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A A
<Core Design>
Wistron Corporation
Title
Size
Reserved
Document Number Rev
Custom
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
A B C D E
4 4
3 3
(Blanking)
2 2
1 <Core Design> 1
Wistron Corporation
Title
Reserved
A3
Berry A00
A B C D E
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
+KBC_PWR X01 20091111
R3701 +3.3V_RUN +3.3V_RUN 10mW circuit
CAP close to VCC-GND pin pair
2
DY 1
0R2J-2-GP
+3.3V_RTC_LDO
VBAT +KBC_PWR
2 1 x01 change tolerant 20091118
R3702 0R0603-PAD R3704
1
X02-20091222 C3702 C3703 1 2 KBC_PWRBTN_EC#
DY 0R2J-2-GP 2 1
SCD1U10V2KX-5GP R3703 100KR2J-1-GP
DY SC2D2U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
Q2302 +3.3V_RTC_LDO
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1
1
KBC_SDA1 +3.3V_RTC_LDO
C3701
C3704
C3705
C3706
C3707
C3708
C3709
C3710
39 THERM_SDA 4 3
KBC_PWRBTN# 3 R3706
DY 66 KBC_PWRBTN#
2
5 2 D3702 10KR2J-3-GP
2
115
102
BAT54C-U-GP
X01 20091111
88
76
46
19
80
4
U3701A 1 OF 2 KBC_SCL1 6 1
BAT_IN# 44 THERM_SCL 39
2
D D
GPIO41
VCC
VCC
VCC
VCC
VCC
AVCC
VDD
S
2N7002EDW-GP R3707
1
x01 change tolerant 20091117 KBC_ON# 2 1KBC_ON#_GATE
45 AD_IA
84.27002.F3F R3708
G
Q3703
1
x01 change tolerant 20091118 A00-20100202 104
VREF GPIO10/LPCPD#
124 PCH_TEMP_ALERT# 25 1 DY 2 10KR2J-3-GP C3713
SCD1U10V2KX-5GP
PLT_RST1#_1 0R2J-2-GP SI2301CDS-T1-GE3-GP
C3715
1
DY 2
SCD1U10V2KX-5GP LRESET#
7
+1.05V_VTT AC_IN#_KBC
97 A/D 2 PCLK_KBC 21
D
TP3704 KBC_GPIO91 GPI90/AD0 LCLK
1 98 3 LPC_LFRAME# 24,70
GPI91/AD1 LFRAME# LPC_LAD0 D3703 +KBC_PWR
99 126
1
82 THERMTRIP_VGA# GPI92/AD2 LAD0 LPC_LAD1 +KBC_PWR BAT54C-U-GP
76 PSID_EC 100 127 LPC_LAD[0..3] 24,70
DISCRETE_ID GPI93/AD3 LAD1 LPC_LAD2 R3710
KBC_THERMTRIP#
108
GPIO05 LAD2
128
LPC_LAD3
DY 2K2R2J-2-GP
96
GPIO04 LPC LAD3
1 3 AC_IN# 45
X01 change location SERIRQ
125
8
INT_SERIRQ 23,24
C3711
PM_CLKRUN# 22 Q3704
2
GPIO11/CLKRUN# H_THERMTRIP_R# 2 DY1
X01 20091111 122 SIO_RCIN# 25
2
KBRST#
22 SUS_PWR_DN_ACK 101 121 SIO_A20GATE 25 G
. .
1
GPI94 GA20 ECSCI#_KBC SCD1U10V2KX-5GP
105 29
90 3.3V_RUN_VGA_EN GPI95 ECSCI#/GPIO54 KBC_ON#
106 D/A 9 PANEL_BLEN 55 DY D
.
.
.
9 VDDPWRGOOD_KBC PCB_VER2 GPI96 GPIO65/SMI# ECSWI#_KBC
107 123 2 3 KBC_THERMTRIP#
GPI97 GPIO67/PWUREQ# 9,25,42,82 H_THERMTRIP# EC_ENABLE#
PH for Discrete 1 UMA 2 Q3705 S
R3714 10KR2F-2-GP PMBS3904-1-GP
Internal PL for UMA
2N7002E-1-GP
22,42,47,50,51,89 PM_SLP_S3#
KBC_PWRBTN_EC#
64
GPIO01/TB2 GPIO74/SDA2
68 KBC_SDA1 23 X02-20100104
+KBC_PWR
A00-20100301 AC_IN#_KBC
95
93
GPIO03 SMB GPIO73/SCL2
67
69
KBC_SCL1 23 84.2N702.D31
GPIO06 GPIO22/SDA1 BAT_SDA 44,45
69 LID_CLOSE# 94 70 BAT_SCL 44,45
R3715 PCB_VER0 GPIO07 GPIO17/SCL1
119 D3701
KBC_BIOS_ID GPIO23
2 1 6 25 SIO_EXT_WAKE# 1
GPIO24
DIS
2K2R2J-2-GP
90 1.0V_RUN_VGA_EN
PCB_VER1
109
GPIO30 ECSWI#_KBC
120
65
GPIO31 SP GPIO66/G_PWM
81 1.8V_VGA_RUN_EN 90 3
66 PWRLED#
66 PWR_BTN_LED#
66 WHITE_LED#_KBC
66
16
GPIO32/D_PWM
GPIO33/H_PWM
GPIO40/F_PWM
2 SSID = KBC
17 84 ECSMI#_KBC BAS16PT-GP
68 KB_LED_BL_DET GPIO42/TCK GPIO77
A00-20100203
22 PCH_RSMRST# 20
GPIO43/TMS SPI GPIO76/SHBM
83 BLUETOOTH_EN 73 +KBC_PWR
22,50 PM_SLP_S4# 21
22
GPIO44/TDI GPIO GPIO75
82
91
WIFI_RF_EN 76
1
D3704
80 PLTRST_DELAY# GPIO45/E_PWM GPIO81 WWAN_RADIO_DIS# 76 25 SIO_EXT_SCI#
23
46 3V_5V_POK GPIO46/TRST# ECSCI#_KBC
22 PM_PWROK 24 3 DY
1
GPIO47
62 EC_SPI_WP#_R 25
EC_ENABLE# GPIO50/TDO R3705
26 111 E51_TxD 76 2
GPIO51 GPO83/SOUT_CR/BADDR1 2K2R2J-2-GP
27 113
C 54 BLON_OUT
47 IMVP_VR_ON
76 PSID_DISABLE#
28
73
GPIO52/RDY#
GPIO53
GPIO87/SIN_CR
GPO84/BADDR0
112
E51_RxD 76
AC_PRESENT_EC 22
PM_LAN_ENABLE 76
BAS16PT-GP +KBC_PWR
C
2
GPIO70
89 GFX_CORE_EN 74 114 RN3701
GPIO71 GPIO16 1.05VTT_PWRGD_KBC DISCRETE_ID
24 ME_UNLOCK# 75 14 1 2 1.05VTT_PWRGD 49,50
GPIO72 GPIO34 R3723 0R0402-PAD THERMTRIP_VGA#
63 USB_PWR_EN# 110 15 5 4
GPO82/TRIS# GPIO36 BAT_SCL
SER/IR S5_ENABLE 42 X02-20091222 D3705 A00-20100301 6 3
1
1 BAT_SDA 7 2
25 SIO_EXT_SMI#
ECRST# 8 1 DY EC3701
44 KBC_VCORF 3 ECSMI#_KBC +3.3V_RUN SCD1U10V2KX-5GP
2
VCORF SRN4K7J-10-GP
1
C3712 2
AGND
+3.3V_RUN SC1U6D3V2KX-GP RN3703

GND
GND
GND
GND
GND
GND
BAS16PT-GP E51_RxD 1 2 KB_DET# 4 1

DY
2
R3711 10KR2J-3-GP LCD_CBL_DET# 3 2
NPCE781BA0DX-GP
Vendor recomment FW can do it x01 Change tolerant 20091117
116
89
78
45
18
5
103
SRN100KJ-6-GP
1
1
R3728
10KR2J-3-GP
10KR2J-3-GP
KBC_THERMTRIP# 2 1
R3727 AC_IN#_KBC R3709 2 1 100KR2J-1-GP
R3729
10KR2J-3-GP R3718 100KR2J-1-GP

DY MB VERSION U3701B 2 OF 2
KCOL[0..16] 68
2
PCB_VER0 ID VER2 VER1 VER0 77 53 KCOL0

X01 change location
22 PCH_SUSCLK_KBC 32KX1/32KCLKIN KBSOUT0/JENK#
PCB_VER1 52 KCOL1 BLUETOOTH_EN R3712 1 2 10KR2J-3-GP
PCB_VER2 A01 0 0 0 KBSOUT1/TCK
KBSOUT2/TMS
51 KCOL2 S5_ENABLE R3713 1 2 10KR2J-3-GP
10KR2J-3-GP
50 KCOL3 IMVP_VR_ON R3717 1 2 10KR2J-3-GP

X01 0 0 1
1
KBSOUT3/TDI
10KR2J-3-GP
R3737 1 2TOURBO_BOOST 79 49 KCOL4

+KBC_PWR DY 32KX2 KBSOUT4/JEN0#
R3732
R3733
10KR2J-3-GP 30 48 KCOL5 GFX_CORE_EN R3719 1 2 10KR2J-3-GP

R3731 DY X02 0 1 0 30 AMP_MUTE# GPIO55/CLKOUT KBSOUT5/TDO KCOL6
10KR2J-3-GP DY KBSOUT6/RDY#
47
KCOL7
A00 0 1 1 47 IMVP_PWRGD 63
GPIO14/TB1 KBSOUT7
43
KCOL8
X01 20091116
22 PM_PWRBTN# 117 KBC 42
2
GPIO20/TA2 KBSOUT8 KCOL9 +KBC_PWR

54 LCD_TST_EN 31 41
GPIO56/TA1 KBSOUT9 KCOL10
A00-20100125 A00-20100203 30 KBC_BEEP 32
GPIO15/A_PWM KBSOUT10
40
118 39 KCOL11
66 AMBER_LED#_KBC
2
GPIO21/B_PWM KBSOUT11 KCOL12
68 KB_BL_CTRL 62 38
GPIO13/C_PWM KBSOUT12/GPIO64 KCOL13 R3722
37
KBSOUT13/GPIO63 KCOL14
36 10KR2J-3-GP
KBSOUT14/GPIO62 KCOL15
35
KBSOUT15/GPIO61/XOR_OUT KCOL16 TP3708
68 KB_DET# 13 34
1
GPIO12/PSDAT3 GPIO60/KBSOUT16 KCOL17 TPAD14-GP
54 LCD_CBL_DET# 12 33 1
VGA STRAP 82 THERMTRIP_VGA_GATE 2 1 THERMTRIP_VGA_GATE_C 11 GPIO25/PSCLK3 GPIO57/KBSOUT17 PURE_HW_SHUTDOWN#
B option GPIO24 GPIO5
R3746 0R0402-PAD 54 LCD_TST
68 TPDATA
10
71
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1 KBSIN0
54 KROW0
KROW1
KROW[0..7] 68
B
68 TPCLK 72
GPIO37/PSCLK1 PS/2 KBSIN1
55
56 KROW2 +3.3V_RUN
UMA 0 0 KBSIN2
KBSIN3
57 KROW3
58 KROW4
Madisan 1 1 62 EC_SPI_DI 86
F_SDI
KBSIN4
KBSIN5
59 KROW5
1 2 EC_SPI_DO_C 87 60 KROW6
Park 1 0 62 EC_SPI_DO
62 EC_SPI_CS#
R3745 33R2J-2-GP 90
F_SDO
F_CS0# FIU
KBSIN6
KBSIN7
61 KROW7 RN3702
R3734 1 2 33R2J-2-GP EC_SPI_CLK_C SIO_A20GATE
M96 1 0 For EMI 62 EC_SPI_CLK 92
F_SCK SIO_RCIN#
2
1
3
4
85 ECRST#
VCC_POR# SRN10KJ-5-GP
PM_PWROK PCLK_KBC NPCE781BA0DX-GP

Vendor recomment can remove
1
EC3702
SC470P50V2JN-GP EC3703
A00-20100204 X02-20091222
DY SC18P50V2JN-1-GP
2
R3716
X02-20100105 2 1 PLT_RST1#_1
9,21,70,76,78,80 PLT_RST#
0R0402-PAD
ECRST#
1
C3714
SC470P50V2JN-GP
DY
2
1 C3716
DY
2
SC1U6D3V2KX-GP
39,42 PURE_HW_SHUTDOWN# 1
2
Q3701
3
PMBS3906-GP
A A
<Core Design>
Wistron Corporation
Title

KBC Nuvoton NPCE781BA0DX Rev
A2
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Wistron Corporation A
Title
Reserved
A4
Berry A00
5 4 3 2 1
5 4 3 2 1
+5V_RUN +3.3V_RUN
SSID = Thermal x01 change tolerant 20091117
1
1
1
R3901
C3902 C3901 10KR2J-3-GP
SC10U6D3V5MX-3GP SCD1U10V2KX-5GP
2
+3.3V_RUN EMC2102_FAN_TACH
1. Place near CPU PWM CORE and PCH. EMC2102_FAN_TACH 58
D D
Layout notice : R3902
Both DN1 and DP1 routing 10 mil 49D9R2F-GP EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE 58
trace width and 10 mil spacing. 2 1 EMC2102_VDD_3D3
near EMC2102
1
C3905 must be near Q3901
C3903
SCD1U10V2KX-5GP
2
2
1
C3904 C3905 +3.3V_RUN
1 SC470P50V2JN-GP SC470P50V2JN-GP
Q3901 DY THERM_SCL 37
RN3901
THERM_SDA 37
2
2
PMBS3904-1-GP THERM_SCL 3 2
3
THERM_SDA 4 1
SRN4K7J-8-GP
29
28
27
26
25
24
23
22
U3901
SRN10KJ-5-GP
GND
TACH
VDD_5Va
FANa
FANb
VDD_5Vb
SMCLK
SMDATA
EMC2102_DN2_UMA THERM_POWER_OK# 3 2
THERMTRIP# 4 1
2
C3906
SC470P50V2JN-GP RN3902
UMA 1
DY
2
Q3902 1 21
3
VDD_3V NC#21
2
PMBS3904-1-GP EMC2102_DP2_UMA
0R2J-2-GP
R3903 EMC2102_DN1 2 20
DN1 GND
2
2. System Sensor(UMA Only) UMA

R3904 EMC2102_DP1
0R2J-2-GP
3 DP1 ALERT# 19 X02-20091222 +3.3V_RUN

Layout notice : UMA EMC2102
1
Both DN2 and DP2 routing 10 mil EMC2102_DN2 4 18 CLK_32K

DN2 CLK_IN R3905
C trace width and 10 mil spacing. C
1
EMC2102_DP2 5 17 EMC2102_CLK_SEL 1 2
DP2 CLK_SEL 0R0402-PAD
Reserved DISCRETE
DIS EMC2102_DN3 6 16 EM2102_RESET# 1 GND = Internal Oscillator Selected
DN3 RESET#
1
82 VGA_THERMDC 1 2 C3907 TP3901

R3906 0R2J-2-GP SC470P50V2JN-GP EMC2102_DP3 7 15 +3.3V = External 32.768kHz Clock Selected
DP3 NC#15
2
THERMTRIP#
POWER_OK#
SYS_SHDN#
FAN_MODE
SHDN_SEL
DIS
TRIP_SET
82 VGA_THERMDA 1 2
R3907 0R2J-2-GP
NC#8
3.VGA Sensor(DISCRETE Only) GND = Channel 1 Main G7922R61U for GMT P/N:74.07922.0B3
EMC2102-DZK-GP
OPEN = Channel 3 SEC. EMC2102 for SMSC P/N:74.02102.A73
10
11
12
13
14
Layout notice :
Both VGA_THERMDA and VGA_THERMDC routing +3.3V = Disabled
10 mil trace width and 10 mil spacing.
R3908
2 EMC2102_SHDN THERM_POWER_OK#
DY 1 THERMTRIP#
C3907 must be near Q3902 10KR2J-3-GP
+3.3V_RUN
R3909
2
THERM_SYS_SHDN#
C3908 C3909 2 EMC2102_FAN_mode
1 SC470P50V2JN-GP SC470P50V2JN-GP DY 1
Q3903 DY 10KR2J-3-GP +3.3V_RUN

2
PMBS3904-1-GP C63 must be +3.3V_RUN

A00-20100204
3
near EMC2102 Q3904

R3911
B 4.HW T8 sensor 1 2 G B
. .
0R0402-PAD
1
D PURE_HW_SHUTDOWN# 37,42
.
.
.
1
Layout notice : GND = Fan is OFF C3910 R3913
Both DN3 and DP3 routing 10 mil S SCD1U10V2KX-5GP 10KR2F-2-GP
trace width and 10 mil spacing.
OPEN = Fan is at 60% full-scale
2
+3.3V = Fan is at 75% full-scale
2
2N7002E-1-GP
84.2N702.D31 TRIP_SET Pin Voltage

V_DEGREE
V_DEGREE=(((Degree-75)/21)
1
1
22 PCH_SUSCLK_2102 C3911 R3914
SCD1U10V2KX-5GP 2K37R2F-GP
32K suspend clock output
2
D
2
x01 change tolerant 20091117 T8 shutdown is set 88 deg-C.
. Q3905
2N7002E-1-GP
.
.
. . 84.2N702.D31
G
R3915
42 RUN_ENABLE CLK_32K_R 1 2 CLK_32K
10R2J-2-GP
1
A C3913 A
DY SC4D7P50V2CN-1GP
<Core Design>
2
Wistron Corporation
Title
Size
Thermal/Fan Controllor EMC2102
Document Number Rev
Custom A00
Berry
Date: Tuesday, April 06, 2010 Sheet 39 of 92
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend H_THERMTRIP# 9,25,37,82
E
R4201
H_PW RGD_R
9,25 H_PW RGD 1
DY 2 B
DY Q4201
1
1KR2J-1-GP C4202 CHT2222APT-GP
C
SCD1U10V2KX-5GP DY
BAS16PT-GP
2
D 2 x01 change to 10V tolerant 20091117 D
3 PURE_HW _SHUTDOW N# 37,39
46 3V_5V_EN 1
D4201
1
1 2 S5_ENABLE 37
R4203 1KR2J-1-GP
R4202
200KR2J-L1-GP
DY
Run Power +15V_ALW AO4468 MAX 9A

Rds(on) = 18.5mOhm
+5V_RUN
+5V_ALW +5V_RUN
2
U4201
5 D G 4
R4204 6 D S 3 +5V_RUN Comsumption
100KR2J-1-GP 7 D S 2
C
1
8 D S 1
Peak current 7.73A C
1
R4205 C4203
5V_RUN_ENABLE SI4800BDY-T1-GP SC10U10V5KX-2GP
1 2
+3.3V_RTC_LDO
2
1
10KR2J-3-GP
C4201 84.04800.D37
100KR2J-1-GP SC6800P25V2KX-1GP
PS_S3CNTRL 18,50
2
R4207 x01 change to 10V tolerant 20091117
1 2 PS_S3CNTRL
D G S
+3.3V_RUN
6
Q4202 AO4468 MAX 11.6A

2N7002EDW -GP Rds(on) = 18.5mOhm
84.27002.F3F +3.3V_ALW +3.3V_RUN
1
U4202 +3.3V_RUN Comsumption

S G D 5 D G 4
Peak current 8.14A
6 D S 3
7 D S 2
8 D S 1
1
22,37,47,50,51,89 PM_SLP_S3#
R4211 C4205
RUN_ENABLE 3.3V_RUN_ENABLE SI4800BDY-T1-GP SC10U6D3V5KX-1GP
39 RUN_ENABLE 1 2
2
1
10KR2J-3-GP
B C4207 84.04800.D37 B
SCD01U50V2KX-1GP
2
1.5V_RUN for VGA Comsumption

+1.5V_RUN_CPU +1.5V_RUN
S3 Power Reduction
1 MAX Current 3000 mA
Peak current 7.39A
Design Current 2100 mA +1.5V_RUN_CPU Comsumption

1
S3 Power Reduction X01 20091111

DY
R4213
220R2J-L2-GP 2 +1.5V_SUS
+1.5V_RUN_CPU +1.5V_RUN
Peak current 3A
+1.5V_RUN for Mini-Card Comsumption
X02-20091222 Peak current 1A
2
DY
DISCHARGE_1D5V_CPU_C
R4214 1 2 1 2
0R5J-5-GP R4215 0R0805-PAD
R4219 1 DY 2 1 2 Total= 11.39A
0R5J-5-GP R4220 0R0805-PAD
TPCA8039-H MAX 34A

Rds(on) = 3.8m OHM
U4203
8 D S 1
7 D S 2
6 D S 3
D
5 D G 4 <Core Design>
A . Q4206 C4208 A
2N7002E-1-GP R4227 TPCA8039-H-GP SC10U6D3V5KX-1GP
2
. 1 21.5V_RUN_ENABLE
COLAY
. .
. 84.2N702.D31 Wistron Corporation
10KR2J-3-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1

G
C4210
DY SCD01U50V2KX-1GP Title
2
DIS uses 84.08039.037 TPCA8039-H Peak current=34A

PS_S3CNTRL
UMA uses 84.07686.037 SI7686DP Peak current=35A Size
Power Plane Enable
Document Number Rev
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
Batt Connecter
+VCHGR
1
PG4401
2 1 PC4402 PC4401
D 45 BATT_SENSE SCD1U50V3KX-GP SC2200P50V2KX-2GP BATT1 D
2
GAP-CLOSE-PWR-3-GP 10
1
2
R4401 1 2 100R2J-2-GP PBAT_SMBCLK1 3
37,45 BAT_SCL
R4402 1 2 100R2J-2-GP PBAT_SMBDAT1 4
37,45 BAT_SDA
R4403 1 2 100R2J-2-GP PBAT_PRES1# 5
37 BAT_IN#
PR4401 6
+KBC_PWR 2 1 AFTP4401 1BAT_ALERT 7
8
470KR2J-2-GP 9
11
ALP-CON9-2-GP-U
20.81316.009
C
For actual location, need to be swap all pin C
Close to Batt Connector
BAT_IN#
BAT_SDA
BAT_SCL
AFTP4402 1 PBAT_PRES1# PD4401
3
AFTP4403 1 PBAT_SMBDAT1 PD4402 PD4403
3
3
B AFTP4404 1 PBAT_SMBCLK1 1 2 B
AFTP4405 1 +VCHGR 1 2 1 2
BAV99-8-GP
BAV99-8-GP BAV99-8-GP
+KBC_PWR
<Core Design>
A
Title
BATT CONN
A4
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = Charger modify +VCHGR

+SDC_IN +PWR_SRC
PU4502 PR4502 +VCHGR
+DC_IN_SS 8 D S 1 PU4503
7 D S 2 1 2 1 S D 8
6 D S 3 2 S D 7
D01R2512F-4-GP
1
5 D G 4 3 S D 6
PR4503
G D
100KR2J-1-GP
+DC_IN_SS 4 5
AO4407A-GP
1
AO4407A-GP
2
Id=-12A PG4502
10KR2J-3-GP
D PG4503 D
PR4504
PR4513_03
2
Qg=-25nC
1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
Id=-12A
2
Rdson=10~38mohm PR4506
10KR2F-2-GP
PR4533_02 2
2
+DC_IN_SS Qg=-25nC
PG4501
PG4506
PG4504
PG4505
PR4505
470KR2J-2-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1
DY Rdson=10~38mohm
PR4524_03
2 1
2
PQ4502_03
1
PR4507
X02-20091223
PQ4502_05
0R2J-2-GP
1
PQ4501
316KR3F-2-GP
3 4 PR4508 PR4510
1
0R0402-PAD 0R0402-PAD
PR4509
BQ24745_ACOK 2 5
2
1 6 CHAGER_SRC
SCD1U50V3KX-GP
2
2N7002EDW-GP 1 2
X02-20091223
SC2200P50V2KX-2GP
PC4502
84.27002.F3F
PC4504
SCD1U50V3KX-GP
SCD1U25V2ZY-1GP
2
CHAGER_SRC
SC1U6D3V2KX-GP
1
2 1
EC4501
EC4502
CHG_AGND
PR4511 0R0402-PAD
1
PC4505
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
DY
ICREF
1
2 1
1
PR4513
PC4506
PC4507
PC4508
PC4509
BQ24745_DCIN BQ24745_CSSP1
33R3J-2-GP
22 28 2
PC4503 DCIN CSSP DY DY
1
5
6
7
8
SCD1U50V3KX-GP
2
SI4800BDY-T1-GP
BQ24745_ACIN 2 SCD1U50V3KX-GP
DY DY
PU4504
PR4514 48K7R3F-1-GP
ACIN
D
D
D
D
BQ24745_REF 27 BQ24745_CSSN CHG_AGND
+KBC_PWR x01 change tolerant 20091117
2
BQ24745_LDO CSSN BQ24745_ICOUT
2 10KR2F-2-GP
11 26
2
VDDSMB ICOUT
10KR2F-2-GP
X02-20091223 PD4501
Charger Current=1.4~3.6A
1
1
PR4516
CHG_AGND
SCD01U50V2KX-1GP
1
C
PC4501 1 PR4517 2BQ24745_BST1 C
25 BQ24745_BOOT_1 K A 1 2
SCD1U10V2KX-5GP PR4512 BOOT 0R0603-PAD
modify +VCHGR
1
PC4510
PR4515
BQ24745_LDO PC4511
G
S
S
S
DY 2 1 BQ24745_ACOK VDDP 21
SD103AWS-1-GP SCD1U50V3KX-GP
2
4
3
2
1
0R0402-PAD 13 ACOK X02-20091223 X02-20100116
CHG_AGND 2009/11/24
2
ACAV_IN BQ24745_CHARGER_UGATE
2
UGATE 24
1
2 1 BAT_SCL_1 10 1 2 PC4513 +VCHGR1 +VCHGR
37,44 BAT_SCL SCL
PG4507 GAP-CLOSE-PWR-3-GP PC4512 SC3300P50V3KX-1GP PL4501
1 PR4518 2 DY PR4519
1
SCD1U50V3KX-GP BQ24745_LX1
15K8R3F-GP
23 0R0603-PAD
2009/08/04
2
PHASE 1 2 1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
D01R2512F-4-GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
BAT_SDA_1 BQ24745_PHASE_GND
DY 37,44 BAT_SDA 2 1 9 SDA 1 2
DY L-5D6UH-GP-U
1SMA18AT3G-GP
PR4520
CHG_AGND PG4508 GAP-CLOSE-PWR-3-GP BQ24745_LGATE_1 PC4514
SCD1U50V3KX-GP
20
K
LGATE
PC4515
PC4516
PC4517
PC4518
PC4519
SC220P50V2JN-3GP
5
6
7
8
2
SI4800BDY-T1-GP
1
PG4510
PG4509
PD4502
DY
PU4505
PR4501
D
D
D
D
14 19
37 AD_IA 2 1 NC#14 PGND DY
SCD1U50V3KX-GP
0R2J-2-GP
2
18 BQ24745_CSOP_1
A
CHG_AGND CSOP
X03-20100119
2
BQ24745_VICM CSON 17
G
S
S
S
8
PC4520
4K7R2J-2-GP
BQ24745_FBO VICM BQ24745_PR4505
4
3
2
1
1
1
PR4522
PR4521
SC220P50V2JN-3GP
200KR2F-L-GP
SCD1U50V3KX-GP
2
8K45R2F-2-GP
1 2
PR4525
PR4524
6 CHG_AGND
BQ24745_EAI FBO 1 PR4523 2 BQ24745_CSOP 0R0402-PAD
1BQ24745_FBO1
5 16
1 PC4524
EAI NC#16
2
PC4522 BQ24745_EAO 4
PR4526 EAO 0R0402-PAD X02-20091223
1
PC4523
2SC2200P50V2KX-2GP BQ24745_REF
1
1 3
2 1PR4526_01
2 7K5R2F-1-GP
1 BQ24745_CE 7 VREF X02-20091223 X02-20091223
1 PR4527 2
1
PC4521 CE BQ24745_CSON
DY 12 15
GND
PC4530
PC4525 0R0402-PAD
SCD1U10V2KX-5GP
SC150P50V2JN-3GP GND VFB
SCD1U50V3KX-GP
1
1 2 BAT_SENSE
X02-20091223 2 PR4528 1
1
2
B
DY B
PC4531
BATT_SENSE 44
DY PC4527 SC56P50V2JN-2GP PC4529
2
PU4501
2
DY
SC1U6D3V2KX-GP
PC4526 0R0402-PAD
29
SCD01U50V2KX-1GP
1
BQ24745RHDR-GP
2
DY X02-20091223
SCD1U50V3KX-GP
1
1K8R6J-GP
DY
SCD1U25V2ZY-1GP
PC4528
2
PC4532
PR4530
2 PR4529 1 DY DY
SCD01U50V2KX-1GP 0R0402-PAD
2
CHG_AGND
CHG_AGND
CHG_AGND CHG_AGND
This Resistor
must be 1%
tolerance.
37 AC_IN#
D
1
PC4533
DY SCD1U10V2KX-5GP . Q4502
2N7002E-1-GP
2
.
. .
.
S
A ACAV_IN A
x01 change tolerant 20091117 <Core Design>
Wistron Corporation
Title
CHARGER BQ24745
Custom
Berry A00
5 4 3 2 1
A B C D E
+3.3V_ALW_2
51125_VCLK
1
PC4603 PC4604
SC1KP50V2KX-1GP
PC4602
PR4602 SCD1U25V3KX-GP SCD1U25V3KX-GP
100KR2J-1-GP
2
2
PD3903_1
PD3904_1
51125_ENTRIP
D
51125_ENTIP1
3
.
1
Q4601 PR4601
2N7002E-1-GP . PC4601 DY PD4601 PD4602
. .
SC18P50V2JN-1-GP
. 76K8R2F-GP BAT54S-5-GP BAT54S-5-GP
4
84.2N702.D31 PQ4602
1
2N7002EDW-GP +15V_ALW +5V_PWR
84.27002.F3F
PD3903_04
PG4605
3
42 3V_5V_EN A00-20100224 x01 change tolerant 20091117
1 2 PD3903_2
51125_ENTIP2 GAP-CLOSE-PWR-3-GP
1
4 PC4605 PC4606 4
1
SC1U25V3KX-1-GP SCD1U10V2KX-5GP
SC18P50V2JN-1-GP
1
PR4603
2
1
82KR2F-1-GP
PC4607
DY
PC4608
2
SCD1U25V3KX-GP
2
TPS51125 RT8205B
PR4622 DY ASM
X01 20091124
+PWR_SRC +PWR_SRC
PR4622 +PWR_SRC
X01 EMI stuff 20091118 51125_EN 1 2
PC4612
SC10U25V6KX-1GP
820KR3J-GP PC4613
1
PC4610 PC4611 TPS51125 RT8205B X01 EMI stuff 20091118
1
SCD01U50V2KX-1GP
PC4609 PR4605 0R3J 4R7
DY
SC10U25V6KX-1GP
SC10U25V6KX-1GP
2
+5V_PWR
SCD1U25V2KX-GP
TPS51125 RT8205B PC4614 PC4616 PC4617 +5V_ALW

D D
2
D 8
D 7
D 6
D 5
5
6
7
8
1
PR4604 0R3J 4R7 PG4613
D
D
D
D
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U25V2KX-GP
PU4602 PU4603 2 1
16
FDS8880-NL-GP FDS8880-NL-GP
2
PU4601 GAP-CLOSE-PWR
PG4614
VIN
Design Current =9.07A PC4615 Design Current = 8.48A 2 1
G
S
S
S
SCD1U25V3KX-GP PR4604 PR4605 SCD1U25V3KX-GP
1 S
2 S
3 S
4 G
14.25A<OCP<16.84A X02-20100116 4D7R3J-L1-GP 4D7R3J-L1-GP PC4618 13.32A<OCP< 15.75A GAP-CLOSE-PWR
G S
4
3
2
1
51125_VBST2_1 251125_VBST2 51125_VBST1 51125_VBST1_1
S G 2 1 1 9
BOOT2 BOOT1
22 1 2 1 2
2
PG4615
1
+3.3V_ALW PL4601 +5V_PWR
51125_DRVH2 10 21 51125_DRVH1 X02-20100116
UGATE2 UGATE1 PL4602
GAP-CLOSE-PWR
1 2 51125_LL2 11 20 51125_LL1 1 2 PG4616
PHASE2 PHASE1
2 1
1
PC4619 PTC4601 PTC4602 IND-3D3UH-115-GP 51125_DRVL2 51125_DRVL1

D 12
LGATE2 LGATE1
19
IND-2D2UH-46-GP-U
1
1
x01 change tolerant 20091117 GAP-CLOSE-PWR
D
D 8
D 7
D 6
D 5
5
6
7
8
SCD1U10V2KX-5GP
ST220U6D3VDM-15GP
PR4606 PG4617
DY DY DYPR4607
D
D
D
D
PG4624 2D2R5F-2-GP PU4604 51125_VO2 7 24 51125_VO1 PU4605 PG4626 PTC4603 PTC4604 2 1
ST100U6D3VBM-5GP
151125_LL2_R
2
VOUT2 VOUT1
1
1
GAP-CLOSE-PWR-3-GP
FDS6676AS-GP
FDS6676AS-GP 2D2R5F-2-GP PC4620
151125_LL1_R
2
GAP-CLOSE-PWR-3-GP
SCD1U10V2KX-5GP
ST220U6D3VDM-15GP
ST100U6D3VBM-5GP
51125_FB2 5 2 51125_FB1 GAP-CLOSE-PWR
DY
2
FB2 FB1
PG4618
2
2 1
2
2
G
S
S
S
1 2 51125_EN 13 23 3V_5V_POK
DY
1 S
2 S
3 S
4 G
PC4621 PR4608 820KR2F-GP EN PGOOD GAP-CLOSE-PWR

DY G S
4
3
2
1
SC330P50V2KX-3GP 51125_ENTIP2 6 51125_ENTIP1
S G 51125_VREF ENTRIP2 ENTRIP1
1
PC4622 2
PG4619
1
2
x01 change tolerant 20091117 3 15 SC560P50V-GP

DY
2
REF PGND GAP-CLOSE-PWR
X02-20100201
1
SCD22U10V2KX-1GP
PC4623
51125_TONSEL 4 25 PG4620
TONSEL GND
2 1
1
PR4611
2
1
PR4610 14 18 51125_VCLK 0R2J-2-GP GAP-CLOSE-PWR

SKIPSEL LG1_CP
1
0R2J-2-GP 51125_SKIPSEL DY PG4621
PR4609 DY PR4612 2 1
VREG3
VREG5
6K65R2F-GP 33KR2F-GP
1 2
51125_FB1_R GAP-CLOSE-PWR
2
1 2
51125_FB2_R
2
RT8205BGQW-GP PC4624 DY
8
17
3 +3.3V_ALW 3
DY PC4625 +5V_ALW2 SC18P50V2JN-1-GP
2
SC18P50V2JN-1-GP +3.3V_ALW_2 3D3V_AUX_S5_5_51125
PG4635
2
1
1 2
1
PR4614 PR4615 PR4616

PR4613 GAP-CLOSE-PWR-3-GP 21K5R2F-GP
10KR2F-2-GP
51125_VREF 2 1
0R2J-2-GP
Change to RT8205B 100KR2J-1-GP
PR4617 74.08205.B73 Close to VFB Pin (pin2)
2
2 1
+3.3V_ALW_2 DY0R2J-2-GP 3V_5V_POK 37
2
SC22U6D3V5MX-2GP
PC4628
51125_VREF 2 DY PR4618
1
1
1
0R2J-2-GP PC4626 PC4627
Close to VFB Pin (pin5) PR4619 SC4D7U6D3V3KX-GP
DY
SC10U10V5KX-2GP
+3.3V_ALW_2 2 1 I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

2
0R2J-2-GP
X02-20091228 PR4620 Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B
2 1
DY0R2J-2-GP O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
X02-20091223 H/S: FDS8880 9.6mohm/12mOhm@4.5Vgs/ 84.08880.037
+3.3V_ALW_2 +3.3V_RTC_LDO
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L L/S: FDS6676AS 5.9mOhm/7.25mOhm@4.5Vgs/ 84.06676.A37
Inductor: 3.3UH PCMB104T-3R3MS Cyntec 10.8mohm/11.8mohm Isat =16Arms 68.3R310.20C TPS51125 RT8205B PR4621
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L PR4614 DY ASM 1 2
PR4617 ASM DY
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081 0R0402-PAD
H/S: FDS8880 9.6mohm/12mOhm@4.5Vgs/ 84.08880.037
L/S: FDS6676AS 5.9mOhm/7.25mOhm@4.5Vgs/ 84.06676.A37
TPS51125:
TONSEL CH1 CH2 SKIPSEL VREG3 or VREG5 VREF(2V) GND

GND 200kHz 265kHz Operating OOA Auto Skip Auto Skip
Mode PWM only
VREF 245kHz 305kHz
VREG3 300kHz 375kHz
VREG5 365kHz 460kHz EN0 Open 820kΩ to GND GND
Operating
Mode enable both enable both LDOs, disable all
LDOs, VCLK on VCLK off and circuit
and ready to ready to turn on
turn on switcher channels
switcher
channels
RT8205B:
TONSEL CH1 CH2

2 2
GND 200kHz 250kHz
VREF 300kHz 375kHz
VREG3 365kHz 460kHz
VREG5 365kHz 460kHz
1 1
Bom
Wistron Corporation
Title
RT8205B_5V/3D3V
A1
Berry A00
A B C D E
5 4 3 2 1
PM_DPRSLPVR 12 +PWR_SRC
IMVP_VR_ON 37 X01 20091111
D4701
1
+PWR_SRC 7 VR_CLKEN# PC4706 PC4703 PC4704 PC4705
A K PM_SLP_S3# 22,37,42,50,51,89
DY DY
SCD1U50V3KX-GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
2
2
5
6
7
8
RB551V-30-2GP
H_VID[6..0] 12
D
D
D
D
SI7686DP-T1-GP
PU4702
1
TC4702 TC4703 +3.3V_RUN
H_VID6
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID0
DY DY
SE100U25VM-11GP
SE100U25VM-11GP
2
G
S
S
S
X02-20100116
4
3
2
1
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
X02-20091223 UGATE1 +VCC_CORE
PL4701
D D
PHASE1 1 2
1
1
IND-D36UH-9-GP
PR4775
2D2R5J-1-GP
1
PR4745
5
6
7
8
1
1K91R2F-1-GP PTC4703 PTC4702
D
D
D
D
SIR460DP-T1-GE3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PU4703 DY
1SNUBBER_1
ST330U2VDM-4-GP
SE220U2VDM-12GP
2
2
PG4708
PG4706
PR4735
PR4749
PR4773
PR4718
PR4755
PR4746
PR4730
PR4762
PR4729
PR4766
62883_DPRSLPVR
1
62883_CLK_EN#
62883_VR_ON
PC4718
SC330P50V2KX-3GP
62883_VID6
62883_VID5
62883_VID4
62883_VID3
62883_VID2
62883_VID1
62883_VID0
S
S
S
4 G
3
2
1
2
DY
+VCC_CORE_PHASE1
2
+3.3V_RUN LGATE1
PHASE1_R
X01 20091111
40
39
38
37
36
35
34
33
32
31
1
PU4701 Design Current = 48A

PR4720 ISEN1 1 2
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
1K91R2F-1-GP +5V_RUN PR4756 10KR2F-2-GP 52.8A<OCP<67.2A
VSUM+ 1 2
PR4772 PR4767 3K65R2F-1-GP
2
1 2 62883_PGOOD 1 30 BOOT2 1 2 B00T2_R VSUM- 1 2

37 IMVP_PWRGD PR4704 0R0402-PAD PGOOD BOOT2 PR4742 1R2F-GP
12 PSI# 1 2 62883_PSI# 2 29 UGATE2 2D2R3J-2-GP PR4770 ISEN2 1 2
PSI# UGATE2
PR4733 0R0402-PAD 1 DY 2 X02-20091223 PR4716 10KR2F-2-GP
1 2 62883_RBIAS 3 28 PHASE2 1 2 ISEN3 1 2
RBIAS PHASE2
1
NTC 470K close to H/S MOSFET of Phase1 PR4781 147KR2F-GP PC4710 4K02R2F-GP PR4738 10KR2F-2-GP
9 H_PROCHOT# PR4771
1
PR4758
DY 2H_PROCHOT#_R 4
VR_TT# VSSP2
27 SCD22U16V3KX-1-GP PR4751
0R0603-PAD
1 DY 2 6266A_NTC_R1 DY2 NTC-470K-1-GP 4K02R2F-GP 62883_NTC 5 26 LGATE2 +PWR_SRC
PR4774 NTC LGATE2
2
4K02R2F-GP 1 DY2 62883_VW 6 25 62883_VCCP
SCD01U25V2KX-3GP VW VCCP
PC4737 1 2 62883_COMP 7 24 62883_PWM3 PC4708 PC4732 PC4715 PC4713 PC4714 PC4712
COMP PWM3/LGATE1#
1
PR4726
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
8K06R2F-GP 62883_FB LGATE1
8
FB LGATE1
23 DY
SC10U25V6KX-1GP
2
2
1 2 ISEN3 9 22
5
6
7
8
ISEN3/FB2 VSSP1
D
D
D
D
SCD22U25V3KX-GP
SI7686DP-T1-GP
C PC4719 1PC4702 ISEN2 10 21 PHASE1 PU4704 C
ISEN2 PHASE1
SCD22U16V3KX-1-GP
SC1KP50V2KX-1GP X02-20091223
UGATE1
+1.05V_VTT
SCD22U25V3KX-GP
PC4709
2 1 PC4707
BOOT1
ISUM+
ISEN1
ISUM-
VSEN
IMON
PR4744 41
VDD
RTN
2
GND
VIN
1 DY 2 1 2 2
G
S
S
S
PC4738 PR4723
2
0R2J-2-GP SC33P50V2JN-3GP ISL62883HRTZ-T-GP 0R0402-PAD X02-20100116
11
12
13
62883_ISUM- 14
15
16
17
18
19
20
4
3
2
1
PR4786
UGATE1
DY DY 100KR2F-L1-GP X01 20091111
1
ISEN3 1 2 1 262883_COMP_R
1 2 ISEN1 PR4722 UGATE2 +VCC_CORE
62883_VIN
62883_VDD
PL4702
PC4735 PC4740 PR4752 BOOT1 1 2BOOT1_PHASE1
1
SC22P50V2JN-4GP SC150P50V2JN-3GP 324KR2F-GP 1 PC4736 2D2R3J-2-GP PHASE2 1 2
SCD22U25V3KX-GP X02-20091223 IMVP_IMON 12
PR4754 0R0402-PAD X02-20091223 +5V_RUN IND-D36UH-9-GP
PR4728
2
2D2R5J-1-GP
1
5
6
7
8
1
PR4776 PC4730 PTC4705 PTC4704
X01 20091121 1 2 +PWR_SRC
D
D
D
D
SIR460DP-T1-GE3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
VSUM- SCD22U10V2KX-1GP PC4734 PU4705
6K98R2-GP
1 2 1 PR4731 2 1 2 DY
ST330U2VDM-4-GP
SE220U2VDM-12GP
+5V_RUN
1SNUBBER_2
2
2
PC4722
PG4712
PG4713
PC4716 PR4759 0R0402-PAD
1
1
1 262883_FB_VSEN1 2 1 1R2F-GP SC1U10V2KX-1GP PR4734
2
PR4714 BOOT3 1 2 6208_PHASE3
6208_FCCM
S
S
S
562R2F-GP SC390P50V2KX-GP PC4729
PC4733
2
SC330P50V2KX-3GP
VSS_SENSE 12
2
2
SC1U10V2KX-1GP
1 2 SCD22U25V3KX-GP 2D2R3J-2-GP
6208_PWM
4
3
2
1
2
PR4712 1K82R2F-1-GP PC4723
X01 20091111
1
PU4706 SCD22U16V3KX-1-GP DY
1
LGATE2
X01 20091124
VCC
BOOT
PHASE2_R
+VCC_CORE_PHASE2
VSUM+
2 7 PHASE3
1
1
PC4717 PC4741 PWM PHASE UGATE3
8
UGATE
SCD33U16V3KX-1GP
SCD01U16V2KX-3GP
PC4721 PR4750 4 LGATE3

LGATE
1
SC330P50V2KX-3GP 2K61R2F-1-GP 6 ISEN2 1 2

2
PR4725 FCCM PR4780 10KR2F-2-GP
GND
GND
1
82D5R2F-1-GP PR4736 1VSUM_RR

2 VSUM+ 1 2
PR4739 3K65R2F-1-GP
VSUM_RC
11KR2F-L-GP
ISL6208CRZ-TGP-U VSUM- 1 2
2
9
3
12 VCC_SENSE X02-20100108 PR4708 1R2F-GP
ISEN1 1 2
2
1
PC4711 PR4760 10KR2F-2-GP

SC330P50V2KX-3GP PC4742 PR4721 ISEN3 1 2
2
SCD01U25V2KX-3GP NTC-10K-26-GP PR4707 10KR2F-2-GP

2
12 VSS_SENSE +PWR_SRC
B B
1
1 2 VSUM-
2
PR4748 715R2F-GP NTC 10K close to Choke of Phase1

PC4701
1
SC1KP50V2KX-1GP PC4727 PC4725 PC4728 PC4726

X01 20091124
1
1
PC4731
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SCD1U25V3KX-GP
Intel support POC (Power On Configuration). DY
2
2
5
6
7
8
+1.05V_VTT
D
D
D
D
SI7686DP-T1-GP
PG4715 PU4707
1 2
PR4737 PR4701 PR4709 PR4732 PR4713 PR4705 PR4769 PR4724 PR4753 GAP-CLOSE-PWR-3-GP
1
G
S
S
S
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
X02-20100116
4
3
2
1
DY DY DY DY
UGATE3 +VCC_CORE
PL4703
2
PHASE3 1 2
H_VID0
H_VID1 IND-D36UH-9-GP
PR4740
2D2R5J-1-GP
5
6
7
8
1
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
H_VID2 PTC4706 PTC4707
D
D
D
D
SIR460DP-T1-GE3-GP
H_VID3 PU4708
PG4701
PG4714
H_VID4 DY
ST330U2VDM-4-GP
ST330U2VDM-4-GP
2
2
1SNUBBER_3
1
H_VID5
H_VID6
2
PM_DPRSLPVR
S
S
S
PSI#
PC4739
SC330P50V2KX-3GP
2
4
3
2
1
PR4715 PR4702 PR4768 PR4743 PR4727 PR4710 PR4706 PR4703 PR4777
1
DY
PHASE3_R
+VCC_CORE_PHASE3
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
2
LGATE3
DY DY DY DY DY
2
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L ISEN3 1 2

PR4763 10KR2F-2-GP
Inductor: 0.36UH PCMC104T-R36MN1R05J Cyntec 1.05mohm/ 68.R3610.20C VSUM+ 1 2
A O/P cap: 330U 2V EEFSX0D221E7 6mOhm 3.0Arms Panasonic/79.33719.20L PR4764 3K65R2F-1-GP A
O/P cap: 220U 2V EEFSX0D331XE 7mOhm 3.4Arms Panasonic/79.22719.90L VSUM- 1 2

PR4747 1R2F-GP
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 ISEN1 1 2
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 PR4719 10KR2F-2-GP
ISEN2 1 2
PR4765 10KR2F-2-GP <Core Design>
Wistron Corporation
Title
ISL62883_CPU_CORE
A2 Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
+PWR_SRC +PWR_SRC_VTT
TPS51218 for +1.05V_VTT
PG4901
1 2
GAP-CLOSE-PWR
PG4902
1 2
+PWR_SRC_VTT
GAP-CLOSE-PWR
PG4903
1 2
X01 EMI stuff 20091118
GAP-CLOSE-PWR
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U25V2KX-GP
D PG4904 X02-20100111 D
1 2
2
PC4906
PC4902
PC4904
PC4903
GAP-CLOSE-PWR
PG4907
1
5
6
7
8
5
6
7
8
1 2 PU4902 PU4903
D
D
D
D
D
D
D
D
DIS(Arrandale 1.05V_VTT)
SIS406DN-T1-GE3-GP
SIS406DN-T1-GE3-GP
GAP-CLOSE-PWR
DY Design Current = 20.57A
X01 30.79A<OCP<36.39A
S
S
S
S
S
S
G
G
37,50 1.05VTT_PWRGD
M96_X01-20091124 PU4901 PC4908 X02-20100116
4
3
2
1
4
3
2
1
PR4902 SCD1U25V3KX-GP
1 11 2D2R3J-2-GP
51218_VTT_TRIP PGOOD GND 51218_VBST_VTT +1.05V_VTT
1 2 2 10 1 251218_VBST_VTT12 1 PL4901 x01 change tolerant 20091117
PR4901 78K7R2F-GP 51218_VTT_EN TRIP VBST 51218_DRVH_VTT
3 9
51218_VTT_VFB EN DRVH 51218_SW_VTT
4 8 1 2
51218_VTT_CCM VFB SW IND-D56UH-12-GP
50,51,89,90 RUNPWROK 1 2 5 7 +5V_ALW
CCM V5IN
GAP-CLOSE-PWR-3-GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
PR4903 0R0402-PAD 6 51218_DRVL_VTT
1
1
DRVL
X02-20091223 PC4910 PC4911 PTC4901 PTC4902
SE330U2VDM-L-GP
SE330U2VDM-L-GP
PC4909 PR4905
DY 2D2R5J-1-GP PG4916
DY
1
1
PR4904 TPS51218DSCR-GP-U1 SC1U10V2KX-1GP
PC4901
DY
SC1KP50V2KX-1GP
2
470KR2F-GP
5
6
7
8
5
6
7
8
PU4904 PU4905
2
151218_SW_GND_VTT 2
D
D
D
D
D
D
D
D
2
SIS402DN-T1-GE3-GP
SIS402DN-T1-GE3-GP
1+1.05V_VTT_VOUT
1 2
DY VTT_SENSE 12
S
S
S
S
S
S
G
G
PR4906
SC330P50V2KX-3GP
4
3
2
1
4
3
2
1
10R2J-2-GP
PC4912
10KR2F-2-GP
PR4907
+3.3V_RUN +3.3V_ALW R1
DY
2
Vout=0.704V*(R1+R2)/R2
2
1
C C
1
PR4909
PR4908 100KR2J-1-GP
10KR2J-3-GP 51218_VTT_VFB
X01
PQ4901
2
2
1 6
20KR2F-L-GP
1
1.05VTT_PWRGD 2 5 H_VTTPWRGD_R
+1.05V_VTT
PR4910
R2
SCD1U10V2KX-5GP
3 4
1
PC4913
1
DY
2
2N7002EDW-GP PR4911
2
84.27002.F3F 1KR2J-1-GP
2
H_VTTPWRGD
H_VTTPWRGD 9
A00 20100329
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D
Frequency setting O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
470K -->290KHz H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037
L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037
200K -->340KHz
100K -->380KHz
39K -->430KHz
B B
A A
<Core Design>
Wistron Corporation
Title
TPS51218_+1.05V_VTT
A2
Berry A00
Date: Tuesday, April 06, 2010 Sheet 49 of 92
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v
+5V_ALW
PR5001
5 S3 Power Reduction X01 20091111
1
5D1R3J-GP
+5V_ALW
x01-20091124
PR5002 PQ5003
2
Modified net name 1 2 TPS51116_VDD G
. .
14K7R2F-L-GP +5V_ALW 18,42 PS_S3CNTRL
D D 0D75V_EN D
.
.
.
1
+5V_ALW
SC1U10V2KX-1GP
1 2 PC5003 1.05VTT_PWRGD 37,49
PC5001
SC1U10V2KX-1GP S
A
1
PC5002 +3.3V_RUN
1
+3.3V_RUN SC1KP50V2KX-1GP PD5001
DY 2N7002E-1-GP
2
+PWR_SRC_1D5V DY PR5016
1
RB551V-30-2GP 100KR2J-1-GP 84.2N702.D31 PR5015
TPS51116_VDD_R PR5018 0R2J-2-GP
K
2
10KR2J-3-GP
DY
16
14
15
PQ5002
2
PR5004 PU5001 +1.5V_RUN_CPU
1
20KR2F-L-GP 1.5V_RUN_CPU_EN# G X02-20091224
ILIM
VDDP
VDDP
. .
2
PR5005
22 TPS51116_VBST 1 2 TPS51116_VBST1 D 0D75V_EN_L 2 PR5019 1 0D75V_EN 9
.
.
.
1
BST
3
13 PR5017 PQ5001 0R0402-PAD
49,51,89,90 RUNPWROK PGD 0R3J-0-U-GP DY 11.5V_RUN_CPU_EN 1 DY PMBS3904-1-GP PR5003
1 2 TPS51116_NC#12 12 21 TPS51116_UGT
2
4K7R2J-2-GP
S
DY 1 DY 2 x01 change tolerant 20091117
NC#12 DH 22,37,42,47,51,89 PM_SLP_S3#
1
PR5006 620KR2F-GP PC5024 0R2J-2-GP
2
2N7002E-1-GP
1
1D5V_EN 11
EN/PSV DY SCD1U10V2KX-5GP PC5004
84.2N702.D31 DY SCD1U10V2KX-5GP
2
0D75V_EN 10 20 TPS51116_PHS
2
VTTEN LX
RT: ASM x01 change tolerant 20091117 23 x01 change tolerant 20091118
+1.5V_SUS VTTIN
TI: Non_ASM
1
PC5005 19 TPS51116_LGT
SC1U6D3V2KX-GP DL
7
+5V_ALW NC#7
X02-20091223
2
PR50081 1M1R2J-GP TPS51116RGER-GP-U +PWR_SRC +PWR_SRC_1D5V

DY 2 1 18 1 2 1D5V_EN PG5002
+1.5V_SUS PGND2 PGND1 22,37 PM_SLP_S4# PR5007 0R0402-PAD
PGND1 17 2 1
C 1 2 TPS51116_TON 4 C
TON
1
PR5009 0R0402-PAD 8 TPS51116_VDDQSNS PC5006 GAP-CLOSE-PWR
VDDQS
2
X02-20091223 DY SCD1U10V2KX-5GP PG5003

PC5007 24 9 TPS51116_VDDQSET 2 1
2
SC1KP50V2KX-1GP VTT FB
DY
1
+0D75V_DDR_P +5V_ALW PR5010 GAP-CLOSE-PWR

2 VTTS x01 change tolerant 20091117
6 1 2 PG5004
VCCA DY
VSSA
2 1
GND
REF
0R2J-2-GP +PWR_SRC_1D5V
GAP-CLOSE-PWR
1
PC5008 PG5006
DY
25
+V_DDR_REF SC1U10V2KX-1GP 2 1
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U25V2KX-GP
SC4D7U25V5KX-GP
PC5014
1TPS51116_REF
PC5009
PC5011
PC5012
PC5013
1 PR5011 2 GAP-CLOSE-PWR
DY
1
0R0603-PAD
5
6
7
8
PU5002
2
D
D
D
D
Design Current = 14.45A
SI7686DP-T1-GP
PC5010 22.71A<OCP< 26.84A
+0D75V_DDR_P SCD033U16V3KX-GP
Design Current = 0.7A
2
G
S
S
S
4
3
2
1
+0D75V_DDR_P +0.75V_DDR_VTT
X02-20100116 +1.5V_SUS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-5GP
PC5016
PC5017
PC5018
PC5015
PG5001 TPS51116_UGT
PL5001
1
2 1 x01 change to 330uF 20091124

TPS51116_VBST1 1 2 TPS51116_PHS 1 2
B B
GAP-CLOSE-PWR
2
PG5016 PC5019
IND-1D5UH-34-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
2 1 SCD1U25V3KX-GP
5
6
7
8
5
6
7
8
PC5020
PC5021
PU5003 PU5004 PTC5002 PTC5001
D
D
D
D
D
D
D
D
1
PG5017
GAP-CLOSE-PWR PR5012
DY DY
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
GAP-CLOSE-PWR-3-GP
2D2R5F-2-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
x01 change tolerant 20091117 DY
2
TPS51116_LGT TPS51116_PHS_SET
S
S
S
S
S
S
G
1
State S3 S5 VDDR VTTREF VTT
4
3
2
1
4
3
2
1
PC5022
S0 Hi Hi On On On DY SC330P50V2KX-3GP
2
S3 Lo Hi On On Off(Hi-Z) TPS51116_VDDQSNS x01 change tolerant 20091117
1
S4/S5 Lo Lo Off Off Off DY
X02-20100201 PR5013 PC5023
30KR2F-GP SC18P50V2JN-1-GP
2
2
TPS51116_VDDQSET
1
VDDQSET VDDQ (V) VTTREF and VTT NOTE
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L PR5014 Close to VFB Pin (pin5)
30KR2F-GP
GND 2.5 VVDDQSNS/2 DDR
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
2
O/P cap: 220U 2V EEFCX0D221ER 15mOhm 2.7Arms PANASONIC/ 79.22719.20L
A H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 <Core Design> A
V5IN 1.8 VVDDQSNS/2 DDR2 L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037
Switching freq-->400KHz
FB Resistors Adjustable VVDDQSNS/2 1.5 V < VVDDQ < 3 V Wistron Corporation
Title
TPS51116_+1.5V_SUS
Custom
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p8v
D
APL5930 for +1.8V_RUN D
+3.3V_ALW +1.8V_RUN_VIN +5V_ALW +1.8V_RUN_VIN
1
PG5107 PC5109 PC5113
PC5110
2 1
DY
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC1U10V2KX-1GP
2
GAP-CLOSE-PW R
PG5106
2 1
Design Current =1.23A +1.8V_RUN_P +1.8V_RUN
GAP-CLOSE-PW R X02-20091223
6
PU5101
VCNTL
49,50,89,90 RUNPW ROK 1 2 1.8V_RUN_POK 7 5
PR5113 0R0402-PAD POK VIN#5 +1.8V_RUN_P PG5105
VIN#9 9
1 2
22,37,42,47,50,89 PM_SLP_S3# 1 2 1D8V_RUN_EN 8 3
EN VOUT#3
SC22U6D3V5MX-2GP
PR5109 0R0402-PAD 4 GAP-CLOSE-PW R
VOUT#4
SC68P50V2JN-1GP
SC22U6D3V5MX-2GP
PG5108
1
16K5R2F-2-GP
PR5111 PC5108 PC5111 PC5112 1 2
2
DY
GND
FB GAP-CLOSE-PW R
2
5912_1.8V_RUN_FB
C APL5930KAI-TRG-GP C
2
SO-8-P
SC4700P50V2KX-1GP
1
PC5114
DY
2
Vout=0.8V*(R1+R2)/R2
1
PR5110
13K3R2F-L1-GP
2
B B
A <Core Design> A
Wistron Corporation
Title
APL5930_+1.8V_RUN
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU.GFX.Regulator
+PWR_SRC +VGFXCORE_PWR_SRC
PG5301
1 2
GAP-CLOSE-PWR
+3.3V_ALW
X02-20091223 PG5303
1 2
1 2
13 GFX_VR_EN PR5310 0R0402-PAD GAP-CLOSE-PWR
PG5305
1 2
51611_VREFF
GAP-CLOSE-PWR
51611_VREFF PG5308
PR5311 1 2
D UMA GAP-CLOSE-PWR
D
51611_VREFF 1 2
90K9R2F-GP PG5311
1 2
6263AGND
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
1 2 +3.3V_RUN GAP-CLOSE-PWR
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
51611_VREFF PC5313 SC2D2U10V3KX-1GP +3.3V_RUN
UMA UMA DY
2
1 2 PC5314
SC68P50V2JN-1GP
UMA 2 UMA DY DY UMA
PR5301
1 UMA
1
PR5312 1K69R2F-2-GP
PR5313
PR5314
PR5315
PR5316
PR5317
PR5318
1
1
A00-20100224 PR5319
1K91R2F-1-GP
DY
10KR2F-2-GP
51611_TRIPSEL
51611_OSRSEL
51611_TONSEL
UMA
1
51611_DROOP
+VGFXCORE_PWR_SRC
51611_VR_ON
51611_VREFF
51611_V5FILT
51611_ISLEW
2
UMA PC5315
SCD22U10V2KX-1GP
2
1
51611_CLKEN
X01 20091121 PC5302 PC5303
UMA
51611_PGOOD
UMA UMA PC5304
33
32
31
30
29
28
27
26
25
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PU5301 SCD1U25V2KX-GP
2
5
6
7
8
DROOP
OSRSEL
TONSEL
TRIPSEL
GND
VREF
V5FILT
ISLEW
VR_ON
D
D
D
D
+5V_ALW Design Current =17.6A
PU5302
1 24 SI7686DP-T1-GP 27.2<OCP<32.15A
GND CLKEN#
51611_CSP 2 23
CSP PGOOD
G
S
S
S
51611_CSN
UMA
3 22 PC5301
4
3
2
1
CSN MODE +CPU_GFX_CORE
X02-20100116
Close to VGA 51611_GSNS
51611_VSNS
4
GNDSNS UMA V5IN
21 UMA
1 2
SC2D2U10V3KX-1GP
DY
5
VSNS TPS51611RHBR-GP DRVL
20 PL5301
1 DY 251611_THERM_R 1 2 51611_THERM 6 19 51611_PHASE 1 2
PR5320 11K8R2F-GP PR5321 NTC-100K-10-GP THERM LL 2D2R3J-2-GP PC5316 IND-D56UH-12-GP
PC5319
SC22U6D3V5MX-2GP
PC5312
SC22U6D3V5MX-2GP
PC5311
SC22U6D3V5MX-2GP
PTC5302
SE330U2VDM-L-GP
1 2 51611_VR_TT 7 18 51611_BOOT 1 2 6236A_BOOT_C 1 2 PR5324
UMA
2D2R3J-2-GP
9 PM_EXTTS#0_C
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PR5322 0R2J-2-GP VR_TT# VBST PR5323 UMA SCD22U16V3KX-2-GP PTC5301
C DY C
1
13 GFX_IMON 51611_UGATE PG5323
8
IMON DRVH
17 UMA DY
DPRSLP
1
PG5322 DY DY DY UMA UMA SE330U2VDM-L-GP
VID6
VID5
VID4
VID3
VID2
VID1
VID0
2
2
5
6
7
8
5
6
7
8
PU5303 PU5304
51611_RF
2
1
D
D
D
D
D
D
D
D
PR5325 PC5317 74.51611.073
9
10
11
12
13
14
15
16
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
UMA
SC470P50V2KX-3GP
18K7R2F-GP
UMA DY
2
SC3300P50V2KX-1GP
1
1
DYPC5318
S
S
S
S
S
S
G
G
UMA
4
3
2
1
4
3
2
1
2
PRN5301
5 4 51611_DPRSLP_1
13 GFX_DPRSLPVR
6 3 51611_VID6
13 GFX_VID6 51611_VID5
13 GFX_VID5
7 UMA 2
51611_VID4
8 1
13 GFX_VID4
SRN0J-7-GP 51611_LGATE
PRN5302
5 4 51611_VID3
6 3
13 GFX_VID1
7 UMA 2
51611_VID0
8 1
13 GFX_VID0
SRN0J-7-GP
Close to choke (L5301)

PR5327 PR5328
51611_CSP 1UMA 2 51611_CSP_R 1 2 51611_CSP_G
UMA
24K3R2F-1-GP
2
330R2F-GP
1
PR5326
UMA PC5320 UMA NTC-100K-10-GP
SC33P50V2JN-3GP
2
1
PC5321 PC5326
1
B PR5330 B
UMA
SCD022U50V3KX-GP
SCD022U50V3KX-GP
51611_CSP_CSN 86K6R2F-GP
DY
2
UMA
1
2
UMA PC5322 PR5331
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L SC33P50V2JN-3GP 29K4R2F-GP
2
I0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D UMA
2
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 PR5332
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 51611_CSN 1 2 51611_CSN_R
UMA X01 20091124
330R2F-GP
PC5323
2
UMA
1
51611_GSNS SC33P50V2JN-3GP
X01-0713
X02-20091223 X01 20091118
1
PC5324
1 PR5333 2
UMA SC33P50V2JN-3GP
0R0402-PAD +CPU_GFX_CORE
2
51611_VSNS
2
6263AGND
PR5334 PC5325
UMA 100R2F-L1-GP-U
UMA
1 2
PG5324
1
SC33P50V2JN-3GP
1 2
13 VCC_AXG_SENSE
GAP-CLOSE-PWR-3-GP
PG5325
1 2
13 VSS_AXG_SENSE
GAP-CLOSE-PWR-3-GP
2
A A
PR5335
UMA 100R2F-L1-GP-U
1
<Core Design>
Wistron Corporation
Title
TPS51611_+GFX_CORE(UMA)
A2
Berry A00
5 4 3 2 1
x02-20091208
SSID = VIDEO SSID = Inverter
+3.3V_RUN_VGA
+3.3V_RUN
3.3V_LCD_RUN DIS
+3.3V_RUN INVERTER POWER
1 2
LVDS CONNECTOR R5404 0R2J-2-GP
1
R5401
GFX_PW R_SRC 1
UMA2 DY10KR2J-3-GP
LCD1 R5407 0R2J-2-GP
48 100R2J-2-GP
2
R5402 1 2 LBKLT_CTL 55
41 50 +LCDVDD
LCD_BRIGHTNESS
2
SCD1U10V2KX-5GP
C5401
3
2
4 C5402
5 Change Poly-fuse +PW R_SRC
SC1U6D3V2KX-GP R5405
42 6
DY100KR2J-1-GP
1
7 3.3V_LCD_RUN GFX_PW R_SRC
8 LCD_BRIGHTNESS
1
9 BLON_OUT_C F5401
10 LCD_CBL_DET#_C 2 1
11 LCD_TST_C
2
12 LVDSB_TX2 55 POLYSW -1D1A24V-GP-U
43 13 LVDSB_TX2# 55 1 2 C5406 C5407
14 LCD_DET_G R5408 100KR2J-1-GP SC1KP50V2KX-1GP SCD1U50V3KX-GP
1
15 LVDSB_TX1 55 RN5401
16 LVDSB_TX1# 55 BLON_OUT_C 1 8 BLON_OUT 37 Main:69.50007.A41
17 LCD_CBL_DET#_C 2 7
18 LCD_TST_C 3 6
LCD_CBL_DET# 37 Second:69.50007.A31
LVDSB_TX0 55 LCD_TST 37
19 LVDSB_TX0# 55 LCD_DET_G 4 5
44 20
21 LVDSB_TXC 55 SRN100J-4-GP
22 LVDSB_TXC# 55
23
24 LVDSA_TXC 55
25 LVDSA_TXC# 55
26
45 27 LVDSA_TX2 55
28 LVDSA_TX2# 55
29
30 LVDSA_TX1 55
31 LVDSA_TX1# 55
32
33 LVDSA_TX0 55
46 34 LVDSA_TX0# 55
35 GPU_LVDS_DATA 20,82
36 GPU_LVDS_CLK 20,82 A00-20100204
37
38 USB_CAMERA# 1 2 USB_PN13 21
39 USB_CAMERA R5409 1 2 0R0603-PAD USB_PP13 21
40 +3.3V_CAMERA R5411 0R0603-PAD
47 51
49
SSID = VIDEO
IPEX-CONN40-2R-GP-U +3.3V_RUN
LCD POWER +LCDVDD
For Camera GND
Q5401
20.F1093.040 1 D D 6
2 D D 5
3 G S 4
Close to LVDS connector
+15V_ALW 1 2 SI3456DDV-T1-GE3-GP
R5412 330KR2J-L1-GP
1
LVDSB_TXC#
FPVCC_CTL1
1 2
C5409 SCD1U25V2KX-GP R5416
LVDSB_TXC 150R3J-L-GP
Camera Power LVDSA_TXC#
2 DY 100KR2J-1-GP
1
2
+3.3V_RUN
X02-20091222 +3.3V_CAMERA
LCD_BRIGHTNESS R5406 Q5402
LVDSA_TXC 4 3 LCDVDD_1
LCD_TST_C
1
1 R5414 2 EC5406 EC5407 EC5408 EC5409 5 2

SC33P50V2JN-3GP
SC33P50V2JN-3GP
0R0603-PAD
EC5401
DY DY DY DY
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
EC5402 6 1
2
2
1
EC5405
SCD1U10V2KX-5GP C5403 DY DY 2N7002EDW -GP
DY
2
SC10U6D3V5MX-3GP
84.27002.F3F
2
55 LCDVDD_EN
+5V_ALW 1 2
R5415 100KR2J-1-GP
1
For EMI request Q5403
x01 change tolerant 20091117 3 FPVCC_CTL3
D5401 3 LCDVCC_EN 1 R1
2
BAT54C-U-GP R2
PDTC144EU-1-GP
2
X01 change part-20091116
37 LCD_TST_EN <Core Design>
Wistron Corporation
Title
LCD/Inverter Connector
A3
Berry A00
5 4 3 2 1
LVDS Channel A Panel BL brightness/Power En/BL En

RN5501
20 PCH_LVDSA_TX2# 5 4 LVDSA_TX2# 54
20 PCH_LVDSA_TX2 6 3 LVDSA_TX2 54 RN5502
20 PCH_LVDSA_TXC# 7 2 LVDSA_TXC# 54 5 4
20 PCH_LVDSA_TXC 8 1 LVDSA_TXC 54 20 PCH_VGA_BLEN 6 3 PANEL_BLEN 37
SRN0J-7-GP 20 PCH_LCDVDD_EN 7 UMA 2 LCDVDD_EN 54
UMA 20 PCH_LBKLT_CTL 8 1 LBKLT_CTL 54
D Impedance:85 ohm SRN0J-7-GP D
RN5503
Impedance:90 ohm
82 GPU_LVDSA_TX2# 4 5
82 GPU_LVDSA_TX2 3 6
82 GPU_LVDSA_TXC# 2 7 RN5504
82 GPU_LVDSA_TXC 1 8 82 VGA_BLEN 5 4
82 VGA_LBKLT_CTL 6 3
DIS SRN0J-7-GP 7 DIS 2
82 VGA_LCDVDD_EN
Impedance:100 ohm 8 1
RN5507 SRN0J-7-GP
20 PCH_LVDSA_TX0 6 3 LVDSA_TX0 54
20 PCH_LVDSA_TX1 8 1 LVDSA_TX1 54
UMASRN0J-7-GP
Impedance:85 ohm
RN5508
4 5
Impedance:90 ohm
82 GPU_LVDSA_TX0# LVDSA_TX0# 54
82 GPU_LVDSA_TX0 3 6 LVDSA_TX0 54
82 GPU_LVDSA_TX1# 2 7 LVDSA_TX1# 54
82 GPU_LVDSA_TX1 1 8 LVDSA_TX1 54
DISSRN0J-7-GP
Impedance:100 ohm
C C
LVDS Channel B
RN5505
20 PCH_LVDSB_TXC# 5 4 LVDSB_TXC# 54
20 PCH_LVDSB_TXC 6 3 LVDSB_TXC 54
20 PCH_LVDSB_TX0# 7 2 LVDSB_TX0# 54
20 PCH_LVDSB_TX0 8 1 LVDSB_TX0 54
UMA SRN0J-7-GP
Impedance:85 ohm
Impedance:90 ohm
RN5510
82 GPU_LVDSB_TXC# 4 5 LVDSB_TXC# 54
82 GPU_LVDSB_TXC 3 6 LVDSB_TXC 54
82 GPU_LVDSB_TX0# 2 7 LVDSB_TX0# 54
82 GPU_LVDSB_TX0 1 8 LVDSB_TX0 54
DISSRN0J-7-GP
B
Impedance:100 ohm B
RN5509
UMASRN0J-7-GP
Impedance:85 ohm
Impedance:90 ohm
RN5506
DIS SRN0J-7-GP
Impedance:100 ohm
A A
<Core Design>
Wistron Corporation
Title
LVDS_Switch
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
Title
LVDS_Switch
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO HDMI Level Shifter & CONNECTOR

+3.3V_RUN
HDMI CONN +3.3V_RUN
HDMI1
1
22
1
1
20 UMA R5709
R5702 R5701 1 HDMI_DATA2 20KR2J-L2-GP
DY 4K7R2J-2-GP
+3.3V_RUN 4K7R2J-2-GP 2
DY
2
x01 change to 10V tolerant 20091117 3 HDMI_DATA2# HDMI_OE#
2
2
HDMI_DATA1
Impedance:100 ohm 4
5
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
HDMI_CCT2
HDMI_CCT1
C5717 C5716 C5715 C5714 C5701 6 HDMI_DATA1#
D
7 HDMI_DATA0
D UMA UMA UMA UMA UMA 8
UMA . Q5701 D
2
2
9 HDMI_DATA0# 2N7002E-1-GP
10 HDMI_CLK .
11 . .
. 84.2N702.D31
HDMI_CLK#
11
15
21
26
33
40
46
35
34
12
2
U5701
Close to HDMI Connector 13
S
14
NC#35
NC#34
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
15 DDC_CLK_HDMI +5V_RUN
SRN0J-6-GP RN5703 16 DDC_DATA_HDMI HPD_HDMI_CON
38 23 HDMI_LS_TXC# 1 4 HDMI_CLK# 17
20,82 HDMI_PCH_CLK# IN_D1- OUT_D1- HDMI_LS_TXC HDMI_CLK
39 22 2 3 18
20,82 HDMI_PCH_CLK IN_D1+ OUT_D1+ UMA RN5704 19
1
41 20 HDMI_LS_TX0# SRN0J-6-GP
1 4 HDMI_DATA0# 21 C5705
20,82 HDMI_PCH_DATA0# IN_D2- OUT_D2- HDMI_LS_TX0 HDMI_DATA0 SCD1U10V2KX-5GP
20,82 HDMI_PCH_DATA0
42
IN_D2+ OUT_D2+
19 2
UMA 3 23
HPD_HDMI_CON
RN5706
2
44 17 HDMI_LS_TX1# SRN0J-6-GP
1 4 HDMI_DATA1# SKT-HDMI19P-69-GP
20,82 HDMI_PCH_DATA1# IN_D3- OUT_D3- HDMI_LS_TX1 HDMI_DATA1
45
IN_D3+ OUT_D3+
16 2
UMA 3 x01 change tolerant 20091117
RN5707
+3.3V_RUN 20,82 HDMI_PCH_DATA2#

47
IN_D4- OUT_D4-
14 HDMI_LS_TX2# SRN0J-6-GP
1 4 HDMI_DATA2# 22.10296.211 +3.3V_RUN_VGA
48 13 HDMI_LS_TX2 2 3 HDMI_DATA2
UMA
R5703
HDMI_PC0
IN_D4+
UMA OUT_D4+
2 UMA 1 4K7R2J-2-GP 3 8 PCH_HDMI_DATA 20

PC0 SDA
3
R5704 1 4K7R2J-2-GP HDMI_PC1 DIS
2
DY 4
PC1 SCL
9
7
PCH_HDMI_CLK 20
HDMI_PCH_DET 20 1 2HDMI_HPD_B 1 Q5702
R5705 HPD R5711 150KR2J-L1-GP PMBS3904-1-GP
DIS
1
2 UMA 1 HDMI_REXT 6
2
1
1
499R2F-2-GP REXT HPD_HDMI_CON R5707
10 30
R5706 HDMI_OE# 25
RT_EN# HPD_SINK
29 DDC_DATA_HDMI DY 20KR2J-L2-GP R5710 HDMI_HPD_DET 82
OE# SDA_SINK
4K7R2J-2-GP DY 1 UMA 2 HDMI_DDC_EN 32 28 DDC_CLK_HDMI
+3.3V_RUN 200KR2J-L1-GP
DY
1
R5708 4K7R2J-2-GP DDC_EN SCL_SINK
2
R5712 DIS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
2
10KR2J-3-GP
PS8101-GP
Change from 5.1K to 4.7K.
1
5
12
18
24
27
31
36
37
43
49
2
1st Parade 71.P8101.003
2nd Pericom 71.03411.B03
C C
HDMI DISCRETE/ UMA Co-lay Impedance:100 ohm +3.3V_RUN_VGA +5V_RUN
Close to Level Shift x01 change tolerant 20091117
4
3
4
3
RN5702
RN5708 SRN0J-6-GP SRN2K2J-1-GP RN5701
HDMI_PCH_CLK# 2 3 HDMI_CLK#_R C5706 1DIS 2 SCD1U10V2KX-5GP HDMI_CLK# +3.3V_RUN_VGA SRN1K5J-GP
HDMI_PCH_CLK 1 4 DIS HDMI_CLK_R C5707 1DIS 2 SCD1U10V2KX-5GP HDMI_CLK DY
+5V_RUN
U5702 5V Tolerance
HDMI_PCH_DATA0# 2 3 HDMI_DATA0#_R C5708 1DIS 2 SCD1U10V2KX-5GP HDMI_DATA0#
DIS
1
2
1
2
HDMI_PCH_DATA0 1 4 HDMI_DATA0_R C5709 1DIS 2 SCD1U10V2KX-5GP HDMI_DATA0 1 2
1OE 1A GPU_HDMI_CLK 82
7 5 GPU_HDMI_DATA 82
RN5709 SRN0J-6-GP 2OE 2A
8
DY
RN5710 SRN0J-6-GP VCC DDC_CLK_HDMI
3
HDMI_PCH_DATA1# HDMI_DATA1#_R C5713 SCD1U10V2KX-5GP HDMI_DATA1# 1B DDC_DATA_HDMI
2 3 1DIS 2 4 6
HDMI_PCH_DATA1 1 DIS 4 HDMI_DATA1_R C5710 1DIS 2 SCD1U10V2KX-5GP HDMI_DATA1 GND 2B
HDMI_PCH_DATA2# 2 3 HDMI_DATA2#_R C5711 1DIS 2 SCD1U10V2KX-5GP HDMI_DATA2# TSCBTD3305CPWR-GP

HDMI_PCH_DATA2 1 DIS 4 HDMI_DATA2_R C5712 1DIS 2 SCD1U10V2KX-5GP HDMI_DATA2
RN5711 SRN0J-6-GP
RN5705
Close to HDMI Connector
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
GPU_HDMI_CLK 2 3
DIS
1
1
GPU_HDMI_DATA
Impedance:100 ohm Impedance:100 ohm 1 4
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS SRN0J-6-GP
2
2
R5715
R5716
R5717
R5718
R5719
R5720
R5721
R5722
HDMI_PLL_GND
D
DIS . Q5703
2N7002E-1-GP
B B
.
.
. . 84.2N702.D31
+5V_RUN
G
S
1
R5714
DY 100KR2J-1-GP
2
A A
<Core Design>
Wistron Corporation
Title
HDMI Level Shifter/Connector

A2
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
ITP Connector
H_CPURST# use pull-up Resistor close
D D
ITP connector 500 mil ( max ),
others place near CPU side.
CPU ITP Connector

TCK(PIN 5)
TCK(PIN AC5)
FBO(PIN 11)
C C
SSID = Thermal
Fan Connector
B B
3 1
*Layout* 15 mil
FAN1
5
39 EMC2102_FAN_TACH 3
AFTP5801 1 2
39 EMC2102_FAN_DRIVE 1
4
AFTP5802 1 EMC2102_FAN_TACH
FOX-CON3-6-GP-U
AFTP5803 1 EMC2102_FAN_DRIVE
K
1
D5801
C5801 RB551V-30-2GP
SC10U6D3V5MX-3GP
2
20.D0210.103
A <Core Design> A
Wistron Corporation
Title
Size
ITP/Fan Connector
Document Number Rev
A3
Berry A00
5 4 3 2 1
SSID = SATA
SATA HDD Connector
+3.3V_RUN
1
HDD1
C5904 C5901
SC10U6D3V5MX-3GP DY DY SCD1U10V2KX-5GP P1 16
2
V33 16
P2 V33 17 17
P3 V33 18 18
+5V_RUN P7 V5
P8 V5
1
P9 V5
C5905 C5906
SC10U10V5KX-2GP SCD1U10V2KX-5GP P13 S1
2
V12 GND
P14 V12 GND S4
x01 Change tolerant 20091117 P15 V12 GND S7
P4
GND
GND P5
24 SATA_TXP0 S2 A+ GND P6
24 SATA_TXN0 S3 A- GND P10
GND P12
24 SATA_RXP0_C C5903 1 2 SCD01U16V2KX-3GP SATA_RXP0 S6
C5902 B+
24 SATA_RXN0_C 1 2 SCD01U16V2KX-3GP SATA_RXN0 S5 B- DAS/DSS P11
SKT-SATA7P-15P-17-GP
62.10065.C71
ODD Connector
ODD1
8
NP1
S1
S2 SATA_TXP1 24
S3 SATA_TXN1 24 SATA_RX- and SATA_RX+ Trace
S4
S5 SATA_RX1-_C C5907 1 2SCD01U16V2KX-3GP
Length match within 20 mil
SATA_RXN1_C 24
S6 SATA_RX1+_C C5908 1 2SCD01U16V2KX-3GP SATA_RXP1_C 24
S7
x01 Change tolerant 20091117 +5V_RUN
P1
P2
P3
1
P4 C5910
P5 C5909 SC10U10V5KX-2GP
P6 SCD1U10V2KX-5GP
2
2
NP2
9
SKT-SATA7P+6P-42-GP
62.10065.581 <Core Design>
Wistron Corporation
Title

HDD/ODD Rev
A3
Berry A00
5 4 3 2 1
SSID = AUDIO
Speaker LINE1
Connector OUT
D D
A00-20100406
5
SPK1
FOX-CON4-24-GP
BLM18BD601SN1D-GP
1 AUD_HP1_JD#
30 AUD_SPK_L- 30 AUD_HP1_JD# L6001 LINEOUT1
2 AUD_HP1_JACK_L2 1 2 AUD_HP1_JACK_L1 6
30 AUD_SPK_L+ 30 AUD_HP1_JACK_L2
30 AUD_SPK_R- 3 5
4 AUD_HP1_JACK_R2 1 2 AUD_HP1_JACK_R1 2
30 AUD_SPK_R+ 30 AUD_HP1_JACK_R2 L6002 BLM18BD601SN1D-GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
EC6007
EC6008
4
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SC100P50V2JN-3GP
1
EC6005 EC6006 1
6
1
1
SC1KP50V2KX-1GP SC1KP50V2KX-1GP
EC6001
EC6002
EC6003
EC6004
3
2
DY DY DY DY 7
2
SEC. 20.F0693.004 X01 modify to GND 20091120 8
2
2 PHONE-JK383-GP
1 1 AUD_HP1_JD#
AFTP6002 AFTP6003
AFTP6001 1 AUD_SPK_L- 1 AUD_HP1_JACK_L1
x02-20091224
AFTP6005
AFTP6007
1 AUD_SPK_L+
AUD_SPK_R-
AFTP6004
AUD_HP1_JACK_R1
600ohm 100MHz AFTP6006 1 22.10133.K31
1 1
AFTP6009 1 AUD_SPK_R+ AFTP6008 200mA 0.5ohm DC
C C
X01 modify to GND 20091120

MIC IN
30 AUD_VREFOUT_B
2
1
RN6001
Internal
SRN4K7J-8-GP
Microphone
3
4
MICIN1
8
MIC1 is in DIP
X02-20091222 7
3
1 1 MIC1
MIC_IN_L_C 30 INT_MIC_L_R MICROPHONE-40-GP-U1
30 MIC_IN_L 2 1 4
R6001 0R0603-PAD
23.42143.001
2
1
2
5 EC6009
2 1 MIC_IN_R_C 6 SC1KP50V2KX-1GP
2
B 30 MIC_IN_R R6002 0R0603-PAD B
PHONE-JK383-GP
30 EXT_MIC_JD#
22.10133.K31
1
EC6011
EC6010
2
SC100P50V2JN-3GP 1 AFTP6010
SC100P50V2JN-3GP
1 MIC_IN_L_C DY
1 2
AFTP6011 EC6012 SCD1U10V2KX-5GP
1 MIC_IN_R_C
AFTP6012 1 2
1 EXT_MIC_JD# EC6013 SCD1U10V2KX-5GP
AFTP6013
X01 modify to GND 20091120 1 2
EC6014 SCD1U10V2KX-5GP
X02-20100206 DY
1 2
1 2
A <Core Design> A
DY
1 2
Wistron Corporation
Title
Audio Jack
A3
Berry A00
Date: Monday, April 26, 2010 Sheet 60 of 92
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = Flash.ROM
SPI FLASH ROM (4M byte) for PCH +3.3V_RUN
+3.3V_RUN
1
C6202
D
C6201 DY SCD1U10V2KX-5GP
D
8
7
6
5
SC10U6D3V5MX-3GP
2
RN6201
SRN4K7J-10-GP
1
2
3
4
PCH_SPI_HOLD_0#
+3.3V_RUN
U6201
24 PCH_SPI_CS0# PCH_SPI_CS0# 1 8
PCH_SPI_DI_R CS# VCC PCH_SPI_HOLD_0#
24 PCH_SPI_DI 1 2 2 SO NC#7 7
PCH_SPI_W P# 3 6 PCH_SPI_CLK 24
R6202 WP# SCK
4 GND SI 5 PCH_SPI_DO 24
15R2J-GP
1
DY
1
EC6202 MX25L3205DM2I-12G-GP
SC4D7P50V2CN-1GP 2 EC6203 DY DY EC6204
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
2
C +KBC_PW R C
SPI FLASH ROM (256K byte) for KBC

+KBC_PW R
1
C6204
SC10U6D3V5MX-3GP
X02 20091221 DY
2
1
4
3
R6203 RN6202
100KR2J-1-GP
DY SRN100KJ-6-GP
2
1
2
EC_SPI_HOLD#
U6202 +KBC_PW R
37 EC_SPI_CS# 1 CS# VCC 8

37 EC_SPI_DI R6205 1 2 0R0402-PAD EC_SPI_DI_R 2 7 EC_SPI_HOLD#
R6206 0R0402-PAD EC_SPI_W P# SO HOLD#
37 EC_SPI_W P#_R 1 2 3 WP# SCLK 6 EC_SPI_CLK 37
4 GND SI 5 EC_SPI_DO 37
1
1
1
EC6201 R6208 MX25L2005C-12G-GP
B SC4D7P50V2CN-1GP DY DY 100KR2J-1-GP R6201 EC6205 DY DY EC6206 B
2
10KR2J-3-GP SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP

2
2
1
X02-20091221
+3.3V_RTC_LDO
U6203
+RTC_CELL
SSID = RBATT 2
+RTC_VCC
3 RTC1
R6210
1 RTC_PW R 1 2 1 PWR
2
2 GND
C6205 1KR2J-1-GP NP1
SC1U6D3V2KX-GP SDMG0340LC7F-GP-U NP1
NP2
1
NP2
1
AFTP6203
A Width=20mils BAT-CON2-1-GP-U <Core Design> A
62.70001.011 Wistron Corporation

1 +RTC_VCC Taipei Hsien 221, Taiwan, R.O.C.
AFTP6202
Title

Flash/RTC Rev
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = USB
Close to I/O connector
IO Board USB Power
Support 2A
+5V_ALW +5V_USB1
U6301
at least 80 mil
D at least 80 mil 1 GND VOUT#8 8 D
2 VIN VOUT#7 7
3 VIN VOUT#6 6
1
37 USB_PW R_EN# 4 EN# OC# 5
1
C6301 C6302
DY
SCD1U10V2KX-5GP
SC1U10V2KX-1GP
USB POWER SW
2
UP7534BRA8-15-GP
2
Main UP7534BRA8-15 P/N:74.07534.079
SEC AP2101MPG-13 P/N: 74.02101.079 USB_OC#8_9 21
CRT Board USB Power
Close to CRT Board connector

C C
Support 2A
+5V_ALW +5V_USB2
U6302
at least 80 mil
at least 80 mil 1 GND VOUT#8 8
2 VIN VOUT#7 7
3 VIN VOUT#6 6
1
37 USB_PW R_EN# 4 EN# OC# 5
1
C6303 C6304
DY
SCD1U10V2KX-5GP
SC1U10V2KX-1GP
2
UP7534BRA8-15-GP
2
USB_OC#0_1 21
B B
<Core Design>
A A
Wistron Corporation
Title
USB Power SW
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Reserved
A4 Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
Power LED(White)
+5V_ALW
Q6602
R2
E
PW RLED#_C B R1
D C LED_PW R 2 1 PW R_LED_B D
R6601 1KR2J-1-GP
1
EC6601
PDTA143ET-GP
RN6601 1 POW ER_SW _LED_B
W HITE_LED_BAT# DYSC220P50V2KX-3GP 2
R6603 1KR2J-1-GP
1 4
84.00143.M11
2
37 W HITE_LED#_KBC SATA_LED#_C
24 SATA_LED# 2 3
2 1 POW ER_SW _LED_C
SRN15KJ-3-GP R6609 1KR2J-1-GP
RN6602
X02-20100203
37 AMBER_LED#_KBC
37 PW RLED#
1
2
4
3
AMBER_LED_BAT#
PW RLED#_C SATA HDD LED(White)
SRN15KJ-3-GP +5V_RUN
Q6601
X02-20100108 R2
E
SATA_LED#_C B R6604
R1
C SATA_LED_R 2 1 SATA_LED
1KR2J-1-GP
SC220P50V2KX-3GP
1
EC6604
PDTA143ET-GP
DY
84.00143.M11
2
C Battery LED1(White) C
+5V_ALW
Q6603
R2
E LEDBD1
W HITE_LED_BAT# B R6602 7
R1
C W HITE_LED_BAT 2 1 BAT_W HITE
1KR2J-1-GP PW R_LED_B 1
SC220P50V2KX-3GP
1
EC6602
PDTA143ET-GP SATA_LED
DY BAT_W HITE
2
84.00143.M11 3
2
BAT_AMBER 4
5
6
8
Battery LED2(Amber) ACES-CON6-13-GP
+5V_ALW
Q6604
R2
E
AMBER_LED_BAT# B R6606
R1
C AMBER_LED_BAT 1 2 BAT_AMBER
1KR2J-1-GP
PDTA143ET-GP
1 EC6603
B 84.00143.M11 DY 2
SC220P50V2KX-3GP B
Power button LED(White)
37 KBC_PW RBTN# 1 2 PW RBTN1

R6605 100R2J-2-GP 5
KBC_PW RBTN#_C
X01 20091111 +5V_ALW A00-20100203 POW ER_SW _LED_C
2
3
POW ER_SW _LED_B 4
Q6605
R2 A00-20100205 6
1
DY 2 PW R_BTN_LED#_C B
E
37 PW R_BTN_LED# R6607 15KR2J-1-GP
R1
POW ER_SW _LED_R 2 POW ER_SW _LED_C
DY 100R2J-2-GP ACES-CON4-10-GP-U
DY C 1
R6610
A
PDTA143ET-GP
20.K0320.004 <Core Design> A
1 DY 2 POW ER_SW _LED_B

R6608 100R2J-2-GP
84.00143.M11 Wistron Corporation
Title
LED Bard/Power Button

A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = KBC SSID = Touch.Pad
D
Internal KeyBoard Connector TouchPad Connector
D
A00-20100203
KB1 1 AFTP6801
31
1 KB_DET# 37
2 KROW 7 1
3 KROW 6 1 AFTP6802
4 KROW 4 1 AFTP6803 +5V_RUN
5 KROW 2 1 AFTP6804
6 KROW 5 1 AFTP6805 +5V_RUN
7 KROW 1 1 AFTP6806 x01 change tolerant 20091117
8 KROW 3 1 AFTP6807
9 KROW 0 1 AFTP6808
1
10 KCOL5 1 AFTP6809 C6801
2
1
11 KCOL4 1 AFTP6810 SCD1U10V2KX-5GP
12 KCOL7 1 AFTP6811 KROW [0..7] 37 RN6801
2
13 KCOL6 1 AFTP6812 SRN10KJ-5-GP
14 KCOL8 1 AFTP6813
15 KCOL3 1 AFTP6814 KCOL[0..16] 37 TPAD1
16 KCOL1 1 AFTP6815 6
3
4
17 KCOL2 1 AFTP6816
18 KCOL0 1 AFTP6817 4
19 KCOL12 1 AFTP6818 37 TPCLK 3
C 20 KCOL16 1 AFTP6819 37 TPDATA 2 C
21 KCOL15 1 AFTP6821
22 KCOL13 1 AFTP6823 1
1
KCOL14 AFTP6822
23
24 KCOL9
1
1 AFTP6824 C6802 DY DY C6803 5
25 KCOL11 1 AFTP6825 SC33P50V2JN-3GP SC33P50V2JN-3GP
2
26 KCOL10 1 AFTP6826 1 ACES-CON4-10-GP-U
27 AFTP6827 AFTP6820
28
29
20.K0320.004
30 1
32 AFTP6828
1 +5V_RUN
ACES-CON30-8-GP AFTP6829 1 TPCLK
AFTP6830 1 TPDATA
AFTP6831
A00-20100205
KB Backlight Connector B
+5V_RUN +5V_KB_BL
L6801
F6801
KB_LED_PW R 1
1
DY 2
DY 2
1
C6804 FUSE-D5A6V-2-GP BLM18PG181SN1D-GP C6805

SCD1U10V2KX-5GP 20.K0320.004
DY DY
SC10U10V5KX-2GP
1
DY 2
2
R6802 0R2J-2-GP KBLIT1

5
R6804 1
DY 2KB_LED_DET_C
37 KB_LED_BL_DET 1
100R2J-2-GP
2
3
DY
1
4
1
R6803 C6806
KB_BL_CTRL#
SCD1U10V2KX-5GP
+5V_KB_BL
100KR2J-1-GP DY DY 6
KB_LED_BL_DET
1
1 AFTP6832
2
KB_BL_CTRL# 1 AFTP6833
2
ACES-CON4-10-GP-U AFTP6834
1
AFTP6835
D
A <Core Design> A
Q6801
DY P8503BMG-GP
37 KB_BL_CTRL G
Wistron Corporation
1

S
R6801 Taipei Hsien 221, Taiwan, R.O.C.

DY 100KR2J-1-GP
Title
Key Board/Touch Pad

2

A3
Berry A00
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
AFTP6901 1 +3.3V_ALW
AFTP6902 1 LID_CLOSE#_1
D x01 Change tolerant 20091117 D
1
+3.3V_ALW C6903
SCD1U10V2KX-5GP
2
1
R6901 HALLSW1
DY 100KR2J-1-GP
2 VDD
1
2
LID_CLOSE# LID_CLOSE#_1 VSS
37 LID_CLOSE# 2 1 3 OUT
R6902 0R0402-PAD
1
C6902 X02-20091223 S-5711ACDL-M3T1S-GP
DY SCD047U16V2KX-1-GP
2
AFTP6903 1
C C
B B
<Core Design>
A
Title
Hall Sensor
A4
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_RUN
DB1
1
24,37 LPC_LAD0 2
24,37 LPC_LAD1 3
24,37 LPC_LAD2 4
24,37 LPC_LAD3 5
24,37 LPC_LFRAME# 6
7
DY
9,21,37,76,78,80 PLT_RST#
8
21 PCLK_FWH 9
10
11
12
C MLX-CON10-7-GP C
20.D0183.110
B B
<Core Design>
A
Title
Dubug connector
A4
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Size
RESERVED
Document Number Rev
A4 Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
RESERVED
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D Bluetooth Module conn. D
BT1
15
NP1
AFTP7301 1 BLUETOOTH_DET# 1 2 BT_ACT +3.3V_RUN
W LAN_ACT 3 4 x01 change tolerant 20091118

AFTP7302 1 BDC_ON 5 6 USB_PP5
BLUETOOTH_EN 7 8 USB_PN5
AFTP7304 1 BT_LED 9 10
1
AFTP7305 1 BLUETOOTH_GPIO3 11 12 C7301
AFTP7314 1 BLUETOOTH_GPIO5 13 14
NP2 SC2D2U6D3V3KX-GP
2
16
1 AFTP7313
HRS-CONN14D-GP-U
20.F0987.014
21 USB_PP5 AFTP7316 1 W LAN_ACT

21 USB_PN5 AFTP7317 1 BLUETOOTH_EN
76 BT_ACT BT_ACT AFTP7315 1 BT_ACT
37 BLUETOOTH_EN BLUETOOTH_EN AFTP7318 1 +3.3V_RUN
76 W LAN_ACT W LAN_ACT AFTP7319 1 USB_PP5
AFTP7320 1 USB_PN5
C C
EC7302
SC220P50V2KX-3GP
10KR2J-3-GP
100KR2J-1-GP
1
1
1
R7303
R7304
DY DY
2
2
B B
A <Core Design> A
Wistron Corporation
Title
Bluetooth
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Reserved
A4
Berry A00
5 4 3 2 1
5 4 3 2 1
IO Board CONN 80 pin
IOBD1
85 NP1
86 84
21 USB_PP9 2 1
D USB(ESATA) SATA_TXN4 24
D
21 USB_PN9 4 3 SATA_TXP4 24
SATA(ESATA)
6 5
21 USB_PP11 8 7 SATA_RXN4_C 24
WWAN USB 21 USB_PN11 10 9 SATA_RXP4_C 24
SATA(ESATA)
12 11
21 USB_PN8 14 13
USB1 21 USB_PP8 16 15
PCIE_TXP2 23
18 17
PCIE_TXN2 23 WLAN PCIE
21 USB_PP2 20 19
WLAN USB 21 USB_PN2 22 21
PCIE_RXP2 23
PCIE_RXN2 23
WLAN PCIE
24 23
37 E51_RXD 26 25 CLK_PCIE_W LAN 23
37 E51_TXD 28 27
30 29
CLK_PCIE_W LAN# 23 WLAN CLK
23 PCIE_RXP4 32 31
WWAN PCIE 23 PCIE_RXN4 34 33
CLK_PCIE_LAN 23
36 35
CLK_PCIE_LAN# 23 LAN CLK
23 PCIE_TXP4 38 37
WWAN PCIE 23 PCIE_TXN4 40 39
CLK_PCIE_W W AN 23
42 41
CLK_PCIE_W W AN# 23 WWAN CLK
7,18,19,23 PCH_SMBDATA 44 43
WWAN/WLAN SMBUS 7,18,19,23 PCH_SMBCLK 46 45 at least 80 mil
48 47 +5V_USB1
+DC_IN_SS 50 49 +5V_ALW
52 51
54 53 +3.3V_RUN
56 55
58 57
C 60 59 C
37 W IFI_RF_EN 62 61 +3.3V_ALW
23 W W AN_CLKREQ# 64 63 +1.5V_RUN
37 W W AN_RADIO_DIS# 66 65 A00-20100203
37 PSID_DISABLE# 68 67 PM_LAN_ENABLE 37
X02-20091230 70 69 PLT_RST# 9,21,37,70,78,80
23 PCIE_RXP3 72 71 W LAN_CLKREQ# 23
LAN PCIE 23 PCIE_RXN3 74 73 PCIE_W AKE# 22
76 75 BT_ACT 73
23 PCIE_TXP3 78 77 W LAN_ACT 73
LAN PCIE 23 PCIE_TXN3 80 79 PSID_EC 37
83 81
82 NP2
ACES-CONN80D-GP
20.F1009.080
B B
A <Core Design> A
Wistron Corporation
Title
Size
IO Board Connector
Document Number Rev
A3 Berry A00
5 4 3 2 1
5 4 3 2 1
CRT Board Connector A00-20100120

CRTBD1
21 USB_PN1_C
USB_PN1 21
1
at least 80 mil
2 +5V_USB2
3
3
4 +5V_RUN
5 USB_PN1_C
6 USB_PP1_C USB3 PORT
7
8 USB_PN0_C
9 USB_PP0_C USB2 PORT FILTER-130-GP
10 TR7701
D 11 CRT_R D
4
12
13 CRT_G
14 CRT RGB USB_PP1_C
USB_PP1 21
15 CRT_B
16
17 CRT_HSYNC_CON USB_PN0_C
18 CRT_VSYNC_CON CRT H/VSYNC USB_PN0 21
19 CRT_DDCCLK_CON
20 CRT_DDCDATA_CON CRT SMBUS
3
22
TR7702
FILTER-130-GP
ACES-CON20-1-GP-U
20.F0772.020
SEC. 20.F1035.020
4
USB_PP0_C
USB_PP0 21
CRT RGB X01 20091111 L7701 X02-20100108

CRT_RED CRT_R
Close to CRT Board CONN 1 2
FCM1608CF-220T05-GP
Filter design on CRT Board
L7702
RN7701 CRT_GREEN 1 2 CRT_G
1 8 CRT RGB FCM1608CF-220T05-GP
2 7 CRT_RED
82 VGA_CRT_RED CRT_GREEN L7703
3 6
82 VGA_CRT_GREEN
4
DIS 5 CRT_BLUE CRT_BLUE 1 2 CRT_B
C
82 VGA_CRT_BLUE FCM1608CF-220T05-GP C
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SRN0J-7-GP
8
7
6
5
1
C7703 C7704 C7705
C7706
C7707
C7708
RN7702 RN7708 DY DY DY
SC8P250V2CC-GP
SC8P250V2CC-GP
SC8P250V2CC-GP
2
2
1 8
2 7 SRN150F-1-GP
20 PCH_CRT_RED
3
UMA 6
1
2
3
4
20 PCH_CRT_GREEN
4 5
20 PCH_CRT_BLUE
SRN0J-7-GP
CRT DDCDATA & DDCCLK level shift CRT Hsync & Vsync level shift Close to CRT Board CONN
+3.3V_RUN
Pull High 5V Design on CRT Board
A00-20100120
2
1
RN7707 +3.3V_RUN RN7703

3.3V Tolerance SRN0J-6-GP
UMA SRN2K2J-1-GP
RN
1 4 CRT_HSYNC_IN
80,82 VGA_CRT_HSYNC
RN7706
Need Level Shift 80,82 VGA_CRT_VSYNC 2
DIS 3
1 4 CRT_HSYNC_CON
3
4
Q7701 2 3 CRT_VSYNC_CON
4 3 CRT_DDCDATA_CON 2 3 0R4P2R-PAD
20 PCH_CRT_DDCDATA 20 PCH_CRT_HSYNC
1 4 CRT_VSYNC_IN
5 2
20 PCH_CRT_VSYNC UMA
RN7704
20 PCH_CRT_DDCCLK UMA
6 1
2.5V Tolerance? SRN33J-5-GP-U
2N7002EDW-GP X02-20100105
5V Tolerance 84.27002.F3F
B RN7709 B
2 3
82 VGA_CRT_DDCDATA
82 VGA_CRT_DDCCLK 1 DIS 4 CRT_DDCCLK_CON
SRN0J-6-GP
A A
<Core Design>
Wistron Corporation
Title
CRT Board Connector

A2
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
D D
Card Reader connector
x01 20091121 +3.3V_RUN

C C
CARDBD1
9,21,37,70,76,80 PLT_RST# 7
1
A00-20100120 2
3
USB_PN4_C 4
21 USB_PN4
USB_PP4_C 5
6
8
3
MLX-CON6-21-GP
20.F1035.006
TR7801
4
B B
FILTER-130-GP
21 USB_PP4
<Core Design>
A
Title
CARD Reader CONN

A4
Berry A00
5 4 3 2 1
5 4 3 2 1
H1 H2 H3 H4 H5 H6 H7 H8 H9
HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HOLE256R111-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP
1
1
1
D D
H10 H11
CPU Thermal module hole GPU Thermal module hole stand off
HOLE335R115-GP HOLE256R111-GP
HTML1 HTML2 HTML3
HOLE197R166-GP HOLE197R166-GP HOLE197R166-GP HGPU1 HBT1
STF237R117H83-1-GP STF237R117H123-GP
1
1
1
1
DY DY DY
EMI Reserve
+PW R_SRC
C X01 stuff 20091119 +VGFXCORE_PW R_SRC C
+PW R_SRC_VTT +PW R_SRC_1D5V
1
1
EC7901 EC7902 EC7904 EC7903 EC7905 EC7907 EC7909 EC7906
EC7911 EC7916
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
2
2
DY SCD1U25V2KX-GP
DY
SCD1U25V2KX-GP
2
2
X01 stuff 20091118
1
DY EC7942
DY EC7940
DY EC7941
DY EC7939
DY EC7943
DY EC7938
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
2
B +1.05V_VTT
X02-20100208 B
EMI Reserve
SPR1
X01 RF Reserved-20091118
1
EC7923 EC7924 EC7926 EC7927
SPRING-58-GP +PW R_SRC_1D5V DY UMA UMA UMA
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
+PW R_SRC
56pF*1 56pF*7
1
2
+PW R_SRC +1.5V_SUS
DY 0.1uF*2
1
1
EC7908 EC7912 EC7913 EC7917 EC7919 EC7920 EC7922 EC7925 EC7921 EC7933
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY DY DY DY DY DY DY DY
2
+1.5V_SUS
1
+CPU_GFX_CORE +VGA_CORE EC7945 EC7929 EC7936 EC7944
+1.5V_SUS +VCC_CORE DY DY DY DY
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
+5V_RUN
0.1uF*2 56pF*1 56pF*3 56pF*2
2
56pF
EC7937
1
EC7946 EC7947 EC7928 EC7930 EC7931 EC7932 EC7934 EC7935

A00-20100204 DY
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
DY DY DY DY DY DY UMA DY
2
A <Core Design> A
X02-20100209 Wistron Corporation

Title
UNUSED PARTS/EMI Capacitors

A3
Berry A00
5 4 3 2 1
5 4 3 2 1
8 PEG_TXP[0..15] PEG_RXP[0..15] 8
VGA1A 1 OF 8
8 PEG_TXN[0..15] PEG_RXN[0..15] 8
CONFIGURATION STRAPS RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, 1 = INSTALL 3K RESISTOR
x01 change tolerant 20091117 X = DESIGN DEPENDANT
THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
PEG_TXP0 AA38 Y33 PEG_C_RXP0 C8001 DIS

1 2 SCD1U10V2KX-5GP PEG_RXP0 PLATFORM
PCIE_RX0P PCIE_TX0P
PEG_TXN0 Y37 Y32 PEG_C_RXN0 C8002 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN0 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMEND
PCIE_RX0N PCIE_TX0N SETTING
Transmitter Power Savings Enable
D PEG_TXP1 Y35 W33 PEG_C_RXP1 C8003 DIS
1 2 SCD1U10V2KX-5GP PEG_RXP1 TX_PWRS_ENB GPIO0 X 1 D
PEG_TXN1 PCIE_RX1P PCIE_TX1P 0: 50% Tx output swing 1: Full Tx output swing
W36 PCIE_RX1N PCIE_TX1N W32 PEG_C_RXN1 C8004 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN1
PCIE TRANSMITTER DE-EMPHASIS ENABLED
PEG_TXP2
TX_DEEMPH_EN GPIO1 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled X 1
W38 PCIE_RX2P PCIE_TX2P U33 PEG_C_RXP2 C8005 DIS
1 2 SCD1U10V2KX-5GP PEG_RXP2
PEG_TXN2 V37 U32 PEG_C_RXN2 C8006 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN2 0:Advertises the PCIe device as 2.5GT/s capable at power on.
PCIE_RX2N PCIE_TX2N
BIF_GEN2_EN_A GPIO2 1:Advertises the PCIe device as 5.0GT/s capable at power on. 0 0
PEG_TXP3 V35 U30 PEG_C_RXP3 C8008 DIS
1 2 SCD1U10V2KX-5GP PEG_RXP3 optional input allow the system to request a fast
PEG_TXN3 PCIE_RX3P PCIE_TX3P
U36 U29 PEG_C_RXN3 C8007 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN3 GPIO5_AC_BATT GPIO5 ? 0
PCIE_RX3N PCIE_TX3N power reduction by setting GPIO5 to low.
PEG_TXP4 U38 T33 PEG_C_RXP4 C8009 DIS
1 2 SCD1U10V2KX-5GP PEG_RXP4 RESERVED GPIO8 RESERVED 0 0
PEG_TXN4 PCIE_RX4P PCIE_TX4P PEG_C_RXN4 C8010
T37 PCIE_RX4N PCIE_TX4N T32 DIS
0:VGA Controller capacity enabled
VGA_DIS GPIO9 1:The device won't be recognized as the system's VGA controller 0 0
PEG_TXP5 T35 T30 PEG_C_RXP5 C8011 DIS
R36 PCIE_RX5N PCIE_TX5N T29 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN5 BIOS_ROM_EN=1, Config[2:0] defines the ROM type 0 0 1
PCI EXPRESS INTERFACE

ROMIDCFG[2:0] GPIO[13:11] BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size X X X
(256MB)
PEG_TXP6 R38 P33 PEG_C_RXP6 C8013 DIS
P37 PCIE_RX6N PCIE_TX6N P32 PEG_C_RXN6 C8014 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN6 RESERVED GPIO21 RESERVED 0 0
0:Disable external BIOS ROM device
PEG_TXP7 P35 P30 PEG_C_RXP7 C8016 DIS
1 2 SCD1U10V2KX-5GP PEG_RXP7 BIOS_ROM_EN GPIO_22_ROMCSB X 0
PEG_TXN7 PCIE_RX7P PCIE_TX7P 1:Enable external BIOS ROM device
N36 PCIE_RX7N PCIE_TX7N P29 PEG_C_RXN7 C8015 DIS
VIP Device Strap Enable indicates to the software driver that it sense
VIP_DEVICE_STRAP_EN V2SYNC X 0
PEG_TXP8
whether or not a VIP device is connected on the VIP Host interface.
N38 PCIE_RX8P PCIE_TX8P N33 PEG_C_RXP8 C8018 DIS
C PEG_TXN8 M37 N32 PEG_C_RXN8 C8017 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN8 C
PCIE_RX8N PCIE_TX8N
RSVD H2SYNC RESERVED 0 0
PEG_TXP9 M35 N30 PEG_C_RXP9 C8020 DIS
L36 PCIE_RX9N PCIE_TX9N N29 PEG_C_RXN9 C8019 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN9 RSVD GENERICC RESERVED 0 0
PEG_TXP10 L38 L33 PEG_C_RXP10 C8021 DIS

1 2 SCD1U10V2KX-5GP PEG_RXP10 AUD[1] HSYNC X 1
K37 PCIE_RX10N PCIE_TX10N L32 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN10 AUD[1:0]:11-Audio for both DisplayPort and HDMI
AUD[0] VSYNC X 1
PEG_TXP11 K35 L30 PEG_C_RXP11 C8023 DIS
J36 PCIE_RX11N PCIE_TX11N L29 DIS
PEG_TXP12 J38 K33 PEG_C_RXP12 C8025 DIS

H37 PCIE_RX12N PCIE_TX12N K32 PEG_C_RXN12 C8026 DIS
+3.3V_RUN_VGA
PIN STRAPS
PEG_TXP13 H35 J33 PEG_C_RXP13 C8028 DIS
PEG_TXN13 PCIE_RX13P PCIE_TX13P PEG_C_RXN13 C8027 DIS 2 SCD1U10V2KX-5GP PEG_RXN13
G36 PCIE_RX13N PCIE_TX13N J32 1
82 TX_PW RS_ENB R8001 1
DY 2 3KR2J-2-GP
PEG_TXP14 G38 K30 PEG_C_RXP14 C8030 DIS

1 2 SCD1U10V2KX-5GP PEG_RXP14 82 TX_DEEMPH_EN R8002 1
DY 2 3KR2J-2-GP
K29 PEG_C_RXN14 C8029 DIS 2 SCD1U10V2KX-5GP PEG_RXN14
F37 PCIE_RX14N PCIE_TX14N 1
82 BIF_GEN2_EN_A R8003 1
DY 2 10KR2J-3-GP
PEG_TXP15 F35 H33 PEG_C_RXP15 C8032 DIS

1 2 SCD1U10V2KX-5GP PEG_RXP15 82 GPIO8_ROMSO R8004 1
DY 2 10KR2J-3-GP
H32 PEG_C_RXN15 C8031 DIS 2 SCD1U10V2KX-5GP PEG_RXN15
B
E37 PCIE_RX15N PCIE_TX15N 1
82 VGA_DIS R8005 1
DY 2 10KR2J-3-GP B
CLOCK
82 CONFIG0 R8006 1
DIS 2 10KR2J-3-GP
23 CLK_PCIE_VGA AB35
AA36
PCIE_REFCLKP
82 CONFIG1 R8007 1
DY 2 10KR2J-3-GP
23 CLK_PCIE_VGA# PCIE_REFCLKN
X02-20091208 82 CONFIG2 R8008 1
DY 2 10KR2J-3-GP
CALIBRATION R8017 +1.0V_RUN_VGA
Y30 PCIE_CALRP
DIS R8009 10KR2J-3-GP
PARK
AJ21
AK21
NC#AJ21 PCIE_CALRP 1
1K27R2F-L-GP
2 77,82 VGA_CRT_VSYNC 1
DIS 2
PW RGOOD NC#AK21 PCIE_CALRN R8010 10KR2J-3-GP

1
R8018
2
10KR2F-2-GP
AH16 PWRGOOD PCIE_CALRN Y29
R8019
1 2
2KR2F-3-GP
77,82 VGA_CRT_HSYNC 1
DIS 2
DIS
1 R8020 2VGA_RST# AA30
37,70,76,78 PLT_RST#
0R2J-2-GP DY PERST# R8012 1
DY 2 10KR2J-3-GP
82 VSYNC_DAC2
MADISON-PRO-2-GP R8013 1
DY 2 10KR2J-3-GP
82 HSYNC_DAC2
DY
R8021 DIS 82 BIOS_ROM_EN R8014
R8015
1
DY
2 10KR2J-3-GP
10KR2J-3-GP
37 PLTRST_DELAY# 1 2 82 GPIO5_AC_BATT 1 2
0R0402-PAD
82 GPIO21_BB_EN R8016 1
DY 2 10KR2J-3-GP
X02-20091224
A <Core Design> A
Wistron Corporation
Title
GPU_PCIE/STRAPPING(1/5)
A3 Berry A00
5 4 3 2 1
5 4 3 2 1
VGA1C 3 OF 8 VGA1D 4 OF 8
DDR2 DDR2 DDR2 DDR2
85 MDA[0..31] GDDR3/GDDR5 GDDR5/GDDR3 87 MDB[0..31] GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 DDR3 DDR3
MDA0 C37 G24 MAA0 85,86 MDB0 C5 P8 MAB0 87,88
MDA1 DQA0_0/DQA_0 MAA0_0/MAA_0 MDB1 DQB0_0/DQB_0 MAB0_0/MAB_0
C35 J23 MAA1 85,86 C3 T9 MAB1 87,88
A35 H24 MAA2 85,86 E3 P9 MAB2 87,88
DQA0_2/DQA_2 MAA0_2/MAA_2 DQB0_2/DQB_2 MAB0_2/MAB_2
MEMORY INTERFACE A
MEMORY INTERFACE B
MDA3 E34 J24 MAA3 85,86 MDB3 E1 N7 MAB3 87,88
G32 H26 MAA4 85,86 F1 N8 MAB4 87,88
D33 J26 MAA5 85,86 F3 N9 MAB5 87,88
F32 H21 MAA6 85,86 F5 U9 MAB6 87,88
E32 G21 MAA7 85,86 G4 U8 MAB7 87,88
D31 H19 MAA8 85,86 H5 Y9 MAB8 87,88
D
MDA9 DQA0_8/DQA_8 MAA1_0/MAA_8 MDB9 DQB0_8/DQB_8 MAB1_0/MAB_8 D
F30 H20 MAA9 85,86 H6 W9 MAB9 87,88
C30 L13 MAA10 85,86 J4 AC8 MAB10 87,88
A30 G16 MAA11 85,86 K6 AC9 MAB11 87,88
F28 J16 MAA12 85,86 K5 AA7 MAB12 87,88
C28 H16 A_BA2 85,86 L4 AA8 B_BA2 87,88
MDA14 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 MDB14 DQB0_13/DQB_13 MAB1_5/BA2
A28 J17 A_BA0 85,86 M6 Y8 B_BA0 87,88
MDA15 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 MDB15 DQB0_14/DQB_14 MAB1_6/BA0
E28 H17 A_BA1 85,86 M1 AA9 B_BA1 87,88
MDA16 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 MDB16 DQB0_15/DQB_15 MAB1_7/BA1
D27 M3
MDA17 DQA0_16/DQA_16 MDB17 DQB0_16/DQB_16
F26 A32 DQMA0 85 M5 H3 DQMB0 87
MDA18 DQA0_17/DQA_17 WCKA0_0/DQMA_0 MDB18 DQB0_17/DQB_17 WCKB0_0/DQMB_0
C26 C32 DQMA1 85 N4 H1 DQMB1 87
MDA19 DQA0_18/DQA_18 WCKA0#_0/DQMA_1 MDB19 DQB0_18/DQB_18 WCKB0#_0/DQMB_1
A26 D23 DQMA2 85 P6 T3 DQMB2 87
F24 E22 DQMA3 85 P5 T5 DQMB3 87
C24 C14 DQMA4 86 R4 AE4 DQMB4 88
A24 A14 DQMA5 86 T6 AF5 DQMB5 88
E24 E10 DQMA6 86 T1 AK6 DQMB6 88
C22 D9 DQMA7 86 U4 AK5 DQMB7 88
A22 V6
MDA26 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 MDB26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3
F22 C34 QSAP_0 85 V1 F6 QSBP_0 87
MDA27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 MDB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0
D21 D29 QSAP_1 85 V3 K3 QSBP_1 87
A20 D25 QSAP_2 85 Y6 P3 QSBP_2 87
F20 E20 QSAP_3 85 Y1 V5 QSBP_3 87
D19 E16 QSAP_4 86 Y3 AB5 QSBP_4 88
86 MDA[32..63] E18 E12 QSAP_5 86 88 MDB[32..63] Y5 AH1 QSBP_5 88
C18 J10 QSAP_6 86 AA4 AJ9 QSBP_6 88
A18 D7 QSAP_7 86 AB6 AM5 QSBP_7 88
F18 AB1
D17 A34 QSAN_0 85 AB3 G7 QSBN_0 87
MDA36 DQA1_3/DQA_35 DDBIA0_0/QSA_0#/WDQSA_0 MDB36 DQB1_3/DQB_35 DDBIB0_0/QSB_0#/WDQSB_0
A16 E30 QSAN_1 85 AD6 K1 QSBN_1 87
F16 E26 QSAN_2 85 AD1 P1 QSBN_2 87
D15 C20 QSAN_3 85 AD3 W4 QSBN_3 87
E14 C16 QSAN_4 86 AD5 AC4 QSBN_4 88
F14 C12 QSAN_5 86 AF1 AH3 QSBN_5 88
D13 J11 QSAN_6 86 AF3 AJ8 QSBN_6 88
F12 F8 QSAN_7 86 AF6 AM3 QSBN_7 88
A12 AG4
D11 J21 AH5 T7
MDA45 DQA1_12/DQA_44 ADBIA0/ODTA0 ODTA0 85 MDB45 DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB0 87
F10 G19 AH6 W7
MDA46 DQA1_13/DQA_45 ADBIA1/ODTA1 ODTA1 86 MDB46 DQB1_13/DQB_45 ADBIB1/ODTB1 ODTB1 88
C A10 AJ4 C
C10 H27 AK3 L9
MDA48 DQA1_15/DQA_47 CLKA0 CLKA0 85 MDB48 DQB1_15/DQB_47 CLKB0 CLKB0 87
G13 G27 AF8 L8
MDA49 DQA1_16/DQA_48 CLKA0# CLKA0# 85 MDB49 DQB1_16/DQB_48 CLKB0# CLKB0# 87
H13 AF9
J13 J14 AG8 AD8
MDA51 DQA1_18/DQA_50 CLKA1 CLKA1 86 MDB51 DQB1_18/DQB_50 CLKB1 CLKB1 88
H11 H14 AG7 AD7
MDA52 DQA1_19/DQA_51 CLKA1# CLKA1# 86 MDB52 DQB1_19/DQB_51 CLKB1# CLKB1# 88
G10 AK9
G8 K23 AL7 T10
MDA54 DQA1_21/DQA_53 RASA0# RASA0# 85 MDB54 DQB1_21/DQB_53 RASB0# RASB0# 87
K9 K19 AM8 Y10
MDA55 DQA1_22/DQA_54 RASA1# RASA1# 86 MDB55 DQB1_22/DQB_54 RASB1# RASB1# 88
K10 AM7
G9 K20 AK1 W10
MDA57 DQA1_24/DQA_56 CASA0# CASA0# 85 MDB57 DQB1_24/DQB_56 CASB0# CASB0# 87
A8 K17 AL4 AA10
MDA58 DQA1_25/DQA_57 CASA1# CASA1# 86 MDB58 DQB1_25/DQB_57 CASB1# CASB1# 88
C8 AM6
E8 K24 AM1 P10
MDA60 DQA1_27/DQA_59 CSA0#_0 CSA0#_0 85 MDB60 DQB1_27/DQB_59 CSB0#_0 CSB0#_0 87
MDA61
A6
C6
DQA1_28/DQA_60 CSA0#_1
K27 X01-20091116 MDB61
AN4
AP3
DQB1_28/DQB_60 CSB0#_1
L10

E6 M13 AP1 AD10
MDA63 DQA1_30/DQA_62 CSA1#_0 CSA1#_0 86 MDB63 DQB1_30/DQB_62 CSB1#_0 CSB1#_0 88
A5 K16 AP5 AC10
DQA1_31/DQA_63 CSA1#_1 +3.3V_RUN_VGA DQB1_31/DQB_63 CSB1#_1
MVREFDA L18 K21 U10
MVREFSA MVREFDA CKEA0 CKEA0 85 MVREFDB CKEB0 CKEB0 87
L20 J20 Y12 AA11
MVREFSA CKEA1 CKEA1 86 MVREFDB CKEB1 CKEB1 88
2
MVREFSB AA12 +1.5V_RUN
MEM_CALRN0 R8121 MVREFSB
L27 K26 N10
MEM_CALRN1 MEM_CALRN0 WEA0# WEA0# 85 WEB0# WEB0# 87
N12
MEM_CALRN1 WEA1#
L15
WEA1# 86 DY 10KR2J-3-GP WEB1#
AB11
WEB1# 88
1
MEM_CALRN2
X02-20091208 AG12
MEM_CALRN2 R_MEM_3
MEM_CALRP1 M12
MEM_CALRP1 MAA0_8
H23 MAA13 85,86 1 TEST_EN AD28
TESTEN MAB0_8
T8 MAB13 87,88 DY R8102
+1.5V_RUN MEM_CALRP0 M27 J19 W8 2K2R2J-2-GP
MEM_CALRP0 MAA1_8 MAB1_8
2
DY MEM_CALRP2 AH12 CLKTESTA AK10 R_MEM_2

GDDR5
DIS
GDDR5
2
MEM_CALRN0 MEM_CALRP2 CLKTESTBAL10 CLKTESTA DRAM_RST
1 2 AH11 1 2 MEM_RST 85,86,87,88
243R2F-2-GP R8104 R8122 CLKTESTB DRAM_RST# R8103 51R2J-2-GP
DIS
1
PARK 10KR2J-3-GP C_MEM R_MEM_1
2
1
1
1 2 MEM_CALRN1 DIS C8103
1
243R2F-2-GP R8106 RN8101 SC68P50V2JN-1GP R8105

DIS10KR2J-3-GP
DY SRN4K7J-8-GP
2
1 2 MEM_CALRN2 MADISON-PRO-2-GP
X01-20091118
DIS
2
243R2F-2-GP R8107 MADISON-PRO-2-GP
M96
DIS
3
4
B B
DIS
R8110 1 2MEM_CALRP1 20100210
243R2F-2-GP
** This basic topology should be used for DRAM_RST for
DY DDR3/GDDR3/GDDR5.These Capacitors and Resistor values
R8111 1 2MEM_CALRP0 PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC are an example only. The Series R and || Cap values
243R2F-2-GP
will depend on the DRAM load and will have to be
R8112 1
DY calculated for different Memory ,DRAM Load and board
2MEM_CALRP2
243R2F-2-GP +1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN to pass Reset Signal Spec.
1
Ra R8113 Ra R8114 R8115 R8116

40D2R2F-GP 40D2R2F-GP Ra 40D2R2F-GP Ra 40D2R2F-GP
M96
M96 DIS DIS Designator For Mannhatton For M96-M2/M92-M2
2
MVREFDA MVREFSA MVREFDB MVREFSB

1
M96 M96 DIS DIS R_MEM_1 10K 2.2nF

R8117 C8104 R8118 C8105 R8119 C8106 R8120 C8107
Rb 100R2F-L1-GP-U Rb 100R2F-L1-GP-U Rb 100R2F-L1-GP-U Rb 100R2F-L1-GP-U
2
M96 SCD1U10V2KX-5GP M96 SCD1U10V2KX-5GP DIS SCD1U10V2KX-5GP DIS SCD1U10V2KX-5GP R_MEM_2 51R 0R/Short
2
R_MEM_3 DNI DNI

x01 Change tolerant 20091117 C_MEM 68pF 10K
DDR3/GDDR3 Memory Stuff Option(Mad/Park) DDR3/GDDR3 Memory Stuff Option(M92/M96)
GDDR5 GDDR3 DDR3 GDDR3 DDR3
A MVDDQ 1.5V 1.8V/1.5V 1.5V MVDDQ 1.8V/1.5V 1.5V A
Ra 40.2R 40.2R 40.2R Ra 40.2R 100R

<Core Design>
Rb 100R 100R 100R Rb 100R 100R

Wistron Corporation
Title
GPU Memory(2/5)
C Berry A00
5 4 3 2 1
5 4 3 2 1
VGA1B 2 OF 8
MEMORY ID Table
LVDS Interface RN8203
DVPDATA[0:3] Description TXCAP_DPA3P
AU24 HDMI_PCH_CLK 20,57
AV23 HDMI_PCH_CLK# 20,57 1 4
TXCAM_DPA3N
2 DIS 3
0001 DDR3 Hynix-H5TQ1G63BFR-12C (800MHz) 64M*16 AT25 VGA1G 7 OF 8
TX0P_DPA2P HDMI_PCH_DATA0 20,57
MUTI GFX AR24 SRN10KJ-5-GP
TX0M_DPA2N HDMI_PCH_DATA0# 20,57
DPA
0011 DDR3 Hynix-H5TQ2G63BFR-12C (800MHz) 128M*16 TX1P_DPA1P
AU26 HDMI_PCH_DATA1 20,57
AV25 LVDS CONTROL AK27
TX1M_DPA1N HDMI_PCH_DATA1# 20,57 VARY_BL VGA_LBKLT_CTL 55
0010 DDR3 SAMSUNG K4W2G1646B-HC12 (800MHz) 128M*16
MEM_ID Control AR8 AT27
DIGON
AJ27 VGA_LCDVDD_EN 55
DVPCNTL_MVP_0 TX2P_DPA0P HDMI_PCH_DATA2 20,57
X02-20091222 AU8
DVPCNTL_MVP_1 TX2M_DPA0N
AR26 HDMI_PCH_DATA2# 20,57
AP8
DVPCNTL_0
0000 DDR3 SAMSUNG-K4W1G1646E-HC12 (800MHz) 64M*16 AW8
DVPCNTL_1 TXCBP_DPB3P
AR30
+1.8V_RUN_VGA AR3 AT29 AK35 GPU_LVDSB_TXC 55
DVPCNTL_2 TXCBM_DPB3N TXCLK_UP_DPF3P
DVPDATA[0:3] Default:Pull down Hynix AR1
DVPCLK TXCLK_UN_DPF3N
AL36 GPU_LVDSB_TXC# 55
D R8207 1 2 10KR2J-3-GP MEM_ID0 AU1 AV31 D
R8209 1 MEM_ID1 DVPDATA_0 TX3P_DPB2P
2 10KR2J-3-GP AU3 AU30 AJ38 GPU_LVDSB_TX0 55
THERMTRIP_R
MEM_ID2 AW3 DVPDATA_1 DPB TX3M_DPB2N TXOUT_U0P_DPF2P

VRAM_1G 1
TP8222 TPAD14-GP MEM_ID3 DVPDATA_2 TXOUT_U0N_DPF2N
AK37 GPU_LVDSB_TX0# 55
1 AP6 AR32
THERMTRIP_VGA TP8223 TPAD14-GP DVPDATA_3 TX4P_DPB1P
AW5 AT31 AH35 GPU_LVDSB_TX1 55
DVPDATA_4 TX4M_DPB1N TXOUT_U1P_DPF1P
AU5 AJ36 GPU_LVDSB_TX1# 55
DVPDATA_5 TXOUT_U1N_DPF1N
AR6 AT33
1
DVPDATA_6 TX5P_DPB0P
THERMTRIP_VGA# 37 AW6 AU32 AG38 GPU_LVDSB_TX2 55
DVPDATA_7 TX5M_DPB0N TXOUT_U2P_DPF0P
X02-20100104 DY R8208 AU6
AT7
DVPDATA_8
AU14
TXOUT_U2N_DPF0N
AH37 GPU_LVDSB_TX2# 55
6
10KR2J-3-GP DVPDATA_9 TXCCP_DPC3P

AV7 AV13 AF35
D
DVPDATA_10 TXCCM_DPC3N TXOUT_U3P
AN7 AG36
2
2N7002EDW-GP DVPDATA_11 TXOUT_U3N

Q8203
. Q8202 AV9
DVPDATA_12 TX0P_DPC2P
AT15
DY .
2N7002E-1-GP AT9
AR10
DVPDATA_13 TX0M_DPC2N
AR14
LVTMDP
84.27002.F3F DY . 84.2N702.D31
1
DVPDATA_14 DPC
. . AW10
DVPDATA_15 TX1P_DPC1P
AU16
AU10 AV15 AP34 GPU_LVDSA_TXC 55
DVPDATA_16 TX1M_DPC1N TXCLK_LP_DPE3P
AP10 AR34 GPU_LVDSA_TXC# 55
S
DVPDATA_17 TXCLK_LN_DPE3N
AV11 AT17
DVPDATA_18 TX2P_DPC0P R8202 VGA_BLEN
9,25,37,42 H_THERMTRIP# X02-20100104 AT11 AR16 1 DIS 210KR2J-3-GP AW37 GPU_LVDSA_TX0 55
DVPDATA_19 TX2M_DPC0N TXOUT_L0P_DPE2P
AR12 AU35 GPU_LVDSA_TX0# 55
+3.3V_RUN_VGA DVPDATA_20 TXOUT_L0N_DPE2N
AW12 AU20
DVPDATA_21 TXCDP_DPD3P
37 THERMTRIP_VGA_GATE AU12 AT19 AR37 GPU_LVDSA_TX1 55
DVPDATA_22 TXCDM_DPD3N TXOUT_L1P_DPE1P
AP12 AU39 GPU_LVDSA_TX1# 55
DVPDATA_23 TXOUT_L1N_DPE1N
AT21
2
1
TX3P_DPD2P
AR20 AP35 GPU_LVDSA_TX2 55
JTAG_TRST#_VGA RN8201 TX3M_DPD2N TXOUT_L2P_DPE0P
AR35 GPU_LVDSA_TX2# 55
DPD TXOUT_L2N_DPE0N
AU22
X01-20091116 DIS SRN4K7J-8-GP TX4P_DPD1P
AV21 AN36
TX4M_DPD1N TXOUT_L3P
AP37
I2C TXOUT_L3N
AT23
DIS
3
4
TX5P_DPD0P
2
R8201 JTAG_TCK_VGA RN8202 AR22

TX5M_DPD0N
I2C Bus for LVDS 4 1 GPU_LVDS_CLK_C AK26
DY 20,54 GPU_LVDS_CLK SCL
2
2 GPU_LVDS_DATA_C AJ26
10KR2J-3-GP R8203
20,54 GPU_LVDS_DATA 3
DIS SDA MADISON-PRO-2-GP
DY Straps SRN0J-6-GP AD39 VGA_CRT_RED 77
1
10KR2J-3-GP GENERAL PURPOSE I/O R

AD37
R#
80 TX_PWRS_ENB AH20
1
GPIO_0 +1.8V_RUN_VGA
80 TX_DEEMPH_EN AH18
GPIO_1 G
AE36 VGA_CRT_GREEN 77 (1.8V@65mA AVDD)
80 BIF_GEN2_EN_A AN16 AD35 AVDD
GPIO_2 G# L8202 DIS
C
AH23
AJ23
GPIO_3_SMBDATA
AF37 1 2
x01 Change tolerant 20091117 C
GPIO_4_SMBCLK B VGA_CRT_BLUE 77
80 GPIO5_AC_BATT AH17
GPIO_5_AC_BATT B#
AE38 +3.3V tolerant BLM15BD121SS1D-GP
1
1 GPIO6_VGA AJ17 DAC1 RN8204 C8203 C8204
SCD1U10V2KX-5GP
TP8207 TPAD14-GP GPIO_6 VGA_CRT_BLUE C8201
+3.3V_RUN_VGA
55 VGA_BLEN AK17
GPIO_7_BLON HSYNC
AC36 VGA_CRT_HSYNC 77,80 1
VGA_CRT_GREEN 2
8
SC4D7U6D3V3KX-GP
DIS DIS DISSC1U6D3V2KX-GP
AJ13 AC38 7
80 GPIO8_ROMSO VGA_CRT_VSYNC 77,80 DIS
2
GPIO_8_ROMSO VSYNC VGA_CRT_RED
80 VGA_DIS AH15 3 6
GPIO_9_ROMSI
AJ16
GPIO_10_ROMSCK DIS 4 5
2
AK16 AB34 GPU_RSET 1 2 AVSSQ

80 CONFIG0 GPIO_11 RSET
R8205 AL16 R8214 499R2F-2-GP SRN150F-1-GP
DY 80 CONFIG1
80 CONFIG2 AM16
GPIO_12
AD34 AVDD VDD1DI
10KR2J-3-GP VPIO14_VGA GPIO_13 AVDD L8203 DIS
1 AM14
GPIO_14_HPD2 AVSSQ
AE34 (1.8V@100mA VDD1DI)
TP8208 TPAD14-GP
89 PWRCNTL_0 AM13 1 2 x01 Change tolerant 20091117
1
TPAD14-GP GPIO16_SSIN GPIO_15_PWRCNTL_0 VDD1DI BLM15BD121SS1D-GP

1 AK14 AC33
1
JTAG_TMS_VGA TP8203 TPAD14-GP GPIO17_VGA GPIO_16_SSIN VDD1DI C8206 C8207
1 AG30 AC34 X02-20091222
SC1U6D3V2KX-GP
TP8213 TPAD14-GP GPIO18_VGA GPIO_17_THERMAL_INT VSS1DI AVSSQ C8202 SCD1U10V2KX-5GP
TP8209
1
THERMTRIP_VGA
AN14
GPIO_18_HPD3 SC4D7U6D3V3KX-GP
DIS DIS
AM17 DIS
2
GPIO_19_CTF R8206
89 PWRCNTL_1 AL13 AC30
GPIO_20_PWRCNTL_1 R2
80 GPIO21_BB_EN AJ14 AC31 1 2
GPIO_21_BB_EN R2#
80 BIOS_ROM_EN AK13
GPIO_22_ROMCS# 0R0402-PAD
23 PEG_CLKREQ# AN13 AD30
JTAG_TRST#_VGA GPIO_23_CLKREQ# G2
AM23 AD31
R8204 TP8202 TPAD14-GP JTAG_TDI_VGA JTAG_TRST# G2# AVSSQ
1 AN23
JTAG_TCK_VGA JTAG_TDI
JTAG SIGNAL OPTION 7 CLK_VGA_27M_SS
1 DY 2 AK23
JTAG_TCK B2
AF30 (1.8V@50mA VDD2DI)
JTAG_TMS_VGA
Normal Debug pilot run 0R2J-2-GP TP8205 1 TPAD14-GP
AL24
JTAG_TDO_VGA AM24 JTAG_TMS B2#
AF31 x01 Change tolerant 20091117
JTAG_TDO
1
Signal X01-20091116 TP8206 1 TPAD14-GP GEN_A AJ19 C8209 C8210
mode mode mode TP8211 1 TPAD14-GP GEN_B GENERICA
DY
For new version no 27M TP8218 1 TPAD14-GP GENERICC
AK19
AJ20
GENERICB C
AC32
AD32 SCD1U10V2KX-5GP
DY SC1U6D3V2KX-GP
2
GENERICD GENERICC Y
TESTEN "1"(PU) "1"(PU) "0"(PD) TP8219 1 TPAD14-GP AK20
GENERICD COMP
AF32
TP8212 1 TPAD14-GP GENERICE_HPD4 AJ24
TP8220 GENERICF GENERICE_HPD4 DAC2
1 TPAD14-GP AH26
GENERICG GENERICF
JTAG_TRST# "0"(PD) "1"(PU) NC TP8221 1 TPAD14-GP AH24
GENERICG H2SYNC
AD29 HSYNC_DAC2 80
AC29 A2VDDQ
V2SYNC VSYNC_DAC2 80
JTAG_TCK CLK "1"(PU) NC +1.8V_RUN_VGA
57 HDMI_HPD_DET AK24
HPD1
L8205 DIS (1.8V@1.5mA A2VDDQ)
AG31 +1.8V_RUN_VGA 1 2
VDD2DI BLM15BD121SS1D-GP
AG32
SC1U6D3V2KX-GP
VSS2DI
1
1
JTAG_TMS "1"(PU) "1"(PU) NC +3.3V_RUN_VGA C8212 C8213
PLACE VREFG DIVIDER AND CAP R8216 DIS DIS
DIS 499R2F-2-GP AG33 A2VDDQ SCD1U10V2KX-5GP
CLOSE TO ASIC
2
A2VDD
B +1.8V_RUN_VGA DPLL_PVDD AD33 B
2
GPU_VREFG A2VDDQ
(1.8V@75mA DPLL_PVDD) AH13
VREFG
L8201
DIS AF33 x01 Change tolerant 20091117
1
C8217 DPLL_PVDD A2VSSQ

1 2
1
SCD1U10V2KX-5GP
BLM18PG471SN1D-GP C8219 R8217 DIS +3.3V_RUN_VGA

1
1
SCD1U10V2KX-5GP
C8218 249R2F-GP R2SET (3.3V@130mA A2VDD)

DIS DIS AA29 1 2
SC1U6D3V2KX-GP
R2SET
1
C8205 R8218 715R2F-GP

DY DIS AM32
2
SC4D7U6D3V3KX-GP DPLL_PVDD
DIS AN32
2
1
DPLL_PVSS C8215 C8216
SC1U6D3V2KX-GP
2
DDC/AUX SCD1U10V2KX-5GP
DDC1CLK
AM26 VGA_CRT_DDCCLK 77 DY DY
AN31 AN26 VGA_CRT_DDCDATA 77 DDC1 channel for CRT
2
DPLL_VDDC DDC1DATA
x01 Change tolerant 20091117 AM27
+1.0V_RUN_VGA DPLL_VDDC XTALIN PLL/CLOCK AUX1P
(1.0V@125mA DPLL_VDDC) AV33
XTALIN AUX1N
AL27
DIS (1.1V@150mA DPLL_VDDC For M96/M92) XTALOUT AU34
XTALOUT
1
L8207
2
BLM18PG471SN1D-GP
X02 20091208 DDC2CLK
AM19
AL19
GPU_HDMI_CLK 57
DDC2 channel for HDMI
DDC2DATA GPU_HDMI_DATA 57
C8222 1PARK 2 XO_IN AW34
7 CLK_VGA_27M_NSS
1
C8221 R8210 0R2J-2-GP XO_IN

AN20
AUX2P
SCD1U10V2KX-5GP
C8220 DY DIS DIS 1 M96 2 AW35 AM20

SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP R8211 0R2J-2-GP XO_IN2 AUX2N

2
39 VGA_THERMDA DDCCLK_AUX3P
AL30
AM30
DDC1/DDC2/DDC6 have 5V-tolerant
2
C8226 DDCDATA_AUX3N
X02-20091210 SC470P50V2JN-GP
Voltage Swing:1.8V DY AF29
DDCCLK_AUX4P
AL29
AM29
1
DPLUS THERMAL DDCDATA_AUX4N

39 VGA_THERMDC AG29
DMINUS
AN21
DDCCLK_AUX5P
AM21
TP8214 FAN_PWM DDCDATA_AUX5N
M96 1 TPAD14-GP AK32 X8201
CLK_VGA_27M_NSS 1 XTALIN TS_FDO
2 AJ30 C8227
R8212 124R2F-U-GP DDC6CLK
AL31 AJ31
1
+1.8V_RUN_VGA TSVDD TS_A DDC6DATA XTALIN

2 1 1 4
R8213 L8204 DIS (1.8V@20mA TSVDD) AK30
M96 150R2F-1-GP 1 2 AJ32
DDCCLK_AUX7P
AK29
DY
TSVDD DDCDATA_AUX7N SC18P50V2JN-1-GP C8228
BLM15BD121SS1D-GP AJ33
TSVSS
2
DY 3 XTALOUT 1 2
2
DIS C8224 C8225

C8223 DY SC1U6D3V2KX-GP DIS SCD1U10V2KX-5GP MADISON-PRO-2-GP
SC4D7U6D3V3KX-GP
DIS SC18P50V2JN-1-GP
2
XTAL-27MHZ-85-GP
A DY A
<Core Design>
Clock Input Configuraiton -GDDR3/DDR3
a) 27MHz crystal connected to XTALIN or XTALOUT or Wistron Corporation
b) 27MHz (1.8V) oscillator connected to XTALIN or 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)
Title
GPU_DP/LVDS/CRT/GPIO(3/5)
A2
Berry A00
5 4 3 2 1
5 4 3 2 1
VGA1E 5 OF 8 +1.8V_RUN_VGA
For DDR3/GDDR5, MVDDQ = 1.5V
+1.5V_RUN x01 change tolerant 20091117
MEM I/O
x01 change tolerant 20091117 PCIE (1.8V@504mA PCIE_VDDR)
AC7 AA31
VDDR1 PCIE_VDDR
SC1U6D3V2KX-GP
AD11 AA32
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1
1
VDDR1 PCIE_VDDR
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8301 C8304 C8305 C8306 C8307 C8308 C8309 C8310 C8311 C8312 AF7 AA33 C8313 C8314 C8315 C8316 C8317
VDDR1 PCIE_VDDR SC4D7U6D3V3KX-GP
AG10
VDDR1 PCIE_VDDR
AA34 DY DIS
DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS AJ7 V28 DIS DY DIS
2
2
VDDR1 PCIE_VDDR
AK8 W29
VDDR1 PCIE_VDDR
AL9 W30
VDDR1 PCIE_VDDR +1.0V_RUN_VGA
G11 Y31
VDDR1 PCIE_VDDR
G14
VDDR1
G17
VDDR1 (1.0V@1920mA PCIE_VDDC)
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
G20 G30
VDDR1 PCIE_VDDC
1
1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8318 C8319 C8320 C8321 C8322 C8323 C8324 C8325 C8326 C8327 G23 G31
1
VDDR1 PCIE_VDDC
SC1U6D3V2KX-GP
DIS DIS DIS G26 H29 C8328 C8329 C8330 C8331 C8332 C8333 C8302 C8334
VDDR1 PCIE_VDDC
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DIS SC4D7U6D3V3KX-GP
DIS DIS DY DY DY DY DY G29 H30
2
2
VDDR1 PCIE_VDDC
H10 J29
DIS
2
VDDR1 PCIE_VDDC
J7 J30
D
J9
VDDR1 PCIE_VDDC
L28
DIS DIS DIS DIS DIS DIS D
VDDR1 PCIE_VDDC
K11 M28
VDDR1 PCIE_VDDC
K13 N28
VDDR1 PCIE_VDDC
x01 change tolerant 20091117 K8
VDDR1 PCIE_VDDC
R28
L12 T28
VDDR1 PCIE_VDDC
L16 U28 For UMA +VGA_CORE connect to GND
1
VDDR1 PCIE_VDDC
C8303 C8335 L21
VDDR1 X02-20091224 +VGA_CORE
L23
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VDDR1
L26 AA15
2
VDDR1 CORE VDDC

L7 AA17
DIS DIS VDDR1 VDDC
1
SC1U6D3V2KX-GP
M11 AA20 C8336 C8337 C8339 C8340 C8341 C8342 C8343 C8344 C8345
VDDR1 VDDC
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
N11 AA22 SC1U6D3V2KX-GP R8301
VDDR1 VDDC
P7 AA24
DIS DIS DIS DIS DIS DIS DIS DIS DIS UMA 0R3J-0-U-GP
2
VDDR1 VDDC
R11 AA27
VDDR1 VDDC
U11 AB16
2
VDDR1 VDDC
U7 AB18
VDDR1 VDDC
Y11 AB21
VDDR1 VDDC
Y7 AB23
VDDR1 VDDC
AB26
VDDC
SCD1U10V2KX-5GP
+1.8V_RUN_VGA
VDDC
AB28 x01 change tolerant 20091117
1
AC17 C8346 C8347 C8348 C8349 C8350
VDDC
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
x01 change tolerant 20091117 LEVEL VDDC
AC20
DIS DIS DY DIS DIS SC1U6D3V2KX-GP
VDDC_CT AC22
2
TRANSLATION VDDC
(1.8V@110mA VDD_CT) VDDC
AC24
POWER
1 2 AF26 AC27
DIS VDD_CT VDDC
SCD1U10V2KX-5GP
L8301 BLM15BD121SS1D-GP AF27 AD18
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
1
C8351 C8352 C8353 C8354 C8355 VDD_CT VDDC
AG26 AD21
VDD_CT VDDC
DIS DIS DIS DIS AG27
VDD_CT VDDC
AD23 x01 change tolerant 20091117 x01 change tolerant 20091117
AD26
DIS
2
2
VDDC
AF17
VDDC
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
I/O AF20
1
VDDC
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
+3.3V_RUN_VGA AF23 AF22 C8356 C8357 C8358 C8359 C8360 C8361 C8362 C8363 C8364 C8365
VDDR3 VDDC
AF24
VDDR3 VDDC
AG16 DIS DY DIS COLAY
AG23 AG18
DIS DIS DIS DIS DIS DIS
2
VDDR3 VDDC
AG24 AG21
SC4D7U6D3V3KX-GP
VDDR3 VDDC
1
C8366 C8367 C8368 C8369 AH22

SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDDC
DIS VDDC
AH27
AF13 AH28
2
VDDR4 VDDC
DIS DIS DIS AF15
VDDR4 VDDC
M26
AG13 N24
VDDR4 VDDC
C AG15 N27 C
VDDR4 VDDC/BIF_VDDC
R18
VDDC
1
SC10U6D3V5KX-1GP
R21 C8370 C8371 C8372 C8373
VDDC
AD12 R23
VDDR4 VDDC DY
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
AF11 R26
DIS DIS DIS
2
VDDR4 VDDC
AF12 T17
VDDR4 VDDC
AG11 T20
VDDR4 VDDC
X02-20091208 VDDC
T22
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
T24
1
C8374 C8375 +1.5V_RUN VDDC

T27
VDDC/BIF_VDDC
DIS M96 VDDRH VDDC
U16
1 2 M20 U18
SC1U6D3V2KX-GP
2
NC_VDDRHA VDDC
L8306 BLM15BD121SS1D-GP 1 M96 2VSSRHA
DIS 120ohm, 0.3A R8302 0R2J-2-GP
M21
NC_VSSRHA VDDC
U21
U23
1
C8394 VDDC
VDDC
U26 A00 change 22uF 20100329
M96 M96 V12 V17
1 2VSSRHB U12
NC_VDDRHB VDDC
V20 VDDCI and VDDC should have seperate regulators with a merge option on PCB
2
NC_VSSRHB VDDC
x01 change tolerant 20091117 R8303 0R2J-2-GP
VDDC
V22
V24
PCIE_PVDD
VDDC
VDDC
V27
Y16
For Madison and Park, VDDCI and VDDC can share one common regulator
PLL VDDC
(1.8V@40mA PCIE_PVDD) VDDC
Y18
1
DIS 2 X02-20091208 AB37
PCIE_PVDD VDDC
Y21
SCD1U10V2KX-5GP
L8302 BLM15BD121SS1D-GP MPV18 Y23

1
C8377 C8378 +VGA_CORE SPV10 VDDC

H7 Y26
SC1U6D3V2KX-GP
C8376 L8307 MPV18 VDDC

DIS DIS M96 H8 Y28 (GDDR3/DDR3 1.12V@4A VDDCI)
DIS 1 2 SPV18 MPV18 VDDC
2
SC4D7U6D3V3KX-GP BLM18PG471SN1D-GP (GDDR5 1.12V@16A VDDCI) +VGA_CORE

+1.0V_RUN_VGA AM10
L8303 SPV18
(120mA PARK SPV10) VDDCI
AA13
1 2 AN9 AB13
SPV10 VDDCI
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
BLM18PG471SN1D-GP AC12
SC1U6D3V2KX-GP
VDDCI
1
1
(For M96 SPV10 = VDDC) C8380 C8381 AN10 AC15 C8382 C8383 C8384 C8385 C8386 C8387 C8388
SPVSS VDDCI
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(For M97, Broadway, Madison and Park SPV10 = 1.0V) C8379 DIS DIS AD13 DIS SC1U6D3V2KX-GP
DIS VDDCI DIS
SC22U6D3V5MX-2GP
AD16
DIS DIS DIS DIS DIS
2
2
SC4D7U6D3V3KX-GP VDDCI
M15
VDDCI
M16
VOLTAGE VDDCI
x01 change tolerant 20091117 VDDCI
M18
SENESE M23 X02-20091224
VDDCI
N13
VDDCI
M97, Broadway, Madison and Park only 1FB_VDDC AF28 N15 A00 change 22uF 20100329
B TP8301 TPAD14-GP FB_VDDC VDDCI B
M96 do not support core vsense feature VDDCI
N17
N20
VDDCI
1FB_VDDCI AG28 N22
TP8302 TPAD14-GP FB_VDDCI ISOLATED VDDCI
R12
CORE I/O VDDCI
M96 VDDCI
R13
X02-20091208 1 2 FB_GND AH29 R16
R8304 0R2J-2-GP FB_GND VDDCI
T12
VDDCI
T15
VDDCI
VCORE_SEN/RTN and VDDCI_SEN/RTN route as differetial pair VDDCI
V15
Y13
VDDCI
MADISON-PRO-2-GP
M97, Broadway, Madison and Park only
SPV18
DIS
(1.8V@75mA SPV18) NOTE1:
PARK 2
1
Back Bias is not supported on M97, Broadway, Madison and Park
SCD1U10V2KX-5GP
L8304 BLM15BD121SS1D-GP
1
C8390 C8391
C8389
For the M96 Back Bias circuitry, refer to REF134
PARK PARK PARK
SC1U6D3V2KX-GP
2
SC4D7U6D3V3KX-GP
NOTE2:
FB_VDDC, FB_VDDCI and FB_GND are not support on M96
NOTE3:
M97 VDDC and VDDCI ball assignments are different from M96.
(M97, Broadway and Madison: 1.8V@150mA MPV18) If M96 is populated on this design, VDDC and VDDCI will be shorted on the substrate.
(Park: 1.8V@75mA MPV18)
MPV18
NOTE4:
PARK 2
1 For M2 design compatibility, refer to the document AN_M96_Ax and AN_M97_Ax
SCD1U10V2KX-5GP
L8305 BLM18PG471SN1D-GP
SC1U6D3V2KX-GP
1
C8393 C8396
C8392 PARK PARK PARK
2
A SC4D7U6D3V3KX-GP A
x02-20091208 <Core Design>
Wistron Corporation
Title
GPU_POWER(4/5)
A2
Berry A00
Date: Wednesday, March 31, 2010 Sheet 83 of 92
5 4 3 2 1
5 4 3 2 1
VGA1F 6 OF 8
VGA1H 8 OF 8
AB39 A3 DPA_VDD18
PCIE_VSS GND DPB_VDD18 DP C/D POWER DP A/B POWER
E39 A37
PCIE_VSS GND
F34 AA16
PCIE_VSS GND
F39 AA18 AP20 AN24
PCIE_VSS GND +1.0V_RUN_VGA DPC_VDD18 DPA_VDD18
G33 AA2 AP21 AP24
PCIE_VSS GND DPC_VDD18 DPA_VDD18 +1.0V_RUN_VGA
G34
PCIE_VSS GND
AA21 DNI for M96/M92
H31 AA23 DPA_VDD10
PCIE_VSS GND L8403
H34
PCIE_VSS GND
AA26 (1.0V@110mA DPC_VDD10) (1.0V@110mA DPA_VDD10) DIS
H39 AA28 AP13 AP31 1 2 +1.8V_RUN_VGA DPA_VDD18
SCD1U10V2KX-5GP
1
1
PCIE_VSS GND DPC_VDD10 DPA_VDD10 C8402 BLM15BD121SS1D-GP
J31 AA6 AT13 AP32
SC1U6D3V2KX-GP
PCIE_VSS GND DPC_VDD10 DPA_VDD10 C8403 C8405
J34
PCIE_VSS GND
AB12 DIS SC10U6D3V5KX-1GP L8402
K31 AB15 DIS DIS PARK (1.8V@130mA DPA_VDD18)
2
PCIE_VSS GND
K34
PCIE_VSS GND
AB17 AN17
DPC_VSSR DPA_VSSR
AN27 1 2 x01 change tolerant 20091117
K39 AB20 AP16 AP27 BLM15BD121SS1D-GP
1
PCIE_VSS GND DPC_VSSR DPA_VSSR C8407 C8408
L31 AB22 AP17 AP28
SC1U6D3V2KX-GP
D D
PCIE_VSS GND DPC_VSSR DPA_VSSR C8406
L34
PCIE_VSS GND
AB24 AW14
DPC_VSSR DPA_VSSR
AW24
SC4D7U6D3V3KX-GP
PARK PARK
SCD1U10V2KX-5GP
M34 AB27 AW16 AW26 PARK
2
PCIE_VSS GND DPC_VSSR DPA_VSSR
M39
PCIE_VSS GND
AC11 x01 change tolerant 20091117
N31 AC13 DPD_VDD18 DPB_VDD18
PCIE_VSS GND DPB_VDD18
N34 AC16
PCIE_VSS GND +1.0V_RUN_VGA
P31 AC18 AP22 AP25
PCIE_VSS GND DPD_VDD18 DPB_VDD18
P34 AC2 AP23 AP26
PCIE_VSS GND DPD_VDD18 DPB_VDD18 +1.0V_RUN_VGA
P39
PCIE_VSS GND
AC21 PARK (1.8V@130mA DPB_VDD18)
R34 AC23 1 2
PCIE_VSS GND R8402 0R2J-2-GP
T31
PCIE_VSS GND
AC26 (1.0V@110mA DPD_VDD10)
1
T34 AC28 AP14 AN33 (1.0V@110mA DPB_VDD10) DY C8410 C8411
SC1U6D3V2KX-GP
PCIE_VSS GND DPD_VDD10 DPB_VDD10 C8409
T39
PCIE_VSS GND
AC6 AP15
DPD_VDD10 DPB_VDD10
AP33
SC4D7U6D3V3KX-GP
DY PARK
SCD1U10V2KX-5GP
U31 AD15
2
PCIE_VSS GND
U34 AD17
PCIE_VSS GND
V34 AD20
PCIE_VSS GND
V39 AD22 AN19 AN29
PCIE_VSS GND DPD_VSSR DPB_VSSR
W31 AD24 AP18 AP29
W34 AD27 AP19 AP30
Y34 AD9 AW20 AW30
PCIE_VSS GND DPD_VSSR DPB_VSSR +1.8V_RUN_VGA
Y39 AE2 AW22 AW32
PCIE_VSS GND DPD_VSSR DPB_VSSR DPA_PVDD
GND
AE6 (1.8V@20mA DPA_PVDD)
GND
AF10
DP mode
x01 change tolerant 20091117 L8404
DIS
AF16 R8401 DIS R8404 1 2
GND
AF18 (1.8V@130mA DPE_VDD18) 1 2DPCD_CALR AW18 AW28DPAB_CALR1 2 BLM15BD121SS1D-GP
SCD1U10V2KX-5GP
1
1
GND +1.8V_RUN_VGA 150R2F-1-GP DPCD_CALR DPAB_CALR 150R2F-1-GP C8412
AF21
GND
SC1U6D3V2KX-GP
GND
1
LVDS mode DPE_VDD18 C8413
GND
AG17 DIS
F15 AG2 DIS L8401 (1.8V@200mA DPE_VDD18) DP E/F POWER DP PLL POWER DIS DIS C8414
DIS
2
GND GND SC4D7U6D3V3KX-GP DPD_VDD18
F17 AG20 1 2 AH34 AU28
2
GND GND BLM18PG471SN1D-GP DPE_VDD18 DPA_PVDD
F19 AG22 AJ34 AV27
SC1U6D3V2KX-GP
1
2
GND GND C8401 C8418 C8419 DPE_VDD18 DPA_PVSS
F21 AG6
GND GND SC4D7U6D3V3KX-GP
F23
GND GND
AG9 DIS DIS DIS PARK (1.8V@130mA DPD_VDD18)
F25 AH21 LVDS mode SCD1U10V2KX-5GP (1.8V@20mA DPB_PVDD) 1 2
1
GND GND R8405 0R2J-2-GP
F27 AJ10 (1.0V@120mA DPE_VDD10) AL33 AV29
2
GND GND DP mode DPE_VDD10 DPE_VDD10 DPB_PVDD C8421
F29 AJ11 AM33 AR28 DY
SC1U6D3V2KX-GP
GND GND DPE_VDD10 DPB_PVSS C8415 C8422
F31
GND GND
AJ2 (1.0V@110mA DPE_VDD10) PARK
F33 AJ28 SC4D7U6D3V3KX-GP DY SCD1U10V2KX-5GP
1
GND GND
F7
GND GND
AJ6 +1.0V_RUN_VGA x01 change tolerant 20091117 (1.8V@20mA DPC_PVDD)
L8408
F9
G2
GND GND
AK11
AK31 1
DIS2
AN34
AP39
DPE_VSSR DPC_PVDD
AU18
AV17 x01 change tolerant 20091117
GND GND BLM15BD121SS1D-GP DPE_VSSR DPC_PVSS
G6 AK7 AR39
GND GND DPE_VSSR
1
C H9 AL11 C8404 C8424 AU37 C
GND GND SC4D7U6D3V3KX-GP C8425 DPE_VSSR
J2 AL14 DIS DIS DIS (1.8V@20mA DPD_PVDD)
SC1U6D3V2KX-GP
GND GND
J27 AL17 SCD1U10V2KX-5GP AV19
2
GND GND DP mode DPD_PVDD
J6 AL2 AR18
GND GND DPD_PVSS
J8
GND GND
AL20 (1.8V@130mA DPF_VDD18)
K14 AL21 LVDS mode AF34 DPF_PVDD
GND GND/PX_EN DPF_VDD18 DPF_VDD18
K7
GND GND
AL23 (1.8V@200mA DPF_VDD18) AG34
DPF_VDD18 (1.8V@20mA DPE_PVDD)
L11 AL26 AM37
GND GND +1.8V_RUN_VGA DPE_PVDD
L17 AL32 AN38
GND GND L8405 DIS DPE_PVSS
L2 AL6
GND GND
L22 AL8 1 2 AK33
GND GND BLM18PG471SN1D-GP DPF_VDD10
L24
GND GND
AM11 AK34
DPF_VDD10 PARK (1.8V@20mA DPF_PVDD) L8406 DIS
1
2
L6 AM31 C8423 C8427 AL38 DPF_PVDD_1 1 2 1 2
GND GND SC4D7U6D3V3KX-GP C8428 DPF_PVDD R8407 0R2J-2-GP BLM15BD121SS1D-GP
M17 AM9 DIS SC1U6D3V2KX-GP
DIS AM35
SCD1U10V2KX-5GP
1
1
GND GND DPF_PVSS C8429 C8430
M22 AN11 DIS SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
2
1
GND GND C8416
M24
GND GND
AN2
LVDS mode
AF39
DPF_VSSR DIS DIS DIS
N16 AN30 AH39 PARK
2
GND GND DPF_VDD10 DPF_VSSR DPF_PVSS SC4D7U6D3V3KX-GP
N18
GND GND
AN6 (1.0V@120mA DPF_VDD10) AK39
DPF_VSSR
1 2
N2 AN8 DP mode AL34 R8408 0R2J-2-GP
GND GND DPF_VSSR
N21
GND GND
AP11 (1.0V@110mA DPF_VDD10) AM34
DPF_VSSR
N23
GND GND
AP7 x02 20091208
N26
GND GND
AP9 +1.0V_RUN_VGA x01 change tolerant 20091117
N6
GND GND
AR5 L8407
DIS x01 change tolerant 20091117
R15 B11 1 2 AM39
GND GND BLM15BD121SS1D-GP DPEF_CALR
R17 B13
2DPEF_CALR
GND GND
1
1
R2 B15 C8426 C8433 C8434
GND GND
SCD1U10V2KX-5GP
R20 B17 SC4D7U6D3V3KX-GP DIS DIS DIS MADISON-PRO-2-GP
SC1U6D3V2KX-GP
GND GND
R22 B19
DIS
2
2
GND GND
R24 B21
GND GND
R27 B23
GND GND
R6 B25
GND GND R8406
T11 B27
GND GND 150R2F-1-GP
T13
GND GND
B29 DIS
T16 B31
GND GND
T18 B33
1
GND GND
T21 B7
GND GND
T23 B9
GND GND
T26 C1
GND GND
U15 C39
GND GND
U17 E35
GND GND
U2 E5
B GND GND B
U20
GND GND
F11 For M97/M96, DPF_VDD18 can be shared with DPE_VDD18
U22 F13
GND GND
U24
GND For M97/M96, DPF_VDD10 can be shared with DPE_VDD10
U27
GND
U6
GND
V11
GND
V16
GND
For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively
V18
GND
V21
GND
V23
GND
For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively
V26
GND
W2
GND
W6
GND For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively
Y15
GND
Y17
GND
Y20
GND
Y22 A39 VSS_MECH1 TPAD14-GP1 TP8401
GND VSS_MECH
Y24 AW1 VSS_MECH2 TPAD14-GP1 TP8402
GND VSS_MECH
Y27 AW39VSS_MECH3 TPAD14-GP1 TP8403
GND VSS_MECH
U13
GND
V13
GND
MADISON-PRO-2-GP
DIS
A A
<Core Design>
Wistron Corporation
Title
GPU_DPPWR/GND(5/5)
A2 Berry A00
Date: Monday, February 22, 2010 Sheet 84 of 92
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
x01 change tolerant 20091117 VRAM1 x01 change tolerant 20091117 VRAM2
MDA[0..31] 81 MDA[0..31] 81
K8 E3 MDA3 K8 E3 MDA29
VDD DQL0 MDA7 VDD DQL0 MDA24
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
K2 VDD DQL1 F7 K2 VDD DQL1 F7
C8507
C8510
C8514
C8524
C8516
C8517
C8508 C8509 C8512 C8511 C8513 N1 F2 MDA1 C8515 C8520 N1 F2 MDA30
VDD DQL2 VDD DQL2
1
1
C8525
C8518
C8519
MDA6 MDA26
SC1U6D3V2KX-GP
R9 VDD DQL3 F8 R9 VDD DQL3 F8
MDA2 MDA28
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
B2 H3
VDD DQL4 MDA4 M96 B2 VDD DQL4 H3
MDA27
M96 M96M96 M96 M96 M96M96 M96 D9 H8
M96 M96 M96 M96M96 M96 M96 D9 H8
2
2
D VDD DQL5 MDA0 VDD DQL5 MDA25 D
G7 VDD DQL6 G2 G7 VDD DQL6 G2
R1 H7 MDA5 R1 H7 MDA31
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D7 MDA20 D7 MDA8
DQU0 DQU0
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
A8 C3 MDA19 A8 C3 MDA14
VDDQ DQU1 MDA23 VDDQ DQU1 MDA9
A1 VDDQ DQU2 C8 A1 VDDQ DQU2 C8
SC10U6D3V5KX-1GP
C8502 C8505 C1 C2 MDA18 C8521 C8522 C1 C2 MDA10
VDDQ DQU3 VDDQ DQU3
1
C9 A7 MDA22 C9 A7 MDA15
M96 D2 VDDQ DQU5 A2
MDA21
D2 VDDQ DQU5 A2
MDA13
M96 E9 B8
M96 M96 E9 B8
2
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSAP_2 81 H2 VDDQ DQSU C7 QSAP_1 81
DQSU# B7 QSAN_2 81 DQSU# B7 QSAN_1 81
VRAM1_VREF H1 VRAM2_VREF H1
VRAM2_VREF VREFDQ VRAM1_VREF VREFDQ
M8 VREFCA DQSL F3 QSAP_0 81 M8 VREFCA DQSL F3 QSAP_3 81
1 2 VRAM_ZQ1 L8 G3 QSAN_0 81 1 2VRAM_ZQ2 L8 G3 QSAN_3 81
R8503 243R2F-2-GP ZQ DQSL# R8504 243R2F-2-GP ZQ DQSL#
M96 K1 ODTA0 81
M96 K1 ODTA0 81
ODT ODT
81,86 MAA0 N3 A0 81,86 MAA0 N3 A0
81,86 MAA1 P7 A1 81,86 MAA1 P7 A1
81,86 MAA2 P3 A2 CS# L2 CSA0#_0 81 81,86 MAA2 P3 A2 CS# L2 CSA0#_0 81
81,86 MAA3 N2 A3 RESET# T2 MEM_RST 81,86,87,88 81,86 MAA3 N2 A3 RESET# T2 MEM_RST 81,86,87,88
81,86 MAA4 P8 A4 81,86 MAA4 P8 A4
81,86 MAA5 P2 A5 81,86 MAA5 P2 A5
81,86 MAA6 R8 A6 NC#T7 T7 81,86 MAA6 R8 A6 NC#T7 T7
81,86 MAA7 R2 A7 NC#L9 L9 81,86 MAA7 R2 A7 NC#L9 L9
81,86 MAA8 T8 A8 NC#L1 L1 81,86 MAA8 T8 A8 NC#L1 L1
81,86 MAA9 R3 A9 NC#J9 J9 81,86 MAA9 R3 A9 NC#J9 J9
C 81,86 MAA10 L7 A10/AP NC#J1 J1 81,86 MAA10 L7 A10/AP NC#J1 J1 C
81,86 MAA11 R7 A11 81,86 MAA11 R7 A11
81,86 MAA12 N7 A12/BC# 81,86 MAA12 N7 A12/BC#
81,86 MAA13 T3 A13 VSS J8 81,86 MAA13 T3 A13 VSS J8
M7 NC#M7 VSS M1 M7 NC#M7 VSS M1
VSS M9 VSS M9
VSS J2 VSS J2
81,86 A_BA0 M2 BA0 VSS P9 81,86 A_BA0 M2 BA0 VSS P9
81,86 A_BA1 N8 BA1 VSS G8 81,86 A_BA1 N8 BA1 VSS G8
81,86 A_BA2 M3 BA2 VSS B3 81,86 A_BA2 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
81 CLKA0 J7 CK VSS T9 81 CLKA0 J7 CK VSS T9
81 CLKA0# K7 CK# VSS E1 81 CLKA0# K7 CK# VSS E1
VSS P1 VSS P1
81 CKEA0 K9 CKE 81 CKEA0 K9 CKE
1
VSSQ G1 VSSQ G1
R8508 R8507 F9 F9
56R2F-1-GP 56R2F-1-GP VSSQ VSSQ
81 DQMA2 D3 DMU VSSQ E8 81 DQMA1 D3 DMU VSSQ E8
M96 M96 81 DQMA0 E7 DML VSSQ E2
D8
81 DQMA3 E7 DML VSSQ E2
D8
2
VSSQ VSSQ
VSSQ D1 VSSQ D1
GPU_CLKA0_T 81 WEA0# L3 B9 81 WEA0# L3 B9
W E# VSSQ W E# VSSQ
81 CASA0# K3 CAS# VSSQ B1 81 CASA0# K3 CAS# VSSQ B1
81 RASA0# J3 RAS# VSSQ G9 81 RASA0# J3 RAS# VSSQ G9
1
C8503
SCD01U16V2KX-3GP M96
DUMMY-K4W2G1646B-HC12-GP DUMMY-K4W2G1646B-HC12-GP
2
B
x01 20091121
M96 M96 B
+1.5V_RUN
+1.5V_RUN
1
1
R8513
R8510 2K1R2F-GP
2K1R2F-GP
M96
M96
2
2
VRAM2_VREF
VRAM1_VREF
1
C8506
1
C8504 R8512 SCD1U10V2KX-5GP

R8511 SCD1U10V2KX-5GP 2K1R2F-GP M96
M96
2
2K1R2F-GP
M96
2
M96
2
2

A A
<Core Design>
Wistron Corporation
Title
Size
GPU-VRAM1,2 (1/4)
Document Number Rev
Custom Berry A00
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
MDA[32..63] 81 MDA[32..63] 81
K8 E3 MDA36 K8 E3 MDA61
SC1U6D3V2KX-GP VDD DQL0 MDA38 VDD DQL0 MDA57
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
K2 VDD DQL1 F7 K2 VDD DQL1 F7
C8602
C8610
C8612
C8611
C8614
C8613
C8621
C8618
C8623
C8622
C8625
C8624
C8616
C8615
MDA33 MDA63
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 N1 VDD DQL2 F2 N1 VDD DQL2 F2
1
C8607
C8609
R9 F8 MDA39 MDA60
B2
VDD DQL3
H3 MDA32 M96 R9
B2
VDD DQL3 F8
H3 MDA59
M96 M96M96 M96M96 M96 M96 M96 D9 H8
M96 M96M96 M96 M96 M96M96 D9 H8
2
2
R1 H7 MDA37 R1 H7 MDA58
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
x01 change tolerant 20091117 D7 MDA46 D7 MDA50
D DQU0 MDA43 DQU0 MDA55 D
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
MDA45 MDA49
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C8606 C1 C2 MDA40 C8617 C8619 C1 C2 MDA52
VDDQ DQU3 VDDQ DQU3
1
C8608 C9 A7 MDA44 C9 A7 MDA48
D2 A2
VDDQ DQU5 MDA47 M96 M96 D2 VDDQ DQU5 A2
MDA51
M96 M96 E9 B8 E9 B8
2
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSAP_5 81 H2 VDDQ DQSU C7 QSAP_6 81
DQSU# B7 QSAN_5 81 DQSU# B7 QSAN_6 81
M8 VREFCA DQSL F3 QSAP_4 81 M8 VREFCA DQSL F3 QSAP_7 81
1 2VRAM_ZQ3 L8 ZQ DQSL# G3 QSAN_4 81 1 2VRAM_ZQ4 L8 ZQ DQSL# G3 QSAN_7 81
R8603 243R2F-2-GP R8604 243R2F-2-GP
M96 K1 ODTA1 81
M96 K1 ODTA1 81
ODT ODT
81,85 MAA0 N3 A0 81,85 MAA0 N3 A0
81,85 MAA1 P7 A1 81,85 MAA1 P7 A1
81,85 MAA2 P3 A2 CS# L2 CSA1#_0 81 81,85 MAA2 P3 A2 CS# L2 CSA1#_0 81
81,85 MAA3 N2 A3 RESET# T2 MEM_RST 81,85,87,88 81,85 MAA3 N2 A3 RESET# T2 MEM_RST 81,85,87,88
81,85 MAA4 P8 A4 81,85 MAA4 P8 A4
81,85 MAA5 P2 A5 81,85 MAA5 P2 A5
81,85 MAA6 R8 A6 NC#T7 T7 81,85 MAA6 R8 A6 NC#T7 T7
81,85 MAA7 R2 A7 NC#L9 L9 81,85 MAA7 R2 A7 NC#L9 L9
81,85 MAA8 T8 A8 NC#L1 L1 81,85 MAA8 T8 A8 NC#L1 L1
81,85 MAA9 R3 A9 NC#J9 J9 81,85 MAA9 R3 A9 NC#J9 J9
81,85 MAA10 L7 A10/AP NC#J1 J1 81,85 MAA10 L7 A10/AP NC#J1 J1
81,85 MAA11 R7 A11 81,85 MAA11 R7 A11
81,85 MAA12 N7 A12/BC# 81,85 MAA12 N7 A12/BC#
81,85 MAA13 T3 A13 VSS J8 81,85 MAA13 T3 A13 VSS J8
C M7 NC#M7 VSS M1 M7 NC#M7 VSS M1 C
VSS M9 VSS M9
VSS J2 VSS J2
81,85 A_BA0 M2 BA0 VSS P9 81,85 A_BA0 M2 BA0 VSS P9
81,85 A_BA1 N8 BA1 VSS G8 81,85 A_BA1 N8 BA1 VSS G8
81,85 A_BA2 M3 BA2 VSS B3 81,85 A_BA2 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
81 CLKA1 J7 CK VSS T9 81 CLKA1 J7 CK VSS T9
81 CLKA1# K7 CK# VSS E1 81 CLKA1# K7 CK# VSS E1
VSS P1 VSS P1
81 CKEA1 K9 CKE 81 CKEA1 K9 CKE
1
VSSQ G1 VSSQ G1
R8607 R8608 F9 F9
81 DQMA5 D3 DMU VSSQ E8 81 DQMA6 D3 DMU VSSQ E8
M96 M96 81 DQMA4 E7 DML VSSQ E2
D8
81 DQMA7 E7 DML VSSQ E2
D8
2
VSSQ VSSQ
VSSQ D1 VSSQ D1
GPU_CLKA1_T 81 WEA1# L3 B9 81 WEA1# L3 B9
W E# VSSQ W E# VSSQ
81 CASA1# K3 CAS# VSSQ B1 81 CASA1# K3 CAS# VSSQ B1
81 RASA1# J3 RAS# VSSQ G9 81 RASA1# J3 RAS# VSSQ G9
1
C8603
SCD01U16V2KX-3GP M96
DUMMY-K4W2G1646B-HC12-GP DUMMY-K4W2G1646B-HC12-GP
2
x01 20091121
M96 M96
B B
+1.5V_RUN
+1.5V_RUN
1
R8605
1
2K1R2F-GP
R8601
2K1R2F-GP M96
2
M96 VRAM4_VREF
2
VRAM3_VREF
1
C8605
R8606 SCD1U10V2KX-5GP
M96
1
C8601 2K1R2F-GP
2
R8602 SCD1U10V2KX-5GP
2K1R2F-GP M96 M96
2
2
M96
2

A A
<Core Design>
Wistron Corporation
Title

GPU-VRAM3,4 (2/4) Rev
Custom
Berry A00
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
MDB[0..31] 81 MDB[0..31] 81
K8 E3 MDB14 K8 E3 MDB16
VDD DQL0 MDB13 VDD DQL0 MDB18
K2 F7 K2 F7
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8702
C8710
C8714
C8717
C8715
C8720
C8723
C8722
C8724
C87011
C87012
C87013
N1 F2 N1 F2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 VDD DQL2 VDD DQL2
1
MDB15 MDB19
C8707
C8709
C8721
C8725
B2 H3 MDB11 DY B2 H3 MDB22
VDD DQL4 VDD DQL4
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
D9 H8 MDB8 D9 H8 MDB17
2
2
R1 H7 MDB10 R1 H7 MDB21
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D D7 MDB26 D7 MDB1 D
DQU0 MDB27 DQU0 MDB5
A1 C8 MDB30 A1 C8 MDB2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C8706 VDDQ DQU2 MDB24 C8718 C8719 VDDQ DQU2 MDB4
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2
1
C8708 C9 A7 MDB31 C9 A7 MDB3
VDDQ DQU4 MDB25 VDDQ DQU4 MDB7
D2 VDDQ DQU5 A2 D2 VDDQ DQU5 A2
DIS
DIS
DIS
DIS
E9 B8 MDB29 E9 B8 MDB0
2
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSBP_3 81 H2 VDDQ DQSU C7 QSBP_0 81
DQSU# B7 QSBN_3 81 DQSU# B7 QSBN_0 81
M8 VREFCA DQSL F3 QSBP_1 81 M8 VREFCA DQSL F3 QSBP_2 81
1 2 VRAM_ZQ5 L8 G3 QSBN_1 81 1 2 VRAM_ZQ6 L8 G3 QSBN_2 81
DIS DIS
ODT K1 ODTB0 81 ODT K1 ODTB0 81
81,88 MAB0 N3 A0 81,88 MAB0 N3 A0
81,88 MAB1 P7 A1 81,88 MAB1 P7 A1
81,88 MAB2 P3 A2 CS# L2 CSB0#_0 81 81,88 MAB2 P3 A2 CS# L2 CSB0#_0 81
81,88 MAB3 N2 A3 RESET# T2 MEM_RST 81,85,86,88 81,88 MAB3 N2 A3 RESET# T2 MEM_RST 81,85,86,88
81,88 MAB4 P8 A4 81,88 MAB4 P8 A4
81,88 MAB5 P2 A5 81,88 MAB5 P2 A5
81,88 MAB6 R8 A6 NC#T7 T7 81,88 MAB6 R8 A6 NC#T7 T7
81,88 MAB7 R2 A7 NC#L9 L9 81,88 MAB7 R2 A7 NC#L9 L9
81,88 MAB8 T8 A8 NC#L1 L1 81,88 MAB8 T8 A8 NC#L1 L1
81,88 MAB9 R3 A9 NC#J9 J9 81,88 MAB9 R3 A9 NC#J9 J9
81,88 MAB10 L7 A10/AP NC#J1 J1 81,88 MAB10 L7 A10/AP NC#J1 J1
81,88 MAB11 R7 A11 81,88 MAB11 R7 A11
81,88 MAB12 N7 A12/BC# 81,88 MAB12 N7 A12/BC#
C T3 J8 T3 J8 C
81,88 MAB13 A13 VSS 81,88 MAB13 A13 VSS
VSS M9 VSS M9
VSS J2 VSS J2
81,88 B_BA0 M2 BA0 VSS P9 81,88 B_BA0 M2 BA0 VSS P9
81,88 B_BA1 N8 BA1 VSS G8 81,88 B_BA1 N8 BA1 VSS G8
20090902 81,88 B_BA2 M3 BA2 VSS B3
T1
81,88 B_BA2 M3 BA2 VSS B3
T1
VSS VSS
VSS A9 VSS A9
81 CLKB0 J7 CK VSS T9 81 CLKB0 J7 CK VSS T9
81 CLKB0# K7 CK# VSS E1 81 CLKB0# K7 CK# VSS E1
VSS P1 VSS P1
1
81 CKEB0 K9 CKE 81 CKEB0 K9 CKE

R8707 R8708 G1 G1
VSSQ F9 VSSQ F9
DIS DIS 81 DQMB3 D3 DMU VSSQ E8 81 DQMB0 D3 DMU VSSQ E8
81 DQMB1 E7 E2 81 DQMB2 E7 E2
2
DML VSSQ DML VSSQ

VSSQ D8 VSSQ D8
GPU_CLKB0_T D1 D1
VSSQ VSSQ
81 W EB0# L3 WE# VSSQ B9 81 W EB0# L3 WE# VSSQ B9
81 CASB0# K3 CAS# VSSQ B1 81 CASB0# K3 CAS# VSSQ B1
1
C8703 DIS 81 RASB0# J3 G9 81 RASB0# J3 G9

SCD01U16V2KX-3GP RAS# VSSQ RAS# VSSQ
2
DUMMY-K4W 2G1646B-HC12-GP DUMMY-K4W 2G1646B-HC12-GP
x01 20091121 DIS DIS

B B
+1.5V_RUN +1.5V_RUN
1
1
R8701 R8703
2K1R2F-GP 2K1R2F-GP
DIS DIS
2
2
VRAM5_VREF VRAM6_VREF
1
1
C8701 C8705
R8702 SCD1U10V2KX-5GP R8705 SCD1U10V2KX-5GP
2K1R2F-GP 2K1R2F-GP
DIS DIS
2
2
DIS DIS
2
2
A <Core Design> A
Wistron Corporation
Title
GPU-VRAM5,6 (3/4)
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
MDB[32..63] 81 MDB[32..63] 81
K8 E3 MDB40 K8 E3 MDB53
K2 F7 K2 F7
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8802
C8808
C8809
C8810
C8813
C8814
C8816
C8819
C8820
C8822
C8823
C8824
N1 F2 N1 F2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDD DQL2 VDD DQL2
1
1
MDB44 MDB49
C8811
C8812
C8821
C8825
B2 H3 MDB41 DY DY DY B2 H3 MDB54
VDD DQL4 VDD DQL4
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
D9 H8 MDB45 D9 H8 MDB48
2
2
D R1 H7 MDB46 R1 H7 MDB50 D
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D7 MDB36 D7 MDB61
DQU0 MDB35 DQU0 MDB62
A1 C8 MDB39 A1 C8 MDB58
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C8806 C8807 VDDQ DQU2 MDB32 C8817 C8818 VDDQ DQU2 MDB59
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2
1
C9 A7 MDB37 C9 A7 MDB63
DIS D2 VDDQ DQU5 A2 DIS DIS D2 VDDQ DQU5 A2
DIS
E9 B8 MDB38 E9 B8 MDB57
2
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSBP_4 81 H2 VDDQ DQSU C7 QSBP_7 81
DQSU# B7 QSBN_4 81 DQSU# B7 QSBN_7 81
M8 VREFCA DQSL F3 QSBP_5 81 M8 VREFCA DQSL F3 QSBP_6 81
1 2 VRAM_ZQ7 L8 G3 QSBN_5 81 1 2 VRAM_ZQ8 L8 G3 QSBN_6 81
DIS DIS
ODT K1 ODTB1 81 ODT K1 ODTB1 81
81,87 MAB0 N3 A0 81,87 MAB0 N3 A0
81,87 MAB1 P7 A1 81,87 MAB1 P7 A1
81,87 MAB2 P3 A2 CS# L2 CSB1#_0 81 81,87 MAB2 P3 A2 CS# L2 CSB1#_0 81
81,87 MAB3 N2 A3 RESET# T2 MEM_RST 81,85,86,87 81,87 MAB3 N2 A3 RESET# T2 MEM_RST 81,85,86,87
81,87 MAB4 P8 A4 81,87 MAB4 P8 A4
81,87 MAB5 P2 A5 81,87 MAB5 P2 A5
81,87 MAB6 R8 A6 NC#T7 T7 81,87 MAB6 R8 A6 NC#T7 T7
81,87 MAB7 R2 A7 NC#L9 L9 81,87 MAB7 R2 A7 NC#L9 L9
81,87 MAB8 T8 A8 NC#L1 L1 81,87 MAB8 T8 A8 NC#L1 L1
81,87 MAB9 R3 A9 NC#J9 J9 81,87 MAB9 R3 A9 NC#J9 J9
81,87 MAB10 L7 A10/AP NC#J1 J1 81,87 MAB10 L7 A10/AP NC#J1 J1
C R7 R7 C
81,87 MAB11 A11 81,87 MAB11 A11
81,87 MAB12 N7 A12/BC# 81,87 MAB12 N7 A12/BC#
81,87 MAB13 T3 A13 VSS J8 81,87 MAB13 T3 A13 VSS J8
VSS M9 VSS M9
VSS J2 VSS J2
81,87 B_BA0 M2 BA0 VSS P9 81,87 B_BA0 M2 BA0 VSS P9
81,87 B_BA1 N8 BA1 VSS G8 81,87 B_BA1 N8 BA1 VSS G8
81,87 B_BA2 M3 BA2 VSS B3 81,87 B_BA2 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
81 CLKB1 J7 CK VSS T9 81 CLKB1 J7 CK VSS T9
81 CLKB1# K7 CK# VSS E1 81 CLKB1# K7 CK# VSS E1
VSS P1 VSS P1
1
81 CKEB1 K9 CKE 81 CKEB1 K9 CKE

R8807 R8808 G1 G1
VSSQ F9 VSSQ F9
DIS DIS 81 DQMB4 D3 DMU VSSQ E8 81 DQMB7 D3 DMU VSSQ E8
81 DQMB5 E7 E2 81 DQMB6 E7 E2
2
DML VSSQ DML VSSQ

VSSQ D8 VSSQ D8
GPU_CLKB1_T D1 D1
VSSQ VSSQ
81 W EB1# L3 WE# VSSQ B9 81 W EB1# L3 WE# VSSQ B9
81 CASB1# K3 CAS# VSSQ B1 81 CASB1# K3 CAS# VSSQ B1
1
C8803 DIS 81 RASB1# J3 G9 81 RASB1# J3 G9

SCD01U16V2KX-3GP RAS# VSSQ RAS# VSSQ
2
DUMMY-K4W 2G1646B-HC12-GP DUMMY-K4W 2G1646B-HC12-GP
B x01 20091121 DIS DIS B
+1.5V_RUN +1.5V_RUN
1
1
R8801 R8805
2K1R2F-GP 2K1R2F-GP
DIS DIS
2
2
VRAM7_VREF VRAM8_VREF
1
1
C8801 C8804
R8802 SCD1U10V2KX-5GP R8806 SCD1U10V2KX-5GP
2K1R2F-GP 2K1R2F-GP
DIS DIS
2
2
DIS DIS
2

A <Core Design> A
Wistron Corporation
Title
GPU-VRAM7,8 (4/4)
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = Video.PWR.Regulator RT8208BGQW for +VGA_CORE
D D
+PW R_SRC
X01 EMI stuff 20091118
SCD1U25V2KX-GP
X01 20091111
SC2200P50V2KX-2GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PC8911
PC8907
1
1
PC8914
PC8903
PC8905
DIS DIS
DIS DIS DIS
2
+5V_RUN
5
6
7
8
Vout=0.75V*(R1+R2)/R2
D
D
D
D
PU8902
SI7686DP-T1-GP
PR8910 DIS Design Current = 21.94A

1
PC8908 +GFX_CORE_TON 1 DIS 2 24.14A<OCP< 28.53A
G
S
S
S
SC1U10V2KX-1GP
DIS
2
249KR2F-GP
4
3
2
1
PU8901
PR8902 X02-20100116
PC8906 +VGA_CORE
PR8903 16 13 +GFX_CORE_BOOT
2 DIS 1+GFX_CORE_BOOT_C
1 DIS2
TON BOOT
2 DIS 1 9 VDDP
1R3J-L1-GP
PL8901 x01 change tolerant 20091117
10R2F-L-GP 12 +GFX_CORE_UGATE SCD1U25V3KX-GP
+GFX_CORE_VDD UGATE +GFX_CORE_PHASE
2 VDD PHASE 11 1 2
+GFX_CORE_LGATE IND-D56UH-12-GP
X01 20091124 LGATE 8
PC8915
DIS
SCD1U10V2KX-5GP
1
1
PR8906 PTC8901
49,50,51,90 RUNPW ROK DIS 2+GFX_CORE_CS 4 7
GAP-CLOSE-PWR-3-GP
PGOOD G0 PW RCNTL_0 82
1
SE330U2VDM-L-GP
C +GFX_CORE_FB PU8903 PU8904 DY PTC8902 PTC8903 C
1 10 CS DIS FB 3
DY
5
6
7
8
5
6
7
8
SE330U2VDM-L-GP
SE330U2VDM-L-GP
PR8905 7K15R2F-L-GP 14 2D2R5F-2-GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
PW RCNTL_1 82
2
G1
1
D
D
D
D
D
D
D
D
PW RCNTL_1#
PG8920
5
DIS
2
D1
1
+GFX_CORE_EN_R 15 6 PW RCNTL_0# DY DIS
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
EM/DEM D0
1VGA_CORE_DIV
PC8904 DIS
SC1U10V2KX-1GP 17 1 +GFX_CORE_VOUT DIS DIS
2
2
GND VOUT
1
S
S
S
S
S
S
G
G
RT8208BGQW -GP
DY DY
4
3
2
1
4
3
2
1
+GFX_CORE_VOUT
2
A00-20100204 PC8910
1
SC330P50V2KX-3GP
PC8917
PC8913
RT8208B:74.08208.A73 PR8908
37 GFX_CORE_EN 1
PR8921
2
0R0402-PAD DY 10KR2F-2-GP
2
DIS
X01 20091111
2
X02-20100201
K A +GFX_CORE_EN_R
22,37,42,47,50,51 PM_SLP_S3#
D8901
DYRB551V-30-2GP
+GFX_CORE_FB
1
PC8912 x01 20091124

SCD1U10V2KX-5GP
DY
1
2
x01 change tolerant 20091117 PR8909 PR8911 PR8912

DIS 150KR2F-L-GP 49K9R2F-L-GP 44K2R2F-1-GP
DIS
DIS
2
B B
PWRCNTL_0#
PWRCNTL_1#
Park-XT
Madison-LP
PWRCNTL_0 PWRCNTL_1 +VGA_CORE
H H 0.9V
H H 0.9V
L H 0.95V
L H 0.95V
H L 1.05V
L L 1.12V
L L 1.12V
M96-LP
H H 0.9V
L H 0.95V
L L 1.0V
A <Core Design> A
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Wistron Corporation

Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
O/P cap: 330U 2.5V PSLV0E337M(15) 15mOhm 2.886Arms NEC_TOKIN/ 77.C3371.10L Taipei Hsien 221, Taiwan, R.O.C.
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 Title
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037
RT8208B_+VGA_CORE
A3
Arsenal DJ1 Discrete A00
Date: W ednesday, March 31, 2010 Sheet 89 of 92
5 4 3 2 1
5 4 3 2 1
APL5930 for +1.8V_RUN_VGA

+1.8V_RUN_VGA_P +1.8V_RUN_VGA
PG9002
1 2
+3.3V_RUN +1.8V_RUN_VGA_VIN +5V_RUN +1.8V_RUN_VGA_VIN
GAP-CLOSE-PWR
PG9003
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
1
D D
PG9001 PC9002 PC9003 PC9004
2 1 DIS GAP-CLOSE-PWR
SC1U10V2KX-1GP DY
2
GAP-CLOSE-PWR DIS
PG9004
2 1
+5V_ALW GAP-CLOSE-PWR
X02-20091230 Design Current =1.13A
6
PU9001
X02-20091230
M96
VCNTL
2
49,50,51,89 RUNPWROK 1 21.8V_RUN_VGA_POK 7 5

R9006 R9009 0R2J-2-GP POK VIN#5 +1.8V_RUN_VGA_P
9
PR9002 VIN#9
M96 100KR2J-1-GP
37 1.8V_VGA_RUN_EN 1 21.8V_VGA_RUN_EN_C 8 3
EN VOUT#3
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
0R0402-PAD 4
1
VOUT#4 PR9003 PC9005 PC9006 PC9007

Vo=0.8*(1+(R1/R2)) DIS
1
16K5R2F-2-GP
SC68P50V2JN-1GP
PC9001 DIS
DY
1.8V_DIS_GATE
SC4700P50V2KX-1GP
DY 2
GND
FB
DIS
2
DIS
5912_1.8V_DELAY_FB
APL5930KAI-TRG-GP
2
SO-8-P
X02-20091230
6
PQ9001 +1.8V_RUN_VGA
M96 2N7002EDW-GP
84.27002.F3F
1
1
M96 Vout=0.8V*(R1+R2)/R2 PR9006
13K3R2F-L1-GP
1.8V_DIS 1 2 DIS
R9005 10R2J-2-GP
2
1.8V_VGA_RUN_EN
C C
+3.3V_RUN_VGA X02-20091208
APL5930KAI for +1.0V_RUN_VGA
PARK
1 2 +5V_ALW +1.5V_SUS
R9001 0R2J-2-GP
+3.3V_RUN_VGA
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
Q9001
1
+3.3V_ALW PC9008 PC9009 PC9010
+3.3V_RUN S D M96 M96 DY
SI2301CDS-T1-GE3-GP SC1U10V2KX-1GP
M96
2
1
Id: 2A R9007 +1.0V_RUN_VGA

G
R9002 M96
100KR2J-1-GP M96 Rds: 0.15ohm 100KR2J-1-GP
Design Current: 1.51A
2
6
3.3V_ALW_1 PU9002
+1.0V_RUN_VGA +1.05V_VTT
1.0V_DIS_GATE
VCNTL
49,50,51,89 RUNPWROK 7 5
POK VIN#5
1
R9004 9
VIN#9
6
Q9002 100R2J-2-GP PR9007 X02-20091208

M96 37 1.0V_RUN_VGA_EN 1 21.0V_RUN_VGA_EN_C 8 3
PARK
1 2
2N7002EDW-GP 0R0402-PAD EN VOUT#3 R9011 0R5J-5-GP
4
VOUT#4
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
84.27002.F3F M96
SC4700P50V2KX-1GP
2
1
12KR2F-L-GP
X02-20091224 PC9011 M96 PR9009 PC9012 PC9013 X01 20091120
1
DY 2 M96 M96 DYPC9014
GND
FB
6
M96
SCD01U16V2KX-3GP
2
2
PQ9002
3.3V_RUN_VGA_1 M96 2N7002EDW-GP APL5930KAI-TRG-GP
2
SO-8-P
84.27002.F3F +1.0V_RUN_VGA
1
B B
37 3.3V_RUN_VGA_EN M96
1.0V_DIS_GATE_EN
1.0V_DIS 1 2
R9010 10R2J-2-GP
5930_1.0VRUN_FB
1
M96 2 1.0V_RUN_VGA_EN
1
R9003 0R2J-2-GP PR9011
Vout=0.8V*(R1+R2)/R2
M96 32K4R2F-1-GP
1
DY 2 RUNPWROK
R9008 0R2J-2-GP
2
X01-20091116
A A
<Core Design>
Wistron Corporation
Title
DISCRETE VGA POWER
C Berry A00
5 4 3 2 1
5 4 3 2 1
D15 Intel-Power Up Sequence

(AC mode) red word: KBC GPIO
(DC mode) red word: KBC GPIO
+RTC_VCC
+RTC_VCC T1
T1
PCH_RTCRST#
PCH_RTCRST#
+PWR_SRC
+PWR_SRC T2
T2
+3.3V_RTC_LDO
+3.3V_RTC_LDO
T3 KBC GPIO36 control
D Press Power button D
S5_ENABLE KBC_PWRBTN_EC# KBC_PWRBTN_EC# GPIO3
T4
+5V_ALW EC_ENABLE# (GPIO51) keep low
T5 T3
+KBC_PWR
+3.3V_ALW T4 KBC GPIO36 control
T6
S5_ENABLE
+5VALW_PCH_VCC5REFSUS T5
+5V_ALW
T6 +5V_ALW & +3.3V_ALW need meet 0.7V difference
+15V_ALW T7
T8 TPS51125 to KBC GPIO46 +3.3V_ALW
T7 +5V_ALW & +3.3V_ALW need meet 0.7V difference
3V_5V_POK
PCH to KBC GPI94 +5VALW_PCH_VCC5REFSUS
SUS_PWR_DN_ACK T9
KBC GPIO43 to PCH +15V_ALW T8
T10 T9 TPS51125 to KBC GPIO46
PCH_RSMRST#(EC Delay 40ms) >10ms
T11 PCH to KBC GPIO00 3V_5V_POK
T10 KBC GPO84 to PCH
PCH_SUSCLK_KBC
PM_PWRBTN#
AC_PRESENT_EC T12 <200ms PCH to KBC GPI94
SUS_PWR_DN_ACK T11
KBC GPIO43 to PCH
PCH_RSMRST# T12 >10ms
PCH to KBC GPIO01
Press Power button T13
PCH_SUSCLK_KBC
AC KBC_PWRBTN_EC# KBC_PWRBTN_EC# GPIO3
3V_5V_POK
T13 KBC GPO84 to PCH DC PCH_RSMRST#
AC PM_PWRBTN# T14
PM_SLP_S4#
AC PM_PWRBTN# T15
T14 PM_SLP_S3# >30us
T16 KBC GPO16 to LAN
PM_LAN_ENABLE
PM_SLP_S4# T17
T15
+3.3V_LAN
PM_SLP_S3# >30us
C
T16 KBC GPO16 to LAN C
+1.5V_SUS T18
PM_LAN_ENABLE
T17
+V_DDR_REF(0.9V) T19
+3.3V_LAN +5V_RUN & +3.3V_RUN need meet 0.7V difference
+5V_RUN T20
+1.5V_SUS T18
+3.3V_RUN T21
+V_DDR_REF(0.9V) T19 T22
+5V_RUN & +3.3V_RUN need meet 0.7V difference
+5VS_PCH_VCC5REF
+5V_RUN T20
+1.5V_RUN T23 H_PWRGD
+3.3V_RUN T21 T25 >1ms
T22
+1.8V_RUN T24
+5VS_PCH_VCC5REF KBC GPIO71 to RT8208B
GFX_CORE_EN(Discrete only) T26
+1.5V_RUN T23 H_PWRGD
T25 >1ms T27
+VGA_CORE(Discrete only)
+1.8V_RUN T24 T28 KBC GPIO30 to APL5930
KBC GPIO71 to RT8208B 1.0V_RUN_VGA_EN(Discrete only)
GFX_CORE_EN(Discrete only)------Delay 5ms T26
T29
T27 +1.0V_RUN_VGA(Discrete only)
+VGA_CORE(Discrete only) T30 KBC GPIO66 to APL5930
T28 KBC GPIO30 to APL5930 1.8V_VGA_RUN_EN(Discrete only)
1.0V_RUN_VGA_EN(Discrete only)------Delay 4ms
T31
T29 +1.8V_RUN_VGA(Discrete only)
+1.0V_RUN_VGA(Discrete only) T32 KBC GPI95
T30 KBC GPIO66 to APL5930 +3.3V_RUN_VGA_EN(Discrete only)-->DY reserved
1.8V_VGA_RUN_EN(Discrete only)------Delay 5ms T33
T31 +3.3V_RUN_VGA(Discrete only) -->Reserved for sequence
+1.8V_RUN_VGA(Discrete only)
T32 KBC GPI95
+3.3V_RUN_VGA_EN(Discrete only)-->DY reserved RUNPWROK T34
T33
T35
+3.3V_RUN_VGA(Discrete only) -->Reserved for sequence +1.05V_VTT
T36 TPS51218 to KBC GPI34
1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output for s3 reduction)
RUNPWROK T34
T37
T35 +0.75V_DDR_VTT
+1.05V_VTT
B
T36 TPS51218 to KBC GPI34 H_VTTPWRGD T38 B
1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output for s3 reduction)

T37
+0.75V_DDR_VTT
H_VTTPWRGD T38
+1.05V_VTT
T39
CPU to TPS51611
GFX_VR_EN(UMA only)
+1.05V_VTT UMA GFX CORE Power
T39 T40
CPU to TPS51611 +CPU_GFX_CORE(UMA only)
GFX_VR_EN(UMA only)
T40 UMA GFX CORE Power
+CPU_GFX_CORE(UMA only)
1.5CPU_1.05VTT_PWRGD
T41 ( >99ms )
KBC GPO53 to ISL62883
IMVP_VR_ON
1.5CPU_1.05VTT_PWRGD T42
T41 ( >99ms ) CPU CORE Power
KBC GPO53 to ISL62883 +VCC_CORE <3ms
IMVP_VR_ON
T42 CLK_CPU_BCLK
CPU CORE Power CLKIN_BCLK(from CK505) stable
+VCC_CORE <3ms
43 >1ms ISL62883 to CLOCKGEN
CLK_CPU_BCLK
CLKIN_BCLK(from CK505) stable CK_PWRGD
ISL62884 to KBC GPO14
T44 >1ms
43 >1ms ISL62883 to CLOCKGEN IMVP_PWRGD T45
CK_PWRGD 1.5CPU_1.05VTT_PWRGD Delay 10ms
ISL62884 to KBC GPO14 T46 >5ms
T44 >1ms
IMVP_PWRGD T45 KBC GPIO47 to PCH
1.5CPU_1.05VTT_PWRGD Delay 10ms PM_PWROK 3ms< T47 <20ms
T46 >5ms
T48 >1ms
KBC GPIO47 to PCH +1.5V_RUN_CPU T49 >100ns
PM_PWROK 3ms< T47 <20ms PM_DRAM_PWRGD (for S3 Reduction)
T48 >1ms
+1.5V_RUN_CPU T49 >100ns
H_VTTPWRGD
A
PM_DRAM_PWRGD (for S3 Reduction) T50 >1ms A
PM_PWROK
H_VTTPWRGD T51 >1ms
T50 >1ms
+VCC_CORE
PM_PWROK 0.05ms< T52 <650ms
T51 >1ms
H_PWRGD
T53 KBC LRESET#
+VCC_CORE
0.05ms< T52 <650ms PLT_RST# >1ms
T54 KBC GPIO45
H_PWRGD <Core Design>
T53 KBC LRESET# PLTRST_DELAY#
T55
PLT_RST# >1ms
T54 H_CPURST# Wistron Corporation
KBC GPIO45 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
PLTRST_DELAY#
T55 Title
H_CPURST# Power Sequence
A1
Berry A00
Date: Tuesday, March 02, 2010 Sheet 91 of 92
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Change History
A3
Berry A00
5 4 3 2 1

Dell Inspiron N5010-Intel

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Dell Inspiron N5010-Intel

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5 4 3 2 1

Berry DG15 Discrete/UMA Schematics Document

UMA:UMA platform installed

Size Document Number

Dell P/N:C995R$AA SAMSUNG

2.Park-XT;1GB (128Mx16b*4) DDR3 Revision : 09909-1 SYSTEM DC/DC

PCIE x 1 10/100 NIC RJ45 +PWR_SRC +CPU_GFX_CORE

PCI/PCI BRIDGE SYSTEM DC/DC

SATA x 2 HDD +1.5V_SUS +1.5V_RUN

Internal Analog MIC +5V_ALW +5V_RUN

ISL62883 TPS51218 TPS51611

UP7534BRA8 AO4468 UP7534BRA8 AO4468 PA102FMG

+5V_USB1 +5V_RUN +5V_USB2 +3.3V_RUN +3.3V_RUN_VGA +3.3V_LAN

+1.8V_RUN_VGA +LCDVDD +3.3V_RUN_CARD +1.2V_LOM

Regulator LDO Switch

SRN2K2J-1-GP Minicard GPIO73/SCL2 KBC_SCL1

DDC1DATA LCD CONN

+3.3V_RUN DIS +5V_RUN

SMBUS Block Diagram

Thermal Block Diagram Audio Block Diagram

Place near CPU

PCH Strapping Processor Strapping

GPIO33 Default: Do not pull low.

PCIE Routing USB Table SATA Table

23 CLK_PCIE_SATA 1 4 CLK_PCIE_SATA_C 10 SRC_1/SATA

23 CLK_CPU_BCLK 23 27 CLK_XTAL_OUT EC703

Clock Generator SLG8SP585

PCI EXPRESS -- GRAPHICS

C26 PEG_C_TXN0 C801 1DIS 2 SCD1U10V2KX-5GP PEG_TXN0

SRN1KJ-4-GP PEG_TX2 PEG_C_TXP12 C829 SCD1U10V2KX-5GP PEG_TXP12

PEG_TX3 PEG_C_TXP11 C828 SCD1U10V2KX-5GP PEG_TXP11

x01 change tolerant 20091117

JTAG & BPM

XDP_OBS3 17 18 XDP_TDO_R 1 R934 2

No Stuff --> R931, R934, R933

R938 0R2J-2-GP 47 48 R939 1KR2J-1-GP XDP_DBRESET# 22,23

SSID = CPU CPU1D 4 OF 9

M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ40 AK3 AR5 M_B_DQS#6

DDR SYSTEM MEMORY - B

A CLARKUNF <Core Design> A

TPAD14-GP TP1105 1 CFG6 AN29 AP33

0:Enabled; An external Display Port SA_CK2

DY CFG7 Clarksfield (only for early samples pre-ES1) -

SSID = CPU CPU1F 6 OF 9

1.1V RAIL POWER

C1225 C1227 DY DY AC31

VCC VTT0 C1234

R28 AJ34 VCC_SENSE 47

Size Document Number

PEG & DMI

C1320 DY J25 H20

SC10U6D3V5KX-1GP H27 H19

x01 change tolerant 20091117

Size Document Number

AT20 VSS VSS AE34

NCYF TEST PIN:

SSID = MEMORY M_A_DM[7..0] 10

C1812 M_A_DQ40 DQ39

B M_A_DQS#5 DQS4# VSS B

VSS 42,50 PS_S3CNTRL

SSID = MEMORY DM2

M_B_A0 98 NP1 M_B_DM[7..0] 10

C1916 DQS7 VSS