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Simulation and implementation of the BPSK modulation on a FPGA Xilinx Spartan 3 xcs200-

4ftp256, using Simulink and the System Generator blockset for DSP/FPGA.

Johanna S. Ruque*, David I. Ruiz*, Carlos E. Carrión&

jsruquex@utpl.edu.ec, diruizx@utpl.edu.ec, cecarrion1@utpl.edu.ec

School of Electronic and Telecommunications,

Group of Electricity and Electronic Systems
Technical University of Loja.

Abstract the carrier of the original transmitter. The

This work presents the simulation of a BPSK balanced modulator is a product detector whose
modulation using the Matlab’s Simulink output is the product of the two inputs (the
program, as well as its implementation in a BPSK signal and the recovered carrier). Since
Xilinx’s Spartan 3 Field Programmable Gate the only possible outputs are the signals cos(ωt)
Array (FPGA) development board. and –cos(ωt), the product detector’s possible
outputs will be:
The steps taken to simulate the modulation and cos2(ωt) = ½ + ½ cos(2ωt),
demodulation blocks are shown. The rules for cos2(ωt) = - ½ - ½ cos(2ωt),
the realization of FSK and OOK modulations
are also presented.


BPSK Modulation

In this modulation one has as possible results

two exit phases for the carrier with a single
frequency. An exit phase represents a logical 1
and the other one a logical 0. As the input
digital signal changes the state, the phase of the Figure 1
exit carrier moves between two angles that lie
180° outside of phase.

BPSK Transmitter

Figure 1 shows a simplified block diagram of a

BPSK modulator. The coded signal enters to a
multiplexer that commutes the phase of the
carrier signal. Depending on the logical
condition of the digital input, the carrier is
transferred to the output, either in phase or at
180° outside of phase, with the reference carrier Figure 2: BPSK Modulation.

The output spectrum of a BPSK modulator is

only a double lateral band signal with BPSK Receptor
suppressed carrier, where the high and low
lateral frequencies are separated from the carrier Figure 3 shows the blocks diagram of a BPSK
frequency for a value that is a half of the bit
rate. Therefore, the minimal required bandwidth
to allow the worst case of the BPSK output
signal is similar to the input bit reason. Figure 2
shows the output phase versus the time
relationship for a BPSK wave form.

The input signal can be +cos(ωt) or -cos(ωt).

The recovery circuit detects and regenerates a
carrier signal, as in frequency as in phase with Figure 3
As only the continuous part is needed, a low- on the binary values of the signal to be
pass (LPF) filter is used to separate the transmitted.
recovered binary data from the complex
demodulated signal [1].


BPSK Modulator

The simulation was done using Simulink and

the components of System Generator. The
following tools were necessary for the
simulation and implementation:

Simulink Blockset Figures 4: BPSK Modulator.

- Pulse Generator: it simulates a train of pulses. This Mcode block makes a call to a .m file
- Scope: oscilloscope used to visualize the which contains the programming of the
results. multiplexer in the following way:
- Sine Wave: it generates sine functions.
function sal = BPSKmultiplex
System Generator Blockset
if ent_codif==1;
- Mcode: it calls a Matlab .m file and executes it sal = porta;
inside the simulation [2]. sal = porta_despl;
- Gateway In: it makes an approach to the end
behaviour of a signal in hardware.
- Gateway Out: it returns an approach of the This code, allows us to obtain an output carrier
behaviour of a signal in hardware to the (porta) signal when the input is a level of high
simulation mode. voltage, a cosine in this case, and a dephased
- Mult: it carries out the multiplication of its cosine (porta_despl) signal of exit when the
two inputs. input is a level of low voltage. This high or low
- FIR: it simulates a FIR Filter, making a call to state is given by the signal that contains the
the Matlab FDATool. information.
- System Generator: It provides control of the
system and simulation parameters. It is used to The output signal of the multiplexer is the
invoke the generated code. modulated one and is ready to be thrown to the
- Resource Estimator: it presents the resources channel.
of the device used in the simulation of the
circuit. Figure 5 shows the signal containing the
- FDATool: Filter Design and Analysis tool. information upper part, and the modulated
signal bottom part.
System Generator

It is a software tool that allows to create and to

verify hardware designs for Xilinx FPGAS, it
works together with Simulink and Matlab. It
also allows the inclusion of DSP tools DSP to
design with FPGAs, automatic generation of
HDL code starting from a Simulink model and
allows the user to create its own libraries.

The first phase is the realization of the
modulator according to the scheme showed in
the figure 4.

The coded signal is entered in the (Mcode) Figure 5: Information signal-Modulated

block that works as multiplexer between the two signal.
carrier signals (cos(ωt) and -cos(ωt)) depending
BPSK Demodulator

The demodulation is performed according to the

scheme shown below.

Figure 6: BPSK Demodulator.

To demodulate the signal coming from the

channel, a (Mult) block that multiplies the
signal for the recovered carrier is used.

The pass-low filter FIR separates the continuous

signal of + ½ amplitude recovered from the
demodulated complex signal and allows to
select the zero frequency signal (+1/2 or -1/2).

This filter is obtained making a call to the

Figure 7: Modulation-Demodulation process.
Matlab FDATool, that is an interface that allows
Results obtained by the software.
designing a pass-low filter.
- The first figure represents the coded signal
Since at the output of the filter there are signals
containing the information.
with ½ amplitude and with ruffled border in
- Second figure represents the modulated signal
each pulse, a comparison block that will provide
that is sent to the channel.
levels of voltage of ones and zeros, and will
- Third figure shows the modulated signal with
avoid the curly of such pulses will be placed.
noise (cuanto de ruido?).
The code of the .m file comparison is presented
- Fourth figure represents the recovered signal at
the output of the pass-low filter.
function sal = BPSKcompa (ent)
- Finally the fifth figure represents the signal at
the output of the comparison, and it is the
If ent > 0 containing recovered information signal. One
sal = 1; can observe that this signal has some delay due
else to the prosecution of the computer
sal = 0;

This code, allows us to obtain at the output a Implementation of the modulator and
voltage level 1, when the input (ent) is higher demodulator in the Xilinx FPGA Spartan3
than certain reference voltage in this case 0V development board.
and a level voltage 1 when the input (ent) is
lower than such reference voltage. To implement the modulators in the Spartan3
development board it is necessary to know basic
It should also be mentioned that for the concepts on how is its operation and internal
transmission channel simulation a white structure:
gaussian noise block generator will be placed.
Field-Programmable Gate Array (FPGA)
In Figure 7 it is presented the simulated
demodulation process. An FPGA consists on arrangements of several
programmable blocks (logical blocks) which are
interconnected between themselves with
input/output cells by means of vertical and
horizontal connection channels [3].
Program Tools for the Implementation
An FPGA presents the following characteristics:
For the implementation of the OOK, FSK and
BPSK modulators, already simulated, a tool
offered by Xilinx, denominated JTAG Co-Sim
will be used; this block allows the co-simulation
of the design elaborated in the Spartan-3
development board.

Figures 8: Basic architecture of a FPGA.

• Mean consumption of power, although there

are families specialized in lower Figura 10: Block JTAG Cosimulation
• Intermediate speed. By double-clicking in this block, one can select
• High reliability. the most convenient simulation options. Which
• Very low development time. in this case were : poner aca que opciones
• Simple methodology. usaron.
• Simple equipment.
• They increase the confidentiality of the card Once added to the design, we should verify that
[4] the development board is correctly connected to
the computer. Then run the simulation.
Implementation in the Spartan-3
The FPGAs Xilinx Spartan™ are ideal for the development board
low cost and high volume applications and are
designed as substitutions for arrangements of The complete design is presented in the Figure
fixed logic gates and for standard products of 11 [6].
specific application (ASSP), like chips sets for
bus interface [5].

Figura 11: Block diagram of the Modulation-Demodulation


The result of the simulation is compared with

the results given by the actual implementation.
Figura 9: The Sapartan-3 This allows us to verify how close the
simulation was to the real implementation. The
Figure 9 shows the development board that will Figure 12 shows the results of the implemented
be used in the implementation of simulations. system.
The Spartan devices are characterized to have a
flexible and regular architecture composed by a
Configurable Logic Blocks (CLBs)
arrangement, surrounded by programmable
Input/Output Blocks (IOBs).

- Simulink tools offer a simplified environment

for the simulation of communication systems in

- The tools also simplied the process of passing

from simulation to implementation, without the
necessity of being an specialized hardware

- One can observe that the use of the Mcode tool

of System Generator, doesn't offer such
advantages as minimizing the use of resources
of the device and the design simplicity.

- Since the results obtained in hardware are

dependent of the design in software, it is much
simpler to carry out changes in these results by
means of the software, even after having
finished the design and its implementation. This
fact is considered one of the most important in
the development of this type of designs.



Couch, Quinta Edición.
Figura 12: Modulation-Demodulation process. Results
given by the developement board. [2]
One can observe that the results obtained in the n/app_docs/user_guide_Chapter_7_Section_3.ht
development board are practically the same that m
those obtained in the previous simulation.
In a similar way to the modulation block FPGA. ANÁLISIS Y EJEMPLOS DE
simulation, other blocks can be simulated. DISEÑO, Bozich Eduardo Carlos
As incentive for readers to know more about
these tools, some rules are given for the [4] DISPOSITIVOS LÓGICOS
realization and simulation of the FSK and OOK PROGRAMABLES, CAPII, Torres Valle
modulations. These rules will simply their Francisco
Firstly it is necessary to consider that in the FSK [5]
modulation it is the frequency what varies, http://www.xilinx.com/products/silicon_solutio
instead of the signal phase. This could be done ns/fpgas/spartan_series/spartan3_fpgas/index.ht
using a block that doesn't contain a dephased m
carrier but a carrier of different frequency. In
the same way in the OOK modulation one can [6] Workshop Xilinx University Program,
implement keeping in mind that for the change ISTEC, Pontificia Universidad Javeriana de Cali
of binary value of the coded signal it is used a Colombia (PUJ), University of New México,
carrier signal for the 1 value and a zero signal RedDSP – PUJ-UTPL, Ing. Ferney Amaya, Ing.
when the carrier is 0. This part is eased using Alonzo Vera.
Matlab programming and making a call through
a Mcode block.