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A B C D E

1 1

Compal Confidential
2 2

HBL51 Schematics Document


Intel Yonah Processor with 945GM/945PM + DDRII + ICH7M

3
2005-11-03 3

REV: 0.2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 1 of 47
A B C D E
A B C D E

Compal Confidential
Thermal Sensor Clock Generator
Model Name : HBL50 Fan Control
page 47
Yonah
F75383M ICS9LPRS325
page 4 page 14
File Name : LA-2921 uPGA-478 Package
page 4,5
1 1
PSB
H_A#(3..31) 533/667MHz H_D#(0..63)
DVI-D Conn. LCD Conn. CRT & TV-out
page 17 page 15 page 16

DVI LVDS Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2


Intel 945PM/GM Dual Channel BANK 0, 1, 2, 3 page 12,13
CH7307C SDVO
page 17 1.8V DDRII 400/533
uFCBGA-1466
page 6,7,8,9,10,11

DMI New Card LAN(GbE) MINI CARD x2 USB conn x4 Bluetooth


BCM5789
Socket page 29 page 26 page 28 page 29 Conn page 34
PCI Express USB port 3, 7 USB port 0, 2 USB port5
PCI BUS USB port 1
2
3.3V 33 MHz Intel ICH7-M 3.3V 48MHz 2

IDSEL:AD16 IDSEL:AD18 IDSEL:AD17 IDSEL:AD20 3.3V 24.576MHz/48Mhz HD Audio


(PIRQE#, (PIRQG/H#, (PIRQF#, (PIRQA#, BGA-652
GNT#2, GNT#3, GNT#3, GNT#2, 3.3V ATA-100
REQ#2) REQ#3) REQ#3) REQ#2) IDE
S-ATA
page 18,19,20,21
IEEE 1394 Mini PCI LAN (10/100) CardBus
VT6311S socket BCM4401E ENE CB714 CDROM MDC 1.5 HDA Codec
page 30 (WLAN) page 26 page 24 port 0 port 0 Conn. Conn ALC883
page 23 page 42 page 36
(TV-Tuner)
page 28

1394 Conn. RJ45 6 in 1 S-ATA HDD SATA-to-IDE HDD


Slot 0 socket SPIF3811-HV096
page 30 page 27
page 25 page 25
Conn.page 22 page 22
Conn.
page 22
Audio AMP Subwoofer
LPC BUS page 37 page 37
3 3

RTC CKT. Super I/O TPM1.2 Phone Jack x3


page 35
ENE KB910Q page 37
SMsC LPC47N207 SLB9635 TT 1.2
page 32 page 31 page 31

Power On/Off CKT. Switch/B Conn.


USB port4, 6
page 35
page 34
Touch Pad Int.KBD
page 35 page 33 FIR
TFDU6102-TR3
page 31
DC/DC Interface CKT. LCM Conn. EC I/O Buffer BIOS
page 34
page 40 page 33 page 33

Power Circuit DC/DC MEDIA/B Conn.


page 34
page 40,41,42,43 CIR
44,45,46,47 page 34
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 2 of 47
A B C D E
A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+3VALW 3.3V always on power rail ON ON ON* Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+5VALW 5V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+VSB VSB always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+RTCVCC RTC power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
2 2

BOARD ID Table BTO Option Table


Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1 UMA's DVI 7307@
CardBus(SD) AD20 2 PIRQA/PIRQB
1 LAN(10/100) 4401@
13 94 AD16 0 PIRQE
2 LAN(GIGA) 5789@
LAN(10/100) AD17 3 PIRQF
3 MINI CARD1 MINI1@
Mini-PCI(WLAN/TV-Tuner) AD18 1 PIRQG/PORQH
4 MINI CARD2 MINI2@
5 SATA-to-IDE 8040@
6 PATA PATA@
7 GRAPEVINE GRA@
MEDIA/B MEDIA@
SKU ID Table CIR CIR@
EC SM Bus1 address EC SM Bus2 address FIR FIR@
3
Device Address Device Address
SKU ID SKU GENEVA GEN@ 3

Smart Battery 0001 011X b Fintek F75383M 1001 100X b


0 LCM LCM@
EEPROM(24C16/02) 1010 000X b
1 GM TVOUT TVOUT@
GMT G781-1 1001 101X b
2 1394 6311S@
3 CARDREADER 4IN1@
4 Sub-woofer SUB@
5 5789&5787 8789@
6 4401&5789 0189@
ICH7M SM Bus address 7
Device Address

Clock Generator 1101 001Xb


(ICS9LPRS325AKLFT_MLF72)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 3 of 47
A B C D E
5 4 3 2 1

JP18A H_D#[0..63]
H_D#[0..63] (6)
H_A#[3..31] H_A#3 J4 E22 H_D#0
(6) H_A#[3..31]
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 +3VS
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3 C624
H_A#7 A6# D3# H_D#4 0.1U_0402_16V4Z
M1 A7# D4# F23
D H_A#8 H_D#5 D
N2 A8# D5# G25 1 2
H_A#9 J1 E25 H_D#6
H_A#10 A9# D6# H_D#7
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8
H_A#12 A11# D8# H_D#9
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10 1 U37
H_A#14 A13# D10# H_D#11 C625
P4 A14# D11# J23 1 VDD SCLK 8 EC_SMB_CK2 (32)
H_A#15 P1 H26 H_D#12
H_A#16 A15# D12# H_D#13 2200P_0402_50V7K THERMDA
R1 A16# D13# F26 2 D+ SDATA 7 EC_SMB_DA2 (32)
H_A#17 H_D#14 2
Y2 A17# D14# K22
H_A#18 U5 H25 H_D#15 THERMDC 3 6
H_A#19 A18# D15# H_D#16 D- ALERT#
R3 A19# D16# N22
H_A#20 W6 K25 H_D#17 4 5
H_A#21 A20# D17# H_D#18 THERM# GND
U4 A21# D18# P26
H_A#22 Y5 R23 H_D#19
H_A#23 A22# D19# H_D#20 ADM1032ARMZ-2REEL_MSOP8
U2 A23# D20# L25
H_A#24 R4 L22 H_D#21
H_A#25 A24# D21# H_D#22 F75383M_MSOP8
T5 A25# ADDR GROUP DATA GROUP D22# L23
H_A#26 T3 M23 H_D#23
H_A#27 A26# D23# H_D#24
W3 A27# D24# P25
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28
Y1 A31# D28# R24
L26 H_D#29
H_REQ#[0..4] H_REQ#0 D29# H_D#30
(6) H_REQ#[0..4] K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31
H_REQ#2 REQ1# D31# H_D#32
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33
H_REQ#4 REQ3# D33# H_D#34 +1.05VS
L5 REQ4# D34# V24
V26 H_D#35
D35# H_D#36
(6) H_ADSTB#0 L2 ADSTB0# D36# W25
C H_D#37 C
(6) H_ADSTB#1 V4 ADSTB1# D37# U23
U25 H_D#38
D38# H_D#39 ITP_TDI R15 56_0402_5%
D39# U22 2 1
AB25 H_D#40
D40# H_D#41 ITP_TDO R17 56_0402_5%
D41# W22 2 1
Y23 H_D#42
D42# H_D#43 ITP_TMS R16 56_0402_5%
(14) CLK_CPU_BCLK A22 BCLK0 D43# AA26 2 1
A21 HOST CLK Y26 H_D#44
(14) CLK_CPU_BCLK# BCLK1 D44#
Y22 H_D#45 H_PROCHOT# R500 2 1 75_0402_5%
D45# H_D#46
D46# AC26
AA24 H_D#47 ITP_BPM#5 R18 2 1 56_0402_5%
D47# H_D#48
(6) H_ADS# H1 ADS# D48# AC22
E2 AC23 H_D#49 H_IERR# R501 2 1 56_0402_5%
(6) H_BNR# BNR# D49#
G5 AB22 H_D#50
(6) H_BPRI# BPRI# D50# H_D#51
(6) H_BR0# F1 BR0# D51# AA21
H5 AB21 H_D#52
(6) H_DEFER# DEFER# D52# H_D#53
(6) H_DRDY# F21 DRDY# D53# AC25
G6 AD20 H_D#54
(6) H_HIT# HIT# D54#
E4 CONTROL AE22 H_D#55
(6) H_HITM# HITM# D55#
H_IERR# D20 AF23 H_D#56
IERR# D56# H_D#57
(6) H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
(6) H_RESET# RESET# D58# H_D#59
D59# AD21
AE25 H_D#60
H_RS#[0..2] H_RS#0 D60# H_D#61
(6) H_RS#[0..2] F3 RS0# D61# AF25
H_RS#1 F4 AF22 H_D#62
H_RS#2 RS1# D62# H_D#63 ITP_TRST# R19 56_0402_5%
G3 RS2# D63# AF26 2 1
(6) H_TRDY# G2 TRDY# ITP_TCK R20 2 1 56_0402_5%
DINV0# J26 H_DINV#0 (6)
M26 TEST1 R513 2 1 @ 1K_0402_5%
DINV1# H_DINV#1 (6)
PAD ITP_BPM#0 AD4 V23
B T5 BPM0# DINV2# H_DINV#2 (6) B
PAD ITP_BPM#1 AD3 AC20 TEST2 R512 2 1 51_0402_5%
T3 BPM1# DINV3# H_DINV#3 (6)
PAD ITP_BPM#2 AD1
T1 BPM2#
PAD ITP_BPM#3 AC4
T4 BPM3#
DSTBN0# H23 H_DSTBN#0 (6)
ITP_DBRRESET# C20 M24
(20) ITP_DBRESET# DBR# DSTBN1# H_DSTBN#1 (6)
(6) H_DBSY# E1 DBSY# DSTBN2# W24 H_DSTBN#2 (6)
(19) H_DPSLP# B5 DPSLP# DSTBN3# AD23 H_DSTBN#3 (6)
(19,47) H_DPRSTP# E5 DPRSTP# DSTBP0# G22 H_DSTBP#0 (6)
(6) H_DPWR# D24 DPWR# DSTBP1# N25 H_DSTBP#1 (6)
PAD ITP_BPM#4 AC2 MISC Y25
T2 PRDY# DSTBP2# H_DSTBP#2 (6)
ITP_BPM#5 AC1 AE24
PREQ# DSTBP3# H_DSTBP#3 (6)
H_PROCHOT# D21
PROCHOT#
H_PW RGOOD D6
(19) H_PWRGOOD PWRGOOD
H_CPUSLP# D7
(6) H_CPUSLP# SLP#
ITP_TCK AC5
ITP_TDI TCK
AA6 TDI A20M# A6 H_A20M# (19)
ITP_TDO AB3 A5
TDO FERR# H_FERR# (19)
TEST1 C26 C4
TEST1 IGNNE# H_IGNNE# (19)
TEST2 D25 B3
TEST2 INIT# H_INIT# (19)
ITP_TMS AB5 C6
TMS LINT0 H_INTR (19)
ITP_TRST# AB6 B4
TRST# LINT1 H_NMI (19)
LEGACY CPU
THERMAL
THERMDA A24 D5
THERMDC THERMDA DIODE STPCLK# H_STPCLK# (19)
A25 THERMDC SMI# A3 H_SMI# (19)
(6,19) H_THERMTRIP# C7 THERMTRIP#

FOX_PZ47903-2741-42_YONAH

A A

Layout Note:
THERMDA & THERMDC Trace / Space = 10 / 10 mil
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 4 of 47
5 4 3 2 1
5 4 3 2 1

Layout Note:
Route VCCSENSE and VSSSENSE traces at 27.4Ohms
with 50 mil spacing.
Place PU and PD wihin 1 inch of CPU.

+CPU_CORE
+CPU_CORE JP18B +CPU_CORE JP18C
(47) VCCSENSE
R499 1 100_0402_1% VCCSENSE
3 x 330uF(9mOhm/3)
2 AF7 VCCSENSE VSS AB26 AE18 VCC VSS K1
R498 1 2 100_0402_1% VSSSENSE AE7 AA25 1 1 1 AE17 J2
D VSSSENSE VSS @ VCC VSS D
(47) VSSSENSE VSS AD25 AB15 VCC VSS M2
+ C614 + C609 + C621
20mils VSS AE26 AA15 VCC VSS N1
+1.5VS B26 VCCA VSS AB23 AD15 VCC VSS T1
AC24 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 AC15 R2
VSS 2 2 2 VCC VSS
1 1 +1.05VS K6 VCCP VSS AF24 2005/11/02 AF15 VCC VSS V2
C628 C626 J6 AE23 AE15 W1
VCCP VSS VCC VSS
M6 VCCP VSS AA22 South Side Secondary AB14 VCC VSS A26
10U_0805_10V4Z 0.01U_0402_16V7K N6 AD22 AA13 D26
2 2
T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
K21 AB19 +CPU_CORE AF14 B24
VCCP VSS VCC VSS
J21 VCCP VSS AA19 3 x 330uF(9mOhm/3) AE13 VCC VSS A23
Layout Note: M21 VCCP VSS AD19 AB12 VCC VSS D23
N21 AC19 2005/11/02 AA12 E24
Place C14 near Pin B26 T21
VCCP
VCCP
VSS
VSS AF19
1
+ C620
2005/11/02
+ C608
1
+ C619
1
AD12
VCC
VCC
YONAH VSS
VSS B21
R21 VCCP VSS AE19 AC12 VCC VSS C22
V21 AB16 @ AF12 F22
VCCP VSS VCC VSS

POWER, GROUNG, RESERVED SIGNALS AND NC


W21 AA16 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 AE12 E21
VCCP VSS 2 2 2 VCC VSS
V6 VCCP VSS AD16 AB10 VCC VSS B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VSS AF16 North Side Secondary AA10 VCC VSS D19
VSS AE16 AA9 VCC VSS C19
(47) PSI# AE6 PSI# VSS AB13 AD10 VCC VSS F19
AA14 +CPU_CORE AD9 E19
VSS VCC VSS
(47) CPU_VID0 AD6 VID0 VSS AD13 AC10 VCC VSS B16
+1.05VS (47) CPU_VID1 AF5 AC14 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M AC9 A16
VID1 VSS VCC VSS
(47) CPU_VID2 AE5 VID2 VSS AF13 1 1 1 1 1 1 1 1 AF10 VCC VSS D16
(47) CPU_VID3 AF4 AE14 C31 C33 C35 C32 C30 C28 C26 C24 AF9 C16
VID3 VSS VCC VSS
1

(47) CPU_VID4 AE3 VID4 VSS AB11 AE10 VCC POWER, GROUND VSS F16
R511 (47) CPU_VID5 AF2 AA11 AE9 E16
1K_0402_1% VID5 VSS 2 2 2 2 2 2 2 2 VCC VSS
(47) CPU_VID6 AE2 VID6 VSS AD11 AB7 VCC VSS B13
AC11 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M AA7 A14
C VSS (Place these capacitors on South side,Secondary Layer) VCC VSS C
AF11 AD7 D13
2

GTL_REF0 VSS VCC VSS


1 2 AD26 GTLREF VSS AE11 AC7 VCC VSS C14
R510 2K_0402_1% AB8 +CPU_CORE B20 F13
VSS VCC VSS
(14) CPU_BSEL0 B22 BSEL0 VSS AA8 A20 VCC VSS E14
(14) CPU_BSEL1 B23 AD8 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M F20 B11
BSEL1 VSS VCC VSS
(14) CPU_BSEL2 C21 BSEL2 VSS AC8 1 1 1 1 1 1 E20 VCC VSS A11
AF8 C623 C618 C616 C613 C22 C20 B18 D11
COMP0 VSS VCC VSS
R26 COMP0 VSS AE8 B17 VCC VSS C11
COMP1 U26 AA5 A18 F11
COMP2 COMP1 VSS 2 2 2 2 2 2 VCC VSS
U1 COMP2 VSS AD5 A17 VCC VSS E11
COMP3 V1 AC6 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M D18 B8
COMP3 VSS (Place these capacitors on South side,Secondary Layer) VCC VSS
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
E7 AC3 +CPU_CORE C17 C8
+CPU_CORE VCC VSS VCC VSS
AB20 VCC VSS AF3 F18 VCC VSS F8
AA20 AE4 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M F17 E8
VCC VSS VCC VSS
AF20 VCC VSS AB1 1 1 1 1 1 1 E18 VCC VSS G26
AE20 AA2 C611 C607 C29 C27 C25 C23 E17 K26
VCC VSS VCC VSS
AB18 AD2 B15 J25
BSEL2 BSEL1 BSEL0 BCLK AB17
VCC VSS
AE1 A15
VCC VSS
M25
VCC VSS 2 2 2 2 2 2 VCC VSS
AA18 VCC VSS B6 D15 VCC VSS N26
AA17 C5 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C15 T26
VCC VSS (Place these capacitors on North side,Secondary Layer) VCC VSS
0 0 1 133 AD18 VCC VSS F5 F15 VCC VSS R25
AD17 VCC VSS E6 E15 VCC VSS V25
AC18 H6 +CPU_CORE B14 W26
VCC VSS VCC VSS
0 1 1 166 AC17 VCC VSS J5
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 1 1 1 1 1 1 1 1 C13 VCC VSS K23
P6 C21 C19 C622 C617 C615 C612 C610 C606 F14 L24
VSS VCC VSS
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
2 2 2 2 2 2 2 2
F6 RSVD VSS U6 A12 VCC VSS T23
B 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M B
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 A4 (Place these capacitors on North side,Secondary Layer) C12 Y24
RSVD VSS VCC VSS
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 +CPU-CORE C,uF ESR, mohm ESL,nH B9 VCC VSS M22
AA1 K4 A10 L21
AA4
RSVD VSS
L3 Decoupling A9
VCC VSS
P21
RSVD VSS VCC VSS
AB2 RSVD VSS P3 SPCAP,Polymer 6X330uF 9m ohm/6 1.8nH/6 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 MLCC 0805 X5R 32X22uF 3m ohm/32 0.6nH/32 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
R515 1 2 27.4_0402_1% COMP0 T2 Y3 F10
RSVD VSS VCC
V3 RSVD VSS W4 F9 VCC
R514 1 2 54.9_0402_1% COMP1 B2 D1 E10
RSVD VSS VCC
C3 RSVD VSS C2 E9 VCC
R13 1 2 27.4_0402_1% COMP2 T22 F2 +1.05VS B7
RSVD VSS VCC
B25 RSVD VSS G1 A7 VCC
R14 1 2 54.9_0402_1% COMP3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z F7 VCC
1
1 1 1 1 1 1 1 1
FOX_PZ47903-2741-42_YONAH C13 + C34 C36 C38 C37 C16 C18 C17 C15 FOX_PZ47903-2741-42_YONAH
@ @
220U_D2_2VMR15
2 2 2 2 2 2 2 2 2
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
COMP1, COMP3 layout : Space 25mils (55Ohms)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 5 of 47
5 4 3 2 1
5 4 3 2 1

945GM(A-1)(QJ15)[ES2]: SA000005970
945GM(A-2)(QK44)[ES3]: SA000005980
945PM(A-2)(QK46)[ES3]: SA00000UV10

(4) H_D#[0..63] H_A#[3..31] (4) Description at page10


U40A U40B
H_D#0 F1 H9 H_A#3
H_D#1 HD0# HA3# H_A#4 DMI_ITX_MRX_N0 MCH_CLKSEL0
J1 HD1# HA4# C9 (20) DMI_ITX_MRX_N0 AE35 DMIRXN0 CFG0 K16 MCH_CLKSEL0 (14)
H_D#2 H1 E11 H_A#5 DMI_ITX_MRX_N1 AF39 K18 MCH_CLKSEL1
HD2# HA5# (20) DMI_ITX_MRX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 (14)
H_D#3 J6 G11 H_A#6 DMI_ITX_MRX_N2 AG35 J18 MCH_CLKSEL2
HD3# HA6# (20) DMI_ITX_MRX_N2 DMIRXN2 CFG2 MCH_CLKSEL2 (14)
H_D#4 H3 F11 H_A#7 DMI_ITX_MRX_N3 AH39 F18 CFG3 PAD
HD4# HA7# (20) DMI_ITX_MRX_N3 DMIRXN3 CFG3 T15
H_D#5 K2 G12 H_A#8 E15 CFG4 PAD
D HD5# HA8# CFG4 T8 D
H_D#6 G1 F9 H_A#9 F15 CFG5
HD6# HA9# CFG5 CFG5 (10)
H_D#7 G2 H11 H_A#10 DMI_ITX_MRX_P0 AC35 E18 CFG6 PAD
HD7# HA10# (20) DMI_ITX_MRX_P0 DMIRXP0 CFG6 T14
H_D#8 K9 J12 H_A#11 DMI_ITX_MRX_P1 AE39 D19 CFG7
HD8# HA11# (20) DMI_ITX_MRX_P1 DMIRXP1 CFG7 CFG7 (10)
H_D#9 K1 G14 H_A#12 DMI_ITX_MRX_P2 AF35 D16 CFG8 PAD
HD9# HA12# (20) DMI_ITX_MRX_P2 DMIRXP2 CFG8 T11

DMI
H_D#10 K7 D9 H_A#13 DMI_ITX_MRX_P3 AG39 G16 CFG9
HD10# HA13# (20) DMI_ITX_MRX_P3 DMIRXP3 CFG9 CFG9 (10)
H_D#11 J8 J14 H_A#14 E16 CFG10 PAD
HD11# HA14# CFG10 T12
H_D#12 H4 H13 H_A#15 D15 CFG11
HD12# HA15# CFG11 CFG11 (10)
H_D#13 J3 J15 H_A#16 DMI_MTX_IRX_N0 AE37 G15 CFG12
HD13# HA16# (20) DMI_MTX_IRX_N0 DMITXN0 CFG12 CFG12 (10)
H_D#14 K11 F14 H_A#17 DMI_MTX_IRX_N1 AF41 K15 CFG13
HD14# HA17# (20) DMI_MTX_IRX_N1 DMITXN1 CFG13 CFG13 (10)

CFG
H_D#15 G4 D12 H_A#18 DMI_MTX_IRX_N2 AG37 C15 CFG14 PAD
HD15# HA18# (20) DMI_MTX_IRX_N2 DMITXN2 CFG14 T7
H_D#16 T10 A11 H_A#19 DMI_MTX_IRX_N3 AH41 H16 CFG15 PAD
HD16# HA19# (20) DMI_MTX_IRX_N3 DMITXN3 CFG15 T13
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 (10)
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD
HD18# HA21# CFG17 T9
H_D#19 U7 A13 H_A#22 DMI_MTX_IRX_P0 AC37 J25 CFG18
HD19# HA22# (20) DMI_MTX_IRX_P0 DMITXP0 CFG18 CFG18 (10)
H_D#20 U9 E13 H_A#23 DMI_MTX_IRX_P1 AE41 K27 CFG19
HD20# HA23# (20) DMI_MTX_IRX_P1 DMITXP1 CFG19 CFG19 (10)
H_D#21 U11 G13 H_A#24 DMI_MTX_IRX_P2 AF37 J26 CFG20
HD21# HA24# (20) DMI_MTX_IRX_P2 DMITXP2 CFG20 CFG20 (10)
H_D#22 T11 F12 H_A#25 DMI_MTX_IRX_P3 AG41
HD22# HA25# (20) DMI_MTX_IRX_P3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27 CLK_MCH_3GPLL
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL (14)
H_D#25 T8 C12 H_A#28 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# (12) DDRA_CLK0 SM_CK0 G_CLKN CLK_MCH_3GPLL# (14)
H_D#26 T4 A14 H_A#29 AR1
HD26# HA29# (12) DDRA_CLK1 SM_CK1
H_D#27 W7 C14 H_A#30 AW7 A27 CLK_DREF_96M#

CLK
HD27# HA30# (13) DDRB_CLK0 SM_CK2 D_REF_CLKN CLK_DREF_96M# (14)
H_D#28 U5 D14 H_A#31 AW40 A26 CLK_DREF_96M
HD28# HA31# (13) DDRB_CLK1 SM_CK3 D_REF_CLKP CLK_DREF_96M (14)
H_D#29 T9
H_D#30 HD29# CLK_DREF_SSC#
W6 HD30# (12) DDRA_CLK0# AW35 SM_CK0# D_REF_SSCLKN C40 CLK_DREF_SSC# (14)
H_D#31 T5 AT1 D41 CLK_DREF_SSC
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] (4) (12)
(13)
DDRA_CLK1#
DDRB_CLK0# AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP CLK_DREF_SSC (14)
H_D#33 AA9 G8 H_REQ#1 AY40 H32 MCH_CLKREQ#
HD33# HREQ#1 (13) DDRB_CLK1# SM_CK3# CLK_REQ# MCH_CLKREQ# (14)
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3
W3 HD35# HREQ#3 F8 (12) DDRA_CKE0 AU20 SM_CKE0

DDR MUXING
H_D#36 Y3 A8 H_REQ#4 AT20
HD36# HREQ#4 (12) DDRA_CKE1 SM_CKE1
H_D#37 Y7 BA29 A3
C HD37# (13) DDRB_CKE0 SM_CKE2 NC0 C
H_D#38 W5 AY29 A39
HD38# (13) DDRB_CKE1 SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 (4) NC2
H_D#40 AB8 C13 H_ADSTB#1 AW13 A40
HD40# HADSTB#1 H_ADSTB#1 (4) (12) DDRA_SCS#0 SM_CS0# NC3
H_D#41 W2 AW12 AW1
HD41# (12) DDRA_SCS#1 SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# (14) (13) DDRB_SCS#0 SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK AW21 AY1
HD43# HCLKP CLK_MCH_BCLK (14) (13) DDRB_SCS#1 SM_CS3# NC6
H_D#44 AA2 BA1

NC
H_D#45 HD44# H_DSTBN#0 M_OCDOCMP0 NC7
AA6 HD45# HDSTBN#0 K4 H_DSTBN#0 (4) T17 PAD AL20 SM_OCDCOMP0 NC8 BA2
H_D#46 AA10 T7 H_DSTBN#1 PAD M_OCDOCMP1 AF10 BA3
HD46# HDSTBN#1 H_DSTBN#1 (4) T6 SM_OCDCOMP1 NC9
H_D#47 Y8 Y5 H_DSTBN#2 BA39
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 H_DSTBN#2 (4) NC10
AA1 HD48# HDSTBN#3 AC4 H_DSTBN#3 (4) (12) DDRA_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#49 AB4 K3 H_DSTBP#0 BA12 BA41
HD49# HDSTBP#0 H_DSTBP#0 (4) (12) DDRA_ODT1 SM_ODT1 NC12
H_D#50 AC9 T6 H_DSTBP#1 AY20 C1
HD50# HDSTBP#1 H_DSTBP#1 (4) +1.8V (13) DDRB_ODT0 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 AU21 AY41
HD51# HDSTBP#2 H_DSTBP#2 (4) (13) DDRB_ODT1 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 H_DSTBP#3 (4) R47 SMRCOMPN NC15
AB3 HD53# 1 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+1.05VS H_D#54 AC2 R46 1 2 80.6_0402_1% SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 (4) NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
H_D#57 HD56# HDINV#1 H_DINV#2 H_DINV#1 (4) SMVREF SM_VREF0
AC1 HD57# HDINV#2 U3 H_DINV#2 (4) AK41 SM_VREF1
H_D#58 AD7 AB10 H_DINV#3 T32
HD58# HDINV#3 H_DINV#3 (4) RESERVED1
2

2
54.9_0402_1%

54.9_0402_1%

H_D#59 AC6 R32


H_D#60 HD59# PM_BMBUSY# RESERVED2
AB5 HD60# (20) PM_BMBUSY# G28 PM_BMBUSY# RESERVED3 F3
R530

R532

H_D#61 AD10 B7 H_RESET# PM_EXTTS#0 F25 F7


HD61# HCPURST# H_RESET# (4) (12,13) PM_EXTTS#0 PM_EXTTS0# RESERVED4

RESERVED
PM
H_D#62 AD4 E8 H_ADS# PM_EXTTS#1 H26 AG11
HD62# HADS# H_ADS# (4) PM_EXTTS1# RESERVED5
H_D#63 AC8 E7 H_TRDY# (4,19) H_THERMTRIP# H_THERMTRIP# G6 AF11
H_TRDY# (4)
1

HD63# HTRDY# H_DPWR# GMCH_PWROK AH33 PM_THERMTRIP# RESERVED6


HDPWR# J9 H_DPWR# (4) PWROK RESERVED7 H7
H8 H_DRD Y# 1 2 PLTRST_R# AH34 J19
HDRDY# H_DRDY# (4) (18,20,23,26,31,32) PLT_RST# RSTIN# RESERVED8
J13 C3 H_DEFER# R128 100_0402_1% A41
HVREF0 HDEFER# H_DEFER# (4) RESERVED9
H_VREF K13 D4 H_HITM# (18) MCH_ICH_SYNC# K28 A34
HVREF1 HHITM# H_HITM# (4) ICH_SYNC# RESERVED10
H_XRCOMP E1 D3 H_HIT# D28
HXRCOMP HHIT# H_HIT# (4) RESERVED11
H_XSCOMP E2 B3 H_LOCK# D27
B HXSCOMP HLOCK# H_LOCK# (4) RESERVED12 B
H_YRCOMP Y1 C7 H_BR0# A35
HYRCOMP HBREQ0# H_BR0# (4) RESERVED13
H_YSCOMP U1 C6 H_BNR#
HYSCOMP HBNR# H_BNR# (4)
H_SWNG0 E4 F6 H_BPRI# CALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_BPRI# (4)
H_SWNG1 W1 A7 H_DBSY#
HYSWING HDBSY# H_DBSY# (4)
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# (4)
24.9_0402_1%

24.9_0402_1%

SMVREF trace
1

width and spacing


R531

R529

B4 H_RS#0
HRS0# H_RS#1
HRS1# E6 is 20/20.
D6 H_RS#2
HRS2# R127 @ 0_0402_5%
H_RS#[0..2] (4)
2

GMCH_PWROK 1 2 VGATE
+1.8V VGATE (14,20,47)
CALISTOGA_FCBGA1466~D
R130 0_0402_5%
1 2 SYS_PWROK
SYS_PWROK (20,35)

2
R577
100_0402_1%
Layout Note:

1
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / SMVREF
H_SWNG1 trace width and spacing is 10/20.
2
0.1U_0402_16V4Z

+3VS
1 R578 R111
+1.05VS +1.05VS 100_0402_1% 10K_0402_5%
C46

PM_EXTTS#0 1 2
+1.05VS
1

2 R100
1

1
221_0603_1%

221_0603_1%

10K_0402_5%
2

100_0402_1%

1 2 PM_EXTTS#1 1 2
(20,47) PM_DPRSLPVR
R528

R527

R121 0_0402_5% @
R60

A A
2

H_SWNG0 H_SWNG1
1

H_VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

2
100_0402_1%

100_0402_1%
0.1U_0402_16V4Z

1 1
1

200_0603_1%

1
R53

R44

C48

R526

C641
C66

2 2 Security Classification Compal Secret Data Compal Electronics, Inc.


1

2 2005/06/20 2006/06/20 Title


Issued Date Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 6 of 47
5 4 3 2 1
5 4 3 2 1

DDRB_SDQ[0..63]
(13) DDRB_SDQ[0..63]
DDRA_SDQ[0..63]
(12) DDRA_SDQ[0..63] DDRB_SMA[0..13]
(13) DDRB_SMA[0..13]
DDRA_SMA[0..13]
D
(12) DDRA_SMA[0..13] D

U40D U40E

AU12 AJ35 DDRA_SDQ0 AT24 AK39 DDRB_SDQ0


(12) DDRA_SBS0# SA_BS0 SA_DQ0 (13) DDRB_SBS0# SB_BS0 SB_DQ0
AV14 AJ34 DDRA_SDQ1 AV23 AJ37 DDRB_SDQ1
(12) DDRA_SBS1# SA_BS1 SA_DQ1 (13) DDRB_SBS1# SB_BS1 SB_DQ1
BA20 AM31 DDRA_SDQ2 AY28 AP39 DDRB_SDQ2
(12) DDRA_SBS2# SA_BS2 SA_DQ2 (13) DDRB_SBS2# SB_BS2 SB_DQ2
AM33 DDRA_SDQ3 AR41 DDRB_SDQ3
SA_DQ3 DDRA_SDQ4 SB_DQ3 DDRB_SDQ4
SA_DQ4 AJ36 SB_DQ4 AJ38
(12) DDRA_SDM[0..7] AK35 DDRA_SDQ5 (13) DDRB_SDM[0..7] AK38 DDRB_SDQ5
DDRA_SDM0 SA_DQ5 DDRA_SDQ6 DDRB_SDM0 SB_DQ5 DDRB_SDQ6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDRA_SDM1 AM35 AH31 DDRA_SDQ7 DDRB_SDM1 AR38 AP41 DDRB_SDQ7
DDRA_SDM2 SA_DM1 SA_DQ7 DDRA_SDQ8 DDRB_SDM2 SB_DM1 SB_DQ7 DDRB_SDQ8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDRA_SDM3 AN22 AP33 DDRA_SDQ9 DDRB_SDM3 BA31 AV41 DDRB_SDQ9
DDRA_SDM4 SA_DM3 SA_DQ9 DDRA_SDQ10 DDRB_SDM4 SB_DM3 SB_DQ9 DDRB_SDQ10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDRA_SDM5 AL9 AP31 DDRA_SDQ11 DDRB_SDM5 AH8 AV38 DDRB_SDQ11
DDRA_SDM6 SA_DM5 SA_DQ11 DDRA_SDQ12 DDRB_SDM6 SB_DM5 SB_DQ11 DDRB_SDQ12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDRA_SDM7 AH4 AM36 DDRA_SDQ13 DDRB_SDM7 AN4 AR40 DDRB_SDQ13
SA_DM7 SA_DQ13 DDRA_SDQ14 SB_DM7 SB_DQ13 DDRB_SDQ14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDRA_SDQ15 AY38 DDRB_SDQ15
SA_DQ15 DDRA_SDQ16 SB_DQ15 DDRB_SDQ16
SA_DQ16 AK26 SB_DQ16 BA38
AL27 DDRA_SDQ17 AV36 DDRB_SDQ17
DDRA_SDQS0 SA_DQ17 DDRA_SDQ18 DDRB_SDQS0 SB_DQ17 DDRB_SDQ18
(12) DDRA_SDQS0 AK33 SA_DQS0 SA_DQ18 AM26 (13) DDRB_SDQS0 AM39 SB_DQS0 SB_DQ18 AR36
DDRA_SDQS1 AT33 AN24 DDRA_SDQ19 DDRB_SDQS1 AT39 AP36 DDRB_SDQ19
(12) DDRA_SDQS1 DDRA_SDQS2 SA_DQS1 SA_DQ19 DDRA_SDQ20 (13) DDRB_SDQS1 DDRB_SDQS2 SB_DQS1 SB_DQ19 DDRB_SDQ20
AN28 AK28 AU35 BA36

DDR SYS MEMORY A

DDR SYS MEMORY B


(12) DDRA_SDQS2 DDRA_SDQS3 SA_DQS2 SA_DQ20 DDRA_SDQ21 (13) DDRB_SDQS2 DDRB_SDQS3 SB_DQS2 SB_DQ20 DDRB_SDQ21
(12) DDRA_SDQS3 AM22 SA_DQS3 SA_DQ21 AL28 (13) DDRB_SDQS3 AR29 SB_DQS3 SB_DQ21 AU36
C DDRA_SDQS4 DDRA_SDQ22 DDRB_SDQS4 DDRB_SDQ22 C
(12) DDRA_SDQS4 AN12 SA_DQS4 SA_DQ22 AM24 (13) DDRB_SDQS4 AR16 SB_DQS4 SB_DQ22 AP35
DDRA_SDQS5 AN8 AP26 DDRA_SDQ23 DDRB_SDQS5 AR10 AP34 DDRB_SDQ23
(12) DDRA_SDQS5 DDRA_SDQS6 SA_DQS5 SA_DQ23 DDRA_SDQ24 (13) DDRB_SDQS5 DDRB_SDQS6 SB_DQS5 SB_DQ23 DDRB_SDQ24
(12) DDRA_SDQS6 AP3 SA_DQS6 SA_DQ24 AP23 (13) DDRB_SDQS6 AR7 SB_DQS6 SB_DQ24 AY33
DDRA_SDQS7 AG5 AL22 DDRA_SDQ25 DDRB_SDQS7 AN5 BA33 DDRB_SDQ25
(12) DDRA_SDQS7 SA_DQS7 SA_DQ25 DDRA_SDQ26 (13) DDRB_SDQS7 SB_DQS7 SB_DQ25 DDRB_SDQ26
SA_DQ26 AP21 SB_DQ26 AT31
AN20 DDRA_SDQ27 AU29 DDRB_SDQ27
DDRA_SDQS0# SA_DQ27 DDRA_SDQ28 DDRB_SDQS0# SB_DQ27 DDRB_SDQ28
(12) DDRA_SDQS0# AK32 SA_DQS0# SA_DQ28 AL23 (13) DDRB_SDQS0# AM40 SB_DQS0# SB_DQ28 AU31
DDRA_SDQS1# AU33 AP24 DDRA_SDQ29 DDRB_SDQS1# AU39 AW31 DDRB_SDQ29
(12) DDRA_SDQS1# DDRA_SDQS2# SA_DQS1# SA_DQ29 DDRA_SDQ30 (13) DDRB_SDQS1# DDRB_SDQS2# SB_DQS1# SB_DQ29 DDRB_SDQ30
(12) DDRA_SDQS2# AN27 SA_DQS2# SA_DQ30 AP20 (13) DDRB_SDQS2# AT35 SB_DQS2# SB_DQ30 AV29
DDRA_SDQS3# AM21 AT21 DDRA_SDQ31 DDRB_SDQS3# AP29 AW29 DDRB_SDQ31
(12) DDRA_SDQS3# DDRA_SDQS4# SA_DQS3# SA_DQ31 DDRA_SDQ32 (13) DDRB_SDQS3# DDRB_SDQS4# SB_DQS3# SB_DQ31 DDRB_SDQ32
(12) DDRA_SDQS4# AM12 SA_DQS4# SA_DQ32 AR12 (13) DDRB_SDQS4# AP16 SB_DQS4# SB_DQ32 AM19
DDRA_SDQS5# AL8 AR14 DDRA_SDQ33 DDRB_SDQS5# AT10 AL19 DDRB_SDQ33
(12) DDRA_SDQS5# DDRA_SDQS6# SA_DQS5# SA_DQ33 DDRA_SDQ34 (13) DDRB_SDQS5# DDRB_SDQS6# SB_DQS5# SB_DQ33 DDRB_SDQ34
(12) DDRA_SDQS6# AN3 SA_DQS6# SA_DQ34 AP13 (13) DDRB_SDQS6# AT7 SB_DQS6# SB_DQ34 AP14
DDRA_SDQS7# AH5 AP12 DDRA_SDQ35 DDRB_SDQS7# AP5 AN14 DDRB_SDQ35
(12) DDRA_SDQS7# SA_DQS7# SA_DQ35 DDRA_SDQ36 (13) DDRB_SDQS7# SB_DQS7# SB_DQ35 DDRB_SDQ36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDRA_SDQ37 AM16 DDRB_SDQ37
SA_DQ37 DDRA_SDQ38 SB_DQ37 DDRB_SDQ38
SA_DQ38 AL14 SB_DQ38 AP15
DDRA_SMA0 AY16 AL12 DDRA_SDQ39 DDRB_SMA0 AY23 AL15 DDRB_SDQ39
DDRA_SMA1 SA_MA0 SA_DQ39 DDRA_SDQ40 DDRB_SMA1 SB_MA0 SB_DQ39 DDRB_SDQ40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDRA_SMA2 AW16 AN7 DDRA_SDQ41 DDRB_SMA2 AY24 AH10 DDRB_SDQ41
DDRA_SMA3 SA_MA2 SA_DQ41 DDRA_SDQ42 DDRB_SMA3 SB_MA2 SB_DQ41 DDRB_SDQ42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDRA_SMA4 BA17 AK7 DDRA_SDQ43 DDRB_SMA4 AT27 AN10 DDRB_SDQ43
DDRA_SMA5 SA_MA4 SA_DQ43 DDRA_SDQ44 DDRB_SMA5 SB_MA4 SB_DQ43 DDRB_SDQ44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDRA_SMA6 AV17 AN9 DDRA_SDQ45 DDRB_SMA6 AU27 AH11 DDRB_SDQ45
DDRA_SMA7 SA_MA6 SA_DQ45 DDRA_SDQ46 DDRB_SMA7 SB_MA6 SB_DQ45 DDRB_SDQ46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDRA_SMA8 AW17 AL5 DDRA_SDQ47 DDRB_SMA8 AV27 AJ8 DDRB_SDQ47
DDRA_SMA9 SA_MA8 SA_DQ47 DDRA_SDQ48 DDRB_SMA9 SB_MA8 SB_DQ47 DDRB_SDQ48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDRA_SMA10 AU13 AW2 DDRA_SDQ49 DDRB_SMA10 AV24 AW10 DDRB_SDQ49
DDRA_SMA11 SA_MA10 SA_DQ49 DDRA_SDQ50 DDRB_SMA11 SB_MA10 SB_DQ49 DDRB_SDQ50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDRA_SMA12 AV20 AN2 DDRA_SDQ51 DDRB_SMA12 AY27 AW4 DDRB_SDQ51
DDRA_SMA13 SA_MA12 SA_DQ51 DDRA_SDQ52 DDRB_SMA13 SB_MA12 SB_DQ51 DDRB_SDQ52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDRA_SDQ53 AY9 DDRB_SDQ53
B SA_DQ53 DDRA_SDQ54 SB_DQ53 DDRB_SDQ54 B
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDRA_SDQ55 AY5 DDRB_SDQ55
SA_DQ55 DDRA_SDQ56 SB_DQ55 DDRB_SDQ56
(12) DDRA_SCAS# AY13 SA_CAS# SA_DQ56 AG7 (13) DDRB_SCAS# AR24 SB_CAS# SB_DQ56 AV4
AW14 AF9 DDRA_SDQ57 AU23 AR5 DDRB_SDQ57
(12) DDRA_SRAS# SA_RAS# SA_DQ57 (13) DDRB_SRAS# SB_RAS# SB_DQ57
AY14 AG4 DDRA_SDQ58 AR27 AK4 DDRB_SDQ58
(12) DDRA_SWE# SA_WE# SA_DQ58 (13) DDRB_SWE# SB_WE# SB_DQ58
PAD SA_RCVENIN# AK23 AF6 DDRA_SDQ59 PAD SB_RCVENIN# AK16 AK3 DDRB_SDQ59
T18 SA_RCVENIN# SA_DQ59 T10 SB_RCVENIN# SB_DQ59
PAD SA_RCVENOUT# AK24 AG9 DDRA_SDQ60 PAD SB_RCVENOUT# AK18 AT4 DDRB_SDQ60
T19 SA_RCVENOUT# SA_DQ60 T16 SB_RCVENOUT# SB_DQ60
AH6 DDRA_SDQ61 AK5 DDRB_SDQ61
SA_DQ61 DDRA_SDQ62 SB_DQ61 DDRB_SDQ62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDRA_SDQ63 AJ3 DDRB_SDQ63
SA_DQ63 SB_DQ63
check layout check layout
CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 7 of 47
5 4 3 2 1
5 4 3 2 1

D D

U40C
H27 D40 PEG_COMP 1 2 +1.5VS_PCIE
(17) SDVO_SDAT SDVOCTRL_DATA EXP_COMPI
H28 D38 10mils R138 24.9_0402_1%
(17) SDVO_SCLK SDVOCTRL_CLK EXP_COMPO
F34 PCIE_GTX_C_MRX_N0
TXOUT0+ EXP_RXN0 PCIE_GTX_C_MRX_N1 T32 PAD
(15) TXOUT0+ B37 LA_DATA0 EXP_RXN1 G38
TXOUT1+ B34 H34 PCIE_GTX_C_MRX_N2
(15) TXOUT1+ LA_DATA1 EXP_RXN2
TXOUT2+ A36 J38 PCIE_GTX_C_MRX_N3 T33 PAD
(15) TXOUT2+ LA_DATA2 EXP_RXN3
L34 PCIE_GTX_C_MRX_N4 T34 PAD
TXOUT0- EXP_RXN4 PCIE_GTX_C_MRX_N5 T35 PAD
(15) TXOUT0- C37 LA_DATA#0 EXP_RXN5 M38
TXOUT1- B35 N34 PCIE_GTX_C_MRX_N6 T36 PAD
(15) TXOUT1- LA_DATA#1 EXP_RXN6
TXOUT2- A37 P38 PCIE_GTX_C_MRX_N7 T37 PAD
(15) TXOUT2- LA_DATA#2 EXP_RXN7
R34 PCIE_GTX_C_MRX_N8 T38 PAD
TZOUT0+ EXP_RXN8 PCIE_GTX_C_MRX_N9 T39 PAD
(15) TZOUT0+ F30 LB_DATA0 EXP_RXN9 T38
TZOUT1+ PCIE_GTX_C_MRX_N10 T40 PAD

LVDS
(15) TZOUT1+ D29 LB_DATA1 EXP_RXN10 V34
TZOUT2+ F28 W38 PCIE_GTX_C_MRX_N11 T41 PAD
(15) TZOUT2+ LB_DATA2 EXP_RXN11
Y34 PCIE_GTX_C_MRX_N12 T42 PAD
TZOUT0- EXP_RXN12 PCIE_GTX_C_MRX_N13 T43 PAD
(15) TZOUT0- G30 LB_DATA#0 EXP_RXN13 AA38
TZOUT1- D30 AB34 PCIE_GTX_C_MRX_N14 T44 PAD
(15) TZOUT1- LB_DATA#1 EXP_RXN14
TZOUT2- F29 AC38 PCIE_GTX_C_MRX_N15 T45 PAD
(15) TZOUT2- LB_DATA#2 EXP_RXN15 T46 PAD
TXCLK+ A32 D34 PCIE_GTX_C_MRX_P0
(15) TXCLK+ LA_CLK EXP_RXP0
TXCLK- A33 F38 PCIE_GTX_C_MRX_P1 T47 PAD
(15) TXCLK- LA_CLK# EXP_RXP1
TZCLK+ E26 G34 PCIE_GTX_C_MRX_P2
(15) TZCLK+ LB_CLK EXP_RXP2
TZCLK- E27 H38 PCIE_GTX_C_MRX_P3 T48 PAD
(15) TZCLK- LB_CLK# EXP_RXP3
J34 PCIE_GTX_C_MRX_P4 T49 PAD

PCI-EXPRESS GRAPHICS
R108 0_0402_5% EXP_RXP4 PCIE_GTX_C_MRX_P5 T50 PAD
D32 LBKLT_CTL EXP_RXP5 L38
C C
(32) ENBKL 1 2 LBKLT_EN LBKLT_EN J30 LBKLT_EN EXP_RXP6 M34 PCIE_GTX_C_MRX_P6 T51 PAD
LCTLA_CLK H30 N38 PCIE_GTX_C_MRX_P7 T52 PAD
LCTLB_DATA LCTLA_CLK EXP_RXP7 PCIE_GTX_C_MRX_P8 T53 PAD
H29 LCTLB_DATA EXP_RXP8 P34
(15) I2CC_SCL I2CC_SCL G26 R38 PCIE_GTX_C_MRX_P9 T54 PAD
I2CC_SDA LDDC_CLK EXP_RXP9 PCIE_GTX_C_MRX_P10 T55 PAD
(15) I2CC_SDA G25 LDDC_DATA EXP_RXP10 T34
GMCH_ENVDD F32 V38 PCIE_GTX_C_MRX_P11 T56 PAD
(15) GMCH_ENVDD LVDD_EN EXP_RXP11
LIBG B38 W34 PCIE_GTX_C_MRX_P12 T57 PAD
LIBG EXP_RXP12 PCIE_GTX_C_MRX_P13 T58 PAD
C35 LVBG EXP_RXP13 Y38
C33 AA34 PCIE_GTX_C_MRX_P14 T59 PAD
LVREFH EXP_RXP14 PCIE_GTX_C_MRX_P15 T60 PAD
C32 LVREFL EXP_RXP15 AB38
T61 PAD
F36 PCIE_MTX_GRX_N0
GMCH_TV_COMPS EXP_TXN0 PCIE_MTX_GRX_N1
(16) GMCH_TV_COMPS A16 TVDAC_A EXP_TXN1 G40
GMCH_TV_LUMA C18 H36 PCIE_MTX_GRX_N2
(16) GMCH_TV_LUMA TVDAC_B EXP_TXN2
GMCH_TV_CRMA A19 J40 PCIE_MTX_GRX_N3
(16) GMCH_TV_CRMA TVDAC_C EXP_TXN3

TV
L36 PCIE_MTX_GRX_N4
EXP_TXN4
1 2 TV_IREF J20 TV_IREF EXP_TXN5 M40 PCIE_MTX_GRX_N5 T62 PAD
R82 4.99K_0402_1% N36 PCIE_MTX_GRX_N6 T63 PAD
TVOUT@ EXP_TXN6 PCIE_MTX_GRX_N7 T64 PAD
B16 TV_IRTNA EXP_TXN7 P40
B18 R36 PCIE_MTX_GRX_N8 T65 PAD
TV_IRTNB EXP_TXN8 PCIE_MTX_GRX_N9 T66 PAD
B19 TV_IRTNC EXP_TXN9 T40
V36 PCIE_MTX_GRX_N10 T67 PAD
EXP_TXN10 PCIE_MTX_GRX_N11 T68 PAD
J29 TV_DCONSEL1 EXP_TXN11 W40
K30 Y36 PCIE_MTX_GRX_N12 T69 PAD
TV_DCONSEL0 EXP_TXN12 PCIE_MTX_GRX_N13 T70 PAD
EXP_TXN13 AA40
AB36 PCIE_MTX_GRX_N14 T71 PAD
EXP_TXN14 PCIE_MTX_GRX_N15 T72 PAD
EXP_TXN15 AC40
GMCH_CRT_CLK C26 T73 PAD
(16) GMCH_CRT_CLK DDCCLK
CRT

GMCH_CRT_DATA C25 D36 PCIE_MTX_GRX_P0


(16) GMCH_CRT_DATA DDCDATA EXP_TXP0
F40 PCIE_MTX_GRX_P1
EXP_TXP1 PCIE_MTX_GRX_P2
(16) GMCH_CRT_VSYNC H23 VSYNC EXP_TXP2 G36
G23 H40 PCIE_MTX_GRX_P3
B (16) GMCH_CRT_HSYNC HSYNC EXP_TXP3 B
E23 J36 PCIE_MTX_GRX_P4
(16) GMCH_CRT_B BLUE EXP_TXP4
2 1 D23 L40 PCIE_MTX_GRX_P5 T74 PAD
R567 150_0402_1% BLUE# EXP_TXP5 PCIE_MTX_GRX_P6 T75 PAD
(16) GMCH_CRT_G C22 GREEN EXP_TXP6 M36
2 1 B22 N40 PCIE_MTX_GRX_P7 T76 PAD
R565 150_0402_1% GREEN# EXP_TXP7 PCIE_MTX_GRX_P8 T77 PAD
(16) GMCH_CRT_R A21 RED EXP_TXP8 P36
2 1 B21 R40 PCIE_MTX_GRX_P9 T78 PAD
R564 150_0402_1% RED# EXP_TXP9 PCIE_MTX_GRX_P10 T79 PAD
EXP_TXP10 T36
V40 PCIE_MTX_GRX_P11 T80 PAD
EXP_TXP11
1 2 CRT_IREF J22 CRT_IREF EXP_TXP12 W36 PCIE_MTX_GRX_P12 T81 PAD
R91 255_0402_1% Y40 PCIE_MTX_GRX_P13 T82 PAD
EXP_TXP13 PCIE_MTX_GRX_P14 T83 PAD
10mils EXP_TXP14 AA36
PCIE_MTX_GRX_P15 T84 PAD
EXP_TXP15 AB40
+3VS T85 PAD

CALISTOGA_FCBGA1466~D
R122 1 2 10K_0402_5% I2CC_SCL

R104 1 2 10K_0402_5% I2CC_SDA


PCIE_GTX_C_MRX_N1 7307@ C696 1 2 0.1U_0402_16V4Z
SDVO_INT# (17)
R125 1 2 10K_0402_5% LCTLB_DATA PCIE_GTX_C_MRX_P1 C695 1 2 0.1U_0402_16V4Z
SDVO_INT (17)
7307@
R117 1 2 10K_0402_5% LCTLA_CLK
PCIE_MTX_GRX_N0 7307@ C216 1 2 0.1U_0402_16V4Z
SDVOB_R# (17)
R107 1 2 4.7K_0402_5% GMCH_CRT_CLK PCIE_MTX_GRX_P0 C209 1 2 7307@ 0.1U_0402_16V4Z SDVOB_R (17)
R94 1 2 4.7K_0402_5% GMCH_CRT_DATA PCIE_MTX_GRX_N1 C240 1 2 7307@ 0.1U_0402_16V4Z SDVOB_G# (17)
PCIE_MTX_GRX_P1 C239 1 2 7307@ 0.1U_0402_16V4Z SDVOB_G (17)
PCIE_MTX_GRX_N2 C242 1 2 7307@ 0.1U_0402_16V4Z SDVOB_B# (17)
R109 1 2 100K_0402_5% LBKLT_EN PCIE_MTX_GRX_P2 C241 1 2 7307@ 0.1U_0402_16V4Z SDVOB_B (17)
R576 1 2 1.5K_0402_1% LIBG PCIE_MTX_GRX_N3 C235 1 2 7307@ 0.1U_0402_16V4Z
A SDVOB_CLK# (17) A
PCIE_MTX_GRX_P3 C234 1 2 0.1U_0402_16V4Z
SDVOB_CLK (17)
R541 1 2 150_0402_1% GMCH_TV_COMPS 7307@
TVOUT@
R544 1 2 150_0402_1% GMCH_TV_LUMA
TVOUT@
R563 1 2 150_0402_1% GMCH_TV_CRMA
TVOUT@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 8 of 47
5 4 3 2 1
5 4 3 2 1

D7 R101
@ RB751V_SOD323 @ 10_0402_5%
+1.05VS 2 1 1 2 +2.5VS

D6 R93
@ RB751V_SOD323 @ 10_0402_5%
+1.5VS 2 1 1 2 +3VS

D +2.5VS D

U40H +1.5VS_DPLLA L46 +1.5VS_DPLLB L45


+1.05VS H22 1 2 MBK1608301YZF_0603 MBK1608301YZF_0603
VCC_SYNC C117 2 1 +1.5VS 2 1 +1.5VS
AC14 (60mA) 0.1U_0402_16V4Z +2.5VS
VTT0

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
(800mA) AB14 B30 +2.5VS
VTT1 VCCTX_LVDS0
W14 VTT2 VCCTX_LVDS1 C30 1 1 1
V14 A30 +1.5VS_PCIE R580
VTT3 VCCTX_LVDS2 1 1

C194

C683

C196
T14 0_0805_5% + C687 + C690
R14
VTT4
VTT5 VCC3G0 AB41 W=60 mils 2 1 +1.5VS 2
P14 AJ41 330U_D2E_2.5VM 330U_D2E_2.5VM
VTT6 VCC3G1 2 2 2 2

10U_0805_10V4Z

10U_0805_10V4Z
N14 L41 (1500mA) 1
VTT7 VCC3G2
M14 VTT8 VCC3G3 N41 1 1
L14 R41 C739 +
VTT9 VCC3G4

C712

C722
AD13 VTT10 VCC3G5 V41 close pin G41
AC13 Y41 220U_D2_2VMR15
VTT11 VCC3G6 2 2 2
AB13 VTT12
1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VS_3GPLL
Y13 VTT14 VCCA_3GBG G41 +2.5VS
C629 + W13 H41 (2mA) +3VS_TVDACB L7 +3VS +3VS_TVDACA L5 +3VS
VTT15 VSSA_3GBG L8 MBK1608301YZF_0603 MBK1608301YZF_0603
V13 VTT16
220U_D2_2VMR15 U13 MBK1608301YZF_0603 2 1 2 1
2 VTT17

0.022U_0402_16V7K

0.022U_0402_16V7K
T13 VTT18 VCCA_CRTDAC0 E21 (70mA) +2.5VS_CRTDAC 2 1 +2.5VS

0.022U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R13 VTT19 VCCA_CRTDAC1 F21 1

0.1U_0402_16V4Z
N13 VTT20 VSSA_CRTDAC2 G21 1 2005/09/21 1 1 1 1
M13 + C49
VTT21 1 1

C105

C92

C84

C85
L13 + C927
VTT22

C118

C106
AB12 VTT23 VCCA_DPLLA B26 (50mA) +1.5VS_DPLLA 220U_D2_4VM
2 2 2 2 2
AA12 VTT24 VCCA_DPLLB C39 (50mA) +1.5VS_DPLLB 220U_D2_4VM
2 2 2
Y12 VTT25 VCCA_HPLL AF1 (45mA) +1.5VS_HPLL
W12 VTT26
C C
V12 VTT27
U12 VTT28 VCCA_LVDS A38 (10mA) +2.5VS
T12 VTT29 VSSA_LVDS B39
R12 VTT30
P12 VTT31
N12 AF2 (45mA)
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL +3VS_TVDACC L4 +3VS
+2.5VS
2.2U_0805_10V6K
4.7U_0805_10V4Z

L12 H20 +3VS_TVBG MBK1608301YZF_0603


VTT34 VCCA_TVBG
R11 VTT35 VSSA_TVBG G20 2 1

0.022U_0402_16V7K
1 1 P11 (120mA)
VTT36

0.01U_0402_16V7K
C627

C67

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N11 VTT37
M11 VTT38 VCCA_TVDACA0 E19 +3VS_TVDACA 1 1
R10 VTT39 VCCA_TVDACA1 F19
2 2

C93

C107
P10 VTT40 VCCA_TVDACB0 C20 +3VS_TVDACB 1 1 CRTDAC: Route caps within

C195

C180
N10 VTT41 VCCA_TVDACB1 D20
M10 E20 +3VS_TVDACC
250mil of Alviso. Route FB 2 2
VTT42 VCCA_TVDACC0
P9 VTT43 VCCA_TVDACC1 F20 within 3" of Calistoga
2 2
N9 VTT44
M9 VTT45
R8 VTT46 VCCD_HMPLL0 AH1 (150mA) +1.5VS
P8 VTT47 VCCD_HMPLL1 AH2
N8 VTT48 close pin A38
M8 VTT49
P7 VTT50 VCCD_LVDS0 A28
N7 B28 (20mA)
VTT51 VCCD_LVDS1
M7 C28
R6
P6
VTT52
VTT53
VCCD_LVDS2
D21 (24mA) +1.5VS_TVDAC
+3VS_TVBG R90
0_0603_5%
+3VS
PCI-E/MEM/PSB PLL decoupling
VTT54 VCCD_TVDAC
M6 VTT55 VCCDQ_TVDAC H19 2 1

0.022U_0402_16V7K
MCH_A6 A6 VTT56 +1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
0.47U_0603_16V4Z

0.1U_0402_16V4Z
R5 A23 +3VS R112 R568
VTT57 VCCHV0 (40mA) 0_0603_5% 0_0603_5%
P5 VTT58 VCCHV1 B23 1 1
0.1U_0402_16V4Z

10U_0805_10V4Z

B B
1 N5 VTT59 VCCHV2 B25 2 1 2 1

0.022U_0402_16V7K
C643

C108

C109

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M5 VTT60 1 1
C111

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P4 VTT61 VCCAUX0 AK31
2 2
C127

N4 VTT62 VCCAUX1 AF31 1 1 1 1 1 1


2

C141

C140

C119

C672
M4 VTT63 VCCAUX2 AE31
2 2

C94
C139
R3 VTT64 VCCAUX3 AC31
P3 AL30 @ @
VTT65 VCCAUX4 2 2 2 2 2 2
N3 VTT66 VCCAUX5 AK30
M3 VTT67 VCCAUX6 AJ30
+1.5VS
0.22U_0603_16V7K

R2 VTT68 VCCAUX7 AH30


P2 VTT69 VCCAUX8 AG30
1 M2 VTT70 VCCAUX9 AF30
C630

0.1U_0402_16V4Z

MCH_D2 D2 AE30
VTT71 VCCAUX10
0.22U_0603_16V7K

AB1 VTT72 VCCAUX11 AD30 1


R1 AC30
MCH_AB1

2 VTT73 VCCAUX12
C68

1 P1 VTT74 VCCAUX13 AG29


+1.5VS_MPLL +1.5VS_HPLL
C633

N1 AF29 R517 R516


VTT75 VCCAUX14 2 0_0603_5% 0_0603_5%
M1 VTT76 VCCAUX15 AE29
0.47U_0603_16V4Z

2 VCCAUX16 AD29 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS


1 VCCAUX17 AC29

0.1U_0402_16V4Z

0.1U_0402_16V4Z
VCCAUX18 AG28
C632

10U_0805_10V4Z

10U_0805_10V4Z
VCCAUX19 AF28
VCCAUX20 AE28 1 1 1 1
2

C637

C638
VCCAUX21 AH22

C636

C631
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
2 2 2 2
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20
Y14 VCCAUX35 VCCAUX26 AH19
AF13 VCCAUX36 VCCAUX27 P19
AE13 VCCAUX37 VCCAUX28 P16
+1.5VS AF12 AH15
A VCCAUX38 VCCAUX29 A
AE12 VCCAUX39 VCCAUX30 P15
AD12 VCCAUX40 VCCAUX31 AH14

CALISTOGA_FCBGA1466~D

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 9 of 47
5 4 3 2 1
5 4 3 2 1

Strap Pin Table


CFG[3:17] have internal pull up
CFG[19:18] have internal pull down
+1.05VS U40F +1.5VS +1.05VS U40G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
(3500mA) AC27 AF27 W33 AT41 MCH_AT41 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 MCH_AM41
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2

0.47U_0603_16V4Z

0.47U_0603_16V4Z
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved

C718

C717
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU*(Default)
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_16V7K

0.22U_0603_16V7K

0.22U_0603_16V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34


2 2 0 = Lane Reversal Enable
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 CFG9 1 = Normal Operation*(Default)
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30
C639

C42

C640

AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30


AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 L32 VCC13 VCC_SM13 AW30 CFG11 0 = Reserved
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 PSB 4X CLK Enable 1 = Calistoga *
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29 11 = Normal Operation *(Default)
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 M31 VCC22 VCC_SM22 AL29
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28 0 = 1.05V *(Default)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 CFG18 1 = 1.5V
1U_0603_10V4Z

T25 W17 T30 AJ27


P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1
10U_0805_10V4Z

10U_0805_10V4Z

R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)

C75

C86
C121

C129
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 N30 VCC31 VCC_SM31 AY26
2 2 2 2
C45

C44

C43

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 L30 VCC33 VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 V29 VCC37 VCC_SM37 AJ26
C
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0603_16V4Z
1 AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22
V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22
C41 + U22 AE15 U28 AW22
VCC_NCTF47 VCCAUX_NCTF47 VCC47 VCC_SM47 1

C679
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22
220U_D2_2VMR15 R22 AC15 R28 AU22
2 VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22
2 R58
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 (6) CFG5 1 2 @ 2.2K_0402_5%
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
T21 W15 L28 AK22 R81 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53 (6) CFG7
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 P27 VCC54 VCC_SM54 AJ22
AD20 U15 N27 AK21 R67 1 2 @ 2.2K_0402_5%
VCC_NCTF55 VCCAUX_NCTF55 VCC55 VCC_SM55 (6) CFG9
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 R57 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 (6) CFG11
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19
R20 N26 AW19 R59 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 (6) CFG12

10U_0805_10V4Z

10U_0805_10V4Z
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19 1
1 V19 AE26 N25 AU19 1 1 R69 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 + C735 (6) CFG13
U19 VCC_NCTF62 VSS_NCTF2 AE25 M25 VCC62 VCC_SM62 AT19

C720

C719
C40 + T19 AE24 L25 AR19 R68 1 2 @ 2.2K_0402_5%
VCC_NCTF63 VSS_NCTF3 VCC63 VCC_SM63 (6) CFG16
@ AD18 AE23 P24 AP19 220U_D2_4VM
220U_D2_2VMR15 VCC_NCTF64 VSS_NCTF4 VCC64 VCC_SM64 2 2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
2
AB18 VCC_NCTF66 VSS_NCTF6 AE21 M24 VCC66 VCC_SM66 AJ19
AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18
Y18 VCC_NCTF68 VSS_NCTF8 AE19 AA23 VCC68 VCC_SM68 AJ17
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16
B
U18 Y17 N23 AH16 +3VS B
VCC_NCTF71 VSS_NCTF11 VCC71 VCC_SM71
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
+1.05VS L23 AY15 R92 1 2 @ 1K_0402_5%
VCC73 VCC_SM73 (6) CFG18

0.47U_0603_16V4Z
AC22 VCC74 VCC_SM74 AW15
+1.8V R95
M19 VCC100 AB22 VCC75 VCC_SM75 AV15 (6) CFG19 1 2 @ 1K_0402_5%
L19 VCC101 VCC_SM100 AR6 Y22 VCC76 VCC_SM76 AU15 1

C650
N18 AP6 W22 AT15 R118 1 2 @ 1K_0402_5%
VCC102 VCC_SM101 VCC77 VCC_SM77 (6) CFG20
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 MCH_AV1 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 MCH_AJ1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_16V4Z

0.47U_0603_16V4Z

L16 VCC110 N21 VCC85 VCC_SM85 AH12


M21 VCC86 VCC_SM86 AG12 Place near pin BA15
1 1 L21 VCC87 VCC_SM87 AK11
C635

C634

CALISTOGA_FCBGA1466~D AC20 BA8


VCC88 VCC_SM88
AB20 VCC89 VCC_SM89 AY8
Y20 VCC90 VCC_SM90 AW8
2 2
W20 VCC91 VCC_SM91 AV8
P20 VCC92 VCC_SM92 AT8
N20 VCC93 VCC_SM93 AR8
M20 VCC94 VCC_SM94 AP8
L20 VCC95 VCC_SM95 BA6
AB19 VCC96 VCC_SM96 AY6
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 10 of 47
5 4 3 2 1
5 4 3 2 1

U40I U40J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39 AJ31 AP17 G7
T39
VSS29
VSS30
VSS129
VSS130 AG31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39 E30 AL16 Y6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 11 of 47
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V

JP22 *** +1.8V


+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ6
VSS DQ4

1
DDRA_SDQ4 5 6 DDRA_SDQ0
DDRA_SDQ1 DQ0 DQ5 R153
7 DQ1 VSS 8
9 10 DDRA_SDM0
DDRA_SDQS0# VSS DM0 1K_0402_1%
(7) DDRA_SDQS0# 11 DQS0# VSS 12
DDRA_SDQS0 13 14 DDRA_SDQ5 20mils

2
(7) DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7
15 VSS DQ7 16 +DIMM_VREF
DDRA_SDQ2 17 18
DQ2 VSS

1
DDRA_SDQ3 19 20 DDRA_SDQ13 1 1
DQ3 DQ12 DDRA_SDQ12 C281 C294 R156
21 VSS DQ13 22
DDRA_SDQ8 23 24
D DDRA_SDQ14 DQ8 VSS DDRA_SDM1 0.1U_0402_16V4Z 2.2U_0805_10V6K 1K_0402_1% D
25 DQ9 DM1 26
2 2
27 28

2
DDRA_SDQS1# VSS VSS
(7) DDRA_SDQS1# 29 DQS1# CK0 30 DDRA_CLK0 (6)
DDRA_SDQS1 31 32
(7) DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# (6)
33 VSS VSS 34
DDRA_SDQ9 35 36 DDRA_SDQ11
DDRA_SDQ15 DQ10 DQ14 DDRA_SDQ10
37 DQ11 DQ15 38
39 VSS VSS 40
DDRA_SMA[0..13]
(7) DDRA_SMA[0..13]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDQ[0..63]
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 (7) DDRA_SDQ[0..63]
45 DQ17 DQ21 46
47 48 0_0402_5% DDRA_SDM[0..7]
VSS VSS (7) DDRA_SDM[0..7]
DDRA_SDQS2# 49 50 R119 1 2
(7) DDRA_SDQS2# DQS2# NC PM_EXTTS#0 (6,13) +1.8V
DDRA_SDQS2 51 52 DDRA_SDM2
(7) DDRA_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRA_SDQ18 55 56 DDRA_SDQ23
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ22
57 DQ19 DQ23 58
59 VSS VSS 60 1 1 1 1 1
DDRA_SDQ29 61 62 DDRA_SDQ28 C71 C53 C123 C125 C54
DDRA_SDQ24 DQ24 DQ28 DDRA_SDQ25
63 DQ25 DQ29 64
65 66 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K
DDRA_SDM3 VSS VSS DDRA_SDQS3# 2 2 2 2 2
67 DM3 DQS3# 68 DDRA_SDQS3# (7)
69 70 DDRA_SDQS3
NC DQS3 DDRA_SDQS3 (7)
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ31
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ30
75 DQ27 DQ31 76
77 78 +1.8V
DDRA_CKE0 VSS VSS DDRA_CKE1 +0.9VS
(6) DDRA_CKE0 79 CKE0 NC/CKE1 80 DDRA_CKE1 (6)
81 VDD VDD 82
83 84 DDRA_CKE0 1 4
C DDRA_SBS2# NC NC/A15 DDRA_SBS2# C
(7) DDRA_SBS2# 85 BA2 NC/A14 86 2 3 1 1 1 1
87 88 RP41 56_0404_4P2R_5% C115 C113 C62 C63
DDRA_SMA12 VDD VDD DDRA_SMA11
89 A12 A11 90
DDRA_SMA9 91 92 DDRA_SMA7 DDRA_SMA12 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA8 A9 A7 DDRA_SMA6 DDRA_SMA9 2 2 2 2
93 A8 A6 94 2 3
95 96 RP39 56_0404_4P2R_5%
DDRA_SMA5 VDD VDD DDRA_SMA4
97 A5 A4 98
DDRA_SMA3 99 100 DDRA_SMA2 DDRA_SMA8 1 4
DDRA_SMA1 A3 A2 DDRA_SMA0 DDRA_SMA5
101 A1 A0 102 2 3
103 104 RP37 56_0404_4P2R_5%
DDRA_SMA10 VDD VDD DDRA_SBS1#
105 A10/AP BA1 106 DDRA_SBS1# (7)
DDRA_SBS0# 107 108 DDRA_SRAS# DDRA_SMA3 1 4
(7) DDRA_SBS0# BA0 RAS# DDRA_SRAS# (7) +0.9VS
DDRA_SWE# 109 110 DDRA_SCS#0 DDRA_SMA1 2 3
(7) DDRA_SWE# WE# S0# DDRA_SCS#0 (6)
111 112 RP35 56_0404_4P2R_5%
DDRA_SCAS# VDD VDD DDRA_ODT0
(7) DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 (6)
DDRA_SCS#1 115 116 DDRA_SMA13 DDRA_SMA10 1 4
(6) DDRA_SCS#1 NC/S1# NC/A13
117 118 DDRA_SBS0# 2 3 1 1 1 1 1
DDRA_ODT1 VDD VDD RP33 56_0404_4P2R_5% C645 C648 C653 C660 C667
(6) DDRA_ODT1 119 NC/ODT1 NC 120
121 VSS VSS 122
DDRA_SDQ37 123 124 DDRA_SDQ39 DDRA_SWE# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ36 DQ32 DQ36 DDRA_SDQ38 DDRA_SCAS# 2 2 2 2 2
125 DQ33 DQ37 126 2 3
127 128 RP31 56_0404_4P2R_5%
DDRA_SDQS4# VSS VSS DDRA_SDM4
(7) DDRA_SDQS4# 129 DQS4# DM4 130
DDRA_SDQS4 131 132 DDRA_SCS#1 1 4
(7) DDRA_SDQS4 DQS4 VSS DDRA_SDQ34 DDRA_ODT1
133 VSS DQ38 134 2 3
DDRA_SDQ35 135 136 DDRA_SDQ33 RP29 56_0404_4P2R_5% +0.9VS
DDRA_SDQ32 DQ34 DQ39
137 DQ35 VSS 138
139 140 DDRA_SDQ45
DDRA_SDQ40 VSS DQ44 DDRA_SDQ43
141 DQ40 DQ45 142
DDRA_SDQ44 143 144 DDRA_CKE1 1 4 1 1 1 1 1
DQ41 VSS DDRA_SDQS5# DDRA_SMA11 C671 C678 C104 C69 C76
145 VSS DQS5# 146 DDRA_SDQS5# (7) 2 3
DDRA_SDM5 147 148 DDRA_SDQS5 RP12 56_0404_4P2R_5%
B DM5 DQS5 DDRA_SDQS5 (7) 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
149 VSS VSS 150
DDRA_SDQ41 DDRA_SDQ47 DDRA_SMA7 2 2 2 2 2
151 DQ42 DQ46 152 1 4
DDRA_SDQ46 153 154 DDRA_SDQ42 DDRA_SMA6 2 3
DQ43 DQ47 RP10 56_0404_4P2R_5%
155 VSS VSS 156
DDRA_SDQ49 157 158 DDRA_SDQ52
DDRA_SDQ48 DQ48 DQ52 DDRA_SDQ53 DDRA_SMA4
159 DQ49 DQ53 160 1 4
161 162 DDRA_SMA2 2 3 +0.9VS
VSS VSS RP8 56_0404_4P2R_5%
163 NC,TEST CK1 164 DDRA_CLK1 (6)
165 VSS CK1# 166 DDRA_CLK1# (6)
DDRA_SDQS6# 167 168 DDRA_SMA0 1 4
(7) DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6 DDRA_SBS1#
(7) DDRA_SDQS6 169 DQS6 DM6 170 2 3 1 1 1
171 172 RP6 56_0404_4P2R_5% C80 C88 C95
DDRA_SDQ54 VSS VSS DDRA_SDQ51
173 DQ50 DQ54 174
DDRA_SDQ50 175 176 DDRA_SDQ55 DDRA_SRAS# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DQ51 DQ55 DDRA_SCS#0 2 2 2
177 VSS VSS 178 2 3
DDRA_SDQ60 179 180 DDRA_SDQ57 RP4 56_0404_4P2R_5%
DDRA_SDQ61 DQ56 DQ60 DDRA_SDQ56
181 DQ57 DQ61 182
183 184 DDRA_ODT0 1 4
DDRA_SDM7 VSS VSS DDRA_SDQS7# DDRA_SMA13
185 DM7 DQS7# 186 DDRA_SDQS7# (7) 2 3
187 188 DDRA_SDQS7 RP2 56_0404_4P2R_5%
DDRA_SDQ59 VSS DQS7 DDRA_SDQS7 (7)
189 DQ58 VSS 190
DDRA_SDQ58 191 192 DDRA_SDQ62
DQ59 DQ62 DDRA_SDQ63
193 VSS DQ63 194
D_CK_SDATA 195 196
(13,14) D_CK_SDATA SDA VSS
D_CK_SCLK 197 198 R23 1 2 10K_0402_5%
(13,14) D_CK_SCLK SCL SAO
+3VS 199 200 R21 1 2 10K_0402_5%
VDDSPD SA1
203 GND1 GND2 204

P-TWO_A5692A-A0G16-N

A
DIMM0 STD H:9.2mm (BOT) A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 12 of 47
5 4 3 2 1
A B C D E

+1.8V +1.8V

JP21 ***
1 2 +DIMM_VREF +1.8V
+DIMM_VREF VREF VSS
3 4 DDRB_SDQ5
DDRB_SDQ0 VSS DQ4 DDRB_SDQ4
5 DQ0 DQ5 6
DDRB_SDQ1 7 8 1 1
DQ1 VSS DDRB_SDM0
9 VSS DM0 10 1 1 1 1 1 1
DDRB_SDQS0# 11 12 C263 C276 C39 + C290 + C78 C89 C79 C90
(7) DDRB_SDQS0# DDRB_SDQS0 DQS0# VSS DDRB_SDQ6
(7) DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7 2.2U_0805_10V6K @ 150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ2 VSS DQ7 2 2
0.1U_0402_16V4Z 2 2
150U_D2_6.3VM 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24
1 DDRB_SDQ9 DQ8 VSS DDRB_SDM1 1
25 DQ9 DM1 26
27 VSS VSS 28
DDRB_SDQS1# 29 30
(7) DDRB_SDQS1# DQS1# CK0 DDRB_CLK1 (6)
DDRB_SDQS1 31 32
(7) DDRB_SDQS1 DQS1 CK0# DDRB_CLK1# (6)
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DDRB_SDQ17 43 44 DDRB_SDQ21 DDRB_SMA[0..13]
DQ16 DQ20 (7) DDRB_SMA[0..13]
DDRB_SDQ20 45 46 DDRB_SDQ16
DQ17 DQ21 0_0402_5% DDRB_SDQ[0..63]
47 VSS VSS 48 (7) DDRB_SDQ[0..63]
DDRB_SDQS2# 49 50 R120 1 2
(7) DDRB_SDQS2# DQS2# NC PM_EXTTS#0 (6,12) DDRB_SDM[0..7]
DDRB_SDQS2 51 52 DDRB_SDM2 (7) DDRB_SDM[0..7]
(7) DDRB_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22 +1.8V
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 DQ19 DQ23 58
59 VSS VSS 60
DDRB_SDQ28 61 62 DDRB_SDQ26
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ24
63 DQ25 DQ29 64 1 1 1 1 1
65 66 C50 C55 C124 C126 C70
DDRB_SDM3 VSS VSS DDRB_SDQS3#
67 DM3 DQS3# 68 DDRB_SDQS3# (7)
69 70 DDRB_SDQS3 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K
NC DQS3 DDRB_SDQS3 (7) 2 2
2.2U_0805_10V6K 2 2
2.2U_0805_10V6K 2
71 VSS VSS 72
DDRB_SDQ30 73 74 DDRB_SDQ29
DDRB_SDQ31 DQ26 DQ30 DDRB_SDQ27
75 DQ27 DQ31 76
77 VSS VSS 78
DDRB_CKE0 79 80 DDRB_CKE1
(6) DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1 (6) +0.9VS +1.8V
81 VDD VDD 82
83 NC NC/A15 84
2 DDRB_SBS2# 2
(7) DDRB_SBS2# 85 BA2 NC/A14 86
87 88 DDRB_SBS2# 1 4
DDRB_SMA12 VDD VDD DDRB_SMA11 DDRB_CKE0
89 A12 A11 90 2 3 1 1 1 1
DDRB_SMA9 91 92 DDRB_SMA7 RP13 56_0404_4P2R_5% C64 C61 C114 C116
DDRB_SMA8 A9 A7 DDRB_SMA6
93 A8 A6 94
95 96 DDRB_SMA9 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SMA5 VDD VDD DDRB_SMA4 DDRB_SMA12 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
97 A5 A4 98 2 3
DDRB_SMA3 99 100 DDRB_SMA2 RP11 56_0404_4P2R_5%
DDRB_SMA1 A3 A2 DDRB_SMA0
101 A1 A0 102
103 104 DDRB_SMA5 1 4
DDRB_SMA10 VDD VDD DDRB_SBS1# DDRB_SMA8
105 A10/AP BA1 106 DDRB_SBS1# (7) 2 3
DDRB_SBS0# 107 108 DDRB_SRAS# RP9 56_0404_4P2R_5%
(7) DDRB_SBS0# BA0 RAS# DDRB_SRAS# (7)
DDRB_SWE# 109 110 DDRB_SCS#0
(7) DDRB_SWE# WE# S0# DDRB_SCS#0 (6)
111 112 DDRB_SMA1 1 4
DDRB_SCAS# VDD VDD DDRB_ODT0 DDRB_SMA3 +0.9VS
(7) DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 (6) 2 3
DDRB_SCS#1 115 116 DDRB_SMA13 RP7 56_0404_4P2R_5%
(6) DDRB_SCS#1 NC/S1# NC/A13
117 VDD VDD 118
DDRB_ODT1 119 120 DDRB_SBS0# 1 4
(6) DDRB_ODT1 NC/ODT1 NC
121 122 DDRB_SMA10 2 3 1 1 1 1 1
DDRB_SDQ32 VSS VSS DDRB_SDQ36 RP5 56_0404_4P2R_5% C669 C677 C647 C652 C659
123 DQ32 DQ36 124
DDRB_SDQ33 125 126 DDRB_SDQ37
DQ33 DQ37 DDRB_SCAS# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
127 VSS VSS 128 1 4
DDRB_SDQS4# DDRB_SDM4 DDRB_SWE# 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
(7) DDRB_SDQS4# 129 DQS4# DM4 130 2 3
DDRB_SDQS4 131 132 RP3 56_0404_4P2R_5%
(7) DDRB_SDQS4 DQS4 VSS DDRB_SDQ39
133 VSS DQ38 134
DDRB_SDQ34 135 136 DDRB_SDQ38 DDRB_ODT1 1 4
DDRB_SDQ35 DQ34 DQ39 DDRB_SCS#1
137 DQ35 VSS 138 2 3
139 140 DDRB_SDQ44 RP1 56_0404_4P2R_5% +0.9VS
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45
141 DQ40 DQ45 142
DDRB_SDQ41 143 144
DQ41 VSS DDRB_SDQS5# DDRB_CKE1
145 VSS DQS5# 146 DDRB_SDQS5# (7) 1 4
DDRB_SDM5 147 148 DDRB_SDQS5 DDRB_SMA11 2 3 1 1 1 1 1
3 DM5 DQS5 DDRB_SDQS5 (7) RP40 56_0404_4P2R_5% C662 C87 C91 C97 C110 3
149 VSS VSS 150
DDRB_SDQ42 151 152 DDRB_SDQ46
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA7 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
153 DQ43 DQ47 154 1 4
DDRB_SMA6 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
155 VSS VSS 156 2 3
DDRB_SDQ48 157 158 DDRB_SDQ52 RP38 56_0404_4P2R_5%
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
159 DQ49 DQ53 160
161 162 DDRB_SMA4 1 4
VSS VSS DDRB_SMA2 +0.9VS
163 NC,TEST CK1 164 DDRB_CLK0 (6) 2 3
165 166 RP36 56_0404_4P2R_5%
VSS CK1# DDRB_CLK0# (6)
DDRB_SDQS6# 167 168
(7) DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SMA0
(7) DDRB_SDQS6 169 DQS6 DM6 170 1 4
171 172 DDRB_SBS1# 2 3 1 1 1
DDRB_SDQ51 VSS VSS DDRB_SDQ54 RP34 56_0404_4P2R_5% C65 C73 C77
173 DQ50 DQ54 174
DDRB_SDQ50 175 176 DDRB_SDQ55
DQ51 DQ55 DDRB_SRAS# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
177 VSS VSS 178 1 4
DDRB_SDQ56 DDRB_SDQ60 DDRB_SCS#0 2 2
0.1U_0402_16V4Z 2
179 DQ56 DQ60 180 2 3
DDRB_SDQ61 181 182 DDRB_SDQ57 RP32 56_0404_4P2R_5%
DQ57 DQ61
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7# DDRB_ODT0 1 4
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# (7) DDRB_SMA13
187 VSS DQS7 188 DDRB_SDQS7 (7) 2 3
DDRB_SDQ59 189 190 RP30 56_0404_4P2R_5%
DDRB_SDQ58 DQ58 VSS DDRB_SDQ62
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
D_CK_SDATA VSS DQ63
(12,14) D_CK_SDATA 195 SDA VSS 196
D_CK_SCLK 197 198 1 2
(12,14) D_CK_SCLK SCL SAO
+3VS 199 200 R24 1 2 10K_0402_5% +3VS
VDDSPD SA1 R22 10K_0402_5%
203 GND1 GND2 204

P-TWO_A5652C-A0G16

4
DIMM1 STD H:5.2mm (BOT) 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 13 of 47
A B C D E
A B C D E F G H

+CLK_VDDREF
L58
40mil
+CLK_VDD1
Clock Generator
FSLC FSLB FSLA CPU SRC PCI +CLK_VDD48 1 +3VS 1 2
CLKSEL2 CLKSEL1 CLKSEL0 C474
MHz MHz MHz 1
C432
1
C444
1 1 1 1 1
0.047U_0402_16V7K KC FBM-L11-201209-221LMAT_0805 C452 C477 C443 C469 C475
10U_0805_10V4Z 0.047U_0402_16V7K 2 10U_0805_10V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
0 0 1 133 100 33.3 2 2 2 2 2 2 2

0 1 1 166 100 33.3


L59 +CLK_VDD2
Table : ICS9LPR325 20mil L60
U19 +CLK_VCCA 1 2 +CLK_VDD1 40mil
1 +CLK_VDD1 1
0 1 1 1 1 2 +3VS
KC FBM-L11-201209-221LMAT_0805
**SEL_PCI5/REF1 CLKREQ3# 33.3MHz PCICLK5 1 7 C483 C476 1 1 1 KC FBM-L11-201209-221LMAT_0805
VDDSRC VDDA 10U_0805_10V4Z 0.047U_0402_16V7K C457 C460 C440
49 VDDSRC 2 2
**SEL_PCI6/PCICLK1 CLKREQ5# 33.3MHz PCICLK6 54 VDDSRC GNDA 8
65 0.047U_0402_16V7K 0.047U_0402_16V7K 10U_0805_10V4Z
+CLK_VDD2 VDDSRC 2 2 2
**SEL_24M/PCICLK2 TESTMODE 24MHz Output
25 PM_STP_PCI#
PCI_SRC_STOP# PM_STP_PCI# (20)
**SEL_48M/PCICLK3 CLKREQ7# 48MHz_1 Output 30 VDDPCI
36 24 PM_STP_CPU#
VDDPCI CPU_STOP# PM_STP_CPU# (20)
ITP_EN/PCICLK_F0 SRC pair CPU_ITP pair
+CLK_VDD1 12 VDDCPU
11 CLK_CPU1 R373 1 2 0_0402_5% CLK_MCH_BCLK
CPUCLKT1LP CLK_MCH_BCLK (6)
**SEL_24M/PCICLK2=0=TESTMODE C466 1 2 +CLK_VDDREF 18
33P_0402_50V8J R376 1_0603_5% VDDREF CLK_CPU1# R372 1
**SEL_PCI6/PCICLK1=0=CLKREQ5# 15mil CPUCLKC1LP 10 2 0_0402_5% CLK_MCH_BCLK#
CLK_MCH_BCLK# (6)
1 2 1 2 +CLK_VDD48 40 VDD48
R316 2.2_0603_5% 15mil

1
14 CLK_CPU0 R375 1 2 0_0402_5% CLK_CPU_BCLK
+3VS CPUCLKT0LP CLK_CPU_BCLK (4)
Y3 CLK_XTALIN 20
C468 X1 CLK_CPU0# R374 1
**SEL_PCI5=1=PCICLK5 CPUCLKC0LP 13 2 0_0402_5% CLK_CPU_BCLK#
CLK_CPU_BCLK# (4)
33P_0402_50V8J 14.31818MHz_20P_1BX14318BE1A

2
1 2 CLK_REF 1 2 CLK_XTALOUT 19
R712 10K_0402_5% X2
CPUCLKT2_ITP/SRCCLKT10LP 6
CLK_ICH_48M R288 1 2 12_0402_5%
(20) CLK_ICH_48M
CLK_SD_48M R307 1 2 12_0402_5% CLKSEL0 41 5 CLK_MCH_BCLK 1 2
(24) CLK_SD_48M USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
1 2 CLK_PCI0 R383 @ 49.9_0402_1%
R619 10K_0402_5% CLKSEL1 45 CLK_MCH_BCLK# 1 2
FSLB/TEST_MODE/24Mhz CLK_SRC9 R371 1 EXPCARD@ CLK_PCIE_CARD
ITP_EN/PCICLK_F0=0=SRC pair SRCCLKT9LP 3 2 0_0402_5% CLK_PCIE_CARD (29)
R382 @ 49.9_0402_1%
CLK_14M_SIO R349 2 1 33_0402_5% CLKSEL2 23 CLK_CPU_BCLK 1 2
(31) CLK_14M_SIO REF0/FSLC/TEST_SEL
2 CLK_SRC9# R370 1 EXPCARD@
2 0_0402_5% CLK_PCIE_CARD# R385 @ 49.9_0402_1%
SRCCLKC9LP CLK_PCIE_CARD# (29)
2005/10/31 CLK_CPU_BCLK# 1 2
CLK_PCI_SIO R326 1 2 33_0402_5% CLK_PCI4 34 72 R384 @ 49.9_0402_1%
2 (31) CLK_PCI_SIO PCICLK4/FCTSEL1 CLKREQ9# EXP_CLKREQ# (29) 2
CLK_PCI_MINI R327 1 2 12_0402_5% R658 1 2 10K_0402_5% +3VS
(28) CLK_PCI_MINI
CLK_PCI_LAN R333 1 4401@ 2 33_0402_5% CLK_PCI3 33 70 CLK_SRC8 R367 1 MINI2@ 2 0_0402_5% CLK_PCIE_MINI2
(26) CLK_PCI_LAN SEL_48M/PCICLK3 SRCCLKT8LP CLK_PCIE_MINI2 (28)
CLK_PCI_PCM R338 1 2 33_0402_5% CLK_PCI2 32 69 CLK_SRC8# R365 1 MINI2@ 2 0_0402_5% CLK_PCIE_MINI2#
(24) CLK_PCI_PCM SEL_24M/PCICLK2 SRCCLKC8LP CLK_PCIE_MINI2# (28)
1 2 CLK_PCI4
R713 CLK_PCI_LPC R345 1 2 33_0402_5% CLK_PCI1 27 71
(32) CLK_PCI_LPC SEL_PCI6/PCICLK1 CLKREQ8# MINI2_CLKREQ# (28)
10K_0402_5% CLK_PCI_TPM R344 1 @ 2 12_0402_5% R659 1 2 10K_0402_5% +3VS
(31) CLK_PCI_TPM
SRCCLKT7LP 66
CLK_ICH_14M R353 1 2 33_0402_5% CLK_REF CLK_PCIE_MINI2
08/29 add (20) CLK_ICH_14M 22 SEL_PCI5/REF1
67
1
R366
2
@ 49.9_0402_1%
SRCCLKC7LP CLK_PCIE_MINI2# 1 2
CLK_DREF_96M R306 1 2 0_0402_5% CLK_DOT 43 38 R364 @ 49.9_0402_1%
(6) CLK_DREF_96M DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1 CLK_PCIE_ICH 1 2
CLK_DREF_96M# R305 1 2 0_0402_5% CLK_DOT# 44 63 CLK_SRC6 R355 1 2 0_0402_5% CLK_PCIE_SATA R346 @ 49.9_0402_1%
(6) CLK_DREF_96M# DOTC_96MHz/27MHz_spread SRCCLKT6LP CLK_PCIE_SATA (19)
CLK_PCIE_ICH# 1 2
64 CLK_SRC6# R361 1 2 0_0402_5% CLK_PCIE_SATA# R350 @ 49.9_0402_1%
SRCCLKC6LP CLK_PCIE_SATA# (19)
CLK_PCI_ICH R308 1 2 33_0402_5% CLK_PCI0 37 CLK_PCIE_MINI1 1 2
(18) CLK_PCI_ICH ITP_EN/PCICLK_F0
62 R283 @ 49.9_0402_1%
CLKREQ6# SATA_CLKREQ# (20)
R647 1 2 10K_0402_5% +3VS CLK_PCIE_MINI1# 1 2
CLK_ENABLE# 39 60 CLK_SRC5 R347 1 2 0_0402_5% CLK_PCIE_ICH R282 @ 49.9_0402_1%
(47) CLK_ENABLE# VTT_PWRGD#/PD SRCCLKT5LP CLK_PCIE_ICH (20)
CLK_PCIE_SATA 1 2
61 CLK_SRC5# R351 1 2 0_0402_5% CLK_PCIE_ICH# R354 @ 49.9_0402_1%
+3VS SRCCLKC5LP CLK_PCIE_ICH# (20)
R657 1 2 0_0402_5% CLKIREF 9 CLK_PCIE_SATA# 1 2
GND R637 1
15mil CLKREQ5#/PCICLK6 29 2 10K_0402_5% +3VS R360 @ 49.9_0402_1%
CLK_DREF_SSC 1 2
1 2 CLK_ENABLE# 58 CLK_SRC4 R336 1 8789@ 2 0_0402_5% CLK_PCIE_LAN R285 @ 49.9_0402_1%
SRCCLKT4LP CLK_PCIE_LAN (26)
R620 D_CK_SCLK 16 CLK_DREF_SSC# 1 2
(12,13) D_CK_SCLK SMBCLK
10K_0402_5% 59 CLK_SRC4# R340 1 8789@ 2 0_0402_5% CLK_PCIE_LAN# R284 @ 49.9_0402_1%
SRCCLKC4LP CLK_PCIE_LAN# (26)
CLK_DREF_96M 1 2
2005/10/17 57 R640 1 2 @ 10K_0402_5% +3VS R287 @ 49.9_0402_1%
D_CK_SDATA CLKREQ4# CLK_DREF_96M# 1
(12,13) D_CK_SDATA 17 SMBDAT 2
55 CLK_SRC3 R286 @ 49.9_0402_1%
3 SRCCLKT3LP CLK_PCIE_CARD 1 3
2
4 56 CLK_SRC3# R381 @ 49.9_0402_1%
+3VS GNDSRC SRCCLKC3LP CLK_PCIE_CARD# 1 2
R387 15 28 CLK_PCI5 R636 1 2 @ 10K_0402_5% +3VS R380 @ 49.9_0402_1%
4.7K_0402_5% GNDCPU CLKREQ3#/PCICLK5 R334 2 33_0402_5% CLK_PCI_1394 CLK_MCH_3GPLL 1
1 CLK_PCI_1394 (30) 2
2

CLK_SRC2 R300 1 2 0_0402_5% CLK_MCH_3GPLL R281 @ 49.9_0402_1%


G

1 2 +3VS 21 GNDREF SRCCLKT2LP 52 CLK_MCH_3GPLL (6)


CLK_MCH_3GPLL# 1 2
VGATE (6,20,47)
1 3 D_CK_SDATA 31 53 CLK_SRC2# R299 1 2 0_0402_5% CLK_MCH_3GPLL# R280 @ 49.9_0402_1%
(20,26,28,29) ICH_SMBDATA GNDPCI SRCCLKC2LP CLK_MCH_3GPLL# (6)
CLK_PCIE_LAN 1 2
D

Q15 R335 @ 49.9_0402_1%


G

35 GNDPCI CLKREQ2# 26 MCH_CLKREQ# (6)


2N7002_SOT23 R639 1 2 10K_0402_5% +3VS CLK_PCIE_LAN# 1 2
CLK_ENABLE# 1 3 42 50 CLK_SRC1 R302 1 MINI1@ 2 0_0402_5% CLK_PCIE_MINI1 R339 @ 49.9_0402_1%
+3VS GND48 SRCCLKT1LP CLK_PCIE_MINI1 (28)
D

R386 Q38 68 51 CLK_SRC1# R301 1 MINI1@ 2 0_0402_5% CLK_PCIE_MINI1#


GNDSRC SRCCLKC1LP CLK_PCIE_MINI1# (28)
4.7K_0402_5% 2N7002_SOT23
2
G

1 2 +3VS CLKREQ1# 46 MINI1_CLKREQ# (28)


2005/10/17 73 R626 1 2 10K_0402_5% +3VS
D_CK_SCLK THRM_PAD CLK_SRC0 R304 1
(20,26,28,29) ICH_SMBCLK 1 3 74 THRM_PAD LCD100/96/SRC0_TLP 47 2 0_0402_5% CLK_DREF_SSC
CLK_DREF_SSC (6)
75
D

Q14 THRM_PAD CLK_SRC0# R303 1


76 THRM_PAD LCD100/96/SRC0_CLP 48 2 0_0402_5% CLK_DREF_SSC#
CLK_DREF_SSC# (6)
2N7002_SOT23

ICS9LPR325AKLFT_MLF72
+1.05VS +1.05VS +1.05VS
ICS9LPR325AKLFT_MLF72: SA00000RE00
2

R623 R624 SLG8LP465VTR: SA00000TS00 R638


@ 56_0402_5% @ 1K_0402_5% @ 1K_0402_5%

R621 R622 R625 R643 R645


8.2K_0402_5% 1K_0402_5% 1K_0402_5% 8.2K_0402_5% 1K_0402_5%
1

4 CLKSEL0 1 CLKSEL1 CLKSEL2 1 4


2 1 2 MCH_CLKSEL0 (6) 1 2 MCH_CLKSEL1 (6) 2 1 2 MCH_CLKSEL2 (6)
1 2 1 2 CPU_BSEL1 (5) 1 2 1 2 CPU_BSEL2 (5)
1 2 1 2 CPU_BSEL0 (5) R617 R618 R646 R642
R616 R615 @ 0_0402_5% 0_0402_5% @ 0_0402_5% 0_0402_5%
@ 1K_0402_5% 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Thursday, November 10, 2005 Sheet 14 of 47
A B C D E F G H
5 4 3 2 1

LCD POWER CIRCUIT

+3VALW +3VS
+LCDVDD
W=60mils

1
1
R493 C12
R485 100K_0402_5%
D 300_0402_5% 4.7U_0805_10V4Z D
2

1 2

3
D S
G
Q25 2 2 1 2 Q28 AOS 3413
2N7002_SOT23 G R496 1K_0402_5%
S 1 SI2301BDS_SOT23

3
C600 +LCDVDD
D
W=60mils

1
1
D 0.047U_0402_16V7K
Q1 2
(8) GMCH_ENVDD 2
G 2N7002_SOT23 1 1
S C593 C597

3
1
4.7U_0805_10V4Z 0.1U_0402_16V4Z
R490 2 2
10K_0402_5%
2

+3VS

1
R492

4.7K_0402_5%
D27

2
BKOFF# 1 2 RB751V_SOD323 DISPOFF#
(32) BKOFF#

C C

LCD/PANEL BD. Conn.


JP1 I2CC_SCL I2CC_SCL (8)
+INVPWR_B+ DAC_BRIG I2CC_SDA I2CC_SDA (8)
40 20 DAC_BRIG (32)
INVT_PWM
39 19 INVT_PWM (32)
DISPOFF# TXOUT0-
38 18 TXOUT0- (8)
+3VS +LCDVDD TXOUT0+
37 17 TXOUT0+ (8)
I2CC_SCL (60 MIL)
I2CC_SDA 36 16 TXOUT1-
35 15 TXOUT1- (8)
TXOUT1+
34 14 TXOUT1+ (8)
TZOUT0- TXOUT0-
TZOUT0+ 33 13 TXOUT0+ TXOUT2+
32 12 TXOUT2+ (8)
TXOUT2-
31 11 TXOUT2- (8)
TZOUT1+ TXOUT1-
TZOUT1- 30 10 TXOUT1+ TXCLK-
29 9 TXCLK- (8)
TXCLK+
28 8 TXCLK+ (8)
TZOUT2+ TXOUT2+
TZOUT2- 27 7 TXOUT2- TZOUT0-
26 6 TZOUT0- (8)
TZOUT0+
25 5 TZOUT0+ (8)
TZCLK- TXCLK-
TZCLK+ 24 4 TXCLK+ TZOUT1+
23 3 TZOUT1+ (8)
TZOUT1-
B 22 2 TZOUT1- (8) B
21 1 TZOUT2+
TZOUT2+ (8)
ACES_88107-4000G TZOUT2-
TZOUT2- (8)
TZCLK-
TZCLK- (8)
(SAME AS ACES_87216-4016) TZCLK+
TZCLK+ (8)

+LCDVDD
+INVPWR_B+ +3VS
08/30 modified
L1 2 1 B+
KC FBM-L11-201209-221LMAT_0805 1 1 1
C11 C586 C591
L2 2 1
KC FBM-L11-201209-221LMAT_0805 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2
1 1
C930 C10

68P_0402_50V8K
680P_0603_50V7K 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 15 of 47
5 4 3 2 1
A B C D E

CRT Connector D20


@
D21
@
D26
@ +5VS
W=40mils
+R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D22 F1 W=40mils

1
2 1 1 2

RB411D_SOT23 1.1A_6VDC_FUSE
1
C575

3
0.1U_0402_16V4Z
2
+2.5VS 2 1 R474 +CRT_PULLUP
1 0_0603_5% 1

VGA:8P_0402_50V8K
UMA:10P_0402_50V8J
JP15
6
FCM2012C-800_0805 11
(8) GMCH_CRT_R 1 2 CRT_R_L 1
L36 7
12
(8) GMCH_CRT_G 1 2 CRT_G_L 2
L37 8
FCM2012C-800_0805 13
(8) GMCH_CRT_B 1 2 CRT_B_L 3
L42 DDC_MD2 9
FCM2012C-800_0805 1 1 1 14

1
10P_0402_50V8J1 1 1 4
R477 R483 R487 C96 C98 C99 10
C81 C82 C83 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 15
10P_0402_50V8J 2 2 2
1 5
150_0402_1% 150_0402_1% 150_0402_1% 2 2
10P_0402_50V8J2 C573

2
SUYIN_070549FR015S208CR
+CRT_VCC CRT_HSYNC_L
1 2
L38 FCM1608C-121T_0603 2
1 2 2 1 100P_0402_50V8J DSUB_12
C584 0.1U_0402_16V4Z R489 10K_0402_5% 1 2 CRT_VSYNC_L
L40 FCM1608C-121T_0603 1

1
U35
1 1
(HDQ70)

OE#
1 2 CRT_HSYNC 2 4 CRT_HSYNC_B C574
(8) GMCH_CRT_HSYNC A Y
R106 C577 C579 2

G
39_0402_5% 10P_0402_50V8K 10P_0402_50V8K 68P_0402_50V8K DSUB_15
2 SN74AHCT1G125DCKR_SC70-5 2 2 2

3
+CRT_VCC 1

Place closed to chipset C572


1 2 68P_0402_50V8K
C590 0.1U_0402_16V4Z 2

1
U36

OE#
1 2 CRT_VSYNC 2 4 CRT_VSYNC_B
(8) GMCH_CRT_VSYNC A Y
R116

G
39_0402_5% +CRT_VCC
SN74AHCT1G125DCKR_SC70-5

3
+3VS

1
R479
TV-OUT Conn. 4.7K_0402_5% R478

2
D1 D23 D24

G
@ @ @ 4.7K_0402_5%
DAN217_SC59 DAN217_SC59 DAN217_SC59 DSUB_12 1 3
GMCH_CRT_DATA (8)

S
1

1
Q27

2
2N7002_SOT23

G
DSUB_15 1 3 GMCH_CRT_CLK (8)

S
Q26
2

3
2N7002_SOT23
3 3
+3VS

TVOUT@ JP14
(8) GMCH_TV_LUMA 1 2 3
L39 FCM1608C-121T_0603 TV_CRMA_L 6
TVOUT@ TV_COMPS_L 7
(8) GMCH_TV_CRMA 1 2 5
L43 FCM1608C-121T_0603 2
TV_LUMA_L 4
(8) GMCH_TV_COMPS 1 2 1
L41 FCM1608C-121T_0603 8
TVOUT@ 9
1 1 1 TVOUT@ 1 1 C60 1
1

R486 R488 R484 C74 TVOUT@


C52 C72 C57 C56 TVOUT@ SUYIN_030107FR007SX08FU
TVOUT@ TVOUT@ 6P_0402_50V8K TVOUT@ TVOUT@ TVOUT@
2 2 2 6P_0402_50V8K 2 2 2 6P_0402_50V8K
150_0402_5% 150_0402_5% 6P_0402_50V8K 6P_0402_50V8K (ECQ60)
2

TVOUT@ 6P_0402_50V8K
150_0402_5%
TVOUT@

4
VGA:82P_0402_50V8J 4
UMA:6P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Monday, November 14, 2005 Sheet 16 of 47
A B C D E
5 4 3 2 1

+2.5VS +3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3VS
+2.5VS
1 1 1 1 1 1
C5 C3 C9 C4 C8 C6
7307@ 7307@ 7307@ 7307@ 7307@ 7307@
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
BOM structure DVI from SDVO
D D
7307@ Stuff

12
28

15
21
36
42
48
1
U1 @ No _Stuff

DVDD
DVDD

TVDD
TVDD
AVDD
AVDD
AVDD
AVDD_PLL
32 13 DVI_TXC- +DVI_VCC
(8) SDVO_INT SDVOB_INT+ TLC#
33 14 DVI_TXC+
(8) SDVO_INT# SDVOB_INT- TLC
16 DVI_TXD0-
TDC0# DVI_TXD0+
(8) SDVOB_R 37 SDVOB_R+ TDC0 17

1
38 19 DVI_TXD1-
(8) SDVOB_R# SDVOB_R- TDC1#
20 DVI_TXD1+ R481 R482
TDC1 DVI_TXD2- 4.7K_0402_5% 4.7K_0402_5%
(8) SDVOB_G 40 SDVOB_G+ TDC2# 22
+2.5VS DVI_TXD2+ 7307@ 7307@
(8) SDVOB_G# 41 SDVOB_G- TDC2 23

2
(8) SDVOB_B 43 SDVOB_B+
1

R10 44 29 DVI_DET
(8) SDVOB_B# SDVOB_B- HPDET
10K_0402_5%
7307@ 46 11 DVI_SCLK
(8) SDVOB_CLK SDVOB_CLK+ SC_DDC
47 10 DVI_SDATA
(8) SDVOB_CLK# SDVOB_CLK- SD_DDC
2

AS AS 3 9
AS SC_PROM
(18,28,31) PLT_RST_BUF# 2 RESET# SD_PROM 8
1

25 VSWING

AGND_PLL
R9 5 SDVO_SDAT
SPD SDVO_SDAT (8)
10K_0402_5% 27 4 SDVO_SCLK
ATPG SPC SDVO_SCLK (8)

DGND
DGND
AGND
AGND
AGND
TGND
TGND
@ 26 SCEN

NC
NC
Keep 30mil spacing to other signals
2

1
+2.5VS
R6 R1 R5 7307@ CH7307_LQFP48

7
30
31
39
45
18
24
6

34
35
1.2K_0402_5% 10K_0402_5% 10K_0402_5% SDVO_SDAT 1 2
7307@ 7307@ 7307@ R12 7307@ 5.6K_0402_5%
C C

2
SDVO_SCLK 1 2
R11 7307@ 5.6K_0402_5%

DVI-D Connector D25


+DVI_VCC 7307@ RB411D_SOT23
JP16
DVI_TXD0- 17 14 1 2 +5VS
DVI_TXD0+ TMDS_DATA0- +5V
18 TMDS_DATA0+ W=40mils 1
DVI_TXD1- 9 C1
DVI_TXD1+ TMDS_DATA1- 7307@ 0.1U_0402_16V4Z
10 TMDS_DATA1+ 2
DVI_TXD2- 1
DVI_TXD2+ TMDS_DATA2- DVI_SCLK
2 TMDS_DATA2+ DDC_CLOCK 6

12 TMDS_DATA3-
B DVI_SDATA B
13 TMDS_DATA3+ DDC_DATA 7

4 TMDS_DATA4-
5 TMDS_DATA4+
20 TMDS_DATA5-
21 TMDS_DATA5+ Hot Plug Detect 16

DVI_TXC+ 23
DVI_TXC- TMDS_Clock+
24 TMDS_Clock-

TMDS_DATA2/4 shield 3
TMDS_DATA1/3 shield 11
TMDS_DATA0/5 shield 19
TMDS_Clock shield 22

8 Analog VSYNC GND 15

SUYIN_070939FR024S531PL

R2
DVI_DET 1 2
7307@ 20K_0402_5%
1

1
R7
D2 7307@
A @ SKS10-04AT_TSMA 100K_0402_5% A
2

(HDQ70)

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CH7307 & DVI-D Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 17 of 47
5 4 3 2 1
5 4 3 2 1

ICH7M(B-0)(QK17)[ES3]:SA00000JK30
D D

+3VS

R665 1 2 8.2K_0402_5% PCI_DEVSEL#

R629 1 2 8.2K_0402_5% PCI_STOP#

R630 1 2 8.2K_0402_5% PCI_TRDY#

R631 1 2 8.2K_0402_5% PCI_FRAME# (24,26,28,30) PCI_AD[0..31] U48B


PCI_AD0 E18 D7 PCI_REQ#0
AD0 REQ0# PCI_REQ#0 (30)
R648 1 2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 C18 E7 PCI_GNT#0
AD1 GNT0# PCI_GNT#0 (30)
PCI_AD2 A16 C16 PCI_REQ#1
R668 1 2 8.2K_0402_5% PCI _IRDY# PCI_AD3 F18
AD2 PCI REQ1#
D16 PCI_GNT#1
PCI_REQ#1 (28)
AD3 GNT1# PCI_GNT#1 (28)
PCI_AD4 E16 C17 PCI_REQ#2
AD4 REQ2# PCI_REQ#2 (24)
R666 1 2 8.2K_0402_5% PCI_SERR# PCI_AD5 A18 D17 PCI_GNT#2
AD5 GNT2# PCI_GNT#2 (24) +3VS
PCI_AD6 E17 E13 PCI_REQ#3
AD6 REQ3# PCI_REQ#3 (26)
R628 1 2 8.2K_0402_5% PCI_PERR# PCI_AD7 A17 F13 PCI_GNT#3
AD7 GNT3# PCI_GNT#3 (26)
PCI_AD8 A15 A13 PCI_REQ#4
AD8 REQ4# / GPIO22

5
R664 1 2 8.2K_0402_5% PCI_REQ#4 PCI_AD9 C14 A14 U17
PCI_AD10 AD9 GNT4# / GPIO48 PCI_REQ#5 PLT_RST#
E14 C8 2

P
R649 1 AD10 GPIO1 / REQ5# B
2 8.2K_0402_5% PCI_REQ#3 PCI_AD11 D14 AD11 GPIO17 / GNT5# D8 Y 4 PLT_RST_BUF# (17,28,31)
PCI_AD12 B12 1
AD12 A

G
PCI_AD13 C13 B15 PCI_CBE#0
AD13 C/BE0# PCI_CBE#0 (24,26,28,30)
PCI_AD14 G15 C12 PCI_CBE#1 NC7SZ08P5X_NL_SC70-5
PCI_CBE#1 (24,26,28,30)

3
PCI_AD15 AD14 C/BE1# PCI_CBE#2
G13 AD15 C/BE2# D12 PCI_CBE#2 (24,26,28,30)
PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 (24,26,28,30)
PCI_AD17 C11
PCI_AD18 AD17 PCI _IRDY#
D11 AD18 IRDY# A7 PCI_IRDY# (24,26,28,30) 2 1
C PCI_AD19 PCI_PAR R331 @ 0_0402_5% C
A11 AD19 PAR E10 PCI_PAR (24,26,28,30)
PCI_AD20 A10 B18 PCI_RST#
AD20 PCIRST# PCI_RST# (24,26,28,29,30)
PCI_AD21 F11 A12 PCI_DEVSEL#
+3VS AD21 DEVSEL# PCI_DEVSEL# (24,26,28,30)
PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# (24,26,28,30)
PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10 PCI_SERR# (24,26,28)
R670 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP#
AD25 STOP# PCI_STOP# (24,26,28,30)
PCI_AD26 A8 F14 PCI_TRDY#
AD26 TRDY# PCI_TRDY# (24,26,28,30)
R669 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME#
AD27 FRAME# PCI_FRAME# (24,26,28,30)
PCI_AD28 C7
R655 1 PCI_PIRQC# PCI_AD29 AD28 PLT_RST#
2 8.2K_0402_5% B6 AD29 PLTRST# C26 PLT_RST# (6,20,23,26,31,32)
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH (14)
R660 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19 PCI_PME#
AD31 PME# PCI_PME# (26,28,32)
R632 1 2 8.2K_0402_5% PCI_PIRQE#

R644 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQA# A3


Interrupt I/F G8 PCI_PIRQE#
(24) PCI_PIRQA# PIRQA# GPIO2 / PIRQE# PCI_PIRQE# (30)
PCI_PIRQB# B4 F7 PCI_PIRQF#
(24) PCI_PIRQB# PIRQB# GPIO3 / PIRQF# PCI_PIRQF# (26)
R324 1 2 8.2K_0402_5% PCI_PIRQG# PCI_PIRQC# C5 F8 PCI_PIRQG#
PIRQC# GPIO4 / PIRQG# PCI_PIRQG# (28)
PCI_PIRQD# B5 G7 PCI_PIRQH#
PIRQD# GPIO5 / PIRQH# PCI_PIRQH# (28)
R650 1 2 8.2K_0402_5% PCI_PIRQH#

R633 1 2 8.2K_0402_5% PCI_REQ#0 AE5


MISC AE9
RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8
R652 1 2 8.2K_0402_5% PCI_REQ#1 AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R651 1 2 8.2K_0402_5% PCI_REQ#2 AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# (6)
R654 1 2 8.2K_0402_5% PCI_REQ#5 Place closely pin A9
ICH7_BGA652~D

CLK_PCI_ICH
B B

2
R667
10_0402_5%
@

1
1
C851
10P_0402_50V8K
@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 18 of 47
5 4 3 2 1
5 4 3 2 1

C826
+RTCVCC 18P_0402_50V8J
2 1 ICH_RTCX1

10M_0402_5%
1 2005/11/02 X3

1
3 NC OUT 4

R614
R274
32.768KHZ_12.5P_1TJS125DJ2A073 2 1
1M_0402_5% NC IN U48A
C827
2

RTC
SM_INTRUDER# 18P_0402_50V8J AB1 AA6 LPC_AD0
RTXC1 LAD0 LPC_AD0 (31,32)
2 1 ICH_RTCX2 AB2 AB5 LPC_AD1
D RTCX2 LAD1 LPC_AD1 (31,32) D
AC4 LPC_AD2
LAD2 LPC_AD2 (31,32)
+RTCVCC 1 2 ICH_RTCRST# AA3 Y6 LPC_AD3
RTCRST# LAD3 LPC_AD3 (31,32)

LPC
+RTCVCC ENABLE INTERNAL R263
1.05V 20K_0402_5% ICH_INTVRMEN W4 AC3 LPC_DRQ0#
INTVRMEN LDRQ0# LPC_DRQ#0 (31)
SUSPEND SM_INTRUDER# Y5 AA5
INTRUDER# LDRQ1# / GPIO23
REGULARTOR
1

2 1 AB3 LPC_FRAME#
LFRAME# LPC_FRAME# (31,32)
R278 close to RAM door J3 @ JOPEN W1
332K_0402_1% EE_CS
Y1 EE_SHCLK 2 1 R249 10K_0402_5% +3VS
Y2 AE22 EC_GA20
EE_DOUT A20GATE EC_GA20 (32)

LAN
C427 W3 AH28 H_A20M#
H_A20M# (4)
2

EE_DIN A20M#

CPU
1U_0603_10V4Z
ICH_INTVRMEN 1 2 V3 AG27 H_CPUSLP_R# PAD
LAN_CLK CPUSLP# T25
U3 AF24 DPRSTP# R240 1 2 0_0402_5%
LAN_RSTSYNC TP1 / DPRSTP# H_DPRSTP# (4,47)
AH25 H_DPSLP#
+3VS TP2 / DPSLP# H_DPSLP# (4)
U5 R604 2 1 56_0402_5% +1.05VS
LAN_RXD0 H_FERR#
V4 LAN_RXD1 FERR# AG26 H_FERR# (4)
T5 LAN_RXD2
1

AG24 H_PW RGOOD


GPIO49 / CPUPWRGD H_PWRGOOD (4)
R610 U7 LAN_TXD0 H_IGNNE#
V6 LAN_TXD1 IGNNE# AG22 H_IGNNE# (4)
10K_0402_5% V7 AG21
LAN_TXD2 INIT3_3V# H_INIT#
AF22 H_INIT# (4)
2

INIT# H_INTR
INTR AF25 H_INTR (4)
1 2 ICH_AC_BITCLK
(34) ICH_BITCLK_MDC +1.05VS

AC-97/AZALIA
SATA_LED# R627 39_0402_5% U1 R239 2 1 10K_0402_5%
ACZ_BCLK +3VS
(34) ICH_SYNC_MDC 1 2 ICH_AC_SYNC_R R6 AG23 EC_KBRST#
ACZ_SYNC RCIN# EC_KBRST# (32)
R298 39_0402_5%

1
1 2 ICH_AC_RST_R# R5 AF23 H_SMI#
(34) ICH_RST_MDC# ACZ_RST# SMI# H_SMI# (4)
R313 39_0402_5% AH24 H_NMI R605
NMI H_NMI (4)
1 2 ICH_AC_BITCLK (36) ICH_AC_SDIN0 T2
C (36) ICH_BITCLK_AUDIO ACZ_SDIN0 C
R634 39_0402_5% (34) ICH_AC_SDIN1 T3 AH22 H_STPCLK# 56_0402_5%
ACZ_SDIN1 STPCLK# H_STPCLK# (4)
T1

2
ICH_AC_SYNC_R ACZ_SDIN2 THRMTRIP_ICH# R606 1
(36) ICH_SYNC_AUDIO 1 2 THERMTRIP# AF26 2 24.9_0402_1% H_THERMTRIP#
H_THERMTRIP# (4,6)
R297 39_0402_5% 1 2 ICH_AC_SDOUT_R T4
(34) ICH_SDOUT_MDC ACZ_SDOUT
R292 39_0402_5% IDE_DA[0..2] (22,23)
1 2 ICH_AC_RST_R# AH17 IDE_DA0
(36) ICH_RST_AUDIO# DA0
R320 39_0402_5% (32) SATA_LED# SATA_LED# AF18 AE17 IDE_DA1
SATALED# DA1 IDE_DA2
DA2 AF17
(36) ICH_SDOUT_AUDIO 1 2 ICH_AC_SDOUT_R
MAINPWON (41,42,44)
R291 39_0402_5% (22) SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AF3 AE16 IDE_DCS1# IDE_DCS1# (22,23)
SATA_DTX_C_IRX_P0 SATA0RXN DCS1# IDE_DCS3#
(22) SATA_DTX_C_IRX_P0 AE3 SATA0RXP DCS3# AD16 IDE_DCS3# (22,23)
SATA_ITX_DRX_N0 AG2 R222
SATA0TXN

1
SATA
SATA_ITX_DRX_P0 AH2 @ 330_0402_5% C
SATA0TXP IDE_DD[0..15] (22,23)
AB15 IDE_DD0 +1.05VS 1 2 2 Q6
SATA_DTX_C_IRX_N2 DD0 IDE_DD1 B
AF7 SATA2RXN DD1 AE14
SATA_DTX_C_IRX_P2 AE7 AG13 IDE_DD2 E 2SC2411K_SC59

3
SATA2RXP DD2 IDE_DD3 @
AG6 SATA2TXN DD3 AF13
AH6 AD14 IDE_DD4
SATA2TXP DD4 IDE_DD5 H_THERMTRIP#
DD5 AC13
CLK_PCIE_SATA# AF1 AD12 IDE_DD6
(14) CLK_PCIE_SATA# SATA_CLKN DD6
CLK_PCIE_SATA AE1 AC12 IDE_DD7
(14) CLK_PCIE_SATA SATA_CLKP DD7
AE12 IDE_DD8
DD8 IDE_DD9
AH10 SATARBIASN DD9 AF12
R613 1 2 24.9_0402_1% SATARBIAS AG10 AB13 IDE_DD10
SATARBIASP DD10 IDE_DD11
10mils DD11 AC14
IDE_DD12
DD12 AF14
AH13 IDE_DD13
DD13 IDE_DD14
R612 1 2 4.7K_0402_5% IDE_ DIORDY IDE_ DIORDY AG16
IDE DD14 AH14
AC15 IDE_DD15
+3VS (22,23) IDE_DIORDY IORDY DD15
IDE_IRQ AH16
(22,23) IDE_IRQ IDEIRQ
IDE_DDACK# AF16
(22,23) IDE_DDACK# DDACK#
R611 1 2 8.2K_0402_5% IDE_IRQ IDE_DIOW# AH15 AE15 IDE_DDREQ
B (22,23) IDE_DIOW# DIOW# DDREQ IDE_DDREQ (22,23) B
IDE_DIOR# AF15
(22,23) IDE_DIOR# DIOR#

ICH7_BGA652~D

SATA_ITX_DRX_N0 1 2 SATA_ITX_C_DRX_N0
C824 3900P_0402_50V7K SATA_ITX_C_DRX_N0 (22)

SATA_ITX_DRX_P0 1 2 SATA_ITX_C_DRX_P0
C823 3900P_0402_50V7K SATA_ITX_C_DRX_P0 (22)

close ICH7 1 2 SATA_DTX_C_IRX_N0


R247 @ 1K_0402_5%
1 2 SATA_DTX_C_IRX_P0
R252 @ 1K_0402_5%

1 2 SATA_DTX_C_IRX_N2
R248 1K_0402_5%
1 2 SATA_DTX_C_IRX_P2
R254 1K_0402_5%

SATA_RXn/p need tie to ground when SATA port no used

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(2/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 19 of 47
5 4 3 2 1
5 4 3 2 1

Place closely pin B2 Place closely pin AC1


+3VS CLK_ICH_48M CLK_ICH_14M
10K_0402_5% +3VALW
R607 1 2 SERIRQ

1
8.2K_0402_5% R656 R258

1
R609 1 2 PM_CLKRUN# 10_0402_5% 10_0402_5%
R325 R332 @ @
10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%

2
R256 1 2 ICH_VGATE U48C
1 1

2
(14,26,28,29) ICH_SMBCLK ICH_SMBCLK C22 AF19 C844 C406
D +3VALW ICH_SMBDATA SMBCLK GPIO21 / SATA0GP 10P_0402_50V8K 10P_0402_50V8K D
(14,26,28,29) ICH_SMBDATA B22 SMBDATA GPIO19 / SATA1GP AH18

SMB
SATA
GPIO
10K_0402_5% LINKALERT# A26 AH19 @ @
R671 1 EC_SWI# ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
2 B25 SMLINK0 GPIO37 / SATA3GP AE19 1 R608 2
ICH_SMLINK1 A25 100_0402_5%
10K_0402_5% SMLINK1
R352 1 2 ICH_SMLINK0
AC1 CLK_ICH_14M
CLK14 CLK_ICH_14M (14)

Clocks
10K_0402_5% EC_SWI# A28 B2 CLK_ICH_48M
(32) EC_SWI# RI# CLK48 CLK_ICH_48M (14)
R359 1 2 ICH_SMLINK1
SB_SPKR A19
(36) SB_SPKR SPKR
10K_0402_5% (31,33) SUS_STAT# SUS_STAT# A27 C20 SUS_CLK
R672 1 LINKALERT# ITP_DBRESET# SUS_STAT# SUSCLK
2 (4) ITP_DBRESET# A22 SYS_RST#

SYS
B24 PM_SLP_S3#
SLP_S3#