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BTS(C) IV 10 013 C

B. Tech Degree IV Semester Examination, April 2010


CS 403 COMPUTER ARCHITECTURE AND ORGANIZATION
(2006 Scheme) Time: 3 Hours PART A (Answer ALL questions) (8 x 5 = 40)
I.

Maximum Marks: 100

a.

h.

List different types of instructions with examples. Explain briefly any five addressing modes with examples. What do you mean by grouping of control signals in micro programmed control? Explain. Bring out any four comparison of hard wired and micro programmed control. Write short notes on cache memory. Brief on (i) Direct mapping (ii) Block set associative mapping. What is 1/0 mapped I/O Memory mapped I/O Polling Daisy chairing Ventured interrupts Briefly explain DMA.

PART B (4 x 15 = 60) A given computer has 16 bit instructions. Operand addresses are specified using 6 bit fields. There are two operand, one operand and zero operand instructions. What are the maximum possible number of instructions for each type, that can be provided by this computer. Draw instruction formats for all three types of instructions. List the various registers used in a processor which help execution and explain function of each register OR Write short notes on Stack Little endian Big endian Draw and explain functional units of a computer as a block diagram. Explain restoring division with block diagram, algorithm and example.

(9) (6)

III.

a.

b. IV. V. a.

(3 x 2 = 6) (9) (15)

OR
Explain with examples Skip-over is method CO (ii) Bit pair recoding method. Explain briefly with examples normalizing (H) non-nenman rounding Multiply +13 and 6 using booth method (skip over is). (6)

(4) (5) (Turn over)

VI.

a. b.

Explain virtual memory Write short notes on Memory interleaving replacement algorithms Static memory dynamic memory OR A block-set-associative cache consists of a total of 64 blocks divided into 4 block set. The main memory contains 4096 blocks, each block consisting of 128 words: How many bits are there in main memory address How many bits are there in each of TAG, SET and WORD fields. What is Page fault hit ratio

(10)

(5)

VII.

a.

(7)

b.

(3)

c. VIII.

Draw and explain the internal organization of a memory chip of 16 x 8 (16 words x 8 bit) What are I/O channels, explain Multiplexer Selector type channels. OR

(5)

(15)

IX.

a.

Explain Synchronous bus Asynchronous bus (10)

b.

Write short notes on SCSI bus USB.

(5)

**

BTS (C) IV 10 016 B

B. Tech Degree IV Semester Examination, April 2010


CS/IT 406 DATA COMMUNICATION (2006 Scheme) Time: 3 Hours PART A (Answer ALL questions) 1. (a) Maximum Marks: 100

(8 x 5 = 40)

(0

What is line of sight transmission? A TV picture is to be transmitted over a channel of 6 MHZ Bandwidth at a 35 dB SNR. Find the channel capacity. Distinguish between PCM and DM. A carrier is simultaneously modulated by two sine waves with modulation indices of 0.3 and 0.4. If the modulated carrier power is 10 kW. Find the total modulated power. Give the concept of redundancy in error detection. Compare asynchronous and synchronous transmission. What is ADSL? Write short notes on spread spectrum. PART B (4 x 15 = 60)

(a)

(b) (a) (b)

A transmission channel between two communicating DTE's is made up of three stations. The first introduces an attenuation of 16 dB, the second an amplification of 20 dB and the third an attenuation of 10 dB. Assuming a mean transmitted power level of 400 mw. Determine the mean output power level of the channel. Briefly explain the transmission impairments present in the communication system. OR Describe in detail the various wireless transmission media. Data is to be transmitted over the PSTN using a transmission scheme with eight levels per signaling element. If the bandwidth of the PSTN is 3000 HZ, deduce the Nyquist maximum data transfer rate C and the bandwidth efficiency B. Encode the data 01010011 by NRZ-L, AMI, Manchester and differential Manchester techniques. Explain the term MODEM and the various modem standards. OR Construct a Huffman code tree with probabilities 0.4, 0.19, 0.16, 0.15 and 0.1. Draw the spectrum of an AM signal. A series of 8 bit message blocks 11100110 transmitted across a data link using a CRC for error detection. A generator polynomial of 11001 is to be used. Illustrate the following: CRC Generation Process (I) CRC Checking Process. (ii) OR What is flow control? Discuss how stop and wait ARQ is implemented. Give the significance of Hamming Code. With the help of necessary sketch explain Frequency division multiplexing. Write notes on CDMA. OR Explain in detail synchronous time division multiplexing with appropriate diagram. Describe frequency hopping spread spectrum.

(8) (7) (8)

(7) (8) (7) (10) (5)

(a) (b) (a) (b) VI.

(15) (10) (5) (10) (5) (8) (7)

VII.

VIII. IX.

**

BTS (C) IV 10 016 B

B. Tech Degree IV Semester Examination, April 2010


CS/IT 406 DATA COMMUNICATION (2006 Scheme) Time: 3 Hours PART A (Answer ALL questions) 1. (a) Maximum Marks: 100

(8 x 5 = 40)

(0

What is line of sight transmission? A TV picture is to be transmitted over a channel of 6 MHZ Bandwidth at a 35 dB SNR. Find the channel capacity. Distinguish between PCM and DM. A carrier is simultaneously modulated by two sine waves with modulation indices of 0.3 and 0.4. If the modulated carrier power is 10 kW. Find the total modulated power. Give the concept of redundancy in error detection. Compare asynchronous and synchronous transmission. What is ADSL? Write short notes on spread spectrum. PART B (4 x 15 = 60)

(a)

(b) (a) (b)

A transmission channel between two communicating DTE's is made up of three stations. The first introduces an attenuation of 16 dB, the second an amplification of 20 dB and the third an attenuation of 10 dB. Assuming a mean transmitted power level of 400 mw. Determine the mean output power level of the channel. Briefly explain the transmission impairments present in the communication system. OR Describe in detail the various wireless transmission media. Data is to be transmitted over the PSTN using a transmission scheme with eight levels per signaling element. If the bandwidth of the PSTN is 3000 HZ, deduce the Nyquist maximum data transfer rate C and the bandwidth efficiency B. Encode the data 01010011 by NRZ-L, AMI, Manchester and differential Manchester techniques. Explain the term MODEM and the various modem standards. OR Construct a Huffman code tree with probabilities 0.4, 0.19, 0.16, 0.15 and 0.1. Draw the spectrum of an AM signal. A series of 8 bit message blocks 11100110 transmitted across a data link using a CRC for error detection. A generator polynomial of 11001 is to be used. Illustrate the following: CRC Generation Process (I) CRC Checking Process. (ii) OR What is flow control? Discuss how stop and wait ARQ is implemented. Give the significance of Hamming Code. With the help of necessary sketch explain Frequency division multiplexing. Write notes on CDMA. OR Explain in detail synchronous time division multiplexing with appropriate diagram. Describe frequency hopping spread spectrum.

(8) (7) (8)

(7) (8) (7) (10) (5)

(a) (b) (a) (b) VI.

(15) (10) (5) (10) (5) (8) (7)

VII.

VIII. IX.

**

BTS(C) IV 10 015 B

B. Tech Degree IV Semester Examination, April 2010


CS/IT 405 DATA STRUCTURES AND ALGORITHMS
(2006 Scheme)

Maximum Marks : 100 Time : 3 Hours


PART- A (Answer ALL questions)

(8 x 5 = 40)

I.

(a)

(h)

What are multidimensional arrays? List the time complexity of different sorting algorithms. Explain how insertion and deletion are done in a Doubly Linked List. Explain the role of Stack in postlix expression evaluation. What is a complete binary tree? Write the non-recursive algorithm for pre-order tree traversal. What are the different ways to represent a graph in memory? What are B-trees?
PART B

(4 x 15 = 60)

Illustrate the working of quick sort algorithm.


OR Ill.

Explain Hashing in detail.

What is a Circular Queue? Write and explain the basic operations on a circular queue.
OR

Write notes no : (iii) Tree Binary Tree AVL Tree

Explain the different kinds of traversals on trees.


OR

Explain how searching and inserting are done in binary search trees.

Explain the graph taversak methods.


OR

W..ite and illustrate the algorithans used to implement minimum spanning tree.
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BTS(C) IV 10 012 L

B. Tech Degree IV Semester Examination, April 2010


CS/EB/EC/EI 402 MICROPROCESSORS
(2006 Scheme) Time: 3 Hours PART A (Answer ALL questions) Maximum Marks: 100

(8 x 5 -= 40)

I.

a.

h.

Write a short note on usage of temporary registers in 8085. Write the usages of 8085 pins (i) READY (ii) ALE Differentiate between the op-codes LHLD and LDAX. Write a short note on various rotate instructions and their functionalities in 8085. Write a short note on (i) T State (ii) Machine cycle Draw an Instruction Fetch Timing Diagram of 8085. Write a short note on various ports available in 8255. Write a note on Transmitter section of 8251 peripheral device. PART B (4 x 15 = 60) (8) (7) (15) (8) (7)

II. III.

Differentiate between I/O Mapped I/O and Memory mapped I/O mapping techniques. Describe the Register organization of 8085 in detail. OR Write the functions of following group of pins in 8085. (iii) SID, SOD (ii) HOLD, HLDA (i) SO, SI Explain various addressing modes available in 8085 with the help of examples. Design and write a Delay routine for 1 second delay. Assume the clock speed of microprocessor is 3 MHz. OR Write an assembly Language program in 8085 to range a set of numbers stored from memory address 3001 onwards in ascending order and number of elements in the set is available in location address 3000. Write a short note on stack based op-codes and how will it modify the contents of register SP. Draw and explain the timing diagram for the instruction LDA 3000. OR Describe various types of interrupts and their organization in 8085. Write the concept of memory interfacing with the help of an example. Draw the architecture and register organization of peripheral chip 8251. OR Describe various operating modes and control words of peripheral chip 8255. Design an interface circuit to accept 8 bits of data from a ADC and produce various control signals according to the data read is less than 128 The data read is equal to 128 The data read is greater than 128

IV.

V.

(10) (5) (15) (15)

VIII.

a. b.

(8) (7) (5)

IX.

(iii)

Also write the program for implementing the interfacing circuit. ***