4 Bit Ripple Adder

Verilog Model

Full Adder Sub Module : module fulladder(a,b,cin,sum,cout); input a,b,cin; output cout,sum; wire w1,w2,w3; xor (w1,a,b); and (w2,a,b); and (w3,w1,c); xor (sum,w1,cin); or (cout,w2,w3); endmodule

Main Module : module Ripple_adder(a, b, cin, sum, cout); input [3:0] a; input [3:0] b; input cin; output [3:0] sum; output cout; wire w1, w2, w3; fulladder FA0(a[0],b[0],cin,sum[0],w1), FA1(a[1],b[1],w1,sum[1],w2), FA2(a[2],b[2],w2,sum[2],w3), FA3(a[3],b[3],w3,sum[3],cout); endmodule

Simulation Results