Programmable Logic Array (PLA)

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A programmable logic array (PLA) is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products (and sometimes product of sums) canonical forms. One application of a PLA is to implement the control over a datapath. It defines various states in an instruction set, and produces the next state (by conditional branching). [eg. if the machine is in state 2, and will go to state 4 if the instruction contains an immediate field; then the PLA should define the actions of the control in state 2, will set the next state to be 4 if the instruction contains an immediate field, and will define the actions of the control in state 4]. Programmable Logic Arrays should correspond to a state diagram for the system. Other commonly used programmable logic devices are PAL, CPLD and FPGA. Note that the use of the word "programmable" does not indicate that all PLAs are fieldprogrammable; in fact many are mask-programmed during manufacture in the same manner as a mask ROM. This is particularly true of PLAs that are embedded in more complex and numerous integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are called FPLA (Field-programmable PLA).

Programmable logic arrays (PLA's)

The ROM implementation of a function may become quite expensive for functions with a large number of variables, because all potential minterms of the function are implemented, whether or not they are needed. A programmable logic array (PLA) requires that only the minterms required for a function be implemented, and allows the implementation of several functions simultaneously. Moreover, the functions can be implemented directly from their minterm forms (although it is often possible to eliminate some of the minterms, further decreasing the cost of the PLA). The PLA can be considered as a direct POS (or SOP) implementation of a set of switching functions, with a set of AND functions followed by a set of OR functions. A PLA is often said to have an ``AND'' plane followed by an ``OR'' plane. In practice, either NAND or NOR gates are normally used, with the resulting PLA said to be a NAND/NAND or a NOR/NOR device. Figure 1.20 shows a full adder implemented using a NAND/NAND PLA. Note that, since the full adder does not require the minterm , this minterm is not included in the ``AND'' plane of the PLA. Note also that the PLA can implement a function in POS form directly,

without reducing the function to minterm form. This often leads to opportunities for minimizing the area of a PLA. Also, a PLA can implement additional functions of the same set of variables simply by adding another logic gate to the ``OR'' plane. Thus the PLA is an efficient device for the implementation of several functions of the same set of variables.

Figure 1.20: A PLA implementation of a full adder