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  • Cs 1251 Computer Architecture Anna University Previous Year Question Bank Download

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    CS 1251 COMPUTER ARCHITECTURE ANNA UNIVERSITY PREVIOUS YEAR QUESTION BANK DOWNLOAD B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2007. Sixth Semester (Regulation 2004) Electronics and Communication Engineering CS 1251 »- COMPUTER ARCHITECTURE (Common to B.E. (Part-Time) Fifth Semester - regulation 2005) Time : Three hours maximum : 100 marks Answer ALL question PARTA-(1Ox2=2 ) 1. The memory unit of a computer has ds 0182 bits each. The computer has an instruction format with four fie operation code

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    COA - May - June 2007

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    CS 1251 COMPUTER ARCHITECTURE ANNA UNIVERSITY PREVIOUS YEAR QUESTION BANK DOWNLOAD B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2007. Sixth Semester (Regulation 2004) Electronics and Communication Engineering CS 1251 »- COMPUTER ARCHITECTURE (Common to B.E. (Part-Time) Fifth Semester - regulation 2005) Time : Three hours maximum : 100 marks Answer ALL question PARTA-(1Ox2=2 ) 1. The memory unit of a computer has ds 0182 bits each. The computer has an instruction format with four fie operation code

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    37 vues1 page

    Cs 1251 Computer Architecture Anna University Previous Year Question Bank Download

    Transféré par

    lmsrt
    CS 1251 COMPUTER ARCHITECTURE ANNA UNIVERSITY PREVIOUS YEAR QUESTION BANK DOWNLOAD B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2007. Sixth Semester (Regulation 2004) Electronics and Communication Engineering CS 1251 »- COMPUTER ARCHITECTURE (Common to B.E. (Part-Time) Fifth Semester - regulation 2005) Time : Three hours maximum : 100 marks Answer ALL question PARTA-(1Ox2=2 ) 1. The memory unit of a computer has ds 0182 bits each. The computer has an instruction format with four fie operation code

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme DOC, PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 1

    CS 1251 COMPUTER ARCHITECTURE ANNA UNIVERSITY PREVIOUS YEAR QUESTION BANK DOWNLOAD

    B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2007. Sixth Semester (Regulation 2004) Electronics and Communication Engineering CS 1251 - COMPUTER ARCHITECTURE (Common to B.E. (Part-Time) Fifth Semester - regulation 2005) Time : Three hours maximum : 100 marks Answer ALL question PARTA-(1Ox2=2 ) 1. The memory unit of a computer has ds 0182 bits each. The computer has an instruction format with four fie operation code field, a mode field to specify one of seven addressin des? register address field to specify one of 60 processor registers, and a address. Specify the instruction format and the number of bits in ea he instruction is in one memory word. 2. What is meant by the store ogram concept? Discuss. 3. Discuss the principle behind Booths multiplier. 4. What is a ripple carry adder? 5. Discuss the principle of operation of a micro programmed control unit? 6. What is the ideal speedup expected in a pipelined architecture with n stages? Justify your answer? 7. Define average Memory Access Time for a computer system with two levels of caches? 8. How you construct a 8 M >< 32 memory using 512 K X 8 memory chips? 9. what are the functions of a typical I/O interface? 10. How does the processor handle an interrupt request?

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