8bit ALU

entity alu is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
s : in std_logic_vector(2 downto 0);
y : out std_logic_vector(7 downto 0));
end alu;
architecture Behavioral of alu is
signal s1,s2 : std_logic_vector(7 downto 0);
begin
s1<="0000"&a;
s2<="0000"&b;
process(a,b,s1,s2,s)
begin
case s is
when "000"=> y<=s1+s2;
when "001"=> y<=s1-s2;
when "010"=> y<=a*b;
when "011"=> y<=not s1;
when "100"=> y<=s1 and s2;
when "101"=> y<=s1 or s2;
when "110"=> y<=s1 xor s2;
when "111"=> y<=s1 nand s2;
when others => null;
end case ;
end process;
end Behavioral;
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BCD up/down counter
entity bcd_counter is
Port ( dir : in std_logic;
res : in std_logic;
clk : in std_logic;
count : out std_logic_vector(3 downto 0));
end bcd_counter;
architecture Behavioral of bcd_counter is
signal sclk : std_logic;
signal clk1 : std_logic_vector(15 downto 0):= "0000000000000000";
begin
process (clk)
begin

if (rising_edge(clk)) then
clk1 <= clk1 + '1';
sclk <= clk1(15);
end if ;
end process;
process (sclk, dir,res)
variable t: std_logic_vector(3 downto 0):="0000";
begin
if (res='1')then t:="0000";
elsif (rising_edge(sclk) ) then
if (dir='1')then
t:=t+'1';
if (t>"1001")then t:="0000";
end if;
else t:=t-'1';
if (t>"1001")then t:="1001";
end if;
end if ;
end if ;
count <=t;
end process ;
end Behavioral;
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4 bit counter with async reset
entity counterasync_reset is
Port ( clk : in std_logic;
rst : in std_logic;
dir : in std_logic;
count : out std_logic_vector(3 downto 0));
end counterasync_reset;
architecture Behavioral of counterasync_reset is
signal sclk : std_logic;
signal clk1 : std_logic_vector(15 downto 0):= "0000000000000000";
begin
process (clk)
begin
if (rising_edge(clk)) then
clk1 <= clk1 + '1';
sclk <= clk1(15);
end if ;
end process;
process (clk1, dir,rst)
variable t: std_logic_vector(3 downto 0):="0000";
begin
if (rst='1')then t:="0000";

elsif (rising_edge(sclk) ) then

if (dir='1')then t:=t+'1';
else t:=t-'1';
end if ;
end if ;
count <=t;
end process ;
end Behavioral;
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4 bit counter with sync reset
entity countersync_rst is
Port ( clk : in std_logic;
rst : in std_logic;
dir : in std_logic;
count : out std_logic_vector(3 downto 0));
end countersync_rst;
architecture Behavioral of countersync_rst is
signal sclk : std_logic;
signal clk1 : std_logic_vector(15 downto 0):= "0000000000000000";
begin
process (clk)
begin
if (rising_edge(clk)) then
clk1 <= clk1 + '1';
sclk <= clk1(15);
end if ;
end process;
process (sclk, dir,rst)
variable t: std_logic_vector(3 downto 0):="0000";
begin
if (rising_edge(sclk))then
if (rst='1')then t:="0000";
elsif (dir='1')then t:=t+'1';
else t:=t-'1';
end if;
end if;
count<=t;
end process ;
end Behavioral;
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_
DC MOTOR

entity dc_motor is
Port ( clkin,reset,dir : in std_logic;
SC : in std_logic_vector(1 downto 0);
IN1,IN2 : out std_logic);
end dc_motor;
architecture dc_motor of dc_motor is
signal sig1,sig2,sig_in:std_logic;
signal clk1,clk2,clk3,clk4:std_logic;
signal clk_div:std_logic_vector(15 downto 0);
begin
process(clkin,reset)
begin
if(reset='1')then
clk_div<=(others=>'0');
elsif(clkin'event and clkin='1')then
clk_div<=clk_div+1;
end if;
end process;
clk1<=clk_div(3);
clk2<=clk_div(4);
clk3<=clk_div(5);
clk4<=clk_div(6);
sig1<=clk3;
sig2<=clk4;
sig_in<='1' when SC="00" else
sig2 when SC="01" else
sig1 when SC="10" else
clk2 when SC="11";
IN1<=sig_in when dir='0' else
'0';
IN2<=sig_in when dir='1' else
'0';
end dc_motor;
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1:8 DEMUX
entity demux1 is
Port ( a : in std_logic;
e : in std_logic;
s : in std_logic_vector(2 downto 0);
y : out std_logic_vector(7 downto 0));

end demux1;
architecture Behavioral of demux1 is
begin
process(a,s,e)
begin
y<="00000000";
if(e='0')then
if(s="000")then
y(0)<=a;
elsif(s="001")then
y(1)<=a;
elsif(s="010")then
y(2)<=a;
elsif(s="011")then
y(3)<=a;
elsif(s="100")then
y(4)<=a;
elsif(s="101")then
y(5)<=a;
elsif(s="110")then
y(6)<=a;
elsif(s="111")then y(7)<=a;
else y<="ZZZZZZZZ";
end if;
end if;
end process;
end Behavioral;
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_
D F/F
entity dff is
Port ( d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pr : in std_logic;
q : out std_logic;
qb : out std_logic);
end dff;
architecture Behavioral of dff is
begin
process (clk,clr,pr,d)
variable t : std_logic;
begin

if (pr='1' and clr= '0')then t:='0';

elsif (pr='0' and clr= '1')then t:='1';
elsif (pr='0' and clr= '0')then t:='Z';
elsif (pr='1' and clr= '1')then
if (rising_edge(clk)) then
case d is
when '0'=>t:='0';
when '1'=>t:='1';
when others => null;
end case;
end if ;
q<=t;
qb<=not t;
end if;
end process;
end Behavioral;
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__
encoder without priority
entity encoder3_8 is
Port ( d : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end encoder3_8;
architecture Behavioral of encoder3_8 is
begin
process (d)
begin
if (d="00000001")
y<="000";
elsif (d="00000010")
y<="001";
elsif (d="00000100")
y<="010";
elsif (d="00001000")
y<="011";
elsif (d="00010000")
y<="100";
elsif (d="00100000")
y<="101";
elsif (d="01000000")
y<="110";
elsif (d="10000000")
y<="111";

then
then
then
then
then
then
then
then

end if ;
end process

end Behavioral;
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__
FULLADDER _ STRUCTURAL
entity fa_st is
Port ( x : in std_logic;
y : in std_logic;
cin : in std_logic;
cout : out std_logic;
sum : out std_logic);
end f
a_st;
architecture Behavioral of fa_st is
component ha
port ( x,y :in std_logic ;
sum,carry : out std_logic);
end component ;
signal tmp1,tmp2,tmp3 : std_logic;
begin
L1: ha port map (x,y,tmp1,tmp2);
L2: ha port map (tmp1,cin,sum,tmp3);
cout <= tmp3 or tmp2;

end Behavioral;
//(in sub file)
entity ha is
Port ( x : in std_logic;
y : in std_logic;
sum : out std_logic;
carry : out std_logic);
end ha;
architecture Behavioral of ha is
begin

sum <= x xor y;

carry <= x and y;
end Behavioral;
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__
fulladder in dataflow
entity fadder_df is
Port ( a : in std_logic;
b : in std_logic;
ci : in std_logic;
co : out std_logic;
sum : out std_logic);
end fadder_df;
architecture dataflow of fadder_df is
signal s1,c1,c2,c3 :std_logic;
begin
s1 <= a xor b;
c1 <= a and b ;
c2 <= ci and b ;
sum <= s1 xor ci;
c3 <= c1 and a ;
co <= c3 or c2 or c1 ;
end dataflow;
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_
Fulladder in behavioral
entity fulladder is
Port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
cout : out std_logic;
sum : out std_logic);
end fulladder;
architecture Behavioral of fulladder is
begin
process(a,b,cin)
begin
sum <= a xor b xor cin;
cout <= (a and b) or (b and cin) or (cin and a)

end process;
end Behavioral;
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_
jk F/F
entity jkff is
Port ( pr : in std_logic;
clr : in std_logic;
clk : in std_logic;
jk : in std_logic_vector(1 downto 0);
q : out std_logic;
qb : out std_logic);
end jkff;
architecture Behavioral of jkff is
signal sclk : std_logic;
signal clk1 : std_logic_vector(15 downto 0):= "0000000000000000";
begin
process (clk)
begin
if (rising_edge(clk)) then
clk1 <= clk1 + '1';
sclk <= clk1(15);
end if ;
end process;
process (pr,clr,clk,jk)
variable t : std_logic;
begin
if (pr='1' and clr= '0')then t:='1';
elsif (pr='0' and clr= '1')then t:='0';
elsif (pr='0' and clr= '0')then t:='Z';
elsif (pr='1' and clr= '1')then
if rising_edge(clk) then
case jk is
when "00"=>t:=t;
when "01"=>t:='0';
when "10"=>t:='1';
when "11"=>t:=not t;
when others => null;
end case;
end if ;
q<=t;
qb<=not t;
end if;

end process;
end Behavioral;
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1:8 MUX
entity mux8_1 is
Port ( d : in std_logic_vector(7 downto 0);
s : in std_logic_vector(2 downto 0);
e : in std_logic;
y : out std_logic);
end mux8_1;
architecture Behavioral of mux8_1 is
begin
process(d,e,s)
begin
if(e='0')then
if(s="000")then
y<=d(0);
elsif(s="001")then
y<=d(1);
elsif(s="001")then
y<=d(2);
elsif(s="011")then
y<=d(3);
elsif(s="100")then
y<=d(4);
elsif(s="101")then
y<=d(5);
elsif(s="110")then
y<=d(6);
elsif(s="111")then
y<=d(7);
end if;
else
y<='Z';
end if;
end process;

end Behavioral;
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_
nbitcomparator

entity nbitcomp is
generic (N:integer := 1)
;
Port ( a : in std_logic_vector(N downto 0);
b : in std_logic_vector(N downto 0);
agrtb : out std_logic;
alessb : out std_logic;
aeqb : out std_logic);
end nbitcomp;
architecture Behavioral of nbitcomp is
begin
process(a,b)
variable g,l,e:std_logic;
begin
if (a<b)then
g:='0';
l:='1';
e:='0';
elsif (a>b)then
g:='1';
l:='0';
e:='0';
else
g:='0';
l:='0';
e:='1';
end if ;
agrtb <=g;
alessb <=l;
aeqb <=e;
end process ;
end Behavioral;
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__
priority encoder
entity priority_enc is
Port ( d : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end priority_enc;
architecture Behavioral of priority_enc is
begin
process (d)

begin
if (d(7)='1') then y<="111";
elsif(d(6)='1') then y<="110";
elsif(d(5)='1') then y<="101";
elsif(d(4)='1') then y<="100";
elsif(d(3)='1') then y<="011";
elsif(d(2)='1') then y<="010";
elsif(d(1)='1') then y<="001";
elsif(d(0)='1') then y<="000";
else y <= "ZZZ";
end if

end process;
end Behavioral;
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__
SR F/F
entity srff is
Port ( sr : in std_logic_vector(1 downto 0);
clk : in std_logic;
clr : in std_logic;
pr : in std_logic;
q : out std_logic;
qb : out std_logic);
end srff;
architecture Behavioral of srff is
signal sclk : std_logic;
signal clk1 : std_logic_vector(15 downto 0):= "0000000000000000";
begin
process (clk)
begin
if (rising_edge(clk)) then
clk1 <= clk1 + '1';
sclk <= clk1(15);
end if ;
end process;
process (sclk,clr,pr,sr)
variable t : std_logic;
begin
if (pr='1' and clr= '0')then t:='0';
elsif (pr='0' and clr= '1')then t:='1';
elsif (pr='0' and clr= '0')then t:='Z';

elsif (pr='1' and clr= '1')then

if (rising_edge(sclk)) then
case sr is
when "00"=>t:=t;
when "01"=>t:='0';
when "10"=>t:='1';
when "11"=>t:='X';
when others => null;
end case;
end if ;
q<=t;
qb<=not t;
end if;
end process;
end Behavioral;
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_
stepper motor
ntity steppermotor is
Port ( dir,reset,clk : in std_logic;
a1 : out std_logic_vector(3 downto 0));
end steppermotor;
architecture Behavioral of steppermotor is
signal clk_div :std_logic_vector(15 downto 0);
signal count:std_logic_vector(1 downto 0);
signal clk_div2:std_logic;
signal sig:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(rising_edge(clk))then
clk_div<=clk_div+1;
end if;
clk_div2<=clk_div(15);
end process;
process(clk_div2,reset,dir)
begin
if(reset='1') then
count<="00";
elsif(rising_edge(clk_div2)) then
if(dir='1') then count<=count+1;
else
count<=count-1;
end if;
end if;
end process;

process(count)
begin
if(count="00") then
sig<="0011";
elsif (count="01") then
sig<="0110";
elsif (count="10") then
sig<="1100";
elsif (count="11") then
sig<="1001";
end if;
end process;
a1<=sig;
end Behavioral;
______________________________________________________________________
_
T F/F
entity tff is
Port ( t : in std_logic;
clk : in std_logic;
clr : in std_logic;
pr : in std_logic;
q : out std_logic;
qb : out std_logic);
end tff;
architecture Behavioral of tff is
signal sclk : std_logic;
signal clk1 : std_logic_vector(15 downto 0):= "0000000000000000";
begin
process (clk)
begin
if (rising_edge(clk)) then
clk1 <= clk1 + '1';
sclk <= clk1(15);
end if ;
end process;
process (sclk)
variable t1: std_logic;
begin
if (pr='1' and clr= '0')then t1:='0';
elsif (pr='0' and clr= '1')then t1:='1';
elsif (pr='0' and clr= '0')then t1:='Z';
elsif (pr='1' and clr= '1')then
if (rising_edge (sclk)) then

case t is
when '0'=>t1:=t1;
when '1'=>t1:=not t1;
when others => null;
end case;
end if ;
q <= t1;
qb <= not t1;
end if;
end process;
end Behavioral;
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_
Decoder 2:4

entity dec24 is
Port ( i : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0));
end dec24;
architecture dec24 of dec24 is
begin
process (i)
begin
case i is
when "00" =>y<= "0001";
when "01" =>y<= "0010";
when "10" =>y<= "0100";
when "11" =>y<= "1000";
when others => NULL;
end case;
end process;
end dec24;
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elevator
entity elevator is

port(col:in std_logic_vector(3 downto 0);

row:out std_logic_vector(3 downto 0);
display:out std_logic_vector(6 downto 0);
mux:out std_logic_vector(3 downto 0);
clk:in std_logic);
end elevator;
architecture Behavioral of elevator is
signal countfloor,keyfloor,integer range 0 to 15;
signal keypress:std_logic;
signal skeyscn:std_logic_vector(3 downto 0);
signal lkeyscn,lkeyret:std_logic_vector(3 downto 0);
signal clkdiv:std_logic_vector(15 downto 0);
signal okfloor,clkkey:std_logic;
begin
process(col)
begin
case col is
when "1110"=>keypress<='1';
begin
end Behavioral;
______________________________________________________________________
__
HEX keypad
entity Hexkeypad is
Port ( col : in std_logic_vector(3 downto 0);
clk : in std_logic;
row : out std_logic_vector(3 downto 0);
display : out std_logic_vector(6 downto 0));
end Hexkeypad;
architecture hexkeypad of Hexkeypad is
signal skeyval:integer range 0 to 15;
signal keypress:std_logic;
signal skeyscn:std_logic_vector(3 downto 0);
signal lkeyscn:std_logic_vector(3 downto 0);
signal lkeyret:std_logic_vector(3 downto 0);
signal clk_div:std_logic_vector(7 downto 0);
signal clkkey:std_logic;
begin
process(clk)
begin
if(rising_edge(clk))then

clk_div<=clk_div+1;
end if;
clkkey<=clk_div(6);
end process;
process(col)
begin
case col is
when "1110"=>keypress<='1';
when "1101"=>keypress<='1';
when "1011"=>keypress<='1';
when "0111"=>keypress<='1';
when others=>keypress<='0';
end case;
end process;
process(clkkey)
begin
if(rising_edge(clkkey)) then
if (skeyscn="1110") then skeyscn<="1101";
elsif(skeyscn="1101") then skeyscn<="1011";
elsif(skeyscn="1011") then skeyscn<="0111";
elsif(skeyscn="0111") then skeyscn<="1110";
else skeyscn<="1110";
end if;
end if;
row<=skeyscn;
end process;
process(keypress)
begin
if(rising_edge(keypress)) then lkeyscn<=skeyscn;
lkeyret<=col;
end if;
end process;
process(keypress)
begin
if(rising_edge(keypress)) then
if(lkeyscn="1110" and lkeyret="1110") then skeyval<=0;
elsif(lkeyscn="1110" and lkeyret="1110") then skeyval<=0;
elsif(lkeyscn="1110" and lkeyret="1101") then skeyval<=1;
elsif(lkeyscn="1110" and lkeyret="1011") then skeyval<=2;
elsif(lkeyscn="1110" and lkeyret="0111") then skeyval<=3;
elsif(lkeyscn="1101" and lkeyret="1110") then skeyval<=4;
elsif(lkeyscn="1101" and lkeyret="1101") then skeyval<=5;
elsif(lkeyscn="1101" and lkeyret="1011") then skeyval<=6;
elsif(lkeyscn="1101" and lkeyret="0111") then skeyval<=7;
elsif(lkeyscn="1011" and lkeyret="1110") then skeyval<=8;
elsif(lkeyscn="1011" and lkeyret="1101") then skeyval<=9;
elsif(lkeyscn="1011" and lkeyret="1011") then skeyval<=10;
elsif(lkeyscn="1011" and lkeyret="0111") then skeyval<=11;
elsif(lkeyscn="0111" and lkeyret="1110") then skeyval<=12;
elsif(lkeyscn="0111" and lkeyret="1101") then skeyval<=13;
elsif(lkeyscn="0111" and lkeyret="1011") then skeyval<=14;

elsif(lkeyscn="0111" and lkeyret="0111") then skeyval<=15;

end if;
end if;
end process;
process(skeyval)
type tseg7 is array(0 to 15) of std_logic_vector(6 downto 0);
constant segval:tseg7:=("0111111","0000110","1011011","1001111",
"1100110","1101101","1111101","0000111",
"1111111","1101111","1110111","1111100",
"1011000","1011110","1111001","1110001");
begin
display<=segval(skeyval);
end process;
end hexkeypad;